The TELEFUNKEN CHASSIS 415A1 is a semi modular chassis type.
The basis of the TELEFUNKEN CHASSIS 615A1 is coming from
TELEFUNKEN CHASSIS 714A From 1980 .
Obviously the
TELEFUNKEN CHASSIS 714A is higly different !
This type of chassis was fitted from 15 to 21 Inches screen formats !
When dismounted from the wooden cabinet it's a FLEXY monocarrier Chassis (Not a Flexy Girl Which is another thing !) ; since it has no metal bars soldered along his perimeter it's very wobbling.
This chassis was very reliable and durable but was suffering from a high rate of dry joint.
It runs very cold.
TDA1940 - SYNCHRONIZATION
Line Circuits for TV Receivers (18-Pin Plastic Package)
These integrated circuits are advanced versions of the well-known types TDA1940, TDA1940F, TDA1950 and TDA1950F are identical
TBA940/950,
TDA9400/9500 etc. integrated line oscillator circuits. except the
following: at pin 2 the types having the suffix "F" supply ,
They
comprise all stages for sync separation and line synchronisation
horizontal output pulses of longer duration compared with the basic I
in
TV receivers in one single silicon chip. Due to their high degree
of types Integration, the number of external components is very
small.
This integrated circuit contains the horizontal sweep
generator (HO), the amplitude filter (AS), the sync-signal
separating circuit (SA) and the frequency/phase comparator (FP). For
the purpose of suppressing noise pulses which are caused via the
operating voltage during the upper and the lower inversion point of
the horizontal sweep generator (HO) which contains a single
capacitor (C) and a first threshold stage circuit (SS1) with two
fixed thresholds, there are provided a second and a third threshold
stage circuit (SS2, SS3), to the inputs of which the sawtooth signal
is applied, and with the thresholds thereof, approximately 2 μs
prior to reaching the upper or the lower peak value of the sawtooth
signal, are being passed through thereby. The output signal of the
second threshold circuit (SS2) and the output signal of the third
threshold stage circuit (SS3) which is applied via the pulse shaper
circuit (IF), are superimposed linearly and, via the stopper circuit
(blocking stage) (SP) serve to control the application of the
composite video signal (BAS) to the amplitude filter (AS), or else they
are applied to a clamping circuit which serves to apply the
operating points of the amplitude filter (AS) and/or of the
sync-signal separating circuit (SA) to such a potential that these
two stages, for the time duration of these output pulses, are
prevented from operating.
1. An integrated circuit for color
television receivers, comprising a voltage- or current-controlled
horizontal sweep generator (HO), an amplitude filter (AS), a
synchronizing-signal separating circuit (SA) and a frequency/phase
comparator (FP) which serves to synchronize the horizontal sweep
generator (HO), with said generator being a sawtooth generator
containing a single capacitor
(C) and a first threshold stage circuit (SS1) having two fixed thresholds, said integrated circuit further comprising:
a
second and a third threshold stage circuit (SS2, SS3) each being
supplied with the sawtooth signal on the input side, comprising each
time one threshold which, approximately 2μs prior to the reaching of
the upper or the lower peak value of the sawtooth signal, is being
passed thereby;
a pulse shaper circuit (IF) coupled to the
output of said third threshold stage circuit (SS3) which pulse shaper
circuit reduces the duration of the output pulse thereof to about
the duration of the output pulse of said second threshold stage
circuit (SS2), and
a stopper circuit (blocking stage) (SP)
coupled to the outputs of both said pulse shaper circuit (IF) and
said second threshold stage circuit (SS2), said stopper circuit
having a signal input to which there is applied a composite video
signal (BAS) and a signal output which is coupled to the input of
said amplitude filter (AS).
2. The
invention of claim 1 wherein the outputs of both said pulse shaper
circuit (IF) and said second threshold stage circuit (SS2) are
coupled to a clamping circuit which applies the operating points of
said amplitude filter (AS) and said sync-separating signal (SA) to
such a potential that they are prevented from operating.
3. An integrated horizontal sweep circuit comprising:
a generator for generating a sawtooth signal;
an amplitude filter having an input for receiving a composite video signal and having an output;
a sync-signal separating circuit having an input coupled to said amplitude filter output and having an output;
a frequency/phase comparator having a first input coupled to said separating circuit output,
a second input receiving said sawtooth signal and an output for controlling said generator; and
a
control circuit responsive to said sawtooth signal for inhibiting
said composite video signal when said sawtooth signal is within
predetermined signal level ranges about the upper and lower inversion
points of said sawtooth signal.
4. An integrated circuit in accordance with claim 3 wherein:
said
generator comprises a capacitor, circuit means for charging and
discharging said capacitor, and a first threshold circuit controlling
said circuit means in response to said sawtooth signal reaching a
first level corresponding to said first inversion point and a second
level corresponding to said second inversion point.
5. An integrated horizontal sweep circuit comprising:
a sawtooth signal generator;
an amplitude filter having an input receiving a composite video signal and having an output;
a sync-signal separating circuit having an input coupled to said amplitude filter output and having an output;
a
frequency/phase comparator having a first input coupled to said
separating circuit output, a second input receiving said sawtooth
signal and an output for controlling said generator; and
a
control circuit responsive to said sawtooth signal for inhibiting
operation of said amplitude filter and/or said sync-signal separating
circuit when said sawtooth signal is within predetermined signal
level ranges about the upper and lower inversion point of said
sawtooth signal.
6. An integrated circuit in accordance with claim 5 wherein:
said
generator comprises a capacitor, circuit means for charging and
discharging said capacitor and a first threshold circuit controlling
said circuit means in response to said sawtooth signal reaching a
first level corresponding to said first inversion point and a second
level corresponding to said second inversion point.
Description:
BACKGROUND OF THE INVENTION
The
invention relates to an integrated circuit for (color) television
receivers, comprising a voltage- or current-controlled
horizontal-sweep generator, an amplitude filter, a synchronizing
signal separating circuit (sync-separator) and a frequency/phase
comparator which serves to synchronize the horizontal sweep
generator which is a sawtooth generator consisting of a single
capacitor and of a first threshold stage having two fixed switching
thresholds, cf. preamble of the patent claim. Such types of
integrated circuits, for example, are known from the technical
journal "Elektronik aktuell", 1976, No. 2, pp. 7 to 14 where they are
referred to as TDA 9400 and TDA 9500.
Especially on account
of the fact that the amplitude filter as well as the horizontal
sweep generator in the form of the aforementioned sawtooth
generator, are integrated on a single semiconductor body, it is likely
that noise interference pulses coming from the individual stages,
and via the supply voltage line, may have a disturbing influence upon
the horizontal sweep generator, i.e. upon the threshold stage
thereof, in such a way that either the lower or the upper or
successively both switching thresholds are exceeded before the time
by the voltage at the capacitor, owing to the noise superposition, so
that the generator will show to have a "wrong" frequency or phase
position. This frequency/phase variation, of course, is compensated
for by the circuit, with the aid of the synchronzing pulses, but only
in such a way that the noise effect remains visible in the
television picture.
SUMMARY OF THE INVENTION
The
invention is characterized in the claim is aimed at overcoming this
drawback by solving the problem of designing an integrated circuit of
the type described in greater detail hereinbefore, in such a way that
noise pulses acting upon the capacitor voltage or the internal
reference voltages for the switching thresholds (see below) in the
proximity of the two switching thresholds, are prevented from having
the described disadvantageous effect. Accordingly, an advantage of
the invention results directly from solving the given problem.
Other
objects, features and advantages of the present invention will
become more fully apparent from the following detailed description of
the preferred embodiment, the appended claims and the accompanying
drawing in which:
BRIEF DESCRIPTION OF THE INVENTION
The
invention will now be described in greater detail with reference to
the accompanying drawing. This drawing, in the form of a
schematical circuit diagram, shows the construction of an integrated
circuit according to the invention.
DETAILED DESCRIPTION OF THE INVENTION
T
he
horizontal sweep generator HO comprises the capacitor C as
connected to the zero point of the circuit, and which is charged and
discharged via the two shown constant current sources CS1 and CS2,
thus causing the intended sawtooth voltage to appear thereat.
Moreover, the horizontal sweep generator HO comprises the first
threshold stage circuit SS1, having an upper and a lower threshold.
As soon as the capacitor voltage exceeds one of the thresholds, the
first threshold stage circuit SS1 switches over to the other
threshold. The two thresholds are defined by the voltage divider P as
connected to the operating voltage U, and in which the
corresponding threshold inputs are connected to corresponding
tapping points. The output of the threshold stage circuit SS1
controls the electronic switch S, so that the constant current
source CS2 as connected thereto, is either disconnected from or
connected to the zero point of the circuit. Accordingly, in the
disconnected state, the capacitor C is charged via the constant
current source CS1 arranged in series therewith while in the
connected state the capacitor C is discharged across the
aforementioned constant current source CS2 arranged in parallel
therewith, if, as a matter of fact, the current of the constant
current source CS1 arranged in series with the capacitor C, is
smaller than that of the parallel-arranged constant current source
CS2.
Now, for the purpose of avoiding the aforementioned
drawbacks, there is provided a second and a third threshold stage
circuit SS2 and SS3, respectively, as well as the pulse shaper circuit
IF. To the respective input of the two threshold stage circuits
SS2, SS3, there is applied the capacitor voltage, in the form of the
sawtooth signal, and these stages have a threshold voltage which,
approximately 2 μs prior to the reaching of the upper or the lower
peak value of the sawtooth voltage, is being passed thereby. This
means to imply that the threshold voltage of the second threshold
stage circuit SS2 is somewhat lower than the voltage of the upper
threshold of the first threshold stage circuit SS1, and that the
threshold voltage of the third threshold stage circuit SS3 is
somewhat higher than the voltage of the lower threshold of the first
threshold stage circuit SS1. The two thresholds of the threshold
stage circuits SS2, SS3 can thus be realized in a simple way by
providing further tapping points at the voltage divider P, as is
shown in the accompanying drawing. Thus, the second threshold stage
circuit SS2 is provided for at a voltage divider tapping point below
the tapping point chosen for the upper threshold, and the tapping
point for the third threshold stage circuit SS3 is provided for above
the tapping point which has been chosen for the lower threshold of
the first threshold stage circuit SS1.
Since, within the
area of the lower inversion point of the sawtooth signal there
results an excessively wide output pulse of the third threshold stage
circuit SS3, the pulse shaper circuit IF is arranged subsequently
thereto, for reducing the duration of the output pulse as applied to
its input, to about the duration of the output pulse of the second
threshold stage circuit SS2. This pulse shaper circuit IF, for
example, may be realized by a monoflop, in parti
cular by a digital
monoflop (=monostable circuit).
The output pulses of the
second threshold stage circuit SS2 and of the pulse shaper circuit IF
are then super-positioned linearly, with this being denoted in the
drawing by a simple interconnection of the two respective lines. The
combined signal is applied to the input of the stopper circuit
(blocking stage) SP, to the signal input of which there is fed the
composite video signal BAS, and the output thereof controls both the
amplitude filter AS and the synchronizing signal separating circuit
SA.
The combined signal may also be used to control a
clamping circuit applying the operating points of the amplitude filter
AS and/or of the sync-signal-separating circuit SA to such a
potential which prevents it from operating.
If now the
sawtooth signal reaches the range of its upper or its lower inversion
point, the composite video signal BAS is not applied to either the
amplitude filter AS or the sync-signal separating circuit SA, so that
shortly before and shortly after the inversion points, signals are
prevented from being processed in the two stages AS, SA. This, in
turn, has the consequence that during these times noise pulses are
prevented from superimposing upon the operating voltage U, so that
there is also prevented an unintended triggering of the first
threshold stage circuit SS1.
Moreover, it is still shown in
the drawing that the amplitude filter AS, the sync-signal separating
circuit SA and the frequency/phase comparator FP are arranged in
series in terms of signal flow, with the latter, in addition,
receiving the sawtooth signal, and with the output signal thereof
acting upon the two current sources in a regulating sense. In the
drawing, this is indicated by the setting arrows at the two current
sources.
While the present invention has been disclosed in
connection with the preferred embodiment thereof, it should be
understood that there may be other embodiments which fall within the
spirit and scope of the invention as defined by the following
claims.
TDA1870 - FRAME DEFLECTION
Form/Case/Outline: Multiwatt-15 (TDA1870A);
Type/Application: TV Vertical Deflection Unit.
Daten/electr.data: Vs max: 35 V; I15: 100 mA; Ptot: 30 W; Tmax j: 150 °C.
Varianten: TDA1670[A], TDA1675[A], TDA1872[A] -
TELEFUNKEN CHASSIS 415A (AT349354097) Switching power supply, especially for a T.V. receiving apparatus:
1. Switch mode power supply means, especially for a television receiver,
having a working winding (5), a switching transistor (6), a
back-coupling winding (7) and a control switch (11) on the primary side
of a divided transformer (1), and also having rectifiers (15, 16, 20)
for the production of the drive voltages (U1, U2, U3) on the secondary
side of the transformer (1), characterized by the following features :
(a) Connected to a winding (19) there is a thyristor (24) which is poled
in the permitted direction for the voltage at the winding (19) arising
during the current conducting phase of the switching transistor (6). (b)
One of the drive voltages (U2) is applied to the control electrode of
the thyristor (24) with such magnitude that the thyristor (24) remains
blocked in the normal working state and fires on the occurrence of an
inadmissible rise of the drive voltage (U3).
TELEFUNKEN PALCOLOR CHASSIS 415A Schaltnetzteil
(AT 349354097), IN GERMAN:
1. Schaltnetzteil,
insbesondere f·ur einen Fernsehempf·anger, mit einer Arbeitswicklung
(5), einem Schalttransistor (6), einer R·uckkopplungswicklung (7) und
einer Regelschaltung (ii) auf der Prim·arseite sowie mit Gleichrichtern
(15,16, 20) zur Erzeugung von Betriebsspannungen (U11U2#U3) auf der
Sekund·arseite eines Trenntransformators (1) gekenn zeichnet durch
folgende Merkmale: a) An eine Wicklung (19) ist ein Thyristor (24)
angeschlos sen, der f·ur die w·ahrend der siromf·uhrenden Phase der
Schalttransistoren (6) an der Wicklung (19) auftreten de Spannung in
Durchlassrichtung gepolt ist. b) An die Steuerelektrode des Thyristors
(24) ist eine der Betriebsspannungen (U2) in solcher H·ohe angelegt,
dass der Thyristor (24) im Normalbetrieb gesperrt bleibt und bei einem
unzul·assigen Anstieg der Betriebs spannung (U3) z·undet.
2. Netzteil nach Anspruch 1, dadurch gekennzeichnet,
dass die Betriebsspannung (U3) ·uber einen Spannungsteiler (25,26) an
die Steuerelektrode des Thyristors (24) angelegt ist.
3. Netzteil nach Anspruch 1, dadurch gekennzeichnet,
dass die Wicklung (19) eine Sekund·arwicklung des Trenntransforma tors
(1) ist.
Description:
Schaltnetzteil, insbesondere f·ur einen Fernsehempf·anger
Bei
Ger·aten der Nachrichtentechnik wie z.B. einem Fernsehempf·anger ist es
bekannt, die f·ur die einzelnen Stufen notwendigen Betriebsspannungen
mit einem Schaltnetzteil aus der Netzspannung zu erzeugen (Funkschau
1975, Heft 5, Seite 40-43). Ein Schaltnetzteil erm·oglicht die f·ur den
Anschluss ·ausserer Ger·ate und f·ur die Massnahmen zur Schutzisolierung
vorteilhafte galvanische Trennung der Empf·angerschaltung vom Netz. Da
ein Schaltnetzteil mit einer gegen·uber der Netzfrequenz hohen Frequenz
von ca. 30 kHz arbeitet, kann der zur galvanischen Trennung dienende
Trenntransformator gegen·uber einem Netztrafo f·ur 50 Hz wesentlich
kleiner und leichter ausgebildet sein. Durch mehrere Wicklungen oder
Wicklungsabgriffe und angeschlossene Gleichrichter k·onnen auf der
Sekund·arseite des Trenntransformators Betriebs~ spannungen
unterschiedlicher Gr·osse und Polarit·at erzeugt werden.
Ein
solches Schaltnetzteil enth·alt eine Regelschaltung zur Stabilisierung
der Amplitude der auf der Sekund·arseite erzeugten Betriebsspannungen.
In dieser Regelschaltung wird eine durch Gleichrichtung der
Impulsspannung am Trafo gewonnene Stellgr·osse erzeugt und mit einer
Bezugsspannung verglichen. In Abh·angigkeit von der Abweichung wird der
Schaltzeitpunkt des auf der Prim·arseite vorgesehenen elektronischen
Schalters so gesteuert, dass die Amplitude der erzeugten
Betriebsspannungen konstant bleibt.
Bei einem solchen
Schaltnetzteil kann die genannte Regelschaltung z.B. durch ein
fehlerhaftes Bauteil ausfallen. Die Regelung der Amplitude der erzeugten
Betriebsspannungen ist dann unkontrolliert. Die Betriebsspannungen
k·onnen dann auf den doppelten oder dreifachen Wert ansteigen. Dadurch
besteht die Gefahr, dass das Schaltnetzteil oder die an die
Betriebsspannungen angeschlossenen Verbraucher wie z.B. der Heizfaden
der Bildr·ohre oder der Zeilenendstufentransistor zerst·ort werden. Der
Anstieg der Betriebsspannungen kann dar·uberhinaus einen Anstieg der im
Fernsehempf·anger erzeugten Hochspannung und dadurch eine
R·ontgenstrahlung ausl·osen.
Es ist auch ein Schaltnetzteil
bekannt (DE-OS 27 27 332), bei dem zum Schutz gegen einen zu starken
Anstieg der erzeugten Betriebsspannungen aus der Impulsspannung an der
Prim·arseite des Trafos eine Stellgr·osse gewonnen wird, die beim
·Uberschreiten eines Schwellwertes den R·uckkopplungsweg unwirksam
steuert. Durch die Unterbrechung des R·uckkopplungsweges kann das
Schaltnetzteil nicht mehr schwingen, so dass in erw·unschter Weise auch
keine Betriebsspannungen mehr erzeugt werden. Diese Schaltung erfordert
jedoch eine Vielzahl von Bauteilen und ist daher relativ teuer.
Der
Erfindung liegt die Aufgabe zugrunde, eine sicher wirkende
Schutzschaltung mit verringertem Schaltungsaufwand gegen
die oben
beschriebenen Gefahren zu schaffen.
Diese Aufgabe wird durch die
im Anspruch 1 beschriebene Erfindung gel·ost. Vorteilhafte
Weiterbildungen der Erfindung sind in den Unteranspr·uchen beschrieben.
Die
Erfindung beruht auf folgender ·Uberlegung: Der Schalttransistor auf
der Prim·arseite wird von der prim·arseitigen R·uckkopplungswicklung
w·ahrend seiner stromleitenden Phase mit einem Basisstrom angesteuert.
Wenn jetzt eine Sekund·arwicklung w·ahrend dieser stromleitenden Phase
stark belastet, z.B. ·uber den Thyristor kurzgeschlossen wird, bricht
auch die Spannung an der prim·arseitigen R·uckkopplungswicklung
zusammen. Diese Wicklung kann dann f·ur den Schalttransistor nicht mehr
einen f·ur den leitenden Betrieb ausreichenden Basis strom liefern. Das
Schaltnetzteil schwingt dann nicht mehr, so dass die sekund·arseitigen
Betriebsspannungen in erw·unschter Weise zusammenbrechen. Der
schaltungstechni- sche Aufwand ist gering. Er besteht vorzugsweise aus
einem Thyristor und zwei Widerst·anden.
Ein Ausf·uhrungsbeispiel
der Erfindung wird anhand der Zeichnung erl·autert. Darin zeigen Figur 1
ein erfindungsgem·ass ausgebildetes Schaltnetzteil und Figur 2 Kurven
zur Erl·auterung der Wirkungsweise. Dabei zeigen die kleinen Buchstaben,
an welchen Punkten in Figur 1 die Spannungen gem·ass Figur 2 stehen.
Das
Schaltnetzteil gem·ass Figur 1 enth·alt auf der Prim·arseite des
Trenntransformators 1 den Netzgleichrichter 2, den Ladekondensator 3,
den Strom-Messwiderstand 4, die Prim·arwicklung 5 den Schalttransistor
6, die zur Schwingungserzeugung dienende R·uckkopplungswicklung 7, den
zur Steuerung des Schalttransistors 6 dienenden Thyristor 8, die
Regelwicklung 9, den zur Erzeugung der Regelspannung dienenden
Gleichrichter 10 sowie die zur Stabilisierung der Betriebsspannungen
dienende Regelschaltung 11 mit dem Transistor 12 und der eine
Referenzspannung lieferndenZenerdiode 13. Die Sekund·arwicklung 14
liefert ·uber den Gleichrichter 15 eine erste Betriebsspannung U1 von
150 V. Ein Abgriff der Wicklung 14 liefert ·uber den Gleichrichter 16
eine zweite Betriebsspannung U2 von 12 V f·ur einen
Fernbedienungsempf·anger.
Eine weitere Sekund·arwicklung 19
liefert ·uber den Gleichrichter 20 eine dritte Betriebsspannung U3 von
12 V. Die Polung der Wicklungen 14,19 und der Gleichrichter 15,16,20 ist
derart, dass die Gleichrichter 15,16,20 w·ahrend der Sperrphase des
Schalttransistors 6 durch die sekund·arseitig auftretenden
Impulsspannungen leitend gesteuert sind und die angeschlossenen
Ladekondensatoren aufladen.
An das untere Ende der Wicklung 19 ist
zus·atzlich der Thyristor 24 angeschlossen. An die Steuerelektrode b
des Thyristors 24 ist die Betriebs spannung U2 ·uber den Spannungsteiler
25,26 angelegt.
Die Wirkungsweise der Schaltung wird anhand der
Figur 2 erl·autert. Es sei angenommen, dass das Schaltnetzteil im
Zeitpunkt tl in Betrieb genommen wird. Mit der Diode 21 wird aus der
Netzspannung am Punkt d ein positiver Impuls erzeugt. Dieser gelangt
·uber den Kondensator 23 auf die Basis des Schalttransistors 6 und
steuert diesen leitend. Dadurch beginnt das Schaltnetzteil zu schwingen,
wobei die Schwingung durch die R·uckk
opplungswicklung 7
aufrechterhalten wird. Am Punkt a entsteht dann eine m·aanderf·ormige
Wechselspannung mit einer Frequenz von etwa 25-30 kHz.
Die
daraufhin in den Sekund·arwicklungen 14,19 erzeugten Impulse erzeugen in
der beschriebenen Weise die Betriebsspannungen U1,U2,U3. Der
Spannungsteiler 25,26 ist so bemessen, dass der Thyristor 24 gesperrt
bleibt, d.h. die Spannung am Punkt 6 jst kleiner als 0,7 V. Der
Thyristor 24 hat dann keine Wirkung. Dir Amplitude der Spannungen
Ui,U2,U3 wird ·uber die Regelschaltung 11 stabilisiert.
Es sei
jetzt angenommen, dass durch einen Fehler in der Regelschaltung 11, z.B.
durch Ausfall eines Bauteiles, die Regelung zur Stabilisierung der
Betriebsspannungen U1,U2,U3 nicht mehr wirkt und diese
Betriebsspannungen stark ansteigen. Dadurch steigt auch die Spannung am
Punkt b an.
Im Zeitpunkt t2 erreicht diese Spannung den Wert von
0,7 V, so dass der Thyristor 24 z·undet. Der untere Teil der Wicklung 19
ist jetzt praktisch kurzgeschlossen. Das Netzteil ist dadurch
sekund·arseitig so stark belastet, dass die R·uck kopplungswicklung 7
keinen ausreichenden Basisstrom zur Steuerung des Schalttransistors 6 in
seine stromleitende Phase mehr liefert. Im Zeitpunkt t2 bricht die
Schwingung des Schaltnetzteiles ab, so dass auch die Wechselspannung am
Punkt a auf null abf·allt. Den Ladekondensatoren der Gleichrichter
15,16,20 wird kein Strom mehr zugef·uhrt, so dass die Betriebspannungen
U1,U2,U3 nicht weiter ansteigen k·onnen, sondern entsprechend den
wirksamen Entladezeitkonstanten abfallen. Das Schaltnetzteil w·urde auf
diese Weise an sich beliebig lange ausgeschaltet bleiben.
Im
Zeitpunkt t3 erscheint am Punkt b der n·achste aus der Netzspannung
gewonnene Startimpuls, der den Schalttransistor 6 wieder leitend
steuert, so dass die Wechselspannung am Punkt a wieder auftritt. Das
Schaltnetzteil geht also in einen getakteten Betrieb ·uber, bei dem die
·ubertragene Leistung entsprechend dem Zeitverh·altnis zwischen
Einschaltphase und Ausschaltphase der Spannung am Punkt a betr·achtlich
verringert ist. Die Betriebsspannungen U11U2,U3 k·onnen nicht mehr
unzul·assig hohe Werte annehmen.
TELEFUNKEN PALCOLOR 2228 CHASSIS 415A UNITS VIEW:
TUNER 737694 AT349357054
With prescaler U665B
ELKO UNIT - BS1451 ET309378047
ST-BY SUPPLY - BS613 ET309309977
PLL SYNTHESIZER TUNING CONTROL BS656 AT349354169
with U3870 -Bit Microcontroller-Microcomputer - Plus 70 instruction set & binary timer
Vishay Telefunken
8-Bit Microcontrollers,Timers
Clock Frequency - Max. (Hz)=4.0M
Clock Frequency - Min. (Hz)=2.0M
Min Instruction Length (bits)=8
Max Instruction Length (bits)=24
Memory Addressing Range=64k
Number of Addressing Modes=5
On-Chip RAM (Bytes)=0
On-Chip ROM (bytes)=1.0k
Number of Interrupt Lines=1
No. of Non-Maskable Interrupts=0
Number of Maskable Interrupts=1
Number of I/O Lines=32
No. of I/O Ports=4
Vsup Nom.(V) Supply Voltage=5.0
Package=DIP
Pins=40
Military=N
Technology=NMOS
+ U3060 + ER1450 EAROM
VIDEO AT349354181
With TDA3562A
The TDA3562A is a monolithic IC designed as
decode PAL and/or NTSC colour television standards
and it combines all functions required for the
identification and demodulation of PAL and NTSC
signals.
.CHROMINANCE SIGNALPROCESSOR
.LUMINANCE SIGNAL PROCESSING WITH
CLAMPING
.HORIZONTAL AND VERTICAL BLANKING
.LINEAR TRANSMISSION OF INSERTED
RGB SIGNALS
.LINEAR CONTRAST AND BRIGHTNESS
CONTROL ACTING ON INSERTED AND MATRIXED
SIGNALS
.AUTOMATIC CUT-OFF CONTROL
.NTSC HUE CONTROL.
THE PHILIPS TDA3562A Circuit arrangement for the control of a picture tube :
1. Circuit arrangement for the control of at least one beam current in a picture tube by a picture comprising
a control loop which in one sampling interval obtains a measuring
signal from the value of the beam current on the occurrence of a given
reference level in the picture signal, stores a control signal derived
therefrom until the next sampling interval and thereby adjusts the beam
current to a value preset by a reference signal.
and a trigger
circuit which suppresses auxiliary pulses used to generate the beam
current after the picture tube has been started up and issues a
switching signal for the purpose of closing the control loop during the
sampling intervals and for releasing the control of the beam current by
the picture signal after the measuring signal has exceeded the threshold
value,
a change detection arrangement which delivers a change
signal when the stored signal has assumed a largely constant value, and
a logic network which does not release the control of the beam current
by the picture signal outside the sampling intervals until the change
signal has also been issued after the switching signal.
2. Circuit arrangement as set forth in claim 1, in
which the picture signal comprises several color signals for the control
of a corresponding number of beam currents for the display of a color
picture in the picture tube and the control loop stores a part measuring
signal or a part control signal derived therefrom for each color
signal, characterized in that the change detection arrangement includes a
change detector for each color signal which delivers a part change
signal when the relevant stored signal has assumed a largely constant
value, and the logic network does not release the control of the beam
currents by the color signals outside the sampling intervals until the
part change signals have been delivered by all change detectors.
3. Circuit arrangement as set forth in claim 1,
including a comparator arrangement which compares the measuring signal
with the reference signal and derives the control signal from this
comparison, characterized in that the change detection arrangement
detects a change in the control signal with respect to time and issues
the change signal when the control signal has assumed a largely constant
value.
4. Circuit arrangement as set forth in claims 1, 2, 3
including a control signal memory which contains at least one
capacitor, characterized in that the change detection arrangement
delivers the change signal when a charge-reversing current of the
capacitor occuring during the starting up of the picture tube falls
below a limit value.
5. Circuit arrangement as set forth in claim 2,
including a comparator arrangement which compares the measuring signal
with the reference signal and derives the control signal from this
comparison, characterized in that the change detection arrangement
detects a change in the control signal with respect to time and issues
the change signal when the control signal has assumed a largely constant
value.
Description:
BACKGROUND OF THE INVENTION
The invention
relates to a circuit arrangement for the control of at least one beam
current in a picture tube by a picture signal with a control loop which
in one sampling interval obtains a measuring signal from the value of
the beam current on the occurrence of a given reference level in the
picture signal, stores a control signal derived therefrom until the next
sampling interval and by this means adjusts the beam current to a value
preset by a reference signal, and with a trigger circuit which
suppresses auxiliary pulses used to generate the beam current after the
picture tube is turned on and issues a switching signal for the purpose
of closing the control loop during the sampling intervals and releasing
the control of the beam current by the picture signal after the
measuring signal has exceeded a threshold value.
Such a circuit
arrangement has been described in Valvo Technische Information 820705
with regard to the integrated color decoder circuit PHILIPS TDA3562A and is
used in this as a so-called cut-off point control. In the known circuit
arrangement, such a cut-off point control provides automatic
compensation of the so-called cut-off point of the picture tube, i.e. it
regulates the beam current in the picture tube in such a way that for a
given reference level in the picture signal the beam current has a
constant value despite tolerances and changes with time (aging, thermal
modifications) in the picture tube and the circuit arrangement, thereby
ensuring correct picture reproduction.
Such a blocking point
control is particularly advantageous for the operation of a picture tube
for the display of color pictures because in this case there are
several beam currents for different color components of the color
picture which have to be in a fixed ratio with one another. If this
ratio changes, for example, as the result of manufacturing tolerances or
ageing processes, distortions of the colors occur in the reproduction
of the color picture. The beam currents, therefore, have to be very
accurately balanced. The said cut-off point control prevents expensive
adjustment and maintenance time which is otherwise necessary.
Conventional
picutre tubes are constructe
d as cathode-ray tubes with hot cathodes
which require a certain time after being turned on for the hot cathodes
to heat up. Not until a final operating temperature has been reached do
these hot cathodes emit the desired beam currents to the full extent,
while gradually rising beam currents occur in the time interval when the
hot cathodes are heating up. The instantaneous values of these beam
currents depend on the instantaneous temperatures of the hot cathodes
and on the accelerating voltages for the picture tube which build up
simultaneously with the heating process and are undefined until the end
of the heating time. After the picture tube is turned on, these values
initially produce a highly distorted picture until the beam currents
have attained their final value. These picture distortions after the
picture tube is turned on are even further intensified by the fact that
the cut-off point control is not yet adjusted to the beam currents which
flow after the heating time is over.
For the purpose of
suppressing distorted pictures during the heating time of the hot
cathodes, the known circuit arrangement has a turn-on delay element
operating as a trigger circuit which, in essence, contains a bistable
flip-flop. When the picture tube and the circuit arrangement controlling
the beam currents flowing in it are turned on, the flip-flop is
switched into a first state in which it interrupts the supply of the
picture signal to the picture tube. Thus, during the heating time the
beam currents are suppressed, and the picture tube does not yet display
any picture. In sampling intervals which are provided subsequent to
flybacks of the cathode beam into an initial position on the changeover
from the display of one picture to the display of a subsequent picture
and even within the changeover, that is outside the display of pictures,
the picture tube is controlled for a short time in such a way that beam
currents occur when the hot cathodes are sufficiently heated up and an
accelerating voltage is resent. If these currents exceed a certain
threshold value, the flip-flop circuit switches into a second state and
releases the picture signal for the control of the beam currents and the
cut-off point control.
It is found, however, that the picture
displayed in the picture tube immediately after the switching over of
the flip-flop is still not fault-free. Because, in fact, the beam
currents are supported during the heating time of the hot cathodes, the
cut-off point co
ntrol cannot respond yet. This response of the cut-off
point control takes place only after the beam currents are switched on,
i.e. after the flip-flop is switched into the second state and therefore
at a time in which the picture signal already controls the beam
currents. In this way the response of the blocking point control makes
its presence felt in the picture displayed.
With the known
circuit arrangement the brightness of the picture gradually increases,
during the response of the cut-off point control, from black to the
final value.
This slow increase in the picture brightness after
the tube is turned on is disturbing to the eyes of the viewer not only
in the case of the black-and-white picture tubes with one hot cathode,
but especially so in the case of colour picture tubes which usually have
three hot cathodes. With a color picture tube, color purity errors can
also occur in addition to the change in the picture brightness if, as a
result of different speeds of response of the cut-off point control for
the three beam currents, there are found to be intermittent variations
from the interrelation between the beam currents required for a correct
picture reproduction.
SUMMARY OF THE INVENTION
The
aim of the invention is to create a circuit arrangement which
suppresses the above-described disturbances of brightness and color of
the displayed picture when the picture tube is being started.
The
invention achieves this aim in that a circuit arrangement of the type
mentioned in the preamble contains a change detection arrangement which
emits a change signal when the stored signal has assumed an essentially
constant value, and a logic network which does not release the control
of the beam current by the picture signal until the change signal has
also been emitted after the switching signal.
In the circuit
arrangement according to the invention, therefore, the display of the
picture is suppressed after the picture tube is turned on until the
cut-off point control has responded. If the picture signal then starts
to control the beam current, a perfect picture is displayed immediately.
In this way, all the disturbances of the picture which affect the
viewer's pleasure are suppressed. The circuit arrangement of the
invention is of simple design and can be combined on one semiconductor
wafer with the existing picture signal processing circuits and also, for
example, with the known circuit arrangement for cut-off point control.
Such an integrated circuit arrangement not only requires very little
space on the semiconductor wafer, but also needs no additional external
leads. Thus the circuit arrangement of the invention can be arranged,
for example, in an integrated circuit which has precisely the same
external connections as known integrated circuits. This means that an
integrated circuit containing the circuit arrangement of the invention
can be directly incorporated in existing equipment without the need for
additional measures.
In one embodiment of the said circuit
arrangement, in which the picture signal contains several color signals
for the control of a corresponding number of beam currents for
representing a color picture in the picture tube and, for each color
signal, the control loop stores a part measuring signal or a part
control signal derived from it, the change detection arrangement
contains a change detector for each color signal which emits a part
change signal when the relevant stored signal has assumed an essentially
constant value, and the logic network does not release the control of
the beam currents by the color signals outside the sampling intervals
until
the part change signals have been emitted from all change
detectors.
In principle, therefore, such a circuit arrangement
has three cut-off point controls for the three beam currents controlled
by the individual color signals. To reduce the cost of the circuitry,
the measuring stage is common to all the cut-off point controls, as in
the known circuit arrangement. All three beam currents are then measured
successively by this measuring stage. In this way, a part measuring
signal or a part control signal derived from it is obtained for each
beam current and is stored sesparately according to which of the beam
currents it belongs. Changes in the part measuring signal or part
control signal are detected for each beam current by one of the change
detectors each time. Each of these change detectors issues a part change
signal to the logic network. The latter does not release the control of
the beam currents by the picture signal outside the sampling intervals
until all the part change signals indicate that the part measuring
signal or the part control signal, as the case may be, remains constant.
This ensures that the cut-off point controls for the beam currents of
all color signals have responded when the picture appears in the picture
tube.
In a further embodiment of the circuit arrangement
according to the invention with a comparator arrangement which compares
the measuring signal with the reference signal and derives the control
signal from this comparison, the change detection arrangement detects a
change in the control signal with respect to time and issues the change
signal when the control signal has assumed an essentially constant
value. In the case of the representation of a color signal the
comparator arrangement derives several part control signals, whose
changes with time are detected by the change detectors, from a
corresponding comparison of the part measuring signals with the
reference signal. In this embodiment of the circuit arrangement of the
invention, preference is given to storage of only the control signal or
the part control signals for the purpose of controlling the beam
currents.
In another embodiment of the circuit arrang
ement of the
invention which includes a control signal memory which contains at
least one capacitor in which a charge or voltage corresponding to the
control signal is stored, the change detection arrangement issues the
change signal when a charge-reversing current of the capacitor occurring
during the turning on of the picture tube has fallen below a limit
value and has thus at least largely decayed. Such a detection of the
steady state of the cut-off point control is independent of the actual
magnitude of the control signal and therefore independent of, for
example, the level of the picture tube cut-off voltage, circuit
tolerances or ageing processes in the circuit arrangement or the picture
tube.
Detection of whether or not the charge-reversing current
exceeds the limit value is performed preferentially by a current
detector which is designed with a current mirror system which is
arranged in a supply line to a capacitor acting as a control signal
store. A current mirror arrangement of this kind supplies a current
which coincides very precisely with the charging current of the
capacitor. This current is then compared, preferably in a further device
contained in the change detection arrangement, with a current
representing a limit value or, after conversion into a voltage, with a
voltage representing the limit value. The change signal is obtained from
the result of this comparison.
On the other hand, digital
memories may also be used as control signal memories, especially when
the picture signal is supplied as a digital signal and the blocking
point control is constructed as a digital control loop. In such a case,
the comparator arrangement, the change detection arrangement and the
trigger circuit are also designed as digital circuits. Then, the change
detection arrangement advantageously forms the difference of the signals
stored in the control signal memory in two successive sampling
intervals and compares this with the limit value formed by a digital
value. If the difference falls short of the limit value, the change
signal is issued.
BRIEF DESCRIPTION OF THE DRAWINGS
An embodiment of the invention is described in greater detail below with the aid of the drawings in which:
FIG. 1 shows a block circuit diagram of the embodiment,
FIG. 2 shows a somewhat more detailed block circuit diagram of the embodiment,
FIG. 3 shows time-dependency diagrams of some signals occurring in the circuit diagram shown in FIG. 2, and
FIG. 4 shows a somewhat moredetailed block circuit diagram of a part of the circuit diagram shown in FIG. 2.
DETAILED DESCRIPTION OF THE INVENTION
FIG.
1 shows a block circuit diagram of a circuit arrangement to which a
picture signal is fed via a first input 1 of a combinatorial stage 2.
From the output 3 of the combinatorial stage 2 the picture signal is fed
to the picture signal input of a controllable amplifier 5 which at an
output 6 issues a current controlled by the picture signal. This current
is fed via a measuring stage 7 to a hot cathode 8 in a picture tube 9
and forms therein a beam current of a cathode ray by means of which a
picture defined by the picture signal is displayed on a fluorescent
screen of the picture tube 9.
The measuring stage 7 measures the
current fed to the hot cathode 8, i.e. the the beam current in the
picture tube 9, and at a measuring signal output 10, issues a measuring
signal corresponding to the magnitude of this current. This is fed to a
measuring signal input 11 of a comparator arrangement 12 to which a
reference signal is supplied at a reference signal input 13. In a
preferably periodically recurring sampling interval during the
occurrence of a given reference level in the picture signal, the
comparator arrangement 12 forms a control signal from the value of the
measuring signal fed to the measuring signal input 11 at this time, on
the one hand, and the reference signal, on the other, by means of
substraction and delivers this at a control signal output 14. From there
the control signal is fed to an input 15 of a control signal memory 16
and is stored in the latter. The control signal is fed via an output 17
of the control signal memory 16 to a second input 18 of combinatorial
stage 2 in which it is combined with the picture signal, e.g. added to
it.
The combinatorial stage 2, the controllable amplifier 5, the
measuring stage 7, the comparator arrangement 12 and the control signal
memory 16 form a control loop with which the beam current is guided
towards the reference signal in the sampling interval during the
occurrence of the reference level in the picture signal. For the
reference level, use is made in particular of a black level or a level
with small, fixed distance from the black level, i.e. a value in the
picture signal which produces a black or almost back picture area in the
displayed picture in the picture tube. In this case the control loop,
as described, forms a cut-off point control for the picture tube. If the
reference level is away from the black level, the control loop is also
designated as quasi-cut-off-point control.
The circuit
arrangement as shown in FIG. 1 also has a trigger circuit 19 to which
the measuring signal from the measuring signal output 10 of measuring
stage 7 is fed at a measuring signal input 20. When the circuit
arrangement and therefore the picture tube are turned on, the trigger
circuit 19 is set in a first state in which by means of a first
connection 21 it blocks the comparator arrangement 12 in such a way that
the latter delivers no control signal or a control signal with the
value zero at its control signal output 14. This prevents the control
signal memory 16 from storing undefined values for the control signal at
the moment of turning on or immediately thereafter.
The circuit
arrangement shown in FIG. 1 also has a logic network 22 which is
connected via a second connection 23, by means of which a switching
signal is supplied, with the trigger circuit 10 and via a third
connection 24 with the controllable amplifier 5. Like the trigger
circuit 19, the logic network 22 also finds itself controlled, when the
circuit arrangement is being turned on, by the switching signal in a
first stage in which by way of the third connection 24 it blocks the
controllable amplifier 5 with a blocking signal in such a way that no
beam currents controlled by the picture signal can yet flow in the
picture tube 9. Thus the picture tube 9 is blanked; no picture is
displayed yet.
When picture tube 9 is turned on, the hot cathode 8
is still cold so that no beam current can flow anyhow. The hot cathode 8
is then heated up and, after a certain time, begins gradually to emit
electrons as the result of which a cathode ray and therefore a beam
current can form. However, during the heating up of the hot cathode 8,
and because the cut-off point control has not yet responded, this would
be undefined and is therefore suppressed by the controllable amplifier
5. Only in time intervals which are provided immediately subsequent to
flybacks of the cathode rays into an initial position at the changeover
from the display of one image to that of a subsequent image, but even
before the start of the display of the subsequent image, the
controllable amplifier 5 delivers a voltage in the form of an auxiliary
pulse for a short time at its output 6, and when the hot cathode 8 in
the picture tube 9 is heated up sufficiently, this voltage produces a
beam current. The time interval for the delivery of this voltage is
selected in such a way that a cathode ray produced by its does not
pr
oduce a visible image in the picture tube 9, and coincides for example
with the sampling interval.
The measuring stage 7 measures the
short-time cathode current produced in the manner described and, at its
measuring signal output 10, delivers a corresponding measuring signal
which is passed via measuring signal output 20 to the trigger circuit
19. If the measuring signal exceeds a definite preset threshold value,
the trigger circuit 19 is switched into a second state in which it
releases the comparator arrangement 12 via the first connection 12 and,
by means of the second connection 23, uses the switching signal to also
bring the logic network 22 into a second state. The comparator
arrangement 12 now evaluates the measuring signal supplied to it via the
measuring signal input 11, i.e. it forms the control signal as the
difference between the measuring signal and the reference signal
supplied via the reference signal input 13. The control signal is
transferred via the control signal output 14 and the input 15 into the
control signal memory 16. It is subsequently fed via the output 17 of
the control signal memory 16 to the second input 18 of the combinatorial
stage 2 and is there combined with the picture signal at the first
input 1, e.g. is superimposed on it by addition. This superimposed
picture signal is fed to the picture signal input 4 of the controllable
amplifier 5 via the output 3 of the combinatorial stage 2.
In the
second state of the logic network 22 th
e controllable amplifier 5 is
switched via the third connection 24 by the blocking signal in such a
way that the picture signal controls the beam currents only during the
sampling intervals and that, for the rest, no image appears yet in the
picture tube. The cut-off point control now gebins to respond, i.e. the
value of the control signal is changed by the control loop comprising
the combinatorial stage 2, the controllable amplifier 5, the measuring
stage 7, the comparator arrangement 12 and the control signal memory 16
until such time as the beam current in the picture tube 9 at the
blocking point or at a fixed level with respect to it is adjusted to a
value preset by the reference signal. For this purpose the sampling
interval, in which the picture signal controls the beam current via the
controllable amplifier 5 is selected in such a way that within it the
picture signal just assumes a value corresponding to the cut-off point
or to a fixed level with respect to it.
During the response of
the cut-off point control the control signal fed to the control signal
memory 16 changes continuously. Between the control signal output 14 of
the comparator arrangement 12 and the input 15 of the control signal
memory 16 is inserted a changed detection arrangement 25 which detects
the variations of the control signal. When the cut-off point control has
responded, i.e. the control signal has assumed a constant value, the
change detection arrangement 25 delivers a change signal at an output 26
which indicates that the steady stage of the cut-off point control is
achieved and the said signal is fed to a change signal input 27 of the
logic network 22. The logic network then switches into a third state in
which via the third connection 24 it enables the controllable amplifier 5
in such a way that the beam currents are now controlled without
restriction by the picture signal. Thus a correctly represented picture
appears in the picture tube 9.
A shadow-like representation of
individual constituents of the circuit arrangement in FIG. 1 is used to
indicate a modification by which this circuit arrangement is equipped
for the representation of color pictures in the picture tube 9. For
example, three color signals are fed in this case as the picture signal
via the input 1 to the combinatorial stage 2. Accordingly, the input 1
is shown in triplicate, and the combinatorial stage 2 has a logic
element, e.g. an adder, for example of these color signals. The
controllable amplifier 5 now has three amplifier stages, one for each of
the color signals, and the picture tube now contains three hot cathodes
8 instead of one so that three independent cathode rays are available
for the three color signals.
However, to simplify the circuit
arrangement and to save on components, only one measuring stage 7 is
provided which measures all three beam currents successively. Also, the
comparator arrangement 12 forms part control signals from the
successively arriving part measuring signals for the individual beam
currents with the reference signal, and these part control signals are
allocated to the individual color signals and passed on to three storage
units which are contained in the control signal memory 16. From there,
the part control signals are sent via the second input 18 of the
combinatorial stage 2 to the assigned logic elements.
The circuit
arrangement thus forms three independently acting control loops for the
cut-off point control of the individual color signals, in which case
only the measuring stage 7 and to some extent at least the comparator
arrangement 12 are common to these control loops.
The change
detection arrangement 25 now has three change detectors each of which
detects the changes with time of the part control signals relating to a
color signal. Then via the output 26 each of these change detectors
delivers a part change signal to the change signal input 27 of the logic
network 22. These part change signals occur independently of one
another when the relevent control loop has responded. The logic network
22 evaluates all three part change signals and does not switch into its
third stage until all part change signals indicate a steady state of the
control loops. Only then, in fact, is it ensured that all the color
signals from the beam currents controlled by them are correctly
reproduced in the picture tube, and thus no distortions of the displayed
image, especially no color purity errors, occur. The color picture
displayed then immediately has the correct brightness and color on its
appearance when the picture tube is turned on.
FIG. 2 shows a
somewhat more detailed block circuit diagram of an embodiment of a
circuit arrangement equipped for the processing of a picture signal
containing three colour signals. Three color signals for the
representation of the colors red, green and blue are fed to this circuit
arrangement via three input terminals 101, 102, 103. A red color signal
is fed via the first input terminal 101 to a first adder 201, a green
colour signal is fed via the second input terminal to a second adder
202, and a blue colour signal is fed via the third input terminal 103 to
a third adder 203. From outputs 301, 302 and 303 of the adders 201,
202, 203 the color signals are fed to amplifier stages 501, 502 and 503
respectively. Each of the amplifier stages contains a switchable
amplifier 511, 512 and 513, an output amplifier 521, 522 and 523 as well
as a measuring transistor 531, 532 and 533 respectively. The emitters
of these measuring transistors 531, 532, 533 are each connected to a hot
cathode 801, 802, 803 of the picture tube 9 and deliver the cathode
currents, whereas the collectors of measuring transistors 521, 532, 533
are connected to one another and to a first terminal 701 of a measuring
resistor 702 the second terminal of which 703 is connected to earth. The
current gain of the measuring transistors 531, 532 and 533 is so great
that their collector currents coincide almost with the cathode currents.
By measuring the voltage drop produced by the cathode currents at the
measuring resistor 802 it is then possible to measure the
cathode
currents and therefore the beam currents in the picture tube 9 with
great accuracy.
The falling voltage at the measuring resistor 702
is fed as a measuring signal to an input 121 of a buffer amplifier 120
with a gain factor of one, at the output 122 of which the unchanged
measuring signal is therefore available at low impedance. From there it
is fed to a first terminal 131 of a reference voltage source 130 which
is connected with its second terminal 132 to inverting inputs 111, 112
and 113 of three differential amplifiers 123, 124, 125 respectively. The
differential amplifiers 123, 124, 125 also each have a non-inverting
input 114, 115, and 116 respectively. These are connected to each other
at a junction 117, to earth via a leakage current storage capacitor 126
and to the output 122 of the buffer amplifier 120 via decoupling
resistor 118 and a leakage current sampling switch 119. In addition, the
input 121 of the buffer amplifier 120 can be connected to earth via a
short-circuiting switch 127.
From outputs 141, 142, and 143
respectively of the differential amplifiers 123, 124 and 125, part
control signals relating to the individual color signals are fed in the
form of electrical voltages (or, in some cases, charge-reversing
currents) via control signal sampling switches 154, 155 and 156, in the
one instance, to first terminals 151, 152 and 153 respectively of
control signal storage capacitors 161, 162, 163 which form the storage
units of the control signal memory 16 and store inside them charges
corresponding to these voltages (or formed by the charge-reversing
currents). In the other instance, the part control signals are fed to
second inputs 181, 182 and 183 of the first, second or third adders 201,
202, 203 respectively and are added therein to the color signals from
the first, second or third input terminals 101, 102 or 103 respectively.
The operation of the comparator arrangement 12 which consists
mainly of the buffer amplifier 120, the reference voltage source 130 and
differential amplifiers 123, 124, 125 will be explained below with the
aid of the pulse diagrams in FIG. 3. FIG. 3a shows a horizontal blanking
signal for a television signal which, as the picture signal, controls
the beam currents in the picture tube 9. In this diagram, H represents
horizontal blanking pulses which follow one another in the picture
signal at the time interval of one line duration and by means of which
the beam currents are switched off during line flyback between the
display of the individual picture lines in the picture tube. FIG. 3b
shows a vertical blanking pulse V by means of which the beam currents
are switched off during the change ober from the display of one picture
to the display of the next picture. FIG. 3c shows a measuring signal
control pulse VH which is formed from a vertical blanking pulse
lengthened by three line duration.
The short-circuiting switch
127 is now controlled in such a way that it is non-conducting only
throughout the duration of the measuring signal control pulse VH and
during the remaining time short-circuits the input 121 of the buffer
amplifier 120 to earth. This means that a measuring signal only reaches
the comparator arrangement 12 during frame change so that the parts of
the picture signal which control the beam currents producing the picture
in the picture tube exert no influence on comparator arrangement 12 and
therefore on the blocking point control.
Throughout the duration
of the measuring signal control pulse VH, the measuring signal from
output 122, reduced by a reference voltage issued by the reference
voltage source 130 between its first 131 and its second terminal 132, is
present at the inverting inputs 111, 112, 113 of differential
amplifiers 123, 124, 125. If the differential amplifiers 123, 124, 125
were not present, this difference would be fed directly as part control
signals to the control signal storage capacitors 161, 162, 162. The
differential amplifiers 123, 124, 125 amplify the difference and thus
form the control amplifiers of the control loops.
The comparator
arrangement 12 further contains a device for compensation of the
influence of any leakage currents occurring in the picture tube 9. For
this purpose, a voltage to which the leakage current storage capacitor
126 is charged is fed to the non-inverting inputs 114, 115, 116 of the
three differential amplifiers 123, 124 and 125. The charging is
performed by the measuring signal from output 122 of the buffer
amplifier 120 via the decoupling resistor 118 and the leakage current
sampling switch 119 which is closed only within the period of the
vertical blanki
ng pulse V, and in certain cases only during part of the
latter. Within this time the beam currents are, in fact, totally
switched off by the picture signal so that in certain cases only a
leakage current flows through the measuring resistor 702. Consequently,
throughout the duration of the vertical blanking pulse V the measuring
signal corresponds to this leakage current. Because the leakage current
also flows during the remaining time, even outside the duration of the
vertical blanking pulse the measuring signal contains a component
originating from the leakage current which therefore is also contained
in the voltage fed to the inverting inputs 111, 112, 113 of differential
amplifiers 123, 124, 125 and is subtracted out in the differential
amplifiers 123, 124, 125.
The part control signal is fed from
output 141 of differential amplifier 123 by the first control signal
sampling switch 154 to the first terminal 151 of the first control
signal storage capacitor 161 during the period of a storage pulse L1 and
is stored in the said capacitor. Similarly, the part control signal
from output 143 of differential amplifier 125 is fed to the third
control signal storage capacitor 163 during the period of a storage
pulse L2 and the part control signal from output 142 of differential
amplifier 124 is fed to the second control signal storage capacitor 162
during a storage pulse L3. The storage pulses L1, L2 and L3 are
illustrated in FIGS. 3d, e and f. They lie in sequence in one of the
three line periods by which the measuring signal control pulse VH is
longer than the vertical blan
king pulse V. These three line periods form
the sampling interval for the measuring signal or the part measuring
signals, as the case may be. During the remaining periods the outputs,
141, 152, 143 of the differential amplifiers 123, 124, 125 are isolated
from the control signal storage capacitors 161, 162, 163 so that no
interference can be transmitted from there and any distortion of the
stored part control signals caused thereby is eliminated. For the
duration of storage pulses L1, L2 and L3 the color signals at the input
terminals 101, 102, 103 are at their reference level i.e. in the present
embodiment at a level, corresponding to the blocking point or at a
fixed level with respect to it so that the control loops can adjust to
this level.
The switchable amplifiers 511, 512, and 513 each
receive at each input 241, 242, 243 a blanking signal BL1, BL2, BL3
respectively, the curves of which are shown in FIGS. 3g, h, i. These
blanking signals interrupt the supply of the color signals during line
flybacks and frame change, i.e. during the period of the measuring
signal control pulse VH, and thus the beam currents in these time
intervals are switched off. Naturally, the red color signal is let
through during the first line period after the end of the vertical
blanking pulse V, the blue color signal during the second line period
after the end of the vertical blanking pulse V and the green color
signal during the third line period after the end of the vertical
blanking pulse V by the switchable amplifiers 511, 512, 513 respectively
so that they can control the beam currents. Blanking signals BL1, BL2
and BL3 also provide for interruptions in the frame change blanking
pulse, which corresponds to the measuring signal control pulse, in the
corresponding time intervals. In these time intervals the beam currents
are measured and part control signals are determined from the part
measuring signals and stored in the control signal storage capacitors
161, 162, 163.
The circuit arrangement shown in FIG. 2 further
contains a trigger circuit 19 to which a supply voltage is fed via a
supply terminal 190. Via a reset input 191 a voltage is also
supplied to
the trigger circuit 19 from a third terminal 133 of the reference
voltage source 130. When the circuit arrangement is turned on, this
voltage is designed so as to be delayed with respect to the supply
voltage so that when the circuit arrangement is brought into operation
the interplay of the two voltages produces a switch-on reset signal such
that a low-value voltage pulse occurs at the reset input 191 during
turn on, which means that the trigger circuit 19 is set in its first
state. The reset input 191 can also be connected to another circuit of
any configuration which generates a switch-on reset signal when the
picture tube is turned on.
The trigger circuit 19 is further
connected via a second connection 23 to a logic network 22 which, when
the circuit arrangement is turned on, is also set into a first state via
the second connection 23. In this first state the logic network 22
delivers a blocking signal at a blocking output 240 which is fed to the
three switchable amplifiers 511, 512, 513. By this means the supply of
the color signals to the output amplifiers 521, 522, 523 is interrupted
completely so that no beam currents can be generated by these. No
picture is therefore displayed.
An insertion signal EL which
extends over the three line periods by which the measuring signal
control pulse VH is longer than the vertical blanking pulse V, i.e. over
the sampling interval, is also fed via a line 233 to the trigger
circuit 19 and the logic network 22. As long as the trigger circuit 19
is in its first state, this insertion pulse EL is issued via a control
output 192 from the trigger circuit 19 and fed to the pulse generator
244. During the period of the insertion pulse EL this generator produces
a voltage pulse of a definite magnitude and passes this to output
amplfiiers 521, 522, 523 as an auxiliary pulse via switching diodes 245,
246, 247. By this means the beam currents are switched on for a short
time so as to receive a measuring signal despite the disconnected color
signals as soon as at least one of the hot cathodes 801, 802, 803
delivers a beam current.
In its first state the trigger circuit
19 also delivers a signal via a control line 211, and this signal is
used to switch the outputs 141, 142, 143 of the differential amplifiers
123, 124, 125 to earth potential or practically to earth potential. This
suppresses effects of voltages at the inputs 111 to 116 of the
differential amplifiers 123, 124, 125, especially effects of the
reference voltage source 130 which may in some cases initiate incorrect
charging of the control sig
nal storage capacitors 161, 162, 163.
The
measuring signal produced by means of the pulse generator 244 at the
input 121 of the buffer amplifier 120 is also fed to the trigger circuit
19 via a measuring signal input 20. If it exceeds a preset threshold
value, the trigger circuit 19 switched into its second state. The logic
network 22 is then also switched into its second state via the second
connection 23. The differential amplifiers 123, 124, 125, too, are
triggered by the signal along the control line 211 into issuing a
control signal defined by the difference in the voltages at its inputs
111 to 116. The pulse generator 244 is blocked by the control output
192. The blocking signal issued from the blocking output 240 of the
logic network 22 now turns on the switchable amplifiers 511, 512, 513 in
the time intervals defined by the storage pulses L1, L2, L3 in such a
way that in these time intervals the color signals can produce beam
currents to form a measuring signal by which the control loops respond.
However, the display of the picture is still suppressed. The control
signal storage capacitors 161, 162, 163 are charged up in this process.
In the leads to the first terminals 151, 152, 153 there are change
detectors 251, 252, 253 which detect the changes of the charging
currents of the control signal storage capacitors 161, 162, 163 and at
their outputs 261, 262, 263 in each case deliver a part change signal
when the charging current of the control signal storage capacitor in
question has decayed and thus the relevant control loop has responded.
The part change signals are fed to three terminals 271, 272, 273 of the
change signal input 27 of the logic network 22.
When part change
signals are present from all change detectors 251, 252, 253, when
therefore all control loops have responded, the logic network 22
switches from its second to its third state. The blocking signal from
the blocking output 240 is now completely disconnected such that the
switchable amplifiers 511, 512, 513 are now switched only by the
blanking signals BL1, BL2, BL3. The colour signals are then switched
through to the output amplifiers 521, 522, 523 and the picture is
displayed in the picture tube.
FIG. 4 shows an embodiment for a
trigger circuit 19 and a logic network 22 of the circuit arrangements as
shown in FIGS. 1 or 2. The trigger circuit 19 contains a flip-flop
circuit formed from two NAND-gates 194, 195 to which the switch-on reset
signal, by which the trigger circuit 19 is returned to its first stage,
is fed via the reset input 191. All the elements of the circuit
arrangement in FIG. 4 are shown in positive logic. Thus, a short-time
low voltage at the reset input 191 immediately after the circuit
arrangement is started up is used to set the flip-flop circuit 194, 195
in such a way that a high voltage occurs at the output of the second
NAND gate 194 and a low voltage at the output of the second NAND gate
195. The low voltage at the output of the second NAND gate 195 blocks
differential amplifiers 123, 124, 125 via the control line 211 in the
manner described.
The insertion pulse EL is fed via the line 233
to the trigger circuit 19, is combined via an AND gate 196 with the
signal from the output of the first NAND gate 194 and is delivered at
the control output 192 for the purpose of controlling the pulse
generator 244.
The signals from the outputs of the NAND-gates
194, 195 are fed via a first line 231 and a second line 232 of the
second connection 23 as a switching signal to the logic network 22. The
first line 231 is connected to reset inputs R of three part change
signal memories 221, 222, 223 in the form of bistable flip-flop circuits
which when the circuit arrangement is started up are reset via the
first line 231 in such a way that they carry a low voltage at their
outputs Q. The second line 232 of the second connection 23 leads via
three AND gates 224, 225, 226 to setting inputs S of the three part
change signal memories 221, 222, 223. By means of the AND gates 224,
225, 226 the signal on the second line 232 of the second connection 23
is combined each time with one of the part change signals supplied via
the terminals 271, 272, 273. The signals from the outputs Q of the part
change signal memories 221, 222, 223 are combined by means of a
collecting gate 227 i
n the form of an NAND gate and are held ready at
its output 228.
The measuring signal is fed to the trigger
circuit 19 via the measuring signal input 20 and passed to a first input
197 of a threshold detector 198 to which at a second input a threshold
value, in the form of a threshold voltage for example, produced by a
threshold generator 199 is also supplied. When the voltage at the first
input 197 of the threshold detector 198 is smaller than the voltage
delivered by the threshold generator 199, the threshold detector 198
delivers a high voltage at its output 200. When, on the other hand, the
voltage at the first input 197 is greater than the voltage of the
threshold generator 199, the voltage at the output 200 jumps to a low
value. This voltage is supplied as the setting signal of the flip-flop
circuit 194, 195, reverses the latter and thereby switches the trigger
circuit 19 into its second state when the voltage at the first input 197
exceeds the voltage of the threshold generator 199.
Between the
output 200 and the flip-flop circuit 194, 195 in the circuit arrangem
ent
shown in FIG. 4 there is inserted an inquiry gate 181 in the form of an
OR gate to which an inquiry pulse is fed via an inquiry input 193 of
the trigger circuit 19. This ensures that the flip-flop circuit 194, 195
is switched over only at a time fixed by the inquiry pulse--in the
present case a negative voltage pulse--and not at any other times due to
disturbances. As such an inquiry pulse it is possible to use, for
example, a pulse which occurs in the second line period after the end of
the vertical blanking pulse V, i.e. one which largely corresponds to
the storage pulse L2.
After the switching over of the flip-flop
circuit 194, 195 corresponding to the setting of the trigger circuit 19
into the second state, appropriately modified signals are supplied via
the control line 211 and the output 192 for the purpose of controlling
the pulse generator 244 and the differential amplifiers 123, 124, 125.
Modified voltages also appear on the lines 231, 232 of the second
connection 23, and these voltages release the part change signal
memories 221, 222, 223 such that they can each be set when the part
change
signals reach the terminals 271, 272, 273.
In certain
cases, a further flip-flop circuit 234 is inserted in the lines 231, 232
to delay the signals passing along these lines; this is reset via the
first line 231 when the circuit arrangement is started up and thus it
also resets the part change signal memories 221, 222, 223. However,
after the trigger circuit 19 is switched into the second state the
further flip-flop circuit 234 is not set via the second line 232 of the
second connection 23 until a release pulse arrives via a release input
235 and another AND gate 236, for example a period of approximately the
interval of two vertical blanking pulses V after the switching of the
trigger circuit 19 into the second state. In this way it is possible to
bridge a period of time in which no defined signal values are present at
the terminals 271, 272, 273.
The signal at the output 228 of the
collecting gate 227 changes its state when the last of the three part
change signals has also arrived and has set the last of the three part
change signal memories. The signal is then combined via a gate
arrangement 229 of two NAND gates and one AND gate with the insertion
pulse EL of line 223 and with the signal on the second line 232 of the
second connection 23 or from the output Q of the further flip-flop
circuit 234 to the blocking signal delivered at the blocking output 24
which is fed to the switchable amplifiers 511, 512, 513.
FIGS.
31, m, n show the combinations of the blocking signal with the blanking
signals BL1, BL2, and BL3 at the blanking inputs 241, 242, 243 of the
switchable amplifiers 511, 512, 513 in the form of logic AND operations.
The dot-dash lines show resulting insertion signals A1, A2, A3 formed
by these operations after the starting up of the circuit arrangement and
before the occurrence of a beam current, i.e. in the first state of the
logic network 22. Here the resulting insertion signals A1, A2, A3 are
constant at low level. The dash curves show the resulting insertion
signals A1, A2, A3 after the appearance of a beam current and before the
steady state of the cut-off point control is reached, i.e. in the
second state of the logic network 22, while the continuous curves
represent the resulting insertion signals A1, A2, A3 in the steady state
of the cut-off point control, i.e. in the third state of logic network
22. The dash curves have similar shapes to storage pulses L1, L2, L3,
whereas the continuous curves correspond in shape to the inverses of the
blanking signals BL1, BL2, BL3. In this case a high level of the
resulting insertion signals A1, A2 or A3 means that the switchable
amplifier 511, 512 or 513 feeds the colour signal to the relevant output
amplifier 521, 522 or 523 respectively, whereas a low level in the
resulting insertion signal A1, A2 or A3 means that the relevant
switchable amplifier 511, 512 or 513 is blocked for the color signal.
The
circuit arrangement described is designed in such a way that the
trigger circuit 19 remains in its second state and logic network 22
remains in its third state even if charging currents reappear at the
difference signal storage cpacitors 161, 162, 163 due to disturbances
during the operation of the circuit arrangement. The cutoff point
control then makes readjustments without the displayed picture being
disturbed.
In the circuit arrangement shown in F
IG. 2, the green
color signal can also be let through during the second line period after
the end of the vertical blanking pulse V and the blue color signal
during the third line period after the end of the vertical blanking
pulse V by the switchable amplifiers 511, 512, 513 for the purpose of
controlling the beam currents. The storage pulses L2 and L3 at the
control signal sampling switches 155 and 156 and the second and third
blanking signals BL2 and BL3 at the blanking inputs 242 and 243 are then
to be interchanged. The resulting insertion signals A2 and A3 as shown
in FIGS. 3m and n are also interchanged then accordingly.
In FIG.
2 a dashed line is used to indicate which components of the circuit
arrangement can be combined advantageously to form an integrated
circuit. The first terminals 151, 152, 153 of the difference signal
storage capacitors 161, 162, 163, one terminal 128 of leakage current
storage capacitor 126, three terminals 524, 525, 526 in the leads to the
output amplifiers 521, 522, 523 as well as a line connection 704
between the first terminal 701 of the measuring resistor 702 and the
input 121 of the buffer amplifier 120 will then form the connecting
contacts of this integrated circuit
TELEFUNKEN PALCOLOR 2228 CHASSIS 415A The Telefunken PPHV Flyback Horizontal Output Transformer Technology:
Line end stage including transformer for a television receiver:
The current Telefunken 415/
615 CTV chassis series like the here above
shown tv is conventional in most respects, with its self oscillating
chopper power supply which also provides mains isolation, TDA 3560 OR
TDA3562A single -chip decoder, class AB RGB output stages, TDA1670 field
timebase i.c. and BU208 line output transistor. The line output
transformer is something quite new however.
Line output
transformers are nowadays reliable components though a percentage of
failures do occur. Tripler breakdown after some years' service is far
more common, except in Japanese sets. The transformer is certainly one
of the most expensive items in a TV receiver: the pulse windings and
secondaries used to provide various supply lines add greatly to the
manufacturing cost and increase the insulation problems. Telefunken
decided to do something about this in designing the 415/615 chassis. The
aims were to reduce the cost of the transformer, make it as small as
possible, mountable without securing screws, and producible by automatic
production methods whilst having a power handling capability,
reliability and internal resistance equal to or better than conventional
designs. To achieve these aims it was decided to use a half -wave
e.h.t. rectifier arrangement. This in itself is not unique of course,
but for CTV use the problem of a half -wave rectifier circuit is the
high leakage inductance and internal capacitance in the transformer. The
result is an e.h.t. system with a high internal resistance. It was
decided therefore to use a transformer with just two windings, the
primary and e.h.t. overwinding. The other supplies are derived from the
chopper transformer, while a transistor to which the line flyback pulses
are fed produces the feedback pulse for the flywheel sync system.
The
latter is in the TDA1950 sync/line oscillator chip, which also produces
the sandcastle pulse used by the TDA3560 or TDA3562A decoder i.c. for
gating, blanking and clamping. This decision greatly simplifies the
transformer of course, while collaboration with a specialist
manufacturer or ferrite cores enabled the cross-sectional area of the
core to be reduced by some 25 per cent. The result is a transformer
which is extremely compact and light. The main design advance however is
the use of what Telefunken call the "push-pull high-voltage concept".
This uses two rectifier diodes, one at each end of the winding as shown
in Fig. 1. The action of the circuit is shown in Fig. 2. D1 acts as a
conventional peak rectifier when the positive going flyback pulse
arrives at its anode, charging transformer George R. Wilding the e.h.t.
reservoir capacitor C2 (tube capacitance). During this time D2 conducts,
clamping the bottom end of the e.h.t. overwiding to chassis. At the end
of the flyback pulse half cycle the bottom end of the winding swings
positively and D2 cuts off. It conducts again when the voltage at its
cathode (circuit oscillatory action) tries to swing negatively, thus
charging the interwinding capacitance Cl. The next time the flyback
pulse occurs, D1 sees an enhanced voltage at its anode, i.e. the sum of
the flyback pulse and the charge on Cl. The circuit thus acts as a
voltage multiplier, and the number of overwinding turns can be
substantially reduced in comparison with a simple half -wave rectifier
circuit. Even though it's on such a small former the primary winding has
only two layers. These terminate in connec- tion pins which together
with two snap-on springs hold the transformer securely to the board for
soldering. The diodes and the e.h.t. connection are secured to the body
of the overwinding and encapsulated in heat hardened epoxy resin. The
focus supply is obtained via a bleed resistor in the tube's anode cap
connector. Fig. 3 shows the feedback pulse generator stage.
Der PPHV-Transformator", by Walter Goseberg, Funkshau 1/1981, pp. 70-71.
"Kaum zu fassen: 23.000 Volt zum Anfassen!-PPHV-Zeilentrafo der Zukunft. Aus Hannover."-Telefunken Heute, Aktuelle Information fur den Fachhandel.
A line end stage for a television receiver which comprises a transformer, a first high voltage rectifier and a second high voltage rectifier. The transformer has a primary winding coupled to the line sweep coils of the receiver, and a secondary winding. The secondary winding has one end coupled through the first high voltage rectifier to ground and through the second high voltage rectifier to the anode of the television receiver picture tube. The transformer comprises a core having a longitudinal axis. The primary winding is mounted on the core coaxial with the longitudinal axis and an insulating winding form surrounds the primary winding. The winding form is provided with spaced longitudinally-distributed radially-extending chambers and the secondary winding is located within these chambers. The thicknesses of the winding form between the bottoms of the chambers and the primary winding are greatest at the ends of the winding form and become progressively smaller toward the center of the form.
1. In a televison receiver having line sweep coils and a picture tube, a line end stage comprising
a transformer coupled to said line sweep coils including
a core having a longitudinal axis;
a single continuous untapped primary winding mounted on said core, said primary winding being coaxial with said longitudinal axis;
an insulating winding form surrounding said single primary winding, said winding form being coaxial with said longitudinal axis and being provided with spaced longitudinally-distributed radially-extending chambers; and
a single continuous untapped secondary winding located within the chambers of said winding form, the distances between the bottoms of the chambers within said winding form and said primary winding decreasing from the ends of said winding form toward the center thereof along said longitudinal axis;
a first high voltage rectifier having its anode connected to ground and its cathode connected to one end of said secondary winding; and
a second high voltage rectifier having its anode connected to the other end of said secondary winding and its cathode connected to the anode of said picture tube.
2. A line end stage as defined in claim 1 wherein the thickness of the insulation of said insulating winding form between said primary and secondary windings is a minimum along a line perpendicular to said longitudinal axis at the center of said core and increases toward the end of said core.
3. A line end stage as defined in claim 1 wherein the thickness of said winding form between the bottom of the chamber at the center of said winding form and said primary winding has a predetermined value, and the thicknesses of each of said chambers toward the ends of said winding form and said primary winding increases with respect to that at the center as a function of the distance from said center chamber.
4. A line end stage as defined in claim 1 wherein at least one of said chambers has parallel sides and the bottom thereof is perpendicular to said sides.
5. A line end stage as defined in claim 1 wherein the chambers at the ends of said winding form are empty, and said secondary winding is located within the chambers therebetween.
6. A line end stage as defined in claim 1 wherein the thicknesses of the secondary windings within said chambers are different, said thicknesses being selected to tune said secondary winding to a predetermined harmonic of the frequency of the return sweep oscillation of said television receiver.
7. A line end stage as defined in claim 1 wherein said primary winding extends in the direction of said longitudinal axis beyond said secondary winding.
8. A line end stage as defined in claim 1 wherein at least one of said chambers has parallel sides and the bottom thereof has a rounded fluted shape.
9. A line end stage as defined in claim 8 wherein the edge of said bottom adjacent one side of said chamber has a different radius of curvature than the edge adjacent the other side of said chamber.
10. A line end stage as defined in claim 9 wherein the chambers containing said secondary winding at the ends of the said winding form have said rounded fluted shape and wherein the edges of the bottoms of said chambers facing the ends of said winding form have a larger radius of curvature than the opposite edges of said chambers.
Description:
BACKGROUND OF THE INVENTION
This invention relates to a line end stage for a television receiver and, in particular, to a transformer comprising a component of this stage. A line end stage for a television receiver includes, among other components, a transistor which functions as a switch, a high voltage rectifier, and a transformer having a primary winding and a high voltage secondary winding. The line end stage produces the high voltage required to energize the picture tube.
A conventional line end stage of this type is a relatively expensive and heavy part of the receiver, whih must withstand high voltages and currents on the order of 25,000 volts and two to three amperes. It performs several functions such as controlling the line sweep coils, and generating the high voltage for the picture tube, pulses for gating purposes and the direct operating voltages. Consequently, the stage must satisfy a number of different requirements.
More specifically, the line end stage should be as small as possible, light in weight and easy to manufacture. A low internal impedance is desirable and, despite the relatively high power involved, the stage should operate over long periods without malfunctioning.
It is known that a low internal impedance can be attained by tuning the stray inductance of the high voltage winding and the effective capacitance to certain oddnumbered harmonics of the frequency of the retrace or return sweep oscillation of the line transformer. In this way, the pulse shape of the retrace pulse is broadened so as to reduce the internal impedance of the high voltage source, it being of particular advantage to tune to the ninth harmonic of the return sweep oscillation frequency. However, tuning to such a high frequency presents a number of technical problems because of the design of the line end stage, and because the effective inductances and capacitances must not exceed certain values. Maintaining these values and simultaneously meeting the other requirements is often difficult in practice.
It is an object of the present invention to provide a line end stage having a particularly simple design and which provides a fixed coupling between the primary and high voltage windings, the stray inductance of the high voltage winding being particularly low. This stage permits tuning to the desired harmonic of the frequency of the return sweep oscillation.
SUMMARY OF THE INVENTION
In accordance with the present invention, a line end stage for a television receiver is provided which comprises a transformer, a first high voltage rectifier and a second high voltage rectifier. The transformer has a primary winding coupled to the line sweep coils of the receiver, and a secondary winding. The secondary winding has a first end coupled through the first high voltage rectifier to ground and a second end coupled through the second high voltage rectifier to the anode of the television receiver picture tube.
The transformer comprises a core having a longitudinal axis. The primary winding is mounted on the core coaxial with the longitudinal axis, and an insulating winding form surrounds the primary winding. The winding form is provided with spaced, longitudinally-distributed, radially--extending chambers, the secondary winding being located within these chambers. The thickness of the winding form between the bottoms of the chambers and the primary winding is greatest at the ends of the winding form and become progressively smaller toward the center of the form.
The present invention offers a plurality of advantages with respect to the design, insulation and voltage distribution of the line transformer. In order to obtain a desired high voltage for the picture tube, a pulse voltage of a particular amplitude must be present across the high voltage winding, and with a given primary this determines the number of turns in the winding. In the present invention, the amplitude of the pulse voltage across the high voltage winding is the same as in prior art circuits in which the high voltage winding is directly grounded at one end. However, several advantages are obtained which are not realized with conventional circuits.
Since the first end of the high voltage winding is grounded through the first high voltage rectifier, it is maintained at a voltage having a direct component and an alternating component. An alternating voltage component is also present at the second end of the high voltage winding, this component having the same amplitude and being of opposite polarity from the alternating voltage component present at the first end of the winding. Accordingly, the alternating voltage component is zero at the center of the high voltage winding thereby producing an alternating voltage symmetry in the high voltage winding relative to the primary winding.
In prior art circuits having one end of the high voltage winding directly grounded, the alternating voltage has the required amplitude only at the ungrounded end of the winding. In contrast, in the present invention, the alternating voltages present at both ends of the coil are in phase opposition and at half the amplitude with respect to ground as compared to the alternating voltage at the ungrounded end of the conventional high voltage winding. The amplitude of the maximum alternating voltage is thus divided approximately in half compared to the maximum alternating voltage in the prior art circuit. This symmetry and reduction of voltage compared to the prior art circuit has several advantages.
The maximum amplitude of the alternating voltage is less than in the prior art circuit and therefore the thickness of the insulation between the high voltage winding and the primary winding can be reduced. This results in tighter coupling between the two windings, reduction in the stray inductance and simplifies tuning to the ninth harmonic.
The reduced amplitude of the alternating voltage across the high voltage winding is also beneficial because the capacitive currents flowing between the high voltage and primary windings are reduced in amplitude. In the prior art circuit, these capacitive currents are practically zero at the grounded end of the high voltage winding but increase toward the ungrounded end to a value corresponding to the amplitude of the alternating voltage at that end. In contrast, in the circuit according to the present invention, the amplitude of the capacitive current is zero at the center of the high voltage winding because the amplitude of the alternating voltage at this point is zero. The capacitive currents increase towards the ends of the high voltage winding to approximately equal and opposite values; however, these values are about half the maximum value of the capacitive current in the prior art circuit. Also, the integrated sum of the capacitive reactive currents flowing across the distributed winding capacitances is lower in the circuit according to the present invention than in the prior art circuit.
The fact that the amplitude of the alternating voltage at the center of the high voltage winding is zero can be utilized to advantage in the design of the winding form for the high voltage winding by making the insulating space at the center smaller than at the ends of the high voltage winding. According to one embodiment of the invention, the insulating space between the two windings is determined by the amplitude distribution of the effective alternating voltage across the high voltage winding.
In the present invention, the high voltage winding has about the same alternating voltage load at both ends, and the alternating voltages appearing at these two ends have the same shape and amplitude but are of opposite polarity. Accordingly, the interfering radiation emanating from the line transformer is reduced because the voltages at the ends of the high voltage winding partially cancel each other.
The primary and secondary sides of the transformer each contain only a single winding and are not provided with taps, thereby greatly simplifying the design of the transformer. In particular, this simple design permits fixed coupling and attainment of a low stray inductance for the high voltage winding which enhances tuning to a high harmonic of the frequency of the return sweep oscillation.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a schematic circuit diagram of the invention.
FIG. 2 shows voltage curves for explaining the operation of the circuit of FIG. 1.
FIG. 3 is an embodiment of the coil assembly of the transformer.
FIGS. 4 and 5 illustrate additional embodiments of the chambers of the winding form depicted in FIG. 3.
DESCRIPTION OF THE PREFERRED EMBODIMENTS
FIG. 1 is a schematic diagram of the line end stage of a television receiver which includes a switching transistor 2 having its base connected to an input terminal for switching by a square-wave input signal 1, a transformer 3 having a primary winding 4 and a high voltage secondary winding 5, two high voltage rectifiers 6 and 7, a smoothing capacitor 8, a picture tube 9, a coupling capacitor 10 which also serves as a tangential equalizer and line sweep coils 11. The anode of diode 6 is grounded and its cathode is connected to one end 12 of the secondary winding 5. The anode of diode 7 is connected to the other end 14 of secondary winding 5, its cathode being grounded for alternating voltages by capacitor 8 which is formed essentially by the capacitance of the anode coating of the picture tube 9. With these connections, the two ends 12 and 14 of the secondary winding 5 carry substantially the same load.
Referring to FIG. 2, the diode 6 prevents the return sweep voltage 13a at point 12 from becoming negative by clamping the negative peak of that voltage at ground potential. A direct voltage U
1 is generated at point 12 and also at point 14. Since the winding 5 is inductive, the return sweep voltage 13b at point 14 is of opposite polarity with respect to the voltage 13a at point 12. Thus, the alternating voltage at the center 15 of the winding is equal to zero and the distribution of the alternating voltage about the line 32 is symmetrical with respect to ground.
The voltage present at point 14 is rectified by rectifier 7 so that the voltage U
2 at terminal 16 functions as the anode voltage for the picture tube 9. If the terminal 12 were grounded, approximately the same direct voltage U
2 would be produced at terminal 16 but the advantages of the present invention would not be obtained.
The amplitude of the alternating voltage component across winding 5 differs greatly from one end to the other. That is, the alternating voltage between winding 5 and ground is zero at the center of the winding and reaches maximum values of opposite polarities at the ends 12 and 14. This permits the insulation space between the high voltage winding 5 and primary winding 4 of transformer 3 to be a function of its position along the winding.
Referring to FIG. 3, the structure of transformer 3 is shown in which the primary winding 4 surrounds a core 17 having a longitudinal axis 30. An insulating winding form 18 having a plurality of chambers 20 surrounds winding 4. The high voltage winding 5 comprises partial windings 19 disposed in those chambers 20 designated by the letters B through L, chambers A and M not having windings placed therein.
All of the partial windings 19 lying within the chambers 20 are wound one after another without any interruption of the wire. The wire is fed through slots within the walls forming the chambers 20. That means that all of the partial windings 19 are series-connected without any interruption, and form together the winding 5 of FIG. 1.
The thickness d of the winding form 18 at the bottom of each of the respective chambers 20 is a minimum at the center of the form along radial axis 32 where the amplitude of the alternating voltage is substantially equal to zero, the thickness increasing symmetrically along a parabolic curve toward the two ends of the winding form 18. In an actual embodiment tested, the wall thickness d of chambers A-M had the following values:
| ______________________________________ |
| Chamber d in mm |
| ______________________________________ |
A 2.0 (empty)
B 1.6
C 1.3
D 1.2
E 1.1
F 1.0
G 1.0
H 1.0
I 1.1
J 1.2
K 1.3
L 1.6
M 2.0 (empty)
|
| ______________________________________ |
The wall thickness d, which determines the insulating space between the high voltage winding 5 and the primary winding 4, corresponds to the amplitude of the alternating voltage distribution along the longitudinal axis of the winding form.
Chambers A and M are intentionally not provided with a winding 19. This has the advantage that the space between the first winding in chamber B and the sharp edge of end 21 of primary winding 4 is relatively large, thereby reducing the danger of arcing at the edge of the winding. Similarly, the distance between the winding in chamber L and the edge of end 22 of the primary winding 4 is relatively large to reduce the possibility that arcing will occur at this end of the transformer.
As shown in FIG. 3, the number of turns of the windings 19 in the individual chambers 20 are, in general, not the same. That is, the radial thicknesses of the windings in chambers F, G and H are equal but the thickness of the windings in the chambers on either side of chambers F and H decrease significantly and are at a minimum in chambers B and L, the stray inductance being controlled to permit tuning to a desired harmonic.
If, for example, the winding is distributed so that there are more turns at the center of the winding form 18 where the distance between the high voltage winding 5 and the primary winding 4 is smaller than at the edges, the coupling is closer at the center thereby changing the stray inductance compared to that which would have been obtained with a uniform winding distribution.
It is desirable that the stray inductance of the winding 5 together with all effective capacitances be tuned to a frequency corresponding to the ninth harmonic of the frequency of the line fly back pulse in order to achieve a low value of internal resistance at terminal 16 of the high voltage source. The stray inductance of the winding 5 which is necessary for achieving this resonant frequency can be obtained by a proper distribution of the partial windings 19 within the chambers 20. In particular the stray inductance can be kept low because the distance between the partial windings 19 in the middle region of form 18, i.e. around chamber G can be made very small. This is possible as the value of the ac-voltage in this region corresponding to center 15 in FIG. 2 is zero.
FIG. 4 shows an embodiment of the winding form in which the edges along the bottom of the chamber 20 are rounded so as to have a fluted shape in order to reduce arcing, rounding the circumferential edges reducing the probability that arcing will take place. Moreover, the wire comprising the turns of the high voltage winding can more conveniently be placed in the chambers 20 during winding.
In FIG. 5, the radii or curvature at the two edges of the chambers 20 are different. This configuration is employed for the first and last chambers B and L having a winding 19 placed therein, the edge 23 having the larger radius of curvature being located at the end of the winding form. Thus, a chamber shaped as shown in FIG. 5 would be used for chamber L to reduce the chance of arcing between edge 22 and the coil placed in chamber L. The embodiment of FIG. 5 is preferably provided only for chambers B and L.
It will be understood that the above description of the present invention is susceptible to various modifications, changes and adaptations, and the same are intended to be comprehended within the meaning and range of equivalents of the appended claims.
TELEFUNKEN PALCOLOR 2228 CHASSIS 415A TELEFUNKEN PLL SYNTHESIZER Digital phase control circuit including an auxiliary circuit:m3870
An electronically controllable tuning device includes a voltage controlled oscillator adapted to have an oscillation frequency controlled by a control voltage and simultaneously generate a fundamental wave of a predetermined frequency, a programmable frequency divider for dividing the fundamental wave frequency at a frequency division ratio corresponding to the control of a channel selection means and a phase locked loop adapted to compare the fundamental wave phase with the phase of the output of the programmable divider to generate a comparison output and feeding the comparison output back to the voltage controlled oscillator to control the output frequency of the voltage controlled oscillator. The tuning device further includes means for supplying as a local oscillation signal to an intermediate frequency generating mixer one of higher harmonic wave components of the fundamental wave.
A digital phase control circuit which includes a controllable oscillator, a programmable divider coupled to the oscillator, a reference frequency source, a phase discriminator coupled to the outputs of the programmable divider and reference frequency source and means coupling the output of the phase discriminator to a control input of the oscillator. In addition to these components, an auxiliary circuit is provided which has its input coupled to the output of the phase discriminator and first and second outputs coupled to the reference frequency source and the programmable divider. The auxiliary circuit generates a first signal at the input of the reference frequency source when the phase difference between the signals at the outputs of the programmable divider and the reference frequency source is in one direction and a second signal at the second input of the programmable divider when the phase difference is in the opposite direction.
1. In a digital phase control circuit including a controllable oscillator having a control input; a programmable first divider having first and second inputs, said first input being coupled to the output of said oscillator; a reference frequency source comprising a second divider having an input; a phase discriminator having first and second inputs coupled to the outputs of said programmable first divider and said second divider respectively, said phase discriminator further having output means; and means coupling the output means of said phase discriminator to the control input of said controllable oscillator, the frequency of said oscillator being controlled in a direction determined by the direction of the phase deviation between the signals applied to the first and second inputs of said phase discriminator and compared therein; the improvement comprising:
an auxiliary circuit having input means coupled to the output means of said phase discriminator, a first output coupled to the input of said second divider comprising said reference frequency source and a second output coupled to the second input of said programmable first divider, said auxiliary circuit generating a first synchronizing signal at the input of said second divider when the phase difference between the signals at the ou
tputs of said programmable first divider and said second divider is in one direction and generating a second synchronizing signal at the second input of said programmable first divider when the phase difference between the signals at the outputs of said programmable first divider and said second divider is in the opposite direction thereby setting either said programmable first divider or said second divider, respectively, to a predetermined initial phase position, the divider set to said predetermined initial phase position being maintained in said position until the other divider reaches its predetermined initial phase position.
2. The phase control circuit defined by claim 1 wherein said auxiliary circuit comprises a clock pulse generator for generating a signal at a predetermined interval after generation of a signal at the output of said phase discriminator, an auxiliary circuit output signal being generated at the input of said second divider or at the input of said programmable first divider only if the signal at the output of said phase discriminator is generated for an interval longer than said predetermined interval. 3. The phase control circuit defined by claim 2 wherein the output of said phase discriminator and the output of said auxiliary circuit each comprise a plurality of sequential pulses having a leading edge and a trailing edge, the leading edges of the pulses at the output of said auxiliary circuit occurring later than the leading edges of the corresponding pulses at the output of said phase discriminator, and the trailing edges of the corresponding pulses at both the output of the auxiliary circuit and the output of the phase discriminator coinciding. 4. The phase control circuit defined by claim 2 wherein said clock pulse generator receives counting pulses at a constant frequency, means are provided for releasing said clock pulse generator to count said counting pulses from its predetermined initial position when a signal is generated at the output of said phase discriminator and means are provided for coupling the signal at the output of said clock pulse generator to a disable input thereof to stop said counter. 5. A phase control circuit as defined by claim 4 wherein the output means of said phase discriminator comprises a first output at which pulses appear when the frequency of said oscillator is increasing and a second output at which pulses appear when the frequency of said oscillator is decreasing, and wherein said auxiliary circuit further includes a first gating circuit having first and second inputs coupled to the first and second outputs of said phase discriminator and an output coupled to a reset terminal of said clock pulse generator, second and third gating circuits for coupling the output of said clock pulse generator to the input of said second divider and to the second input of said programmable first divider, respectively, and fourth and fifth gating circuits coupling the first and second outputs of said
phase discriminator to the inputs of said second and third gating circuits.
Description:
BACKGROUND OF THE INVENTION
This invention relates to digital phase control circuits and, in particular, to a phase control circuit which has improved transient response during its readjustment mode.
Digital phase control circuits are known which include a controllable oscillator, a programmable divider, a reference frequency source, a phase discriminator and a lowpass filter or integrating circuit. The output signal of the controllable oscillator is fed to one input of the phase discriminator via the programmable divider and the other input of the phase discriminator receives a signal from the reference frequency source. The low-pass filter circuit derives a control signal from the output of the phase discriminator so as to control the controllable oscillator.
The signals at the output of the phase discriminator have rectangular pulses. The average d.c. voltage of the rectangular pulses is obtained by means of the series-connected filter circuit which provides a setting voltage for the controllable oscillator. The circuit regulates itself in such a way that, in the steady-state, the signals applied to the phase discriminator coincide in frequency and phase.
In order to prevent excessive overshoot of the controllable oscillator, a minimum time constant is required in the filter circuit which may be designed, for example, as an active integrator. This results in a relatively long time constant for the entire system which can be detrimental in many cases. A long time constant may also increase the tendency toward resonance of the entire circuit.
It is an object of the present invention to provide a phase control circuit which is substantially improved with respect to its transient response during readjustment.
SUMMARY OF THE INVENTION
The present invention comprises a digital phase control circuit which includes a controllable oscillator, a programmable divider coupled to the oscillator, a reference frequency source, a phase discriminator coupled to the outputs of the programmable divider and reference frequency source and means coupling the output of the phase discriminator to a control input of the oscillator. In addition to these components, an auxiliary circuit is provided which has its input coupled to the output of the phase discriminator and first and second outputs coupled to the reference frequency source and the programmable divider. The auxiliary circuit generates a first signal at the input of the reference frequency source when the phase difference between the signals at the outputs of the programmable divider and the reference frequency source are in one direction and a second signal at the second input of the programmable divider when the phase difference is in the opposite direction.
Thus, in the present invention, an auxiliary circuit is provided in addition to the components of the prior art phase control circuit. This auxiliary circuit acts selectively on the programmable divider or the reference frequency source to reset the programmable divider or the reference frequency source, respectively, to a predetermined initial phase position at specific points in time. This initiates a comparison which begins at the predetermined initial phase position of the circuit. The comparison process beginning with the return of the predetermined initial position of the programmable divider or of the reference frequency source is repeated continuously. The invention operates such that, during every comparison cycle, a genuine phase or frequency comparison is effected between the two signals present at the phase discriminator. Each time at the start of the comparison cycle, the phase difference is defined as "zero." Therefore, the phase of frequency deviation present at the end of the comparison cycle between the two signals present at the phase discriminator is an exact measure of the phase deviation.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 shows a phase control circuit in accordance with the present invention.
FIGS. 2 and 3 show the output signals of a prior art phase control circuit for both directions of adjustment.
FIG. 4 is a pulse diagram of the signals in a phase control circuit including the features of the present invention for one direction of adjustment.
FIG. 5 shows signals corresponding to FIG. 4 for the other direction of adjustment.
FIG. 6 is a waveform diagram comparing the operation of the circuit with and without the auxiliary circuit of FIG. 1.
FIG. 7 shows an embodiment of the auxiliary circuit of FIG. 1.
FIG. 8 shows a television tuner constructed in accordance with the invention.
DESCRIPTION OF THE PREFERRED EMBODIMENTS
FIG. 1 is a block diagram showing a phase adjustment circuit which includes a voltage controllable oscillator 1 (VCO), a programmable divider 2, a reference source 4, a phase discriminator 3, a coupling circuit 6 and a l
owpass filter and amplifier circuit 5. These components are combined in a known manner to form a control loop. The programmable divider can be set to a selected dividing ratio which determines the initial frequency of the controllable oscillator 1. The programmable divider may also have fixed predividers (not shown) connected between it and the oscillator 1. The reference frequency source 4 includes a quartz oscillator 4a and a series-connected frequency divider 4b having, for example, a fixed dividing ratio. The output signal of the divider 4b is fed to the phase discriminator 3 to provide a reference signal.
Before describing auxiliary circuit 7 of FIG. 1, the operation of the prior art phase control circuit will be explained with the aid of FIGS. 2 and 3; that is, the circuit shown in FIG. 1 without the auxiliary circuit 7 will be described.
The output signal of the programmable divider 2 is shown at the top of FIG. 2. After each passage through the programmable divider 2, a negative pulse 8 appears at the output of this divider and is fed to the phase discriminator 3. In the second line of FIG. 2, the reference signal is shown which is fed to the other input of the phase discriminator 3.
The
phase discriminator 3 has an output 9 at which control pulses appear when the oscillator 1 is adjusted in the upward direction; that is, toward a higher frequency, and an output 10 at which pulses appear for an adjustment in the downward or lower frequency direction. The signals at outputs 9 and 10 are illustrated in the third and fourth lines of FIG. 2. The last line shows a so-called "tristate signal" which is obtained at the output of coupling circuit 6 and which is fed to the lowpass filter 5. The diagram shown in FIG. 2 is based on a so-called Type 4 phase discriminator which is described at page 19 of the book by Horst Geschwinde "Einfuhrung in die PLL-Technik" (Introduction to the PLL Technique), published by Vieweg. Each of the outputs 9 and 10 of the phase discriminator 3 has an associated output in a bistable circuit comprising the phase discriminator. In the illustrated case, the phase discrimin
ator 3 is designed so that the bistable circuits respond to the negative-going edge of the pulse 8 coming from the programmed divider 2. If there is a phase difference between the signals applied to the phase discriminator 3, pulses appear either at the "upward" output 9 or at the "downward" output 10, depending on the direction of the deviation. The bistable circuit associated with the "upward" output can be set by the edges 11 of the reference signal and reset by the pulses 8 coming from tne programmable divider 2. Conversely, the bistable circuit in the phase discriminator associated with the "downward" output can be set exactly oppositely by the pulses 8 coming from the programmable divider 2 and reset by the edges 11 of the reference signal.
FIG. 2 shows the signals for the case where at time t
0 the dividing ratio of the programmable divider 2 is switched to a higher value. Consequently, the frequency of the oscillator 1 is adjusted toward higher frequencies, which can be seen in FIG. 2 in that the pulses 8 at the output of the programmable divider jump toward a lower frequency after a new dividing ratio has been set into the programmable divider and thereafter are brought closer together by the adjustment process. Thus, at an interval indicated by the bracket 12, the frequency of the pulses coincides with the frequency of the reference signals but there still exists a phase deviation between the signals. This deviation can be overcome by temporarily increasing the frequency of the signal of oscillator 1 beyond the desired value. For that reason, the pulses at the "upward" output 9 continue to be generated. The prior art circuit thus exhibits an overshoot which is required by the system.
FIG. 3 is a pulse diagram in which the dividing ratio of the programmable divider 2 of FIG. 1 is set to a lower value at time t
0 . The time at w
hich coincidence with respect to frequency exists for the signals being compared in the phase discriminator is identified by a bracket 13. The operation of the prior art system under these conditions is analagous to the previously described operation under the conditions of FIG. 2.
The auxiliary circuit 7 of FIG. 1 resets the programmable divider 2 or the reference frequency source 4, to its initial position at specific points in time. The auxiliary circuit 7 is controlled by the signals at outputs 9 and 10 of the phase discriminator 3.
FIGS. 4 and 5 show how the auxiliary circuit of FIG. 1 controls the programmable divider 2 and the reference frequency source 4. FIG. 4 illustrates the operation of the circuit including auxiliary circuit 7 for a change in frequency corresponding to FIG. 2 wherein the oscillator frequency increases; that is, changes in the upward direction. It is assumed that the circuit has the same components as the circuits on which FIGS. 2 and 3 are based but that it includes in addition the auxiliary circuit 7.
The synchronizing signal A shown in the last line of FIG. 4 is generated by the auxiliary circuit 7. The synchronizing signal A includes pulses 14 and 17 which are fed to the reset input R of the reference frequency source. At time t
0 , a new dividing ratio is fed into the programmable divider 2 and at time t
1 the oscillator begins to increase its frequency so that the pulses 8 come closer together again. At time t
1 , the pulse 15 is initiated at the "upward" output 9 of the phase discriminator since the edge 11 of the reference signal appears earlier than the next pulse 8 from the programmable divider. The pulse 14 of the synchronizing signal A is derived from the pulse 15.
Pulse 14 is used initially to reset the divider 4b of the reference frequency source 4 which does not generate reference signal pulses as long as pulse 14 is present. At time t
2 , the pulse 15 and the output pulse 14 derived from pulse 15 are terminated. Thus, at time t
2 , the divider of the frequency source 4 is restarted from its basic position.
The frequency divider 4b may be a twelve bit divider consisting, for example, of two type CD4520 integrated circuits manufactured by RCA. This known divider is set to its basic position by a logical reset signal.
After a period T
1 of the reference signal, at time t
3 , a new control pulse 16 starts at the output 9 of the phase discriminator 3 since the edge 11 again appears earlier than the next pulse 8 from the programmable divider. A synchronizing pulse 17 is again generated which sets back the divider 4b of the reference frequency source 4 and stops it.
The adjustment is effected in the above-described manner until at time t
4 the signals being compared in the phase discriminator 3 coincide with respect to frequency and phase. As can be seen from a comparison of FIG. 4 with FIG. 2, this state is attained much faster than in the circuit without the auxiliary circuit 7. The control pulse terminated each time at the end of the comparison cycle provides a precise indication of the frequency deviation of the two signals applied to the phase discriminator, which is not the case in FIGS. 2 and 3.
Upon a change in the frequency of the oscillator in the opposite direction (downward), a synchronizing signal B is generated in the auxiliary circuit 7, as shown in FIG. 5, from the signal at "downward" output 10 of phase discriminator 3. With this synchronizing signal, the programmable divider 2 is controlled rather than the reference source 4 as shown in FIG. 4.
At time t
0 , as in FIG. 3, the dividing ratio of the programmable divider is reduced to correspond to the reduction in frequency of the oscillator 1. This initially effects an increase in the output frequency of the controllable oscillator. The synchronizing signal B is derived from the pulses 18 and 19 at the "downward" output 10 of the discriminator 3. This signal is fed to the load input L of the programmable divider 2. At time t
1 a pulse 8 from the programmable divider starts the pulse 18 at the output 10. The programmable divider is set by the synchronizing pulse 20 derived from pulse 18 and is kept in the initial position until time t
2 . At time t
2 , the edge 11 of the reference signal terminates the pulse 18. At the same time, the programmable divider begins to operate again. At t
3 , the pulse 19 at the output 10 is started because the next pulse 8 appears earlier than the next negative-going edge 11 of the reference signal. The synchronizing pulse 21 derived from pulse 19 again sets the programmable divider 2 and holds it in its initial position. At time t
4 the programmable divider 2 is released again and
the process continues.
The programmable divider 2 is a known component. For example, four type 74 LS169 integrated circuits manufactured by National Semiconductor may be used in series as a fourteen bit presettable down counter.
As is evident from the explanation of FIGS. 4 and 5, the reference frequency source 4 is controlled by the auxiliary circuit in one direction and the programmable divider 2, located between the oscillator 1 and the discriminator 3, in the other direction. The influenced circuit is controlled in accordance with the signals appearing at the output of the discriminator 3, which correspond to the phase or frequency error, so that at the beginning of each comparison cycle the phase error is assumed to be zero. In this way, adjustment of the circuit beyond the desired value is avoided. Thus, the described phase control circuit, including the auxiliary circuit 7, has very short transient periods.
FIGS. 4 and 5 show that the rising edge of the synchronizing signals A and B are shifted by the time τ with respect to the associated output signal of discriminator 3. By providing a predetermined delay period τ, the auxiliary circuit 7 is made effective for only a certain minimum width of the pulses of the output signal from discriminator 3. If the pulses at outputs 9 and 10 of the discriminator 3 fall below this minimum width, no synchronizing signals A or B are generated any longer. The circuit then operates in the customary manner, as described in connection with FIGS. 2 and 3. The delay period is advantageously selected to be greater than one period of the frequency of the reference oscillator so that the auxiliary circuit will not respond to the non-transient state.
If such a delay period is provided, the control circuit will be brought into a state, by means of the auxiliary circuit 7 provided to avoid overshooting, in which the signals present at the phase discriminator coincide with respect to frequency as well as phase. Then the auxiliary circuit 7 is no longer effective.
FIG. 6 shows the result obtained with the auxiliary circuit 7 by illustrating the control signal for oscillator 1. The top portion of FIG. 6 shows the signal obtained when an auxiliary circuit was used which operates in the manner described above under conditions of increasing frequency. The signal at the bott
om of FIG. 6 was obtained when the same circuit was used without auxiliary circuit 7. It can be seen that the auxiliary circuit 7 resulted in a significant improvement in the transient behavior.
FIG. 7 shows an embodiment of the auxiliary circuit 7 of FIG. 1. The auxiliary circuit includes a counter 22 and logic gates 23 to 27, the counter generating the fixed delay period λ. A typical counter which may be used for this purpose is the type CD4520 manufactured by RCA. The signals at the outputs 9 and 10 of the phase discriminator 3 are fed through an AND gate 23 to the reset input of the counter 22. The clock pulse input of the counter 22 receives, via an input terminal 30, counting pulses at a frequency of, for example, 1 MHz. If no pulse arrives from the outputs 9 and 10 of the phase discriminator, the reset input receives a reset signal and the clock pulses at the clock pulse input of the counter 22 are ineffective. The output Q
n of the n
th stage of the counter 22 is connected with a disable input D of the counter. That is, if the counter state Q
n is reached, the counter stops itself. The synchronizing signals A and B are also derived from output Q
n via gates 25 and 27. A signal is fed via inverters 24 and 26, to the gates 25 and 27 which act as gating circuits so as to indicate which one of the two gates 25 and 27 is to be enabled for the signal coming from output Q
n . Gates 25 and 27 therefore control whether the programmable divider 2 or the reference frequency source 4 of FIG. 1 receives a synchronizing signal.
With reference to FIGS. 4 and
5, the circuit in FIG. 7 operates as follows: The pulse 15 in FIG. 4 is present at the input 9 and enables gate 27 via inverter 26 to provide a synchronizing signal. However, no pulse appears at output 29 because the output Q
n of the counter 22 does not furnish a signal. Pulse 15 cancels the reset signal of counter 22 and counting pulses from input 30 are counted into the counter. After a delay period λ a signal jump appears at the output Q
n , in accordance with the clock pulse frequency and the number of stages in the counter, which stops the counter 22 through the disable input. The change of signals at the output Q
n also changes the logic state at the upper input of gate 27 so that the pulse 14 of FIG. 4 is formed. As soon as pulse 15 in FIG. 4 is completed, the AND condition for gate 27 is no longer met so that the pulse 14 is terminated simultaneously with pulse 15. The termination of pulse 15 causes the counter 22 to be reset to its starting position and held in that position.
When there is a pulse at input 10 of the circuit of FIG. 7, the circuit operates in a corresponding manner with the difference that gate 25 is enabled instead of gate 27. In this case, the synchronizing signal B is formed at output 28 and used to control the programmable divider 2. By selecting the frequency of the counting clock pulse at the input 30 it is possible to preselect the delay period λ.
It is also possible to obtain the delay period λ by means of circuit elements which operate in a different manner. For example, the delay of a plurality of series-connected gates (e.g., inverters) can be utilized.
FIG. 8 shows the complete circuit diagram of a tuner embodying the features of the present invention. At the top left of FIG. 1, block 31 is a tuner including the VCO 1. The signal from the VCO 1 travels through a predivider 32 included in the tuner to the programmable divider 2. At the beginning of a dividing cycle, the programmable divider is set to the preprogrammed value via a "load" input L and is then pulsed until it reaches the value zero. When it reaches the value zero, the load input receives a new charging pulse via a gate 33 with which the starting position of the programmable divider 2 is reset. The charging pulse of the programmable divider is fed to the input 35 of a phase discriminator 3 which is shown in dashed lines in FIG. 8. The other input 34 of the phase discriminator 3 receives a signal from the reference divider 4. The phase discriminator 3 which operates in a known manner, includes a plurality of gates.
At the lower right of FIG. 8, the coupling circuit 6 is shown. The auxiliary circuit 7 which has already been described in connection with FIG. 7 is shown in outline in FIG. 8. The synchronizing signal A is fed to the reset input of the reference divider 4 and the synchronizing signal B is fed to gate 33.
The auxiliary circuit 7 is also connected to a lock indicator which includes a counter 36, an AND gate 37 and an inverter 38. The counter 36 is set back with each synchronizing signal A and B via a reset input. Clock pulses at a relatively low frequency are fed to the clock pulse input of the counter 36 via an AND gate 37. These clock pulses are obtained from the output of the reference divider 4. From an output Q
p , a lock signal is derived. This lock signal appears only if no synchronizing signal appears for a relatively long period of time. The supply of clock pulses through gate 37 is blocked as soon as the lock signal appears because of the feedback of the lock signal via an inverter 38. The lock signal remains in effect until a new synchronizing signal is formed.
The lower left of FIG. 8 shows the filter circuit 5 which includes an operational amplifier 39.
It will be understood that the above description of the present invention is susceptible to various modifications, changes
and adaptations, and the same are intended to be comprehended within the meaning and range of equivalents of the appended claims.
TELEFUNKEN PALCOLOR 2228 CHASSIS 415A PLL MICROCOMPUTER Frequency synthesizer tuning system for television receivers:TFK u3870M
"
A method for tuning a television receiver having automatic frequency
control to the carrier frequency of a selected broadcast channel
with an associated channel number including generating a variable
frequency signal by means of a local oscillator, generating a
reference frequency signal by means of a reference oscillator, and
generating a local oscillator correction signal for matching an
intermediate frequency signal derived from said local oscillator
signal and the carrier frequency signal with a predetermined nominal
intermediate frequency signal, said method being characterized by
the use of a microcomputer and comprising:
generating binary
signals representing first and second digital tune words, said
digital tune words representing a selected channel;
storing said first and second digital tune words in a first data memory in said microcomputer;
reading
said first and second digital tune words from said first memory and
generating a divided-down local oscillator frequency by the use of
said first digital tune word and a divided-down reference oscillator
frequency by the use of said second digital tune word;
comparing
said divided-down local oscillator and reference frequencies and
generating a control signal representative of the difference in
frequency of said divided-down local oscillator and reference
frequencies;
coupling said control signal to said local
oscillator for causing it to be locked to the frequency of said
received carrier signal;
mixing the local oscillator frequency signal and the carrier frequency signal to generate an intermediate frequency signal;
comparing
said intermediate frequency signal with said predetermined nominal
intermediate frequency signal and providing a tuning voltage to said
microcomputer, said tuning voltage being indicative of the
magnitude and direction of a tuning error between said intermediate
frequency signal and said predetermined nominal intermediate frequency
signal;
incrementally adjusting the reference oscillator
frequency by means of a tuning signal provided to said reference
oscillator by said microcomputer in response to said tuning voltage;
detecting
when the incrementally changing, divided-down reference oscillator
frequency causes the intermediate frequency signal to pass said
predetermined nominal intermediate frequency signal; and
incrementally
stepping the divided-down reference oscillator frequency back a
predetermined number of steps following the passage of said
predetermined nominal intermediate frequency signal by said
intermediate frequency signal in tuning said television receiver to
the selected channel.
"
A
television tuning system employs a frequency synthesizer system for
establishing the tuning of the receiver. A programmable frequency
divider counter is connected between the output of a reference
oscillator and a phase comparator to which the output of the local
oscillator in the tuner also is applied. The phase comparator output
provides a tuning voltage for controlling the tuning of the local
oscillator. A microprocessor is used to control the count of the
programmable frequency divider and initially to set a count
corresponding to the selected channel in a counter connected between the
output of the local oscillator and the phase comparator. The tuning
consists of three discrete time periods. First, a settling time to
allow channel change transients to settle; second, a short period of
forced search at a relatively rapid rate to insure proper tuning; and
third, a slower rate of step-by-step correction to accomodate for
station drift and the like during reception. This third time period is
initiated either by the passage of a fixed length of time following
the start of the forced search period or by sensing a preestablished
number of changes of state in the output of the frequency
discriminator during the forced/search period.
1.
A tuning system for the tuner of a television receiver capable of
receiving a composite television signal and including frequency
discriminator (AFT) circuit means, said system including in
combination:
a reference oscillator providing a reference signal at a predetermined frequency;
a
local oscillator in the tuner providing a variable output frequency
in response to the application of a control signal thereto;
a
programmable frequency divider means having first and second inputs
coupled respectively to the output of said reference oscillator and said
local oscillator for producing signals on first and second outputs
having frequencies which are a programmable fraction of the frequency
of the signals applied to the inputs thereto;
phase comparator
means having one input coupled with the first output of said
programmable frequency divider means and having another input coupled
with the second output of said programmable frequency divider means for
developing a control signal and applying such control signal to said
local oscillator for controlling the output frequency thereof;
counter
circuit means coupled with said programmable frequency divider means
for initially setting said divider means to a predetermined division
ratio and operating to change the programmable fraction of division
thereof in accordance with changes in the count in said counter
circuit means;
control circuit means coupled with the output of
said frequency discriminator means and further coupled with said
counter circuit means for causing said counter circuit means to count at
a first rate in a predetermined direction determined by the state of
the output signal from said discriminator means in the absence of a
predetermined signal output from said frequency discriminator means
until a predetermined maximum count is attained, thereupon resetting
said counter circuit means to a count which is a predetermined amount
less than said maximum predetermined count and continuing to count at
said first rate in the same predetermined direction from said new
count to continuously change the programmable fraction of said
frequency divider means in accordance with the state of operation of
said counter circuit means, said control means operating in response
to said predetermined signal output from the frequency discriminator
means for terminating operation of said counter circuit means; and
further
means for terminating operation of said counter circuit means at
said first rate and causing operation thereof at a second slower rate.
2.
The combination according to claim 1 wherein said further means
includes timing means initiated into operation simultaneously with the
setting of said divider means to a predetermined division ratio, and
after a predetermined time interval said timing means producing an
output signal applied to said counter circuit means to cause operation
thereof to take place at said second slower rate.
3. The combination according to claim 1 wherein
said counter circuit means includes a reversible digital counter
coupled with said programmable frequency divider, means and said
control circuit means causes said counter circuit means to count in
said predetermined direction when the output of said frequency
discriminator is of a first state and to count in the opposite
direction when the output of said frequency discriminator is of second
state; and said further means comprises means coupled with the
output of said frequency discriminator and with said counter circuit
means to take place at said second slower rate in response to a
predetermined number of changes of state of frequency discriminator.
4. The combination according to
claim 3 further including means responsive to the selection of a new
channel in said television receiver for resetting said further means to
an initial condition of operation.
5. The combination according to claim 4 wherein said further
means comprises a search termination counter means operative to
provide an output signal applied to said counter circuit means in
response to a count thereby of a predetermined number of changes of
state of said frequency discriminator to cause said counter circuit
means to be operated at said second slower rate.
Description:
BACKGROUND OF THE INVENTION
Both
of the above mentioned patents are directed to frequency synthesizer
tuning systems for use with television receivers to enable operation
of the receivers with minimal viewer fine tuning adjustments. By the
utilization of the frequency synthesizer tuning systems of these
patents, the fine tuning adjustment which is necessary with conventional
types of television receiver tuning systems has been substantially
eliminated. The system employed in the '953 patent permits utilization
of a frequency synthesizer tuning system which correctly tunes to a
desired television station or channel even if the transmitted signals
from that station are not precisely maintained at the proper
frequencies. The '535 patent is directed to a signal seek tuning system
adaptation of the frequency synthesizer tuning system of the '953
patent which still permits implementation of all of the desired
wide-band pull in range of the frequency synthesizer system of the '953
patent.
The systems of the foregoing patents operate
effectively to correct automatically for frequency offsets in a
frequency synthesizer tuning system without affecting the operation of
the conventional frequency synthesizer used in the system. The
systems of these patents are in widespread use commercially and
permit direct selection, with automatic fine tuning adjustment, of
any desired VHF channel which the viewer wishes to observe. In
addition, the signal seek adaptation disclosed in the '535 patent
couples all of the advantages of the frequency synthesizer tuning
system of the '953 patent with the desirability of providing
bidirectional signal seek operation.
While the systems
disclosed in the foregoing patents operate in a highly satisfactory
manner to accomplish the desired results of accurate tuning without
the necessity of fine tuning adjustments, the circuitry for
accomplishing the desired results is somewhat complex. It is
desirable to reduce the circuit complexity and the number of signal
detectors for accomplishing these results without compromising the
accuracy of operation of the system.
SUMMARY OF THE INVENTION
Accordingly, it is an object of this invention to provide an improved tuning system for a television receiver.
It
is an additional object of this invention to provide an improved
frequency synthesizer tuning system for a television receiver.
It
is another object of this invention to provide an improved frequency
synthesizer tuning system for a television receiver which includes a
provision for adjusting the synthesizer loop for frequency offsets in
the received signal with a minimum number of signal detectors.
It
is a further object of this invention to tune the local RF
oscillator of a television receiver to the correct frequency for a
selected channel with a frequency synthesizer tuning system, and
automatically to change the reference frequency of the synthesizer
system, or adjust the count of a programmable divider that produces a
signal that divides the frequency of the local oscillator of the
tuner, if the AFT signal produced by the AFT frequency discriminator
of the receiver is outside a predetermined range corresponding to
correct tuning.
It is still another object of this invention to
provide an improved frequency synthesizer tuning system for a
television receiver which operates to adjust the synthesizer loop for
frequency offsets in the received signal over a relatively wide pull
in range in response to the output of the receiver frequency
discriminator by changing the division ratio of a programmable
frequency divider in the reference oscillator leg or local oscillator
leg of the synthesizer loop at a first relatively high rate from an
initial nominal value to a pre-established maximum in one direction,
and then resetting the division ratio to a second nominal value once
the maximum is reached and continuing to incrementally change the
division ratio in the same direction from the second nominal value
until a properly tuned condition is indicated by the output of the
receiver AFT frequency discriminator, followed by control at a lower
rate of operation to maintain tuning during transmitting station
drifts.
In
accordance with a preferred embodiment of this invention, the
frequency synthesizer tuning system for a television receiver includes
a stable reference oscillator and a voltage controlled local
oscillator in the tuner. A programmable frequency divider is connected
between the output of the reference oscillator and one input to a
phase comparator, the other input of which is supplied by the output
of the local oscillator. The output of the phase comparator then
comprises a control signal which is supplied to the local oscillator
to control the frequency of its operation.
A counter circuit
is connected to the programmable frequency divider for initially
setting the divider to a predetermined division ratio upon selection
of a desired channel by the viewer. The counter then operates to
change the programmable fraction of the division ratio at a first
relatively high rate in a direction controlled by the output from the
receiver picture carrier discriminator in the absence of a
predetermined signal output derived from the discriminator. A control
means causes the counter circuit to count in this direction until it
is determined that a station is tuned or a predetermined maximum
count is attained if no station is correctly tuned, thereupon
resetting the counter circuit to a count which is a predetermined
amount less than the maximum predetermined count. Counting is
continued in the same predetermined direction from the new lesser
count to continuously change the programmable fraction of the
frequency divider in accordance with the state of operation of the
counter.
The
high rate operation of the counter is terminated by the control
means in response to a predetermined signal from the output of the
discriminator, indicating that a station is correctly tuned, or after a
fixed time-out interval; so that the system automatically adjusts
for frequency offsets of the received signal which otherwise would
cause the station to be mistuned if a conventional frequency
synthesizer tuning system were used. After termination of the high
rate operation of the counter, it is switched to a lower rate
operation for maintaining tuning during transmitting station drifts.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a block diagram of a television receiver employing a preferred embodiment of the invention;
FIG. 2 is a detailed block diagram of a portion of the circuit of the preferred embodiment shown in FIG. 1;
FIG. 3 is a detailed circuit diagram of a portion of a circuit shown in FIG. 1;
FIG. 4 is a flow chart of the control sequence of operation of the circuit shown in FIG. 1 and 2; and
FIG.
5 shows a waveform and time/frequency chart, respectively, useful in
explaining the operation of the circuit shown in FIGS. 1, 2 and 3.
DETAILED DESCRIPTION
Referring
now to the drawings, the same reference numbers are used throughout
the several figures to designate the same or similar components.
FIG. 1 is a block diagram of a television receiver, which may be a black and white or color television receiver. Mo
st
of the circuitry of this receiver is conventional, and for that
reason it has not been shown in FIG. 1. Added to the conventional
television receiver circuitry of FIG. 1, however, is a frequency
synthesizer tuning system, in accordance with a preferred embodiment
of the invention, which is capable of automatically changing the
reference frequency when a frequency offset exists in the received
signal for a particular channel.
Transmitted composite
television signals, either received over the air or distributed by
means of a master antenna TV distribution system, are received by an
antenna 10 or on antenna input terminals to the receiver. As is well
known, these composite signals include picture and sound carrier
components and synchronizing signal components, with the composite
signal applied to an RF and tuner stage 11 of the receiver. The stage
11 includes the conventional RF amplifiers and tuner sections of the
receiver, including a VHF oscillator section and a UHF oscillator
section. Preferably, the UHF and VHF oscillators are voltage
controlled oscillators, the freuency of operation of which are varied
in response to a tuning voltage applied to them to effect the
desired tuning of the receiver.
The output of the RF and tuner
stages 11 is applied to the remainder of the television receiver 14,
which includes the IF amplifier stages for supplying conventional
picture (video) and sound IF signals to the video and sound processing
stages of the receiver 14. The circuitry of the receiver 14 may be
of any conventional type used to separate, amplify and otherwise
process the signals for application to a cathode ray tube 16 and to a
loudspeaker 17 which reproduce the picture and sound components,
respectively, of the received signal.
The
receiver 14 also includes a conventional AFT or automatic fine
tuning discriminator circuit and additionally may include a synch
separator circuit for producing an output in response to the presence
of vertical synchronizatin pulses, a picture carrier detection
circuit, and an automatic gain control (AGC) amplifier. Outputs
representative of these sensor components are shown as being coupled
over a group of lead 20 to sensory circuitry 22, which in turn
couples outputs representative of the operation of these various
sensor circuits to a microprocessor unit 23 for controlling the
operation of the microprocessor unit.
The microprocessor unit 23
is utilized in the system of FIG. 1 for controlling the operation of
a frequency synthesizer tuning system capable of automatic offset
correction. When the viewer desires to select a new channel, he enters
the desired channel number into a channel selection keyboard 25.
There are a number of different keyboards which may be employed to
accomplish this function, and the particular design is not important
to this invention. The channel selector keyboard 25 also may include
switches or keys for initiating a signal seek function in either the
"up" or "down" direction.
Information represented by the
selection of channel numbers on the keyboard 25 is supplied to the
microprocessor unit 23 which provides output signals over a
corresponding set of leads 27 to the tuners (local oscillators) 11 to
effect the appropriate band switching control for the tuners 11 in
accordance with the particular channel which has been selected. In
addition, the keyboard 25, operating through the microprocessor unit 23,
provides output signals which operate a channel number display 29 to
provide an appropriate display of the selected channel number to the
viewer.
The microprocessor M3870 unit 23 also processes the
signals which are used to operate the channel number display 29
through a multiplexing circuit operation to decode the selected
channel number into a parallel encoded signal. This signal is applied
to corresponding inputs of the count-down counter or programmable
frequency divider 31 to cause the division number of the divider 31
to relate to the divided down frequency of the tuner local
oscillators connected to the input of the divider 31 through a
prescaler divider circuit 32 to the frequency of the reference
oscillator 34. Thus, the division number or division ratio of the
local oscillator frequency obtained from the output of the
programmable divider 31 is appropriately related to the frequency of
the reference crystal oscillator 34.
The
output of the oscillator 34 also is applied through a countdown
circuit or programmable frequency divider 35. Conventional frequency
synthesizer techniques are employed; and the microprocessor unit 23
automatically compensates, through appropriate code converter
circuitry, for the non-uniform channel spacing of the television
signals. It has been found most convenient to cause the programmable
frequency divider 31 to divide by numbers corresponding directly to
the oscillator frequency of the selected channel, for example, 101,
107, 113 . . . up to 931.
In accordance with the time division
multiplex operation of the microprocessor 23, the count of the
programmable frequency divider 35 initially is adjusted to a fixed
count by the application of appropriate output signals from the
microprocessor unit 23 to a point selected to be at or near the
mid-point of the operating range of the programmable frequency divider
35. Thus, the output of the divider 35 is a stable reference
frequency (because the input is from the reference crystal oscillator
34) which is used to establish initially and to maintain tuning of
the receiver to the selected channel.
The output of the
programmable divider 35 is applied to one of two inputs of a phase
comparator circuit 37. The other input to the phase comparator
circuit 37 is supplied from the selected one of the VHF or UHF
oscillators in the tuner stages 11 through the programmable frequency
divider 31. The phase comparator circuit 37 operates in a
conventional manner to supply a DC tuning control signal through a
phase locked loop filter circuit 39 and over a lead 40 to the
oscillators in the tuner system 11 to change and maintain their
operating frequency.
With the exception of the use of the
microprocessor unit 23, the operation of the system which has been
described thus far is that of a relatively conventional frequency
synthesizer system incorporated into a television receiver. This system
is similar to the system of the '953 patent. As in the system of
that patent, the system shown in FIG. 1, when the transmitted station
or station received on a master antenna distribution system provides
the station or channel signals at the proper frequency, operates as a
relatively conventional frequency synthesizer system. If, however,
there is a frequency offset in the received signal to cause the
carrier of the received signal to be displaced from the frequency
which it should have to some other frequency, it is possible that the
system would give the appearance of mistuning to the received
station. The microprocessor 23, operating in conjunction with the
sensory circuitry 22, is employed in conjunction with the countdown
or programmable frequency divider circuit 35 to eliminate this
disadvantage and still retain the advantages of frequency synthesizer
tuning.
Reference now should be made to FIG. 2 which shows details of t
he
interface between the keyboard 25, the microprocessor unit 23, and
the circuitry used in the frequency synthesizer portions of the
system. A commercially available microprocessor which has been used
for the microprocessor 23, and which forms the basis for the
diagramatic representation of the microprocessor in FIG. 2, is the
Matsushita Electronics Corporation MN1402 four-bit single-chip
microcomputer. This microcomputer has two, four-bit parallel input
ports labeled "A" and "B". In addition, three output ports, a five-bit
output port "C" and two four-bit output ports "D" and "E" are
provided. The internal configuration of the microcomputer 23 includes
an arithmetic logic unit (ALU), a read only memory (ROM) for storing
instructions and constants, and a random access memory (RAM) used for
data memory, arranged into four files, each file containing 16
four-bit words. These words are selected by X and Y registers and this
memory is used, for example, for timers, counters, etc., and also is
used to hold intermediate results. To facilitate an understanding of
the operation of the system, a portion of this memory is shown in
FIG. 2 as a clock 81 and a reversible counter 82 connected between
the "B" input port and the "D" output port. The microcomputer 23 is
programmed to permit it to operate in conjunction with the remainder
of the circuits shown in FIG. 2. The programming techniques are
standard, and the microcomputer 23 itself is a standard commercially
available circuit component.
There are several system parameters
that must be selected in the operation of the system shown in FIG.
2. The selection of the nominal frequency of the two signals that
feed the phase comparator circuit 37 is an example. Channel selection
is provided by changing the frequency division ratio of the selector
counter 31 which divides the local oscillator signal after this
signal is passed through a prescaler circuit 32 and a divide-by-two
divider circuit 41. The nominal frequency from the programmable
frequency divider 31 (selector counter) is selected so that the local
oscillator (tuner) 11 can be set exactly on frequency for all
channels.
Since
the frequency divider 31 is able to divide only by integer numbers,
one distinct frequency possibility in the range of one KHz is
obtained, another in the range of two KHz, etc. A choice must be made
as to which of these values is optimum. Each value yields the
nominal frequency of all of the 82 channels by simply multiplying by
an appropriate integer for each channel. To simplify the phase locked
loop filtering problem by the filter 39, it is desirable that the
frequencies of the signals supplied to the phase comparator 37 are as
high as possible. This permits rapid acquisition of a new channel
along with a very clean DC control signal to adjust the local
oscillator. A trade-off for this, however, must be made to permit
fine tunning adjustment of the local oscillator automatically to
correctly tune in stations which are off their assigned frequency, or
to manually provide this feature, if desired. The two-speed
operation of the system in accordance with the present invention
allows a better trade-off to be made by allowing rapid acquisition
and then a slower speed for precise tuning.
A compromise
solution which is utilized in the circuit of FIG. 2 is to cause the
frequency division chain from the local oscillator 11 in the tuner to
the phase comparator 37 to be composed of the fixed divide-by-256
prescaler 32, and a fixed divide-by-4 division, which is accomplished
by the divider 41 at the input of the counter 31 and a second
divider 42 at the output of the counter 31. The variable frequency
divider counter 31 then is loaded by means of three latch circuits
44, 45 and 46 at an appropriate time by the time division multiplex
operation of the microcomputer 23 and a number that programs the
programmable frequency divider counter 31 to divide by the numerical
value of the frequency of the local oscillator in MHz for the channel
selected. For example, if the receiver is to be tuned to channel 2,
which has a nominal local oscillator frequency of 101 MHz, the
programmable frequency divider 31 is set to divide by 101. If the
receiver is to be tuned to channel 83, which has a nominal local
oscillator frequency of 931 MHz, the programmable frequency divider 31
is set to divide by 931. In both cases, the variable divider 31
produces a 1 MHz signal. However, because of the fixed divide-by-256
and the two fixed divide-by-two dividers in series with the
programmable divider 31, an output frequency of 976.5625 Hz is
supplied from the output of the divider 42 to the upper input of the
phase comparator 37.
The
division ratio of the selector counter 31 is established by
appropriate output signals from the latch circuits 44, 45 and 46, as
mentioned above. The initial operation for changing, or maintaining,
the division ratio of the divider 31 is established by an entry of the
two digits of the selected channel number in the keyboard 25. The
microcomputer 23 operates as a time division multiplex system for
continuously monitoring the input ports and the output ports to control
the operation of the remainder of the system. The selection of the
two digits of the desired channel number is affected by a time
division multiplex iscanning of the outputs of the D output port of
microcomputer 23 and providing that information at the A input port.
From here the information is translated again to the D output ports to
the appropriate drivers of the channel number display circuit 29 and
to the latches 44, 45 and 46, and to a pair of similar four bit
latches 49 and 50 which control the divider ratio of the counter 35.
Although
the D output ports of the microcomputer 23 are connected in common
to all of these various portions of the circuit, the selection of
which of the latches are enabled to respond to the particular output
signals appearing on the D output ports at any given time is effected
through the C and E output ports of the microcomputer 23 in a time
division multiplex fashion. A decoder circuit 52, connected to the
lowermost three outputs of the E output port of the microcomputer 23,
is used to apply unique decoding signals at different times in the
time division multiplex sequence of operation of the microcomputer 23
to the five latch circuits 44, 45, 46, 49 and 50, respectively. At
any given time in the sequence, only one of these latch circuits is
enabled for operation. A latch load signal is applied from the upper
output (EO3) at each cycle of operation of the signals appearing on
the E output port to set the latch circuit which is enabled by the
output of the decoding circuit 52 with the data appearing on the
other inputs to the latch circuit. This data simultaneously appears
on the four outputs of the D output port of the microcomputer 23.
Thus,
in rapid sequence, the latch circuits 44, 45 and 46 are set to store
the division number corresponding to the selected channel entered
onto the keyboard 25, and the latch circuits 49 and 50 are each
operated to set the programmable divider reference counter 35 to a
center or nominal count, which is always the same upon the selection
of a new channel on the keyboard 25. Similarly, the two right-hand
outputs of the C output port (CO6 and CO5) enter the two digits of
the selected channel number in the drivers of the display circuit 29
at the proper time in the binary encoded sequence when these digits
appear on the four-bit binary encoded representation of the D output
port. This results in a visual display of the channel number
selected.
In addition to the selection of a channel number
directly by the keyboard 25, the keyboard also may include an
additional switch 56, which is scanned in the time division multiplex
sequence to determine if the receiver is placed in a "seek" mode of
operation (when the signal seek capability is incorporated into such a
receiver). Operating in conjunction with the signal seek switch 56
are a pair of "up" and "down" seek direction input switches shown
with a graphic representation of the seek directions on the keyboard
25. A further provision is provided by two keys labeled "U" and "D",
which are used for "manual" fine tuning of the receiver in the "up"
or "down" directions depending upon which of the two keys U or D has
been operated. The keyboard 25 includes one additional switch 58
which may be used to disable the automatic fine tuning (AFT) portion
of the circuit by rendering the microcomputer insensitive to the
signal output from the AFT circuit, in a manner described more fully
subsequently.
As is apparent from the foregoing, the
microcomputer 23 provides the intelligence, decision making, and
control for the system operation. It is a complete self contained
computer. The decisions or signal inputs upon which the microcomputer
23 bases its operation include, in addition to the inputs from the
keyboard 25, inputs on sensory inputs into the B input port and into
the SNS1 and SNS0 inputs as shown in FIG. 2. These input signals are
used to provide an indication to the microcomputer 23 of the presence
or absence of a received signal; and if the presence of such a
signal is indicated, the inputs provide a further indication of the
accuracy of the tuning of the receiver to that signal. If the system
is being operated solely in a manual mode of operation (AFT switch 58
open), the microcomputer 23 disregards all of this sensory information
and tunes to the frequency allocation of the channel selected in the
manner described above. The system will stay tuned to this
condition, operating as a conventional frequency synthesizer, whether
or not a station is present in the received signal.
When
the system is placed in its automatic mode of operation (similar to
the mode of operation of the above mentioned '953 patent), the
counter 82, integrally formed as part of the microcomputer 23,
continuously adds or subtracts one number at a time from the nominal
value or programmable division fraction entered into the programmable
frequency divider 35 at the outset of each new channel number
selection when frequency offset (mistuning) is present. The counter
82 is driven at a relatively high counting rate by clock pulses from
the clock 81 during this initial or forced search mode of operation.
Thus, automatic offset correction is provided for any channel which
is off its assigned frequency. The offset correction automatically
adjusts the frequency of the local oscillator by changing the
division ratio of the signal from the reference oscillator 35 applied
to the lower input of the phase comparator 37. By doing this, the
output of the phase comparator 37 applied to the local oscillator 11
varies to cause the oscillator to be tuned in the proper direction to
compensate for the transmitting station mistuning.
When the
system is operating in its automatic mode of operation, the
microcomputer 23 responds to the sensor information applied to it on
its B input ports and on the S1 input port shown in FIG. 2. These
inputs are obtained from the various outputs of the operational
amplifiers shown connected to the corresponding input ports in the
detailed circuit of FIG. 3. Depending upon whether the receiver is
provided with a signal seek feature or not, one or more of the
sensory inputs of the circuit of FIG. 3 are used. The s
ystem
shown in the drawings has a capability of correcting for frequency
offsets larger than 1.5 MHz on channels 2 and 7 and approximately 2
MHz on channels 6 and 13. The remainder of the channels have a range
between these two values.
If the receiver is not tuned
properly, the micromputer 23 executes the localized search of the
tuning range mentioned above. Since there is a necessary settling
down time for the tuning of a television receiver immediately
following selection of a new channel, a time interval of 250
milliseconds has been selected to prevent any localized search or
offset frequency correction until the expiration of this "settling
down" time period. If, at the end of this 250 millisecond time
interval, a properly tuned station is present, this is indicated by
the sensory outputs from the television receiver and no localized
search is effected to change the division ratio or programmable
divider count in the reference counter 35 for a system that also has
signal seek.
A system with no signal seek capability is
described later that requires less sensory input but which uses a time
period where a forced search is required directly after the settling
time interval.
Upon
termination of the 250 millisecond settling down period, the
microcomputer 23 is rendered responsive to the sensory input signals on
its sensory input signal ports. In the simplest form, only the output
of the frequency discriminator 60 (FIG. 3) applied to three
comparators 61, 62 and 63 is used to provide the necessary tuning
information to the microcomputer 23. The outputs of these comparators
are applied to the B12 and B11 inputs of the microcomputer.
The
comparator 61 simply is a conventional comparator for determining
whether or not the output of the frequency discriminator is positive
or negative, as indicated in the upper waveform of FIG. 5. The
comparators 62 and 63 are each adjusted with appropriate reference
input levels to provide a narrow window centered about the center
tuning frequency (fc) of the receiver. If the tuning of the receiver,
as indicated by the output of the frequency discriminator 60, is
outside this window on either side of the central axis shown in FIG.
5, one output condition is indicated on the input terminal B11 of the
microcomputer. Only when the tuning frequency is within the tuning
window, indicative of a properly tuned receiver, is the appropriate
input applied to the microcomputer input terminal B11. This input
overrides any other input that may be present on the input terminal
B12 and is indicative of a properly tuned receiver. The input from the
frequency discriminator 60, as applied to the microcomputer on its
input port B12, is used to determine the direction of operation of the
counter 82 of the microcomputer for the localized search count
signals applied to the latch circuits 49 and 50 to change the count of
the reference programmable divider counter 35 on a step-by-step
basis.
The lower graph of FIG. 5 plots the relative frequency of
the local oscillator 11 to the received signal frequency with
respect to time. The various arrows are used to indicate the manner
of operation of the counter 82 in the microcomputer 23 in conjunction
with the reference counter 35 for adjusting for any mistuning
conditions which may exist after the initial station selection has
been effected in the manner described above.
If the receiver is
properly tuned, the outputs from the comparators 62 and 63 of FIG. 3
which are combined together and applied to the input port B11 of the
microcomputer 23, provide an indication that the tuning is within
the properly tuned center frequency window. As a consequence, no
further operation of the microcomputer to change any of the outputs
applied to the latch circuits 49 and 50 for the duration of this
condition is effected. On the other hand, if the receiver is mistuned
on either side of the proper tuning frequency, the various operating
characteristics shown in FIG. 5 are effected.
Assume initially
that the receiver is capable of making tuning adjustments over a
range of fc plus Δf to fc minus Δf, as indicated in the top waveform
of FIG. 5. Three specific examples of mistuning will then be
considered. Initially, assume that the local oscillator is mistuned
relative to the received signal to a frequency f1 as shown in the
lower graph of FIG. 5. In this condition, the outout of the frequency
discriminator 60 is positive since this signal frequency lies to the
lefthand side of the center or properly tuned region of operation of
the discriminator. Under this condition of the operation, the input
signal applied to the sensor port B12 of the microcomputer 23 is such
that the microcomputer counter 82 is caused to advance in a positive
direction to change the programmable division ratio or count of the
reference counter 35 in a manner to force the output of the phase
comparator 37 to adjust the frequency of the local oscillator until
the proper tuning indicated at point B in the lower graph of FIG. 5
is reached. The time interval for accomplishing this result is
measured from the upper end of the arrow representative of the
frequency f1 to the point B.
Now assume that the receiver
mistuning is to a frequency f2 which as shown in FIG. 5 as located on
the righthand-side of the center axis fc. In this condition, the
discriminator output is negative. This is reflected in the output of
the comparator 61 applied to the input port B12 of the microcomputer
23. The polarity of this signal is identified by the microcomputer 23
to cause the counter 82 in it to operate in the reverse direction.
As this count is applied on a step-by-step basis through the latch
circuits 49 and 50 to the reference counter 35, the division ratio or
count of the reference counter (divider) 35 is changed. As a result,
the reference oscillator signal applied to the phase comparator 37
causes the phase comparator 37 output to drive the local oscillator
frequency in a direction opposite to that considered in the first
example. This is shown by the vector interconnecting the top of the
arrow representative of f2 to point A on the time/frequency graph of
FIG. 5.
As discussed in the general discussion above, whenever
the tuning frequency reaches the narrow window on either side of fc,
the outputs of the comparators 62 and 63 provide the necessary
indication on the sensory input port terminal B11 to cause
termination of the operation of the counter 82 in the microcomputer
23. Then the reference counter 35 remains set to the count attained
just prior to the appearance of this input signal on the input port
B11 of the microcomputer 23.
A third mistuning condition can
exist, and ordinarily this condition results in an ambiguity which
cannot be corrected simply by responding to the signal polarity at the
output of the frequency discriminator. This is indicated by the
mistuned condition where the difference between the local oscillator
frequency f3 and the transmitter frequency is such that the signal f3
lies in the range to the right of the negative portion of the
discriminator output shown in the upper waveform of FIG. 5. In this
condition, the associated sound causes the discriminator output to be
positive; so that the television receiver normally would attempt to
tune toward the next adjacent channel and away from the properly tuned
center frequency of the channel which is desired. The output of the
discriminator 60 in this situation is the same as it was in th
e
first example considered for frequency f1; so that the counter 82 of
the microprocessor 23 operates to change the count in the reference
counter 35 in a manner to cause the local oscillator frequency to go
higher toward a frequency f3 +Δf, as shown in FIG. 5.
A
predetermined number of counts of the counter 82 in the microcomputer 23
are necessary for the microcomputer to count through the frequency
range Δf, and this range is selected to be within the pull in or
operating range of the system. Once this count has been attained, the
microcomputer counter 82 immediately is reset back to a count which
corresponds to a frequency 2 Δf lower than the frequency attained by the
maximum count. This is indicated in FIG. 5 by the frequency f3-Δf.
Because the microcomputer counter 82 is limited to counting a number
of counts equal to Δf, this new frequency now is on the lefthand side
of the center line fc, shown in both waveforms of FIG. 5. This
places the local oscillator frequency at a point such that the
frequency discriminator output is the positive output shown on the
lefthand-side of the upper waveform of FIG. 5. Counting continues in
the same direction as previously. This time, however, it is in a
proper direction to bring about correct tuning; and when the center
frequency is reached, the output of the comparators 62 and 63 cause
the microcomputer 23 to stop its count. The proper tuning point
attained is indicated at point C on the graph of the lower part of
FIG. 5.
Because the counter 82 of the microcomputer is limited
to a maximum count equivalent to Δf above its initial count and
thereupon is reset to a new count equivalent to 2 Δf lower than the
maximum count, it is not necessary to utilize any other sensory
inputs in order to properly tune the receiver over a wide pull in
range (as much as plus or minus 2 MHz). Only the output of the
conventional frequency discriminator 60 is used to provide the
necessary sensory inputs.
The
counter 82 of the microcomputer 23 is operated by the clock 81
during the foregoing sequence of operation, immediately following the
selection of a new channel by the operation of the keyboard 25, at a
fast or high speed operation. Typically, the counter steps are 10
milliseconds per step; so that there are no initial visual effects
which can be noticed by an observer of the television screen of the
receiver being tuned. The maximum forced search period is
approximately 900 milliseconds in duration. At the end of this time
interval, a timer in the microcomputer 23 causes a signal to be
applied through the outputs of the E output port to the decoder
circuit 52 indicative of the completion of this time interval. The
decoder 52 then applies a pulse on an output lead connected to the B13
input of the B input port of the microcomputer 23. This pulse is
sensed by the microcomputer 23 and is applied to the clock 81 to
change the clock rate to a much slower rate, approximately one-third
(1/3) or one-fourth (1/4) the rate used previously during the forced
search mode of operation. This then permits the system to accomodate
station drifts which normally occur at a very slow rate during the
transmission and reception of a television signal. As a consequence,
it is possible to use more filtering in the filter 39 on the tuning
line (FIG. 1) and employ a smaller frequency window for the channel
verification sensed by the circuitry shown in FIG. 3. The result is a
more precise tuning from the receiver than is otherwise possible if
only a high speed operation of the clock 81 is utilized.
When
the channel once again is changed by operation of the keys in the
keyboard 25 or operation of the channel selection circuitry from a
remote control unit, this new channel input is sensed by the
microcomputer 23 from the signals applied to the A input port and the
clock 81 is reset to its fast time or the forced search mode of
operation; and the process resumes.
Instead of employing an
additional decoding function in the decoder 52, a separate decoder also
could be connected to the outputs of the D output ports to feed back
the signal to the B13 input terminal of the B input port of the
microcomputer 23. The operation of the system to change the rate or
frequency of the pulses applied by the clock 81 to the counter 82
otherwise is the same as described above.
Although applicant has
found that it is preferable to correct for mistuning or frequency
offsets by adjusting the count or division ratio of the counter 35,
such offset adjustments also could be effected by adjusting the count
in the counter 31 in the local oscillator signal line. The operation
in such a case is the same as described above for adjusting the
count in the counter 35.
If the receiver is to be used with an
automatic signal seek mode of operation, however, additional sensory
inputs are necessary. These inputs operate in conjunction with the
output of the frequency discriminator 60. The operation of the
microcomputer 23 in controlling the count of the reference
programmable frequency counter divider 35 is the same as described
above. The additional sensory inputs simply are used in conjunction
with the outputs of the comparators 62 and 63 to signal the
microcomputer 23 to assure that tuning is to a picture channel rather
than an adjacent sound channel. This is accomplished by utilizing
the output of the synchronizing signal separator 65 which is applied
to a comparator 67 to produce an output signal to the SNS1 sensory
input of the microcomputer 23 only when vertical synchronizing signal
components are present.
In addition, the output of a picture
carrier detector 69 is applied to the input of a comparator 70 to
produce an output to the B10 sensory input of the microcomputer 23.
If the picture carrier detector 69 is producing an output indicative
of the presence of a carrier, but no output is being obtained from
the vertical synch separator 65 at the same time, the system is
mistuned to a sound carrier and the microcomputer 23 is permitted to
continue its localized search until a properly tuned station is
found. Only when there is coincidence of signals from the picture
carrier detector 69, the synch signal separator 65, and the automatic
frequency discriminator window as determined by the comparators 62
and 63, is the microcomputer operation terminated to indicate that a
properly tuned channel is present.
Further insurance of tuning
the receiver only to a strong signal also can be provided by the
addition of an AGC amplifier 72. This is connected to a comparator 74
coupled to the B10 input port along with the output of the picture
carrier detector comparator 70. When the AGC amplifier 72 is used as a
sensory input, the microcomputer operation, when the system is used
in a signal seek mode, is only terminated to indicate reception of a
valid signal when that signal is strong enough to produce the desired
output from the comparator 74. The signal level which is acceptable
is set by a potentiometer 75.
It should be noted that when the
system is operated in a signal seek mode, the sensory inputs must
indicate the reception of a properly tuned signal within a
pre-established time period. If no signal is sensed by the various
sensory input circuits operating in conjunction with one another as
described above, the microcomputer 23 automatically steps to the next
channel number and repeats the sequence of operation described above.
This is when it is placed in its signal seek mode of operation. If
signal seek is not employed, the additional sensory circuits 65, 69
and 72 are not necessary, and the inputs to the microcomputer which
are provided from these sensory circuits are not utilized. The
sensory signal input which is used both for a receiver without a
signal seek capability of operation and for a receiver which has a
signal seek mode of operation in it, is the output of the frequency
discriminator 60 operating in conjunction with the comparators 61, 62
and 63 as described above.
As indicated above, the wideband
method of tuning precisely to an incoming signal that is at the wrong
frequency described here only needs the frequency discriminator
sensory information. The method that uses the additional sensors
described above is needed to make this system operate compatibly with
signal seek but it is not restricted to seek operation.
For
a system that does not use signal seek operation, only the frequency
discriminator sensory input is required for proper operation. The
discriminator 60 is used for both fine tuning direction information and
to produce a frequency window to indicate the presence of a
correctly tuned station (channel verification). Initially, after a
channel change, there is a 250 millisecond settling time, the same as
the operation described above with compatible seek. After that,
however, comes a period of time where a forced localized search is
produced by the microcomputer 23. The forced search is needed to
insure that the system will correctly tune to stations that initially
may be tuned to the undesired zero voltage crossover in the right
half of the upper curve of FIG. 5. Such signals may be within the
frequency window of the discriminator 60; and if a search is not
forced, this system will not correctly tune. The compatible seek
system described previously correctly tunes the local oscillator
without a forced search, because the picture carrier detector and
vertical detector do not give an output for this situation and the
system automatically goes into its search mode of operation. However,
the non-seek system does not have a picture carrier sensor input and
must be forced to search for an initial period of time sufficient to
allow the system to tune up to its maximum frequency and then reset
(loop) back to a frequency of 2 Δf lower. Then it is tuned to the
positive left half portion of the discriminator curve (FIG. 5) and
the frequency window created by the discriminator 60 is sufficient to
insure proper tuning. If the discriminator output produced by the
desired incoming signal created an initial situation that produces
the correct tuning direction information, i.e., in the left half of
the curve of FIG. 5, or in the right half portion that gives the
correct direction and
frequency
window information, the forced search would not be needed. However,
the forced search will produce a correct tuning situation anyway. In
these cases, the tuning either is correct to begin with or correct
tuning is reached quickly. Then, even though the forced search is
active, it simply alternates up and down through the correct tuning
point because each time the receiver is tuned a little high in
frequency, it produces a negative output from the discriminator 60;
and the tuning direction signal causes the system to tune down in
frequency.
Then,
a positive discriminator output is produced, and the system tunes up
in frequency. This continues until the forced search is removed by
time-out of the microcomputer 23 (a fraction of a second). At such
time, the receiver is correctly tuned by the frequency window of the
discriminator to be very near fc. The system cannot tune to the
undesired discriminator crossover shown in the right half portion of
FIG. 5 because the polarity of the tuning direction signal always
causes it to tune away from that point.
The fast time or forced
search operation of the system can be terminated in a different way
other than the preestablished time-out period described above in
conjunction with the operation of the circuit shown in FIG. 2.
Generally, it is desirable to build into the system (or program into
the system by means of software) such a maximum time-out period to
effect the operation which has been described above to terminate the
search and cause the clock 81 thereafter to operate in a low speed
mode of operation. Termination also can be accomplished by sensing the
number of changes in the direction sensor input applied to the B12
terminal of the B input port to cause the search to be terminated when
this direction changes three times (or more). By doing this, any
flicker that might be observed on the screen of the television
receiver is minimized, since the forced search still takes place at
the high rate of application of clock pulses from the clock 81 to the
counter 82 in the same manner described above.
Termination of
the search, however, also may be effected by means of a search
terminate counter 78 (FIG. 3), which is advanced by pulses applied to
it each time the output of the comparator 61 changes its sign
(indicative of a change in direction for the counter 82) as applied
to it through the B12 input port, as described earlier. After three
of these changes, or some other number if desired, an output pulse is
obtained from the search terminate counter 78 and is applied to the
SNS0 input of the microcomputer 23. This causes the operation of the
clock 81 to be switched to its low speed mode of operation to
terminate the fast or "forced search" mode of operation. The next
time a new channel number is entered on the keyboard 25, a reset
pulse is applied to the search terminate counter 78 to reset it to
its original or zero count, thereby readying it for another sequence
of operation. It is apparent that the search terminate counter 78 may
not always be operated to terminate the count, since the time-out
interval which is sensed by the decode circuit 52 and applied to the
B13 input port of the microcomputer 23 may occur before there are
three changes of direction of the search. In any event, the next time
a new channel number is entered into the keyboard 25, the search
terminate counter 78 is reset; so that it is irrelevant whether this
counter reaches a full count or not to effect the termination of the
forced search operation of the system.
FIG. 4 shows the control
sequence of the system which is stored in the ROM (Read Only Memory)
of the microcomputer 23. The microcomputer 23 operates by always
running through the flow sequence, via loops L1, L2 and L3. Loop L1
corresponds to a new channel selection by two digit number entry. Loop
L2 corresponds to channel number increment or decrement by an up or
down key operation, respectively, or by seek operation. Loop L3
corresponds to fine tuning, either manual or automatic. To obtain
exact timing for system control, the microcomputer 23 receives a
standard timing pulse from the output of the reference counter 35
divided in a divide-by-five counter 80 and applied to the A13 input
port of the microcomputer 23. The control functions which are
programmed into the microcomputer 23, as indicated in the flow chart
of FIG. 4, are outlined in the following paragraphs.
Channel
Number Correction: An invalid two digit channel number entry (0, 1,
84, 99) is corrected. When the operation of the receiver is in the
signal seek mode, the next channel up from 83 is channel 2, and the
next lower channel from channel 2 is 83.
PLL Control I: For a
given channel number, a corresponding binary code for the PLL selector
counter 31 is derived as described previously. For UHF channels, the
local oscillator frequency separation between two adjacent channels
is 6 MHz and the code for PLL is generated by the microcomputer 23
through means of a simple calculation. This code then is transferred
from the microcomputer 23 to the latches 44, 45 and 46 as described
previously.
PLL Control II: This routine of the microcomputer 23
is used to transfer the fine tuning data to the latches 49 and 50
which control the count of the reference counter 35 in the PLL
circuit.
Channel Number Display: The channel number is
transferred from the microcomputer 23 to the driver latches of the
display driver circuit 29.
Key Input Detection: The keyboard is
arranged as the matrix circuit shown in FIG. 2. ROM programming for
scanning and acknowledging a keyboard entry only after successive
indications provides protection against false entry due to contact
bounce. The four data output lines of the D output port of the
microcomputer 23 are used to transfer data to the phase lock loop
section of the circuit and to the display circuit 29, as well as for
scanning the keyboard matrix circuit.
Time Count: The
microcomputer 23 receives a basic timing pulse of approximately 200 Hz
from the output of the divider 80 and performs various controls for
each timing pulse. By way of example, sensing for the vertical synch
input (when the system is used with a signal seek capability) on the
input port SNS1 takes place every 2.5 milliseconds. Automatic seek
timing is selected to be 133 milliseconds for UHF channels. All of
these timing pulses are derived from the basic synchronization timing
pulse applied to the microcomputer on the A13 input port from the
output of the divider 80. Various other timing values used in the
microcomputer to properly time multiplex sequence the operation are
derived from this basic timing pulse.
Sensor Input Detection:
As described previously, the output of the comparators shown in FIG. 3
reflect the status of the tuning of the television receiver. If no
signal seek mode of operation is used, only the frequency
discriminator or AFT discriminator 60 is necessary. When a system is
being used in a signal seek mode, a proper television signal receipt
is indicated by the presence of a vertical synch signal at the output
of the synch signal separator 65 and corresponding outputs are
applied to the input leads B10 and B11 (high level input signals)
indicative of tuning to the "correct tuned" frequency discriminator
window and reception of a picture carrier. As stated previously, the
signal present on the B12 input lead is used to determine the
direction of tuning when the receiver is operated in its automatic
mode.
Mode Detection: The status of the seek and
automatic/manual (A/M) switches are detected. If the A/M switch (not
shown) is in its automatic position, automatic seek and offset
correction are active. If only the seek switch is on, only seek is
performed. If the A/M switch is in manual, manual fine tuning (MFT) is
active.
Automatic Mode: If the TV receiver is not properly
tuned for VHF channels in automatic, the local oscillator frequency
is shifted automatically toward proper tuning. The fine tuning data
is generated in the microcomputer 23 and is transferred to the
latches 49 and 50 for the reference counter 35 in the PLL circuit.
Manual
Fine Tuning (MFT) Control: The local oscillator frequency is shifted
by pushing the fine tuning up (U) or down (D) pushbutton or switch.
This MFT control can be applied to VHF channels as well as to UHF
channels.
Channel Up/Down: When a channel up (upward pointing
arrow) or down (downward pointing arrow) key closure in the keyboard 25
is detected, or upon a direct access to an unused channel, this
routine is activated and the system will advance to the next channel in
the selected direction.
The
foregoing embodiment of the invention which has been described above
and which is illustrated in the drawings is to be considered
illustrative of the invention, which is not limited to the specific
embodiment selected for this purpose. For example, hard-wired logic
could be used to achieve the various circuit operations which are
accomplished by the microcomputer 23 in conjunction with the other
portions of the system. The relative ease of programming and debugging
the microcomputer 23, however, make it much simpler to implement the
system operation with the microcomputer than with hard-wired logic.
With respect to the sensor circuit inputs to the system, an added
degree of operating assurance can be provided by the addition of a
sound carrier sensor in addition to the picture carrier sensor shown
in FIG. 3. If this feature is desired, the output of the comparator
for the sound carrier is combined with the outputs of the comparators
70 and 74 at the input terminal B10 of the B input port of the
microcomputer 23. Because of the manner of the circut operation which
has been described previously, however, the addition of a sound
carrier detector to the system is not considered necessary, even for a
system operating in the signal seek mode of operation. This is in
contrast to conventional television receivers having a signal seek
operation, in which detection of the sound carrier generally is a
necessity to insure that mistuning of the receiver to an adjacent
sound carrier does not take place.
TELEFUNKEN Superheterodyne receiver frequency tracking circuit:
In a superheterodyne signal receiver including an input circuit arranged to be tuned to a frequency to be received and including a signal controllable variable reactance element presenting a reactan
ce whose value is adjusted by a tuning signal and determines the frequency to which the input circuit is tuned, and a controllable local oscillator producing an alternating signal to be mixed with a received signal to produce an intermediate frequency received signal, a tracking circuit composed of: a first frequency control circuit including the local oscillator; a second frequency control circuit including a controllable sampling oscillator and a member connected to respond to the frequency of the output from the sampling oscillator to derive a signal related thereto and supplying that signal, as the tuning signal, to the controllable element; and a control signal generating unit generating first and second control signals and connected for supplying the first control signal to the first frequency control circuit for adjusting the frequency of the signal produced by the local oscillator, and for supplying the second control signal to the second frequency control circuit for adjusting the value of the tuning signal to tune the input circuit to a selected frequency, the generating unit maintaining a relationship between the first and second control signals such that the output frequency of the local oscillator is adjusted to the value corresponding to the received signal frequency to which the input circuit is tuned.
1. In a superheterodyne signal receiver including an input circuit arranged to be tuned to a frequency to be received and including a signal controllable variable reactance element presenting a reactance whose value is adjusted by a tuning signal and determines the frequency to which the input circuit is tuned, and a controllable local oscillator producing an alternating signal to be mixed with a received signal to produce an intermediate frequency received signal, a synchronizing circuit comprising: a first frequency control circuit including said local oscillator; a second frequency control circuit including a controllable sampling oscillator and means connected to respond to the frequency of the output from said sampling oscillator to derive a signal related thereto and supplying that signal, as the tuning signal, to said controllable element; and control signal generating means generating first and second control signals and connected for supplying said first control signal to said first frequency control circuit for adjusting the frequency of the signal produced by said local oscillator, and for supplying said second control signal to said second frequency control circuit for adjusting the value of said tuning signal to tune said input circuit to a selected frequency, said generating means maintaining a relationship between said first and second control signals such that the output frequency of said local oscillator is adjusted to the value corresponding to the received signal frequency to which said input circuit is tuned, wherein each said frequency control circuit includes converter means connected to provide an output signal representative of the frequency of the signal produced by its associated oscillator, and oscillator control means having a first input connected to receive the output signal provided by its associated converter means, a second input connected to receive its respective control signal and an output connected to supply its associated oscillator with a setting signal which is dependent on a relation between the signals at its first and second inputs for establishing a linear relationship between its respective control signal and the frequency produced by its respective oscillator, said synchronizing circuit further comprises a source of an addition a.c. signal, and said converter means of at least one said circuit has at least two inputs one of which is connected to receive a signal derived from the signal at the output of its associated oscillator and the other of which is connected to receive the additional a.c. signal and acts to cause its output signal to be dependent on a relationship between the frequencies of the signals applied to its two inputs.
2. In a superheterodyne signal receiver input section including: an input circuit, arranged to be tuned to the frequency of a signal to be received and containing a controllable reactance the value of which is adjusted by a tuning signal and determines the frequency to which the input circuit is tuned; a controllable local oscillator producing an alternating signal to be mixed with a received signal supplied by the input circuit to produce an intermediate frequency received signal; a first frequency control loop composed of the local oscillator, a first converter connected to provide an output signal representative of the frequency of the signal produced by the local oscillator, and first oscillator control means having a first input connected to receive the output signal provided by the first converter, a second input connected to receive a first control signal and an output connected to supply the local oscillator with a setting signal to adjust the frequency of the signal produced by the local oscillator as a function of a relation between the first control signal and the output signal provided by the first converter, with the local oscillator, first converter and first oscillator control means being connected together in a loop; a second frequency control loop including a controllable sampling oscillator containing a controllable reactance the value of which determines the frequency of the signal produced by the sampling oscillator, a second converter connected to provide an output signal representative of the frequency of the signal produced by the sampling oscillator control means having a first input connected to receive the output signal provided by the second converter, a second input connected to receive a second control signal and an output connected to supply the sampling oscillator with a setting signal to adjust the frequency of the signal produced by the sampling oscillator as a function of a relation between the second control signal and the output signal provided by the second converter, and means connected to supply the tuning signal to the input circuit, the value of which tuning signal is a function of the frequency of the signal being produced by the sampling oscillator, with the sampling oscillator, second converter and second oscillator control means being connected together in a loop; and control signal generating means including a source of a reference signal and means for causing the first and second control signals to be functions of the reference signal and to be so related to one another that the input circuit is tuned to a received signal frequency corresponding to the output frequency of the local oscillator, the improvement wherein said reference signal source comprises a source of an a.c. reference frequency signal, and a third converter connected to receive the reference frequency signal and to provide said reference signal at its output for compensating undesirable changes in the output signals produced by said first and second converters as a result of external adverse influences.
3. Circuit arrangement as defined in claim 2 wherein said control signal generating means comprise a common control element constituting the source of both said first and second control signals.
4. Circ
uit arrangement as defined in claim 3 wherein said control signal generating means further comprise signal modifying means connected to subject the output of said common control element to arithmetic operations for giving said first control signal a value which causes the output frequency of said local oscillator to be offset from the corresponding received signal frequency by a constant amount corresponding to the intermediate frequency value and for giving said second control signal a value which causes said tuning signal to tune said input circuit to a frequency corresponding to the frequency of the output of said local oscillator and differing from said local oscillator frequency by the intermediate frequency.
5. Circuit arrangement as defined in claim 4 wherein each of said first and second converters includes means establishing a linear relationship between its respective control signal and the frequency produced by its respective oscillator.
6. Circuit arrangement as defined in claim 5 wherein at least one of said control signals is an analog signal.
7. Circuit arrangement as defined in claim 6 wherein at least one said oscillator control means comprises a comparator.
8. Circuit arrangement as defined in claim 7 wherein, in said at least one loop, said comparator has two inputs, one of which is connected to the output of said converter in the same loop, said comparator having an output connected to control the frequency of said oscillator associated with the same loop, and said control signal for said loop is supplied to the second input of said comparator.
9. Circuit arrangement as defined in claim 5 wherein said converter of at least one said loop has at least two inputs for receiving a signal from the oscillator associated with said loop and the a.c. reference frequency signal signals and acts to produce an output signal having a d.c. component which varies in dependence on a relationship between the frequencies of the two input signals.
10. Circuit arrangement as defined in claim 9 wherein said third converter is connected to said reference frequency source for producing an output signal having a d.c. component proportional to the reference frequency and constituting said reference signal.
11. Circuit arrangement as defined in claim 9 wherein said converter of said at least one loop produces an output signal which changes only when there is a change in the frequency relationship of the two a.c. input signals and in proportion to this relationship.
12. Circuit arrangement as defined in claim 11 wherein said converter of said at least one loop operates to reverse the frequency relationship to which the change in the direct component of the output signal is proportional when the connections of the input signals to the two inputs of said converter are interchanged.
13. Circuit arrangement as defined in claim 9 wherein said converter of said at least one loop has a further input connected to receive a further a.c. input signal for further controlling the d.c. component of the output signal of said converter as a function of the frequency of the further input signal.
14. Circuit arrangement as defined in claim 9 wherein variation in the d.c. component of the output signal of said converter of said at least one loop is proportional to changes in the duty ratio of at least one of its input signals.
15. Circuit arrangement as defined in claim 9 wherein the d.c. component of the output of said converter of said at least one loop varies according to the relationship V=K
1 +K
2.f
1 /f
2, where V is the value of the d.c. component, K
1 and K
2 are constants, f
1 is the frequency of the output of its respective oscillator and f
2 is the frequency of the output of said reference frequency source.
16. Circuit arrangement as defined in claim 2 wherein all of said converters are structurally and functionally identical.
17. Circuit arrangement as defined in claim 2 or 16 wherein said controllable reactances of said input circuit and said sampling oscillator are constituted such that the values of said reactances vary in a constant ratio to one another in response to changes in the value of said second control signal.
18. Circuit arrangement as defined in claim 17 wherein said controllable reactances of said input circuit and said sampling oscillator are identical in their design and response characteristics.
19. Circuit arrangement as defined in claim 18 further comprising a single semiconductor chip presenting two identically constructed semiconductor varactor diodes, and wherein each said diode constitutes a respective one of said controllable reactances.
20. Circuit arrangement as defined in claim 19 wherein the capacitances of said two diodes bear a constant ratio to one another and further comprising two capacitors each connected in parallel with a respective diode, the values of the capacitances of said capacitors being in said constant ratio to one another.
21. Circuit arrangement as defined in claim 18 wherein said controllable reactances present controllable capacitances having capacitance values which bear a constant ratio to one another and further comprising two capacitors each connected in parallel with a respective controllable capacitance, the values of the capacitances of said capacitors being in said constant ratio to one another.
22. Circuit arrangement as defined in claim 17 wherein said controllable reactances present controllable capacitances having capacitance values which bear a constant ratio to one another and further comprising two capacitors each connected in parallel with a respective controllable capacitance, the values of the capacitances of said capacitors being in said constant ratio to one another.
23. Circuit arrangement as defined in claim 17 further comprising a single semiconductor chip presenting two identically constructed semiconductor varactor diodes, and wherein each said diode constitutes a respective one of said controllable reactances.
24. Circuit arrangement as defined in claim 2 or 16 wherein said controllable reactances of said input circuit and said sampling oscillator are identical in their design and response characteristics.
25. Circuit arrangement as defined in claim 2 or 16 further comprising a single semiconductor chip presenting two identically constructed semiconductor varactor diodes, and wherein each said diode constitutes a respective one of said controllable reactances.
26. Circuit arrangement as defined in claim 2 or 16 wherein said controllable reactances present controllable reactances present controllable capacitances having capacitance values which bear a constant ratio to one another and further comprising two capacitors each connected in parallel with a respective controllable capacitance, the values of the capacitances of said capacitors being in said constant ratio to one another.
Description:
BACKGROUND OF THE INVENTION
It is known that frequency synchronism must exist between the oscillator and the input circuit of a superheterodyne receiver.
In order to attain the required synchronism between oscillator and input circuit, various techniques are employed. For example, it can be attempted to achieve the desired synchronism by specially cutting the discs of the rotary tuning capacitor. However, for electronic tuning systems varactor diodes which have specially adapted capacitance/voltage characteristics are not available. For this reason, tuning systems with varactor diodes employ the known threepoint tracking which, however, permits optimum tracking, or synchronization only at three points of the frequency range. Even with precisely identical characteristics of the tuning elements or diodes, there occur synchronization deviations which result in sensitivity breaks within the tuning range. Moreover, inequality of the characteristics and deviations in the capacitance value of the padding capacitor produce additional deviations and thus increase the problem.
SUMMARY OF THE INVENTION
Objects of the present invention are to provide improved synchronization compared to the known tracking circuits and to eliminate the deviations which, when three-point synchronization is employed, inherently occur in such known circuits across the tuning frequency band.
This and other objects are achieved, according to the present invention, by the provision, in or for a superheterod
yne signal receiver including an input circuit arranged to be tuned to a frequency to be received and including a signal controllable variable reactance element presenting a reactance whose value is adjusted by a tuning signal and determines the frequency to which the input circuit is tuned, and a controllable local oscillator producing an alternating signal to be mixed with a received signal to produce an intermediate frequency received signal, of a tracking circuit composed of: a first frequency control circuit including the local oscillator; a second frequency control circuit including a controllable sampling oscillator and means connected to respond to the frequency of the output from the sampling oscillator to derive a signal related thereto and supplying that signal, as the tuning signal, to the controllable element; and control signal generating means generating first and second control signals and connected for supplying the first control signal to the first frequency control circuit for adjusting the frequency of the signal produced by the local oscillator, and for supplying the second control signal to the second frequency control circuit for adjusting the value of the tuning signal to tune the input circuit to a selected frequency, the control signal generating means maintaining a relationship between the first and second control signals such that the output frequency of the local oscillator is adjusted to the value corresponding to the received signal frequency to which the input circuit is tuned.
When Telefunken came to design the 415/615 chassis they wanted to use the simplest possible LOPT. This led to the adoption of an interesting new e.h.t. rectifier arrangement.A SCART Connector (which stands for Syndicat des Constructeurs d'Appareils Radiorécepteurs et Téléviseurs) is a standard for connecting audio-visual equipment together. The official standard for SCART is CENELEC document number EN 50049-1. SCART is also known as Péritel (especially in France) and Euroconnector but the name SCART will be used exclusively herein. The standard defines a 21-pin connector (herein after a SCART connector) for carrying analog television signals. Various pieces of equipment may be connected by cables having a plug fitting the SCART connectors. Television apparatuses commonly include one or more SCART connectors.
Although a SCART connector is bidirectional, the present invention is concerned with the use of a SCART connector as an input connector for receiving signals into a television apparatus. A SCART connector can receive input television signals either in an RGB format in which the red, green and blue signals are received on Pins 15, 11 and 7, respectively, or alternatively in an S-Video format in which the luminance (Y) and chroma (C) signals are received on Pins 20 and 15. As a result of the common usage of Pin 15 in accordance with the SCART standard, a SCART connector cannot receive input television signals in an RGB format and in an S-Video format at the same time.This kind of connector is todays obsoleted !Consequently many commercially available television apparatuses include a separate SCART connectors each dedicated to receive input television signals in one of an RGB format and an S-Video format. This limits the functionality of the SCART connectors. In practical terms, the number of SCART connectors which can be provided on a television apparatus is limited by cost and space considerations. However, different users wish the input a wide range of different combinations of formats of television signals, depending on the equipment they personally own and use. However, the provision of SCART connectors dedicated to input television signals in one of an RGB format and an S-Video format limits the overall connectivity of the television apparatus. Furthermore, for many users the different RGB format and S-Video format are confusing. Some users may not understand or may mistake the format of a television signal being supplied on a given cable from a given piece of equipment. This can result in the supply of input television signals of an inappropriate format for the SCART connector concerned.
