The THOMSON CHASSIS ICC5 Is a highly engineered chassis (see pictures).
It was introducing high integration of advanced and high precision functions.
It's introducing all digital control of all circuits, from tuning to video matrix and audio.
It was fitted in a very high number of models with screen formats varying from 20 to 32 Inches.
It has known a high rate of improvements and add ons fetures and further functions.
The
version here in collection is the second version marketed in 1986 when
the ICC5 was developed (5110) which eliminates the reset ic but keeping
the basic design here shown.
It has a layout design which is very complex due to high engineering on signal path toghether with integration needings.
Functionally
they run very well and stable but it was showing the highest rate of
failures caused by dry joint evn almost immediately when new !! !!
To run these in reliable way you have to basically rework all the PCB Joint !!
THE SET HERE SHOWN WAS NEVER SERVICED WHICH IS QUITE RARE FOR A THOMSON ICC5 CHASSIS.
Quality of components it's very high, all parts here pictured are original from 1986.
Picture
produced by this chassis is excellent and this is expecially coming
from the accurate and high performed video signal processing.
CIRCUITS DESCRIPTIONS.
THOMSON TF5551 PG5 THOMSQUARE (ICC5) CHASSIS ICC5 (5116) COLOR TV SCANNING AND POWER SUPPLY PROCESSOR TEA2029C
DESCRIPTION
The TEA2029C is a complete (horizontal and vertical)
deflection processor with secondary to primary
SMPS control for color TV sets.
DEFLECTION .CERAMIC 500kHz RESONATOR FREQUENCY
REFERENCE .NO LINE
AND FRAME OSCILLATOR ADJUSTMENT
.DUAL
PLL FOR LINE DEFLECTION .HIGH PERFORMANCE SYNCHRONIZATION .SUPER
SANDCASTLE OUTPUT .VIDEO IDENTIFICATION CIRCUIT .AUTOMATIC 50/60Hz
STANDARD IDENTIFICATION
.EXCELLENT INTERLACING CONTROL .SPECIALPATENTED FRAME SYNCHRO DEVICE
FOR VCR OPERATION .FRAME SAW-TOOTH GENERATOR .FRAME PHASE MODULATOR FOR THYRISTOR
SMPS CONTROL .ERROR AMPLIFIER AND PHASE MODULATOR
.SYNCHRONIZATION WITH HORIZONTAL
DEFLECTION .SECURITY CIRCUIT AND START UP PROCESSOR.
GENERAL DESCRIPTION
This integrated circuit uses I2L bipolar technology
and combines analog signal processing with digital
processing.
Timing signals are obtainedfrom a voltage-controlled
oscillator (VCO) operatingat 500KHzby means
of a cheap ceramic resonator. This avoids the
frequency adjustment normally required with line
and frame oscillators.
A chain of dividers and appropriate logic circuitry
produce very accurately defined sampling pulses
and the necessary timing signals.
The principal functions implemented are :
- Horizontal scanning processor.
- Frame scanning processor. Two applications are
possible :
- D Class : Power stage using an external
thyristor.
- B Class : Powerstageusing an externalpower
amplifier with fly-back generator
such as the TDA8170.
- Secondary switch mode power regulation.
The SMPS output synchronize a primary I.C.
(TEA2260/61)at the mains part.
This concept allows ACTIVE STANDBY facilities.
- Dual phase-locked loop horizontal scanning.
- High performance frameand line synchronization
with interlacing control.
- Video identification circuit.
- Super sandcastle.
- AGC key pulse output.
- Automatic 50-60Hz standard identification.
- VCR input for PLL time constant and frame synchro
switching.
- Frame saw-tooth
generator and phase modulator.
- Switchingmode regulated power supplycomprising
error amplifier and phase modulator.
- Security circuit and start-up processor.
- 500kHzVCO
The circuit is supplied in a 28 pin DIP case.
VCC = 12V.
Synchronization Separator
Line synchronization separator is clamped to
black level of input video signal with synchronization
pulse bottom level measurement.
The synchronization pulses are divided centrally
between the black level and the synchronization
pulse bottom level, to improve performance on
video signals in noise conditions.
Frame Synchronization
Frame synchronization is fully integrated (no external
capacitor required).
The frame timing identification logic permits automatic
adaptation to 50 - 60Hz standards or non-interlaced
video.
An automatic synchronization window width system
provides :
- fast frame capture (6.7ms wide window),
- good noise immunity (0.4ms narrow window).
The internal gen
erator starts the discharge of the
saw-tooth generator capacitor so that it is not disturbed
by line fly back effects.
Thanks to the logic control, the beginning of the
charge phase does not depend on any disturbing
effect of the line fly-back.
A 32ms timing is automatically applied on standardized
transmissions, for perfect interlacing.
In VCR mode, the discharge time is controlled by
an internal monostable independent of the line
frequency and gives a direct frame synchronization.
Horizontal Scanning
The horizontalscanningfrequencyis obtainedfrom
the 500kHz VCO.
The circuit uses two phase-locked loops (PLL) :
the first one controls the frequency, the second one
controls the relative phase of the synchronization
and line fly-back signals.
The frequency PLL has two switched time constants
to provide :
- capture with a short time constant,
- good noise immunity after capture with a long
time constant.
The output pulse has a constant duration of 26ms,
independent of VCC and any delay in switching off
the scanning transistor.
Video Identification
The horizontal synchronization signal is sampled
by a 2ms pulse within the synchronization pulse.
The signal is integrated by an external capacitor.
The identification function provides three different
levels :
- 0V : no video identification
- 6V : 60Hz video identification
- 12V : 50Hz video identification
This information may be used for timing research
in the case of frequency or voltage synthetizer type
receivers, and for audio muting.
Super Sandcastle with 3 levels : burst, line flyback,
frame blanking
In the event of vertical scanning failure, the frame
blanking level goes high to protect the tube.
Frame blanking time (start with reset of Frame
divider) is 24 lines.
VCR Input
This provides for continuous use of the short time
constant of the first phase-locked loop (frequency).
In VCR mode, the frame synchronization window widens out to a search window and there is no
delay of frame fly-back (direct synchronization).
Frame Scanning
FRAME SAW-TOOTH GENERATOR. The current
to charge the capacitoris automatically switched to
60Hz operation to maintain constant amplitude.
FRAME PHASE MODULATOR (WITH TWO DIFFERENTIAL
INPUTS). The output signal is a pulse
at the line frequency, pulse width modulatedby the
voltage at the differential pre-amplifier input.
This signal is used to control a thyristor which
provides the scanning current to the yoke. The
saw-tooth output is a low impedance,however, and
can therefore be used in class B operation with a
power amplifier circuit.
Switch Mode Power Supply (SMPS) Secondary
to Primary Regulation
This power supply uses a differential error amplifier
with an internal reference voltage of 1.26V and a
phase modulator operating at the line frequency.
The powertransistor is turnedoff bythe falling edge
of the horizontal saw-tooth.
The ”soft start” device imposes a very small conduction
angle on starting up, this angle progressively
increases to its nominal regulation value.
The maximum conductionangle may be monitored
by forcing a voltage on pin 15. This pin may also
be used for current limitation.
The outputpulse is sent to the primaryS.M.P.S. I.C.
(TEA2261) via a low cost synchro transformer.
Security Circuit and Start Up Processor
When the security input (pin 28) is at a voltage
exceeding 1.26V the three outputs are simultaneously
cut off until this voltagedrops below the 1.26V
threshold again. In this case the switch mode
power supply is restarted by the ”soft start” system.
If this cycle is repeated three times, the three
outputs are cut off definitively. To reset the safety
logic circuits, VCC must be zero volt.
This circuit eliminates the risk to switch off the TV
receiver in the event of a flash affecting the tube.
On starting up, the horizontal and vertical scanning
functions come into operation at VCC = 6V. The
power supply then comes into operation progressively.
On shutting down, the three functions are interrupted
simultaneously after the first line fly-back.
THOMSON TF5551 PG5 THOMSQUARE (ICC5) CHASSIS ICC5 (5116) APPLICATION INFORMATION ON FRAME
SCANNING IN SWITCHED MODE:
Fundamentals (see Figure 80)
The secondary winding of EHT transformer provides
the energy required by frame yoke.
The frame current modulation is achieved by
modulating the horizontal saw-tooth current and
subsequent integration by a ”L.C” network to reject
the horizontal frequency component.
General Description
The basic circuit is the phase comparator ”C1”
which compares the horizontal saw-tooth and the
output voltage of Error Amplifier ”A”.
The comparator output will go ”high” when the
horizontal saw-tooth voltage is higher than the ”A”
output voltage. Thus, the Pin 4 output signal is
switched in synchronization with the horizontal frequency
and the duty cycle is modulated at frame
frequency.
A driver stage delivers the current required by the
external power switch.
The external thyristor provides for energy transfer
between transformer and frame yoke.
The thyristor will conduct during the last portion of
horizontal trace phase and for half of the horizontal
retrace.
The inverse parallel-connected diode ”D” conducts
during the second portion of horizontal retrace and
at the beginning of horizontal trace phase.
Main advantages of this system are :
- Power thyristor soft ”turn-on”
Once the thyristor has been triggered, the current
gradually rises from 0
to IP, where IP will reach
the maximumvalue at the end of horizontal trace.
The slope current is determined by, the current
available through the secondary winding, the
yoke impedance and the ”L.C.” filter characteristics.
- Power thyristor soft ”turn-off”
The secondary output current begins decreasing
and falls to 0 at the middle of retrace. The thyristor
is thus automatically ”turned-off”.
- Excellent efficiency of power stage dueto very
low ”turn-on” and ”turn-off” switching losses.
Frame Flyback
During flyback, due to the loop time constant, the
frame yoke current cannot be locked onto the
reference saw-tooth. Thus the output of amplifier
”A” will remain high and the thyristor is blocked.
The scanning current will begin flowing through
diode ”D”. As a consequence, the capacitor ”C”
starts charging upto the flyback voltage.The thyristor
is triggeredas soon as the yoke current reaches
the maximum positive value.
TDA4443 MULTISTANDARD VIDEO IF AMPLIFIERDESCRIPTION
The TDA4443 is a Video IF amplifier with standard
switch for multistandard colour or monochromeTV
sets, and VTR’s.
SWITCHING OFF THE IF AMPLIFIER WHEN
OPERATING IN VTR MODE .DEMODULATION OF NEGATIVE OR POSITIVE
IF SIGNALS. THE OUTPUT REMAINS
ON THE SAME POLARITY IN EVERY CASE .IF AGC AUTOMATICALLY ADJUSTED TO
THE ACTUALSTANDARD .TWO AGC POSSIBILITIES FOR B/G MODE :
1. GATED AGC
2. UNGATED AGC ON SYNC. LEVEL AND
CONTROLLED DISCHARGE DEPENDENT
ON THE AVERAGE SIGNAL LEVEL FOR VTR
AND PERI TV APPLICATIONS
FOR STANDARD L : FAST AGC ON PEAK
WHITE
BY CONTROLLED DISCHARGE .POSITIVE OR NEGATIVE GATING PULSE .EXTREMELY
HIGH INPUT SENSITIVITY .LOW DIFFERENTIAL DISTORTION .CONSTANT INPUT
IMPEDANCE .VERY HIGH SUPPLY VOLTAGE REJECTION .FEW EXTERNAL COMPONENTS
.LOW IMPEDANCE VIDEO OUTPUT .SMALL TOLERANCES OF THE FIXED VIDEO
SIGNALAMPLITUDE .ADJUSTABLE, DELAYED AGC FOR PNP
TUNERS.
GENERAL DESCRIPTION
This video IF processing circuit integrates the following
functional blocks : .Three symmetrical, very stable, gain controlled
wideband amplifier stages - without feedback
by a quasi-galvanic coupling. .Demodulator controlled by the picture carrier .Video output amplifier with high supply voltage
rejection
.Polarity switch for the video output signal .AGC on peak white level
.GatedAGC .Discharge control .Delayed tuner AGC .At VTR Reading mode the
video output signal
is at ultra white level.
TDA4445A SOUND IF AMPLIFIER
.QUADRATURE INTERCARRIER DEMODULATOR
.VERY HIGH INPUT SENSITIVITY .GOODSIGNALTO NOISE RATIO .FAST AVERAGINGAGC .IF AMPLIFIER CAN BE SWITCHED OFF FOR
VTR MODE .GOODAM SUPPRESSION .OUTPUT SIGNAL STABILIZED AGAINST
SUPPLY VOLTAGE VARIATIONS .VERY FEW EXTERNAL COMPONENTS
DESCRIPTION
TDA4445A:
Sound IF amplifier, with FM processing for quasi
parallel sound system.
TDA4445B:
Sound IF amplifier, with FM processing and AM
demodulator, for multi-standard sound TV appliances.
TDA4445Badditionnal :
Bistandard applications (B/G and L)
No adjustment of the AM demodulator
Low AMdistortion.
GENERAL DESCRIPTION
This circuit includes the following functions : .Three symmetrical and gain controlled wide
band amplifier stages, which are extremely stable
by quasiDC coupling without feedback. .Averaging AGC with discharge control circuit .AGC voltage generator
Quasi parallel sound operation : .High phase accuracy of the carrier signal processing,
independentfrom AM .Linear quadrature demodulator .Sound-IF-amplifier stage with impedance converter
AM-Demodulation (only TDA4445B) : .Carrier controlled demodulator .Audio frequency stage with impedance converter
.Averaging low passAGC.
TDA4556 Multistandard decoder
GENERAL DESCRIPTION
The TDA4555 and TDA4556 are monolithic integrated
multistandard colour decoders for the PAL, SECAM,
NTSC 3,58 MHz and NTSC 4,43 MHz standards. The
difference between the TDA4555 and TDA4556 is the
polarity of the colour difference output signals (B-Y)
and (R-Y).
Features
Chrominance part
· Gain controlled chrominance amplifier for PAL, SECAM
and NTSC
· ACC rectifier circuits (PAL/NTSC, SECAM)
· Burst blanking (PAL) in front of 64 ms glass delay line
· Chrominance output stage for driving the 64 ms glass
delay line (PAL, SECAM)
· Limiter stages for direct and delayed SECAM signal
· SECAM permutator
Demodulator part
· Flyback blanking incorporated in the two synchronous
demodulators (PAL, NTSC)
· PAL switch
· Internal PAL matrix
· Two quadrature demodulators with external reference
tuned circuits (SECAM)
· Internal filtering of residual carrier
· D
e-emphasis (SECAM)
· Insertion of reference voltages as achromatic value
(SECAM) in the (B-Y) and (R-Y) colour difference output
stages (blanking)
Identification part
· Automatic standard recognition by sequential inquiry
· Delay for colour-on and scanning-on
· Reliable SECAM identification by PAL priority circuit
· Forced switch-on of a standard
· Four switching voltages for chrominance filters, traps
and crystals
· Two identification circuits for PAL/SECAM (H/2) and
NTSC
· PAL/SECAM flip-flop
· SECAM identification mode switch (horizontal, vertical
or combined horizontal and vertical)
· Crystal oscillator with divider stages and PLL circuitry
(PAL, NTSC) for double colour subcarrier frequency
· HUE control (NTSC)
· Service switch.
THOMSON TF5551 PG5 THOMSQUARE (ICC5) CHASSIS ICC5 (5116) U4606 - TEA5040 (TELEFUNKEN) WIDE BAND VIDEO PROCESSOR
DESCRIPTION
The U4647 - TEA5040S is a serial bus-controlled videoprocessing
device which integrates a complex architecture
fulfilling multiple functions.
.DIGITAL CONTROL OF BRIGHTNESS,
SATURATION AND CONTRAST ON TV SIGNALS
AN
D R, G, B INTERNAL OR EXTERNAL
SOURCES .BUS DRIVE OF SWITCHING FUNCTIONS .DEMATRIXING OF R, G, B SIGNALS FROM
Y, R-Y, B-Y, TV MODE INPUTS .MATRIXING OF R, G, B SOURCES INTO
Y, R-Y, B-Y SIGNALS .AUTOMATIC DRIVE AND CUT-OFF CONTROLS
BY DIGITAL PROCESSING DURING
FRAME RETRACE .PEAK ANDAVERAGE BEAM CURRENT LIMITATION
.ON-CHIP SWITCHING FOR R, G, B INPUT
SELECTION .ON-CHIP INSERTION OF INTERNAL OR EXTERNAL
R, G, B SOURCES
An
automatic contrast control circuit in a color television receiver for
stabilizing the average DC level of the luminance information at a
desired level and preventing focus blooming. The control circuitry,
which is suitable for fabrication as a monolithic integrated circuit,
contemplates the provision of a gain-controlled luminance amplifier
stage for driving an image reproducer with luminance information having a
stabilized black level. An average detector coupled to the amplifier
stage output develops a control signal representative of the average DC
level of the luminance information and applies it to the amplifier
stage, varying its gain inversely with changes in the average luminance
level. A peak limiter circuit is also provided for modifying the
control signal to reduce the amplifier stage's gain whenever an AC
brightness component comprising the luminance information exceeds a
defined threshold level, regardless of the average DC level of the
luminance information.
1. In a television receiver
having a luminance processing channel for translating instantaneous
luminance signals derived from received broadcast transmissions to an
image reproducer, said luminance signals including black level
reference information, an automatic contrast control circuit comprising
in combination:
2. An
automatic contrast control circuit in accordance with claim 1, wherein
adjustable level shifting means are interposed between said amplifier
stage and said average detector means, said adjustable level shifting
means providing a contrast control for manually varying the average DC
level of said luminance signals.
3.
An automatic contrast control circuit in accordance with claim 1,
wherein said average detector means includes a capacitor having an
output terminal coupled to said amplifier stage and a second terminal
coupled to a plane of reference potential, said capacitor being charged
by luminance signals from said amplifier stage and developing control
signals representative of the average DC level of said luminance
signals.
4. An automatic
contrast control circuit in accordance with claim 3, wherein said
control signals with respect to a plane of reference potential are
equal to the potential at which black level is stabilized minus the
potential drop between black level and the average DC level of said
luminance information, said control signal increasing with respect to
said plane of reference potential responsive to decreasing average DC
levels of said luminance signals and decreasing responsive to
increasing average DC levels.
5.
An automatic contrast control circuit in accordance with claim 3,
wherein said peak detector means includes a semi-conductor arrangement
for providing said capacitor with a low impedance discharge path
whenever said brightness components exceed a predetermined threshold
level, the impedance of said discharge path being dependent on the
amplitude of said brightness components and the discharge interval of
said semiconductor arrangement being the time period during which said
brightness components exceed said threshold level, said semiconductor
arrangement further decreasing said control signals with respect to
said plane of reference potential irrespective of the average DC level
of said luminance signals.
6.
An automatic contrast control circuit in accordance with claim 5,
wherein said semiconductor arrangement comprises first and second
transistors, said luminance signals from said amplifier stage being
coupled to the input base electrode of said first transistor, said first
transistor further having an emitter electrode coupled to said
capacitor output terminal and a collector electrode coupled to the base
electrode of said second transistor, said second transistor having a
collector electrode coupled to said capacitor output terminal and an
emitter electrode coupled to said plane of reference potential, said
semiconductor arrangement being conductive to provide said capacitor
with a low impedance discharge path whenever said brightness components
exceed the base-emitter junction breakdown voltage of said first
transistor.
7. An automatic
contrast control circuit in accordance with claim 6, wherein said
gain-controlled luminance amplifier stage includes a pair of
transistors arranged in a differential amplifier configuration, the
gain of which is dependent on the bias applied to the base electrodes
of said transistors.
8. An automatic contrast control circuit in accordance wi
th
claim 7, wherein inverter means invert and couple said control signals
to said base electrodes in said amplifier stage, the inverted control
signals increasing the gain of said amplifier stage whenever the
average DC level of said luminance signals decreases and decreasing the
gain of said amplifier stage whenever the average DC level of said
luminance information increases or whenever said brightness components
exceed said threshold level.
9.
An automatic contrast control circuit in accordance with claim 3,
wherein said beam current limiter means provide a low impedance
discharge path for said capacitor whenever the beam current exceeds a
predetermined level.
10. An
automatic contrast control system in accordance with claim 9, wherein
said beam current limiter means monitors pulses from a voltage
multiplier high-voltage system, said pulses being proportional to the
beam current generated during the previous horizontal scan line.
11. An automatic contrast control
circuit in accordance with claim 10, wherein said beam current limiter
means comprises a transistor having a base electrode coupled to said
voltage multiplier high-voltage system, an emitter electrode coupled to
a plane of reference potential and a collector electrode coupled to
said capacitor, said transistor providing a low impedance discharge
path whenever said pulses exceed the base-emitter junction breakdown
voltage of said transistor.
Description:
BACKGROUND OF THE INVENTION
This
invention relates in general to control circuitry for color television
receivers and more particularly to an automatic contrast control
circuit incorporated in the luminance processing channel. In accordance
therewith, a variable DC control signal is derived from the luminance
signal information as a function of the average luminance level. The DC
control signal is applied to a gain-controlled amplifier stage in the
luminance channel, varying its gain and thereby insuring that excessive
beam currents will not be generated due to high average luminance
levels. Conversely, the circuit is effective to increase the gain of
the amplifier stage when under-modulated signals are received thereby
providing the desired contrast level. When the white content of the
instantaneous received signal exceeds a predetermined level, however,
the DC control signal is modified to reflect the excessive white
content even though the average luminance level may be low.
Accordingly, the amplifier stage's gain is reduced to prevent
defocusing.
In color television receivers, the various
elemental areas of differing brightness levels, or shades, in the
televised image correspond to the amplitude levels of the instantaneous
brightness components of the luminance signals which, together with
the chrominance signal, reproduce the transmitted picture information
on the image display tube. The intensity of the electron beams
developed in the receiver's image display tube are varied, for the most
part, according to the detected amplitude levels of the instantaneous
luminance signals. Accordingly, progressively higher amplitude levels
generate higher intensity electron beams and, consequently,
progressively lighter shades. In addition, suitable viewer-adjustable
controls are customarily provided in the television receiver whereby a
particularized contrast and brightness setting may be selected
according to viewer preference.
It is desirable that
the level of the luminance signal component corresponding to black in
the televised image be maintained at the cut-off of the image
reproducer. But even in those instances where there is a measure of DC
coupling, the DC components of the luminance signal coupled from the
video detector to the luminance channel may be degraded or otherwise
restricted due to the nature of the processing circuitry as well as to
other factors. Moreover, the luminance processing channel itself may
well permit a degradation or undesirable shift in the desired DC
characteristics. The result is that the DC level in the processed
luminance signal is not properly maintained, such that, upon application
to the image display tube, the black level is shifted to some
undesirable reference. This leads to less than faithful half-tone
reproduction on the screen of the image display tube. Gray tones can be
lost simply because they are beyond the cut-off of the display tube. In
other instances, blacks may appear as grays on the image display tube
screen.
Thus, it is desirable to make provision for
the maintenance of black level in the televised image at some
stabilized reference. Various systems are of course known in the art
for accomplishing this objective and take various forms and
configurations. For example, an arrangement commonly known as a DC
restorer circuit which includes a clamping device may be employed.
However, when the black level is effectively stabilized at the image
reproducer's cut-off bias point, the average level of the luminance
signal information may reach the point where excessive average beam
currents capable of severely damaging the image reproducer are
generated. In addition, the high voltage power supply during instances
of high beam current may be incapable of delivering the required beam
current. Such overloading reduces the power supply output voltage and
results in undesirable "focus blooming." That is, there will be a loss
of brightness, reduction of horizontal widths and severe defocusing of
the reproduced image. The problem in this regard has been further
compounded by the "new generation" high-brightness cathode-ray tubes
which require higher beam currents in order to illuminate the tube to
its fullest capability during high-modulation (white) scenes. In view
of the added demands on the high voltage power supply and the d
anger of damaging the image display tube, some method for effectively limiting the beam current is required.
Accordingly,
automatic contrast control systems have been developed which reduce
the gain of the luminance amplifier stage to prevent the generation of
excessive beam currents or increase the gain when under-modulated
signals are received. Most of these prior art automatic contrast
control systems, however, measure only the average level of the
luminance signals to derive the control signal utilized to vary the
gain of the luminance amplifier. Consequently, when all or a major
portion of the luminance signal's white content is of a high amplitude
level and is concentrated on a very small portion of the image
reproducer's screen, the control signal derived from the average
luminance level is low, permitting the luminance amplifier stage to
operate at nearly maximum gain. By concentrating the high-amplitude
white content into a small area of the screen, the image display tube is
likely to be overdriven during that period of time and "focus
blooming" will result. Some automatic contrast systems, on the other
hand, derive a control signal based on the peak amplitudes of the
instantaneous luminance signals without regard to the average luminance
level. Thus, while preventing blooming on high-amplitude white
content, such systems are susceptible to luminance signals which have a
dangerously high average level, but do not have any peak white signal
content of a level where the system would take corrective action.
OBJECTS OF THE INVENTION
Accordingly,
it is an object of the present invention to provide a color television
receiver having black level stabilization with a new and improved
automatic contrast control circuit which effectively overcomes the
aforenoted disadvantages and deficiencies of prior circuits.
A
further object of the invention is to provide an improved automatic
contrast control circuit which develops control signals effectively
varying the gain of a luminance amplifier stage to maintain an optimum
contrast, while preventing the generation of excessive beam currents in
the cathode-ray tube.
A more particular object of the
invention is to provide an improved automatic contrast control circuit
for continuously monitoring the average (DC) level of the luminance
signal information and providing a control signal representative thereof
to vary the gain of a luminance amplifier stage while remaining
sensitive to the amplitude levels of brightness components exceeding a
threshold level and modifying the control signal in accordance
therewith.
Another object of the invention is to
provide an improved automatic contrast control circuit which increases
the gain of a luminance amplifier stage during reception of
undermodulated luminance signals.
A further object of
the present invention is to provide an automatic contrast control
circuit of the foregoing type for deriving a variable DC control
potential from applied luminance signals which, upon application to the
luminance channel, adjusts the gain of a luminance amplifier stage in
accordance with the varying luminance signal requirements.
Still
another object of the invention is to provide a luminance processing
channel including automatic contrast control circuitry which may be
fabricated as a monolithic integrated circuit to provide an output
luminance signal having stabilized black level and optimum contrast
without producing excessive beam currents.
SUMMARY OF THE INVENTION
In
accordance with the present invention, an improved automatic contrast
control circuit is provided for varying the gain of an amplifier stage
in the luminance processing channel of a color television receiver
whenever the average DC level of the input luminance information varies
from a desired level, or whenever the peak amplitudes of the AC
brightn
ess
components of the luminance information exceed a predetermined
threshhold level. In a preferred embodiment, the automatic contrast
control circuit includes a gain-controlled luminance amplifier stage in
a luminance processing channel for translating instantaneous luminance
signals derived from received broadcast transmissions to an image
reproducer. The amplified luminance signals found at the output of the
amplifier stage have a stabilized black level. There are also provided
detector means coupled to the amplifier output for developing control
signals that are representative of the average DC level of the
instantaneous luminance signals. The control signals are then applied to
the gain-controlled amplifier stage to vary its gain inversely with
changes in the average luminance level. Finally, peak limiter means are
coupled between the amplifier output and the detector means to modify
the control signals whenever the instantaneous luminance signals exceed a
threshhold level. The modified control signals are similarly utilized
to effect inverse gain variations in the gain-controlled amplifier
stage regardless of the average level of the luminance signals.
GENERAL DESCRIPTION
Brief Description
This integrated circuit incorporates the following
features :
- a synchro and two video inputs
- a fixed video output
- a switchable video output
- normal Y, R-Y, B-Y TV mode inputs
- double set of R, G, B inputs
- brightness, contrast and saturation controls as
wellon aR,G, B picture ason a normalTVpicture
- digital control inputs by means of serial bus
- peak beam current limitation
- average beam current limitation
- automaticdrive and cut-off controls
Block Diagram Description
BUS DECODER
A 3 lines bus (clock, data, enable) delivered by the
microcontroller of the TV-set enters the videoprocessor
integrated circuit (pins 13-14-15). A control
system acts in such a way that only a 9-bit word is
taken intoaccount by the videoprocessor.Six of the
bits carry the data, the remaining three carry the
address of the subsystem.
A demultiplexer directs the data towards latches
which drive the appropriate control. More detailed
information about serial bus operation is given in
the following chapter.
Video Switch
The video switch has three inputs :
- an internal video input (pin 39),
- an external video input (pin 37),
- a synchro input (pin 41),
and two outputs :
- an internal video output (pin 40),
- a switchable video output (pin 42)
The 1Vpp composite video signal applied to the
internal video input is multi
plied by two and then
appears as a 2Vpp low impedance composite
video signal at the output. This signal is used to
deliver a 1Vpp/75W composite video signal to the
peri-TV plug.
The switchable video output canbe any of the three
inputs.When the Int/Ext one active bit word is high
(address number 5), the internal video input is
selected. If not, either a regeneratedsynchro pulse
or the external video signal is directed towards this
output depending on the level of the Sync/Async
one active bit word (address number 4). As this
output is to be connected to the synchro integrated
circuit, RGB information derived from an external
source via the Peri-TV plug canbedisplayed on the
screen, the synchronization of the TV-set being
then made with an external video signal.
When RGB information is derived from a source
integrated in the TV-set, a teletext decoder for
example, the synchronization can be made either
on the internal video input (in case of synchronous
data) or on the synchro input (in case of asynchronous
data).
R, G, B Inputs
There are two sets of R, G, B inputs : one is to be
connected to the peri-TV plug (Ext R, G, B), the
second one to receive the information derived from
the TV-set itself (Int R, G, B).
In order to have a saturation control on a picture
coming from the R, G, B inputs too, it is necessary
to getR-Y, B-Y and Y signals from R, G, B information
: this is performed on the first matrix that
receives the three 0.9Vp (100% white) R, G, B
signals and delivers the corresponding Y, R-Y, B-Y
signals. These ones are multiplied by 1.4 in order
to make the R-Y and B-Y signals compatible with
the R-Y and B-Y TV mode inputs. The desired R,
G, B inputs are selected by means of 3 switches
controlled by the two fast blanking signal inputs. A
high level on FB external pin selects the external
RGB sources. The three selected inputs are
clamped in order to give the required DC level at
the output of this firstmatrix. Thethree not selected
inputs are clamped on a fixed DC level.
Y, R-Y, B-Y Inputs
The 2Vpp composite video signal appearing at the
switchable output of the video switch (pin 42) is
driven through the subcarrier trap and the luminance
delay line with a 6 dB attenuation to the Y
input (1Vpp ; pin 12). In order to make this 1Vpp
(synchro to white) Y signal compatible with the
1Vpp (black to white) Y signal delivered by the first
matrix, it is necessary to multiply it by a coefficient
of 1.4.
Controls
The four brightness, contrastand saturationcontrol
functions are direct digitally controlled without using
digital-to-analog converters.
The contrast control of the Y channel is obtained
by means of a digital potentiometer which is an
attenuator including several switchable cells directly
controlled by a 5 active bit word (address
number 1). The brightness control is also made by
a digital potentiometer (5 active bit word, address
number 0). Since a + 3dB contrast capability is
required, the Y signal value could be up to 0.7Vpp
nominal. For both functions, the control characteristics
are quasi-linear.
In each R-Y and B-Y channel, a six-cell digital
attenuator is directly controlled by a 6 active bit
word (address number 6 and 7). The tracking
needed to keep the satu
ration constant when
changing the contrast has to be done externally by
the microcontroller. Furthermore, colour can be
disabledby blankingR-Y andB-Ysignals using one
active bit word (address number 2) to drive the
one-chip colour ON/OFF switch.
Second Matrix, Clamp, Peak Clipping, Blanking
The second matrix receives the Y, R-Y and B-Y
signals and delivers the corresponding R, G, B
signals. As it is required to have the capability of +
6dB saturation, an internal gain of 2 is applied on
both R-Y and B-Y signals.
A low clipping level is included in order to ensure a
correct blanking during the line and frame retraces.
Ahigh clipping level ensures thepeakbeamcurrent
limitation. These limitations are correct only if the
DC bias of the three R, G, B signals are precise
enough. Therefore a clamp has been added in
each channel in order to compensate for the inaccuracy
of the matrix.
Sandcastle Detector And Counter
The three level supersandcastle is used in the
circuit to deliver the burst pulse (CLP), the horizontal
pulse (HP), and the composite vertical and
horizontal blanking pulse (BLI). This last one is
regenerated in the counter which delivers a new
composite pulse (BL) in which the vertical part lasts
23 lines when the vertical part of the supersandcastle
lasts more than 11 lines.
The TEA5040S cannot work properly if this minimum
duration of 11 lines is not ensured.
The counterdelivers different pulses neededcircuit
and especially the line pulses 17 to 23 used in the
automatic drive and cut-off control system.
Automatic Drive And Cut-off Control System
Cut-off and drive adjustments are no longer required
with this integrated circuit as it has a sample
and hold feedback loop incorporating the final
stages of the TV-set. This system works in a sequentialmode.
For this purpose, special pulses are
inserted in G, R and B channels. During the lines
17, 18 and 19, a ”drive pulse” is inserted respectively
in the green, red and blue channels. The line
20 is blanked on the three channels. During the
lines 21, 22 and 23, a ”quasi cut-off pulse” is
inserted respectively in the green, red and blue
guns.
The resulting signal is then applied to the input of
a voltage controlled amplifier. In the final stages of
the TV-set, the current flowing in each green, red
and blue cathode is measured and sent to the
videoprocessorby a current source.
The three currents are added together in a resistor
matrix which can be programmed to set the ratio
between the three currents in order to get the
appropriate colour temperature. The output of the
matrix forms a high impedance voltage source
which is connectedto the integratedcircuit (pin 34).
Same measurement range between drive and cutoff
is achieved by internally grounding an external
low impedance resistor
during lines 17, 18 and 19.
This is due to the fact that the drive currents are
about one hundred times higher than the cut-off
and leakage currents.
Each voltage appearing sequentially on the wire
pin 34 is then a function of specific cathode current
:
- When a current due to a drive pulse occurs, the
voltage appearing on the pin 34 is compared
within the IC with an internal reference, and the
result of the comparison charges or discharges
an external appropriate drive capacitor which
stores the value during the frame. This voltage is
applied to a voltage controlled amplifier and the
system works in such a waythat the pulse current
drive derived from the cathode is kept constant.
- During the line 20, the three guns of the picture
tube are blanked. The leakagecurrent flowing out
of the final stages is transformed into a voltage which is stored by an external leakage capacitor
to be used later as a reference for the cut-off
current measurement.
- When a current due to a cut-off pulse occurs, the
voltage appearing on the pin 34 is compared
within the ICto the voltagepresenton the leakage
memory. Anappropriate externalcapacitor is then
charged or discharged in such a way that the
difference between each measured current and
the leakage current is kept constant, and thus the
quasi cut-off current is kept constant.
AverageBeam Current Limitation
The total current of the three guns is integrated by
means of an internal resistor and an external capacitor
(pin 36) and thencompared with a programmable
voltage reference(pin 38). When 70% of the
maximum permitted beam current is reached, the
drive gain begins to be reduced ; to do so, the
amplitude of the inserted pulse is increased.
In order to keep enough contrast, the maximum
drive reduction is limited to 6dB. If it is not sufficient,
the brightness is suppressed.
SPECIFICATION FOR THE THOMSON BI-DIRECTIONAL
DATA BUS
This is a bi-directional 3-wire (ENABLE, CLOCK,
DATA) serial bus. The DATA line transmission is
bi-directional whereas ENABLE and CLOCK lines
are only microprocessor controlled. The ENABLE
and CLOCK lines are only driven by the microcomputer.
THOMSON CHASSIS ICC5 Switched mode power supply transformer
A
switched mode power supply transformer, particularly for a television
receiver, including a primary winding and a secondary winding with the
primary winding and the secondary winding each being subdivided into a
plurality of respective partial windings. The partial windings of the
primary lie in a first group of chambers and the partial windings of the
secondary lie in a second group of chambers of a chamber coil body,
and the chambers of both groups are nested or interleaved with one
another.
1. A switched mode power supply transformer, particularly for a television receiver, comprising in combination:
a
primary winding and a secondary winding, with said primary winding
being subdivided into three partial windings and said secondary winding
being subdivided into two partial windings;
a chamber coil body having a plurality of chambers;
said
partial windings of said primary winding being disposed only in a
first group of said chambers, and said partial windings of said
secondary winding being disposed only in a second group of said
chambers, with each of said partial windings being disposed in a
respective one of said chambers;
said chambers of said first group being interleaved with said chambers of said second group such th
at
they alternate in sequence with said primary partial windings and said
secondary partial windings being alternatingly disposed in five
successive said chambers, so as to generate the major operating voltage
at said secondary winding;
an additional secondary winding for
generating a further operating voltage, said additional secondary
winding likewise being subdivided into a plurality of partial windings;
and,
said partial windings of said additional secondary winding
are disposed only in respective said chambers of said second group
below any of said partial windings of said secondary winding.
2. A transformer as defined in claim 1 wherein the total number of said chambers is six.
3.
A transformer as defined in claim 1 wherein the width of the narrowest
of said chambers is approximately 1 mm.
4. A transformer as defined in claim 1 or 2 wherein the widths of said chambers are different.
5.
A transformer as defined in claim 1 or 2 wherein the total width of
all of said chambers is only approximately 20 mm, whereby a flat and
optimally coupled transformer is realized.
6.
A transformer as defined in claim 1 wherein said additional secondary
winding provides an operating voltage for a load which has a
fluctuating current input.
7.
A transformer as defined in claim 1 wherein said partial windings of
said additional secondary winding are connected in parallel.
8. A transformer as defined in claim 1
wherein said partial windings of said primary winding are connected in
series.
9. A transformer
as defined in claim 1 or 8 wherein said partial windings of said
secondary winding are connected in series.
10.
A transformer as defined in claim 1 further comprising a plurality of
auxiliary primary windings disposed in one chamber of said first group
which is disposed in approximately the center of said first group and
above the said partial winding of said primary winding disposed in said
one chamber of said first group.
11.
A transformer as defined in claim 1 wherein all of said partial
winding disposed in said chambers of both said groups are wound with
wire having the same diameter.
12.
A switched mode power supply transformer as defined in claim 1 or 10
wherein: said coil body has six of of said chambers; said additional
secondary winding is subdivided into three said partial windings; and
two of said partial windings of said additional secondary winding are
disposed below respective ones of said partial windings of said
secondary winding and the third said partial winding of said additional
secondary winding is disposed in the sixth said chamber.
13.
A switched mode power supply transformer as defined in claim 10
further comprising at least one further secondary winding disposed in
one of said chambers of said second group above any partial secondary
winding present in said one of said chambers.
14. A switched mode power supply transformer, particularly for a television receiver, comprising in combination:
a
primary winding and a secondary winding, with said primary winding and
said secondary winding each being subdivided into a plurality of
partial windings;
a chamber coil body having a plurality of chambers;
said
partial windings of said primary winding being disposed only in a
first group of said chambers, and said partial windings of said
secondary winding being disposed only in a second group of said chambers
with each of said partial windings being disposed in a respective one
of said chambers;
said chambers of said first group being
interleaved with said chambers of said second group such that said
primary partial windings and said secondary partial windings are
alternatingly disposed in successive said chambers, so as to generate
the major operating voltage at said secondary winding;
an
additional secondary winding for generating a further operating voltage,
said additional secondary winding likewise being subdivided into a
plurality of partial windings, and said partial windings of said
additional secondary winding are disposed only in respective said
chambers of said second group below any of said partial windings of said
secondary winding.
15. A switched mode
power supply transformer as defined in claim 1 or 14 wherein each of
said partial windings of said primary winding contains the same number
of turns and each of said partial windings of said secondary winding
contains the same number of turns.
Description:
BACKGROUND OF THE INVENTION
The present invention relates to a switched mode power supply transformer, particularly for a television receive
r.
In
communications transmissions devices, particularly in television
receivers, it is known to effect the desired dc decoupling from the
mains by means of so-called switched mode power supply transformers.
Such switched mode power supply transformers are substantially smaller
and lighter in weight than a mains transformer for the same power
operating at 50 Hz, because they operate at a significantly higher
frequency of about 20-30 kHz. Such a switched mode power supply
transformer (hereinafter called SMPS transformer) generally includes a
primary side with a primary winding serving as the operating winding for
the switch and further additional auxiliary windings, as well as a
secondary side with a secondary winding for generating the essential
operating voltage and possibly further additional windings for
generating further operating voltages of different magnitude and
polarity. The secondary and primary are insulated from one another as
prescribed by VDE and have the necessary dielectric strength so that
there is no danger of contact between voltage carrying parts on the
secondary. A switched mode power supply (SMPS) circuit for a tv-receiver
is described in U.S. Pat. No. 3,967,182, issued June 29, 1976.
A
further requirement placed on such an SMPS transformer is that the
stray inductance at least of the primary winding and of the secondary
winding should be as small as possible. With too high a stray
inductance, a transient behavior may develop during the switching
operation which would not assure optimum switch operation of the
switching transistor connected to the primary winding and would endanger
this transistor by taking on too much power. Moreover, an increased
stray inductance undesirably increases the internal resistance of the
voltage sources for the individual operating voltages.
It is
known to design the windings for such transformers as layered windings.
Such layered windings, however, contain feathered intermediate foil
layers and, after manufacture, generally require that the coil or the
complete transformer be encased in order to insure VDE safety. Use as a
chamber winding in television receivers presently does not take place
because of the problems to be discussed below. A chamber winding would
have the particular advantage that it could be wound more easily and
economically by automatic machines. when using a chamber winding for a
switched mode power supply, the detailed insulation between the primary
and the secondary would be realized initially by two chambers with one
of these chambers being filled only with the windings of the primary
and the other of these chambers being filled only with the windings of
the secondary. However, with such an arrangement there would exist only
slight coupling between the primary and the secondary and thus an
undesirably high stray inductance. If, on the other hand, the number of
chambers were selected to be substantially larger, the transformer
becomes more expensive and unnecessarily large. Moreover, a larger core
would be required. Consequently, in the past, no television receiver
has been introduced that included an SMPS transformer.
SUMMARY OF THE INVENTION
It
is the object of the present invention to provide an SMPS transformer
designed in the chamber wound technique which permits economical
automatic winding, i.e. can be wound with but a single type of wire, has
a structure which is spatially narrow and as flat as possible,
provides the required insulation between the primary and secondary
windings, and has a low stray inductance. The transformer should not be
encased or saturated and nevertheless should produce no interfering
noise during operation. The transformer should be able to be held in a
circuit board without mechanical aids merely by its connecting
terminals which are soldered to the circuit board.
The above
object is basically achieved according to the present invention in that
the transformer for a switched mode power supply, particularly for a
television receiver, comprises: a primary winding and a secondary
winding with the primary and secondary windings each being subdivided
into a plurality of partial windings; and a chamber coil body with a
plurality of chambers; and wherein the partial windings of the primary
winding are disposed in a first group of chambers of the coil body, the
partial windings of the secondary winding are disposed in a second
group of chambers of the coil body, and the chambers of the first and
second groups are interleaved.
Due to the fact that the
individual windings or partial windings of the primary are disposed
only in chambers of the first group and the windings or partial
windings of the secondary are disposed only in chambers of the second
group, i.e. primary and secondary are distributed to separate chambers,
the necessary dielectric strength between primary and secondary is
assured. By dividing each of the primary and secondary windings to a
respective plurality or group of chambers and, due to the interleaved
or nested arrangement of the chambers of the primary and the secondary,
the desired fixed coupling between primary and secondary, and thus the
desired low stray inductance at the primary and secondary, are
realized. It has been found that a total number of chambers in the
order of magnitude of six constitutes an economically favorable
solution. With a smaller number of chambers, the coupling between
primary and secondary is reduced. With a larger number of chambers,
however, either the individual chambers become too small or the entire
transformer, and particularly the core, become too large.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a circuit diagram for a preferred embodiment of a switched mode power supply transformer according to the invention.
FIG.
2 is a schematic partial sectional view showing the distribution of
the individual windings of FIG. 1 to different chambers according to
the invention.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT
FIG.
1 shows a transformer intended for a switched mode power supply for a
television receiver with a power output between 40 and 150 watts. The
transformer includes a primary side P and a secondary side S which,
while maintaining the required dielectric strength of, for example,
10,00
0
V, are galvanically decoupled or separated from one another. The
primary side P includes a primary winding 1 which, as the operating
winding, will lie in the collector circuit of a switching transistor
switched at about 20-30 kHz. The primary winding 1 is divided into three
partial windings 1a, 1b and 1c which are connected in series. When
utilized in a television receiver, the beginning of partial winding 1a
and the end of partial winding 1c are connected into the collector
circuit of the switching transistor, while the taps between the partial
windings 1a-1b and 1b-1c are not utilized, but rather form supporting
points for the connection of the terminals of the partial windings. The
primary side P also includes an additional winding 3 which feeds the
feedback path with which the primary winding 1a-1c is designed as a
self-resonant circuit. Moreover, the primary side P includes an
additional winding 4 for regulating the moment of current flow in the
switching transistor in the sense of stabilizing the amplitude of the
output voltages on the secondary side S.
The secondary side S
initially includes the secondary winding 2 from which is obtained, via a
rectifier circuit (not shown), the main operating voltage U1. The
secondary winding 2 is divided into two series connected partial
windings 2a and 2b. Additionally, the secondary winding S includes a
winding 5 for generating an operating voltage for the video amplifier
and a further winding 6 for generating the operating voltage for the
vertical deflection stage of a television receiver. Moreover, an
additional secondary winding 7 is provided from which, after
rectification, the operating voltage or the audio output stage of the
receiver is obtained. Winding 7 comprises three partial windings 7a, 7b,
7c which are connected in parallel. The audio output stage of a
television receiver has a greatly fluctuating current input between 50
mA and 1000 mA so that the load of the secondary side S varies
considerably. This variation in load may effect an undesirable change in
the operating voltage U1 which also influences the horizontal
deflection amplitude. This undesirable dependency can be reduced in that
the coupling between winding 7 and winding 4 is dimensioned greater,
for regulating purposes, than the coupling between winding 2 and winding
4. This solution is described in greater detail in Federal Republic of
Germany Offenlegungsschrift (laid open application) DE-OS No.
2,749,847 of May 10, 1979. This increased coupling between windings 7
and 4 is realized in the present case by the three parallel connected
windings 7a, 7b, 7c. Finally, the secondary S includes a further
winding 8 which serves to generate, after rectification, a negative
operating voltage of -30 V.
FIG. 2 shows one half of the
chamber coil body 9 for the individual windings of FIG. 1, with the
body 9 including a total of six chambers 10. The size and particularly
the widths of the individual chambers 10 can vary with respect to one
another and the widths may all be different. Preferably, the width of
the narrowest chamber 10 is about 1 mm and the total width of all six
chambers is only approximately 20 mm so as to realize a flat and
optimally coupled transformer.
As shown, one third of the
primary winding 1, in the form of respective partial windings 1a, 1b
and 1c, is distributed to each of the first, third and fifth chambers
10 of the coil body 9. The additional primary windings 3 and 4 are
disposed in the third chamber 10 above the partial winding 1b. One half
of the secondary winding 2, in the form of respective partial windings
2a, 2b, is dis
tributed
to each of the second and fourth chambers 10 of the coil body 9. The
three partial windings 7a, 7b and 7c of the additional secondary
winding 7 for the audio output stage are distributed to the second,
fourth and sixth chambers 10, respectively, with the partial windings
7a-7c being disposed closest to the longitudinal axis of the coil body 9
and thus below any partial secondary winding 2a, 2b or other secondary
winding which may be located in the same chamber. That is, the partial
windings 7a and 7b are disposed below the partial windings 2a and 2b,
respectively, in the respective second and fourth chambers 10, and
below the additional secondary windings 5 and 8 in the sixth chamber
10. Further winding 6 is disposed above partial secondary winding 2b.
As
can be seen in FIG. 2, the chambers 10 contain alternatingly only
windings or partial windings of the primary side P or of the secondary
side S. The illustrated nesting or interleaving of the windings, i.e.
the alternating arrangement of windings of the primary side P and of
the secondary side S in successive chambers 10, assures the desired
close coupling between the primary side P and the secondary side S. The
arrangement of the windings 3, 4 in approximately the center of the
coil body 9 above partial winding 1b assures the desired close coupling
between the windings 3, 4 with the other windings.
In an
embodiment of the transformer shown in FIGS. 1 and 2 which was
successfully tested in practice, the individual windings were all wound
with the same diameter wire and contained the following numbers of
turns:
| ______________________________________ |
| Winding No. Number of Turns |
| ______________________________________ |
1a 22
1b 22
1c 22
2a 30
2b 30
3 3
4 10
5 25
6 1
7a 11
7b 11
7c 11
8 16
|
| ______________________________________ |
The
diameter of the wire of the windings 1-8 may be about 0.40 or 0.45 mm.
Also, each winding may exist of two parallel shunted wires each of 0.3
mm diameter. The width of the six chambers 10--seen from the left to
the right in FIG. 2--may be 0.95/1.95/1.75/1.95/0.95/2.75 mm and the
thickness of the walls forming the chambers 0.65 mm.
It will be
understood that the above description of the present invention is
susceptible to various modifications, changes and adaptations, and the
same are intended to be comprehended within the meaning and range of
equivalents of the appended claims.
THOMSON CHASSIS ICC5 REPAIRING / SERVICING NOTES:
icc5 (110deg) lg11 faulty cg11(1nf)
icc intermittent controls- replace membrane .
icc5 1 sec eht then stby try s/c pin5 micro pro to earth .
icc5 3 lines of scan at top of pic only il14 tea2029.
icc5 3 trips then off dl55(ba157)+cl58(47uf100v)+rv82(10r).
icc5 330nf s-correction cap, check j134 22v .
icc5 3trips/dead tda2030 .
icc5 3trips/dead ,test pin 4/11 to earth if < 700r loptx.
icc5 3trips/dead dl55 ba157,cl58 47uf100v rv82 (10r, on crt base pcb) .
icc5 3trips/dead l25, zpd10 zener diode.
icc5 3trips/dead tl17 bc548b in trip cct.
icc5 3trips/dead, cp24 47uf,100v from choptr base tp24.
icc5 bent sides ew coil,tda4950,dl41(byw76),dl46(by228),rl44(66+120r).
icc5 bent sides tda4950 ew ig01 dl42(ba157) 18k across it.
icc5 blank bright raster. 10r on crt base.
icc5 blank raster dots hot smell dl21/dl22.
icc5 blank raster no snd tda2541
icc5 blank raster no snd, osd & scart ok,tda2451-2.
icc5 blank raster,line across top, dl21(esm740g).
icc5 child lock “press red green blue then hold yellow 10 secs” .
icc5 cl44(0.44uf250v).
icc5 cl48(12n4f)+tda4950+tl17.
icc5 clicking on nicam add 47k between pins 13 & 16 ic1580 nicam pcb
icc5 cold hiss ds03(bb809).
icc5 cold top lines/foldover cl52 from pin 3 loptx.
icc5 cold tripping il14(tea2029c),
icc5 color cast/bright text tv41(1k).
icc5 dead lg11,cl44(300nf).
icc5 dead rp23+1n4148 dl28.
icc5 dead “88” showing, rp42 1r2 in psu,
icc5 dead 1a6t+cap next to 1r4w resistors in mains filter unit.
icc5 dead 330nf400v lg11 tda4950+fusible jl34(22r) .
icc5 dead bu508at.
icc5 dead choptr(tp24) dp37 tl31 rl10(115k).
icc5 dead cl44 300nf250v .
icc5 dead cl48 12.4nf +tda4950 + bc548b tl17.
icc5 dead cl48.choptr(bu508a),cp23.
icc5 dead coil,lg11, tda4950 tda4950 rl44, cl48 10.5nf cl44 300nf.
icc5 dead cp02(10nf250v) blue disc.
icc5 dead cp37(1000uf) 8v line.
icc5 dead dl55(ba157).
icc5 dead eht surge cp26(470uf16v) loc241
icc5 dead fp05 rp01 rp02 rp01 on scan coils.
icc5 dead front digits ok,line scan coil plug
icc5 dead fuse blown check degauss ptc.
icc5 dead fuse cp02 10nf blue disc cap.
icc5 dead led flash once cp26(470uf25v).
icc5 dead led flash, rr30 pins.
icc5 dead led flicks once,lg11+tda4950+cl44+rl46(1k)+rl44(56r+120r)+j134(22r).
icc5 dead lg11 cl44(33pf) rl44 ig01(tda4950) add 22r in place of ji34.
icc5 dead lg11 coil+rl44(56+120r)+tda4950+cl48(10n5)+cl44(300nf).
icc5 dead lo start volts at il14 ,dp45(zpd9v1).
icc5 dead loptr 2000a3 cl48
icc5 dead loptr cause loptx try discon pins 6/8/9/10 to prove.
icc5 dead loptr cause scan coils leak to field /ew raster coil.
icc5 dead loptr s2000af bend the corners of the heatsink away from choptx.
icc5 dead loptr+cl48 11nf(51k7) loptx rl10
icc5 dead loptr,cl42(360nf250v)
icc5 dead loptr= ew trans=lg11 ig01 rl44 120r+56r.
icc5 dead loptx, choptr bu508a, field thy, jungle chip, fucus/a1 unit
icc5 dead pulse of power at switch off cl44(330nf250v).
icc5 dead rl23 1r
icc5 dead rp23 w/wound,no line drive dl29(1n4148)
icc5 dead s2000a3+4*by255+pins+mains plug.
icc5 dead stby programme up button on tv front for 6 seconds.
icc5 dead stby ir73(mda2062).
icc5 dead stby lg11 ig01 tda4950 cl44 rl46 rrl44 j134 22r
icc5 dead stby tp45=4v(should be 11.5v) stby tx lp03 .
icc5 dead switching stby/on qr27.
icc5 dead throbbing lo ht 50v, 220uf385v mains cap.
icc5 dead tl17 bc548 il14
icc5 dead tl17(bc548)
icc5 dead tp15(bc548b).
icc5 dead tp45 11.5vn, the stby transformer lp03
icc5 dead tp45(bc649).
icc5 dead trip is41(tda2030)
icc5 dead tripping dl18(zpd36),tl31(bu508a),rp43.
icc5 dead/dark blank raster, cp37 4700uf25v
icc5 degauss posistor+1r0+1.6at.
icc5 disable trip by shorting tl17 collector to emitter.
icc5 eht stays up 10 secs/no digits.
icc5 eht stby, ic904(sl486)try reset use remote or hold ch up.”
icc5 eht surge only, try disconnect pin 4 loptx, field collapse
icc5 eht/htrs ok no brill,unplug field scan coils (scr to earth)
icc5 ew (tda4950) cause lg11 flashover.
icc5 ew bowing (59p7).dg 10 6.8 zener
icc5 ew bowing tda4950
icc5 ew coil 1r+6.5r
icc5 ew coil on 110 crt,cl44 330nf,rl44,56+120r,j134 22r,tda4950.cg11 inf
icc5 ew distortion rl44(120r+56r) cl 44 0.3uf tda4950 ig010 ew coil lg11,
icc5 ew j134(22r)+tda4950 dl42(ba159)+18k, ig01
icc5 ew lg11 110deg tubes cl44 330nf; rl44 56r+120r fusible; j134 22r, ig01 tda4950 ew
icc5 ew raster ,tda4950,cg11(1nf),dg13(1n4148),dl41(byw76),lg11,rg08(22r).
icc5 ew raster ig8,rg41(10r),tg62(bc547b).
icc5 ew raster lg11 dl46+dl41+lg11+rl44+cg11+ig01+cl41+cl44+j134(72r),ig01.
icc5 excess blue iv50 .
icc5 excess brill rv82(10r) crt base.
icc5 faint pic snd ok cv90,cp37
icc5 field cl22+rl22+cl52 1000uf.
icc5 field collapse (wavy line) scan coil plug
icc5 field collapse ,line nr top, rl33(3m3),il14.
icc5 field collapse cf01, 470nf,il14,rf01(3m)/rl33, scan coil pins.
icc5 field collapse dp47, bg22,bg36,cf01, scan coil pins.
icc5 field collapse rf01(3m).
icc5 field collapse rf21(820r),rl50(1r), loptx pins.
icc5 field collapse. rf01(3m).
icc5 field top cramp,cl22 rl22,cl52 1,000uf, 23v line.
icc5 field top foldover rf(1k).
icc5 flyback lines, tv50(bf422), dl22,cl22,rl22(1k5),tv81.
icc5 front leds pulsing rp42 (1r) o/c+dp41 o/c pins.
icc5 ha11498 changed to u4647/b1-tea5040
icc5 hot hum bar/field collapse. dp47
icc5 hot snd cracks (51k5), two screen cans on nicam pcb; pin 24 of main edge.
icc5 hot snow it20(tda6316ap).
icc5 hum/hissy snd pc1253 pins cs36 qs05.
icc5 inch of pic lhs, iv02(saa5243) on t/text.
icc5 int blue pic flyback pin 11 of crt base.
icc5 int color when setting pic geometry, mod change dv11 to 100pf.
icc5 int colour,dv21(1n4148)
icc5 int field collapse. dp47
icc5 int interference/lines tda4443
icc5 int line flashes across it20(u6316).
icc5 int nicam pc1253-001.is01 ta8662 is08 adc2300 pins
icc5 int nicam ta8662+adc2300 pins.
icc5 int no color dv21(1n4148).
icc5 int no pic, tuner
icc5 int no snd,headphone socket
icc5 int no start, earth pin28 il14 for tripped test.
icc5 int pic cv57(22nf).
icc5 int sides ew, loptx pins .
icc5 int snd cr56 .
icc5 int snd headphone socket pins.
icc5 int start lines at top,1.5k rl22 4.7nf cl22.cl52 1000uf.
icc5 int stby choptr tp24
icc5 int stby,choptr tp24. pins
icc5 int ticking snd/int mute, earth spkr grill.
icc5 int trip degauss positor .
icc5 int trips ,rl48(4k7).
icc5 int trips led flashing 6 times rl18 4k7 sm.
icc5 int trips,degaussing posistor.
icc5 interference pic ,tda4443
icc5 just osd tda2451-2
icc5 just snow c109(1nf).
icc5 led flashing 6 times,rl18(4k7sm)
icc5 line collapse 2″ dl41, ll46,rl46.
icc5 lineop disconnect ,dummy load tween dp41 cathode, chassis
icc5 lines across screen, pf14(100r) field cct.
icc5 lines flashing , tuner unit,it20(u6316). pll
icc5 low blue tea5040+mod kit.
icc5 low height il14(tea2029c), ty01(bf422).
icc5 low ht(158vn), rl10(115k).
icc5 low tuning voltage ci05(1nf).
icc5 low width cl44(300nf400v)+rl44(120r+56r)
icc5 low width cl54 680nf
icc5 low width, dg10,ig01(tda4950).,dl41(byw76).
icc5 low width/ew ,0.33uf250+td4950+4r7(rf14).
icc5 lop transistor getting hot ,bend h/sink corner away from choptx.
icc5 loptr running hot cause loptx magnetic field hitting heatsink, add shield.
icc5 loptr scancoils lg11/tda4950+,,,.
icc5 loptr(s2000af)
icc5 loptx arcing dst85b172/401416, hr6260
icc5 loptx dst85b243/473197_00= hr6373
icc5 loptx+bu508a choptr (chopper transistor).
icc5 loptx=hr6373/hr6067 dst85b243 473 197_00.
icc5 mod ha11498 changed to u4647/b1-tea5040
icc5 nicam (nasty) resolder earths on nicam pcb screen
icc5 nicam clicking , earth speaker .
icc5 nicam crackles ii71(tda4445b) is09 .
icc5 nicam=nasty inconsistant companded audio muckup
icc5 no 5v cp44(22nf)leaks.
icc5 no blue rv73(47k)
icc5 no blue tea5040 iv21. mod kit wve
icc5 no channel change. ic ir01.
icc5 no channel store ir01 .
icc5 no color chv5700 as panel.
icc5 no eht,loptx.
icc5 no ew correction. j134(22r),ig01(tda4950)
icc5 no fastext ir01.
icc5 no green tv62.
icc5 no line sync ql07 from pin 18 il14.
icc5 no luma/dark screen chroma subpanel.
icc5 no nicam pc1253 qs03(16m384hz).
icc5 no nicam snd poor mono snd c176 10uf inside if can
icc5 no osd rv02(47r) tv05(mps2369a).
icc5 no osd tv07,4v3 zener on text board
icc5 no osd/ttext, tv67(bc547c)
icc5 no osd/ttext. dv05 zener (zpd10) on text pcb.
icc5 no picture bc558b decoder
icc5 no picture dl21
icc5 no picture tv50 on decoder pcb
icc5 no pic/snd lt13 dt21(in4150).
icc5 no pic/snd. cp37(4700uf) .
icc5 no pic/snd/led digits, micropro ir01(ferg07)
icc5 no raster dl22(ba157) il14,rp42(1r).
icc5 no raster/snd cp37(4u700f)
icc5 no remote ,ir receiver remove c950(10uf) add link.
icc5 no remote ir rx (mod c950 with wire)
icc5 no remote ir73/ ir01.
icc5 no scart sound tba120t.
icc5 no sound even on scart tba120t
icc5 no sound just hiss. tda4453 in if can.
icc5 no sound rs13(4r7) tr57(bc558b) ts04 is08(adc2300).
icc5 no sound tba120t sound det chip
icc5 no sound tr57(bc558b), rs13(4r7), headphone socket.
icc5 no start.rp42 on main pcb – low volts to ic il14
icc5 no text cv05 rv43 rv44(0r22).
icc5 no text dv03(zpd4v3)/dvo5(zpd10v) .
icc5 no text/osd iv05 tv67(bc547c) dv05(zpd10)dv03(zpd4v3)
icc5 no text/osd. tv67 (bc547c)
icc5 no ttext/osd. dv05 zener (zpd10) on text pcb.dv03 zener zpd4v3
icc5 no tuning it20 (tda6316ap) no volts to tuner.
icc5 no tuning it20(tda6316ap).
icc5 no video text ok rv74 2r7
icc5 no video tv50.
icc5 no video,nicam pcb 3 connect pins, luma output (top);luma input (bottom).
icc5 no/int color dv21, r35.
icc5 ns raster rg42(1r5).
icc5 odd field coloured lines(1k5) nr thyristor
icc5 odd lines on pic , scart ok,u6316 pll chip it20
icc5 osd sync rv36(22k).
icc5 osg ir01 ir01 tr84(bc238-40).
icc5 picture flutter check cp37(4700uf).
icc5 pic ripple. tr107 l120.
icc5 poor ew,ew coil+tda4950 ,dl41(byw76), dl46(by228),rl44(66+120r)
icc5 poor focus loptx faulty
icc5 poor pic lo emission rv73 47kr 1w,
icc5 poor scart picture,add 6n8f63v across rs26.
icc5 poor sound cs05(22nf/100nf).
icc5 poor start+top lines rl22(1k5) cl22(4u7f)+cl52(1000uf).
icc5 pulsing sound = nicam unit.
icc5 pulsing. dl55 (ba157)
icc5 ragged verticals dv68 on text pcb
icc5 remote control, ir receiver sl466 ic
icc5 rhs crackling is10.
icc5 ripple on picture, tr107+l120.
icc5 rolling lines, dl22(ba157).
icc5 scart poor pic. add 6n8f63v across rs26.
icc5 set trips 3 times tl29(bc639), rl30(1r ).
icc5 slow start dp51(1n4002) 12v bridge.
icc5 smeary picture iv50(u4647b).
icc5 sound hiss, tda4453 in can.
icc5 sound popping add 47k between pins 13 & 16 of is08 on pc1253
icc5 sound stutter front of spk & mid spk mounting
icc5 sound int rhs front mounted headphone socket.
icc5 sparking from res nr coil in corner lg11
icc5 stby programme up button on tv front for 6 seconds.
icc5 stby cp46, dl52(ba157),rp46dp44(zpd5v6),mda2062).
icc5 stby eht surge ic904(sl486) .
icc5 stby loptr s2000a3 tl31,cl48 10.5nf
icc5 stby press prog up front for 6 seconds.
icc5 stby rp42
icc5 stby s2000a3 +cl48(10n5f)
icc5 stby s2000a3 loptr tl31+cl48(10n5)
icc5 telefunken 617 3trips loptx.
icc5 test discon loptx 8+10, bulb 100w pin8 to earth lites 3 times if ok.
icc5 text dropout iv28 dvt5403 ir01.
icc5 text line tearing dv68(zdp6v2).
icc5 text no osg tv07.
icc5 top 3 colored flyback lines dl21 thyristor
icc5 top cramp rf12(1k),il14.
icc5 tripped cp37 4,700uf was .
icc5 tripped rl10
icc5 tripping cl48(11nf).+loptx
icc5 tripping cp29(47nf).
icc5 tripping dl51(by397)/cg05.
icc5 tripping focus arcing.
icc5 tripping ir01(micropro).
icc5 tripping ir81(mc7805).
icc5 tripping lg11 tda 4950 +s2000af .
icc5 tripping loptr+cl48.
icc5 tripping loptx s/c pins 11/3.
icc5 tripping loptx+dp37(byw72).
icc5 trips (0u33f250v)+tda4950 .
icc5 trips (22uf250v)+rl23(1r) .
icc5 trips 3 times dead cp24 47uf100v drive coupler to tr24.
icc5 trips 3 times cp24(47uf100v) drive coupler to tr24 .
icc5 trips 3 times dead dl55 ba157 cl58 47uf100v rv82 10r .
icc5 trips 3 times dl25(zpd10).
icc5 trips 3 times dl55(ba157),cl58(47uf100v),rv82(10r)
icc5 trips cl16(3n3f) il14,dl51.
icc5 trips cp37(4700uf).
icc5 trips disable tl17 c/e. dl25 zpd10 zener 13v line monitor.
icc5 trips dl25(zpd10 zenner.
icc5 trips once stby rl44 56r hold mains sw for 3-4secs
icc5 trips quietly 0u33f 250v nr loptx, e/w coil tda4950
icc5 trips tp16(bc368).
icc5 tuning bad qt16(4mhz).
icc5 tuning no 33v voltage ,tt12 bc547
icc5 vcr flag waving ,use channels end in zero. ie 10, 20 etc.
icc5 warm no ew correction pg02 2k2
icc5 warm trips cl33(10uf25v)+cp23(2n2)
icc5 white raster check rv82.
icc5 white raster rv82.
icc5 width 1″ on lhs text ic iv02.
A SCART Connector (which stands for Syndicat des Constructeurs d'Appareils Radiorécepteurs et Téléviseurs) is a standard for connecting audio-visual equipment together. The official standard for SCART is CENELEC document number EN 50049-1. SCART is also known as Péritel (especially in France) and Euroconnector but the name SCART will be used exclusively herein. The standard defines a 21-pin connector (herein after a SCART connector) for carrying analog television signals. Various pieces of equipment may be connected by cables having a plug fitting the SCART connectors. Television apparatuses commonly include one or more SCART connectors.
Although a SCART connector is bidirectional, the present invention is concerned with the use of a SCART connector as an input connector for receiving signals into a television apparatus. A SCART connector can receive input television signals either in an RGB format in which the red, green and blue signals are received on Pins 15, 11 and 7, respectively, or alternatively in an S-Video format in which the luminance (Y) and chroma (C) signals are received on Pins 20 and 15. As a result of the common usage of Pin 15 in accordance with the SCART standard, a SCART connector cannot receive input television signals in an RGB format and in an S-Video format at the same time.This kind of connector is todays obsoleted !Consequently many commercially available television apparatuses include a separate SCART connectors each dedicated to receive input television signals in one of an RGB format and an S-Video format. This limits the functionality of the SCART connectors. In practical terms, the number of SCART connectors which can be provided on a television apparatus is limited by cost and space considerations. However, different users wish the input a wide range of different combinations of formats of television signals, depending on the equipment they personally own and use. However, the provision of SCART connectors dedicated to input television signals in one of an RGB format and an S-Video format limits the overall connectivity of the television apparatus. Furthermore, for many users the different RGB format and S-Video format are confusing. Some users may not understand or may mistake the format of a television signal being supplied on a given cable from a given piece of equipment. This can result in the supply of input television signals of an inappropriate format for the SCART connector concerned.
