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TELEFUNKEN (THOMSON) PALCOLOR SP212 STEREO CHASSIS 418 IS A THOMSON Chassis IKC2 stereo with a 90 ° CRT TUBE AND TELETEXT AFTER ADDED UNIT IN 1993.
This chassis was with small variants also used in brands and models:
BRANDT 36289B, 36291T, 42232T, 44231, 51203T, 55280P, 55281S, 63258T, 63281S, VCA40F
FERGUSON 41P3, A36F, A51F
NORDMENDE 36A-GALAXY, 40IMC, 40IMCVT, F19, F20
SABA 36C41, 36C904, 36T905, 55ES955, 63PL945, 70E991, M3702, T6345VT
TELEFUNKEN MP142, MP175, MP202, MP202S, MP211, MP215, MR212S, P320C, P330M, P331M, P350NV, S238, SM214, SN252
THOMSON 36201, 36210T, 36231T, 36241T, 36289T, 36291TB, 36C11, 36C41, 36C904, 36M907, 36ML10, 36ML11, 36MP11, 36MPS45, 36MPS46, 36MSE41, 36T905, 40231T, 40M901, 40MPS45, 40MSE41, 40MV11, 40MV16, 42210T, 42232T, 42250T, 42MPS45, 42MPS46, 44231PL, 44232T, 44M920, 44ML10, 44MP21, 44MPS41, 44MSE41, 44MV11, 44MV11S, 44MV22, 51203T, 51233T, 51M932, 51ML11, 51MPS45, 51MPS46, 51MSE41, 55251T, 55254T, 55256T, 55260PL, 55261T, 55265ST, 55280PLST, 55281T, 55292ST, 55AP11, 55DP21, 55ES955, 55FKC22, 55FPS30, 55FPS31, 55M940, 55M942, 55ML10, 55ML11, 55MLL0, 55MP11, 55MP45, 55MPS27, 55MPS28, 55MPS29, 55MS11TX, 55MV11, 55MV21, 55MV21TX, 55MXP43, 55MXP44, 63252T, 63258T, 63261T, 63281ST, 63283ST, 63DP21, 63ES966, 63M964, 63PS27, 63PS28, 70284ST, 70DP28, 70ES991, 70PS28, 7112, 7132, 7138, 72DP21, 7332, 7338, 8138, 8232, 8238, 8328, 8338, 8358, 8428, 8448, 8578, A5501, F3706, M3701, M3702, M3705, M3705S, M4006, M4506, M5105, M5105S, M5505, M5506, M5522, M5523, MP140, MP141, MP142, MP142S, MP155, MP162, MP162S, MP175, MP202, MP211, MP213, MP215, MR143, MR212, MR212S, SM214, TF5557, TF5571, TF5573, TF6353, TF6357, TF7253, TF7257, TS5125, TS5171, TS5575
WALTHAM TS3625PSN, TS3659PSN
TELEFUNKEN (THOMSON) PALCOLOR SP212 STEREO CHASSIS 418 (THOMSON IKC-2) Power supply with protection circuits This chassis is equipped with a line-frequency synchronized power supply with secondary regulation and included stand-by power supply. by power supply is used. When the mains switching transistor is switched on, energy is supplied via the bridge rectifier. transistor is switched through, and this energy is temporarily stored in the stored in the mains isolating transformer. During the blocking phase of the switch energy reaches the consumers on the secondary side via rectifier diodes. consumers. Special features of this concept:
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Low weight and volume.
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No separate stand-by transformer required.
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Voltage constancy (changes smaller than 2%).
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Multiple stabilized output voltages.
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Low sieve media consumption.
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Galvanic isolation from the mains.
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Low power consumption in stand-by mode (approx. 6 W).
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Control range from 180 U to 264 V.
(figure 1)
.The block diagram shows the function of the switching power supply both in stand-by mode and in operating mode. To be able to switch on the device remotely, the power supply for the function of the IR preamplifier and microcomputer must be guaranteed. In order to cover this small power requirement, the flyback converter operates in so-called burst mode. Here, pulse packets control the base of the TP29 transistor, which have different widths and frequencies depending on the mains voltage. These control pulses are generated by the standby regulator together with the standby oscillator. The stand-by regulator generates a sawtooth voltage whose amplitude and frequency depend on the mains voltage and the load on the secondary side. In order to control the power demand in the LP36 transformer, the stand-by regulator is regulated from the auxiliary winding (terminals 9/10). The sawtooth voltage from the regulator serves as the supply voltage for the oscillator and determines the burst frequency and burst width with its frequency. The oscillator oscillates sawtooth with a frequency of approx. 18 kHz. These pulses (G 7) are fed to the driver, which in turn drives the base of the switching transistor TP29 after current amplification. When switching from stand-by to normal operation, the control circuit increases the amplitude of the sawtooth and thus tries to compensate for the change in load until the control of the driver is taken over by pulses generated on the secondary side via LP42.
The stand-by regulator and the oscillator are now controlled by the voltage at transformer LP36, terminal 10, and the control voltage out of operation set. The generation of the line-frequency takeover pulses begins, after the horizontal deflection stage has operated and has supplied the quent-sawtooth-shaped signal "Ba" into the pulse generator. This, together with the system voltage "Usyst" and the voltage U2, 15 V, determines the pulse width of the takeover pulses (H 8). They enter the driver circuit via TP69, LP42 and trigger the the stand-by drive signal. Protection circuits In the event of the collector current of the switching transistor TP29 rising too high, the switching transistor TP29, the voltage drop across the RP32/RP34 activates the primary protection circuit TP18, TP19. 19. transistor TP29 is now no longer triggered. In case of over overvoltage or overload of the 13V busbar, U5, positive voltage is positive voltage enters the pulse generator via the protective circuit input "SP". pulse generator. This provides the supply of the line-frequency control signal for the drive signal for the driver. The power supply in stand-by mode. Power supply unit function description Stand-by mode After start-up of the unit by the mains switch the bridge rectifier DP01...DP04 supplies a voltage of 300 V via winding 2-7 of the transformer LP36, a voltage of 300 V to the coliector of the TP29. For the power supply of the small signal transistors in the primary power supply the bridge rectifier diode DP01 serves as the start-up voltage. diode DP01 serves as the starting voltage. It is fed via the RP06, RP36, RP35 into the filter capacitors CP07 and CP28. Stand-by rectification and oscillator While the transistors TP02, TP03 are still disabled, the charge current generates RP03, RP37 in CP08 generates a sawtooth shaped increase of the oscillator operating voltage. of the oscillator operating voltage at RP09. When the voltage reaches the voltage reaches 2.5 Vpp, TP09 switches via the voltage divider RP08, RP37 in CP08. voltage divider RP08, RP12 is
switched through for the first time. This also makes TP12 conducts, which in turn keeps TP09 in a conductive state until CP09 has discharged. CP09 thus shifts its potential difference steeply potential difference, because DP13 prevents rapid discharge. The negative voltage peaks now generated via CP09 reach DP14 and block TP09. DP14 and block TP13, which was previously blocked by the start-up voltage via RP06, RP13. voltage via RP06, RP13, which was previously in an idle state. After CP09 has discharged via the transistors TP09, TP12, they are again and the charging process of CP09 starts again. The operating state set with RP08, RP12 changes with the oscilla- supply voltage at RP09 and thus also shifts the switching point of TP09, TP12. switching point of TP09, TP12.
The frequency of the oscillator operating with TP09, TP12 is primarily determined by the sawtooth voltage of the oscillator at Measure point (G 4) and the time constant element RP09, CP09 be determined. It is at approx. 18 kHz. The standby regulator, consisting of consisting of TP03, TP02 draws from the mains isolating transformer LP36, connection 10, via DP30, RP38, CP30, RP07 and DP20. ning voltage. If TP02 is switched through by the rising current via RP02, then TP03 TP03 also switches through and draws the supply voltage of the oscillator. voltage of the oscillator down to 0.7 V with a steep edge. This causes a fast discharge of the CP08 via TP03, TP02. When 0.7 V is reached, both transistors are blocked and CP08 can be charged again via RP03, RP37. A new sawtooth new sawtooth is created, which, as described before, serves the oscillator as a working voltage for the oscillator. The frequency of the sawtooth is approx. 170 Hz. Driver and output stage circuit The transistor TP13 is driven by the output signal of the oscillator for for the conduction time of the switching transistor TP29 and switched through for the switched through for the blocking phase. TP13 controls the push-pull emitter follower. follower. A bootstrap circuit consisting of DP18, CP14 increases the efficiency of this circuit. The push-pull emitter The push-pull emitter follower, consisting of TP16, TP17, supplies the base current for TP 29. During the conduction phase, TP16 is switched through and TP17 is disabled. is blocked. During the blocking phase of TP29, TP16 is blocked and TP17 is conductive. The positive base current of TP29 charges CP24. The charging voltage is limited to 2.1 V by the diodes DP24, DP26, DP27. After TP17, CP24 generates a negative reverse voltage for the base of TP29 for the base of TP29. The coil LP 28 causes the base current in TP29 to increase according to an e function, thereby reducing its power dissipation. At the turn-off moment, LP28 rapidly withdraws electrons from the the base zone of TP29 and thus also reduces the dissipation. stance. A further contribution to the reduction of the shutdown losses is made by the attenuator CP29, DP31, RP33, RP 31. By recharging CP29, the collector is CP29 reduces the collector voltage rise and thus the power peak. power peak is reduced. If TP29 is connected through, a sawtooth current flows, starting from the bridge rectifier and CP06, a sawtooth-shaped increasing current flows through the storage inductance in the transformer LP. storage inductance in transformer LP36 (terminals 2/7), TP29, RP32, RP34 to ground.
Afterwards TP29 is blocked again. The collector voltage TP29 results from the sum of the DC voltage of approx. 300 V and the voltage induced by the secondary current flow. induced by the secondary current flow. In this phase, the energy is transferred from the from the primary to the secondary side of the mains isolating transformer LP36. tor LP36. Here, after rectification via DP50, DP65 and DP63, the reduced stand-by operating voltages are available. Power supply in full load operation In full load operation, the switching power supply is supplied by the line output stage line frequency via the line "Ba", CP57, RP57 and TP54. controlled. In order to reduce the collector current of the switching transistor TP29 at the switching transistor TP29 in case of a sudden full load (switching on the device from stand-by!). a soft start is performed first. This is controlled by TP 53, DP56, CP55 and TP54. When switching over from stand-by to full load operation, the emitter-collector path of the TP53 is low impedance the emitter-collector path of the TP53 is low impedance. Without CP55 there would immediately be a 5V voltage at the emitter of TP54 and TP 54 would immediately supply line impulses at the collector with maximum pulse width. Due to the charging time constant of CP55 the voltage rises only slowly in a sawtooth fashion to 5V and TP54 delivers line pulses with slowly increasing pulse width. The secu dary operating voltages Ul, U2, U2', U5, U3 and Us assume their setpoints. CP55 charges to 13V via RP59 and disables DP56. DP58 ensures a fast discharge of CP 55 when switching back to stand-by mode. TP53 regulates, damped by CP54, depending on the system voltage. CP54, depending on the system voltage, regulates the emitter of TP 54. This emitter is determined by a line-frequency sawtooth-shaped base- and a load-dependent regulated DC voltage at the emitter. the pulse width of the control signals for the switching transistor TP29. TP69 amplifies the pulses from TP54 and supplies them to the pulse transformer via the pulse transformer LP42 to the base of TPl3. The further signal processing when DP14 is disabled is the same as in the stand-by by mode and already explained. With PP52 the required system voltage {depending on the screen size) is set at the multipoint N 4. U 3 supplies a 7V operating voltage for the teletext decoder. However, this power rail is only released when the horizontal deflection stage is working and from there the voltage U5, 13 V, is available. It ignites via RP66 the thyristor TP 66, which now takes over the rectification of the pulses from LP36. Protection circuits Overcurrent protection circuit for TP29 If the collector current in TP29 rises above the maximum permissible value, then the voltage drop across the two reference resistors resistors RP32, RP34, so that the transistors TP18, LP36 and LP36, which are connected as thyristors transistors TP18, TP19 switch through. Via DP19 and the transistor TP19, the control pulses intended for the push-pull driver are driver are short-circuited to ground. A new start of the power supply is only possible when the capacitors CP28, CP30 and CP28, CP30 and CP07 have discharged. To do this, the unit must be disconnected from the mains for approx. three seconds. This protection circuit can be activated, for example, in the case of the following fault possibilities: Short circuit of DP50, DP63, DP65, LP36, TL19, DL13, LL05. The stand-by LED display remains dark or goes out dark or goes out within approx. 3 seconds. Mains voltage boost In case that pulse peaks are superimposed on the 220V mains voltage, they are are superimposed on the 220V mains voltage, they reach the base of TP19 via CP10, RP10 and activate the protection circuit through TP19, TP18. The stand-by LED goes out immediately.
Overcurrent protection circuit for the horizontal deflection stage In the event of a short-circuit in the horizontal deflection section the pulses at transformer LP36, terminal 10. CP30 discharges to such an extent that the transistors TP02, TP03 lock and are no longer switched. This causes CP08 via RP37, RP35 and RP36 to approx. 17V. This voltage can be a current into the base of TP12 via RP27, DP21, RP30. This switches through and prevents the standby oscillator from starting. by oscillator. Since TP29 is not affected by the horizontal deflection stage nor by the stand-by oscillator. from the stand-by oscillator, the complete power supply is out of power supply is out of operation. Overvoltage protection circuit Overvoltage is caused either by a defect of the vertical deflection or by a faulty regulator circuit in the secondary power supply. secondary power supply. In the event of a malfunction, the protection circuit described in chapter 2. SP", DP57, RP57 supplies a high level to the base of the TP54. the base of the TP54. This locks and thus no longer supplies a line- frequent control signal. The power supply now operates in the stand-by node. When the protection circuit is activated, the stand-by LED lights up constantly. steadily. Overcurrent protection for the AF output stages In case of a short circuit of Us, 28V, the diodes DP61, DP62 will also the voltage U2, 15V, is pulled to low level. The microcomputer IR 01 and the multifunction processor IV01 lack the operating voltage. voltage. The deflection stages are out of operation, because the control signal is missing. gnal is missing. Due to the load on the LP36, the stand-by regulator via regulator via DP20 is missing the control signal. At the breakpoint "G 4" the voltage rises the voltage rises to approx. 17V, DP21 becomes conductive and disables the stand-by oscillator. The power supply is switched off.
TELEFUNKEN (THOMSON) PALCOLOR SP212 STEREO CHASSIS 418 (THOMSON IKC-2) IR remote control
In this device series a remote control concept is used, which is characterized by service-friendliness and operational reliability. operational reliability. Characteristics:
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IR remote control for 64 commands
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Command output by 11-bit data words
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"Toggle-bits" for unique command recognition
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Clock oscillator with 400kHz
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Particularly low power consumption (active approx. 2mA,
stand-by approx. 2nA)
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Wide supply voltage range (2...6V)
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Low power, "flashed", pulse transmission The whole electronic of the IR remote control is composed of only a few few components, which guarantees a high operational reliability. is guaranteed. A mechanical key matrix supplements the electronic circuitry. In idle state, the driver outputs pin 13...19 of the IC01 with their "Open-drain" outputs are at low level. The "pull- up" sensor inputs, on the other hand, are on High level (pin 2-9). Pressing a key on the 8 x 8 matrix sets a sensor input to low and sensor input is set to low and a polling cycle is started. During the key matrix scan only one driver output is switched low. driver output is switched to low impedance. If the IC detects the actuation of a key, the oscillator starts to oscillate. oscillator starts to oscillate.
The oscillator mainly consists of an inverter inverter, which is extremely fed back with a ceramic oscillator. is. Cl and C2 ensure a short oscillation time over a wide supply voltage range. wide supply voltage range. The oscillator signal is a divider, whose output signal clocks the downstream counter. downstream counter. The respective counter reading is decoded, fed to the driver stage and is available at the outputs pin 13 to 19 for the for
interrogation of the key matrix. A signal detected in the sensor decoder (Pin 2 to 9) is taken over into the data memory. memory. This data is fed via a data multiplexer to the modulation counter, which uses the counter, which generates an 11-bit data word in pulse spacing modulation. bit data word, which, via an amplifier decoupled, which is decoupled via an amplifier and available at the output, pin 1. Figure 2 shows the 11-bit data word. The word interval is 121 ms. Tl and TO are toggle bits. With the toggle bits change, i.e. a new command is only accepted by the receiver when the a new command is only accepted by the receiver, if the new toggle bit differs from the old one. If the transmission path (e.g. a person passes between the IR transmitter and receiver diodes), the toggle bits diode), the state of the toggle bits will not change. change. From this the receiver recognizes that there is no renewed key actuation. key is not pressed again. The user will notice this interlocking especially during teletext operation. After output of the toggle bits, which also contain the reference time for the receiver, S2, S1 and time for the receiver, the data output is continued with S2, S1 and S0 as the address. address the data output is continued. The address is set to 3 x High. The remaining 6 data bits are used for command control. The 11-bit data word runs through IC1 at pin 1 and reaches the base of the output stage transistors Tl, R 2 to the base of the output stage transistors Tl, T2. If these are are controlled, a current of approx. 1A flows from the electrolytic capacitor C3 of approx. 1A flows through the IR transmitting diodes and the transistors to ground. ground. During the pulse pauses, C3 is recharged via the decoupling resistor R5. gresistor R5. The transmit frequency is set by the IR transmit diodes to 950 nm. by the IR transmitting diodes. The range of the transmission system is approx. 15m.
TELEFUNKEN (THOMSON) PALCOLOR SP212 STEREO CHASSIS 418 (THOMSON IKC-2) IR preamplifierThe IR preamplifier is used to process the received IR signals. signals. The output of the preamplifier is directly connected with the "interrupt" of the microprocessor, which is responsible for the logical evaluation of the incoming pulses. The circuit is designed interference signals are suppressed to a large extent. Special features: - Functionality even in direct sunlight. - Optimum suppression of interfering transmitters, such as fluorescent lamps, IR sound transmission and dimmed incandescent lamps. The receiving diode DA01 converts the incoming infrared impulses into an electrical an electrical quantity. Its internal resistance is determined by the incident light. In darkness, this value is in the megaOhm range in darkness, while in sunlight it is only a few kiloOhm in sunlight. To ensure that the operating point of DA01 is optimal over the entire here TA01 is interposed as a variable working resistor. connected. The control stage is designed in such a way that it only responds to DC or low-frequency signals. CA01 couples the AC voltage component to the downstream three-stage bandpass amplifier with TA03, TA07 and TA08. Their emitter circuitry has low-pass characteristics and sets the lower cutoff frequency to approx. 6kHz. Thus the low lying signal components are suppressed. The emitter resistors RA07, RA08 and RA11 are used for operating point stabilization. The operating point is determined by the voltage divider RA03 and RA02. The working resistor of TA08 with LA09, CA08 is connected as a selective circuit tuned to the fundamental wave of the transmit pulses of 56kHz. This gives the amplifier bandpass characteristics. The following amplifier section with TA12 is designed as low pass, so that higher frequency interferences are cut off. The following driver stage with TA13 has three tasks: it serves as a driver stage, peak rectifier and for the control voltage voltage for the automatic gain control. The time constant of RA16, CA14 is less than 5ms and therefore shorter than the smallest pulse interval of the IR transmitter. With this peak rectification ensures that interfering signals, signals smaller than the useful signal amplitude are not transmitted. are not transmitted. The capacitor CA19 forms a low-pass filter in conjunction with RA14, which limits short-term interference pulse peaks. A further time constant element with RA19, CA19 is used for broadening the of the output pulses to approx. 20μs, so that a safe "noise" can be switching transistor TA22 to ensure safe interrupt triggering in the microcomputer. microcomputer is guaranteed. The automatic gain control is dimensioned in such a way that TA08 is not overdriven in the last amplifier stage. From CA14 via RA16, RA17 the "AGC" reaches the amplifier directly via the TA06 to the amplifier TA07. The control time constant is determined by CA14, RA16, RA17. stant is determined by CA14, RA16 and RA17. This large control time constant is paralleled by a faster control branch via DA09. It is used to immediately compensate for very large signals, so that they do not the amplifier TA12, respectively the peak rectifier TA 13, RA16, CA14 before the actual control starts. starts. This control branch is only effective for very large signals. effective. The RC element RA24, CA24 is used for coarse filtering of the operating voltage. voltage. RA10 and CA03 additionally smooth the operating voltages of the first of the first amplifier stages.
Microcomputer-controlled operating electronicsThe 1 chip microcomputer IR01 located on the main chassis has a high processing speed of the versatile program with its 4 MHz clock frequency. processing speed of the versatile program. The explanation features, i.e. the software of the microcomputer, would go beyond the the scope of this circuit description. This information can be taken from the instruction manual. As can be seen from the circuit diagram, the power supply unit supplies in stand-by mode, the power supply provides the operating voltage U2 with approx. 10V. It reaches to the stand-by LED GE01 and via DR83, the series transistor TR82, DR82 stabilized to 5V to the VDD input, pin 42, of the micro- computer and to the IR preamplifier. In the absence of mains voltage the XR81 battery supplies the microcomputer with a backup voltage of 2.4V. of 2.4V. This voltage is also present at the RESET input, pin 33, while the HOLD input, pin 34, is set to low. This ensures that even in the event of a power failure, the 40 program locations stored in the RAM and the data stored in the RAM and the picture and sound settings selected by the user remain sound settings selected by the user remain stored. When remote control is active, an 11 bit data word is sent to the IR input, pin 35, from the IR preamplifier. preamplifier when the remote control is active. Only if this is within the time window specified by the μC and if it is provided with the correct address, the command is accepted. After actuation of the the power switch, 5V is immediately present at pin 42 (VDD). Now oscillates the IC-internal 4 MHz clock oscillator CP6. Time delayed via DR78 TR77, TR76 switch through and set the HOLD input, pin 34, to high level. The voltage rise at the collector of TR76 arrives as a positive pulse via CR73, RR73 at the base of TR 73 and switches it to low for a short time. This low level generates the RESET. This ensures that, when the pC starts operating the operating voltage and the clock frequency are correct. The The switch-on command for full operation is given either via the the IR input, or by the switching voltage of a video recorder to pin of a video recorder to pin 6 of the microcomputer. First the μC checks which way the switch-on command is given. If no IR signal is present and also the mains flip-flop (ON/OFF, pin 20) has not been set by the near control panel, then there has been a mains interrupt. interruption has occurred. This can also be caused by switching off and on by means of a mains switch. Now the μC checks whether the device was in standby or off mode was in standby or on mode before the power was interrupted. In the the latter case, it remains switched on at the selected program position. In the other case, the μC switches to stand-by. The The μC controls the switch-on function by means of a low level at pin 20, TR16 switches through TR17, which controls the stand-by voltage of approx. by voltage of approx. 10V to the multifunction processor IV01, pin 40, supplies. The power-on command is followed by 58 bit words via the I/O serial port, pin 40. accompanied by clock pulses at pin 41. This I2C bus determines with the first byte determines with the first byte the address for command control of the PLL or the VT decoder. The second control byte is followed by the byte for the band selection. Byte 4 and 5 determines the divider ratio in the PLL to obtain the tuner tuning voltage. The D/A converter is equipped with a five-channel pulse width modulator whose base frequency for the tint output, pin 1, is at 7.9kHz. For contrast, pin 2, color, pin 3, brightness, pin 4, and volume, pin 5, the basic frequency is 31.5kHz. All 5 output signals can be finely adjusted in 64 steps. steps. Downstream RC elements form variable control voltages control voltages for the corresponding functions. The volume as well as the mode selection stereo, mono, two-tone is done via the is done via the I2C bus. Instead of the formerly used display LEDs, this chassis concept uses the comfortable the comfortable "Picture Control System"(BRS) is used in this chassis concept. used. All operating and programming procedures are displayed on the large displayed on the screen. Here, too, the microcomputer From the RGB outputs, pin 22, 23, 24, the multifunction processor IV01 controls the picture tube. The Y-blank signal from pin 25 scans the back of the picture during the fade-in time. fade-in time the picture background black. In two lines 16 characters each, with a resolution of 64 pixels in 7 different colors. different colors, can be displayed. The vertical horizontal positioning of the fade-in is fixed in the microcomputer and cannot be and cannot be changed. For synchronous a horizontal pulse is applied to pin 26 and a vertical pulse to pins 27, 38. a vertical pulse. Nit LR03 at pin 28, 29 can be used to determine the line length of the insertion can be determined. As already mentioned, a video recorder connected via the Scart socket provides a horizontal connected via the scart socket supplies a 12V switching voltage to pin 8 of the scart socket during playback. pin 8 of the scart socket, which gives the switch-on command via RR64 at pin 6. the switch-on command via RR64 on pin 6. AV detect, Pin 7, accepts low level and the video and audio signal path on the scart interface board for the for the transmission of the signals at the scart socket.
The standard detection of the microcomputer is done via pin 17 and pin 18. according to the wiring of RR93 to RR97 the "ON-SCREEN" menu for single standard or multi-standard is activated. Pin 19 supplies low level in NTSC mode. A High-Pege1, supplied by the IV01 multifunction processor to pin 8 of the microcomputer, fits the the "ON-SCREEN" menu to the 60Hz deflection frequency. Low level at pin 37 mutes the FM tone on the stereo decoder and activates the AM tone activates the AM tone signal path if wired accordingly. Pin 35 is directly with the mute circuit connected. During the During the station search function, the sound is muted by low level. level. A high level signals to the microcomputer that a station has been found and a station and stops the station search. An IC-internal time loop switches the device to stand-by mode after approx. 5 minutes ("snooze function"). At When a key on the local control unit is pressed, pulses are sent to the command control from the A/D converter in the Keyboard-Input- Pin 13, 14, 15, 16. Pin 30 "TEST" is exclusively used for test programs used exclusively for test programs fed in by the production side. Chapter 5 VHF/UHF tuner with PLL The HF receiving section consists of a UHF/VHF tuner with built-in PLL. PLL. It is through a metal housing anti-interference next to the IF amplifier assembly on the chassis. net. The tuner, designed for the B/G standard, processes the following frequency ranges: - Band I - Band III - Band IV V 48,25... 84.25 MHz 126.25...294.25 MHz 471.25...855.25 MHz The HF input signal is split and routed to the UHF or VHF tuner. tuner. LH26 and CH02 couple the UHF signal into the input filter LH01, DH01 and CH03. Via CH01 the MOS- FET transistor TH04 at the gate receives the signal. Its source potential is by the UHF band switching voltage of TI11 via RH07, RH04 and RH06. CH06 decouples the now preamplified UHF signal to the RF two-pole filter consisting of DH01, CH07, LH07, DH01, CH08 and LH08. The mixing stage with TH14 forms from the input signal and the oscillator signal coming from TH16 via CH17 at the emitter the IF signal. The 1st IF circuit CH44, LH44, CH45, LH43 couples the the IF signal via DH46, RH46, CH 86 and the emitter follower TH 93. low impedance via terminal 3 of the tuner to the IF module, terminal l. In the VHF signal path, there is first an IF blocking circuit with CH31, LH31. It is followed by a low pass filter switchable with DH58 for band I and III. pass filter, consisting of CH58, LH58, LH59, CH59, LH61, LH62, DH61, LH57, DH57, CH61. The upper cutoff frequency is 300 MHz. The diodes DH55 and DH56 protect the MOS-FET transistor TH 65 from voltage peaks. TH65 is the first amplifier stage after the low-pass filter. The IF module supplies the two preamplifier transistors TH65, TH56 and TH65. TH65, TH04 an AGC control voltage for protection against overload. overload. The signal amplified in TH65 is fed back to the IF module via the band I and III and tuned with DH57, DH57. two-pole filter to the mixing transistor TH75. Transistor TH87 works as an oscillator. This couples its frequency via RH87, CH87, CH78 to the VHF input signal to the base of mixer TH75.
A two-pole filter with CH77, LH81, CH84, LH82, CH83 supplies the IF signal signal coming from the mixing transistor via the decoupling diode DH83 to the first IF amplifier stage TH 93. PLL circuit The circuit concept used here includes a 1-chip PLL with integrated prescaler and three band selector outputs (Bd. I, Bd. III, UHF). For a tuner tuning operation, the control unit- microcomputer supplies the divider and band data via the data bus in four four 15 bit shift registers of the PLL IC II06, pin 14/15. process takes place with each channel- or Program- ' place call and repeats itself periodically. The I2C bus contains five bytes for calling up a program location. Byte 1 gives the address, byte 2 and 3 contain control bits and the tape infor- formation, byte 4 and 5 define the tuning voltage at pin l and thus the thus the receive frequency. The band select transistors TI14, Bd.I, TI13, Bd.III and TI 11, UHF, are activated by the PLL-IC. From the oscillator signal applied to pin 4 and the 4MHz- reference signal (pin 16), a comparison quantity for tuner tuning is formed and tuning and is fed to the operational amplifier at pin 18. to the operational amplifier. The operational amplifier works as a switch and acts for the 30V signal connected to pin 2 via RI 10 at pin 2 as a controllable load resistor. Thus a tuning voltage of 0.5 to 30V is available for the tuner. is available for the tuner. If the frequency at the output of the programmable part changes as a result of a tuning process, controlled by the data bus, at the output of the programmable divider, the tuning voltage of the tuner is the tuner oscillator is controlled by the tuning voltage until the oscillator is until the oscillator frequency and the divided crystal frequency are identical again. are identical again. The smallest tuning step is 62.5 kHz. This means that the 7 MHz bandwidth of the VHF standard radio can be tuned in 112 fine standard can be tuned. IF amplifier The IF amplifier consists of the decoupling emitter follower TH93 in the tuner. the emitter follower TH93 in the tuner, the preamplifier TI10 with downstream surface wave filter FI19 for the picture and QI 30 for the sound. for the sound. Due to its physical and electrical properties, the surface physical and electrical properties, the surface acoustic wave filter replaces conventional LC in IF signal processing. At the output of QI30, the image the 38.9MHz image carrier and the 33.4MHz audio carrier are selectively audio carrier with 33.4MHz are available. The outputs pin 4, pin 5, of the FI19 couple the image IF signal symmetrically to the image IF IC II20. II20. A three-stage regulated wideband amplifier feeds the IF signal into the image carrier controlled demodulator, whose external resonant circuit FI20 is tuned to 38.9MHz. Above a two-stage video amplifier with a low-pass characteristic the video signal to pin ll for further signal processing. coupled. Adjustable with PS21, the RF preamplifiers in the tuner receive the delayed AGC from pin 5 of the IF block. An AFC is not necessary because of the frequency synthesizer tuning system. necessary. The audio IF signal processing is performed by IC II71. Here, according to the quasi-parallel tone method, image and sound carriers are combined. are combined. The oscillating circuit FI30 at pin 8 and 9 supplies the carrier frequency carrier frequency required for demodulation. Pin 12 is used for further the audio IF signal with 5.5MHz and additionally with 5.74MHz for stereo for stereo additionally with 5.74MHz.
TELEFUNKEN (THOMSON) PALCOLOR SP212 STEREO CHASSIS 418 (THOMSON IKC-2) Sound signal processing and mutingStereoderoder The stereo decoder module includes the follo
wing functional groups: - Two FM IF amplifiers with demodulator (TBA 120 UB) - Pilot frequency decoder for stereo and two-tone with matrix for left-right separation of left-right information (TDA 6600) - I2C bus controlled tone adjuster with surround sound section and Scart input Demodulator At input BA04, connection 10, of the stereo decoder module the audio IF frequencies 5.5MHz and 5.74MHz (for stereo/two-tone) or 6.5MHz for OIRT tone transmitters are available frequency modulated. Since without switching information in the case of 6.5 MHz IF, this should also be demodulated. demodulated, a 6.5 MHz ceramic filter QS01 is required in the 5.5 MHz input branch. 6.5MHz ceramic filter QS09 is connected in parallel with QS01 and in series with the 5.5MHz reference circuit (FSOS/CH08), a resonant circuit (FS10/CS10) tuned to 6.5MHz. tuned to 6.5MHz (FS10/CS10) (Attention, this applies only to devices for devices which are factory equipped with the reception possibility transmitters at the factory). The circuits are damped in such a way that that the output LF just matches the amplitude of the following IC amplitude of the following IC IS30. At a deviation of 50 kHz it amounts to approx. 300 mV. Via a diode matrix (DS01/DS02/DS03/DS04 /DS11) the demodulator IC's IS10 and IS01 can be muted with low level at pin 2 via three control paths: 1. from the mute circuit via DS03. 2. data bus controlled via DS04. 3. sound standard controlled by microcomputer IR01 via DS02. For devices in multi-standard version, e.g. demodulated AM- sound signals can be fed as AF to pin 3 of IC IS01. Uon pin 8 of the ICs TBA 120 UB the AF signals are fed to the stereo decoder IC TDA 6600. Stereo decoder In stereo mode the L + R signal is fed to IC IS30, pin 23, and the pin 21 the 2R signal, accompanied by the modulated 54kHz pilot tone. tone. Here the right and left signals are processed in the stereo matrix. signals are processed in the stereo matrix, and in two-tone mode the channels l and 2 are are separated. The outputs pin 2 and pin 6 supply the AF signal galvanically decoupled via CS20/CS23 to the scart socket, connection l/3 and via CS50/CS51 to IC IS60. PS35 is set to lowest crosstalk. For evaluation of the pilot tone CS17 to the oscillating circuit FS38, which is tuned to the pilot carrier frequency. FS38, which is tuned to the pilot carrier frequency. From there, the 54kHz pilot sig- nal via pin 20 into two PLL loops. Here the evaluation of the evaluation of the modulated pilot carrier. 117Hz for stereo and 274Hz for two-tone. Four IC-internal demodulators support this task. task, whereby the capacitors at the mixer outputs pin 14/15/17/18 determine the bandwidth and thus the signal-to-noise ratio. determine. The PLL is supplied with line pulses at pin 13, coming from the diode splitter transformer. from the diode splitter transformer. The external wiring of the PLL time constant is connected to pin 11 for stereo and to pin 10 for dual tone. 10. the degree of noise suppression for stereo is set with CS25 at pin 9. For two-tone CS24 at pin 8 takes over this task. The IC-internal digital evaluation stereo/mono/two-tone delivers the information to the matrix and to the four-level input/output, Pin 7. Data bus controlled IC IS60 signals coming from pin 2 at pin 7 with OV forced mono. IC IS30 on the other hand supplies via pin 7 6V for stereo, 3V for dual tone and l.3V for mono. Tone control The control of IC IS60 is done via the I2C bus pin 24, 25 and the four level lines at pin 2. At the input pin 1, pin 3 there is a two-channel AF analog switch for switching between between TV mode or scart playback. A subsequent switch is used to switch between channel 1 or 2 for multi-channel multi-channel audio broadcasts. Next in the signal path is the surround sound circuit, the at Nono signal a spatial, stereo-like sound impression. This function can be switched and switched on. The spatial sound circuit consists of one operational amplifier per amplifier per channel. The first amplifier (output pin 21) has an internally IC-internally fixed gain of -1. The second amplifier is switchable amplifier is switchable between gain -l and a gain selected by gain selected by RS55. The surround sound effect is is achieved by connecting the input of the second amplifier via the the bandstop RS50/RS51/CS52/RS52/RS53/CS53/RS54/CS54 a signal via the bandstop rs50/rs51/cs52/rs52/rs53/rs54/cs54 and the phase inverted signal via the bandpass CS56/RS58/CS55/RS 57 the phase inverted signal is fed. It amplitude is linear, but the phase is inverted by 180° at medium frequencies. 180° at medium frequencies.
The tone and volume control per stereo channel consists of three operational amplifiers with electronic potentiometers. The volume setting is made - for both channels separately - in 64 steps. A balance adjustment can thus be made by different by adjusting both channels in different ways. The aurally correct (physiological) volume characteristic is achieved by linking the volume the volume setting with the treble/ bass setting. adjustment. In the case of treble and bass settings, the following is achieved by means of an external circuit with one capacitor each. in 31 steps each. The IR01 microcomputer, based on the IS60 sound adju IS60, the information mono/stereo/two-tone is displayed on the screen via the I2C bus. Two-tone is displayed on the screen via the I2C bus. The connections Pin 13, 15 couple, galvanically separated by CS61/CS65 the NF signals to the NF power amplifier ICs IA05/IA25. IC's IA05/IA25. NF power amplifiers Both output stages are identical in design. The NF-IC's work as operational amplifiers with negative feedback path; they are short-circuit short-circuit proof and thermally protected. The sine output power is lOW at 8 ohms. To suppress disturbing switch-off noises in the loudspeaker, the microcomputer IR01, Pin 20, sends a high level via RA13 high level via RA13/RA15 to the base of the TA15. This srhaltet RA03/RA04, RA23/RA24 to the AF input, pin 1, of the IC. pin 1 of the ICs. Thereby the LF output stages are immediately disabled. Mute Since the chassis must comply with legal requirements, a mute circuit blocks the sound a mute circuit blocks the audio channel as long as no standard television signal is television signal is received. This mute circuit should only evaluate the FBAS signal coming from the IF section. signal coming from the IF section. Teletext, on-screen text or video signals fed in externally via the the Scart socket must not influence the sound cutoff. must not influence the sound cutoff. The mute circuit is realized with the transistors TM03, TM 12, TM16, TM18. At the same time it generates the search STOP im pulse. TM03 is controlled via RM01, CM02 with the FBAS signal from the IF module, terminal 6. It acts as a pulse separator and and supplies the horizontal and vertical synchronous pulses to an electronic electronic bandpass filter, which is tuned to 15625Hz. At the collector of the TM12 a sinusoidal horizontal- frequency control voltage for the switching stage with TM16 and TM18. TM16 periodically becomes conductive and charges CM17 (2.2 μF) via RM17, whereupon TM18 remains conductive as long as H-synchronous pulses are present in the control signal. control signal are present. The 12V voltage reaches the mute input from the collector of TM18. input, terminal BA 04-17, of the audio module and as STOP signal pin 36 of the IR01 control processor as a STOP signal for the station search. the snooze circuit (automatic switching to standby after 5 seconds). (automatic switching to standby after 5 minutes without a transmitter signal). activated.
TELEFUNKEN (THOMSON) PALCOLOR SP212 STEREO CHASSIS 418 (THOMSON IKC-2) Video signal processingFrom output 6 of the IF amplifier, the FBAS signal passes through the 5,5MHz-lock ( sound carrier) CV63, LV63, RV63, and RV62 to the connection connection 13 of the Scart interface board. Decoupled with CE11, the the FBAS signal from pin 3 of the IC IE10 via pin 2 and RE11 to the to the Scart socket, pin 19. External video si- gnals are fed to connection 20 of the Scart socket. Lying, from the IROl microcomputer is high at connection 7 of the scart interface faceplate, transistor TE10 switches through and applies a low level to pin 5. and applies a low level to pin 5 of the IE10. In this case the internal internal video signal passes the video switch to pin 6 of the IC. At low level at pin 7 of the scart interface board, the external video signal is at the Scart socket is switched through. From connector 10 of the scart interface board the video signal is fed through via RV27, RV 28, the Y-delay line VV28 and CV71 the video signal is connected to pin 58 of the multifunction processor IC IV01. Integrated in VV28 there is a 4.43 MHz trap. Consequently, the Y-signal without color information is Y signal without color information. In SECAM mode, the 4.25MHz trap LV29, CV29, TV29 is also activated. By TV65, CV65, LV 64, RV64 the Y-signal is differentiated and via CV68 at pin 56 is added to the Y-signal in the sharpness stage. The amount of the the resulting frequency boost in the Y-signal path is determined by the pin 55 with PV58. At pin 59 takes place, voltage controlled, the contrast is set, whereby the color saturation is the color saturation is also changed at the same time. An IC-internal matrix forms a color difference matrix from the Y-signal and the already the RGB signals from the supplied Y-signal and the already low-frequency color difference signals. External RGB-H signals from the Scart connector or "picture control sy- stem" signals from the control unit microcomputer reach the multi-function unit via pin 47, 49, 51 and 53 to the multifunction processor. The "Fastblan- king" signal on pin 53 determines whether the video input signal or the the RGB signals are routed to the picture tube control. The brightness adjustment is DC-controlled at Pin 48, while in the capacitors CV49, CV51, CV52 at Pin 44, 45, 46 a DC voltage is stored for black level control. is stored. After horizontal and vertical reverse darkening, the RGB signals leave the the RGB signals leave the multi-function processor at pins 41, 42, 43. function processor. A downstream low-pass filter frees the RGB signal from any the RGB signal from parasitic oscillations above 5 MHz. above 5MHz. From here the RGB signals are transmitted via connector BV01 to the picture tube plate. Beam current limitation Depending on the beam current, the following occurs at the base point, connection 4, of the high voltage winding of the diode split transformer via RL08 a negative control voltage, which is converted into a positive one by the voltage via RL05 into a positive one. It reaches the contrast controller via RL 06, CV81, DV81 and with PV79 adjustable to the contrast control input, pin 59. This automatically prevents an excessive increase of the beam current in the picture beam current in the picture tube. Chroma signal processing The IV01 multifunction processor includes a multistandard chroma decoder chroma decoder, as well as an automatic color standard recognition which can be used for PAL, Secam, NTSC 4.43 MHz (Videore- NTSC 3.58 MHz (transmitter), activates the respective color decoder. activated. The device version shown in the enclosed circuit diagram processes PAL and PAL and SECAM B/G signals. From the Scart interface plate, the FBAS signal reaches the chroma filters. chroma filters. A special switch circuit is required for each standard. is required for each standard. The PAL chroma filter, consisting of RC24, LC24, CC24, CC25, RC26, LC26, CC26 and CC53 provides the required 4.43 MHz bandwidth. 4.43 MHz bandpass characteristic. In the Secam signal path RC22, CC22 contains the bell filter characteristic for this standard. CC23, LC23, RC23 and CC48. The PAL signal path leads from pin 20 via a regulated amplifier stage. amplifier stage. This is necessary to compensate for slightly different IF passband curves or receiver tuning, the color difference signals are always signals always in a certain relation to the Y-signal. to the Y-signal. As "actual value signal" for the control, the burst amplitude for the PAL- the burst amplitude is used for the PAL signal and for the frequency-modulated Secam- signal the total signal is used. CC47 and RC47 serve as filter for the control voltage. The controlled chroma signal reaches the standard identification with the burst part. To the identification signals on the rear black shoulder are used for this purpose. shoulder are used. Here, the individual standards differ standards differ characteristically from one another. The identification The identification circuit in the decoder consists of three modules:
-
Phase discriminator for comparing the burst phases of PAL and
NTSC-H signals with the reference signal.
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Frequency discriminator for deriving the H/2 signal in seram-
transmissions.
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H/2 demodulator for PAL and Secam signal with logic circuitry
for the actual identification.
The IC contains one identification circuit each for PAL, Secam and NTSC. At the external capacitors CC57 (Pin 22), CC58 (pin 23), CC62 (pin 27), the DC voltage levels applied there indicate the voltage level at synchronized reference oscillator the recognized standard. A logic circuit supplies at pin 10, 11 and 21 a switching voltage corresponding to the Chroma standard. Pin 21 is not used with this chassis concept. With PAL, TC34 switches through and blocks TV29, so the 4.25 MHz trap is ineffective. MHz trap is ineffective. Via the logic connectors, by applying external voltage levels, the voltage levels, according to the Chroma standard table, the Chroma standard must be selected by force: Standard Logic connection Identification connection Pin Pin 10 11 22 23 27 PAL 6V 6V 12V 6V 12V Secam 6V OV 6V 12V 6V NTSC 4,43MHz 0V 6V 6V 6V 12V NTSC 3,58MHz 0V 0V 0V 0V 12V In SECAM mode the IC works with horizontal identification. If pin 18 is terminated with a resistor to ground, the IC is automatically switched to horizontal or vertical identification vertical identification according to the requirement. After standard detection and burst blanking, the chroma signal from pin chroma signal from pin 14 via CC44, RC44, phase adjustable with LC43 to the PAL delay line VC43. This delivers the signal delayed by one line, amplitude adjustable with PC44, via pin via pin 12 to the color signal demodulator. In the matrix, to obtain the two carrier-frequency components F (B-Y) and F (R-Y), the IC-internally looped signal and the signal delayed by one line with VC 43 is added and subtracted respectively. In the (R-Y) demodulator is the PAL switch, which is used to control the phase position of the carrier-frequency signal component F (B-Y) and the component F (B-Y) and F (R-Y) is reversed. The demodulators are synchronous demodulators, which are fed from the from the 4.43 MHz reference carrier generated by CQ66, pin 26. are switched. When sequential Secam signals are received, they are sent directly to the cross switch (permutator). This supplies the two synchronous demodulator stages in an alternating sequence from line to line. from line to line the undelayed signal and the signal delayed by VC43. signal. For frequency demodulation of these signals quadra- quadrature demodulators, each consisting of a phase shifter circuit at pins 4 and 5 (VC43). phase shifter circuit at pins 4 and 5 (B-Y) and pins 8 and 9 (R-Y), respectively, and a multiplier stage. the Secam reference circuits rotate the phase of the corresponding color signal. phase of the corresponding color signal at the respective unbundled frequency. 90°, so that the signal voltage at the demodulator output disappears. disappears. With Secam decoding, two deempha- CC01 at pin 1 (B-Y) and CC02 at pin 3 (R-Y) are switched on. connected. NTSC signals take the same signal path as PAL. For NTSC 3.58MHz a 3.58MHz reference carrier crystal is required at pin 28. is required. The multifunction processor supplies the color difference signals from pin 2 and pin 64. color difference signals from pin 2 and pin 64 via one low pass each LL03, RC03, CC04, CC 03 and RC07, LC07, CC07 to pin 60, 62. They are used to remove any existing HF residues are eliminated. After clamping of the (R-Y) and (B-Y) signals in the IC, they pass through a controllable amplifier, which is externally the color saturation externally from pin 7. externally from pin 7. Then the color difference signals are mixed with the Y-signal in the RGB matrix. signals are mixed with the Y-signal in the RGB matrix. RGB output stages The positive RGB output signals supplied by the IV01 video processor IC RGB output signals delivered by the video processor IC IV01 have to be RGB output stage transistors TT11, TT21, TT31 to drive the picture tube. inverted. Since all three video output stages are identical the blue output stage will be explained for the purpose of this will be explained.
In order to ensure a good constancy of the amplification factor and the working point, it is necessary that the amplification of the power amplifier is amplification of the power amplifier without negative feedback is sufficiently is sufficiently large. For this reason the present AB output stage was chosen. The TT31 transistor amplifies the video sig nal to approx. 70 Vpp. Rising signal edges reach the cathode via TT27, RT28 and LT28 to the cathode, while falling signal edges via via DT28, RT28 and LT28 to the picture tube. This type of of the picture tube cathode and improves the frequency response in the cathode capacitance and improves the frequency response in the high frequencies. The gain (white balance) of the red and green output stages is set with PT11, PT21; the gray balance with PT12, PT22. These settings may influence each other slightly and should therefore be repeated should therefore be repeated alternately. Transistor TT33 serves as a common low impedance footpoint of the RGB output stage. If the device is switched off or into stand-by mode, the collector will be mode, from the collector of the protection switching transistor TV02 via DV47, DT32, DT31 to the base of the TT33, so that the TT33 is so that the TT33 is blocked. Thus the complete RGB output stage is deenergized and the and the screen is dark. A flashing of the screen at the moment of flashing of the screen at the moment of switch-off is thus largely prevented. Flare suppression During normal operation CT03 is charged via RT10 and DT04, limited by DT03 limited, charged to 150 V. After decommissioning the or return to the stand-by node, the voltage U4 (180V) is very voltage U4 (180V) decreases very quickly. In CT03 a charge so that at grid 1 of the picture tube minus 150 V is present for a longer period. minus 150 V for a longer period. Thus the screen remains dark after dark after switching off. Automatic black level and gain control (Auto Cut Off) In modification to the preceding explanations, some models are equipped with this additional device models are equipped with this additional circuit. The IC ID01 is a special circuit to control the automatic black and white automatic black and white level control. Since the DC operating point and the amplitude of the RGB si- gnals must match, a clamp is required in each channel. is required in each channel. With the positive edge of the negative vertical return pulse at connector pin BD 04, after signal inver- tigation in in TD31, the cut-off function is started at pin 18 of the IC. started. The control compensates the drift of all video stages, including the video output stages. including the video output stages. The control loop works in parallel for all RGB stages, invisible for the viewer, during the image change. In terms of time, the start of the black level control is line 18 of the 23 lines of vertical rewind. vertical rewind. The clock signal is provided by the line pulses fed to pin 13. pin 13 serve as the clock signal. During the 18th and 19th line the IC supplies at pin 22, 26, 30 for black level measurement for the RGB output stage. In lines 20 and 21 the white value is measured in the same way. measurement. To process the control pulses, the IC requires a DC voltage at pins 2, 4 and 6 a DC voltage level of 3V. Pin 15 is connected during during the measuring time (18th to 22nd line) to IC ID12, pin 9, 10, 11, 11. This now supplies from the voltage divider RD11, ID11, RD 14, PD11, RD13 the required 3V-DC level. The measuring resistors of the RGB output stage PT12, RT09, PT22, RT19, RT30 provide a voltage drop proportional to the cathode current. This voltage drop is fed to IC ID01 via pins 19, 23, 27 and is compared there compared with two reference voltages. As comparison voltage voltage is 9.5V for the black level and 5V for the gain. and a voltage of 5V for the gain control. This results in a ratio This results in a ratio of 1:10 between the black and white value measurement. The The difference between the DC voltage level at pins 2, 4 and 6 and the voltage drop and the voltage drop at the measurement resistors is used for the black the black level in the capacitors CD 01, CD02, CD03. for the black level. The capacitors CD04, CD06 and CD07 store the voltage for the white value. voltage for the white value. According to the level of these voltages IC ID01, individually adapted to the picture tube, adjusts the gray and gray value and white value. The amplitude of the RGB output signals determines the white level and is is adjustable with PT12, PT22. The DC voltage applied to the RGB signal DC voltage under the RGB signal determines the gray value. This can be set with PD11. adjustable.
TELEFUNKEN (THOMSON) PALCOLOR SP212 STEREO CHASSIS 418 (THOMSON IKC-2) Horizontal deflection stage with east/west correction circuitryThe drive signals for the horizontal output stage are processed in a PLL function processor IV01 in a PLL circuit. A VCO (Voltage Controlled Oscillator) oscillating at 503 kHz. voltage controlled oscillator) supplies via a divider line-frequency pulses. A phase comparison compares these with the the frequency of the line sync
pulses from the amplitude sieve. If there is a frequency or phase deviation of the VCO, a control voltage pulls it the VCO, a control voltage is applied to the VCO until the two frequencies match exactly in frequency and phase. Externally at pin 37 operates the 503kHz ceramic oscillator QL45. For filtering the VCO CL43, RL44 and CL 44 are connected to pin 36 for filtering the VCO control voltage. line return pulses from the diode split transformer LL05 via RL38, RL41, CL41 at pin 38 determine in phase comparison the start of the line on the screen. on the screen. With PL39 the basic setting of the horizon- tal position (-phase). At pin 39 the processed line-frequency square-wave im- pulses are fed out. Decoupled with DL17, they reach TL17 via RL 16, CL16 to TL17. The horizontal driver transistor TL17 amplifies the pulses to amplifies the pulses in order to supply the necessary base required base saturation current for TL19. The RC element RL18, CL18 attenuates the voltage peaks that occur when TL17 is switched off. voltage peaks that occur when TL17 is switched off. Transistor TL19 operates as a switch with diodes DL21, DL22 are connected in parallel. This prevents an inverse operation of the transistor is prevented. In addition, the diodes are part of the 0/W diode modulator(110° devices). The function of the horizontal deflection circuit in the steady state is circuit in the steady state. The most important components are marked as follows: - BL01 = Horizontal deflection coil - CL24 = Forward and tangential capacitor - CL21/22 = Return capacitor - TL19 = Switching transistor - DL21/22 = Switching diode The effective flyback capacitor during the blocking phase of TL19 is formed by series connection of CL21 and CL22. Voltage and current waveforms during the time interval of one line are shown in Figures 3 and 4.
The following sequence can be seen: At the end of the forward propagation time tl, TL19 is disabled by a corresponding base drive signal. The stored energy in the coil and the diode-splitting transformer leads to a rapid charging of the return charging of the return capacitor. At the end of the first return half at time t2, the charge reaches the maximum value. value. The current passes through the zero point and changes direction during the second return half. direction during the second half of the return flow. Now the return capacitor discharges capacitor discharges and shifts the energy back into the deflection deflection coil (resonant circuit principle). At the end of the return t3 the voltage passes through zero and takes on negative values. At DL21/22 become conductive and prevent the so-called "inverse operation" of the The return capacitor CL21/22 is short-circuited via the diodes and is short-circuited via the diodes and the run-up phase begins. The circuit energy is in the deflection coil. During the half of the outward phase, current flows from the deflection coil via DL21/22 into the via DL21/22 into the forward capacitor CL24 and charges it. This process is completed at t4 in the middle of the picture. The current changes its direction and flows from CL24 via TL19 into the deflection coil. via TL19 back into the deflection coil. Precondition is however, that TL19 is controlled accordingly at the base. For the defi- at the end of the outward run t5, TL19 receives a negative impulse from the receives a negative pulse from the driver stage at the base, which is which is slightly advanced in time. During this period the base zone of TL19 be cleared of charge carriers very quickly. Practical execution of the circuit In addition to the basic function of the horizontal deflection three further functional groups are to be considered to be considered: 1. the L-C-R circuit, consisting of LL23, CL23, RL23 attenuates harmonics. During the line scan they could lead to modulation and vertical dark interference stripes on the screen. on the screen. 2. 2. to at vertical lines of a grid test pattern at black/white jump to prevent "mousing", additional energy is fed into the deflection circuit via RL27, RL28, CL27 and LG08. deflection circuit. 3. to compensate the east/west pincushion distortion the 0/W-IC IG01 of pin 5 provides a line-frequency pulse width modu- lated signal. modulated signal. This signal is applied via the coupling coil LG08 to the capacitor CL24 and causes a vertical-frequency parabolic distortion. vertical-frequency parabolic modulation of the deflection current.
The energy required for the deflection process is supplied by LL05 from the winding 3/2, which generates the required magnetic energy. energy from this. On the secondary side, rectifier diodes the secondary operating voltages are obtained from the line pulses. The integrator RL40, CL12 generates for the control in the secondary power supply dary power supply. At DL40 line imp- pulses, limited in amplitude by DL40, DL41. In the circuit of the high-voltage winding, terminal 4, there is the the reference resistor RL08. A negative voltage is generated at this resistor negative voltage, which is compensated by a positive voltage across compensated by a positive voltage across RL05. The control voltage at RL08 pin 59 of IC IV01 determines the maximum beam current. beam current. East/west pincushion equalization The conditioning of the east/west drive signal is done in IC IG 01. From the difference of the input currents of pin 1 (vertical- (vertical sawtooth) and pin 2 (adjustable DC voltage) a parametric of the multiplier. If the arithmetic mean value of the sawtooth current at pin 1 is equal to the current at pin 2, a symmetrical parabola is formed at the output of the multiplier (Figure 5). parabola (Figure 5). With PG04, an east/west trapezoidal correction can be performed (Figure 6). (Figure 6). The output current of the multiplier causes a stray current at the external impedance. The output current of the multiplier produces a voltage proportional to the current at the externally connected impedance. This voltage is fed into the downstream comparator with a linear horizontal frequency sawtooth voltage. The DC voltage The DC position of the sawtooth voltage can be changed by PG01. It influences the image width (figure 7).
The pulse width modulated signal from the comparator controls the output stage output stage operating in D mode. The integration of the line output signal at pin 5 is integrated by the coupling coil LG08 coupling coil and the CL24 capacitor. As negative feedback, which is also used for east/west amplitude adjustment, the impulse the pulse width modulated output signal is fed via RG06, PG06 with signal is connected to CG06 via RG06, PG06. The parabolic voltage generated at CG05 is added to the signal at the multiplier, pin 7, added. For static and dynamic image width a control signal proportional to the beam current is applied to pin 7 via RG07. This signal is fed from the base of the high voltage winding at transformer LL05. of the high voltage winding at transformer LL05, pin 4. Chapter 9 Vertical deflection stage with protection circuit Control of the Uertical Output Stage The multifunction processor IV01 supplies the 50Hz uertical syn- chron pulses via pin 31, RF26 to the base of the switching transistor TF25. During the vertical flyback phase TF25 switches through, so that capacitor CF06 is switched on via the now conductive transistor transistor TF08 and RF27 to the voltage level defined by RF04, RF27. voltage level. For the time of the vertical run-up TF25 and TF08 are blocked. During this period, CF 06 charges itself via RF01, RF02 with an almost constant current. This results in the vertical 8-saw tooth shown in oscillogram K 4, the amplitude and linearity of which amplitude and linearity of which has a direct influence on the current in the vertical vertical deflection coil. The capacitor CF02 causes at the end of the vertical deflection coil. Through it the transistor TF08, which is blocked at the beginning of the vertical run-in. is bypassed at the first moment. This wet measure prevents a speed modulation at the speed modulation at the beginning of the image. The linear vertical sawtooth now arrives via RF05 and pin 3 at the plus input of the the positive input of the 1st differential amplifier in IC IF01. The output, pin l, is connected as negative feedback branch via RF14 to the negated input of the differential amplifier. With the the amplitude of the vertical sawtooth at the output, pin 1. at the output, pin 1, of the differential amplifier can be determined. be determined. The sawtooth at pin l is decoupled by RF13, with the negative feedback component generated at RF23, RF20 from the amplifier via RF13 and fed to the negating comparator input at pin 5. input at pin 5. The positive input of the compara tor, pin 6, line-frequency sawtooths are fed via CF11, RF13, which are supplied for vertical position stabilization with a DC voltage from the from the vertical output stage via RF15, RF13. The PF04 adjuster determines the vertical position, RF12, DF03 and DF 02 are used for temperature compensation. In teletext mode a 25Hz signal supplied by the videotext decoder sets the line jump jump auper operation.
In Mix mode or during TV reception, the interlace is interlace is active. The differential amplifier 2, which works as a modulator, is offered three input signals three input signals are offered: - Vertical sawtooth (fig. 8) - Horizontal sawtooth (figure 9) - Vertical position correction clamping. Figure 10 shows the principle operation of the Module- ator. The modulator works as a comparator. Its Switching threshold is at approx. 10V. From the beginning to the the end of the image, the line-frequency saw teeth exceed the switching threshold of the line higher and higher the switching threshold of the comparator. At the output a line-frequency pulse-width modulated signal is generated. is generated. These switching pulses are decoupled with DF15 and serve thyristor TF16 as a control signal. Vertical output stage The deflection coil is connected as a bridge from the operating voltage U5, 13V, to the voltage generated in the transformer winding 5/6, the actual generator. the generator itself. It is DC coupled. The LL05 transformer thus provides all the energy for the Uertical deflection. The generator winding in LL05, connection 5/6, supplies line impulses with approx. 280 Vpp. pulses with approx. 280 Vpp. They are alternately supplied by the diode during the by the diode DF16 during the line retrace and by the thyristor TF16 during the by the thyristor TF16. Two extreme states shall illustrate how a bipolar current in the deflection coil: 1. the thyristor is not fired. 2. the thyristor is always switched. In the 1st case we have to do with a normal clamping circuit. to do. Terminal 6 of the diode split transformer winding would be connected only during the during the horizontal return to ground. At terminal 5 of LL05 we would have the voltage waveform shown in Figure ll. The integrator LL19, CF25 would produce a high voltage at CF25. voltage at CF25. Thus, a large current, starting from CF25 via the deflection coil and RF20/23 into CF24 (U5', 13V). flow. This case actually occurs during the vertical the electron beam as fast as possible to the start position of the next image at the position of the next image at the upper edge of the image. ken. In the 2nd case, the diode split transformer winding 5/6 with connection 6 is always connected to ground. Figure 12 shows the average DC voltage of 0 is 0 V. In this assumed operating condition, a current in the reverse direction would now be fed from CF24 (U5', 13V) via RF20/23 and the deflection coil into CF25. Both borderline cases show that3 this circuit enables allows current to flow in both directions through the deflection coil. in both directions. For linearity reasons the possible control range is used only minimally. At CF25 maximum voltage values of 13V plus/minus approx. 10V (13V to 23V for the upper half of the image, 13V to 3V corresponds to the lower half of the image, Figure 13).
The horizontal frequency residual components are negligible, since the reactive part of the vertical deflection coil for line frequency is very high and practically is very high and practically does not allow any current to flow. How is a vertical sawtooth generated from horizontal frequency line pulses? vertical sawtooth? At the beginning of the picture, at the upper edge of the picture, the modulator delivers to the gate of the thyristor, which enable the diode to regulate the voltage in the diode to clamp the voltage in the integrator LL19/CF25 to approx. to approx. 23V. With the further written line the gate the gate drive signal, whereby the clamping time of DF16 becomes shorter. becomes shorter. Proportional to this, the resulting clamping voltage in the integrator in the integrator decreases continuously. The result is the verti- ka1 sawtooth component, which drives the current through the vertical deflection coil. coil (figure 14). The line-frequency quenching of the fired thyristor occurs with each line return pulse from winding 5/6. Operating point stabilization and tangent equalization The negative feedback signal results from the voltage drop at the reference resistors RF20/RF23 and is fed via RF13 to the negative input of the input of the differential amplifier 2 via RF13. temperature response of the vertical amplitude. A further negative coupling via RF22, RF19 ensures constant image height in the event of a span change of U5'. voltage change of U5', 13V. The tangent correction is performed by DF17, DF19 and RF19. the vertical center of the image, the voltage drop across the reference resistor RF20/23 is so small that no current flows through the diodes. In the upper and lower quarters of the image, the threshold values of DF 17, DF19 are exceeded. The now conducting diodes increase the the deflection current decreases, and the tangent current caused by the image The tangent error caused by the shape of the image screen is compensated.
Protection circuitThe transistors TV01, TV02 connected as a thyristor form a a protection circuit. In the idle state, both are disabled. The protection circuit is activated in case of: a. Overvoltage of U5 (13V) b. Overcurrent from U5 (13V) 1. overvoltage protection If the system voltage Ul (143V) increases as a result of a defect in the control circuit of the secondary (143V) increases due to a defect in the control circuit of the secondary power supply unit, then the tionally to the U5 (13V) voltage. Via RV02, DV02 after the Z-voltage of DV08, TV02 and TV01 is exceeded. switched through. The high level now at the collector of TV01 DL16 blocks the diode DL17, so the line output stage lacks the is missing the drive signal. At the same time the high level at the collector of the TV01 is routed via the "SP" line DP 57, RP57 to the base of the TP54. base of TP54. This blocks and disables the control circuit of the secondary power supply out of operation. The power supply now operates in stand-by mode. The protection circuit operates in the same way if the thyristor TF16 is not activated or is interrupted. is interrupted. As already explained, in this case an excessive voltage arises in the integrator. LL19, CF25, which is then fed back via the vertical deflection coil, RF20. deflection coil, RF20, RF23 and RF24 raises the U5 (13V) voltage. 2. overcurrent protection In case of short circuit of the switch TF16, DF16 or continuous high level at the gate of thyristor TF16, a low level is set at CF25. low level is set. As a result, the voltage at CF is reduced. Transistor TV12, which is always blocked during trouble-free operation, switches through. during fault-free operation, switches through and activates the protection circuit with its now activates the protection circuit TV02, TV0l.
TDA6600-2
TDA6200
BOTH SIEMENS
TV Stereo Decoder with Matrix TDA 6600 2 (TDA6600)
SIEMENS
Preliminary Data Bipolar IC
The TDA 6600-2 includes an advanced decoder for the identification signals for the
multichannel TV sound systems according to the dual-carrier system as well as a matrix
switched by the decoder to provide the L-Ft-information.
Features
0 Increased switching reliability and recognition by means of two PLLs for stereo
(117 Hz) and / or dual channel (274 Hz)
0 Separate bandwidth selection for dual-tone (pins 17-18) and stereo (pins 14-15)
0 Separate setting for the PLL time constants for dual-tone (pin 10) and stereo (pin 11)
0 Adjustable cut level for dual-tone (pin 8) and stereo (pin 9)
0 Cross-talk rejection independent of external component accuracy
0 Adjustment to minimal cross-talk level through external DC voltage
0 Suitable for TV sets with a 15625-Hz signal.
Type Ordering Code Package
TDA 6600-2 Q67000-A8210 P-DlP-24
Circuit Description
The circuitry has two functional sections:
Two phase locked loops for generating the required comparison frequencies (54.96
kHz and 54.8 kHz) from the line frequency. The phase detectors of the control loops
operate in a frequency range of 117 Hz and/or 274 Hz.
Four demodulators to evaluate the 54-kHz pilot signal. The capacitors at the mixer
outputs determine the bandwidth (and thus the signal-to-noise ratio) of the pilot tone
recognition.
An evaluation circuitry for decoding "stereo", "dual sound", and "mono" from the mixer
output levels. ln order to assure interference-free operation in case of high noise level
input signals, the individual signals "stereo" and "dual sound" are delayed via an
externally adjustable integrator. The subsequent digital evaluation provides the
information "mono", "dual sound", or "stereo" to the matrix and the 4 level input/output
(to drive the TDA 6200). If this four level input/output is connected to ground externally
(e.g. by the TDA 6200), the decoder will recognize this signal as "forced mono".
A stereo matrix with deemphasis and SCART output switched by the pilot frequency
decoder. The SCART output can be disabled by a MUTE signal (coincidence).
SIEMENS TDA6200 TV Stereo Tone Control IC with Quasi-Stereo Section,
Channel 1/2 Switch, SCART Input, and I2C Bus Control
Features
0 Treble, bass, balance, and volume control by means of an integrated digital-to-analog
converter
I Quasi~stereo circuit during mono operation
0 Stereo basewidth expansion during stereo operation
O Physiological volume control
I Channel 1/2 switch-over during dual audio transmission
0 SCART connection
0 Control of all functions via the IZC bus and the bidirectional 4 level line of the
TDA 6600-2 (stereo demodulator IC)
O LED driver
0 Volume control range 80 dB
0 Treble, bass control 1 ‘I2 dB
O Channel separation min. 60 dB, cross-talk rejection min. 60 dB
O Parasitic voltage spacing up to 78 dB
Type W W Ordering Code Package
TDA 6200 Q67000-A2461 P-DIP-28
The TDA 6200 is comprised of a SCART switch-over, channel 1/2 switch-over, quasi-
stereo circuit, stereo basewidth expansion, physiological volume control, a treble, bass,
and volume control of the injected AF signals as well as an LED driver. The IC is
controlled by means of an FC bus serial interface as well as by the bidirectional 4 level
line from the TDA 6600-2. The component is used for AF sound signal processing in
stereo TV sets.
PHILIPS SAA5231 Teletext video processor:
GENERAL DESCRIPTION
The SAA5231 is a bipolar integrated circuit intended as a successor to the SAA5030. It extracts Teletext Data from the
video signal, regenerates Teletext Clock and synchronizes the text display to the television syncs. The integrated circuit
is intended to work in conjunction with CCT (Computer Controlled Teletext), EUROM or other compatible devices.
Features
· Adaptive data slicer
· Data clock regenerator
· Adaptive sync separator, horizontal phase detector and 6 MHz VCO forming display phase locked loop (PLL)
The function is quoted against the corresponding pin number.
1. Synch output to TV
Output with dual polarity buffer, a load resistor to 0 V or + 12 V selects positive-going or negative-going syncs.
2. Video input level select
When this pin is LOW a 1 V video input level is selected. When the pin is not connected it floats HIGH selecting a
2,5 V video input level.
3. HF filter
The video signal for the h.f.-loss compensator is filtered by a 15 pF capacitor connected to this pin.
4. Store h.f.
The h.f. amplitude is stored by a 1 nF capacitor connected to this pin.
5. Store amplitude
The amplitude for the adaptive data slicer is stored by a 470 pF capacitor connected to this pin.
6. Store zero level
The zero level for the adaptive data slicer is
stored by a 22 nF capacitor connected to this pin.
7. External data input
Current input for sliced teletext data from external device.
Active HIGH level (current), low impedance input.
8. Data timing
A 270 pF capacitor is connected to this pin for timing of the adaptive data slicer.
9. Store phase
The output signal from the clock phase detector is stored by a 100 pF capacitor connected to this pin.
10. Video tape recorder mode (VCR)
Signal input to command PLL into short time constant mode. Not used in application circuit Fig.4a or Fig.4b.
11. Crystal
A 13,875 MHz crystal, 2 x data rate, connected in series with a 15 pF capacitor is applied via this pin to the oscillator
and divide-by-two to provide the 6,9375 MHz clock signal.
12. Clock filter
A filter for the 6,9375 MHz clock signal is connected to this pin.
13. Ground (0 V)
14. Teletext clock output (TTC)
Clock output for CCT (Computer Controlled Teletext).
15. Teletext data output (TTD)
Data output for CCT.
16. Supply voltage VCC (+ 12 V typ.)
17. Clock output (F6)
6 MHz clock output for timing and sandcastle generation in CCT.
18. Oscillator output (6 MHz)
A series resonant circuit is connected between this pin and pin 20 to control the nominal frequency of the VCO.
19. Filter 2
A filter with a short time constant is connected to this pin for the horizontal phase detector. It is used in the video
recorder mode and while the loop is locking up.
20. Oscillator input (6 MHz)
See pin 18.
21. Filter 1
A filter with a long time constant is connected to this pin for the horizontal phase detector.
22. Sandcastle input pulse (PL/CBB)
This input accepts a sandcastle waveform, which is formed from PL and CBB from the CCT.
Signal timing is shown in Fig.5.
23. Pulse timing resistor
The current for the pulse generator is defined by a 68 W resistor connected to this pin.
24. Pulse timing capacitor
The timing of the pulse generator is determined by a 220 pF capacitor connected to this pin.
25. Video composite sync output (VCS)
The output signal is for CCT.
26. Black level
The black level for the adaptive sync separator is stored by a 68 nF capacitor connected to this pin.
27. Composite video input (CVS)
The composite video signal is input via a 2,2 mF clamping capacitor to the adaptive sync separator.
28. Text composite sync input (TCS)/Scan composite sync input (SCS)
TCS is input from CCT or SCS from external sync circuit. SCS is expected when there is no load resistor at pin 1.
If pin 28 is not connected the sync output on pin 1 will be the composite video input at pin 27, internally buffered.
TELEFUNKEN (THOMSON) PALCOLOR SP212 STEREO CHASSIS 418 (THOMSON IKC-2) Teletext decoder with improved processor which determines the beginning and end of a teletext page:
As shown in FIG. 2, a teletext decoder has a multi-page memory (MEM)
comprising a plurality of memory portions (CH0 to CH3) in which
individual pages can be stored on a priority basis. The numbers of
selected pages are entered into page request registers (PR0 to PR3) and
when the number of a selected page is detected by the relevent one of
page comparators (PC0 to PC3) a found bit (FB) is produced by the
relevant one of flip-flops (FB0 to FB3) and recorded in the memory
portion allotted to the selected page by processor means (PM). In order
to ensure that the end of a selected page can also be detected, one of
the memory portions is allotted to store every page received so that a
found bit is always produced at the end of a selected page stored in
another memory portion. The processor means (PM) uses this latter found
bit to signify detection of the end of the selected page.
1. A teletext decoder
for teletext information comprising a plurality of different pages each
of which is identified by a respective page number, said teletext
decoder comprising:
processor means,
a multi-page memory having a plurality of memory portions for storing the different pages on a priority basis,
means for selecting given ones of the different pages by their
respective page number in preparation for storing in the memory portions
according to an allotment by the processor means, and
means
responsive to the respective page number of a page selected by the
selecting means to store a found signal corresponding to a memory
portion allotted to the page selected by the selecting means,
wherein the processor means is operable;
to allot a particular memory portion for storing a first page,
to cause the selection means to select the first page in preparation
for storing the first page in said particular memory portion,
to detect a beginning of storing of the first page selected by the selecting means in response to a first stored found signal
to detect a beginning of storing of a second page selected by said
selecting means in response to a second stored found signal, and
to detect an end of storing of the first page by changing the state of
the first found signal in response to the second found signal.
2. The teletext decoder of claim 1 wherein the
processor means is operable to test for the first and second found
signals.
3. The teletext decoder of claim 1 wherein each
memory portion includes a respective single bit location for storing a
respective found signal in the form of a single bit, the single bit
having one logic value when the processor means has allotted such memory
portion to one of the different pages, which one page has not been
found after being selected by the selecting means, the single bit having
a second logic value when the one page has been found.
4. The teletext decoder of claim 3 wherein the
processor means is operable to change a value of the single bit from the
second logic value to the first logic value when a currently selected
page is allotted to the respective memory portion.
5. The teletext decoder of claim 1 wherein the
processor means is operable to set flags therein representing a
respective beginning and end of storage of the page selected by the
selecting means.
6. A teletext decoder as claimed in claim 5,
characterised in that each of said flags is a single bit which is given
one logic value when it is set and the opposite logic value when it is
cleared.
7. The teletext decoder of claim 1 wherein the processor means is
operable to allot first and second particular memory portions to first
and second first pages; and
to cause the first and second particular memory portions to store the
first and second first pages alternately, so that the first particular
memory portion retains the first first page while the second particular
memory portion stores the second first page, with beginning and ends of
the first and second first pages being detected between the first and
second first pages using first and second first stored found signals.
8. The teletext decoder of claim 7, wherein the
processing means is operable to determine from a logic value of a single
flag bit which of the first and second particular memory portions is to
store a next page selected by the selecting means and which is to
retain a current page selected by the selecting means.
9. The teletext decoder of claim 8 wherein said first particular
memory portion is accorded a higher priority than said second particular
memory portion; and
said single flag bit is associated with said first particular memory
portion, so that said second particular memory portion automatically
stores the next page when said single flag bit determines that said
first particular memory portion is not to store the next page.
10. A method for identifying an end of a teletext
page which is one of a plurality of different teletext pages, the method
comprising the following steps: (a) allotting a first portion of a multi-page memory to a first teletext page;
(b) selecting a first teletext page;
(c) when the first page is found, first storing a first found signal and the first teletext page in the first portion;
(d) second storing a second found signal and a second teletext page in a second portion of the multi-page memory;
(e) identifying a beginning of the second page in response to the second stored found signal; and
(f) identifying an end of the first page by changing a state of the
stored first found signal in response to the second stored found signal.
11. A method for identifying an end of a teletext page comprising the
following steps in the order given: (a) receiving a plurality of
teletext pages;
(b) allotting a first portion of multi-page memory to a first one of the teletext pages;
(c) first finding the first one of the teletext pages;
(d) first storing a first logic value for a first found signal in the
first portion, to indicate that the first one of the teletext pages is
being either stored or sought;
(e) second storage the first one of the teletext pages in the first portion;
(f) second finding a second one of the teletext pages;
(g) third storing the first logic value for a second found signal in a
second portion of the multi-page memory, to indicate that the second
one of the teletext pages is being either stored or sought; and
(g) setting the first found signal to a second logic value, to indicate
that the end of the first one of the teletext pages has been reached,
in response to the first logic value of the second found signal;
whereby the end of the first one of the teletext pages is identified
without embedding an end of page signal in the first teletext page and
without loss of the first teletext page.
12. The method of claim 11 wherein (a) the first and third storing
steps are performed by hardwired data acquisition circuits; and
(b) the setting step is performed by software in a processor.
13. The method of claim 11 further comprising the step of acquiring a control page.
14. The method of claim 11 further comprising the step of
maintaining internal flags in a processor, which internal flags
represent ends of teletext pages, in response to the found signals.
15. The method of claim 11 further comprising the steps of
(a) allocating first, second, third, and fourth page locations of the
multi-page memory to a control page, a first data page, a second data
page, and a trash page, respectively;
(b) selecting the control, first and second data pages; and
(c) selecting a range of trash pages.
16. The method of claim 15 further comprising the steps of (a)
alternating acquisition of the first and second data pages, and
(b) using a beginning of the trash page to signify an end of any other page.
Description:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This
invention relates to teletext decoders for receiving, storing and
processing teletext information which is transmitted as digitally coded
data and comprises a plurality of different pages each of which is
identified by a respective page number. Transmissions of teletext
information are in television signals in television lines where no
picture signals representing normal television picture information are
present. These television lines are referred to as data-lines.
2. Related Art
The
document "Broadcast Teletext Specification", September 1976, published
jointly by the British Broadcasting Corporation, Independent
Broadcasting Authority and British Radio Equipment Manufacturers'
Association, discloses a specification for transmitting teletext
information in 625-line television systems.
In the
above-identified document "Broadcast Teletext Specification", a quantity
of teletext information to be considered as an entity is termed a page
and will be so termed herein. All of the pages which are available are
normally transmitted in a recurrent cycle, with or without up-dat
ing
page information, as appropriate. At a teletext decoder any page can be
selected, and the digitally coded data representing the page information
is then acquired by the teletext decoder from the cyclic transmission
and is stored in a page memory of the teletext decoder for as long as
the page is required. A teletext decoder may have a multi-page memory
having a plurality of memory portions in which individual pages can be
stored. These memory portions may be used on a priority basis, that is,
if two (or more) memory portions are allotted to store the same selected
page, then priority logic in the decoder allows only one portion to
receive the page in preference to the other(s).
The pages are
organised into different magazines (or groups) and each page consists of
up to 24 data rows. The first data row (Row 0) of each page is termed a
page-header and contains inter alia the page number. The transmission
of each page begins with, and includes, its page-header and ends with,
and excludes, the next page-header which is transmitted in respect of a
page in the same magazine. Thus, it is assumed that all of the data rows
containing the relevant magazine number which are transmitted between
two such successively transmitted different page-headers belong to the
page having the first page-header.
Proposals for enhancing the
teletext specification given in the "Broadcast Teletext Specification"
document are given in the document "World System Teletext Technical
Specification", March 1985, compiled by the Department of Trade and
Industry. One of these enhancement proposals concerns the provision of a
conditional access teletext service in which teletext message
information in data pages is scrambled prior to transmission, and can
only be received as useful information by a teletext decoder having an
appropriate descrambling key. Such a descrambling key is itself
transmitted as encrypted teletext information in the data page
concerned, whilst other keys which are provided to regulate the
conditional access to transmitted teletext message information are
transmitted in encrypted control pages. Decryption therefore has also to
be performed within the teletext decoder.
The reception and
processing of the scrambled data pages and the encrypted control pages
necessitates the use of a type of teletext decoder which includes
processor means for carrying out the descrambling and decryption. The
actual reception of the data pages and control pages can be carried out
by dedicated hardware circuits of the teletext decoder, albeit under the
control of the processor means.
A problem that has been
encountered in the realisation of a teletext decoder of this type is
that the processor means needs to know when acquisition of a selected
teletext page (control or data) has been completed before descrambling
or decryption, as the case may be, of the teletext page can commence.
This problem occurs because although the aforementioned page-header
feature provides a specific page-found indication from which a
`page-found` signal can be produced directly to signify the start of a
selected page, this feature does not provide a specific end-of-page
indication at the end of the transmitted page from which an end-of-page
signal can be produced directly at the end of a transmitted page.
SUMMARY OF THE INVENTION
It
is an object of the present invention to provide a teletext decoder of
the type set forth above which includes means for determining when all
of the teletext information contained in selected page has been received
by the teletext decoder.
According to the invention a teletext
decoder for teletext information comprising a plurality of different
pages each of which is identified by a respective page number,
comprises:
processor means,
a multi-page memory having a plurality of memory portions in which individual pages can be stored on a priority basis,
means for selecting pages by their page number for storage in memory portions allotted by the processor means, and
means
responsive to the receipt of the page number of a selected page to
record a found signal in respect of the memory portion allotted to that
page, which teletext decoder is characterised in that said processor
means is operable:
to allot a particular memory portion for the storage of any received page,
to cause the selection means to select all the received pages of said plurality for storage in said particular memory portion,
to
signify the beginning of the storage of an individually selected page
in another memory portion in response to the presence of a found signal
in respect of that memory portion, and
to signify the end of the
storage of the selected page in response to the presence of a found
signal in respect of said particular memory portion.
By causing
any received page to be accepted and stored in said particular memory
portion, it is ensured that a found signal is always produced at the end
of an individually selected page, which found signal thus becomes an
effective end of page signal for the selected page.
Because of
the priority logic in the docoder, a page which is individually selected
and has a memory portion allotted to it will be stored in that memory
portion rather than in said particular memory portion. It therefore
follows that when two different immediately adjacent pages are
individually selected, each will have a respective memory portion
allotted to it for storage therein and neither will be stored in said
particular page.
Thus, in carrying out the invention, it is
preferable to arrange the operation of the processor means such that the
presence of a found signal is looked for in respect of both said
particular memory portion and each other memory portion that may be
allotted to an immediately following individually selected page.
Conveniently,
the found signal is a single, found, bit which is stored in the memory
portion to which it pertains, this found bit having one logic value when
a page to which its memory portion has been allotted has not been found
following its selection, and this found bit having the opposite logic
value when the page number for that page has been received.
In
order that the found bit pertaining to said particular memory portion is
always at said one logic value prior to the receipt of the page number
for the page immediately following a selected page, the processor means
may be arranged to write a found bit of said one logic value into said
particular memory portion each time the presence of a found bit of said
opposite logic value is detected in the memory portion allotted to an
individually selected page.
The beginning and end of the storage
of an individually selected page can be signified in the processor means
by the setting therein of respective flags. These flags may be
respective single bits which are given one logic value when they are set
and the opposite logic value when they are cleared .
BRIEF DESCRIPTION OF THE DRAWING
In
order that the invention may be fully understood reference will now be
made by way of example to the accompanying drawings, of which:
FIG. 1 is a block diagram of a teletext decoder in which the invention can be embodied;
FIG. 2 is a block diagram showing elements of the teletext decoder of FIG. 1;
FIG.
3 is a flow chart showing operations of the processing means of the
teletext decoder in the performance of the invention; and
FIG. 4 is a timing diagram showing the time relationships of various of the steps in the flow chart of FIG. 3.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
Referring
to the drawin
gs, the teletext decoder shown in FIG. 1 has a front end 1
for receiving an incoming television signal VS. This front end 1
comprises the usual amplifying, tuning and i.f. detector circuits and is
under tuning control of processor means 2. The demodulated video signal
VS' produced at the output of the front end 1 is applied to a video
processor circuit 3 which performs data slicing for retrieving teletext
data pulses D from the video signal VS'. The video processor circuit 3
also produces input data clock pulses C from the data pulses D. The data
pulses D are fed together with the clock pulses C to a data acquisition
circuit 4 which is operable to feed selected groups D/G of the data
pulses to a memory 5 as address, message and control information. The
memory 5 has a capacity for storing at least four pages, comprising a
plurality of data rows, in respective memory portions which are
hereinafter referred to as "chapters". A page and row format according
to the aforementioned "Broadcast Teletext Specification" is assumed.
The
processor means 2 is operable in accordance with select signals applied
to it from a user interface device 6 to control channel selection and
which pages, as composed of the selected groups D/G of the data pulses,
are acquired by the data acquisition circuit 4. The processor means 2 is
further operable to read out from the memory 5 the control and message
information which has been acquired. The message information is used to
drive a character generator 7 which produces R,G,B, component signals
for utilisation. A timing circuit 8 provides timing signals on
connections t1, t2 and t3 for the circuit elements 4, 5 and 7. These
circuit elements and the timing circuit 8 are accessed by the processor
means 2 via an interface circuit 9. The operation of the timing circuit 8
is synchronised with the received video signal VS by a composite pulse
signal VCS which contains the line and field synchronising pulses which
are separated from the demodulated video signal VS' in the video
processor circuit 3.
The operation of the processor means 2 may
also be under the control of a remote terminal or computer which has
access to the teletext decoder via a suitable two-way link 10 and
interface 11, for instance an RS232 external link. Acquired teletext
information can then be transmitted over this external link for
utilisation remotely. Channel and page selection may also be effected
from a remote terminal rather than by the interface device 6.
The
processor means 2 can be a commercially available microcomputer; e.g.
from the MAB 8400 Series (Philips). The circuit element can be the
integrated circuit VIP2 type 5230 (Mullard); the circuit elements 4, 5
and 8 can be the integrated circuit EURO CCT type SAA 5240 (Mullard);
and the interface circuit 9 can be a so-called I
2 C bus.
The
block diagram of FIG. 2 shows elements of the data acquisition circuit
(4 - FIG. 1) of the teletext decoder. An 8-bit shift register SR/8 has
the received teletext data pulses D clocked into it by the clock pulses
C. In the aforementioned "Broadcast Teletext Specification", each
teletext data row includes for byte synchronisation an 8-bit framing
code. This framing code is looked for by a framing code detector FCD and
when it is found, this indicates the start of proper data on a
data-line and a `start` signal ST is applied by the detector FCD to a
data bit counter BC. The bit counter BC is clocked by the clock pulses C
and counts the teletext data pulses as they are clocked into the shift
register SR/8. Various decodes from the bit counter BC provide pulses to
other parts of the data acquisition circuit at certain times during the
data-line. One of these decodes provides a signal (≉8) every eight
clock pulses, and is used to clock the data pulses into an 8-bit latch
LA. The serial teletext data pulse stream is thus broken up into 8-bit
words. The 8-bit words are fed to a Hamming and parity checker HPC.
Seven of the eight bits of words from the latch LA form data bytes of
teletext information TI to be stored in the relevant chapters of a page
memory MEM (5 - FIG. 1). This memory MEM has four chapters CH0 and CH3
for storing respective pages. The eighth bit is a parity bit, which is
not stored but is used by the Hamming and parity checker HPC to test for
odd parity in the words. The first two 8-bit words after the framing
code on each data-line are used to define row and magazine addresses,
which are protected by Hamming codes. The checker HPC effects Hamming
correction for one bit errors and Hamming detection of two bit errors
and produces two 4-bit corrected words of which 5 bits define row
addresses and the remaining 3 bits define magazine addresses. These two
addresses are clocked into respective row and magazine address latches.
However, for the sake of simplicity there is shown in FIG. 2 only the
row address latch RL which is clocked by row pulses RA from the bit
counter BC to latch in successive 5-bit row addresses.
The row
address output RAO from the latch RL identifies in various chapters the
row addresses where the teletext information TI is to be stored in the
memory MEM. The row address output RAO is also applied to a detector DRO
which can detect the address of Row 0. When Row 0 (i.e. a page-header)
is detected, the detector DRO produces a signal which `sets` (s) a
flip-flop PHR (page header received). The resulting signal from the
flip-flop PHR `enables` (e) a group of four page comparators PC0 to PC3,
`resets` (rs) a group of four flip-flops CPHR0-CPHR3 (correct page
header received), and `activates` (a) a write element WC via an OR-gate
OWC. When activated, the element WC produces a `write` signal WS which
enables a memory interface and control element MCE to permit data (TI)
in a detected page-header (Row 0) to be written into one of the chapters
of the memory MEM. The particular one of four chapters concerned is
determined by the processor means PM (2 - FIG. 1) by a chapter `select`
signal CHS which is applied to the element MCE from the processor means
PM via the bus I
2 C (9 -FIG. 1).
Associated with the
page comparators PC0 to PC3 are respective page request registers PRO to
PR3 into which the page numbers PN of selected pages are entered by the
processor means PM. As already mentioned, a page may be selected
directly from a user interface device (6 - FIG. 1). A page may also be
selected by the processor means 2 in accordance with control information
contained in a previously acquired page. When a page number is entered
into one of the registers PRO to P
R3 an associated one of four
flip-flops PBLF0 to PBLF3 (page being looked for) is set (s) and a PBLF
bit of logic value `1` is entered into the associated one of the memory
chapters CH0 to CH3.
Each page-header (Row 0) contains a Hamming
protected page number which is compared in each of the comparators PC0
to PC3 with any page number that has been entered into the registers PR0
to PR3. If there is correspondence between any of the compared page
numbers the or each comparator concerned `sets` (s) the associated one
of the four flip-flops CPHR0 to CPHR3. The resulting output signal from a
set one of these flip-flops `activates` (a) the write control element
WC via the OR-gate OWC for all the following data-lines that cohtain the
data rows of the selected page, until receipt of the next page-header
(Row 0) causes the flip-flops which are set to be reset by the flip-flop
PHR and thereby terminate the writing action. A reset pulse RS is
applied to the flip-flop PHR at the end of every data-line by the bit
counter BC. The activation of the write control element WC is in respect
of an output signal from any of the flip-flops CPHR0 to CPHR3, but a
priority detector PD to which these output signals are applied
determines on a pre-selected priority basis into which memory chapter
the selected page is to be written in the event that more than one of
the flip-flops CPHR0 to CPHR3 signifies that a correct page header has
been received.
The output signals from the set flip-flops
CPHR0-CPHR3 are also used to `reset` (rs) a respective one of the four
flip-flops PBLF0 to PBLF3. This results in the relevant PBLF bit being
changed from a logic value `1` to a logic value `0`. Finally, the output
signals from the flip-flops CPHR0-CPHR3 reset (rs) respective
flip-flops FB0 to FB3 to provide found bits FB of `0` logic value which
are stored in the relevant memory chapter. These found bits FB and the
bits PBLF are used by the processor means PM for data acquisition
control. The bits PBLF are changed between the logic values `1` and `0`
values as the flip-flops PBLF0 to PBLF3 are `set` and `reset` by the
circuit action. However, this is not the case for the bits FB which, as
stored, are only given the logic value `0` by the circuit action. A bit
FB can only be changed to the logic value `1` by the processor means PM
setting the relevant one of the flip-flops FB0 to FB3 using a setting
signal SS. Three situations concerning the logic values of the bits FB
and PBLF can be determined. Firstly, there is a normal situation in
which a page has been received and all relevant control functions have
been dealt with by the processor means PM. This is indicated by PBLF =0
and FB =1 (written by the processor means PM). Second, after a page has
been requested and is being searched for, PBLF =1 and FB =1. Third, when
a page has been received but the processor means PM has not yet
observed the fact, this is indicated by PBLF =0 and FB =0.
When
the processor means PM has dealt with any actions which are necessary on
receipt of a page, it changes the relevant found bit FB to a logic
value `1`. This then acts as a flag to signify to control software that
such actions have been taken and it need not process that page again.
Each time the page is subsequently received the found bit FB will be
reset to the logic value `0`, indicating to the processor means PM that
action may be required (e.g. the page may be updated). If no special
action is to be taken by the control software on receipt of a page there
is no need for the processor means PM to set the found bit FB to a
logic `1`, and this bit will remain at the logic value `0` after the
first reception of a page.
It can be seen from the foregoing
description of the operation of the data acquisition circuit that the
processor means PM can determine from the relevant bit PBLF whether or
not a requested page is being looked for, as determined by the logic
value `0` or `1` value of this bit, and it can determine from the logic
value `0` of the found bit FB when a requested page has been found. The
processor means PM cannot, however, determine when all the data rows of
a found page have been received because the logic value of the found
bit FB is not changed by the data acquisition circuit in response to
receipt of a subsequent page header, which provides the assumption that
all the data rows of the previous page have been sent.
In
accordance with the present invention, the control software of the
processor means PM is organised so as to give an end-of-page indication.
Such an indication has been found to be necessary when dealing with
scrambled and encrypted teletext pages. The flow chart of FIG. 3
illustrates the control software which provides the end-of-page
detection. For the purposes of the following description of the software
control, it will be assumed that different teletext pages in a
hexadecimal page number range 700 to 7FF are to be received by the
teletext decoder, and that the processor means PM always allots the
memory chapter CH0 for storing a control page (e.g. page 700), the
memory chapters CH1 to CH2 for storing data pages, (e.g. 701, 702 . . .
), and the memory chapter CH3 for storing any page 7xx, :n this number
range. The processor means PM allots the memory chapters CH1 and CH2
alternately for the storage of selected data pages, by alternating the
entry of individually selected data page numbers into the page request
registers PR1 PR2. The page request register PR3 has all the page
numbers of the range entered into it by the processor means PM.
In
the flow chart of FIG. 3, the various boxes and the legends contained
therein specify the control software programme steps as follows:
F1: STRT - this is an instruction to enter the programme.
F2: TIM 0/F? -- this is an instruction to determine whether (Y) or not (N) a timer has timed-out.
(The
purpose of the timer is to set a flag once every 20ms - i.e. once per
television field - to identify the start of each vertical blanking
interval. The timer is automatically reset after each interval, to
remove the flag, and commences a new time-out period.
F3: CPpf? -
this is an instruction to determine whether (Y) or not (N) a flag CPpf
in the processor means PM has is set (=1) or cleared (=0). (When a
control page CP is currently being acquired in the memory chapter CH0,
as signified by FB/CP =0, this flag CPpf =1).
F4: FB/DP-TP - this
step is entered into when the flag CPpf is set, and is an instruction
requiring the processor means PM to get the found bit FB from the
chapter memory CH1 (or CH2 as will be discussed) and also from the
chapter memory CH3.
F5: FB=0? - this is an instruction to
determine whether either of the found bits FB which have been obtained
are at logic value `0`.
(When FB/DP1 =0 (or FBDP2 =0) in the
chapter memory CH1 (or CH2) this signifies that a data page DP is stored
or is being stored therein. Likewise, when FB/TP =0 in the chapter
memory CH3 this signifies that another (trash) page TP is stored or is
being stored therein. When either of these found bits FB has a logic
value `1` this signifies that the control page CP is still being
acquired).
F6: EXT - this is an instruction to exit the programme when the control page CP is still being acquired.
F7:
DPpf? - this step is entered into when step F3 determines that the flag
CPpf =0, and is an instruction for determining whether (Y) or not (N) a
flag DPpf in the processor means PM is set (=1) or cleared (=0). (When a
data page DP is currently being acquired in the memory chapter CH1 (or
CH2), as signified by FB/DP1 =0 (or FB/DP2 =0), this flag DPpf =1).
F8
FB/CP-TP - this step is entered into when the flag DPpf is set, and is
an instruction requiring the processor means PM to get the found bit
FB/CP from the chapter memory CH0 and also the found bit FB/TP from the
chapter memory CH3.
F9: FB=0? - this is an instruction to
determine whether either of the found bits FB which have been obtained
are at logic value `0`.
(When FB/CP =0 in the chapter memory CH0
this signifies that a control page CP is stored or is being stored
therein. Likewise, when FB/TP =0 in the chapter memory CH3 this
signifies that another (trash) page TP is stored or is being stored
therein. When either of these found bits FB has a logic value `1` this
signifies that the data page DP is still being acquired).
F10: EXT - this is an instruction to exit the programme when the data page DP is still being acquired.
F11:
CLR CPpf - when step F5 determines that the found bit FB in SET CPepd
either chapter memory CH1 (or CH2) or chapter memory and CH3 has a logic
value `0` this WR FB/CP instruction F11 is entered into and requires
the processor means PM to clear the flag CPpf, to set another flag
CPepd, and to write a bit of logic value `1` for the found bit FB/CP in
the chapter memory CH0. (The clearing of the flag CPpf signifies that
the control page is no longer being acquired and the setting of the flag
CPepd signifies that the entire control page has been received. The bit
FB/CP =1 in the chapter memory CH0 signifies that the control software
action for receiving the control page has been completed).
F12:
CLR DPpf - this instruction corresponds to the instruction in SET DP epd
step F11 but it is carried out in respect of a data
WR FB/DP
page DP1 (or DP2) when either FB/CP =0 in the memory chapter CH0, or
FB/TP =0 in the memory chapter CH3 as determined by step F9.
F13:
FB/DP=0? - this is an instruction to determine whether the found bit
FBDP1 (or FB/DP2) obtained by step F4 in the memory chapter CH1 (or CH2)
is at logic value `0`. If it is not, then the programme is exited at
step F14. If this found bit is at logic value `0`, signifying that a
data page is being stored in the relevant chapter memory, step F15 is
entered into.
F14: EXT - this is an instruction to exit the programme as just mentioned.
F15:
SET DPpf - this instruction requires the processor means PM to CLR
DPepd set the flag DPpf, to clear another flag DPepd, and WR FB/TP to
write a bit of logic value `1` for the found bit FB/TP in the chapter
memory CH3. (The setting of the flag DPpf signifies that a data page is
being acquired and the clearing of the flag DPepd prepares for the
subsequent setting of this latter flag when the entire data page has
been received. The bit PB/TP is set to 0 in response to the next page
header when it is received to provide an end-of-page indication for the
page immediately preceding that page header).
F16: EXT - this is
an instruction to exit the programme. F17: FB/CP=0? - this is an
instruction to determine whether the found bit FB/CP obtained by step F8
in the memory chapter CH0 is at logic value `0`. If it is not, then the
programme is exited at step F18. If this found bit is at logic value
`0`, signifying that a control page CP is being stored in the chapter
memory CH0, step F19 is entered into.
F18: EXT - this is an instruction to exit the programme as just mentioned.
F19:
SET CPpf - this instruction corresponds to the instruction in CLR CPepd
step F15 but it is carried out in respect of the WR FB/TP control page
CP.
F20: FB/DP-CP - this is an instruction requiring the
processor means PM to get the found bits FB from the chapter memories
CH1 (or CH2) and CH0.
F21: FB/CP=0? - this step coresponds to step F17 and leads into step F19 when FB =0 in the chapter memory CH0.
F22: FB/DP=0? - this step corresponds to step F13 and leads into step F15 when FB =0 in the chapter memory CH1 (or CH2).
F23/24: EXT - these are instructions to exit the programme.
The
overall operation of the flow chart of FIG. 3 may be summarised, as
follows, with reference to the timing diagrams of FIG. 4. Diagram (a)
represents a teletext transmission in which the blocks RO--RN signify
successive data rows. Each block RO signifies a page header row of which
five, PH1 to PH5, are shown. The data rows RO(PH1) to RN contain data
for a control page CP, the data rows RO(PH2) to RN contain data for a
data page DP, the data rows RO(PH3) to RN contain data for a trash page
TP, the data rows RO(PH4) to RN contain data for a second data page DP,
and the page header RO(PH5) is for a second control page CP.
Diagram
(b) shows the output logic levels from the flip-flop PHR. The output
logic levels from each of the flip-flops FB0 to FB3 which form the found
bits FB are represented by diagrams (c), (d) and (e), respectively.
At
the time that the page header RO(PH1) is received both the flags CPpf
and DPpf are cleared, so that step F20 is entered via steps F3 and F7 to
obtain FB/DP and FB/CP in step F20. Step F19 is then entered into
because step F21 detects FB/CP =0. Because CPpf =1 is now detected by
step F3, steps F4 and F5 are entered periodically. When the page-header
R0(PH2) has been received, FB/DP =0 to allow step F11 to be entered to
set the flag CPepd which signifies that all the data rows of the control
page CP have been received. Because the page-header RO(PH2) relates to
the data page DP, step F15 is entered via step F13 to set the flag DPpf.
With the flag CPpf reset and the flag DPpf set, step F8 is entered into
via steps F3 and F7. When the page-header RO (PH3) has been received,
FB/TP =0 to allow step F12 to be entered into via steps F8 and F9 to set
the flag DPepd which signifies that all the data rows of the data page
DP have been received. Both the flags CPpf and DPpf are now reset again
so that steps F20, F21 and F22 are entered via steps F3 and F7 and are
passed through without any change because FB/CP =1 and FB/DP =1. When
the page-header RO(PH4) has been received, FB/DP =0 to allow step F15 to
be entered into via step F22 to set the flag DPpf. When the page-header
RO(PH5) has been received, step F12 is entered into via steps F8 and F9
to set the flag DPepd to signify that all the second data page DP has
been received. Because FB/CP =0, step F19 is next entered into from step
F17 to set the flag CPpf.
It can be seen from the foregoing that
whenever the page header for a control page or a data page is received,
as detected by the logic value `0` of the found bit in the relevant
memory chapter, the processor means writes a found bit of logic value
`1` into the memory chapter allocated to the trash page. A found bit of
logic value `1` will also be stored in the memory chapter for a control
page or a data page prior to such pages being received. When the next
page header for either a control page or a data page is received, this
causes the relevant found bit to be changed to the logic value `0` which
is detected by the processor means to set the end-of-page detector flag
in respect of the preceding page. If the next page-header is not for a
control page or a data page, then the data acquisition circuit will
accept the page-header as belonging to a trash page to change the found
bit for this trash page to logic value `0` and this again will be
detected by the processor means to set the end-of-page detector flag in
respect of the preceding page. Depending on the page-header sequence the
found bit for the fresh page may already be of logic value `1` when a
logic value `1` is written to it.
The flow chart of FIG. 3 also
includes a multi-instruction step F25: CPL ACQb, HOL SP, ACQ DP. This
instruction step serves to make the two memory chapters CH1 and CH2
available alternately for storing the next acquired data page, even
though both these chapters are always allotted to store this page. CPL
ACQb is a complement instruction to change the value of a flag ACQb
between logic value `1` and `0` to cause the processor means to carry
out the other steps of the programme in respect of the two memory
chapters in turn as they become available alternately. HOL SP and AQC DP
are instructions which identify in the processor means which memory
chapter is holding a previously acquired data page (i.e. a shadow page
SP) and which memory chapter is being used to acquire the next data page
(DP). When the flag ACQb =1, the memory chapter CH1 is used to acquire
the next data page and the memory chapter CH2 holds the shadow page.
When the flag ACQb =0, the memory chapter CH1 holds the shadow page and
the memory chapter CH2 is used to acquire the next data page. Because of
the priority detector PD of the data acquisition circuit, the chapter
CH1 will normally be chosen before chapter CH2 to store the next
received data page. Therefore, it only becomes necessary to use the
single flag ACQb to select the "hold" or "acquire" function of the
memory chapter CH1, because the memory chapter CH2 will then
automatically have the alternate function. Because of the toggling
action in respect of alternate data pages, the instruction WR FB/DP in
step F12 is now carried out after step F25.
PHILIPS SAA5243 -0.3 to +7.5V enhanced computer controlled teletext circuits (ECCT).
(which stands for Syndicat des Constructeurs
d'Appareils Radiorécepteurs et Téléviseurs) is a standard for connecting
audio-visual equipment together. The official standard for SCART is
CENELEC document number EN 50049-1. SCART is also known as Péritel
(especially in France) and Euroconnector but the name SCART will be used
exclusively herein. The standard defines a 21-pin connector (herein
after a SCART connector) for carrying analog television signals. Various
pieces of equipment may be connected by cables having a plug fitting
the SCART connectors. Television apparatuses commonly include one or
more SCART connectors.
television apparatuses include a separate SCART connectors each
dedicated to receive input television signals in one of an RGB format
and an S-Video format. This limits the functionality of the SCART
connectors. In practical terms, the number of SCART connectors which can
be provided on a television apparatus is limited by cost and space
considerations. However, different users wish the input a wide range of
different combinations of formats of television signals, depending on
the equipment they personally own and use. However, the provision of
SCART connectors dedicated to input television signals in one of an RGB
format and an S-Video format limits the overall connectivity of the
television apparatus. Furthermore, for many users the different RGB
format and S-Video format are confusing. Some users may not understand
or may mistake the format of a television signal being supplied on a
given cable from a given piece of equipment. This can result in the
supply of input television signals of an inappropriate format for the
SCART connector concerned.
(WAS)
is a German radio and television apparatus company, founded in 1903,
in Berlin, as a joint venture of two large companies, Siemens &
Halske (S & H) and the Allgemeine Elektricitäts-Gesellschaft
(General Electricity Company).
The
German radio station in Zeesen near Königswusterhausen (8 kW
shortwave transmitter) was built by Telefunken and was officially
placed in service on August 28, 1929. The Mühlacker radio station (60
kW output) was handed over on December 20, 1930. Telefunken is now
in, and on, the air.
