LA1357N - VIF AMP , VIDEO DET. , AGC , AFT
M51381P - VIDEO AMPLIF.
TA7193P - BANDPASS AMPL, CW OSC DEMOD.
LA1320A - SIF AMP , SIF DEMOD.
LA1460 - SYNC SEP, VERT OSC/DRIVE , AFC , HORIZ. OSC.
LA5112N - POWER SUPPLY REGULATOR
2SD839 HORIZ / LINE OUT.
2SB514 . 2SD330 VERT / FRAME OUT.
2SC1507 X 3 RGB AMPL.
2SA608 ACL
2SB544 LUM / VIDEO DRIVE
SANYO CTP3209 CHASSIS 79P-88CA02 Combination VHF-UHF tuner for use in a television receiver:
A combination VHF-UHF tuner includes a VHF tuner and a UHF tuner in which the VHF tune
r has at least three tuning networks connected in a stage preceding a mixer and each constituted by first and second coils and a variable capacitance diode. The first coil in each of the tuning network is coupled to a switching diode for shortcircuiting the first coil for establishing a network operable to a high band VHF signal and for opening the first coil connected to the second coil for establishing a tuning network operable to a low band VHF signal. A band selecting circuit is provided for controlling the three tuning networks in such a manner that the three tuning networks are all operable to the high or low band VHF signal when the VHF channel is tuned in and that at least one of the three tuning networks is operable to the high band VHF signal while the remaining is operable to the low band VHF signal when the UHF channel is tuned in.
1. A combination VHF-UHF tuner comprising, in combination:
a UHF tuner;
a VHF tuner having an input tuning circuit, a primary interstage tuning circuit, a secondary interstage tuning circuit and a mixer connected in series between a VHF input and a tuner output;
means connected to the UHF tuner for operating the same when UHF channel is tuned in; and
means connected to the VHF tuner for making the input tuning circuit, primary interstage tuning circuit and secondary interstage tuning circuit operative to high band VHF signal when high channel VHF signal is tuned in, for making the input tuning circuit, primary interstage tuning circuit and secondary interstage tuning circuit operative to low band VHF signal when low channel VHF signal is tuned in, and for making at least one of the input tuning circuit, primary interstage tuning circuit and secondary interstage tuning circuit operative to high band VHF signal and the remaining operative to low band VHF signal when UHF channel is tuned in.
2. A combination VHF-UHF tuner as claimed in claim 1, wherein each of the input tuning circuit, primary interstage tuning circuit and secondary interstage tuning circuit includes a tuning network constituted by a variable capacitance diode and first and second inductance coils, said second inductance coil coupled with a switching diode for short-circuiting the second inductance coil for making the tuning network operative to the high band VHF signal.
Description:
BACKGROUND OF THE INVENTION
The present invention relates to a television receiver, and more particularly, to a combination VHF-UHF tuner in which a variable capacitance element is so arranged as to serve as a tuning element for electrically selecting a desired channel while a mixer employed in a VHF tuner serves as an intermediate frequency amplifier when a UHF channel is tuned in.
The abbreviation VHF and UHF used hereinabove and hereinbelow stands for very-high frequency and ultra-high frequency, respectively.
Conventionally, there have been proposed various types of the combination VHF-UHF tuner, one example is shown in FIG. 1. Referring to FIG. 1, there is shown a block diagram of the conventional tuner which includes a VHF tuner 1 having an input tuning circuit 2, a radio frequency amplifier, a primary interstage tuning circuit 3, a secondary interstage tuning circuit 4, a mixer 5, which are connected in series between a VHF input A and a tuner output B, and a local oscillator 6 connected to a junction Ja between the secondary interstage tuning circuit 4 and the mixer 5. The conventional tuner shown in FIG. 1 further includes a UHF tuner 7 connected between a UHF input C and a switch 8 which is in turn connected to the junction Ja.
According to the above described conventional tuner, particularly the one which is located at place where the VHF signal is strong, the input tuning circuit 2 and primary and secondary interstage tuning circuits 3 and 4 are normally set in a tuned condition with VHF high band signal, even when the UHF channel is tuned in, so that the VHF broadcasting signals carried in high channels are apt to be transmitted to the mixer 5. Therefore, in the case where the television receiver is set to receive UHF broadcasting signal, the VHF broadcasting signals carried in high channels may interfere with the UHF broadcasting signal.
Such interference may take place when the input tuning circuit 2 and primary and secondary interstage tuning circuits 3 and 4 are normally set in a tuned condition with VHF low band signals. In this case, the UHF broadcasting signal may be interfered by the VHF broadcasting signal of low channels.
Accordingly, a primary object of the present invention is to provide a tuning device which prevents the VHF signals from being transmitted to the mixer when the UHF signal is tuned in.
Another object of the present invention is to provide a tuning device of the above described type which is simple in construction and can readily be manufactured at low cost.
In accordance with a preferred embodiment of the invention, a combination VHF-UHF tuner comprises: a UHF tuner; a VHF tuner having an input tuning circuit, a primary interstage tuning circuit, a secondary interstage tuning circuit and a mixer connected in series between a VHF input and a tuner output and local oscillator; means connected to the UHF tuner for operating the same when UHF channel is tuned in; and means connected to the VHF tuner for making the input tuning circuit, primary interstage tuning circuit and secondary interstage tuning circuit operative to high band VHF signal when high channel VHF signal is tuned in, for making the input tuning circuit, primary interstage tuning circuit and secondary interstage tuning circuit operative to low band VHF signal when low channel VHF signal is tuned in, and for making at least one of the input tuning circuit, primary interstage tuning circuit and secondary interstage tuning circuit operative to high band VHF signal and the remaining operative to low band VHF signal when UHF channel is tuned in.
BRIEF DESCRIPTION OF THE DRAWINGS
These and other objects and features of the present invention will become apparent from the following description taken in conjunction with a preferred embodiment thereof with reference to the accompanying drawings, in which:
FIG. 1 which have already been referred to in the foregoing description is a block diagram of a combination VHF-UHF tuner of a prior art;
FIG. 2 is a block diagram partly showing a detailed network of a combination VHF-UHF tuner of the present invention; and
FIG. 3 is a circuit diagram of a band selecting circuit.
DETAILED DESCRIPTION OF THE INVENTION
Before the description of the present invention proceeds, it is to be noted that like parts are designated by like reference numerals throughout the accompanying drawings.
Referring to FIG. 2, there is shown a combination VHF-UHF tuner of the present invention, in which a reference numeral 10 designates a VHF tuner while a reference numeral 11 designates a UHF tuner. The VHF tuner 10 includes an input tuning circuit 16, a radio frequency amplifier 17, a primary interstage tuning circuit 18, a secondary interstage tuning circuit 19 and a mixer 15 which are connected in series between a VHF input 12 and a tuner output 41. The VHF tuner 10 further includes a local oscillator 14 connected to a junction J1 between the secondary interstage tuning circuit 19 and the mixer 15.
Before describing each of the tuning circuits 16, 18 and 19, it is to be noted that FIG. 2 illustrates only circuit components necessary to describe the present invention, and that these tuning circuits 16, 18 and 19 operate, when VHF channel is tuned in, in a known manner.
The input tuning circuit 16 comprises a resistor R1 and a capacitor C1 connected in series between a power supplying terminal 33 for the mixer 15 and the ground. A junction J2 between the resistor R1 and the capacitor C1 is connected to an anode of a switching diode 30, whereas the cathode of the switching diode 30 is connected to a capacitor C2 through a junction J3. The junction J3 is connected through a resistor R2 to a terminal 35 which receives a band selecting signal from a band selecting circuit 50 as will be described in detail later with reference to FIG. 3. The input tuning circuit 16 further comprises an LC circuit including coils 24 and 27, capacitor C3 and a variable capacitance diode 21. A junction J4
between the coils 24 and 27 is connected to the capacitor C2 whereas a junction J5 between the capacitor C3 and cathode of the variable capacitance diode 21 is connected through a resistor R3 to a tuning voltage supplying terminal 20. The anode side of the variable capacitance diode 21 and the coil 27 are grounded.
The radio frequency amplifier 17 is constituted by any known amplifier so designed as to amplify high frequency signal. Therefore, a detailed description thereof is omitted for the sake of brevity.
The primary and secondary interstage tuning circuits 18 and 19 have a similar network as the network of the input tuning circuit 16. The primary interstage tuning circuit 18 comprises a resistor R4 and a capacitor C4 connected in series between the ground and a power supplying terminal 34 which is provided for supply power to the radio frequency amplifier 17 and to the local oscillator 14. The terminal 24 receives power from the band selecting circuit 50. A junction J6 between the resistor R4 and the capacitor C4 is connected to an anode of a switching diode 3, whereas the cathode of the switching diode 31 is connected to a capacitor C5 through a junction J7. The junction J7 is connected through a resistor R5 to a terminal 35. The primary interstage tuning circuit 18 further comprises an LC circuit including coils 25 and 28, capacitor C6 and a variable capacitance diode 22. A junction J8 between the coils 25 and 28 is connected to the capacitor C5 whereas a junction J9 between the capacitor C6 and cathode of the variable capacitance diode 22 is connected through a resistor R6 to the tuning voltage supplying terminal 20. The anode side of the variable capacitance diode 22 and the coil 28 are grounded.
The secondary interstage tuning circuit 19 comprises a resistor R7 and a capacitor C7 connected in series between the ground and the power supplying terminal 33 provided for supplying power to the mixer 25. A junction J10 between the resistor R7 and the capacitor C7 is connected to an anode of a switching diode 32, whereas the cathode of the switching diode 32 is connected to a capacitor C8 through a junction J11. The junction J11 is connected through a resistor R8 to a terminal 35. The secondary interstage tuning circuit 19 further comprises an LC circuit including coils 26 and 29, capacitor C9 and a variable capacitance diode 23. A junction J12 between the coils 26 and 29 is connected to the capacitor C8 whereas a junction J13 between the capacitor C9 and the cathode of the variable capacitance diode 23 is connected through a resistor R9 to the tuning voltage supplying terminal 20. The anode side of the variable capacitance diode 23 and the coil 29 are grounded.
The variable capacitance diodes 21, 22 and 23 are set to produce a predetermined capacitance by a DC voltage applied from the terminal 20.
Still referring to FIG. 2, the UHF tuner 11 of any known type is actuated when high voltage signal is applied to a terminal 37 from the band selecting circuit 50. Such high voltage applied to the terminal 37 also actuates a switching diode 36 connected between the output of the UHF tuner and the junction J1. Therefore, when the terminal 37 receives high voltage, the UHF tuner 11 is actuated and, at the same time, the switching diode 36 electrically connects the UHF tuner 11 to the mixer 15 for supplying intermediate frequency signal produced from the UHF tuner 11 to the mixer 15. On the other hand, when the terminal 37 receives a low signal, the UHF tuner 11 is brought into inoperative position and, at the same time, the switching diode 36 electrically interrupts the UHF tuner from the mixer 15. The mixer 15 is always provided with an actuating voltage (+B3) from the terminal 33 when and so long as the television receiver is turned on.
Referring to FIG. 3, the band selecting circuit 50 includes three transistors Q1, Q2 and Q3 the emitters of these transistors Q1, Q2 and Q3 being connected to each other and in turn to a source of voltage (+B1). The base of the transistor Q1 is connected through a resistor R10 to a terminal 38 which receives a negative VHF low band setting signal from an electric channel selecting apparatus (not shown) of any known type. The collector of the transistor Q1 is connected through a resistor R11 to the terminal 34 of the VHF-UHF tuner described above and also to the ground through a zener diode Dz. The base of the transistor Q2 is connected through a resistor R12 and diode D2 to a terminal 39. The diode D2 is provided for directing electric current to flow towards the terminal 39, when the terminal 39 receives negative VHF high band setting signal from the electric channel selecting apparatus. A diode D1 is connected between the terminals 38 and 39, so that the negative VHF high band setting signal applied to the terminal 39 is directed to the base of the transistor Q1 and also to the base of the transistor Q2. The collector of the transistor Q2 is connected through a resistor R13 to a transistor Q4 which has the collector connected to a source of voltage (+B2) and the emitter connected to the ground. The collector of the transistor Q4 is also connected to a terminal 35 of the VHF-UHF tuner. The base of the transistor Q3 is connected through a resistor R14 to a terminal 40 which receives a negative UHF setting signal from the electric channel selecting apparatus. The collector of the transistor Q3 is connected to the terminals 37 through a resistor R15. A diode D3 is connected between the terminal 40 and the anode side of the diode D2, so that the negative UHF setting signal applied to the terminal 40 is directed to the base of the transistor Q2. An operation of the band selecting circuit 50 is described hereinbelow with reference to FIGS. 2 and 3.
When the electric channel selecting apparatus (not shown) as a whole including the band selecting circuit 50 provides the negative VHF low band setting signal to the terminal 38, the transistor Q1 conducts to provide a predetermined voltage (+15V) determined by the zener diode Dz to the terminals 34 for actuating the radio frequency amplifier 17 and local oscillator 14. Since other terminals 39 and 40 are not provided with any negative setting signals, the remaining transistors Q2, Q3 and Q4 are held in a non-conductive state. Therefore, the terminal 35 receives a predetermined positive voltage (+30V) from the voltage source while the terminal 37 is maintained at zero volt. Under the condition described above, the switching diodes 30, 31 and 32, shown in FIG. 2, are impressed on the cathode sides thereof with positive voltage +30V and on the anode sides thereof with positive voltage +15V. Therefore, the diodes 30, 31 and 32 are all reversely biased to interrupt the electrical connection between the anode and cathode sides of the respective switching diodes 30, 31 and 32. As a consequence, the coils 27, 28 and 29 are in association with the coils 24, 25 and 26, respectively, to establish tuning circuits 16, 18 and 19 which are operative to the low band VHF signals.
When the electric channel selecting apparatus (not shown) provides the negative VHF high band setting signal to the terminal 39, the transistor Q2 conducts to provide biasing voltage to the transistor Q4. Therefore, the transistor Q4 conducts to ground the terminal 35. At the same time, the negative VHF high band setting signal applied to the terminal 39 is fed to the transistor Q1 through a diode D1, so that the terminal 34 is applied with the predetermined voltage (+15V) in a similar manner as described above. The terminal 37 is maintained at zero volt since there is no signal applied to the terminal 40. Under the condition described above, the switching diodes 30, 31 and 32, shown in FIG. 2, are impressed on the cathode sides thereof with zero volt from the terminal 35 and on the anode sides thereof with positive voltage +15V from the terminal 34 and 33. Therefore, the switching diodes 30, 31 and 32 are all forward biased to conduct the same. As a consequence, the junctions J4, J8 and J10 are grounded in terms of high frequency region, through the diodes 30, 31 and 32, respectively, to substantially shortcircuit the coils 27, 28 and 29. Accordingly, thus established tuning circuits 16, 18 and 19 are operative to the high band VHF signals.
On the contrary, when the UHF channel is tuned in, the negative UHF setting signal is applied to the terminal 40 for conducting the transistor Q3 on and, in turn, providing a predetermined voltage (+15 V) to the terminal 37. At the same time, the negative UHF setting signal applied to the terminal 40 is also fed through the diode D3 to the transistor Q2 for turning on the transistors Q2 and Q4. Thus, the terminal 35 is grounded. The terminal 34 is maintained at zero voltage since there is no signal applied to the transistor Q1. Under the condition described above, the signal applied to the terminal 37 actuates the UHF tuner 11 and, at the same time, conducts the switching diode 36 to transmit the output signal from the UHF tuner 11 to the mixer 15. In the mixer 15, the intermediate frequency signal of the UHF channel is amplified to produce an output signal of UHF channel from the output terminal 41. When and so long as the UHF channel is tuned in in the manner described above, the signal of VHF channel is interrupted in the VHF tuner as in the manner described hereinbelow.
Since the switching diodes 30 and 32 are provided at their anode sides with positive voltage (+15V) from the terminal 33 and at their cathode sides with zero voltage from the terminal 35, the switching diodes 30 and 32 are turned on to make the tuning circuits 16 and 19 operative to the high band VHF signals. On the contrary, the switching diode 31 is provided at its anode side with zero voltage from the terminal 34 and at its cathode side with zero voltage from the terminal 35, so that the switching diode 31 is maintained non-conductive to make the tuning circuit 18 operative to the low band VHF signal. Accordingly, when the UHF channel is tuned in, the irregularity in the VHF tuner 10 that the tuning circuit 16 and 19 are operative to the high band VHF signals while the tuning circuit 18 is operative to the low band VHF signal prevents any of the VHF signal from being transmitted through the VHF tuner 10. For example, the high band VHF signal applied to the input of the VHF tuner 10 may be transmitted through the input tuning circuit 16, however, will not be transmitted through the primary interstage tuning circuit 18, since the circuit 18 is operative only to the low band VHF signal. Therefore, the UHF signal transmitted through the mixer 15 will not be interfered by any VHF signal.
It is to be noted that, when the UHF channel is tuned in, the irregularity in the VHF tuner 10 may have other combination than those described above and yet having the same effect as to prevent any of the VHF signal from being transmitted through the VHF tuner 10. For example, when the UHF channel is tuned in, one of the three tuning circuits 16, 18 and 19 may be arranged to be operative to the low band VHF signal while other two tuning circuits may be arranged to be operative to the high band VHF signal.
As it has been described fully in the foregoing description, the combination VHF-UHF tuner of the present invention produces VHF or UHF signal which is not interferenced by UHF or VHF signal, respectively, since when the UHF signal is tuned in, one of the three tuning circuits is tuned as operative to the low band VHF signal or high band VHF signal while other two tuning circuits are tuned as operative to the high band VHF signal or low band VHF signal.
Furthermore, the combination VHF-UHF tuner of the present invention employing the variable capacitance diode as an element constituting the tuning circuit and employing the mixer of the VHF tuner, when UHF channel is tuned in, as the intermediate frequency amplifier is applicable to a television receiver particularly positioned in a place where the VHF broad casting signal is strong.
Although the present invention has been fully described by way of examples with reference to the accompanying drawings, it is to be noted that various changes and modifications are apparent to those skilled in the art. Such changes and modifications are, unless they depart from the true scope of the present invention, to be understood as included therein.
SANYO CTP3209 CHASSIS 79P-88CA02 Chrominance signal processing circuit in color television receiver:
A chrominance signal processing circuit in a color television receiver which comprises a bandpass amplifier, a burst gate pulse source, a subcarrier generator, a 90° phase shifter for phase shifting the generated subcarrier, a B - Y demodulator and an R - Y demodulator both coupled to the bandpass amplifier and separately coupled to the subcarrier generator and the 90° phase shifter, respectively, characterized in that a flip-flop is provided responsive to the burst gate pulse to alternately provide a first and second selected burst gate pulses, the B - Y and R - Y demodulators are structured to provide a burst magnitude representing signal and a subcarrier phase drift representing signal, respectively, in the line blanking period and to be disabled responsive to the first and second selected burst gate pulses, respectively, an automatic col
or control sample and hold circuit is provided to be enabled to the second burst gate pulse to hold the burst magnitude representing output of the B - Y demodulator to supply the held level signal to the bandpass amplifier as a gain control signal, and an automatic phase control sample and hold circuit is provided to be enabled responsive to the first selected burst gate pulse to hold the subcarrier phase drift representing output of the R - Y demodulator to supply the held level signal to the subcarrier generator as a frequency control signal. Preferably a color gain control and tint control are provided, which are structured to be responsive to the burst gate pulse to be disassociated with the bandpass amplifier and the subcarrier generator.
1. A chrominance signal processing circuit in a color television receiver, comprising:
means for amplifying a composite chrominance signal including a burst signal in a line blanking period and a chrominance signal suppression modulated on a subcarrier during a line scanning period,
means for providing a burst gate pulse during said line blanking period,
means for generating a subcarrier,
first chrominance demodulating means responsive to said composite chrominance signal amplifying means and said subcarrier generating means for providing a first chrominance demodulated signal in said line scanning period and for providing a first signal representing the magnitude of said burst signal in said blanking period,
second chrominance demodulating means responsive to said composite chrominance signal amplifying means and said subcarrier generating means for providing a second chrominance demodulated signal in said line scanning period and for providing a second signal representing the phase drift of said subcarrier in said blanking period,
first sample and hold means responsive to said burst gate pulse to be enabled and responsive to said first chrominance demodulating means for sampling said first magnitude representing signal and holding a first level signal representing said first magnitude representing signal, and
second sample and hold means responsive to said burst gate pulse to be enabled and responsive to said second chrominance demodulating means for sampling said second phase drift representing said second phase drift representing signal,
said composite chrominance signal amplifying means comprising a voltage controlled variable gain amplifying means connected to receive as a voltage control signal said first level signal representing said magnitude representing signal,
said subcarrier generating means comprising a voltage controlled variable frequency oscillating means connected to receive as a voltage control signal said second level signal representing said phase drift representing signal;
means coupled to said subcarrier generating means for adjusting the phase of said subcarrier; and
means coupled to said phase adjusting means and responsive to said burst gate pulse for making said subcarrier generating means unresponsive to said phase adjusting means.
2. A chrominance signal processing circuit in a color television receiver in accordance with claim 1, wherein
said burst gate pulse providing means comprises means responsive to said burst gate pulse for providing first and second trains of selected burst gate pulses which are complementary to each other,
said first sample and hold means is adapted to be responsive to said first train of selected burst gate pulses to be enabled and responsive to said first chrominance demodulating means for sampling said first magnitude representing signal and holding said first level signal representing said first magnitude representing signal, and
said second sample and hold means is adapted to be responsive to said second train of selected burst gate pulses to be enabled and responsive to said second chrominance demodulating means for sampling said second phase drift representing signal and holding a second level signal representing said second phase drift representing signal.
3. A chrominance signal processing circuit in a color television receiver in accordance with claim 2, wherein
said first chrominance demodulating means is structured to be disabled responsive to said first train of selected burst gate pulses for the time period of said first train of selected burst gate pulses, and
said second chrominance demodulating means is structured to be disabled responsive to said second train of selected burst gate pulses for the time period of said second train of selected burst gate pulses.
4. A chrominance signal processing circuit in a color television receiver in accordance with claim 2, wherein said first and second burst gate pulse train providing means comprises means responsive to said burst gate pulses for alternatively selecting said burst gate pulses as said first and second trains of selected burst gate pulses.
5. A chrominance signal processing circuit in a color television receiver in accordance with claim 4, wherein said alternate selecting means comprises a toggle type flip-flop.
6. A chrominance signal processing circuit in a color television receiver in accordance with claim 1, wherein said composite chrominance signal amplifying means comprises means for adjusting the gain of said composite chrominance signal amplifying means.
7. A chrominance signal processing circuit in a color television receiver in accordance with claim 6, wherein said composite chrominance signal amplifying means further comprises means coupled to said gain adjusting means and responsive to said burst gate pulse for making said composite chrominance signal amplifying means irresponsive to said gain adjusting means.
8. A chrominance signal processing circuit in a color television receiver in accordance with claim 1, which further comprises means responsive to said first sample and hold means for providing a signal representing the presence or absence of said burst signal in said composite chrominance signal for disabling said composite chrominance signal amplifying means when said burst signal is not included in said composite chrominance signal.
9. A chrominance signal processing circuit in a color television receiver in accordance with claim 1, which further comprises means responsive to said first and second chrominance demodulating means for providing a third chrominance demodulated signal.
10. A chrominance signal processing circuit in a color television receiver in accordance with claim 1, wherein said first chrominance demodulating means comprises B-Y color difference signal demodulating means for providing a B-Y color difference signal, and said second chrominance demodulating means comprises R-Y color difference signal demodulating means for providing an R-Y color difference signal.
11. A chrominance signal processing circuit in a color television receiver in accordance with claim 10, which further comprises G-Y color difference signal providing means operatively coupled to said B-Y color difference signal demodulating means and said R-Y color difference signal demodulating means for providing a G-Y color difference signal.
12. A chrominance signal processing circuit in a color television receiver in accordance with claim 11, wherein said subcarrier generating means comprises a subcarrier generator for generating a first subcarrier signal to said B-Y color difference signal demodulating means, and phase shift means coupled to said subcarrier generator for phase shifting by 90° said first subcarrier signal for providing a second subcarrier signal having a phase difference of 90° with respect to said first subcarrier signal to said R-Y color difference signal demodulating means.
13. A chrominance signal processing circuit in a color television receiver, comprising:
means for amplifying a composite chrominance signal including a burst signal in a line blanking period and a chrominance signal suppression modulated on a subcarrier during a line scanning period,
means for providing a burst gate pulse during said line blanking period,
means for generating a subcarrier,
first chrominance demodulating means responsive to said composite chrominance signal amplifying means and said subcarrier generating means for providing a first chrominance demodulated signal in said line scanning period and for providing a first signal representing the magnitude of said burst signal in said blanking period,
second chrominance demodulating means responsive to said composite chrominance signal amplifying means and said subcarrier generating means for providing a second chrominance demodulated signal in said line scanning period and for providing a second signal representing the phase drift of said subcarrier in said blanking period,
first sample and hold means responsive to said burst gate pulse to be enabled and responsive to said first chrominance demodulating means for sampling said first magnitude representing signal and holding a first level signal representing said first magnitude representing signal, wherein said first sample and hold means is responsive to said second chrominance demodulating means and comprises means for comparing the output of said first chrominance demodulating means with the output of said second chrominance demodulating means as a reference for providing said first magnitude representing signal, and
second sample and hold means responsive to said burst gate pulse to be enabled and responsive to said second chrominance demodulating means for sampling said second phase drift representing signal and holding a second level signal representing said second phase drift representing signal,
said composite chrominance signal amplifying means comprising a voltage controlled variable gain amplifying means connected to receive as a voltage control signal said first level signal representing said magnitude representing signal,
said subcarrier generating means comprising a voltage controlled variable frequency oscillating means connected to receive as a voltage control signal said second level signal representing said phase drift representing signal.
14. A chrominance signal processing circuit in a color television receiver, comprising:
means for amplifying a composite chrominance signal including a burst signal in a line blanking period and a chrominance signal suppression modulated on a subcarrier during a line scanning period,
means for providing a burst gate pulse during said line blanking period,
means for generating a subcarrier,
first chrominance demodulating means responsive to said composite chrominance signal amplifying means and said subcarrier generating means for providing a first chrominance demodulated signal in said line scanning period and for providing a first signal representing the magnitude of said burst signal in said blanking period,
second chrominance demodulating means responsive to said composite chrominance signal amplifying means and said subcarrier generating means for providing a second chrominance demodulated signal in said line scanning period and for providing a second signal representing the phase drift of said subcarrier in said blanking period,
first sample and hold means responsive to said burst gate pulse to be enabled and responsive to said first chrominance demodulating means for sampling said first magnitude representing signal and holding a first level signal representing said first magnitude representing signal, and
second sample and hold means responsive to said burst gate pulse to be enabled and responsive to said second chrominance demodulating means for sampling said second phase drift representing signal and holding a second level signal representing said second phase drift representing signal, wherein said second sample and hold means is responsive to said first chrominance demodulating means and comprises means for comparing the output of said second chrominance demodulating means with the output of said first chrominance demodulating means as a reference for providing said second phase drift representing signal,
said composite chrominance signal amplifying means comprising a voltage controlled variable gain amplifying means connected to receive as a voltage control signal said first level signal representing said magnitude representing signal,
said subcarrier generating means comprising a voltage controlled variable frequency oscillating means connected to receive as a voltage control signal said second level signal representing said phase drift representing signal.
Description:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a chrominance signal processing circuit in a color television receiver. More specifically, the present invention relates to an improvement in an automatic color control and an automatic phase control in a color television receiver.
2. Description of the Prior Art
As well known, a composite color television signal comprises a luminance signal and a chrominance signal sup
pression modulated on a subcarrier in a line scanning period, apart from a horizontal and vertical synchronizing signals in a blanking period and a burst signal at the back porch of the horizontal synchronizing signal. In a typical color television receiver, a luminance signal, horizontal and vertical synchronizing signals, and a chrominance signal plus a burst signal are separated for the purpose of signal processing. For the purpose of processing a chrominance signal, a composite chrominance signal including a chrominance signal suppression modulated on a subcarrier and a burst signal is provided. On the other hand, a burst gate pulse is also provided to sample a burst signal in the composite chrominance signal. A subcarrier is locally generated responsive to the sampled burst signal and the original color signals are demodulated responsive to the chrominance signal and as a function of the locally generated subcarrier.
FIG. 1 shows a block diagram of a typical prior art chrominance signal processing circuit in a color television receiver. Referring to FIG. 1, a composite chrominance signal including a burst signal is applied to a bandpass transformer 1 adjusted to cover the frequency band of the composite chrominance signal. The output of the bandpass transformer 1 is applied to a first bandpass amplifier 2 and further to a second bandpass amplifier 3, wherein the composite chrominance signal is amplified. The output of the second bandpass amplifier 3 is applied to a color gain control, wherein the gain of the bandpass amplifiers 2 and 3 is adjusted. The chrominance signal thus amplified and gain adjusted is applied to an R-Y demodulator 5 and a B-Y demodulator 6, wherein an R-Y color difference signal and a B-Y color difference signal are demodulated as a function of a subcarrier obtained through a line 13 and a subcarrier obtained from a line 11, respectively, both of which have a phase difference of 90° to be described subsequently. More specifically, a subcarrier of the frequency 3.58 MHz is generated by a subcarrier generator 8 and is first applied to a hue or tint control 9, wherein the phase of the subcarrier is manually adjusted by means of a tint control variable resistor 10. The output of the tint control 9 is applied through the line 11 to the B-Y demodulator 6. On the other hand, the output of the tint control 9 is applied to a 90° phase shifter 20, wherein the original subcarrier is phase shifted by 90°. The output of the 90° phase shifter 12 is applied through the line 13 as another subcarrier to the R-Y demodulator 5. The output of the R-Y demodulator 5 and the output of the B-Y demodulator 6 are applied to a G-Y matrix 7, wherein the R-Y color difference signal and the B-Y color difference signal are subjected to an arithmetic operation to provide a G-Y color difference signal.
As well known, various automatic controls such as an automatic color control, an automatic phase control, an automatic color disabling control and the like are employed in a chrominance signal processing circuit. Referring to FIG. 1, an automatic color control will be first described. An automatic color control comprises a burst gate circuit 14 responsive to the burst gate pulse to gate only a burst signal in a composite chrominance signal obtainable from the first bandpass amplifier 2 to provide only a burst signal and a detector 15 for detecting the magnitude of the burst signal obtainable from the burst gate circuit 14 to provide the detected output representing the magnitude of the burst signal through a line 16 to the first bandpass amplifier 2 as a voltage control signal. For the purpose of automatic color control, the first bandpass amplifier 2 is structured in a voltage controlled variable gain amplifier. Therefore, the gain of the first bandpass amplifier 2 is controlled as a function of the output of the detector 15 and thus as a function of the magnitude of the burst signal. Thus, the overall gain of the amplifiers 2 and 3 and the control 4 is automatically controlled as a function of the magnitude of the burst signal. This type of automatic gain control is often referred to as an automatic color control. In FIG. 1, the automatic color control detector 15 is implemented by a synchronous detector operable as a function of the output from the subcarrier generator 8. Thus, the detector 15 is shown responsive to both the output of the burst gate circuit 14 and the output of the subcarrier generator 8.
The output obtainable from the automatic color control detector 15 is not only representative of the magnitude of the burst signal but also of the presence or absence of the burst signal. Therefore, the output obtained through the line 16 from the automatic color control detector 15 is also applied to a color disabling circuit 17 and the output from the color disabling circuit 17 is applied to the second bandpass amplifier 3, so that the second bandpass amplifier 3 is disabled if and when no output is obtained from the automatic color control detector 15 representing the absence of the burst signal and is enabled only when the output representing the presence of the burst signal is obtained from the automatic color control detector 15. This type of automatic color disabling control is often referred to as "color killer".
For the purpose of an automatic hue or phase control, the subcarrier generator 8 is implemented by a voltage controlled variable frequency oscillator and the output of the voltage controlled oscillator 8 is applied through a 90° phase shifter 18 to a phase detector 19, which is also connected to receive the burst signal obtained from the burst gate circuit 14. The phase detector 19 serves to detect the phase difference of the burst signal from the burst gate circuit 14 and of the output of the 90° phase shifter 18. The detected output from the phase detector 19 is applied through an amplifier 20 to the voltage controlled oscillator 8 as a voltage control signal. A closed loop including the voltage controlled oscillator type subcarrier generator 8, the phase detector 19 and the amplifier 20 automatically controls the phase of the output of the subcarrier generator 8 and is often referred to as an automatic phase control.
According to the above described automatic phase control, the output of the first bandpass amplifier 2 is first applied to the burst gate circuit 14, where only the burst signal is sampled or gated and the gated burst signal is used to detect by means of the phase detector 19 the phase of the subcarrier generated by the voltage controlled oscillator type subcarrier generator 8, whereupon the output of the phase detector 19 is applied through the amplifier 20 to the subcarrier generator 8. However, this type of automatic phase control has not taken full advantage of an automatic phase control, inasmuch as no consideration has been paid to a phase drift in the tint control 9, the demodulators 5 and 6, the second bandpass amplifier 3, the color gain control 4 and the like. Conventionally, various countermeasures were taken to eliminate such phase drift as much as possible in the respective circuits. In addition, in order to match the phase of the subcarrier with that of the chrominance signal, a phase compensation circuit 21 was required, because no circuits corresponding to the tint control 9 and the demodulators 5 and 6 were not included in the closed loop for the automatic phase control. Thus, the conventional circuit has an undesirably increased number of portions being adjusted. In addition, the feature of a less temperature drift of the automatic phase control was not effectively utilized.
Similarly, in case of a color gain or color saturation as well, a gain drift in the second bandpass amplifier 3, the color gain control 4, the demodulators 5 and 6, and the like was not automatically corrected, because the above described circuits were not included in the closed loop of the automatic gain control and as a result a gain drift in such circuits caused a variation of the color.
SUMMARY OF THE INVENTION
Briefly described, the present invention comprises a chrominance signal processing circuit in a color television receiver, comprising bandpass amplifying means of a voltage controlled variable gain type for amplifying a chrominance signal, burst gate pulse source means, subcarrier generating means of a voltage controlled variable frequency oscillator type, and color demodulating means coupled to the bandpass amplifying means and the subcarrier generating means, characterized in that first chrominance demodulating means is provided responsive to the chrominance signal and subcarrier signal for providing a first chrominance demodulated signal in the line scanning period and for providing a first signal representing the magnitude of the chrominance signal in the blanking period, second chrominance demodulating means is provided responsive to the chrominance signal and the subcarrier signal for providing a second chrominance demodulated signal in the line scanning period and for providing a second signal representing the phase drift of the subcarrier signal in the blanking period, first sample and hold means is provided responsive to the burst gate pulse to be enabled and responsive to the first chrominance demodulating means for sampling the first magnitude representing signal and holding a first level signal representing the first magnitude representing signal, the first level signal being applied to the bandpass amplifying means as a voltage control signal, and second sample and hold means is provided responsive to the burst gate pulse to be enabled and responsive to the second chrominance demodulating means for sampling the second phase drift representing signal and holding a second level signal representing the second phase drift representing signal, the second level signal being provided to the subcarrier generating means as a voltage control signal. According to the present invention, an automatic color control signal and an automatic phase control signal are obtained by the use of the chrominance demodulating means. Therefore, any disadvantages encountered in the above described conventional chrominance signal processing circuit are eliminated.
In a preferred embodiment, means is provided responsive to the burst gate pulse source means for providing first and second selected burst gate pulses which are complementary to each other, the first chrominance demodulating means is structured to be disabled and the first sample and hold means is structured to be enabled responsive to the first selected burst gate pulse for the time period of the first selected burst gate pulse, the second chrominance demodulating means is structured to be disabled and the second sample and hold means is structured to be enabled responsive to the second selected burst gate pulse for the time period of the second selected burst gate pulse, the first sample and hold means is further structured to compare the outputs of the first and second chrominance demodulating means using the latter as a reference and the second sample and hold means is further structured to compare the outputs of the second and first chrominance demodulating means using the latter as a reference.
In a preferred embodiment of the present invention, means is provided coupled to the bandpass amplifying means for adjusting the gain of the bandpass amplifying means and further means is provided coupled to the adjusting means and responsive to the burst gate pulse for making the bandpass amplifying means irresponsive to the adjusting means in the time period of the burst gate pulse.
In a preferred embodiment of the present invention, means is provided coupled to the subcarrier generating means for adjusting the phase of the output of the subcarrier generating means and further means is provided coupled to the phase adjusting means and responsive to the burst gate pulse for making the subcarrier generating means irresponsive to the phase adjusting means in the phase period of the burst gate pulse.
Accordingly, a principal object of the present invention is to provide an improved automatic color control and automatic phase control in a chrominance signal processing circuit in a color television receiver.
Another object of the present invention is to simplify adjustment of a phase relationship in an automatic color control and an automatic phase control in a chrominance signal processing circuit in a color television receiver.
A further object of the present invention is to make a bandpass amplifying means irresponsive to a gain adjusting means in a chrominance signal processing circuit in a color television receiver.
Still a further object of the present invention is to make a subcarrier generating means irresponsive to a phase adjusting means in a chrominance signal processing circuit in a color television receiver.
Another object of the present invention is to provide a simplified circuit configuration of a chrominance signal processing circuit including an automatic color control and an automatic phase control in a color television receiver.
Still another object of the present invention is to provide an improved chrominance signal processing circuit in a color television receiver including an automatic color control and an automatic phase control, which is adapted for implementation in an integrated circuit.
These objects and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a block diagram of a prior art chrominance signal processing circuit in a color television receiver;
FIG. 2 is a block diagram of one embodiment of the inventive chrominance signal processing circuit in a color television receiver;
FIG. 3 shows waveforms of the electrical signals at various portions in the FIG. 2 embodiment;
FIG. 4 shows a vector diagram showing the phases of the burst signal and the color difference signals;
FIG. 5 is a schematic diagram of the chrominance demodulators and the sample and hold circuits in the FIG. 2 embodiment; and
FIG. 6 is a schematic diagram of the tint control shown in the FIG. 2 embodiment.
DESCRIPTION OF THE PREFERRED EMBODIMENTS
FIG. 2 shows a block diagram of the inventive chrominance signal processing circuit in a color television receiver. The circuit configuration and operation of the FIG. 2 embodiment will be described with simultaneous reference to FIG. 3, which shows waveforms of the electrical signals at various portions in the FIG. 2 embodiment. It is pointed out that since some portions of the FIG. 2 embodiment are the same as those in the FIG. 1 diagram the same reference characters are used to denote the corresponding portions in the FIG. 2 embodiment.
The burst gate pulse, as shown in FIG. 3(a) is applied to a toggle type or T type flip-flop 22. Therefore, the flip-flop 22 alternately assumes a reversed storing state responsive to each burst gate pulse, whereby the high level output is obtained alternately from the Q and Q terminals of the flip-flop 22. The waveform of the Q output of the flip-flop 22 is shown in FIG. 3(b) and the waveform of the Q output of the flip-flop 22 is shown in FIG. 3(c). It is pointed out that the burst gate pulse has the intervals of one horizontal period and thus the Q and Q outputs of the flip-flop 22 assume alternately the high level which lasts for one horizontal line period. The Q output of the flip-flop 22 is applied to an AND gate 23 and the Q output of the flip-flop is applied to an AND gate 24. The AND gates 23 and 24 are also connected to receive the burst gate pulse. The waveform of the output of the AND gate 23 is shown in FIG. 3(d) and the waveform of the output of the AND gate 24 is shown in FIG. 3(e). It would be appreciated that the flip-flop 22 and the AND gates 23 and 24 serve to select alternately the burst gate pulse to provide a first and second trains of selected burst gate pulses which are selected at every second burst gate pulse and which trains are complementary to each other.
The output of the AND gate 23 is applied to the R-Y demodulator 5 as a disabling signal to disable the R-Y demodulator 5 as a function of the output of the AND gate 23 and is also applied to a first sample and hold circuit 25 as an enabling signal to enable the first sample and hold circuit 25 as a function of the output of the AND gate 23. Therefore, the R-Y demodulator 5 is disabled while the first sample and hold circuit 25 is enabled only during the pulse period shown in FIG. 3(d).
Similarly, the output of the AND gate 24 is applied to the B-Y demodulator 6 as a disabling signal to disable the B-Y demodulator 6 as a function of the output of the AND gate 24 and is also applied to a second sample and hold circuit 26 as an enabling signal to enable the second sample and hold circuit 26 as a function of the output of the AND gate 23. As a result, the B-Y demodulator 6 is disabled while the second sample and hold circuit 26 is enabled only during the pulse period as shown in FIG. 3(e).
The outputs of the R-Y demodulator 5 and the B-Y demodulator 6 obtainable during every burst gate pulse period are applied to both the first and second sample and hold circuits 25 and 26. Naturally, the outputs of both demodulators 5 and 6 obtainable even during the line scanning period are also applied to the first and second sample and hold circuits 25 and 26. However, since these sample and hold circuits 25 and 26 are not enabled during the line scanning period, the outputs of the demodulators 5 and 6 obtainable during the line scanning period including a chrominance signal, which is to be denoted by a hatched portion in FIG. 3(f) and (g), are not received by the first and second sample and hold circuits 25 and 26, respectively.
Since the R-Y demodulator 5 is disabled for one burst gate pulse period at every second burst gate pulse as shown in FIG. 3(d), a constant level E1 is established in the above described disabled burst gate pulse period, while an output 29 associated with the difference between the phase of the burst signal and the R-Y demodulation axis, i.e. the phase of the R-Y subcarrier, is generated in the not disabled burst gate period. This will be described in more detail with reference to FIG. 4, which shows a vector diagram showing the phases of the burst signal and the color difference signals. As shown in FIG. 4, the R-Y demodulation axis 27 and the burst signal axis 28 must have a phase difference of 90°. However, the phase difference of 90° is changed by virtue of a phase drift in the subcarrier generator 8, a phase drift in other circuits and the like, which causes a level variation associated with the phase drift at the output of the R-Y demodulator 5 in the not disabled burst gate pulse period. Assuming that the above described phase difference between the R-Y demodulator axis and the burst signal axis is exactly 90°, the output of the R-Y demodulator 5 obtainable in the not disabled burst gate pulse period is exactly the reference level E1, since no burst signal component is obtained in the R-Y demodulation axis, but when the above described phase difference becomes larger than 90°, a negative going pulse shaped output is obtained from the R-Y demodulator 5 in the not disabled burst gate pulse period, as shown as the waveform 29 in FIG. 3(f), and when the above described phase difference becomes smaller than 90°, the positive going pulse shaped output is obtained from the R-Y demodulator 5 in the not disabled burst gate pulse period. It would be appreciated that the above described pulse shaped output obtainable from the R-Y demodulator 5 in the not disabled burst gate pulse period could be utilized for the purpose of automatic phase control. In the embodiment shown, however, the second sample and hold circuit 26 is structured to utilize the above described pulse shaped output from the R-Y demodulator 5 as a phase control signal by utilizing the output of the B-Y demodulator 6 in the corresponding burst gate pulse period, i.e. the reference level E2 of the B-Y demodulator 6 as a reference signal for generation of such an automatic phase control signal.
On the other hand, the B-Y demodulator 6 is disabled as a function of the output of the AND gate 24 shown in FIG. 3(e), whereby a reference level E2 is established in the disabled burst gate pulse period, while the B-Y demodulator 6 remains enabled in the other burst gate pulse periods and accordingly a negative going pulse 30 associated with the variation of the color gain is caused. The above described pulse output 30 is applied to the first sample and hold circuit 25 and is utilized to generate an automatic color control signal. In generating the automatic color control signal based on the above described pulse signal 30, however, the reference level output E1 obtainable from the R-Y demodulator 5 is utilized as a reference signal for generation of an automatic color control signal. The first and second sample and hold circuits 25 and 26 also comprise smoothing circuits for smoothing the above described pulse shaped outputs 29 and 30.
The output of the second sample and hold circuit 26 is applied to the subcarrier generator 8 as a voltage control signal. To that end, the subcarrier generator 8 is implemented by a voltage controlled variable frequency oscillator. As a result, the phase of the subcarrier generator 8 is controlled for the purpose of an automatic phase control. Similarly, the output of the first sample and hold circuit 25 is applied to the first bandpass amplifier 2 as a voltage control signal for controlling the gain thereof. To that end, the first bandpass amplifier 2 is implemented by a voltage controlled variable gain amplifier. The output of the first sample and hold circuit 25 can also be applied to the color disabling circuit 17 in the same manner as described in the FIG. 1 diagram, inasmuch as the output of the sample and hold circuit 25 also represents the presence or absence of the burst signal in the composite chrominance signal.
Referring to FIG. 2, it is seen that the burst gate pulse is applied to both the color gain control 4 and the tint control 9. This will be described in some detail. Since the present invention utilizes the outputs of the R-Y demodulator 5 and the B-Y demodulator 6 for the purpose of an automatic color control and an automatic phase control, the levels as manually set by the color gain control 4 and the tint control 9 could influence upon the automatic color control detection and the automatic phase control detection. Therefore, means are provided in the color gain control 4 and the tint control for tentatively disassociating the adjusted levels by the color gain control 4 and by the tint control 9 with the demodulators 5 and 6 only during the burst gate pulse periods in response to the burst gate pulse.
FIG. 5 shows a schematic diagram of the R-Y demodulator 5, the B-Y demodulator 6, the first sample and hold circuit 25 and the second sample and hold circuit 26, which are implemented in an integrated circuit. Referring to FIG. 5, the B-Y demodulator 6 comprises a transistor Q3 serving as a constant current source, a differential amplifier including paired transistors Q4 and Q7 connected to receive a chrominance signal in a differential manner through lines 1 and 2, paired transistors Q8 and Q9 commonly connected at the emitter electrodes thereof to the collector electrode of the above described transistor Q4 and paired transistors Q10 and Q11 commonly connected at the emitter electrodes thereof to the collector electrode of the above described transistor Q7, whereby a double balanced type synchronous multiplier is implemented. The base electrodes of the above described transistors Q8 and Q11 are connected to receive the B-Y subcarrier CW1 through a terminal 36. The B-Y signal and the -(B-Y) signal are obtained across load resistors R13 and R14 connected to the collector electrodes of the transistors Q8 and Q10 and Q9 and Q11. Switching transistors Q5 and Q6 are connected in parallel with the above descirbed transistors Q4 and Q7, respectively, and the base electrodes of the switching transistors Q5 and Q6 are connected to receive the output of the AND gate 24 (see FIG. 3(e)) obtained through a line l3. As a result, if and when the transistors Q5 and Q6 are rendered fully conductive during the above described burst gate pulse period shown in FIG. 3(e), the transistors Q4 and Q7 are rendered non-conductive, whereby the B-Y demodulator 6 is disabled, while the transistors Q5 and Q6 are rendered non-conductive during the time period other than the above described burst gate pulse period shown in FIG. 3(e) and accordingly the transistors Q4 and Q7 are rendered conductive, whereby the B-Y demodulator 6 is enabled. During the time period when the above described transistors Q4 and Q7 are rendered conductive thereby to enable the B-Y demodulator 6, a normal demodulation operation is performed, whereby a chrominance signal as shown by a hatched portion in the FIG. 3(e) is obtained in the line scanning period and a negative going pulse shaped output 30 associated with the gain of the burst signal is obtained in the not disabled burst gate pulse period. On the contrary, when the transistors Q5 and Q6 are rendered conductive and the transistors Q4 and Q7 are rendered non-conductive, a constant current flows through the transistors Q5 and Q6, thereby to establish a constant level potential E2 shown in FIG. 3(g) across the resistors R13 and R14 as a detection output of the B-Y demodulator 6.
The R-Y demodulator 5 comprises a transistor Q12 serving as a constant current source, paired transistors Q13 and Q16 connected to receive the chrominance signal from the color gain control 4 in a differential manner through the lines l1 and l2, paired transistors Q17 and Q18 commonly connected at the emitter electrodes to the collector electrode of the transistor 13 and paired transistors Q19 and Q20 commonly connected at the emitter electrodes thereof to the collector electrode of the transistor Q16, whereby a double balanced type synchronous multiplier is implemented. The base electrodes of the transistors Q17 and Q20 are connected to recieve the R-Y subcarrier CW2 through a terminal 37 which has a phase shift of 90° with respect to that of the B-Y subcarrier CW1. The R-Y signal and the -(R-Y) signal are obtained across load resistors R19, and R14 and R15, respectively. Switching transistors Q14 and Q15 are connected in parallel with the transistors Q13 and Q16, respectively, and the base electrodes of the transistors Q14 and Q15 are connected to receive the output pulse of the AND gate 23 shown in FIG. 3(d) through a line l4, so that the transistors Q13 and Q16 are rendered conductive or non-conductive as a function of the output of the AND gate 23, shown in FIG. 3(d). As a result, as fully described with reference to FIG. 2, the R-Y demodulator 5 provides the output of the waveform shown in FIG. 3(f). It is pointed out that since in the FIG. 5 embodiment the demodulators 5 and 6 are implemented in a double balanced type, assuming that the output signal as shown in FIG. 3(f) is obtained across the load resistor R19 of the R-Y demodulator 5, the output of the 180° phase difference is obtained across the resistors R14 and R15, and similarly when the output as shown in FIG. 3(g) is obtained across the load resistor R13 of the B-Y demodulator 6 the output of the 180° phase difference is obtained across the resistor R14.
The signals shown in FIG. 3(g) and (f) developed across the resistors R13 and R19, respectively, are withdrawn through the emitter electrodes of the subsequent stage transistors Q21 and Q23 to the output terminals 31 and 32, and further applied through the emitter followers Q22 and Q24 to the first and second sample and hold circuits 25 and 26, respectively. On the other hand, the -(B-Y) signal developed across the resistor R14 and the -(R-Y) signal developed across the resistors R14 and R15 are properly added to provide a G-Y signal. The G-Y signal is withdrawn from the emitter electrode of the transistor Q25 to the output terminal 33.
The first sample and hold circuit 25 comprises a transistor Q26 serving as a constant current source and paired transistors Q27 and Q28 and a capacitor C1 externally connected at the terminal 34. The base electrode of the transistor Q26 is connected to the line l4. Therefore, the first sample and hold circuit 25 is enabled only in the period of the burst gate pulse obtainable from the AND gate 23 shown in FIG. 3(d). At that time, the output 30 shown in FIG. 3(g) obtained from the B-Y demodulator 6 applied to the base electrode of the transistor Q27 is compared with the constant potential, i.e. the emitter potential of the transistor Q24 based on the reference level output from the R-Y demodulator 5 applied to the base electrode of the transistor Q28, whereby an output having the magnitude and the sense associated with the difference is developed across the load resistor R26. A pulse shaped signal developed across the resistor R26 is applied through the transistor Q29 and the terminal 34 to the externally connected capacitor C1 and is smoothed thereby. The voltage signal as smoothed by the capacitor C1 is applied to the first bandpass amplifier 2 and the color disabling circuit 17, as described with reference to FIG. 2. If and when the first bandpass amplifier 2 and the color disabling circuit 17 are implemented in the same integrated circuit chip, then the collector electrode of the transistor Q29 can be directly coupled to the first bandpass amplifier 2 and the color disabling circuit 17.
The second sample and hold circuit 26 is similarly structured. The output of the AND gate 24 shown in FIG. 3(e) is applied through the line l3 to the base electrode of the constant current source transistor Q30, whereby the transistor Q30 is rendered conductive only during the pulse period shown in FIG. 3(e) and thus the second sample and hold circuit 26 is enabled only during the pulse period shown in FIG. 3(e) and thus the second sample and hold circuit 26 is enabled only during the pulse period shown in FIG. 3(e) while the second sample and hold circuit 26 is disabled during the time period other than the pulse period shown in FIG. 3(e). The base electrode of one transistor Q32 of the transistor pair is connected to receive the output signal representing the phase drift o the R-Y signal obtained from the R-Y demodulator 5 and the base electrode of the other transistor Q31 of the transistor pair is connected to receive as a reference the output E2 representing the reference level of the B-Y demodulator 6. An automatic phase control signal is obtained from the load resistor R31 and is applied through the transistor Q33 to a capacitor C2 externally connected to the terminal 35 and is smoothed thereby. The voltage signal as smoothed by the capacitor C2 is applied to the subcarrier generator 8 as a voltage control signal.
FIG. 6 shows a schematic diagram of the tint control 9 shown in FIG. 2. The subcarrier A obtained from the voltage controlled oscillator type subcarrier generator 8 and the subcarrier A' as 90° phase shifted by means of a phase shifter included in the tint control 9 but not shown in FIG. 6 are applied to the base electrodes of the transistors Q34 and Q35, respectively. The burst gate pulse is applied to the base electrode of the transistor Q40. Therefore, the transistor Q40 is rendered conductive during the scanning period t2 and is rendered non-conductive during the burst gate pulse period t1. Since the resistance values of the resistors R35 and R36 have been properly selected, if and when the transistor Q40 is rendered fully conductive, the base potential of the transistors Q41, Q42, Q43 and Q44 is much lower than the base potential of the transistors Q36, Q37, Q38 and Q39, irrespective of whatsoever level the base potential of the transistors Q36, Q37, Q38 and Q39 is, with the result that the transistors Q41, Q42, Q43 and Q44 are rendered non-conductive. Therefore, the subcarriers A and A' are withdrawn through the transistors Q36, Q37, Q38 and Q39 and combined at the base electrode of the emitter flower Q45 and is obtained at the output terminal 38. In this situation, the signal is subjected to an adjustment of the variable resistor 10 and thus a tint control can be achieved as desired through adjustment of the variable resistor 10 and the output as set by the variable resistor is obtained from the terminal 38.
However, if and when the transistor Q40 is rendered non-conductive responsive to the burst gate pulse t1, the base potential of the transistors Q41, Q42, Q43 and Q44 becomes higher than the base potential of the transistors Q36, Q37, Q38 and Q39 by the value EB1, and the transistors Q36, Q37 Q38 and Q39 are rendered non-conductive with the result that the subcarriers A and A' are withdrawn through the transistors Q41, Q42 Q43 and Q44 and combined at the base electrode of the transistor Q45, which combined output is withdrawn from the output terminal 38. Accordingly, in this situation, the phase of the output signal is determined only dependent upon the division ratio of the current in the transistors Q41, Q42, Q43 and Q44, without being affected at all by adjustment of the variable resistor 10. In other words, the output signal as released from the set state in the variable resistor 10 is obtained. Since the base electrode of the transistor Q40 is supplied with the negative going burst gate pulse during the time period t1 and is supplied with the positive voltage during the scanning time period t2, the outputs obtainable from the R-Y demodulator 5 and the B-Y demodulator 6 during the burst gate pulse period t1 for the purpose of automatic phase control are not subjected to the influence of the variable resistor 10, with the result that the subcarrier generator 8 is controlled as desired. On the other hand, during the scanning period t2, the outputs of the R-Y demodulator 5 and the B-Y demodulator 6 are subjected to the influence of the set state of the variable resistor 10 and thus an automatic phase control as set by the variable resistor can be achieved. The output of the output terminal 38 is applied to the terminal 36 in FIG. 5 and is also applied through the 90° phase shifter 12 shown in FIG. 2 to the terminal 37.
Although in the foregoing only the tint control 9 was described in detail with reference to FIG. 6, it is pointed out that the color gain control 4 can be structured in substantially the same manner. Thus, it is not believed necessary to describe the color gain control 4 in such detail, inasmuch as the same can be implemented by those skilled in the art in the light of the disclosure with reference to the FIG. 6 embodiment.
Although the present invention has been described and illustrated in detail, it is clearly understood that the same is by way of illustration and example only and is not to be taken by way of limitation, the spirit and scope of the present invention being limited only by the terms of the appended claims.
SANYO CTP3209 CHASSIS 79P-88CA02 Video/intercarrier sound detecting circuit in television receiver:
A video detecting circuit and an intercarrier sound signal
generating circuit suited for implementation in an integrated circuit
for use in a television receiver, comprising a video intermediate
frequency amplifier including a final stage video intermediate frequency
transformer, a tuning circuit coupled to the video intermediate
frequency amplifier to be tuned to the video intermediate frequency for
withdrawing a video intermediate frequency carrier signal, a diode
connection coupled to the tuning circuit for pulsing the video
intermediate frequency carrier signal, a double balanced synchronous
detector responsive to the video intermediate frequency amplifier and
the pulsing circuit for synchronous detecting the video intermediate
frequency signal for providing a detected video signal, and a double
balanced multiplier coupled to receive the primary and secondary signals
at the primary and secondary windings of the video intermediate
frequency transformer for evaluating the product of the primary and
secondary signals for providing a sound intermediate frequency signal.
Preferably, a phase shifter is provided in the double balanced
multiplier for causing a phase difference of an odd number times the
phase of π/2 between the primary and secondary signals to be applied to
the double balanced multiplier.
1. A video/intercarrier sound detecting circuit in a television receiver, comprising:
video intermediate frequency amplifying means for amplifying a video intermediate frequency signal including a video carrier signal and a sound carrier signal having a predetermined frequency difference therebetween,
means operatively coupled to said video intermediate frequency amplifying means for extracting the video intermediate frequency carrier signal,
means responsive to said video intermediate frequency carrier signal and the video intermediate frequency signal from said video intermediate frequency amplifying means for synchronously detecting said video intermediate frequency signal with said video intermediate frequency carrier signal for providing a detected video signal, and
multiplier means operatively coupled to said video intermediate frequency amplifying means and having a first and second inputs each adapted to receive the video intermediate frequency signal from said video intermediate frequency amplifying means for evaluating the product of the first and second input signals applied to said first and second inputs for providing the product output including a difference component of said video carrier frequency and said sound carrier frequency as a sound intermediate frequency signal.
2. A video/intercarrier sound detecting circuit in a television receiver in accordance with claim 1, which further comprises means operatively coupled to said multiplier means for causing a phase difference of an odd number times the phase of π/2 between said first input signal and said second input signal.
3. A video/intercarrier sound detecting circuit in a television receiver in accordance with claim 1, wherein said video intermediate frequency amplifying means comprises video intermediate frequency transformer means having a primary circuit and a secondary circuit magnetically coupled to each other, said first input of said multiplier means being coupled to said primary circuit of said video intermediate frequency transformer means and said second input of said multiplier means being coupled to said secondary circuit of said video intermediate frequency transformer means.
4. A video/intercarrier sound detecting circuit in a television receiver in accordance with claim 1, wherein said carrier wave extracting means comprises means responsive to said extracted carrier wave signal for pulsing the same, and said synchrnous detecting means comprises means responsive to said pulse output from said pulsing means for synchronously detecting said video intermediate frequency signal.
5. A video/intercarrier sound detecting circuit in a television receiver in accordance with claim 4, wherein said synchronous detecting means comprises a double balanced synchronous detector.
6. A video/intercarrier sound detecting circuit in a television receiver in accordance with claim 1, wherein said multiplier means comprises a double balanced detector.
7. A video/intercarrier sound detecting circuit in a television receiver in accordance with claim 1, wherein said synchronous detecting means comprises a double balanced synchronous detector adapted for a switching operation, and said multiplier means comprises a double balanced detector adapted for a linear operation.
Description:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an improved video/intercarrier sound detecting circuit in a television receiver. More specifically, the present invention relates to a video detecting circuit and an intercarrier sound signal generating circuit particularly suited for implementation in an integrated circuit in a television receiver.
2. Description of the Prior Art
In view of a decreased mixed modulation of synchronous detection of a video intermediate signal for obtaining a d
etected video signal, a synchronous detector has been proposed and widely used for detection of a video signal from a video intermediate frequency signal in television receivers. It has also been proposed and practiced that a common multiplier is utilized for synchronous detection of a video intermediate frequency signal for providing a detected video signal and for multiplication of a video intermediate frequency signal for providing an intercarrier sound signal in the form of a sound signal of the frequency 4.5 MHz which is a beat of the video carrier frequency 58.75 MHz and the sound carrier frequency 54.25 MHz.
FIG. 1 shows a block diagram of the above described typical conventional video synchronous detector which is commonly utilized for generation of an intercarrier sound signal. Referring to FIG. 1, the video intermediate frequency signal from the final stage of the video intermediate frequency amplifier is applied to a video carrier frequency signal extracting circuit 1 and a multiplier 2. The video intermediate frequency carrier signal of the frequency 58.75 MHz obtained from the video intermediate frequency carrier signal extracting circuit 1 is also applied to the other input of the multiplier 2. The multiplier is responsive to the video intermediate frequency carrier signal from the video intermediate frequency signal extracting circuit 1 and the video intermediate frequency signal from the video intermediate frequency amplifier to effect synchronous detection of the video intermediate frequency signal as a function of the video intermediate frequency carrier signal to provide a detected video signal, as well known to those skilled in the art. The detected video output is applied to a video circuit 3. As well known to those skilled in the art, the multiplier 2 also provides an intercarrier sound signal of the frequency 4.5 MHz that is a beat of the video carrier frequency 58.75 MHz and the sound carrier frequency 54.25 MHz (Japanese Television Standard). The intercarrier sound signal is applied to a sound circuit 4.
FIG. 2 shows a schematic diagram of the video intermediate frequency carrier signal extracting circuit 1 and the multiplier 2, as implemented in an integrated circuit. The video intermediate frequency signal as received as a differential signal at input terminals 5 and 6 is applied to a pair of emitter followers Q1 and Q2 and the output video intermediate frequency signals from the emitter followers Q1 and Q2 are applied to the base electrodes of a pair of differential operating transistors Q3 and Q4, respectively, constituting a differential amplifier that constitutes the video intermediate frequency carrier signal extracting circuit 1. The collector electrodes of the differential operating transistors Q3 and Q4 are coupled to a parallel connection of an inductance coil L1 and a capacitor C1 provided externally of the integrated circuit that constitutes a tuning circuit 7 tuned to the central frequency of 58.75 MHz. Therefore, the video intermediate frequency carrier signal is extracted at the collector electrodes of the above described differential operating transistors Q3 and Q4. The collector electrodes of the differential operating transistors Q3 and Q4 are coupled to each other through diodes D1 and D2 in opposite polarities. Therefore, the video intermediate frequency carrier signal as obtained at the collector electrodes of the differential operating transistors Q3 and Q4 are subjected to a limiting function by these diodes D1 and D2, whereby the video intermediate frequency carrier signal is pulsed or is converted into a pulse form. The pulse signal of the video intermediate carrier frequency is obtained at each of the collector electrodes of the differential operating transistors Q3 and Q4 in an opposite polarity to each other and is applied to the corresponding one of a pair of emitter followers Q5 and Q6. The pulse outputs from the emitter followers Q5 and Q6 are applied as a switching control signal to the base electrodes of a pair of upper differential operating transistors Q7 and Q8 and another pair of upper differential operating transistors Q9 and Q10 of a double balanced synchronous detector that constitutes the multiplier 2. On the other hand, the base electrodes of a further pair of lower differential operating transistors Q11 and Q12 of the above described multiplier 2 are connected to receive the video intermediate frequency signal obtainable from the emitter followers Q1 and Q2. As a result, multiplication is made of the video intermediate frequency signal from the emitter followers Q1 and Q2 and the above described pulse control signal as applied to the upper differential operating transistors. As a result, a detected video signal is obtained through synchronous detection and an intercarrier sound signal of the frequency 4.5 MHz is obtained as a beat of the video and sound carrier frequencies at output terminals 8 and 9 as a differential output form. The video signal and the intercarrier sound signal thus obtained are separately extracted by individual filters, not shown, to be provided in the video and sound circuits, respectively.
Since in the above discussed conventional video/intercarrier sound dectecting circuit a detected video signal and an intercarrier sound signal are obtained by the use of a single common multiplier structured to make multiplication of the video intermediate frequency signal by a pulse output of the video intermediate frequency carrier signal as a switching operation, buzz noises and the like are liable to occur for the reasons to be described in the following, that degrade the sound quality in television receivers. More specifically, since the video intermediate frequency signal is obtained from a televised signal, the amplitude of the extracted video intermediate frequency carrier signal is liable to fluctuate, as shown in FIG. 3, in accordance with amplitude modulation. Therefore, when the extracted video intermediate frequency carrier signal is pulsed by means of the limiting diodes D1 and D2 to unify the signal level, a portion a having a large amplitude is completely pulsed as shown as a' in FIG. 4, while portions b and c having smaller amplitude is incompletely pulsed as shown as b' in FIG. 4 or is not pulsed at all as shown as c' in FIG. 4, with the result that pulsing is diversified depending on the amplitude modulation, and thus a residual amplitude component contained in the switching control signal as applied to the multiplier 2.
Another problem is caused with the above described conventional video/intercarrier sound detecting circuit as shown in FIG. 2. More specifically, when one of the limiting diodes D1 and D2 becomes conductive, the other is cut off to function as a capacitance. As a result, it follows that these diodes D1 and D2 exhibits a somewhat rectifying function with respect to the extracted video intermediate frequency signal, which causes harmonics with respect to the above described amplitude modulation component. This means that when a video signal of the frequency 2.25 MHz is received, a frequency component 4.5 MHz that is the second harmonic of the above described video signal is applied to the base electrodes of the upper stage pairs of differential operating transistors Q7 and Q8 and Q9 and Q10 constituting the multiplier 2. As a result, a pseudo sound signal is obtained and is applied to the sound circuit 4, thereby to degrade the quality of sound.
In this context, a video/intercarrier sound detecting circuit of interest is described in the article, entitled "A New TV Video/Intercarrier Sound Detector IC" by Milton E. Wilcox, in IEEE Transaction on Broadcast and TV Receivers. The above discussed problems encountered in the video/intercarrier sound detector shown in FIGS. 1 and 2 are solved to some extent by the video/intercarrier sound detector described in the above referenced article. More specifically, in accordance with the above referenced article, a separate sound detector is employed. The approach used therein is a half wave equivalent of the multiplier which switches the video carrier with the sound carrier input signal to produce a desired difference frequency. The sound detecting circuit shown has a separate input for the sound carrier and applies the video carrier signal derived in the video detector to the base electrodes of the lower differential operating transistors of the half wave equivalent of the multiplier. The output is tuned to the sound intermediate frequency of 4.5 MHz. Nevertheless, the problems discussed previously in conjunction with the sound quality are not fully solved by the video/intercarrier sound detector in the above referenced article. More specifically, in accordance with the video/intercarrier sound detector in the above referenced article, the video carrier signal derived in the video detector is applied to the sound detector, which means that the video carrier signal of a very large signal level is applied to the sound detector rather in the form of a switching control signal. Thus, according to the above referenced article, the sound detector does not operate in a linear manner but rather operates in a non-linear manner. The fact that the sound detector operates rather in a non-linear manner is liable to cause harmonics, which degrades the quality of sound, as fully discussed previously. In this context, there is room for improvement in the video/intercarrier sound detector described in the above referenced article.
SUMMARY OF THE INVENTION
Briefly described, the present invention comprises a television receiver, comprising: a video intermediate frequency amplifier, means coupled to the video intermediate frequency amplifier for extracting the video intermediate frequency
carrier signal, synchronous detecting means responsive to the video intermediate frequency carrier signal from the video intermediate frequency carrier extracting means and the video intermediate frequency output from the video intermediate frequency amplifier for synchronously detecting the video intermediate frequency signal with the video intermediate frequency carrier signal for providing a detected video signal, means for withdrawing the detected video signal, multiplier means having first and second inputs each receiving the video intermediate frequency signal for evaluating the product of the first input signal and the second input signal including a difference component of the video and sound carriers, and means responsive to the product output from the multiplier means for withdrawing an intercarrier sound signal.
According to the present invention, the sound detecting multiplier is adapted to receive directly the video intermediate frequency signal as the first and second input signals. Since the video intermediate frequency signal is utilized which is of a low level and a linear form, a multiplying operation is carried out in a rather linear manner. As a result, the harmonics occuring in the multiplying operation is considerably reduced. As a result, the quality of sound as reproduced is enhanced.
According to another aspect of the present invention, a phase shifter means is provided for causing a phase difference of an odd number times the phase of π/2 between the first and second input signals to be applied to the sound detecting multiplier. As a result, any adverse affect that could be caused by the amplitude modulation component in the video intermediate frequency signal can be eliminated or extremely reduced.
In a preferred embodiment of the present invention, the first and second inputs of the sound detecting multiplier are coupled to the primary and secondary, respectively, of the last stage video intermediate frequency transformer in the video intermediate frequency amplifier.
Accordingly, a principal object of the present invention is to provide an improved video/intercarrier sound detecting circuit in a television receiver, particularly suited for implementation in an integrated circuit.
Another object of the present invention is to provide an improved video/intercarrier sound detecting circuit in a television receiver, wherein the quality of a reproduced sound is enhanced.
A further object of the present invention is to provide an improved video/intercarrier sound detecting circuit in a television receiver separately employing a synchronous video detector and a sound detecting multiplier.
Still a further object of the present invention is to provide an improved video/intercarrier sound detecting circuit in a television receiver separately employing a synchronous video detector and a sound detecting multiplier, wherein any adverse affect caused by an amplitude modulation component in the video intermediate frequency signal is reduced.
These objects and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 shows a block diagram of a conventional video/intercarrier sound detecting circuit employing a synchronous detector in a television receiver;
FIG. 2 shows a schematic diagram of a video intermediate frequency carrier extracting circuit and a multiplier in a conventional video/intercarrier sound detecting circuit;
FIGS. 3 and 4 show wave forms of electrical signals in the FIG. 2 diagram for explanation of the operation thereof;
FIG. 5 shows a block diagram of the inventive video/intercarrier sound detecting circuit in a television receiver;
FIG. 6 shows a schematic diagram of one embodiment of the inventive video/intercarrier sound detecting circuit; and
FIG. 7 shows a schematic diagram of a portion of a modified embodiment of the inventive video/intercarrier sound detecting circuit.
DESCRIPTION OF THE PREFERRED EMBODIMENTS
According to an essential feature of the present invention, a sound detecting multiplier is separately provided from a synchronous video detector, wherein the sound detecting multiplier is adapted to receive a video intermediate frequency signal without using a pulsed output obtainable from the synchronous video detector.
FIG. 5 shows a block diagram of the inventive video/intercarrier sound detecting circuit. In comparison with the FIG. 1 diagram, the FIG. 5 video/intercarrier sound detecting circuit comprises a second multiplier 10 apart from a first multiplier 2 corresponding to the multiplier 2 in FIG. 2. The second multiplier 10 is connected to receive the video intermediate frequency signal from the video intermediate frequency amplifier as a first and second input signals. The first multiplier 2 is utilized as a synchronous video detector. On the other hand, the second multiplier 10 is utlized as a sound detecting multiplier. The output from the first multiplier 2 is coupled to the video circuit 3 and the output of the second multiplier 10 is coupled to the sound circuit 4. Since the remaining portions in the FIG. 5 diagram are the same as those in the FIG. 1 diagram, it is not believed necessary to describe any more.
FIG. 6 shows a schematic diagram of one embodiment of the inventive video/intercarrier sound detecting circuit in accordance with the FIG. 5 block diagram. Since the FIG. 6 embodiment resembles in part the FIG. 2 diagram, the same portions have been denoted by the same reference characters in FIGS. 2 and 6. In comparison with the FIG. 2 diagram, the FIG. 6 embodiment additionally comprises the second multiplier 10 serving as an intercarrier sound signal generator, which is also configured in a double balanced circuit comprising a first upper stage pair of differential operating transistors Q13 and Q14 and a second upper stage pair of differential operating transistors Q15 and Q16 which are coupled to receive the output from the final stage 11 of the video intermediate frequency amplifier and a lower pair of differential operating transistors Q17 and Q18 coupled to a constant current source 12 and serving by themselves as a constant current to the above described upper stage differential operating transistors Q13 and Q14 and Q15 and Q16, the lower stage differentia
l operating transistors Q17 and Q18 being coupled to receive the video intermediate frequency signal from the emitter followers Q1 and Q2. It is pointed out that the embodiment shown has been adapted such that the signal is applied from the emitter followers Q1 and Q2 to the lower stage transistors Q17 and Q18 in a single ended fashion; however, the circuit may be configured such that the signal is applied in a double ended fashion. It is, therefore, intended that both are covered by the present invention. The collector electrodes of the upper stage differential operating transistors are coupled to load resistors R5 and R6 in a well known manner, as done in conjunction with the first multiplier 2, and the collector electrodes of the upper stage differential operating transistors in the second multiplier 10 are coupled through a 4.5 MHz band pass filter in the sound circuit 4.
As seen from FIG. 6, the base electrodes of the upper stage differential operating transistors Q13 and Q14 and Q15 and Q16 in the second multiplier 10 are coupled to a primary circuit including a parallel connection of an inductance coil L2 and a capacitor C2 of a video intermediate frequency transformer 13 in the final stage video intermediate frequency amplifier 11, while the base electrodes of the lower stage differential operating transistors Q17 and 18 in the second multiplier 10 are coupled to the emitter followers Q1 and Q2 which are coupled to a secondary circuit including a series connection of an inductance coil L3 and a capacitor C3 of the video intermediate frequency transformer 13 in the final stage video intermediate frequency amplifier 11.
Thus, it would be appreicated that the second multiplier 10 is connected to receive the first input from the primary circuit of the final stage video intermediate frequency transformer 13 and the second input signal from the secondary circuit of the final stage video intermediate frequency transformer 13. As a result, the second multiplier 10 is supplied with, at both the first and second inputs thereof, a video intermediate frequency signal of a relatively low level, as not pulsed. Therefore, the second multiplier 10 achieves a relatively linear operation rather than a switching operation. Such a linear operation is facilitated by inserting resistors in the emitter electrodes of the differential operating transistors Q13 and Q14 and Q15 and Q16, thereby to broaden the linear operational range. Since in the FIG. 6 embodiment the second multiplier 10 has been coupled to receive a video intermediate frequency signal of a relatively low level, such emitter resistors have been dispensed with.
In the embodiment shown, a biasing circuit has been improved to implement the same economically, which is particularly advantageous in implementing the inventive video/intercarrier sound detecting circuit and the video intermediate frequency amplifier in a single chip integrated circuit. More specifically, the bias circuit comprises a series connection of a first a
nd second biasing voltage source E1 and E2 and the positive terminal of the second voltage source E2 is coupled to the video intermediate frequency amplifier including the final stage video intermediate frequency amplifier 11 for the purpose of supplying a biasing voltage and the positive terminal of the second voltage source E2 is also applied to the upper stage differential operating transistors of the second multiplier 10, while the junction of the first and second voltage sources E1 and E2 is coupled to the lower stage differential operating transistors Q17 and Q18 through the emitter followers Q1 and Q2, inasmuch as the lower stage differential operating transistors Q17 and Q18 need be supplied with a voltage lower than the voltage to be applied to the upper stage differential operating transistors. The direct current output voltage from the emitter followers Q1 and Q2 is also applied as a base bias of the differential operating transistors Q3 and Q4 constituting the video intermediate frequency carrier extracting circuit 1 for the first video detecting multiplier 2 and is also applied as a base bias of the lower differential operating transistors Q11 and Q12 of the first multiplier 2. Thus, the embodiment shown has been contemplated such that the biasing voltages required at various portions therein are supplied from a least number of biasing voltage sources and the signal transmission path is utilized for supplying the bias voltages to various portions. For this reason, the FIG. 6 embodiment is extremely advantageous in implementing the same together with the remaining portion of the video intermediate frequency amplifiers in a single chip integrated circuit. It is pointed out that the above described final stage video intermediate frequency transformer 13 including the coils L2 and L3 and the capacitors C2 and C3 is provided externally of such an integrated circuit.
As understood from the foregoing description, according to the essential feature of the present invention, a first multiplier of such as a double balanced type is provided for synchronous detection of a video intermediate frequency signal as a function of the pulsed output of the video intermediate frequency carrier signal for providing a detected video signal and a second multiplier of such as a double balanced type is separately provided such that the upper and lower stage differential operating pairs are supplied with a video intermediate frequency signal from the video intermediate frequency signal amplifier, whereby an intercarrier sound signal is obtained through multiplication of two video intermediate frequency signal inputs. It has been observed that according to the inventive video/intercarrier sound detecting circuit any pseudo sound signal encountered in the conventional video/intercarrier sound detecting circuit is eliminated. In addition, since the second multiplier is adapted for a linear operation, any distortion of the sound signal in the second multiplier is avoided and hence the quality of a reproduced sound in a television receiver employing the present invention is enhanced.
Although the FIG. 6 embodiment has substantially eliminated the shortcomings encountered in the prior art video/intercarrier sound detecting circuit, there is still further room for improvement in the FIG. 6 embodiment from the standpoint of reduction of buzz noises for the reasons to be described subsequently. More specifically, it could happen that the video intermediate frequency carrier signal as extracted is still subjected to an amplitude fluctuation for some reason, which could cause harmonics with respect to the above described amplitude fluctuation component. Therefore, when the video signal of the frequency 900 KHz is received, the 4.5 MHz component of the fifth harmonic is applied to the base electrodes of the upper stage differential operating transistors Q7 and Q8 and Q9 and Q10 constituting the first multiplier 2, which causes a pseudo signal in the sound circuit 4, with the result that the quality of a repdocued sound is degraded.
The foregoing may be explained using the following mathematical expression. Assuming that the video modulation index is m, the angular frequency of the modulated signal is ωP, the angular frequency of the video carrier wave is ωC, and the angular frequency of the sound carrier wave is ωS, then the synchronous detection may be expressed by the following formula: [(1+m cos ωPt) cos ωCt+cos ωSt]×[(1+m cos ωPt) cos ωCt+cos ωSt] (1)
However, since only the video carrier wave signal cos ωCt in the video intermediate frequency signal is required to produce the intercarrier sound signal, formula (1) may be expressed as follows: [(1+m cos ωPt) cos ωCt+cos ωSt]×cos ωCt (1A)
When the components 2ωC and (ωS+ωC) in the above described formula are cut by the use of the respective filters, then the following formula is obtained: 1/2 (1+m cos ωPt)+1/2 cos (ωC-ωS) t (2)
The formula (2) corresponds to a case where the carrier wave extracted from the carrier wave extracting circuit is completely pulsed. However, in actuality some amplitude modulation component remains as described previously. Therefore, each term is divided by the residual amplitude modulation component 1+m cos ωPt/A, so that the following formula is obtained: 1/2 (1+m cos ωPt)×(1+m cos ωPt/A)+1/2 cos (ωC-ωS) t×(1+m cos ωPt/A) (3)
The first term in the formula (3) indicates that the harmonics of the modulated signal could appear and that when ωP=ωC-ωS/5 a pseudo signal component ωC-ωS occurs by the component ωP.
If and when the circuit configuration as shown in FIGS. 5 and 6 is employed, then the situation may be expressed by the above described formula (2). Although the first term in the formula (2) does not include any harmonic as different from the above described formula (3), the amplitude modulation signal component of the video signal is required in obtaining an intercarrier sound signal corresponding to the second term and should be preferably eliminated.
Therefore, according to another aspects of the present invention, an improvement in the FIG. 6 embodiment is provided, wherein the first term in the above described formulas (2) and (3) is eliminated to properly eliminate or considerably reduce any influence caused by the amplitude modulation component of the video signal.
More specifically, according to an another aspect of the present invention, the above described second sound detecting multiplier is adapted to receive a first and second input signals with a phase difference of an odd number times the phase of π/2.
In practicing the present invention, if the second sound detecting multiplier 10 is adapted to receive the first and second input signals with a phase difference of π/2, then the following formula is obtained: [(1+m cos ωPt) cos ωCt+cos ωSt]×cos (ωCt+π/2) (4)
If and when the components 2ωC and (ωC+ωS) are removed by means of the respective filters, the above described formula (4) may be expressed as follows: 1/2 cos (ωCt-ωSt+π/2) (5)
The above described formula (5) may further be changed to the following: -1/2 sin (ωC-ωS) t (6)
Thus it would be appreciated that nothing corresponding to the first term in the formula (2) occurs. Assuming that the same is applied to the FIG. 5 embodiment, then it would be further appreciated that as seen in the formulas (5) and (6) no amplitude modulation component occurs.
FIG. 7 shows a schematic diagram of a left half portion in the FIG. 6 embodiment, wherein the above described additional feature of the present invention has been practiced. In the following, only a modified portion will be described in the FIG. 7 embodiment in comparison with the FIG. 6 embodiment. Since the remaining portions in the FIG. 7 embodiment are substantially the same as those in the FIG. 6 embodiment and have been denoted by the same reference characters, it is not believed necessary to describe the same again in detail. Now with particular reference to the left portion in FIG. 7, and particularly to a line running from the primary circuit of the video intermediate frequency transformer 13 to the base electrode of the transistor Q13, a phase shifter 14 is interposed in the line, such that one input signal to the multiplier 10 is phase shifted by the phase π/2 or an odd number times the phase π/2 with respect to the second input signal to be applied to the multiplier 10. As a result, the foregoing description made in conjunction with the mathematical equations is achieved and a reproduced sound of good quality is effectively obtained.
Although the present invention has been described and illustrated in detail, it is to be clearly understood that the same is by way of illustration and example only and is not to be taken by way of limitation, the spirit and scope of the present invention being limited only by the terms of the appended claims.
