PHILIPS 26CS3277 chassis K35 Units view .

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Mains Rectifier + Degauss: 8222 280 3135.2

- Supply Control with TDA2581Q (PHILIPS) :8222 280 3123.0

- IF Video Dem + Ampl with TDA2541 (PHILIPS):8222 280 2109.5

- Synchronization with TDA3571Q (PHILIPS):8222 280 3266.0

- Luminance + Chrominance with TDA3560 (PHILIPS):8222 280 3145.1

- Tuner / channel selector VHF :3122 127 41511

- Tuner / channel selector UHF :3112 218 5155

- Sound with TBA120S (Telefunken) :3104 303 30410

- Prescaler (Tuning Frequency Divider) with SAB1018P (PHILIPS):3112 248 57680

- Tuning control system TRD4 with uController D8049PC 163 (NEC) + SAB3034 (PHILIPS) +
ER1400 (hybrid IC)


TDA2541 IF AMPLIFIER WITH DEMODULATOR AND AFC

DESCRIPTION
The TDA2540 and 2541 are IF amplifier and A.M.
demodulator circuits for colour and black and white
televisionreceiversusingPNPorNPNtuners. They
are intended for reception of negative or positive
modulation CCIR standard.
They incorporate the following functions : .Gain controlled amplifier .Synchronous demodulator .White spot inverter .Video preamplifier with noise protection .Switchable AFC .AGC with noise gating .Tuner AGC output (NPN tuner for 2540)-(PNP
tuner for 2541) .VCR switch for video output inhibition (VCR
play back).


SAB3034 COMPUTER INTERFACE FOR TUNING AND CONTROL (CITAC)

GENERAL DESCRIPTION
The SAB3034 provides closed-loop digital tuning of TV receivers, with or without a.f.c., as required. lt
also controls up to 8 analogue functions, 4 general purpose I/O ports and 4 high-current outputs for
tuner band selection.
The IC is used in conjunction with a microcomputer from the MAB84OO family and is controlled via a two-wire, bidirectional I2 C bus.
Featu res
Combined analogue and digital circuitry minimizes the number of additional interfacing components
required
Frequency measurement with resolution of 50 KHz
Selectable prescaler divisor of 64 or 256
32 V tuning voltage amplifier
4 high-current outputs for direct band selection
8 static digital to analogue converters (DACSI for control of analogue functions
Four general purpose input/output (l/O) ports
Tuning with control of speed and direction
Tuning with or without a.f.c.
Single-pin, 4 MHZ on-chip oscillator
I2 C bus slave transceiver

FUNCTIONAL DESCRIPTION
The SAB3034 is a monolithic computer interface which provides tuning and control functions and
operates in conjunction with a microcomputer via an I2 C bus.
Tuning
This is performed using frequency-locked loop digital control. Data corresponding to the required tuner
frequency is stored in a 15-bit frequency buffer. The actual tuner frequency, divided by a factor of 256
(or by 64) by a prescaler, is applied via a gate to a 15-bit frequency counter. This input (FDIV) is
measured over a period controlled by a time reference counter and is compared with the contents of the frequency buffer. The result of the comparison is used to control the tuning voltage so that the tuner frequency equals the contents of the frequency buffer multiplied by 50 kHz within a programmable tuning window (TUW).

The system cycles over a period of 6,4 ms (or 2,56 ms), controlled by the time reference counter which is clocked by an on-chip 4 lVlHz reference oscillator. Regulation of the tuning voltage is performed by a charge pump frequency-locked loop system. The charge IT flowing into the tuning voltage amplifier is controlled by the tuning counter, 3-bit DAC and the charge pump circuit. The charge IT is linear with the frequency deviation Af in steps of 50

D8049AH

8-Bit Microcontroller-Microcomputer - Over 96 instructions, all 1-2 cycles
Intel
8-Bit Microcontrollers
Clock Frequency - Max. (Hz)=11.0M
Clock Frequency - Min. (Hz)=1.0M
Min Instruction Length (bits)=8
Max Instruction Length (bits)=16
Memory Addressing Range=64k
Number of Addressing Modes=5
On-Chip RAM (Bytes)=128
On-Chip ROM (bytes)=2k
Number of Interrupt Lines=1
No. of Non-Maskable Interrupts=0
Number of Maskable Interrupts=1
Number of I/O Lines=16
No. of I/O Ports=2
Vsup Nom.(V) Supply Voltage=5.0
Package=DIP
Pins=40
Military=N
Technology=NMOS


TDA3571 SYNC COMBINATION WITH TRANSMITTER IDENTIFICATION

AND VERTICAL 625 DIVIDER SYSTEM
GENERAL DESCRIPTION
The TDA3571 B is a monolithic integrated circuit for use in colour television receivers with switched-
mode driven or self-regulating horizontal time-base circuits. It is designed in combination with the
TDA2581 to operate as a matched pair. When supplied with a composite video signal the TDA3571 B
delivers drive pulses for the TDA2581 and sync pulses for the vertical deflection. The circuit is
optimized for a horizontal and vertical frequency ratio of 625. It incorporates the following features:
Features
O Horizontal sync separator (including noise inverter) I
O Horizontal phase detector
0 Horizontal oscillator (31,25 kHz)
0 Sandcastle pulse generator
O Vertical sync pulse separator
O Very stable automatic vertical synchronization due to the 625 divider system, without delay after
channel change
I Three voltage level sensor on coincidence detector circuit output
I Video transmitter identification circuit for sound muting and search tuning systems
O Inhibit of vertical sync pulse when no video transmitter is detected
QUICK REFERENCE DATA
Supply voltage _
horizontal (pin 14) V14_13 typ. 12 V
vertical (pin 18) V13_13 typ. 12 V
Supply current (pin 14 + pin 18) V14+18 typ. 52 mA
Sync separator
input voltage level (peak-to-peak value) V2.131p.p) 0,07 to I V
slicing level typ. 50 % _
Output pulse E
horizontal (peak-to-peak value) V3_131p_p1 min. 10 V =
vertical sync (peak-to-peak value) V1_131p_p1 min. 10 V —
burst key (peak-to~peak value) V15_131p_p1 min. 10 V
Video transmitter identification circuit
Output voltage (pin 10)
sync pulse present V10_13 typ. 8 V
no sync pulse V1Q_13 max. 1 V
Phase locked loop
control sensitivity typ. 2000 Hz/;1s
holding range Af typ. 1 1000 Hz
catching range Af typ. : 900 Hz
Operating ambient temperature range Tamb -25 to + 65 °C
PACKAGE OUTLINE
18-lead DIL; plastic (SOT-102A).

FUNCTIONAL DESCRIPTION
The video input voltage to drive the sync separator must have negative-going sync, which can be
obtained from synchronous demodulators such as TDA2540, TDA2541 and TDA2670.
The slicing level of the sync separator is determined by the value of the resistor between pins 3 and 4.
A 5,6 kfl resistor provides a slicing level midway between the top sync level and the blanking level.
Thus the slicing level is independent of the amplitude of the sync pulse input at pin 2.
The nominal top sync level at pin 2 is 1,5 V, and the amplitude selective noise inverter is activated at
0,7 V. The horizontal phase detector has a steepness of 1,2 V/its and together with the 1800 Hz/V of
the horizontal oscillator provides a total control steepness of 2000 Hz/us.
A second horizontal phase detector provides a 5,5 its pulse which ensures symmetrical gating of the
horizontal synchronization. During catching the gating is automatically switched off. At the same time
the flywheel filter is switched to a short time constant. The value of this time constant can be deter~
mined externally via pin 11.
When the indirect vertical sync output is generated by the 625 divider system an anti-top flutter pulse
switches off the equalizing and vertical sync pulse operation of the phase detector. Thus top flutter
distortion of the control voltage due to vertical pulses can be anticipated. When the 625 divider system
is in the direct mode the anti~top flutter pulse is inhibited.
The free running output frequency of the horizontal oscillator is 31,25 kl-lz. The vertical frequency
output is obtained by dividing this double horizontal frequency by 625. The double horizontal
frequency is fed via a binary divider to provide the normal 15,625 kHz horizontal output at pin 8. The
trailing edge of this pulse is positioned 0,9 us after the end of the video sync pulse input at pin 2
(see Fig. 2).
The automatic vertical sync block contains the following:
0 625 divider
0 In/out-sync detector
I Direct/indirect sync switch
O Identification circuit
It is fed by a signal obtained by integration of the composite sync signal and an internally generated,
clipped video signal. The vertical sync pulse is sliced out of this integrated signal by an automatically
biased clipper. The videopart of the signal helps to build up a vertical sync pulse when heavy negative-
going reflections (mountains) distort the video signal. The in/out sync-detector considers a signal
out~of-sync when fifteen or more successive incoming vertical sync pulses are not in phase with a
reference signal from the 625 divider. Therefore a distorted vertical sync signal needs only one
out-of-fifteen pulses to be in phase to keep the system in sync. When the sixteenth successive out-of-
sync pulse is detected, the direct/indirect sync switch is activated to feed the vertical sync signal
directly out of the block at pin 2 (direct sync vertical output).
At the same time the 625 divider is reset by one of the sync pulses. After the reset pulse, if the 7th
sliced vertical sync pulse coincides with a 625 divider window, the sync output pulse is presented
again by the divider system and switch-over to indirect mode occurs.
In the direct mode, every 7th non-coinciding sliced vertical sync pulse will reset the counter. Thus a
non-standard video signal will result in continuous reset pulses and the direct/indirect switch will
remain in the direct position.
To avoid delay in vertical synchronization, caused by waiting time of the divider circuit after channel
change or an unsynchronized camera change in the studio, information is fed from the horizontal coin-
cidence detector to the automatic switch for the vertical sync pulse. The loss of horizontal synchroni-
zation sets the automatic switch to direct vertical sync. When horizontal coincidence is detected again
the setting of the automatic switch depends on whether a standard video signal is received or not. When
an external voltage between 2,5 V and 7,25 V is applied via pin 12 to the coincidence detector, the hor-
izontal phase detector is swsync. A voltage level on pin 12 > 8,25 V switches the horizontal phase detector to a short time constant,
without affecting the indirect/direct vertical sync system which remains operational.
The video transmitter identification circuit detects when a sync pulse occurs during the internal gating
pulse. This indicates the presence of a video transmitter and results in the capacitor connected to pin
10 being charged to 8 V. When no sync pulse is present the capacitor discharges to < 1 V. The voltage
at pin 10 is compared with an internal d.c. voltage. The identification output at pin 9 is active when
pin 10 is < 1,6 V (no video transmitter) and inactive (high impedance) when pin 10 is > 3,5 V.
The vertical sync output pulse at pin 1 is inhibited when no video transmitter is identified, which
prevents interference or noise affecting the frequency of the vertical output stage. This results in a vertical stable picture, plus vertical stable position information of tuning systems.

TDA2581 CONTROL CIRCUIT FOR SMPS

The TDA2581 is a monolithic integrated circuit for controlling switched-mode power supplies (SMPS) which are provided with the drive for the horizontal deflection stage.
The circuit features the following:
— Voltage controlled horizontal oscillator.
— Phase detector.
— Duty factor control for the positive-going transient of the output signal.
— Duty factor increases from zero to its normal operation value.
— Adjustable maximum duty factor.
- Over-voltage and over-current protection with automatic re-start after switch-off.
— Counting circuit for permanent switch-off when n~times over~current or over-voltage is sensed

-Protection for open-reference voltage.
- Protection for too low supply voltage.
Protection against loop faults.
Positive tracking of duty factor and feedback voltage when the feedback voltage is smaller than the
reference voltage minus 1,5 V.



TDA2541 IF AMPLIFIER WITH DEMODULATOR AND AFC

DESCRIPTION
The TDA2540 and 2541 are IF amplifier and A.M.
demodulator circuits for colour and black and white
television receivers using PNP or NPN tuners. They
are intended for reception of negative or positive
modulation CCIR standard.
They incorporate the following functions : .Gain controlled amplifier .Synchronous demodulator .White spot inverter .Video preamplifier with noise protection .Switchable AFC .AGC with noise gating .Tuner AGC output (NPN tuner for 2540)-(PNP
tuner for 2541) .VCR switch for video output inhibition (VCR
play back).




.SUPPLYVOLTAGE : 12V TYP
.SUPPLYCURRENT : 50mATYP
.I.F. INPUT VOLTAGE SENSITIVITY AT
F = 38.9MHz : 85mVRMS TYP
.VIDEO OUTPUT VOLTAGE (white at 10% of
top synchro) : 2.7VPP TYP
.I.F. VOLTAGE GAIN CONTROL RANGE :
64dB TYP .SIGNAL TO NOISE RATIO AT VI = 10mV :
58dB TYP
.A.F.C. OUTPUT VOLTAGE SWING FOR
Df = 100kHz : 10V TYP

The TDA3560A
is a decoder for the PAL colour television standard. It combines all functions required for the identification
and demodulation of PAL signals. Furthermore it contains a luminance amplifier, an RGB-matrix and amplifier. These
amplifiers supply output signals up to 5 V peak-to-peak (picture information) enabling direct drive of the discrete output
stages. The circuit also contains separate inputs for data insertion, analogue as well as digital, which can be used for
text display systems (e.g. (Teletext/broadcast antiope), channel number display, etc. Additional to the TDA3560, the
circuit includes the following features:
· The peak white limiter is only active during the time that the 9,3 V level at the output is exceeded. The start of the
limiting function is delayed by one line period. This avoids peak white limiting by test patterns which have abrupt
transitions from colour to white signals.
· The brightness control is obtained by inserting a variable pulse in the luminance channel. Therefore the ratio of
brightness variation and signal amplitude at the three outputs will be identical and independent of the difference in gain
of the three channels. Thus discolouring due to adjustment of contrast and brightness is avoided.
· Improved suppression of the internal RGB signals when the device is switched to external signals, and vice versa.
· Non-synchronized external RGB signals do not disturb the black level of the internal signals.
· Improved suppression of the residual 4,4 MHz signal in the RGB output stages.
· Cascoded stages in the demodulators and burst phase detector minimize the radiation of the colour demodulator
inputs.
· High current capability of the RGB outputs and the chrominance output.

APPLICATION INFORMATION
The function is described against the corresponding pin
number.
1. + 12 V power supply
The circuit gives good operation in a supply voltage range
between 8 and 13,2 V provided that the supply voltage for
the controls is equal to the supply voltage for the
TDA3561A. All signal and control levels have a linear
dependency on the supply voltage. The current taken by
the device at 12 V is typically 85 mA. It is linearly
dependent on the supply voltage.
2. Control voltage for identification
This pin requires a detection capacitor of about 330 nF for
correct operation. The voltages available under various
signal conditions are given in the specification.
3. Chrominance input
The chroma signal must be a.c.-coupled to the input.
Its amplitude must be between 55 mV and 1100 mV
peak-to-peak (25 mV to 500 mV peak-to-peak burst
signal). All figures for the chroma signals are based on a
colour bar signal with 75% saturation, that is the
burst-to-chroma ratio of the input signal is 1 : 2,25.
4. Reference voltage A.C.C. detector
This pin must be decoupled by a capacitor of about 330
nF. The voltage at this pin is 4,9 V.
5. Control voltage A.C.C.
The A.C.C. is obtained by synchronous detection of the
burst signal followed by a peak detector. A good noise
immunity is obtained in this way and an increase of the
colour for weak input signals is prevented. The
recommended capacitor value at this pin is 2,2 mF.
6. Saturation control
The saturation control range is in excess of 50 dB.
The control voltage range is 2 to 4 V. Saturation control is
a linear function of the control voltage.
When the colour killer is active, the saturation control
voltage is reduced to a low level if the resistance of the
external saturation control network is sufficiently high.
Then the chroma amplifier supplies no signal to the
demodulator. Colour switch-on can be delayed by proper
choice of the time constant for the saturation control
setting circuit.
When the saturation control pin is connected to the power
supply the colour killer circuit is overruled so that the colour
signal is visible on the screen. In this way it is possible to
adjust the oscillator frequency without using a frequency
counter (see also pins 25 and 26).
7. Contrast control
The contrast control range is 20 dB for a control voltage
change from + 2 to + 4 V. Contrast control is a linear
function of the control voltage. The output signal is
suppressed when the control voltage is 1 V or less. If one
or more output signals surpasses the level of 9 V the peak
white limiter circuit becomes active and reduces the output
signals via the contrast control by discharging C2 via an
internal current sink.
8. Sandcastle and field blanking input
The output signals are blanked if the amplitude of the input
pulse is between 2 and 6,5 V. The burst gate and clamping
circuits are activated if the input pulse exceeds a level of
7,5 V.
The higher part of the sandcastle pulse should start just
after the sync pulse to prevent clamping of video signal on
the sync pulse. The width should be about 4 ms for proper
A.C.C. operation.
9. Video-data switching
The insertion circuit is activated by means of this input by
an input pulse between 1 V and 2 V. In that condition, the
internal RGB signals are switched off and the inserted
signals are supplied to the output amplifiers. If only normal
operation is wanted this pin should be connected to the
negative supply. The switching times are very short
(< 20 ns) to avoid coloured edges of the inserted signals
on the screen.
10. Luminance signal input
The input signal should have a peak-to-peak amplitude of
0,45 V (peak white to sync) to obtain a black-white output
signal to 5 V at nominal contrast. It must be a.c.-coupled to
the input by a capacitor of about 22 nF. The signal is
clamped at the input to an internal reference voltage.
A 1 kW luminance delay line can be applied because the
luminance input impedance is made very high.
Consequently the charging and discharging currents of the
coupling capacitor are very small and do not influence the
signal level at the input noticeably. Additionally the
coupling capacitor value may be small.