ITT DIGIVISION 3888 I HI FI Chassis DIGI B 110° FST Digital Deflection Processing and Case Study: Digital TV - Digivision ITT.

Deflection Signal Processing
Video Clamping Circuit
During line retrace, the clamping circuit (output Pin 21,
DPU 2540) maintains the analog video signal at the correct
working point of the integrated analog-digital converter, at the
input of Video Codec IC VCU 2133, Pin 35. For the second
video input at Pin 37 of the VCU, Pin 4 of the DPU delivers a
further clamping pulse.
Pulse Separation
The digitized FBAS (composite colour) signal, which is supplied
as a parallel 7-bit signal from the Video Codec IC 650
(VCU 2133, Pins 2-8) to IC 620 (DPU 2540, Pins 15-9), passes
through a digital low-pass filter internally for interference
elimination, and is then fed in parallel to the circuits for
separating the horizontal and vertical synchronous pulses. The
circuits function independently of each other, and thus ensure
optimum separation.
Horizontal Synchronization
Two operating modes are provided for horizontal
synchronization, depending on whether the station received (or
the video recorder connected) is transmitting a standard PAL
signal, in which a fixed frequency-response ratio between colour
carrier frequency and line frequency does or does not apply. In
the former case, we speak of colour-locked mode, in the second
case of non-locked mode. Switch-over between these two
modes is performed automatically by the standard-signal
detector. In colour-locked mode. after the phase position has
been adjusted in non-locked mode, the programmable
frequency divider is set to the standard divider ratio, and the
phase comparison function between synchronous pulses and
horizontal retrace is switched off, so that interference pulses
and noise no longer affect the horizontal deflection fucntion. ln
non-locked mode, which is necessary when the colour carrier
frequency and the line frequency of the station do not have a
fixed frequency ratio, the line frequency is generated by dividing
down the clock pulse frequency of 17.7 MHz in the
programmable divider so as to produce the correct line
frequency. Correct phase position of this line frequency is
ensured by the phase comparator, which detects the phase and
frequency errors by means of digital phase comparison between
the separated horizontal synchronous pulses and the horizontal
retrace pulses at Pin 23, and corrects the programmable divider
accordingly.
The line-frequency deflection signal is then available at Pin 31
of DPU 2540 for controlling the deflection circuit and generating
the high voltage. Note that this signal already contains all
necessary corrections, which have been carried out inside the
IC via the IM Bus by comparison with the alignment data stored
in the CCU memory.
Vertical Synchronization
As with horizontal synchronization, we also distinguish here
between colour-locked and non-locked modes. In colour-locked
mode, the line frequency is divided down in a fixed ratio so as to
obtain the vertical frequency. In non-locked mode, the settable
divider is operated as a trigger oscillator, and triggered by the
integrated vertical synchronous pulse, with a large trigger
window being used to trap the synchronization, while for
operation the system then switches over to a small trigger
window. All these mode switch-over functions are performed
automatically.
The vertical deflection sawtooth is generated digitally, including
all correction values such as linearity, amplitude and position,
and results from the output signals of Pins 26 and 27. It is
passed via DV 2 to Pin 1 of IC 401, the integrated vertical output
stage TDA 8172. The vertical parabola required for controlling
the east-west modulator is also supplied at Pin 28 by the
deflection processor, and fed via DV 23 to the base of T 562.


Case Study: Digital TV - Digivision ITT
I will explain why this system is the father of all digital video/audio modern application field.
Today there is a race to design interoperable video systems for basic digital computer functions, involving multimedia applications in areas such as media information, education, medecine and entertainment, to name but a few. This chapter provides an overview of the current status in industry of digitized television including techniques used and their limitations, technological concerns and design methodologies needed to achieve the goals for highly integrated systems. Digital TV functions can be optimized for encoding and decoding and be implemented in silicon in a more dedicated way using a kind of automated custom design approach allowing enough flexibility.

Significance of VLSI for Digital TV Systems

When, at the 1981 Berlin Radio and TV Exhibition, the ITT Intermetall company exhibited to the public for the first time a digital television VLSI concept [1], [2], opinions among experts were by no means unanimously favourable. Some were enthusiastic, while others doubted the technological and economic feasibility. Today, after 13 years, more than 30 million TV sets worldwide have already been equipped with this system. Today, the intensive use of VLSI chips does not need a particular justification, the main reasons being increased reliability mainly because of the long-term stability of the color reproduction brought about by digital systems, and medium and long-term cost advantages in manufacturing which are essential for ensuring international competitiveness.

Digital signal processing permits solutions that guarantee a high degree of compatibility with future developments, whether in terms of quality improvements or new features like intermediate picture storage or adaptive comb filtering for example. In addition to these benefits, a digital system offers a number of advantages with regard to the production of TV sets:

- Digital circuits are tolerance-free and are not subject to drift or aging phenomena. These well-known properties of digital technology considerably simplify factory tuning of the sets and even permit fully automated, computer-controlled tuning.

- Digital components can be programmable. This means that the level of user convenience and the features offered by the set can be tailored to the manufacturer's individual requirements via the software.

- A digital system is inherently modular with a standard circuit architecture. All the chips in a given system are compatible with each other so that TV models of various specifications, from the low-cost basic model to the multi-standard satellite receiver, can be built with a host of additional quality and performance features.

- Modular construction means that set assembly can be fully automated as well. Together with automatic tuning, the production process can be greatly simplified and accelerated.

Macro-function Processing

The modular design of digital TV systems is reflected in its subdivision into largely independent functional blocks, with the possibility having special data-bus structures. It is useful to divide the structure into a data-oriented flow and control-oriented flow, so that we have four main groups of components:

1.- The control unit and peripherals, based on well-known microprocessor structures, with a central communication bus for flexibility and ease to use. An arrangement around a central bus makes it possible to easily expand the system constantly and thereby add on further quality-enhancing and special functions for the picture, text and/or sound processing at no great expense. A non-volatile storage element, in which the factory settings are stored, is associated to this control processor.

2.- The video functions are mainly the video signal processing and some additional features like for example deflection, a detailed description follows in the paper. However, the key point for VLSI implementations is a well-organized definition of the macro-blocks. This serves to facilitate interconnection of circuit components, and minimizes power consumption, which can be considerable at the processor speeds needed.

3.- The digital concept facilitates the decoding of today’s new digital sound broadcasting standards as well as the input of external signal sources, such as Digital Audio Tape (DAT) and Compact Disk (CD). Programmability permits mono, stereo, and multilingual broadcasts; the compatibility with other functions in the TV system is resolved with the common communication bus. This leads us to part two which is dedicated to the description of this problem.

4.- With a digital system, it is possible to add some special or quality-enhancing functions simply by incorporating a single additional macro-function or chip. Therefore, standards are no longer so important due to the high level of adaptability of digital solutions. For example adaptation to a 16:9 picture tube is easy.

In this chapter we first discuss the digitization of TV functions by analyzing general concepts based on existing systems. The second section deals with silicon technologies and, in particular design methodologies concerns. The intensive use of submicron technologies associated with fast on chip clock frequencies and huge numbers of transistors on the same substrate affects traditional methods of designing chips. As this chapter only outlines a general approach of the VLSI integration techniques for Digital TV

II. DIGITIZATION OF "TV FUNCTIONS"

The idea of digitization of TV functions is not new. The time some companies have started to work on it, silicon technology was not really adequate for the needed computing power so that the most effective solutions were full custom designs. This forced the block-oriented architecture where the digital functions introduced were the one to one replacement of an existing analog function. In Figure 2 there is a simplified representation of the general concept.

Fig.2: Block Diagram of first generation digital TV set

The natural separation of video and audio resulted in some incompatibilities and duplication of primary functions. The emitting principle is not changed, redundancy is a big handicap, for example the time a SECAM channel is running, the PAL functions are not in operation. New generations of digital TV systems should re-think the whole concept top down before VLSI system partitioning.

In today’s state-of-the-art solution one can recognize all the basic functions of the analog TV set with, however, a modularity in the concept, permitting additional features becomes possible, some special digital possibilities are exploited, e.g. storage and filtering techniques to improve signal reproduction (adaptive filtering, 100 Hz technology), to integrate special functions (picture-in-picture, zoom, still picture) or to receive digital broadcasting standards (MAC, NICAM). The Figure 3 shows the ITT Semiconductors solution which was the first on the market in 1983 !! !!

Fig.3: The DIGIT2000 TV receiver block diagram

Description:
This invention relates generally to digital television receivers and, particularly, to digital television receivers arranged for economical interfacing with a plurality of auxiliary devices.

With the proliferation of low cost microprocessors and microprocessor controlled devices, television (TV) receivers are being designed to utilize digitized signals and controls. There are many advantages associated with digital TV receivers, including uniformity of product, precise control of signal parameters and operating conditions, elimination of mechanical switches and a potential for reliability that has been heretofore unknown. Digital television receivers include a high speed communication bus for interconnecting a central control unit microprocessor (CCU) with various TV function modules for processing a TV signal. These modules include a deflection processing unit (DPU), a video processing unit (VPU), an automatic phase control (APC), a video codec unit (VCU), an audio analog to digital converter (ADC) and an audio processing unit (APU). The CCU has associated with it a non-volatile memory, a hardware-generated clock signal source and a suitable interface circuit for enabling the CCU to control processing of the TV signal throughout the various TV function modules. The received TV signal is in analog form and suitable analog to digital (A/D) converters and digital to analog (D/A) converters are provided for converting the digital and analog signals for signal processing and for reconverting them after processing for driving a cathode ray tube (CRT) and suitable speakers. The CCU microprocessor is heavily burdened because of the high speed timing required to control the various TV function modules.
To further complicate matters, modern TV receivers are increasingly being used with auxiliary devices for other than simple processing of TV signals. For example, the video cassette recorder (VCR) has enabled so-called "time-shifting" of program material by recording TV signals for later, more convenient viewing. The VCR is also extensively used with prerecorded material and with programs produced by users having access to a video camera. Other auxiliary devices providing features such as "Space Phone" whereby the user is enabled to make and receive telephone calls through his TV receiver, are desirable options. Additionally, a source selector auxiliary device enables a host of different signal sources, such as cable, over-the-air antenna, video disk, video games, etc. to be connected for use with the signal processing circuitry of the TV. In addition, all of these many auxiliary devices are preferably controllable from a remote position. A great deal of flexibility is available since each of the above auxiliary devices includes a microprocessor for internally controlling functioning of the device.
In the digital TV system described, the CCU microprocessor and the microprocessors in the auxiliary devices may be conventionally arranged to communicate over the main communication bus. Such a system would entail a specialized microprocessor with a hardware-generated clock signal in each auxiliary device in order to communicate at the high speeds used on the main communication bus. A specialized microprocessor, that is, one that is hardware configured, is significantly more expensive than an off-the-shelf microprocessor. Also, the auxiliary devices may not be required, or even desired, by all users and their low volume production cost becomes very important. It would therefore be desirable to provide a digital TV in which such auxiliary devices utilized off-the-shelf microprocessors for their control.



A digital TV system includes a CCU that is interconnected by a three-wire, high speed bus to a plurality of TV signal function modules for controlling operation thereof by means of a high speed hardware generated clock signal. A software generated clock signal in the CCU is supplied on a low speed two-wire auxiliary device bus which is connected to microprocessors in a plurality of auxiliary devices for performing functions ancillary to TV signal processing. The microprocessor in each auxiliary device is an off-the-shelf type that does not require any special hardware because the timing on the auxiliary device bus is sufficiently slow to enable software monitoring of the line and data transfer.
As mentioned, the three-wire IM bus 21 is a high speed bidirectional bus in which CCU 20 functions as the master and all of the interconnected TV signal processing function modules are slaves that communicate with the CCU in accordance with the protocol established for the system. CCU 20 is also indicated as including a software generated clock which supplies a two-wire auxiliary device bus 50. Two-wire bus 50 includes a clock lead 51 and a data lead 52 coupled to a plurality of auxiliary devices. A VCR 54, including an off-the-shelf microprocessor 55, is coupled to bus 50. A Source Selector 56, including an off-the-shelf microprocessor 57, is also coupled to bus 50. Source Selector 56 has access to four RF inputs, two baseband video and audio inputs and one separate baseband audio input. It will be appreciated that Source Selector 56 may have a greater or lesser number of signal sources to which it has access. Source Selector 56 outputs are coupled to VCR 54 and also to tuner 10 and supply, under control of CCU 20 and keyboard 44, the signal from the signal source selected by keyboard 44 or IR transmitter 46 for use with the digital TV. Auxiliary device bus 50 is also coupled to a Space Phone 58 which includes an off-the-shelf microprocessor 59 and a modem 60 that is connectable to a conventional telephone terminal.
Two-wire auxiliary device bus 50 is a relatively low speed bus and there is no need for separate hardware generated clock signals to be developed by the auxiliary device microprocessors. As mentioned above, this feature involves a significant savings in the cost and complexity of the auxiliary devices.
The protocol used on the two-wire auxiliary device bus consists of a 16 bit sequence, the first eight bits of which are used for bus address commands for the auxiliary devices. Each auxiliary device may respond to 16 addresses which allows the CCU to write into or read from various storage registers in the devices which are used for control or data storage. Thus, with this low cost system, as many as 16 auxiliary devices may be connected to the auxiliary device bus. The second eight bits of the 16 bit sequence contain data which is either transferred from the CCU to the auxiliary device addressed, or transferred from the auxiliary device to the CCU, based upon the bus address used. Thus, the various bus addresses to which a given auxiliary device will respond determine whether the auxiliary device will receive data from the CCU or send data to the CCU. The clock line timing, generated by software in CCU 20, is slow enough to permit software monitoring of the line and data reception by simple auxiliary device microprocessors that are not equipped with an external interrupt feature. The timing on the auxiliary device bus is made sufficiently fast to avoid too many instruction steps or the need for special registers in CCU 20. In the system described, data is clocked every 82.5 microseconds, thus permitting a 16 bit word to be clocked in 1.32 milliseconds. A pause of 277.5 microseconds between the first 8 bits and the second 8 bits permits the slave auxiliary device to process the bus address data contained in the first 8 bits. This timing fits into the 2 millisecond timing block structure used for the CCU in controlling the DIGIT 2000 digital TV. Two-2 millisecond timing blocks have been established in the CCU, which has a 20 millisecond timing loop divided into ten-2 millisecond timing blocks. Thus, two control words may be sent to an auxiliary device every 20 milliseconds, or a request by the CCU to receive data and the actual receipt of that data may take place in that time period.



Referring to the drawing, a digital TV includes a tuner 10 coupled to an IF/Detector 12 which has a pair of outputs 13 and 14 supplying video and audio signals, respectively. Control signals for tuner 10 are supplied through an interface circuit 16 from a CCU microprocessor 20 which functions as a single master control unit for the system. Microprocessor 20 is interconnected by means of a bidirectional three-wire IM (Intermetal) bus 21 to a DPU 22, a VPU 26, an APC 30, a TTX (teletext processor) 38, an APU 36, an ADC 32 and a non-volatile memory 24. A serial control line 29 interconnects a hardware generated clock 28, VPU 26 and VCU 34. VPU 26 and VCU 34 are also interconnected by a seven wire cable and TTX 38 is interconnected with a DRAM 42. DRAM 42 is a dynamic RAM in which TTX information is stored for display. VCU 34 is supplied with video signal and supplies a digitized 7 bit grey coded video signal to VPU 24 for processing and RGB color signals to a Video Drive 40 which, in turn, supplies a cathode ray tube (not shown). A keyboard 44 is coupled to CCU 20 and includes an IR detector that is responsive to coded IR signals supplied from an IR transmitter (IRX) 46. A resident microprocessor in keyboard 44 decodes the received IR signals and generated control commands and supplies appropriate outputs to CCU 20. The diagram, as described, is substantially identical to that for a "DIGIT" 2000 VLSI Digital TV System developed by ITT Intermetal and published in Edition 1984/85 Order No. 6250-11-2E

--------------------------

By its very nature, computer technology is digital, while consumer electronics are geared to the analog world. Starts have been made only recently to digitize TV and radio broadcasts at the transmitter end (in form of DAB, DSR, D2-MAC, NICAM etc). The most difficult technical tasks involved in the integration of different media are interface matching and data compression [5].

After this second step in the integration of multimedia signals, an attempt was made towards standardization, namely, the integration of 16 identical high speed processors with communication and programmability concepts comprised in the architecture !

Many solutions proposed today (for MPEG 1 mainly) are derived from microprocessor architectures or DSPs, but there is a gap between today’s circuits and the functions needed for a real fully HDTV system. The AT&T hybrid codec [29], for instance, introduces a new way to design multimedia chips by optimizing the cost of the equipment considering both processing and memory requirements.

The concept is to provide generic architectures that can be applied to a wide variety of systems taking into account that certain functions have to be optimized and that some other complex algorithms have to be ported to generic processors.

Basics of current video coding standards

Compression methods take advantage of both data redundancy and the non-linearity of human vision. They exploit correlation in space for still images and in both space and time for video signals. Compression in space is known as intra-frame compression, while compression in time is called inter-frame compression. Generally, methods that achieve high compression ratios (10:1 to 50:1 for still images and 50:1 to 200:1 for video) use data approximations which lead to a reconstructed image not identical to the original.

Methods that cause no loss of data do exist, but their compression ratios are lower (no better than 3:1). Such techniques are used only in sensitive applications such as medical imaging. For example, artifacts introduced by a lossy algorithm into a X-ray radiograph may cause an incorrect interpretation and alter the diagnosis of a medical condition. Conversely, for commercial, industrial and consumer applications, lossy algorithms are preferred because they save storage and communication bandwidth.

Lossy algorithms also generally exploit aspects of the human visual system. For instance, the eye is much more receptive to fine detail in the luminance (or brightness) signal than in the chrominance (or color) signals. Consequently, the luminance signal is usually sampled at a higher spatial resolution. Second, the encoded representation of the luminance signal is assigned more bits (a higher dynamic) than are the chrominance signals. The eye is less sensitive to energy with high spatial frequency than with low spatial frequency [7]. Indeed, if the images on a personal computer monitor were formed by an alternating spatial signal of black and white, the human viewer would see a uniform gray instead of the alternating checkerboard pattern. This deficiency is exploited by coding the high frequency coefficients with fewer bits and the low frequency coefficients with more bits.

All these techniques add up to powerful compression algorithms. In many subjective tests, reconstructed images that were encoded with a 20:1 compression ratio are hard to distinguish from the original. Video data, even after compression at ratios of 100:1, can be decompressed with close to analog videotape quality.

Lack of open standards could slow the growth of this technology and its applications. That is why several digital video standards have been proposed:

• JPEG (Joint Photographic Expert Group) for still pictures coding
• H.261 at p times 64 kbit/s was proposed by the CCITT (Consultative Committee on International Telephony and Telegraphy) for teleconferencing
• MPEG-1 (Motion Picture Expert Group) up to 1,5 Mbit/s was proposed for full motion compression on digital storage media
• MPEG-2 was proposed for digital TV compression, the bandwith depends on the chosen level and profile [33].

Another standard, the MPEG-4 for very low bit rate coding (4 kbit/s up to 64 kbit/s) is currently being debated.

Digitalization of the fundamental TV functions is of great interest since more than 30 years. Several million of TV sets have been produced containing digital systems. However, the real and full digital system is for the future. A lot of work is done in this field today, the considerations are more technical than economical which is a normal situation for an emerging technology. The success of this new multimedia technology will be given by the applications running with this techniques.

The needed technologies and methodologies were discussed to emphasize the main parameters influencing the design of VLSI chips for Digital TV Applications like parallelization, electrical constraints, power management, scalability and so on...............................