MIVAR 9BN4V CHASSIS TV3013 INTERNAL VIEW.

Power Supply: The examples chosen are taken from manufacturers' circuit diagrams and are usually simplified to emphasise the fundamental nature of the circuit. For each example the particular transistor properties that are exploited to achieve the desired performance are made clear. As a rough and ready classification the circuits are arranged in order of frequency: this part is devoted to circuits used at zero frequency, field frequency and audio frequencies. Series Regulator Circuit Portable television receivers are designed to operate from batteries (usually 12V car batteries) and from the a.c. mains. The receiver usually has an 11V supply line, and circuitry is required to ensure that the supply line is at this voltage whether the power source is a battery or the mains. The supply line also needs to have good regulation, i.e. a low output resistance, to ensure that the voltage remains constant in spite of variations in the mean current taken by some of the stages in the receiver. Fig. 1 shows a typical circuit of the power -supply arrangements. The mains transformer and bridge rectifier are designed to deliver about 16V. The battery can be assumed to give just over 12V. Both feed the regulator circuit Trl, Tr2, Tr3, which gives an 11V output and can be regarded as a three -stage direct -coupled amplifier. The first stage Tr 1 is required to give an output current proportional to the difference between two voltages, one being a constant voltage derived from the voltage reference diode D I (which is biased via R3 from the stabilised supply). The second voltage is obtained from a preset potential divider connected across the output of the unit, and is therefore a sample of the output voltage. In effect therefore Tr 1 compares the output voltage of the unit with a fixed voltage and gives an output current proportional to the difference between them. Clearly a field-effect transistor could do this, but the low input resistance of a bipolar transistor is no disadvantage and it can give a current output many times that of a field-effect transistor and is generally preferred therefore. The output current of the first stage is amplified by the two subsequent stages and then becomes the output current of the unit. Clearly therefore Tr2 and Tr3 should be current amplifiers and they normally take the form of emitter followers or common emitter stages (which have the same current gain). By adjusting the preset control we can alter the fraction of the output voltage' applied to the first stage and can thus set the output voltage of the unit at any desired value within a certain range. By making assumptions about the current gain of the transistors we can calculate the degree of regulation obtainable. For example, suppose the gain of Tr2 and Tr3 in cascade is 1,000, and that the current output demanded from the unit changes by 0.1A (for example due to the disconnection of part of the load). The corresponding change in Tr l's collector current is 0.1mA and, if the standing collector current of Tr 1 is 1mA, then its mutual conductance is approximately 4OmA/V and the base voltage must change by 2.5mV to bring about the required change in collector current. If the preset potential divider feeds one half of the output voltage to Tr l's base, then the change in output voltage must be 5mV. Thus an 0.1A change in output current brings about only 5mV change in output voltage: this represents an output resistance of only 0.0552.


TEA2037A HORIZONTAL ; VERTICAL DEFLECTION CIRCUIT

The TEA2037A is a horizontal and vertical deflection
circuit for monitors and black and white TV
sets.
This device includes all functions required for deflection,
namely :
- Line and frame sync separation
- Line oscillator with phase comparator
- Driver stage for line deflection darlington transistor
- Frame oscillator
- Frame amplifier with flyback generator for direct
drive of the vertical deflection yoke.
The TEA2037A is particularly well-suited for lowcost
monitors since it is cased in a low-cost package
and requires a few number of external
components and hence optimized for small displays.
However, application areas are by no means limited.
Sophisticated applications requiring various
adjustmentpossibilities such as for display geometry
and centering settings (amplitude, linearity,...)
and operating at different line and frame frequencies
(line frequencies up to 64kHz), are readily
configured around TEA2037A.
In large screen applications, addition of a heatsink
mounted on TEA2037A will enable the vertical
deflection yoke current to be boosted to 2A peakto-
peak.
II - FUNCTIONAL DESCRIPTION OF TEA2037A
II.1 - General Description
The TEA2037A is a 16-pin DIP package. The 4
center pins (2 on each side) are connectedtogether
and used as heatsink.
From composite video or TTL-compatible sync.
signals, the device will extract and generate all
signals required for the line scanning darlington
transistor and direct drive of the frame yoke.
The following functional blocks are implemented
on-chip :
- Line and frame sync. separator
- Line oscillator
- Line phase comparator
- Line output stage
- Frame oscillator
- Frame amplifier
- Frame flyback generator
- Shunt regulator
The common device power supply is implemented
by the on-chip shunt regulator.
In order to optimize the drive to frame deflection
yoke and also enableappropriateuse of the flyback
generator, the frame amplifier is powered by an
independentsupply.
The ground is connected to the 4 center pins of the
device.

Sync. Pulse Separator
The TEA2037A extracts, first the line and frame
sync. pulses from the composite video signal and
then the largest pulses, i.e., the frame syncs.

- The sync. detection level is set at 1.6V.
- The value of R2 is typically 1MW (fixed for a good
internal bias).
- Resistor R1 limits the output current of Pin 15.
As illustrated in the Figure 4, it is recommended to
employ a low-pass filter which will suppress highfrequency
harmonics susceptible to produce jitters
on line sync signal in composite video TV applications.

In monitor application, the sync. signal is generally
separated from the video signal.
In this case, the sync. signal is applied to Pin 15
through a single limiting resistor. Similar to the
former case, the sync. is detected when the input
voltage falls below 1.6V level.

- Line Output Stage
The line output stage has been designed for direct
base drive of the horizontal scanning darlington
transistor.
The low level interval on Pin 14, i.e. the power line
transistor blockingperiod, is determined bythe time
when the voltage of the line oscillator capacitor
(Pin 9) is below 4.8V (internally set thresholdlevel).
In a typical application, this interval corresponds to
22ms at 64ms free-running period.

Phase Comparator (PLL)
II.5.1 - Functional Description
The duty of phasecomparator is to synchronize the
horizontal scanning with the line sync pulse and
ensure correct line flyback during the horizontal
blanking phase.

The line flyback signal (i.e. the pulse on the collector
of the line scanning transistor) is compared with
the line sync. signal issued by sync. separator. If
the detected coincidence is incorrect, the comparator
will then generate an appropriate positive or
negative current so as to charge or discharge the
line oscillator capacitor thereby providing for frequency
and phase locking.

Frame Oscillator
Similar to line oscillator, the frame saw-tooth is
generated by charging an external capacitor on
Pin 1 through a resistor connected to VCC1.
The capacitor is discharged via an internal 500W
resistor. The saw-tooth amplitude is set at two
on-chip threshold levels.

The free-running period is approximately given by :
TOSC 9 0.15 RC
Synchronization is achieved by period reduction.
The frame sync. pulse issued by the sync. separator
will modify the current through the resistor
bridge which is used to set the saw-tooth threshold
levels.
The minimum synchronized frame period (MSFP)
is given by :
MSFP 9
TOSC
1.8
II.7 - Frame Output Amplifier
The frame saw-tooth generated by frame oscillator
is first inverted(Gain : - 0.4) and then applied to the
non-inverting input of the frame amplifier. The output
current capability of this amplifier is as high as
± 1Athus enabling to drive vertical deflection yokes
requiring 2A peak-to-peak.
As a function of dissipated power, the device may
require the addition of a heatsink.
Afeed-backloop is connectedto the inverting input
of the frame amplifier (Pin 6).
As the CRT screen is not part of a sphere centered
on the deflectioncenter point, if the yoke is actually
driven by a saw-tooth waveform, the image is
expanded at the top and bottom. The yoke must
therefore be provided with an ”S” waveform current,
by applying linearity correction.

The circuit configuration depicted above does not
require any linearity adjustment - only an amplitude
adjustment potentiometer ”P” has been provided
for.
- D.C. Feedback : The C1 capacitor is charged to
approximately 1/2 x VCC2. Divider bridge formed
by R2 + R4 and R5 networks will set the d.c.
feedback. The component values of this divider
network will be choosen to avoid saturation at top
and bottom of the output voltage (Pin 6 biasing
voltage is approximately 0.6V).
- LinearityCorrection: Aparabolicsignal at frame
frequency is available on ”+” terminal of the C1
capacitor. This signal is integrated by R2, C2
network. An ”S” waveformis thus obtained,which
is applied to Pin 6 via resistor R4.
Any correction to this ”S” waveform depends on
C1 and C2 values. The linearity correction depends
on ratio : R2/R4
- Vertical Amplitude : Frame current amplitude is
determined by the value of measurement resistor
”R1”, potentiometer ”P” settings and the value of
”R5” resistor.
II.8 - Frame Flyback Generator
The output stage of the vertical amplifier includes
a frame flyback generator connected to pin 3.
During the vertical scanning flyback time, the value
of the yoke inductance ”L” must be taken into
account since the time constant L/R is no longer
negligible. In television applications, the frame
blanking time is 1.6ms. Thuswhen L/R > 1.6 x 10-3,
it is necessary to increase the supply voltage to the
frame output amplifier so as to reduce the flyback
time. This surplus is required only for the frame
flyback and energy is wasted by boosting the supply
to the amplifier at all times (during the frame
scanningtime, theminimumvoltage issubstantially
RI, where I is peak-to-peak frame current).

During the second half of the vertical scanning
time, transistor T2 conducts and capacitor C is
charged toVCC throughD1, D2,R3 andT2. (Switch
K open)
On flyback, switch K closes and Pin 3 is connected
to VCC. The voltage at Pin 7 (VCC2), which was
equal to VCC - VD1, is almost doubled during the
flyback time. The only external components required
are therefore D1, D2 and C.
In addition to reducing the flyback time, the flyback
generator reduces the power consumed by the
power stage, and can in certain cases avoid the
need to use a heatsink.

Diode D2 is a low-signal diode (1N4148) but diode
D1 must be appropriately rated since the positive
current in the first part of the saw-tooth is supplied
to the yoke through D1 and T1. A 1N4001 is generally
used.

The shunt regulator
The TEA2037A incorporates an internal shunt
regulator which delivers the common supply voltage
VCC to various blocks such as oscillators,
comparator, sync separator and so on.
The voltage onPin 16 is 9.7V(9V min, 10.5V max).
The value of the series resistor R must be so
calculated to obtain a 15mAcurrent on Pin 16 - this
current can be 10mAmin. and 20mAmax.

The external current supply from VCC1 to both
oscillators (i.e. line and frame) can be neglected in
majority of cases.
The resistor value is found to be 1.2kW at
VCC = +28V.
At VCC =+ 12V, and taking into account the voltage
tolerance on Pin 16, a 150W series resistor must
be used.
II.10 - Thermal Considerations
In order to ensure reliable device operation, the
dissipatedpowershould be accurately determined.
Calculation will allow an evaluation of the dissipated
power and should be completed by package
temperature measurements in actual applications.
According to results obtained, a heatsink may or
may not be required.
• Power drawn from VCC1 supply :
P1 = VCC1 . I1
Where I1 is the current through the shunt
regulator (Pin 16).
• Power drawn from VCC2 supply :
P2 = VCC2
TYU
IPP
8 + I2
NM<

Where :
- Ipp = peak-to-peak current through the vertical
deflection yoke.
- I2 = Pin 7 quiescent current.
- VCC2 = Pin 7 voltage.


CHARACTERISTICS
- Screen : 9” Monochrome
- Frame deflection yoke : 72mH, 40W,
220mApeak-to-peak
- VCC = + 25V without flyback generator
- Frame flyback time : 1.2ms
- Vertical frequency : 50Hz (20ms)
- Vertical free-running period : 24.5ms
- Horizontal frequency : 15 625Hz
- Capture range : ±5ms
- Holding range : ±10ms
- Input signal : composite video
- Dissipated power : 1.15W
- Only one adjustment : vertical amplitude
This is a low-cost applicationused in French Minitel
type configurations and requiresminimum number
of additional components and adjustments. The
input is a composite video signal at line frequency
= 15 625Hz and frame frequency of 50Hz.
The free-running horizontal frequency is determined
by the component values of RCnetwork on
Pin 9. Since no adjustment is available, precision
components must be used to ensure correct synchronization
:
[R = 35.7kW, 1% and C = 2.2nF,
2% for fH = 15 625Hz]
The capture range is large enough to compensate
for possible variations.
- Synchronizationrange of the vertical oscillator is
quite large which consequentlyallows use of less
accurate components :
[R = 910 kW, 5 % and C = 180 nF, 5 %]
- Since the frame flyback time is short enough at
supply voltage used here, the flyback generator
is not used in this application.