PANASONIC TX-28A2CI CHASSIS ALPHA-3 VIEW

The PANASONIC CHASSIS ALPHA-3 is a sophisticated and complex Television chassis which offers high quality features and it's an expression of Japan electronics engineering and design.

It has lot of features inclusive PSI Picture Signal Improvement and CTI Color transient improvement, all developed in Analog signal processing technology.

Here you have an example of high quality materials all the way and basically no compromise in employing parts and components.

Try to find a today apparatus like this.


Picture-quality improving circuit:

n a picture-quality improving circuit, a luminance transition is detected on the basis of a luminance signal. Chroma edge characteristics of a color signal are enhanced in accordance with the detected luminance transition. A detection is made as to whether the color signal and the luminance signal are correlated or uncorrelated in transition. When the color signal and the luminance signal are uncorrelated in transition, the enhancement of the chroma edge characteristics of the color signal is interrupted.

1. A picture-quality improving circuit comprising:

means for generating a chroma edge signal on the basis of a color signal, the chroma edge signal representing a chroma edge;

means for generating a luminance edge signal on the basis of a luminance signal, the luminance edge signal representing a luminance edge;

means for detecting a chroma edge signal;

means for differentiating an output signal from the detecting means;

means for amplifying an output signal from the differentiating means;

first adding means for adding an output signal from the amplifying means and the luminance edge signal;

means for multiplying a chroma edge signal and an output signal from the first adding means; and

second adding means for adding an output signal from the multiplying means to the color signal to yield an enhanced color signal.

2. A picture-quality improving circuit of claim 1 wherein the chroma-edge-signal generating means comprises first and second subtracters, and a cascade combination of first, second, and third equalizers; the color signal is fed to an input terminal of the first equalizer and a first input terminal of the first subtracter; an output signal from the first equalizer is fed to an input terminal of the second equalizer and a first input terminal of the second subtracter; an output signal from the second equalizer is fed to a second input terminal of the first subtracter, an input terminal of the third equalizer, and the adding means; an output signal from the third equalizer is fed to a second input terminal of the second subtracter; an output signal from the first subtracter is fed to the detecting means; and an output signal from the second subtracter is fed to the multiplying means.

Description:

BACKGROUND OF THE INVENTION

1. Field of the Invention

This invention relates to a picture-quality improving circuit usable in various systems such as television systems or video systems.

2. Description of the Prior Art

There is a recognized need to sharpen the images of television signals, particularly at transition edges where the picture changes brightness or color, or both brightness and color. In television signal formats such as NTSC and PAL, the color information is encoded on a subcarrier which is interleaved with the baseband luminance information. An inherent drawback of these formats is the limited bandwidth for the color information component, called "chroma" or "chrominance".

There are many chances in a color television system for the chroma information to become degraded, particularly at transitions from one hue to another.

U.S. Pat. No. 4,504,853 discloses a color demodulation of the chroma subcarrier. The system of U.S. Pat. No. 4,504,853 includes an input, a delay match for delaying a modulated subcarrier signal by a predetermined amount, a one-half period delay for delaying the modulated subcarrier signal by half the period thereof, and a first adder for combining in equal amounts the undelayed modulated subcarrier with the signal delayed by the one-half period delay to provide a transition envelope. A control generator receives the luminance signal and derives a control signal from transitions occurring in the luminance. A multiplier multiplies the transition envelope signal by the control signal to provide an enhancement product. A second adder combines the delay matched modulated subcarrier in phase with the enhancement product to put out the enhanced modulated subcarrier characterized by shortened transitions in alignment with simultaneous transitions in the baseband.

Since the system of U.S. Pat. No. 4,504,853 uses a correlation between the color signal and the luminance signal in improving the transition characteristics of the color signal, the intended effect is realized when the color signal actually correlates to the luminance signal. In the system of U.S. Pat. No. 4,504,853, when the luminance signal and the color signal are uncorrelated and the color signal changes at a point near a change of the luminance signal, the edge information of the color signal is easily modulated with the edge information of the luminance signal so that the color signal tends to be contaminated by false edge information.

SUMMARY OF THE INVENTION

It is an object of this invention to provide an excellent picture-quality improving circuit.

In a picture-quality improving circuit of this invention, a luminance transition is detected on the basis of a luminance signal. Chroma edge characteristics of a color signal are enhanced in accordance with the detected luminance transition. A detection is made as to whether the color signal and the luminance signal are correlated or uncorrelated in transition. When the color signal and the luminance signal are uncorrelated in transition, the enhancement of the chroma edge characteristics of the color signal is interrupted. The disclosure of application Ser. No. 07/344,874, Filed on Apr. 28, 1989 in its entirety is incorporated herein by reference.

TDA4670 Picture Signal Improvement (PSI)

FEATURES
· Luminance signal delay from 20 to 1100 ns (minimum
step 45 ns)
· Luminance signal peaking with selectable symmetrical
overshoots
· 2.6 or 5 MHz peaking centre frequency and selectable
degree of peaking (-3, 0, +3 and +6 dB)
· Selectable noise reduction by coring
· Handles negative and positive colour-difference signals
· Selectable Colour Transient Improvement (CTI) to
decrease the colour-difference signal transient times to
those of the high frequency luminance signals
· Selectable 5 or 12 V sandcastle input voltage
· All controls selected via the I2C-bus
· Timing pulse generation for clamping and delay time
control synchronized by sandcastle pulse
· Automatic luminance signal delay correction using a
control loop
· Luminance and colour-difference input signal clamping
with coupling capacitor
· 4.5 to 8.8 V supply voltage range
· Minimum of external components required.

GENERAL DESCRIPTION
The TDA4670 delays the luminance signal and improves
colour-difference signal transients. Additionally, the
luminance signal can be improved by peaking and noise
reduction (coring).

FUNCTIONAL DESCRIPTION
The TDA4670 contains luminance signal processing and
colour-difference signal processing. The luminance signal
section comprises a variable integrated luminance delay
line with luminance signal peaking and noise reduction by
coring.
The colour-difference section consists of a transient
improvement circuit to decrease the rise and fall times of
the colour-difference signal transients. All functions and
parameters are controlled via the I2C-bus.
Y-signal path
The video and blanking signal is AC-coupled to the input
at pin 16. Its black porch is clamped to a DC reference
voltage to ensure the correct operating range of the
luminance delay stage.
The luminance delay line consists of all-pass filter sections
with delay times of 45, 90, 100, 180 and 450 ns
(see Fig.1). The luminance signal delay is controlled via
the I2C-bus in steps of 45 ns in the range of 20 to 1100 ns,
this ensures that the maximum delay difference between
the luminance and colour-difference signals is ±22.5 ns.
An automatic luminance delay time adjustment in an
internal control loop (with the horizontal frequency as a
reference) is used to correct changes in the delay time,
due to component tolerances. The control loop is
automatically enabled between the burst key pulses of
lines 16 (330) and 17 (331) during the vertical blanking
interval. The control voltage is stored in the capacitor CDL
connected to pin 2.
The peaking section uses a transversal filter circuit with
selectable centre frequencies of 2.6 and 5 MHz.
It provides selectable degrees of peaking of -3, 0, +3
and +6 dB and a noise reduction by coring, which
attenuates the high-frequency noise introduced by
peaking.
The output buffer stage ensures a low-ohmic VBS output
signal on pin 12 (<160 W). The gain of the luminance
signal path from pin 16 to pin 12 is unity.
An oscillation signal of the delay time control loop is
present on output pin 12 instead of the VBS signal during
the vertical blanking interval in lines 16 (330) to 18 (332).
Therefore, this output signal should not be applied for
synchronization.
Colour-difference signal paths
The colour-difference input signals (on pins 3 and 7) are
clamped to a reference voltage.
Each colour-difference signal is fed to a transient detector
and to an analog signal switch with an attached voltage
storage stage.
The transient detectors consist of differentiators and
full-wave rectifiers. The output voltages of both transient
detectors are added and then compared in a comparator.
This comparator controls both following analog signal
switches simultaneously.
The analog signal switches are in an open position at a
certain value of transient time; the held value (held by
storage capacitors) is then applied to the outputs.
The switches close to rapidly accept the actual signal
levels at the end of these transients. The improved
transient time is approximately 100 ns long and
independent of the input signal transient time.
Colour-difference paths are independent of the input
signal polarity and have a gain of unity.
The CTI functions are switched on and off via the I2C-bus.


TDA4650 Multistandard colour decoder, with negative colour difference output signals

FEATURES
Identifies and demodulates PAL,
SECAM, NTSC 3.58 and NTSC 4.43
chrominance signals with:
· Identification
– automatic standard identification
by sequential inquiry
– secure SECAM identification at
50 Hz only, with PAL priority
– four switched outputs for
chrominance filter selection and
display control
– external service switch for
oscillator adjustment
· PAL / NTSC demodulation
– H (burst) and V blanking
– PAL switch (disabled for NTSC)
– NTSC phase shift (disabled for
PAL)
– PLL-controlled reference
oscillator
– two reference oscillator crystals
on separate pins with automatic
switching
– quadrature demodulator with
subcarrier reference
· SECAM demodulation
– limiter-amplifier
– quadrature-demodulator with a
single external reference tuned
circuit
– alternate line blanking, H and V
blanking
– de-emphasis
· Gain controlled chrominance
amplifier
· ACC demodulation controlled by
system scanning
· Internal colour-difference signal
output filters to remove the residual
subcarrier.

GENERAL DESCRIPTION
The TDA4650 is a monolitic
integrated multistandard colour
decoder for PAL, SECAM and NTSC
(3.58 and 4.43 MHz) with negative
colour difference output signals. The
colour-difference output signals are
fed to the TDA4660/TDA4661,
Switched capacitor delay line.

TDA2579B Horizontal/vertical synchronization circuit:

GENERAL DESCRIPTION
The TDA2579B generates and synchronizes horizontal and vertical signals. The device has a 3 level sandcastle output;
a transmitter identification signal and also 50/60 Hz identification.
Features
· Horizontal phase detector, (sync to oscillator), sync separator and noise inverter
· Triple current source in the phase detector with automatic selection
· Second phase detector for storage compensation of the horizontal output
· Stabilized direct starting of the horizontal oscillator and output stage from mains supply
· Horizontal output pulse with constant duty cycle value of 29 ms
· Internal vertical sync separator, and two integration selection times
· Divider system with three different reset enable windows
· Synchronization is set to 628 divider ratio when no vertical sync pulses and no video transmitter is identified
· Vertical comparator with a low DC feedback signal
· 50/60 Hz identification output combined with mute function
· Automatic amplitude adjustment for 50 and 60 Hz and blanking pulse duration
· Automatic adaption of the burst-key pulsewidth.

FUNCTIONAL DESCRIPTION
Vertical part (pins 1,2,3,4)
The IC embodies a synchronized divider system for generating the vertical sawtooth at pin 3. The divider system has an
internal frequency doubling circuit, so the horizontal oscillator is working at its normal line frequency and one line period
equals 2 clock pulses. Due to the divider system no vertical frequency adjustment is needed. The divider has a
discriminator window for automatically switching over from the 60 Hz to 50 Hz system. The divider system operates with
3 different divider reset windows for maximum interference/disturbance protection.
The windows are activated via an up/down counter. The counter increases its counter value by 1 for each time the
separated vertical sync pulse is within the searched window. The count is decreased by 1 when the vertical sync pulse
is not present.
Large (search) window: divider ratio between 488 and 722
This mode is valid for the following conditions:
1. Divider is looking for a new transmitter.
2. Divider ratio found, not within the narrow window limits.
3. Up/down counter value of the divider system operating in the narrow window mode decreases below count 1.
4. Externally setting. This can be reached by loading pin 18 with a resistor of 220 kW to earth or connecting a 3.6 V
diode stabistor between pin 18 and ground.
Narrow window: divider ratio between 522-528 (60 Hz) or 622-628 (50 Hz).
The divider system switches over to this mode when the up/down counter has reached its maximum value of 12 approved
vertical sync pulses. When the divider operates in this mode and a vertical sync pulse is missing within the window the
divider is reset at the end of the window and the counter value is decreased by 1. At a counter value below count 1 the
divider system switches over to the large window mode.
Standard TV-norm
When the up/down counter has reached its maximum value of 12 in the narrow window mode, the information applied to
the up/down counter is changed such that the standard divider ratio value is tested. When the counter has reached a
value of 14 the divider system is changed over to the standard divider ratio mode. In this mode the divider is always reset
at the standard value even if the vertical sync pulse is missing. A missed vertical sync pulse decreases the counter value
by 1. When the counter reaches the value of 10 the divider system is switched over to the large window mode.
The standard TV-norm condition gives maximum protection for video recorders playing tapes with anti-copy guards.
No-TV-transmitter found: (pin 18 < 1.2 V)
In this condition, only noise is present, the divider is rest to count 628. In this way a stable picture display at normal height
is achieved.
Video tape recorders in feature mode
It should be noted that some VTRs operating in the feature modes, such as picture search, generate such distorted
pictures that the no-TV-transmitter detection circuit can be activated as pin V18 drops below 1.2 V. This would imply a
rolling picture (see Phase detector, sub paragraph d). In general VTR-machines use a re-inserted vertical sync pulse in
the feature mode. Therefore the divider system has been made such that the automatic reset of the divider at count 628
when V18 is below 1.2 V is inhibited when a vertical sync pulse is detected.
The divider system also generates the anti-top-flutter pulse which inhibits the Phase 1 detector during the vertical sync.
pulse. The width of this pulse depends on the divider mode. For the divider mode a the start is generated at the reset of
the divider. In mode b and c the anti-top-flutter pulse starts at the beginning of the first equalizing pulse.

The anti-top-flutter pulse ends at count 8 for 50 Hz and count 10 for 60 Hz. The vertical blanking pulse is also generated
via the divider system. The start is at the reset of the divider while the pulse ends at count 34 (17 lines) for 60 Hz, and at
count 44 (22 lines) for 50 Hz systems. The vertical blanking pulse generated at the sandcastle output pin 17 is made by
adding the anti-top-flutter pulse and the blanking pulse. In this way the vertical blanking pulse starts at the beginning of
the first equalizing pulse when the divider operates in the b or c mode. For generating a vertical linear sawtooth voltage
a capacitor should be connected to pin 3. The recommended value is 150 nF to 330 nF (see Fig.1).
The capacitor is charged via an internal current source starting at the reset of the divider system. The voltage on the
capacitor is monitored by a comparator which is activated also at reset. When the capacitor has reached a voltage value
of 5.85 V for the 50 Hz system or 4.85 V for the 60 Hz system the voltage is kept constant until the charging period ends.
The charge period width is 26 clock pulses. At clock pulse 26 the comparator is switched off and the capacitor is
discharged by an npn transistor current source, the value of which can be set by an external resistor between pin 4 and
ground (pin 9). Pin 4 is connected to a pnp transistor current source which determines the current of the npn current
source at pin 3. The pnp current source on pin 4 is connected to an internal zener diode reference voltage which has a
typical voltage of » 7.5 volts. The recommended operating current range is 10 to 75 mA. The resistance at pin R4 should
be 100 to 770 kW. By using a double current mirror concept the vertical sawtooth pre-correction can be set on the desired
value by means of external components between pin 4 and pin 3, or by connecting the pin 4 resistor to the vertical current
measuring resistor of the vertical output stage. The vertical amplitude is set by the current of pin 4. The vertical feedback
voltage of the output stage has to be applied to pin 2. For the normal amplitude adjustment the values are DC = 1 V and
AC = 0.8 V. Due to the automatic system adaption both values are valid for 50 Hz and 60 Hz.
The low DC voltage value improves the picture bounce behaviour as less parabola compensation is necessary. Even a
fully DC coupled feedback circuit is possible.
Vertical guard
The IC also contains a vertical guard circuit. This circuit monitors the vertical feedback signal on pin 2. When the level
on pin 2 is below 0.35 V or higher than 1.85 V the guard circuit inserts a continuous level of 2.5 V in the sandcastle output
signal of pin 17. This results in the blanking of the picture displayed, thus preventing a burnt-in horizontal line. The guard
levels specified refer to the zener diode reference voltage source level.
Driver output
The driver output is at pin 1, it can deliver a drive current of 1.5 mA at 5 V output. The internal impedance is approximately
170 W. The output pin is also connected to an internal current source with a sink current of 0.25 mA.
Sync separator, phase detector and TV-station identification (pins 5,6,7,8 and 18)
The video input signal is connected to pin 5. The sync separator is designed such that the slicing level is independent of
the amplitude of the sync pulse. The black level is measured and stored in the capacitor at pin 7. The slicing level value
is stored in the capacitor at pin 6. The slicing level value can be chosen by the value of the external resistor between
pins 6 and 7. The value is given by the formula:
Where Rs is the resistor between pins 6 and 7 and top sync level equals 100%. The recommended resistor value is 5.6 kW.

Black level detector
A gating signal is used for the black level detector. This signal is composed of an internal horizontal reference pulse with
a duty factor of 50% and the flyback pulse at pin 12. In this way the TV-transmitter identification operates also for all DC
conditions at input pin 5 (no video modulation, plain carrier only).
During the frame interval the slicing level detector is inhibited by a signal which starts with the anti-top flutter pulse and
ends with the reset vertical divider circuit. In this way shift of the slicing level due to the vertical sync signal is reduced
and separation of the vertical sync pulse is improved.
Noise level detector
An internal noise inverter is activated when the video level at pin 5 decreases below 0.7 V. The IC also embodies a
built-in sync pulse noise level detection circuit. This circuit is directly connected to pin 5 and measures the noise level at
the middle of the horizontal sync pulse. When a signal-to-noise level of 19 dB is detected a counter circuit is activated.
A video input signal is processed as “acceptable noise free” when 12 out of 15 sync pulses have a noise level below
19 dB for two successive frame periods. The sync pulses are processed during a 15 line width gating period generated
by the divider system. The measuring circuit has a built-in noise level hysteresis of approximately 3 dB. When the
“acceptable noise free” condition is found the phase detector of pin 8 is switched to not gated and normal time constant.
When a higher sync pulse noise level is found the phase detector is switched over to slow time constant and gated sync
pulse phase detection. At the same time the integration time of the vertical sync pulse separator is adapted.
Phase detector
The phase detector circuit is connected to pin 8. This circuit consists of 3 separate phase detectors which are activated
depending on the voltage of pin 18 and the state of the sync pulse noise detection circuit. For normal and fast time
constants all three phase detectors are activated during the vertical blanking period, this with the exception of the
anti-top-flutter pulse period, and the separated vertical sync-pulse time. As a result, phase jumps in the video signal
related to the video head, take over of video recorders are quickly restored within the vertical blanking period. At the end
of the blanking period the phase director time constant is increased by 1.5 times. In this way there is no requirement for
external VTR time constant switching, and so all station numbers are suitable for signals from VTR, video games or home
computers.
For quick locking of a new TV station starting from a noise only signal condition (normal time constant) a special circuit
is incorporated. A new TV station which is not locked to the horizontal oscillator will result in a voltage decrease below
0.1 V at pin 18. This will activate a frame period counter which switches the phase detector to fast for 3 frame periods
during the vertical scan period.
The horizontal oscillator will now lock to the new TV-station and as a result, the voltage on pin 18 will increase to
approximately 6.5 V. When pin 18 reaches a level of 1.8 V the mute output transistor of pin 13 is switched OFF and the
divider is set to the large window. In general the mute signal is switched OFF within 5 ms (pin C18 = 47 nF) after reception
of a new TV-signal. When the voltage on pin 18 reaches a level of 5 V, usually within 15 ms, the frame counter is switched
OFF and the time constant is switched from fast to normal during the vertical scan period.

If the new TV station is weak, the sync-noise detector is activated. This will result in a change over of pin 18 voltage from
6.5 V to »10 V. When pin 18 exceeds the level of 7.8 V the phase detector is switched to slow time constant and gated
sync pulse condition. The current is also reduced during the vertical blanking period by 1 mA. When desired, most
conditions of the phase detector can also be set by external means in the following way:
a. Fast time constant TV transmitter identification circuit not active, connect pin 18 to earth (pin 9).
b. Fast time constant TV transmitter identification circuit active, connect a resistor of 220 kW between pin 18 and ground.
This condition can also be set by using a 3.6 V stabistor diode instead of a resistor.
c. Slow time constant, (with exception of frame blanking period), connect pin 18 via a resistor of 10 kW to + 12 V, pin 10.
In this condition the transmitter identification circuit is not active.
d. No switching to slow time constant desired (transmitter identification circuit active), connect a 6.8 V zener diode
between pin 18 and ground.

Supply (pins 9, 10 and 16)
The IC has been designed such that the horizontal oscillator and output stage can start operating by application of a very
low supply current into pin 16.
The horizontal oscillator starts at a supply current of approximately 4 mA. The horizontal output stage is forced into the
non-conducting stage until the supply current has a typical value of 5 mA. The circuit has been designed so that after
starting the horizontal output function a current drop of » 1 mA is allowed. The starting circuit has the ability to derive the
main supply (pin 10) from the horizontal output stage. The horizontal output signal can also be used as the oscillator
signal for synchronized switched mode power supplies. The maximum allowed starting current is 9.7 mA (Tamb = 25 °C).
The main supply should be connected to pin 10, and pin 9 should be used as ground. When the voltage on pin 10
increases from zero to its final value (typically 12 V) a part of the supply current of the starting circuit is taken from pin 10
via internal diodes, and the voltage on pin 16 will stabilize to a typical value of 9.4 V.
In a stabilized condition (pin V10 > 10 V) the minimum required supply current to pin 16 is » 2.5 mA. All other IC functions
are switched on via the main supply voltage on pin 10. When the voltage on pin 10 reaches a value of » 7 V the horizontal
phase detector circuit is activated and the vertical ramp on pin 3 is started. The second phase detector circuit and burst
pulse circuit are started when the voltage on pin 10 reaches the stabilized voltage value of pin 16 which is typically 9.4 V.
To close the second phase detector loop, a flyback pulse must be applied to pin 12. When no flyback pulse is detected
the duty factor of the horizontal output stage is 50%.
For remote switch-off pin 16 can be connected to ground (via a npn transistor with a series resistor of » 500 W) which
switches off the horizontal output.
Horizontal oscillator, horizontal output transistor, and second phase detector (pins 11, 12, 14 and 15)
The horizontal oscillator is connected to pin 15. The frequency is set by an external RC combination between pin 15 and
ground, pin 9. The open collector horizontal output stage is connected to pin 11. An internal zener diode configuration
limits the open voltage of pin 11 to » 14.5 V.
The horizontal output transistor at pin 11 is blocked until the current into pin 16 reaches a value of » 5 mA.
A higher current results in a horizontal output signal at pin 11, which starts with a duty factor of » 40% HIGH.
The duty factor is set by an internal current-source-loaded npn emitter follower stage connected to pin 14 during starting.
When pin 16 changes over to voltage stabilization the npn emitter follower and current source load at pin 14 are switched
OFF and the second phase detector circuit is activated, provided a horizontal flyback pulse is present at pin 12.
When no flyback pulse is detected at pin 12 the duty factor of the horizontal output stage is set to 50%.
The phase detector circuit at pin 14 compensates for storage time in the horizontal deflection output stage. The horizontal
output pulse duration is 29 ms HIGH for storage times between 1 ms and 17 ms (flyback pulse of 12 ms). A higher storage
time increases the HIGH time. Horizontal picture shift is possible by forcing an external charge or discharge current into
the capacitor at pin 14.

Mute output and 50/60 Hz identification (pin 13)
The collector of an npn transistor is connected to pin 13. When the voltage on pin 18 drops below 1.2 V
(no TV-transmitter) the npn transistor is switched ON.
When the voltage on pin 18 increases to a level of » 1.8 V (new TV-transmitter found) the npn transistor is switched OFF.
Pin 13 has also the possibility for 50/60 Hz identification. This function is available when pin 13 is connected to pin 10
(+ 12 V) via an external pull-up resistor of 10 to 20 kW. When no TV-transmitter is identified the voltage on pin 13 will be
LOW (< 0.5 V). When a TV-transmitter with a divider ratio > 576 (50 Hz) is detected the output voltage of pin 13 is HIGH
(+ 12 V).
When a TV-transmitter with a divider ratio < 576 (60 Hz) is found an internal pnp transistor with its emitter connected to
pin 13 will force this pin output voltage down to » 7.6 V.
Sandcastle output (pin 17)
The sandcastle output pulse generated at pin 17, has three different voltage levels. The highest level, (10.4 V), can be
used for burst gating and black level clamping. The second level (4.5 V) is obtained from the horizontal flyback pulse at
pin 12, and is used for horizontal blanking. The third level (2.5 V) is used for vertical blanking and is derived via the
vertical divider system. For 50 Hz the blanking pulse duration is 44 clock pulses and for 60 Hz it is 34 clock pulses started
from the vertical divider reset. For TV-signals which have a divider ratio between 622 and 628 or between 522 and 528
the pulse is started at the first equalizing pulse. With the 50/60 Hz information the burst-key pulse width is switched to
improve the behaviour in multi-norm concepts.



TDA3505 Video control combination circuit with automatic cut-off control


GENERAL DESCRIPTION
The TDA3505 and TDA3506 are monolithic integrated circuits which perform video control functions in a PAL/SECAM
decoder. The TDA3505 is for negative colour difference signals -(R-Y), -(B-Y) and the TDA3506 is for positive colour
difference signals +(R-Y), +(B-Y).
The required input signals are: luminance and colour difference (negative or positive) and a 3-level sandcastle pulse for
control purposes. Linear RGB signals can be inserted from an external source. RGB output signals are available for
driving the video output stages. The circuits provide automatic cut-off control of the picture tube.
Features
· Capacitive coupling of the colour difference and
luminance input signals with black level clamping in the
input stages
· Linear saturation control acting on the colour difference
signals
· (G-Y) and RGB matrix
· Linear transmission of inserted signals
· Equal black levels for inserted and matrixed signals
· 3 identical channels for the RGB signals
· Linear contrast and brightness controls, operating on
both the inserted and matrixed RGB signals
· Peak beam current limiting input
· Clamping, horizontal and vertical blanking of the three
input signals controlled by a 3-level sandcastle pulse
· 3 DC gain controls for the RGB output signals (white
point adjustment)
· Emitter-follower outputs for driving the RGB output
stages
· Input for automatic cut-off control with compensation for
leakage current of the picture tube

Notes
1. < 110 mA after warm-up.
2. Values are proportional to the supply voltage.
3. When V11-24 < 0,4 V during clamping time - the black levels of the inserted RGB signals are clamped on the black
levels of the internal RGB signals.
When V11-24 > 0,9 V during clamping time - the black levels of the inserted RGB signals are clamped on an internal
DC voltage (correct clamping of the external RGB signals is possible only when they are synchronous with the
sandcastle pulse).
4. When pins 21, 22 and 23 are not connected, an internal bias voltage of 5,5 V is supplied.
5. Automatic cut-off control measurement occurs in the following lines after start of the vertical blanking pulse:
line 20: measurement of leakage current (R + G + B)
line 21: measurement of red cut-off current
line 22: measurement of green cut-off current
line 23: measurement of blue cut-off current
6. Black level of the measured channel is nominal; the other two channels are blanked to ultra-black.
7. All three channels blanked to ultra-black.
The cut-off control cycle occurs when the vertical blanking part of the sandcastle pulse contains more than 3 line
pulses.
The internal blanking continues until the end of the last measured line.
The vertical blanking pulse is not allowed to contain more than 34 line pulses, otherwise another control cycle begins.
8. The sandcastle pulse is compared with three internal thresholds (proportional to VP) and the given levels separate
the various pulses.
9. Blanked to ultra-black (-25%).
10. Pulse duration ³ 3,5 ms.