PHILIPS 28SL5800/00B CHASSIS FL 1.0 VIEW.

PHILIPS CHASSIS FL 1.0

This is a two pages chassis development.

Left side signal processing part:

NICAM: TDA8417

VIDEO RGB MATRIX: TDA4680

CTI: TDA4565

LUM + CHROMA: TDA4650

TELETEXT UNIT

COMB FILTER

Right side POWER PARTS:

Line deflection output + EHT

E/W Correction

Frame Output deflection:TDA3654Q

Synchronization:TDA2579B + TDA2595

Audio power amplifier stereo + Sub Woofer amplifier.



POWER SUPPLY

ST-BY Power supply.




TDA4680 Video processor with automatic cut-off and white level control
GENERAL DESCRIPTION
The TDA4680 is a monolithic integrated circuit with a
colour difference interface for video processing in TV
receivers. Its primary function is to process the luminance
and colour difference signals from multistandard colour
decoders, TDA4555, TDA4650/T, TDA4655/T or
TDA4657, Colour Transient Improvement (CTI) IC,
TDA4565, Picture Signal Improvement (PSI) IC,
TDA4670, or from a feature module.
The required input signals are:
· Luminance and negative colour difference signals
· 2 or 3-level sandcastle pulse for internal timing pulse
generation
· I2C-bus data and clock signals for microcontroller
control.
Two sets of analog RGB colour signals can also be
inserted, e.g. one from a peritelevision connector and the
other from an on-screen display generator; both inputs are
fully-controlled internally. The TDA4680 includes full
I2C-bus control of all parameters and functions with
automatic cut-off and white level control of the picture tube
cathode currents. It provides RGB output signals for the
video output stages.
There is a very similar IC TDA4681 available. The only
differences are in the NTSC matrix.

I2C-BUS
Control
The I2C-bus transmitter/receiver provides the data bytes to
select and adjust the following functions and parameters:
· Brightness adjust
· Saturation adjust
· Contrast adjust
· Hue control voltage
· RGB gain adjust
· RGB reference voltage levels
· Peak drive limiting
· Selection of the vertical blanking interval and
measurement lines for cut-off and white level control
according to transmission standard
· Selects either 3-level or 2-level (5 V) sandcastle pulse
· Enables/disables input clamping pulse delay
· Enables/disables white level control
· Enables cut-off control; enables output clamping
· Enables/disables full screen white level
· Enables/disables full screen black level
· Selects either PAL/SECAM or NTSC matrix
· Enables saturation adjust; enables nominal saturation
· Enables/disables synchronization of the execution of
I2C-bus commands with the vertical blanking interval
· Reads the result of the comparison of the nominal and
actual RGB signal levels for automatic white level
control.
I2C-bustransmitter/receiver and data transfer
I2C-BUS SPECIFICATION
The I2C-bus is a bidirectional, two-wire, serial data bus for
intercommunication between ICs in a system.
The microcontroller transmits/receives data from the
I2C-bus transceiver in the TDA4680 over the serial data
line SDA (pin 27) synchronized by the serial clock line SCL
(pin 28). Both lines are normally connected to a positive
voltage supply through pull-up resistors. Data is
transferred when the SCL line is LOW. When SCL is HIGH
the serial data line SDA must be stable. A HIGH-to-LOW
transition of the SDA line when SCL is HIGH is defined as
a START bit. A LOW-to-HIGH transition of the SDA line
when SCL is HIGH is defined as a STOP bit.
Each transmission must start with a START bit and end
with a STOP bit. The bus is busy after a START bit and is
only free again after a STOP bit has been transmitted.

FEATURES
· Operates from an 8 V DC supply
· Black level clamping of the colour difference, luminance
and RGB input signals with coupling-capacitor DC level
storage
· Two fully-controlled, analog RGB inputs, selected either
by fast switch signals or via I2C-bus
· Saturation, contrast and brightness adjustment via
I2C-bus
· Same RGB output black levels for Y/CD and RGB input
signals
· Timing pulse generation from either a 2 or 3-level
sandcastle pulse for clamping, horizontal and vertical
synchronization, cut-off and white level timing pulses
· Automatic cut-off control with picture tube leakage
current compensation
· Software-based automatic white level control or fixed
white levels via I2C-bus
· Cut-off and white level measurement pulses in the last
4 lines of the vertical blanking interval (I2C-bus selection
for PAL, SECAM, or NTSC, PAL-M)
· Increased RGB signal bandwidths for progressive scan
and 100 Hz operation (selected via I2C-bus)
· Two switch-on delays to prevent discolouration before
steady-state operation
· Average beam current and peak drive limiting
· PAL/SECAM or NTSC matrix selection via I2C-bus
· Three adjustable reference voltage levels (via I2C-bus)
for automatic cut-off and white level control
· Emitter-follower RGB output stages to drive the video
output stages
· Hue control output for the TDA4555, TDA4650/T,
TDA4655/T or TDA4657.


TDA4565 Colour transient improvement circuit
DESCRIPTION
The TDA4565 is a monolithic integrated circuit for colour transient improvement (CTI) and luminance delay line in gyrator
technique in colour television receivers.
Features
· Colour transient improvement for colour difference signals (R-Y) and (B-Y) with transient detecting-, storage- and
switching stages resulting in high transients of colour difference output signals
· A luminance signal path (Y) which substitutes the conventional Y-delay coil with an integrated Y-delay line
· Switchable delay time from 730 ns to 1000 ns in steps of 90 ns and additional fine adjustment of 50 ns
· Two Y output signals; one of 180 ns less delay.

TDA3654; TDA3654Q Vertical deflection and guard circuit (110°).

GENERAL DESCRIPTION
The TDA3654 is a full performance vertical deflection output circuit for direct drive of the deflection coils and can be used
for a wide range of 90° and 110° deflection systems.
A guard circuit is provided which blanks the picture tube screen in the absence of deflection current.
Features
· Direct drive to the deflection coils
· 90° and 110° deflection system
· Internal blanking guard circuit
· Internal voltage stabilizer.

FUNCTIONAL DESCRIPTION
Output stage and protection circuits
The output stage consists of two Darlington configurations in class B arrangement.
Each output transistor can deliver 1,5 A maximum and the VCEO is 60 V.
Protection of the output stage is such that the operation of the transistors remains well within the SOAR area in all
circumstances at the output pin, (pin 5). This is obtained by the cooperation of the thermal protection circuit, the
current-voltage detector and the short circuit protection.
Special measures in the internal circuit layout give the output transistors extra solidity, this is illustrated in Fig.5 where
typical SOAR curves of the lower output transistor are given. The same curves also apply for the upper output device.
The supply for the output stage is fed to pin 6 and the output stage ground is connected to pin 4.
Driver and switching circuit
Pin 1 is the input for the driver of the output stage. The signal at pin 1 is also applied to pin 3 which is the input of a
switching circuit (pin 1 and 3 are connected via external resistors).
This switching circuit rapidly turns off the lower output stage when the flyback starts and it, therefore, allows a quick start
of the flyback generator. The maximum required input signal for the maximum output current peak-to-peak value of 3 A
is only 3 V, the sum of the currents in pins 1 and 3 is then maximum 1 mA.
Flyback generator
During scan, the capacitor between pins 6 and 8 is charged to a level which is dependent on the value of the resistor at
pin 8 (see Fig.1).
When the flyback starts and the voltage at the output pin (pin 5) exceeds the supply voltage, the flyback generator is
activated.
The supply voltage is then connected in series, via pin 8, with the voltage across the capacitor during the flyback period.
This implies that during scan the supply voltage can be reduced to the required scan voltage plus saturation voltage of
the output transistors.
The amplitude of the flyback voltage can be chosen by changing the value of the external resistor at pin 8.
It should be noted that the application is chosen such that the lowest voltage at pin 8 is > 1,5 V, during normal operation.
Guard circuit
When there is no deflection current, for any reason, the voltage at pin 8 becomes less than 1 V, the guard circuit will
produce a d.c. voltage at pin 7. This voltage can be used to blank the picture tube, so that the screen will not burn in.
Voltage stabilizer
The internal voltage stabilizer provides a stabilized supply of 6 V to drive the output stage, so the drive current is not
affected by supply voltage variations.

TDA2579B Horizontal/vertical synchronization circuit.
GENERAL DESCRIPTION
The TDA2579B generates and synchronizes horizontal and vertical signals. The device has a 3 level sandcastle output;
a transmitter identification signal and also 50/60 Hz identification.
Features
· Horizontal phase detector, (sync to oscillator), sync separator and noise inverter
· Triple current source in the phase detector with automatic selection
· Second phase detector for storage compensation of the horizontal output
· Stabilized direct starting of the horizontal oscillator and output stage from mains supply
· Horizontal output pulse with constant duty cycle value of 29 ms
· Internal vertical sync separator, and two integration selection times
· Divider system with three different reset enable windows
· Synchronization is set to 628 divider ratio when no vertical sync pulses and no video transmitter is identified
· Vertical comparator with a low DC feedback signal
· 50/60 Hz identification output combined with mute function
· Automatic amplitude adjustment for 50 and 60 Hz and blanking pulse duration
· Automatic adaption of the burst-key pulsewidth.


FUNCTIONAL DESCRIPTION
Vertical part (pins 1,2,3,4)
The IC embodies a synchronized divider system for generating the vertical sawtooth at pin 3. The divider system has an
internal frequency doubling circuit, so the horizontal oscillator is working at its normal line frequency and one line period
equals 2 clock pulses. Due to the divider system no vertical frequency adjustment is needed. The divider has a
discriminator window for automatically switching over from the 60 Hz to 50 Hz system. The divider system operates with
3 different divider reset windows for maximum interference/disturbance protection.
The windows are activated via an up/down counter. The counter increases its counter value by 1 for each time the
separated vertical sync pulse is within the searched window. The count is decreased by 1 when the vertical sync pulse
is not present.
Large (search) window: divider ratio between 488 and 722
This mode is valid for the following conditions:
1. Divider is looking for a new transmitter.
2. Divider ratio found, not within the narrow window limits.
3. Up/down counter value of the divider system operating in the narrow window mode decreases below count 1.
4. Externally setting. This can be reached by loading pin 18 with a resistor of 220 kW to earth or connecting a 3.6 V
diode stabistor between pin 18 and ground.
Narrow window: divider ratio between 522-528 (60 Hz) or 622-628 (50 Hz).
The divider system switches over to this mode when the up/down counter has reached its maximum value of 12 approved
vertical sync pulses. When the divider operates in this mode and a vertical sync pulse is missing within the window the
divider is reset at the end of the window and the counter value is decreased by 1. At a counter value below count 1 the
divider system switches over to the large window mode.
Standard TV-norm
When the up/down counter has reached its maximum value of 12 in the narrow window mode, the information applied to
the up/down counter is changed such that the standard divider ratio value is tested. When the counter has reached a
value of 14 the divider system is changed over to the standard divider ratio mode. In this mode the divider is always reset
at the standard value even if the vertical sync pulse is missing. A missed vertical sync pulse decreases the counter value
by 1. When the counter reaches the value of 10 the divider system is switched over to the large window mode.
The standard TV-norm condition gives maximum protection for video recorders playing tapes with anti-copy guards.
No-TV-transmitter found: (pin 18 < 1.2 V)
In this condition, only noise is present, the divider is rest to count 628. In this way a stable picture display at normal height
is achieved.
Video tape recorders in feature mode
It should be noted that some VTRs operating in the feature modes, such as picture search, generate such distorted
pictures that the no-TV-transmitter detection circuit can be activated as pin V18 drops below 1.2 V. This would imply a
rolling picture (see Phase detector, sub paragraph d). In general VTR-machines use a re-inserted vertical sync pulse in
the feature mode. Therefore the divider system has been made such that the automatic reset of the divider at count 628
when V18 is below 1.2 V is inhibited when a vertical sync pulse is detected.
The divider system also generates the anti-top-flutter pulse which inhibits the Phase 1 detector during the vertical sync.
pulse. The width of this pulse depends on the divider mode. For the divider mode a the start is generated at the reset of
the divider. In mode b and c the anti-top-flutter pulse starts at the beginning of the first equalizing pulse.

The anti-top-flutter pulse ends at count 8 for 50 Hz and count 10 for 60 Hz. The vertical blanking pulse is also generated
via the divider system. The start is at the reset of the divider while the pulse ends at count 34 (17 lines) for 60 Hz, and at
count 44 (22 lines) for 50 Hz systems. The vertical blanking pulse generated at the sandcastle output pin 17 is made by
adding the anti-top-flutter pulse and the blanking pulse. In this way the vertical blanking pulse starts at the beginning of
the first equalizing pulse when the divider operates in the b or c mode. For generating a vertical linear sawtooth voltage
a capacitor should be connected to pin 3. The recommended value is 150 nF to 330 nF (see Fig.1).
The capacitor is charged via an internal current source starting at the reset of the divider system. The voltage on the
capacitor is monitored by a comparator which is activated also at reset. When the capacitor has reached a voltage value
of 5.85 V for the 50 Hz system or 4.85 V for the 60 Hz system the voltage is kept constant until the charging period ends.
The charge period width is 26 clock pulses. At clock pulse 26 the comparator is switched off and the capacitor is
discharged by an npn transistor current source, the value of which can be set by an external resistor between pin 4 and
ground (pin 9). Pin 4 is connected to a pnp transistor current source which determines the current of the npn current
source at pin 3. The pnp current source on pin 4 is connected to an internal zener diode reference voltage which has a
typical voltage of » 7.5 volts. The recommended operating current range is 10 to 75 mA. The resistance at pin R4 should
be 100 to 770 kW. By using a double current mirror concept the vertical sawtooth pre-correction can be set on the desired
value by means of external components between pin 4 and pin 3, or by connecting the pin 4 resistor to the vertical current
measuring resistor of the vertical output stage. The vertical amplitude is set by the current of pin 4. The vertical feedback
voltage of the output stage has to be applied to pin 2. For the normal amplitude adjustment the values are DC = 1 V and
AC = 0.8 V. Due to the automatic system adaption both values are valid for 50 Hz and 60 Hz.
The low DC voltage value improves the picture bounce behaviour as less parabola compensation is necessary. Even a
fully DC coupled feedback circuit is possible.
Vertical guard
The IC also contains a vertical guard circuit. This circuit monitors the vertical feedback signal on pin 2. When the level
on pin 2 is below 0.35 V or higher than 1.85 V the guard circuit inserts a continuous level of 2.5 V in the sandcastle output
signal of pin 17. This results in the blanking of the picture displayed, thus preventing a burnt-in horizontal line. The guard
levels specified refer to the zener diode reference voltage source level.
Driver output
The driver output is at pin 1, it can deliver a drive current of 1.5 mA at 5 V output. The internal impedance is approximately
170 W. The output pin is also connected to an internal current source with a sink current of 0.25 mA.
Sync separator, phase detector and TV-station identification (pins 5,6,7,8 and 18).

Black level detector
A gating signal is used for the black level detector. This signal is composed of an internal horizontal reference pulse with
a duty factor of 50% and the flyback pulse at pin 12. In this way the TV-transmitter identification operates also for all DC
conditions at input pin 5 (no video modulation, plain carrier only).
During the frame interval the slicing level detector is inhibited by a signal which starts with the anti-top flutter pulse and
ends with the reset vertical divider circuit. In this way shift of the slicing level due to the vertical sync signal is reduced
and separation of the vertical sync pulse is improved.
Noise level detector
An internal noise inverter is activated when the video level at pin 5 decreases below 0.7 V. The IC also embodies a
built-in sync pulse noise level detection circuit. This circuit is directly connected to pin 5 and measures the noise level at
the middle of the horizontal sync pulse. When a signal-to-noise level of 19 dB is detected a counter circuit is activated.
A video input signal is processed as “acceptable noise free” when 12 out of 15 sync pulses have a noise level below
19 dB for two successive frame periods. The sync pulses are processed during a 15 line width gating period generated
by the divider system. The measuring circuit has a built-in noise level hysteresis of approximately 3 dB. When the
“acceptable noise free” condition is found the phase detector of pin 8 is switched to not gated and normal time constant.
When a higher sync pulse noise level is found the phase detector is switched over to slow time constant and gated sync
pulse phase detection. At the same time the integration time of the vertical sync pulse separator is adapted.