GRUNDIG SUPER COLOR 1845/30 SERIE 30F18 CHASSIS GSC200 (29304-178.01) UNITS VIEW.

GRUNDIG SUPER COLOR 1845/30 SERIE 30F18 CHASSIS GSC200 (29304-178.01) Modules - Units

Horizontal Bst. 29301-008.05 (Horizontal oscillator + Synch sep. with TDA 2593)
Vertikal Bst. 29301-009.05 (Frame deflection with oscillator with TDA1170)
Nf Baustein 29301-004.4 (Audio sound amplifier with IC with TBA 800)
Sicherung Bst 29301-410.01 (Safety Unit)
Ton-ZF-Baustein (IF SOUND) (TBA 120)
Regel Baustein 29301-035.03 (Horizontal thyristor circuit regulator Stabiliser with SN74121N)

MATRIX + RGB AMPLIFIERS (TDA2800)




















TBA120T (Siemens) SIF (Sound IF)

















TDA1170 vertical deflection FRAME DEFLECTION INTEGRATED CIRCUIT

Vertikal Bst. 29301-009.05 (Frame deflection with oscillator with TDA1170)

GENERAL DESCRIPTION
The TDA1170 and TDA1270 are monolithic integrated
circuits designed for use in TV vertical deflection systems. They are manufactured using
the Fairchild Planar* process.
Both devices are supplied in the 12-pin plastic power package with the heat sink fins bent
for insertion into the printed circuit board.
The TDA1170 is designed primarily for large and small screen black and white TV
receivers and industrial TV monitors. The TDA1270 is designed primarily for driving
complementary vertical deflection output stages in color TV receivers and industrial
monitors.
APPLICATION INFORMATION (TDA1170)
The vertical oscillator is directly synchronized by the sync pulses (positive or negative); therefore its free
running frequency must be lower than the sync frequency. The use of current feedback causes the yoke
current to be independent of yoke resistance variations due to thermal effects, Therefore no thermistor is
required in series with the yoke. The flyback generator applies a voltage, about twice the supply voltage, to
the yoke. This produces a short flyback time together with a high useful power to dissipated power
ratio.



TDA2521 synchronous demodulator for PAL

GENERAL DESCRIPTION
The TDA2521 is a monolithic integrated circuit designed as a synchronous demodulator for PAL color television receivers. It includes an 8.8 MHz oscillator and divider, to generate two 4.4 MHz reference signals, and provides color difference output.

The TDA2521 is intended to interface directly with the TDA251O with a minimum of external components and is constructed on a single silicon chip using the Fairchild Planar
epitaxial process.

ABSOLUTE MAXIMUM RATINGS
Supply Voltage 14 V
Internal Power Dissipation 600 mW ORDER INFQRMATIQN
Operating Temperature Range —2O°C to +6O°C TYPE PART NO.
Storage Temperature Range —55°C to +125°C 2521 TDA2521
Pin Temperature iSo|dering 10 si 260°C

Planar is a patented Fairchild process

















TDA2510 CHROMINANCE COMBINATION

GENERAL DESCRIPTION —
The TDA2510 is a monolithic integrated circuit designed for the function of a color television receiver. It Is designed to Interface directly with the TDA2521, using a minimum number of external components.
TDA251O is constructed on a single silicon chip using the Fairchild Planar‘ epitaxial process.

ABSOLUTE MAXIMUM RATINGS

supply Voltage 15 V
Collector voltage of chroma output transistor (pin 7) 20 V
(PD I 100 mW max)
Collector current of chroma output transistor (pin 7) 20 mA
Collector current of color killer output transistor (pin 11) 10 mA
Power dissipation 500 mW
Operating temperature range —25°C 10 +6O°
Storage temperature range *55°C to +12!-3°C


REGEL BAUSTEIN 29301-035.03 (Horizontal thyristor circuit regulator Stabiliser with SN74121N) LINE DEFL. REGULATION UNIT WITH SN74LS221N

The ’221 and ’LS221 devices are dual
multivibrators with performance characteristics
virtually identical to those of the ’121 devices.
Each multivibrator features a negative-transitiontriggered
input and a positive-transition-triggered
input, either of which can be used as an inhibit
input.

Pulse triggering occurs at a particular voltage level and is not directly related to the transition time of the input
pulse. Schmitt-trigger input circuitry (TTL hysteresis) for B input allows jitter-free triggering from inputs with
transition at rates as slow as 1 V/s, providing the circuit with excellent noise immunity, typically of 1.2 V. A high
immunity to VCC noise, typically of 1.5 V, also is provided by internal latching circuitry.
Once fired, the outputs are independent of further transitions of the A and B inputs and are a function of the timing
components, or the output pulses can be terminated by the overriding clear. Input pulses can be of any duration
relative to the output pulse. Output pulse length can be varied from 35 ns to the maximum by choosing
appropriate timing components. With Rext = 2 kΩ and Cext = 0, an output pulse typically of 30 ns is achieved
that can be used as a dc-triggered reset signal. Output rise and fall times are TTL compatible and independent
of pulse length. Typical triggering and clearing sequences are shown as a part of the switching characteristics
waveforms.
Pulse-width stability is achieved through internal compensation and is virtually independent of VCC and
temperature. In most applications, pulse stability is limited only by the accuracy of external timing components.
Jitter-free operation is maintained over the full temperature and VCC ranges for more than six decades of timing
capacitance (10 pF to 10 µF) and more than one decade of timing resistance (2 kΩ to 30 kΩ for the SN54221,
2 kΩ to 40 kΩ for the SN74221, 2 kΩ to 70 kΩ for the SN54LS221, and 2 kΩ to 100 kΩ for the SN74LS221).
Throughout these ranges, pulse width is defined by the relationship: tw(out) = CextRext In2 ≈ 0.7 CextRext. In
circuits where pulse cutoff is not critical, timing capacitance up to 1000 µF and timing resistance as low as 1.4 kΩ
can be used. Also, the range of jitter-free output pulse widths is extended if VCC is held to 5 V and free-air
temperature is 25°C. Duty cycles as high as 90% are achieved when using maximum recommended RT. Higher
duty cycles are available if a certain amount of pulse-width jitter is allowed.
The variance in output pulse width from device to device typically is less than ±0.5% for given external timing
components. An example of this distribution for the ’221 is shown in Figure 3. Variations in output pulse width
versus supply voltage and temperature for the ’221 are shown in Figures 4 and 5, respectively.
Pin assignments for these devices are identical to those of the SN54123/SN74123 or SN54LS123/SN74LS123
so that the ’221 or ’LS221 devices can be substituted for those products in systems not using the retrigger by
merely changing the value of Rext and/or Cext; however, the polarity of the capacitor must be changed.


FUNCTION TABLE
(each monostable multivibrator)
INPUTS OUTPUTS
CLR A B Q Q
L X X L H
X H X L H
X X L L H
H L ↑ † †
H ↓ H † †
↑‡ L H † †
† Pulsed-output patterns are tested during
AC switching at 25°C with Rext = 2 kΩ, and
Cext = 80 pF.
‡ This condition is true only if the output of
the latch formed by the two NAND gates
has been conditioned to the logic 1 state
prior to CLR going high. This latch is
conditioned by taking either A high or
B low while CLR is inactive (high).

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC 7 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, VI (see Note 1): ’LS221 7 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
’221 5.5 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance, θJA (see Note 2): D package 73°C/W . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DB package 82°C/W . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
N package 67°C/W . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
NS package 64°C/W . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, Tstg −65°C to 150°C.


TDA2591 SYNCHRO AND HORIZONTAL DEFLECTION CONTROL FOR COLOR TV SET

DESCRIPTION
The TDA2591 is a circuit intended for the horizontal
deflection of color TVsets, supplied with transistors
or SCR’S.

The TDA2591 and TDA2593 are integrated line
oscillator ‘_circuits for colour television receivers using
thyristor or transistor line deflection output stages.
The _circuits incorporate a line oscillator ‘which is
based on the threshold switching principle, a line de-
flection output stage capable of direct drive of thyristor
deflection circuits, phase comparison between the
oscillator voltage and both the sync pulse and line
flyback pulse. Also included on the chip is a switch for
changing the filter characteristic and the gate circuit
when used for VCR.
The TDA2593 generates a sandcastle pulse (at pin
7) suitable for use with the TDA.2532.

.LINE OSCILLATOR(two levels switching)
.PHASE COMPARISON BETWEEN SYNCHRO-
PULSE AND OSCILLATOR VOLTAGE Ø 1, ENABLED BY AN INTERNAL PULSE,
(better parasitic immunity)
PHASE COMPARISON BETWEEN THE FLYBACK
PULSES AND THE OSCILLATOR VOLTAGE Ø2
.COINCIDENCE DETECTOR PROVIDING A LARGE HOLD-IN-RANGE.
.FILTER CHARACTERISTICS AND GATE SWITCHING FOR VIDEO RECORDER APPLICATION.
.NOISE GATED SYNCHRO SEPARATOR
.FRAME PULSE SEPARATOR .BLANKING AND SAND CASTLE OUTPUT PULSES
.HORIZONTAL POWER STAGE PHASE LAGGING CIRCUIT
.SWITCHING OF CONTROL OUTPUT PULSE WIDTH
.SEPARATED SUPPLY VOLTAGE OUTPUT STAGE ALLOWING DIRECT DRIVE OF SCR’S CIRCUIT

.SECURITY CIRCUIT MAKES THE OUTPUT PULSE SUPPRESSED WHEN LOW SUPPLY
VOLTAGE.