PHILIPS 24TE2240 /8S TAMIGI CHASSIS E2 INTERNAL VIEW.

Left side:

- Tuner 3122 128 64171

- IF unit: 3112 248 56820

- TBA120AS





















Center:

Main Power Supply;

Line oscillator TBA920T

Right:

Deflections and line output transistor BUY71 (TOSHIBA)

This is a directly mains power supplyed chassis.

Note the Ballast resistor which is employed in parallel with Mains Stabiliser circuit.

TBA920 line oscillator combination
DESCRIPTION
The line oscillator combination TBA920 is a monolithic
integrated circuit intended for the horizontal deflection of the black and white
and colour TV sets
picture tube.

FEATURES:
SYNC-PULSE SEPARATION
OPTIONAL NOISE INVERSION
GENERATION OF A LINE FREQUENCY VOL-
TAGE BY MEANS OF AN OSCILLATOR
PHASE COMPARISON BETWEEN SYNC-
PULSE AND THE OSCILLATOR WAVEFORM
PHASE COMPARISON BETWEEN THE OS-
CILLATOR WAVEFORM AND THE MIDDLE OF
THE LINE FLY-BACK PULSE
AUTOMATIC SWITCHING OF THE VARIABLE
TRANSCONDUCTANCE AND THE VARIABLE
TIME CONSTANT TO ACHIEVE NOISE SUP-
PRESSION AND, BY SWITCHING OFF, POS-
SIBILITY OF TAPE-VIDEO-REGISTERED RE-
PRODUCTION
SHAPING AND AMPLIFICATION OF THE OS-
CILLATOR WAVEFORM TO OBTAIN PULSES
FOR THE CONTROL OF DRIVING STAGES IN
HORIZONTAL, DEFLECTION CIRCUITS
USING EITHER TRANSISTORS OR THYRISTORS.

BUY71 Transistor Datasheet. Parameters and Characteristics.

Type Designator: BUY71

Material of transistor: Si

Polarity: npn

Maximum collector power dissipation (Pc): 40W

Maximum collector-base voltage (Ucb): 2200V

Maximum collector-emitter voltage (Uce):

Maximum emitter-base voltage (Ueb): -

Maximum collector current (Ic max): 10A

Maximum junction temperature (Tj): 200°C

Transition frequency (ft): -

Collector capacitance (Cc), Pf: -

Forward current transfer ratio (hFE), min/max: 8MIN

Manufacturer of BUY71 transistor: TI

Package of BUY71 transistor: TO3

Application: Power, High Voltage, General Purpose


The SN7672O is a monolithic I2L integrated circuit. The device consists of a 5-bit
to 20 line address decoder, 12-bit 20 word RAM, 12-bit transparent presetable up/down
counter used for memory data transfer, a count down frequency selector, a 12-bit data
comparator for deriving the analog output and the necessary logic to interface the
memory, DAC and extemal controls.
The memory is directly accessable by a 5-bit binary code (O-19). The DAC output is
a constant frequency with a variable duty cycle determined by the addressed code in
A the memory. The analog output is derived from a comparator which compares the
contents oF the up/down counter with the contents of a synchronous counter. The DAC
output duty cycle and the corresponding addressed memory word may be changed by
applying a logic O to one, but not both, of the tune control inputs. This will increment
or decrement the binary code in the up/down counter and thus in the memory and the
analog pulse width.
The IC provides an output which delivers one logic 1 level pulse when, in tuning up,
the 12-bit up/down counter makes the transition From all 1~'s to all zeros and, when
tuning down, delivers two pulses when the transitione from all zeros to all is made.




PHILIPS 24TE 2240 /8S "Tamigi" CHASSIS E2 TUNING VOLTAGE MEMORY APPARATUS:
A voltage-memory apparatus comprises a main voltage-sweep circuit capable of holding a voltage without prominent loss of voltage and an auxiliary voltage-sweep circuit capable of boosting the held voltage. The memory apparatus is capable of memorizing a specified voltage applied to a variable capacitance diode which is provided as a tuning capacitance in tuner of a television receiver set, so that a tuned status is retained even when a broadcast wave is interrupted for a short time.


1. An apparatus comprising:

2. An apparatus according to claim 1, further comprising:

3. An apparatus according to claim 2, wherein said third means includes a summing junction, receiving the outputs of said first and second means, which is connected to one end of said variable-capacitance diode.

4. An apparatus according to claim 2, wherein the output of one of said first and second means is applied to one end of said variable-capacitance diode and further comprising sixth means, responsive to the output of the other of said first and second means, for inverting the polarity of said other output and applying said inverted polarity to the other end of said variable-capacitance diode.

5. An apparatus according to claim 2, wherein said fifth means comprises:

6. An apparatus according to claim 5, further comprising detection means, responsive to said second output voltage reaching a preset level, for initiating an increase in said first output voltage by said first means, and

7. An apparatus according to claim 6, wherein said detection means comprises a Schmitt trigger circuit connected at its input to the output of said second means, and its output to the input of said first means.

8. An apparatus according to claim 1 wherein said first means comprises:

9. An apparatus according to claim 1, wherein said first means comprises a metal-oxide-silicon transistor, at one electrode of which said first output voltage is supplied, and a voltage memory capacitor connected between the control gate of said transistor and a source of reference potential.

10. An apparatus according to claim 1 wherein said third means comprises a summing network, connected to the output of said first and second means, for summing said first and second output voltages.

11. An apparatus according to claim 10, further including a resonant circuit, including a variable-capacitance diode, connected to the output of said summing network.

12. An apparatus according to claim 11, further including a Schmitt trigger circuit connected between the output of said second means and the input of said first means.

13. An apparatus according to claim 12, wherein at least one of said first and second means comprises a storage capacitor and a transistor circuit coupled to said capacitor for controlling the charging and discharge thereof in response to a respective one of said inputs.

14. An apparatus according to claim 13, wherein each of said first and second means comprises a storage capacitor and a transistor circuit coupled thereto for supplying said first and second respective output voltages.

Description:

BACKGROUND OF THE INVENTION

This invention relates to a voltage-memory apparatus useful in an automatic tuning apparatus provided with a variable-capacitance diode as a tuning element.

Hitherto, there has been known a conventional automatic-tuning apparatus, or voltage-memory apparatus, wherein a voltage applied to a variable-capacitance element such as a variable-capacitance diode is sweepingly changed, i.e., increased or decreased over a certain lapse of time, so that the tuned frequency received by the tuner, which includes the variable-capacitance diode, is varied gradually so as to sweepingly change the tuned frequency. Then, in such an apparatus, upon being tuned at the frequency of the signal to be received by the tuning apparatus, an intermediate frequency signal is produced in a tuner, and a control signal is generated by detecting the intermediate frequency signal, and the control signal stops the increase or decrease of the applied voltage, so that a specified voltage is held across the diode and the apparatus is kept in a tuned state. In such a conventional apparatus there has been the defect that once the received and tuned signal is interrupted, this tuning is broken and the apparatus again starts to sweep its tuning frequency, and hence, is no longer tuned to the received signal.

SUMMARY OF THE INVENTION

This invention provides a voltage-memory apparatus having a high capability for memorizing a voltage, and further provides an automatic tuning apparatus.