TUNER 737694 AT349357054
With prescaler U665B
ELKO UNIT - BS1451 ET309378047
ST-BY SUPPLY - BS613 ET309309977
PLL SYNTHESIZER TUNING CONTROL BS656 AT349354169
with U3870 -Bit Microcontroller-Microcomputer - Plus 70 instruction set & binary timer
Vishay Telefunken
8-Bit Microcontrollers,Timers
Clock Frequency - Max. (Hz)=4.0M
Clock Frequency - Min. (Hz)=2.0M
Min Instruction Length (bits)=8
Max Instruction Length (bits)=24
Memory Addressing Range=64k
Number of Addressing Modes=5
On-Chip RAM (Bytes)=0
On-Chip ROM (bytes)=1.0k
Number of Interrupt Lines=1
No. of Non-Maskable Interrupts=0
Number of Maskable Interrupts=1
Number of I/O Lines=32
No. of I/O Ports=4
Vsup Nom.(V) Supply Voltage=5.0
Package=DIP
Pins=40
Military=N
Technology=NMOS
+ U3060 + ER1450 EAROM
VIDEO AT349354181
With TDA3562A
The TDA3562A is a monolithic IC designed as
decode PAL and/or NTSC colour television standards
and it combines all functions required for the
identification and demodulation of PAL and NTSC
signals.
.CHROMINANCE SIGNALPROCESSOR
.LUMINANCE SIGNAL PROCESSING WITH
CLAMPING
.HORIZONTAL AND VERTICAL BLANKING
.LINEAR TRANSMISSION OF INSERTED
RGB SIGNALS
.LINEAR CONTRAST AND BRIGHTNESS
CONTROL ACTING ON INSERTED AND MATRIXED
SIGNALS
.AUTOMATIC CUT-OFF CONTROL
.NTSC HUE CONTROL.
with TDA3562APAL/NTSC ONE-CHIP DECODER
DESCRIPTION:
The TDA3562A is a monolithic IC designed as
decode PAL and/or NTSC colour television standards
and it combines all functions required for the
identification and demodulation of PAL and NTSC
signals.
.CHROMINANCE SIGNALPROCESSOR
.LUMINANCE SIGNAL PROCESSING WITH
CLAMPING
.HORIZONTAL AND VERTICAL BLANKING
.LINEAR TRANSMISSION OF INSERTED
RGB SIGNALS
.LINEAR CONTRAST AND BRIGHTNESS
CONTROL ACTING ON INSERTED AND MATRIXED
SIGNALS
.AUTOMATIC CUT-OFF CONTROL
.NTSC HUE CONTROL.
TELEFUNKEN PALCOLOR 6462J CHASSIS 615A1 THE PHILIPS TDA3562A Circuit arrangement for the control of a picture tube :1. Circuit arrangement for the control of at least one beam current in a picture tube by a picture comprising
a control loop which in one sampling interval obtains a measuring signal from the value of the beam current on the occurrence of a given reference level in the picture signal, stores a control signal derived therefrom until the next sampling interval and thereby adjusts the beam current to a value preset by a reference signal.
and a trigger circuit which suppresses auxiliary pulses used to generate the beam current after the picture tube has been started up and issues a switching signal for the purpose of closing the control loop during the sampling intervals and for releasing the control of the beam current by the picture signal after the measuring signal has exceeded the threshold value,
a change detection arrangement which delivers a change signal when the stored signal has assumed a largely constant value, and
a logic network which does not release the control of the beam current by the picture signal outside the sampling intervals until the change signal has also been issued after the switching signal.
2. Circuit arrangement as set forth in claim 1, in which the picture signal comprises several color signals for the control of a corresponding number of beam currents for the display of a color picture in the picture tube and the control loop stores a part measuring signal or a part control signal derived therefrom for each color signal, characterized in that the change detection arrangement includes a change detector for each color signal which delivers a part change signal when the relevant stored signal has assumed a largely constant value, and the logic network does not release the control of the beam currents by the color signals outside the sampling intervals until the part change signals have been delivered by all change detectors.
3. Circuit arrangement as set forth in claim 1, including a comparator arrangement which compares the measuring signal with the reference signal and derives the control signal from this comparison, characterized in that the change detection arrangement detects a change in the control signal with respect to time and issues the change signal when the control signal has assumed a largely constant value.
4. Circuit arrangement as set forth in claims 1, 2, 3 including a control signal memory which contains at least one capacitor, characterized in that the change detection arrangement delivers the change signal when a charge-reversing current of the capacitor occuring during the starting up of the picture tube falls below a limit value.
5. Circuit arrangement as set forth in claim 2, including a comparator arrangement which compares the measuring signal with the reference signal and derives the control signal from this comparison, characterized in that the change detection arrangement detects a change in the control signal with respect to time and issues the change signal when the control signal has assumed a largely constant value.
Description:
BACKGROUND OF THE INVENTIONThe invention
relates to a circuit arrangement for the control of at least one beam
current in a picture tube by a picture signal with a control loop which
in one sampling interval obtains a measuring signal from the value of
the beam current on the occurrence of a given reference level in the
picture signal, stores a control signal derived therefrom until the next
sampling interval and by this means adjusts the beam current to a value
preset by a reference signal, and with a trigger circuit which
suppresses auxiliary pulses used to generate the beam current after the
picture tube is turned on and issues a switching signal for the purpose
of closing the control loop during the sampling intervals and releasing
the control of the beam current by the picture signal after the
measuring signal has exceeded a threshold value. Such a circuit arrangement has been described in Valvo Technische Information 820705 with regard to the integrated color decoder circuit PHILIPS TDA3562A and is used in this as a so-called cut-off point control. In the known circuit arrangement, such a cut-off point control provides automatic compensation of the so-called cut-off point of the picture tube, i.e. it regulates the beam current in the picture tube in such a way that for a given reference level in the picture signal the beam current has a constant value despite tolerances and changes with time (aging, thermal modifications) in the picture tube and the circuit arrangement, thereby ensuring correct picture reproduction.
Such a blocking point control is particularly adv
antageous for the operation of a picture tube
for the display of color pictures because in this case there are
several beam currents for different color components of the color
picture which have to be in a fixed ratio with one another. If this
ratio changes, for example, as the result of manufacturing tolerances or
ageing processes, distortions of the colors occur in the reproduction
of the color picture. The beam currents, therefore, have to be very
accurately balanced. The said cut-off point control prevents expensive
adjustment and maintenance time which is otherwise necessary. Conventional picutre tubes are constructed as cathode-ray tubes with hot cathodes which require a certain time after being turned on for the hot cathodes to heat up. Not until a final operating temperature has been reached do these hot cathodes emit the desired beam currents to the full extent, while gradually rising beam currents occur in the time interval when the hot cathodes are heating up. The instantaneous values of these beam currents depend on the instantaneous temperatures of the hot cathodes and on the accelerating voltages for the picture tube which build up simultaneously with the heating process and are undefined until the end of the heating time. After the picture tube is turned on, these values initially produce a highly distorted picture until the beam currents have attained their final value. These picture distortions after the picture tube is turned on are even further intensified by the fact that the cut-off point control is not yet adjusted to the beam currents which flow after the heating time is over.
For the purpose of suppressing distorted pictures during the heating time of the hot cathodes, the known circuit arrangement has a turn-on delay element
operating as a trigger circuit which, in essence, contains a bistable
flip-flop. When the picture tube and the circuit arrangement controlling
the beam currents flowing in it are turned on, the flip-flop is
switched into a first state in which it interrupts the supply of the
picture signal to the picture tube. Thus, during the heating time the
beam currents are suppressed, and the picture tube does not yet display
any picture. In sampling intervals which are provided subsequent to
flybacks of the cathode beam into an initial position on the changeover
from the display of one picture to the display of a subsequent picture
and even within the changeover, that is outside the display of pictures,
the picture tube is controlled for a short time in such a way that beam
currents occur when the hot cathodes are sufficiently heated up and an
accelerating voltage is resent. If these currents exceed a certain
threshold value, the flip-flop circuit switches into a second state and
releases the picture signal for the control of the beam currents and the
cut-off point control. It is found, however, that the picture displayed in the picture tube immediately after the switching over of the flip-flop is still not fault-free. Because, in fact, the beam currents are supported during the heating time of the hot cathodes, the cut-off point control cannot respond yet. This response of the cut-off point control takes place only after the beam currents are switched on, i.e. after the flip-flop is switched into the second state and therefore at a time in which the picture signal already controls the beam currents. In this way the response of the blocking point control makes its presence felt in the picture displayed.
With the known circuit arrangement the brightness of the picture gradually increases, during the response of the cut-off point control, from black to the final value.
This slow increase in the picture brightness after the tube is turned on is disturbing to the eyes of the viewer not only in the case of the black-and-white picture tubes with one hot cathode, but especially so in the case of colour picture tubes which usually have three hot cathodes. With a color picture tube, color purity errors can also
occur in addition to the change in the picture brightness if, as a
result of different speeds of response of the cut-off point control for
the three beam currents, there are found to be intermittent variations
from the interrelation between the beam currents required for a correct
picture reproduction.SUMMARY OF THE INVENTION
The aim of the invention is to create a circuit arrangement which suppresses the above-described disturbances of brightness and color of the displayed picture when the picture tube is being started.
The invention achieves this aim in that a circuit arrangement of the type mentioned in the preamble contains a change detection arrangement which emits a change signal when the stored signal has assumed an essentially constant value, and a logic network which does not release the control of the beam current by the picture signal until the change signal has also been emitted after the switching signal.
In the circuit
arrangement according to the invention, therefore, the display of the
picture is suppressed after the picture tube is turned on until the
cut-off point control has responded. If the picture signal then starts
to control the beam current, a perfect picture is displayed immediately.
In this way, all the disturbances of the picture which affect the
viewer's pleasure are suppressed. The circuit arrangement of the
invention is of simple design and can be combined on one semiconductor
wafer with the existing picture signal processing circuits and also, for
example, with the known circuit arrangement for cut-off point control.
Such an integrated circuit arrangement not only requires very little
space on the semiconductor wafer, but also needs no additional external
leads. Thus the circuit arrangement of the invention can be arranged,
for example, in an integrated circuit which has precisely the same
external connections as known integrated circuits. This means that an
integrated circuit containing the circuit arrangement of the invention
can be directly incorporated in existing equipment without the need for
additional measures. In one embodiment of the said circuit arrangement, in which the picture signal contains several color signals for the control of a corresponding number of beam currents for representing a color picture in the picture tube and, for each color signal, the control loop stores a part measuring signal or a part control signal derived from it, the change detection arrangement contains a change detector for each color signal which emits a part change signal when the relevant stored signal has assumed an essentially constant value, and the logic network does not release the control of the beam currents by the color signals outside the sampling intervals until the part change signals have been emitted from all change detectors.
In principle, therefore, such a circuit arrangement has three cut-off point controls for the three beam currents controlled by the individual color signals. To reduce the cost of the circuitry, the measuring stage is common to all the cut-off point controls, as in the known circuit arrangement. All three beam currents are then measured successively by this measuring stage. In this way, a part measuring signal or a part control signal derived from it is obtained for each beam current and is stored sesparately according to which of the beam currents it belongs. Changes in the part measuring signal or part control signal are detected for each beam current by one of the change detectors each time. Each of these change detectors issues a part change signal to the logic network. The latter does not release the control of the beam currents by the picture signal outside the sampling intervals until all the part change signals indicate that the part measuring signal or the part control signal, as the case may be, remains constant. This ensures that the cut-off point controls for the beam currents of all color signals have responded when the picture appears in the picture tube.
In a further embodiment of the circuit arrangement according to the invention with a comparator arrangement which compares the measuring signal with the reference signal and derives the control signal from this comparison, the change detection arrangement detects a change in the control signal with respect to time and issues the change signal when the control signal has assumed an essentially constant value. In the case of the representation of a color signal the comparator arrangement derives several part control signals, whose changes with time are detected by the change detectors, from a corresponding comparison of the part measuring signals with the reference signal. In this embodiment of the circuit arrangement of the invention, preference is given to storage of only the control signal or the part control signals for the purpose of controlling the beam currents.
In another embodiment of the circuit arrangement of the invention which includes a control signal memory which contains at least one capacitor in which a charge or voltage corresponding to the control signal is stored, the change detection arrangement issues the change signal when a charge-reversing current of the capacitor occurring during the turning on of the picture tube has fallen below a limit value and has thus at least largely decayed. Such a detection of the steady state of the cut-off point control is independent of the actual magnitude of the control signal and therefore independent of, for example, the level of the picture tube cut-off voltage, circuit tolerances or ageing processes in the circuit arrangement or the picture tube.
Detection of whether or not the charge-reversing current exceeds the limit value is performed preferentially by a current detector which is designed with a current mirror system which is arranged in a supply line to a capacitor acting as a control signal store. A current mirror arrangement of this kind supplies a current which coincides very precisely with the charging current of the capacitor. This current is then compared, preferably in a further device contained in the change detection arrangement, with a current representing a limit value or, after conversion into a voltage, with a voltage representing the limit value. The change signal is obtained from the result of this comparison.
On the other hand, digital memories may also be used as control signal memories, especially when the picture signal is supplied as a digital signal and the blocking point control is constructed as a digital control loop. In such a case, the comparator arrangement, the change detection arrangement and the trigger circuit are also designed as digital circuits. Then, the change detection arrangement advantageously forms the difference of the signals stored in the control signal memory in two successive sampling intervals and compares this with the limit value formed by a digital value. If the difference falls short of the limit value, the change signal is issued.
BRIEF DESCRIPTION OF THE DRAWINGS
An embodiment of the invention is described in greater detail below with the aid of the drawings in which:
FIG. 1 shows a block circuit diagram of the embodiment,
FIG. 2 shows a somewhat more detailed block circuit diagram of the embodiment,
FIG. 3 shows time-dependency diagrams of some signals occurring in the circuit diagram shown in FIG. 2, and
FIG. 4 shows a somewhat moredetailed block circuit diagram of a part of the circuit diagram shown in FIG. 2.
DETAILED DESCRIPTION OF THE INVENTIONFIG. 1 shows a block circuit diagram of a circuit arrangement to which a picture signal is fed via a first input 1 of a combinatorial stage 2. From the output 3 of the combinatorial stage 2 the picture signal is fed to the picture signal input of a controllable amplifier 5 which at an output 6 issues a current controlled by the picture signal. This current is fed via a measuring stage 7 to a hot cathode 8 in a picture tube 9 and forms therein a beam current of a cathode ray by means of which a picture defined by the picture signal is displayed on a fluorescent screen of the picture tube 9.
The measuring stage 7 measures the current fed to the hot cathode 8, i.e. the the beam current in the picture tube 9, and at a measuring signal output 10, issues a measuring signal corresponding to the magnitude of this current. This is fed to a measuring signal input 11 of a comparator arrangement 12 to which a reference signal is supplied at a reference signal input 13. In a preferably periodically recurring sampling interval during the occurrence of a given reference level in the picture signal, the comparator arrangement 12 forms a control signal from the value of the measuring signal fed to the measuring signal input 11 at this time, on the one hand, and the reference signal, on the other, by means of substraction and delivers this at a control signal output 14. From there the control signal is fed to an input 15 of a control signal memory 16 and is stored in the latter. The control signal is fed via an output 17 of the control signal memory 16 to a second input 18 of combinatorial stage 2 in which it is combined with the picture signal, e.g. added to it.
The combinatorial stage 2, the controllable amplifier 5, the measuring stage 7, the comparator arrangement 12 and the control signal memory 16 form a control loop with which the beam current is guided towards the reference signal in the sampling interval during the occurrence of the reference level in the picture signal. For the reference level, use is made in particular of a black level or a level with small, fixed distance from the black level, i.e. a value in the picture signal which produces a black or almost back picture area in the displayed picture in the picture tube. In this case the control loop, as described, forms a cut-off point control for the picture tube. If the reference level is away from the black level, the control loop is also designated as quasi-cut-off-point control.
The circuit
arrangement as shown in FIG. 1 also has a trigger circuit 19 to which
the measuring signal from the measuring signal output 10 of measuring
stage 7 is fed at a measuring signal input 20. When the circuit
arrangement and therefore the picture tube are turned on, the trigger
circuit 19 is set in a first state in which by means of a first
connection 21 it blocks the comparator arrangement 12 in such a way that
the latter delivers no control signal or a control signal with the
value zero at its control signal output 14. This prevents the control
signal memory 16 from storing undefined values for the control signal at
the moment of turning on or immediately thereafter.The circuit arrangement shown in FIG. 1 also has a logic network 22 which is connected via a second connection 23, by means of which a switching signal is supplied, with the trigger circuit 10 and via a third connection 24 with the controllable amplifier 5. Like the trigger circuit 19, the logic network 22 also finds itself controlled, when the circuit arrangement is being turned on, by the switching signal in a first stage in which by way of the third connection 24 it blocks the controllable amplifier 5 with a blocking signal in such a way that no beam currents controlled by the picture signal can yet flow in the picture tube 9. Thus the picture tube 9 is blanked; no picture is displayed yet.
When picture tube 9 is turned on, the hot cathode 8 is still cold so that no beam current can flow anyhow. The hot cathode 8 is then heated up and, after a certain time, begins gradually to emit electrons as the result of which a cathode ray and therefore a beam current can form. However, during the heating up of the hot cathode 8, and because the cut-off point control has not yet responded, this would be undefined and is therefore suppressed by the controllable amplifier 5. Only in time intervals which are provided immediately subsequent to flybacks of the cathode rays into an initial position at the changeover from the display of one image to that of a subsequent image, but even before the start of the display of the subsequent image, the controllable amplifier 5 delivers a voltage in the form of an auxiliary pulse for a short time at its output 6, and when the hot cathode 8 in the picture tube 9 is heated up sufficiently, this voltage produces a beam current. The time interval for the delivery of this voltage is selected in such a way that a cathode ray produced by its does not produce a visible image in the picture tube 9, and coincides for example with the sampling interval.
The measuring stage 7 measures the
short-time cathode current produced in the manner described and, at its
measuring signal output 10, delivers a corresponding measuring signal
which is passed via measuring signal output 20 to the trigger circuit
19. If the measuring signal exceeds a definite preset threshold value,
the trigger circuit 19 is switched into a second state in which it
releases the comparator arrangement 12 via the first connection 12 and,
by means of the second connection 23, uses the switching signal to also
bring the logic network 22 into a second state. The comparator
arrangement 12 now evaluates the measuring signal supplied to it via the
measuring signal input 11, i.e. it forms the control signal as the
difference between the measuring signal and the reference signal
supplied via the reference signal input 13. The control signal is
transferred via the control signal output 14 and the input 15 into the
control signal memory 16. It is subsequently fed via the output 17 of
the control signal memory 16 to the second input 18 of the combinatorial
stage 2 and is there combined with the picture signal at the first
input 1, e.g. is superimposed on it by addition. This superimposed
picture signal is fed to the picture signal input 4 of the controllable
amplifier 5 via the output 3 of the combinatorial stage 2. In the second state of the logic network 22 the controllable amplifier 5 is switched via the third connection 24 by the blocking signal in such a way that the picture signal controls the beam currents only during the sampling intervals and that, for the rest, no image appears yet in the picture tube. The cut-off point control now gebins to respond, i.e. the value of the control signal is changed by the control loop comprising the combinato
rial stage 2, the controllable amplifier 5, the measuring
stage 7, the comparator arrangement 12 and the control signal memory 16
until such time as the beam current in the picture tube 9 at the
blocking point or at a fixed level with respect to it is adjusted to a
value preset by the reference signal. For this purpose the sampling
interval, in which the picture signal controls the beam current via the
controllable amplifier 5 is selected in such a way that within it the
picture signal just assumes a value corresponding to the cut-off point
or to a fixed level with respect to it.During the response of the cut-off point control the control signal fed to the control signal memory 16 changes continuously. Between the control signal output 14 of the comparator arrangement 12 and the input 15 of the control signal memory 16 is inserted a changed detection arrangement 25 which detects the variations of the control signal. When the cut-off point control has responded, i.e. the control signal has assumed a constant value, the change detection arrangement 25 delivers a change signal at an output 26 which indicates that the steady stage of the cut-off point control is achieved and the said signal is fed to a change signal input 27 of the logic network 22. The logic network then switches into a third state in which via the third connection 24 it enables the controllable amplifier 5 in such a way that the beam currents are now controlled without restriction by the picture signal. Thus a correctly represented picture appears in the picture tube 9.
A shadow-like representation of individual constituents of the circuit arrangement in FIG. 1 is used to indicate a modification by which this circuit arrangement is equipped for the representation of color pictures in the picture tube 9. For example, three color signals are fed in this case as the picture signal via the input 1 to the combinatorial stage 2. Accordingly, the input 1 is shown in triplicate, and the combinatorial stage 2 has a logic element, e.g. an adder, for example of these color signals. The controllable amplifier 5 now has three amplifier stages, one for each of the color signals, and the picture tube now contains three hot cathodes 8 instead of one so that three independent cathode rays are available for the three color signals.
However, to simplify the circuit
arrangement and to save on components, only one measuring stage 7 is
provided which measures all three beam currents successively. Also, the
comparator arrangement 12 forms part control signals from the
successively arriving part measuring signals for the individual beam
currents with the reference signal, and these part control signals are
allocated to the individual color signals and passed on to three storage
units which are contained in the control signal memory 16. From there,
the part control signals are sent via the second input 18 of the
combinatorial stage 2 to the assigned logic elements. The circuit arrangement thus forms three independently acting control loops for the cut-off point control of the individual color signals, in which case only the measuring stage 7 and to some extent at least the comparator arrangement 12 are common to these control loops.
The change detection arrangement 25 now has three change detectors each of which detects the changes with time of the part control signals relating to a color signal. Then via the output 26 each of these change detectors delivers a part change signal to the change signal input 27 of the logic network 22. These part change signals occur independently of one another when the relevent control loop has responded. The logic network 22 evaluates all three part change signals and does not switch into its third stage until all part change signals indicate a steady state of the control loops. Only then, in fact, is it ensured that all the color signals from the beam currents controlled by them are correctly reproduced in the picture tube, and thus no distortions of the displayed image, especially no color purity errors, occur. The color picture displayed then immediately has the correct brightness and color on its appearance when the picture tube is turned on.
FIG. 2 shows a somewhat more detailed block circuit diagram of an embodiment of a circuit arrangement equipped for the processing of a picture signal containing three colour signals. Three color signals for the representation of the colors red, green and blue are fed to this circuit arrangement via three input terminals 101, 102, 103. A red color signal is fed via the first input terminal 101 to a first adder 201, a green colour signal is fed via the second input terminal to a second adder 202, and a blue colour signal is fed via the third input terminal 103 to a third adder 203. From outputs 301, 302 and 303 of the adders 201, 202, 203 the color signals are fed to amplifier stages 501, 502 and 503 respectively. Each of the amplifier stages contains a switchable amplifier 511, 512 and 513, an output amplifier 521, 522 and 523 as well as a measuring transistor 531, 532 and 533 respectively. The emitters of these measuring transistors 531, 532, 533 are each connected to a hot cathode 801, 802, 803 of the picture tube 9 and deliver the cathode currents, whereas the collectors of measuring transistors 521, 532, 533 are connected to one another and to a first terminal 701 of a measuring resistor 702 the second terminal of which 703 is connected to earth. The current gain of the measuring transistors 531, 532 and 533 is so great that their collector currents coincide almost with the cathode currents. By measuring the voltage drop produced by the cathode currents at the measuring resistor 802 it is then possible to measure the cathode currents and therefore the beam currents in the picture tube 9 with great accuracy.
The falling voltage at the measuring resistor 702
is fed as a measuring signal to an input 121 of a buffer amplifier 120
with a gain factor of one, at the output 122 of which the unchanged
measuring signal is therefore available at low impedance. From there it
is fed to a first terminal 131 of a reference voltage source 130 which
is connected with its second terminal 132 to inverting inputs 111, 112
and 113 of three differential amplifiers 123, 124, 125 respectively. The
differential amplifiers 123, 124, 125 also each have a non-inverting
input 114, 115, and 116 respectively. These are connected to each other
at a junction 117, to earth via a leakage current storage capacitor 126
and to the output 122 of the buffer amplifier 120 via decoupling
resistor 118 and a leakage current sampling switch 119. In addition, the
input 121 of the buffer amplifier 120 can be connected to earth via a
short-circuiting switch 127. 
The operation of the comparator arrangement 12 which consists mainly of the buffer amplifier 120, the reference voltage source 130 and differential amplifiers 123, 124, 125 will be explained below with the aid of the pulse diagrams in FIG. 3. FIG. 3a shows a horizontal blanking signal for a television signal which, as the picture signal, controls the beam currents in the picture tube 9. In this diagram, H represents horizontal blanking pulses which follow one another in the picture signal at the time interval of one line duration and by means of which the beam currents are switched off during line flyback between the display of the individual picture lines in the picture tube. FIG. 3b shows a vertical blanking pulse V by means of which the beam currents are switched off during the change ober from the display of one picture to the display of the next picture. FIG. 3c shows a measuring signal control pulse VH which is formed from a vertical blanking pulse lengthened by three line duration.
The short-circuiting switch 127 is now controlled in such a way that it is non-conducting only throughout the duration of the measuring signal control pulse VH and during the remaining time short-circuits the input 121 of the buffer amplifier 120 to earth. This means that a measuring signal only reaches the comparator arrangement 12 during frame change so that the parts of the picture signal which control the beam currents producing the picture in the picture tube exert no influence on comparator arrangement 12 and therefore on the blocking point control.
Throughout the duration of the measuring signal control pulse VH, the measuring signal from output 122, reduced by a reference voltage issued by the reference voltage source 130 between its first 131 and its second terminal 132, is present at the inverting inputs 111, 112, 113 of differential amplifiers 123, 124, 125. If the differential amplifiers 123, 124, 125 were not present, this difference would be fed directly as part control signals to the control signal storage capacitors 161, 162, 162. The differential amplifiers 123, 124, 125 amplify the difference and thus form the control amplifiers of the control loops.
The comparator
arrangement 12 further contains a device for compensation of the
influence of any leakage currents occurring in the picture tube 9. For
this purpose, a voltage to which the leakage current storage capacitor
126 is charged is fed to the non-inverting inputs 114, 115, 116 of the
three differential amplifiers 123, 124 and 125. The charging is
performed by the measuring signal from output 122 of the buffer
amplifier 120 via the decoupling resistor 118 and the leakage current
sampling switch 119 which is closed only within the period of the
vertical blanking pulse V, and in certain cases only during part of the
latter. Within this time the beam currents are, in fact, totally
switched off by the picture signal so that in certain cases only a
leakage current flows through the measuring resistor 702. Consequently,
throughout the duration of the vertical blanking pulse V the measuring
signal corresponds to this leakage current. Because the leakage current
also flows during the remaining time, even outside the duration of the
vertical blanking pulse the measuring signal contains a component
originating from the leakage current which therefore is also contained
in the voltage fed to the inverting inputs 111, 112, 113 of differential
amplifiers 123, 124, 125 and is subtracted out in the differential
amplifiers 123, 124, 125. The part control signal is fed from output 141 of differential amplifier 123 by the first control signal sampling switch 154 to the first terminal 151 of the first control signal storage capacitor 161 during the period of a storage pulse L1 and is stored in the said capacitor. Similarly, the part control signal from output 143 of differential amplifier 125 is fed to the third control signal storage capacitor 163 during the period of a storage pulse L2 and the part control signal from output 142 of differential amplifier 124 is fed to the second control signal storage capacitor 162 during a storage pulse L3. The storage pulses L1, L2 and L3 are illustrated in FIGS. 3d, e and f. They lie in sequence in one of the three line periods by which the measuring signal control pulse VH is longer than the vertical blan
king pulse V. These three line periods form
the sampling interval for the measuring signal or the part measuring
signals, as the case may be. During the remaining periods the outputs,
141, 152, 143 of the differential amplifiers 123, 124, 125 are isolated
from the control signal storage capacitors 161, 162, 163 so that no
interference can be transmitted from there and any distortion of the
stored part control signals caused thereby is eliminated. For the
duration of storage pulses L1, L2 and L3 the color signals at the input
terminals 101, 102, 103 are at their reference level i.e. in the present
embodiment at a level, corresponding to the blocking point or at a
fixed level with respect to it so that the control loops can adjust to
this level.The switchable amplifiers 511, 512, and 513 each receive at each input 241, 242, 243 a blanking signal BL1, BL2, BL3 respectively, the curves of which are shown in FIGS. 3g, h, i. These blanking signals interrupt the supply of the color signals during line flybacks and frame change, i.e. during the period of the measuring signal control pulse VH, and thus the beam currents in these time intervals are switched off. Naturally, the red color signal is let through during the first line period after the end of the vertical blanking pulse V, the blue color signal during the second line period after the end of the vertical blanking pulse V and the green color signal during the third line period after the end of the vertical blanking pulse V by the switchable amplifiers 511, 512, 513 respectively so that they can control the beam currents. Blanking signals BL1, BL2 and BL3 also provide for interruptions in the frame change blanking pulse, which corresponds to the measuring signal control pulse, in the corresponding time intervals. In these time intervals the beam currents are measured and part control signals are determined from the part measuring signals and stored in the control signal storage capacitors 161, 162, 163.
The circuit arrangement shown in FIG. 2 further contains a trigger circuit 19 to which a supply voltage is fed via a supply terminal 190. Via a reset input 191 a voltage is also
supplied to
the trigger circuit 19 from a third terminal 133 of the reference
voltage source 130. When the circuit arrangement is turned on, this
voltage is designed so as to be delayed with respect to the supply
voltage so that when the circuit arrangement is brought into operation
the interplay of the two voltages produces a switch-on reset signal such
that a low-value voltage pulse occurs at the reset input 191 during
turn on, which means that the trigger circuit 19 is set in its first
state. The reset input 191 can also be connected to another circuit of
any configuration which generates a switch-on reset signal when the
picture tube is turned on. The trigger circuit 19 is further connected via a second connection 23 to a logic network 22 which, when the circuit arrangement is turned on, is also set into a first state via the second connection 23. In this first state the logic network 22 delivers a blocking signal at a blocking output 240 which is fed to the three switchable amplifiers 511, 512, 513. By this means the supply of the color signals to the output amplifiers 521, 522, 523 is interrupted completely so that no beam currents can be generated by these. No picture is therefore displayed.
An insertion signal EL which
extends over the three line periods by which the measuring signal
control pulse VH is longer than the vertical blanking pulse V, i.e. over
the sampling interval, is also fed via a line 233 to the trigger
circuit 19 and the logic network 22. As long as the trigger circuit 19
is in its first state, this insertion pulse EL is issued via a control
output 192 from the trigger circuit 19 and fed to the pulse generator
244. During the period of the insertion pulse EL this generator produces
a voltage pulse of a definite magnitude and passes this to output
amplfiiers 521, 522, 523 as an auxiliary pulse via switching diodes 245,
246, 247. By this means the beam currents are switched on for a short
time so as to receive a measuring signal despite the disconnected color
signals as soon as at least one of the hot cathodes 801, 802, 803
delivers a beam current. In its first state the trigger circuit 19 also delivers a signal via a control line 211, and this signal is used to switch the outputs 141, 142, 143 of the differential amplifiers 123, 124, 125 to earth potential or practically to earth potential. This suppresses effects of voltages at the inputs 111 to 116 of the differential amplifiers 123, 124, 125, especially effects of the reference voltage source 130 which may in some cases initiate incorrect charging of the control signal storage capacitors 161, 162, 163.
The measuring signal produced by means of the pulse generator 244 at the input 121 of the buffer amplifier 120 is also fed to the trigger circuit 19 via a measuring signal input 20. If it exceeds a preset threshold value, the trigger circuit 19 switched into its second state. The logic network 22 is then also switched into its second state via the second connection 23. The differential amplifiers 123, 124, 125, too, are triggered by th
e signal along the control line 211 into issuing a
control signal defined by the difference in the voltages at its inputs
111 to 116. The pulse generator 244 is blocked by the control output
192. The blocking signal issued from the blocking output 240 of the
logic network 22 now turns on the switchable amplifiers 511, 512, 513 in
the time intervals defined by the storage pulses L1, L2, L3 in such a
way that in these time intervals the color signals can produce beam
currents to form a measuring signal by which the control loops respond.
However, the display of the picture is still suppressed. The control
signal storage capacitors 161, 162, 163 are charged up in this process.
In the leads to the first terminals 151, 152, 153 there are change
detectors 251, 252, 253 which detect the changes of the charging
currents of the control signal storage capacitors 161, 162, 163 and at
their outputs 261, 262, 263 in each case deliver a part change signal
when the charging current of the control signal storage capacitor in
question has decayed and thus the relevant control loop has responded.
The part change signals are fed to three terminals 271, 272, 273 of the
change signal input 27 of the logic network 22. When part change signals are present from all change detectors 251, 252, 253, when therefore all control loops have responded, the logic network 22 switches from its second to its third state. The blocking signal from the blocking output 240 is now completely disconnected such that the switchable amplifiers 511, 512, 513 are now switched only by the blanking signals BL1, BL2, BL3. The colour signals are then switched through to the output amplifiers 521, 522, 523 and the picture is displayed in the picture tube.
FIG. 4 shows an embodiment for a trigger circuit 19 and a logic network 22 of the circuit arrangements as shown in FIGS. 1 or 2. The trigger circuit 19 contains a flip-flop circuit formed from two NAND-gates 194, 195 to which the switch-on reset signal, by which the trigger circuit 19 is returned to its first stage, is fed via the reset input 191. All the elements of the circuit arrangement in FIG. 4 are shown in positive logic. Thus, a short-time low voltage at the reset input 191 immediately after the circuit arrangement is started up is used to set the flip-flop circuit 194, 195 in such a way that a high voltage occurs at the output of the second NAND gate 194 and a low voltage at the output of the second NAND gate 195. The low voltage at the output of the second NAND gate 195 blocks differential amplifiers 123, 124, 125 via the control line 211 in the manner described.
The insertion pulse EL is fed via the line 233 to the trigger circuit 19, is combined via an AND gate 196 with the signal from the output of the first NAND gate 194 and is delivered at the control output 192 for the purpose of controlling the pulse generator 244.
The signals from the outputs of the NAND-gates 194, 195 are fed via a first line 231 and a second line 232 of the second connection 23 as a switching signal to the logic network 22. The first line 231 is connected to reset inputs R of three part change signal memories 221, 222, 223 in the form of bistable flip-flop circuits which when the circuit arrangement is started up are reset via the first line 231 in such a way that they carry a low voltage at their outputs Q. The second line 232 of the second connection 23 leads via three AND gates 224, 225, 226 to setting inputs S of the three part change signal memories 221, 222, 223. By means of the AND gates 224, 225, 226 the signal on the second line 232 of the second connection 23 is combined each time with one of the part change signals supplied via the terminals 271, 272, 273. The signals from the outputs Q of the part change signal memories 221, 222, 223 are combined by means of a collecting gate 227 in the form of an NAND gate and are held ready at its output 228.
The measuring signal is fed to the trigger
circuit 19 via the measuring signal input 20 and passed to a first input
197 of a threshold detector 198 to which at a second input a threshold
value, in the form of a threshold voltage for example, produced by a
threshold generator 199 is also supplied. When the voltage at the first
input 197 of the threshold detector 198 is smaller than the voltage
delivered by the threshold generator 199, the threshold detector 198
delivers a high voltage at its output 200. When, on the other hand, the
voltage at the first input 197 is greater than the voltage of the
threshold generator 199, the voltage at the output 200 jumps to a low
value. This voltage is supplied as the setting signal of the flip-flop
circuit 194, 195, reverses the latter and thereby switches the trigger
circuit 19 into its second state when the voltage at the first input 197
exceeds the voltage of the threshold generator 199. Between the output 200 and the flip-flop circuit 194, 195 in the circuit arrangem
ent
shown in FIG. 4 there is inserted an inquiry gate 181 in the form of an
OR gate to which an inquiry pulse is fed via an inquiry input 193 of
the trigger circuit 19. This ensures that the flip-flop circuit 194, 195
is switched over only at a time fixed by the inquiry pulse--in the
present case a negative voltage pulse--and not at any other times due to
disturbances. As such an inquiry pulse it is possible to use, for
example, a pulse which occurs in the second line period after the end of
the vertical blanking pulse V, i.e. one which largely corresponds to
the storage pulse L2. After the switching over of the flip-flop circuit 194, 195 corresponding to the setting of the trigger circuit 19 into the second state, appropriately modified signals are supplied via the control line 211 and the output 192 for the purpose of controlling the pulse generator 244 and the differential amplifiers 123, 124, 125. Modified voltages also appear on the lines 231, 232 of the second connection 23, and these voltages release the part change signal memories 221, 222, 223 such that they can each be set when the part change signals reach the terminals 271, 272, 273.
In certain cases, a further flip-flop circuit
234 is inserted in the lines 231, 232
to delay the signals passing along these lines; this is reset via the
first line 231 when the circuit arrangement is started up and thus it
also resets the part change signal memories 221, 222, 223. However,
after the trigger circuit 19 is switched into the second state the
further flip-flop circuit 234 is not set via the second line 232 of the
second connection 23 until a release pulse arrives via a release input
235 and another AND gate 236, for example a period of approximately the
interval of two vertical blanking pulses V after the switching of the
trigger circuit 19 into the second state. In this way it is possible to
bridge a period of time in which no defined signal values are present at
the terminals 271, 272, 273. The signal at the output 228 of the collecting gate 227 changes its state when the last of the three part change signals has also arrived and has set the last of the three part change signal memories. The signal is then combined via a gate arrangement 229 of two NAND gates and one AND gate with the insertion pulse EL of line 223 and with the signal on the second line 232 of the second connection 23 or from the output Q of the further flip-flop circuit 234 to the blocking signal delivered at the blocking output 24 which is fed to the switchable amplifiers 511, 512, 513.
The circuit arrangement described is designed in such a way that the trigger circuit 19 remains in its second state and logic network 22 remains in its third state even if charging currents reappear at the difference signal storage cpacitors 161, 162, 163 due to disturbances during the operation of the circuit arrangement. The cutoff point control then makes readjustments without the displayed picture being disturbed.
In the circuit arrangement shown in F
IG. 2, the green
color signal can also be let through during the second line period after
the end of the vertical blanking pulse V and the blue color signal
during the third line period after the end of the vertical blanking
pulse V by the switchable amplifiers 511, 512, 513 for the purpose of
controlling the beam currents. The storage pulses L2 and L3 at the
control signal sampling switches 155 and 156 and the second and third
blanking signals BL2 and BL3 at the blanking inputs 242 and 243 are then
to be interchanged. The resulting insertion signals A2 and A3 as shown
in FIGS. 3m and n are also interchanged then accordingly. In FIG. 2 a dashed line is used to indicate which components of the circuit arrangement can be combined advantageously to form an integrated circuit. The first terminals 151, 152, 153 of the difference signal storage capacitors 161, 162, 163, one terminal 128 of leakage current storage capacitor 126, three terminals 524, 525, 526 in the leads to the output amplifiers 521, 522, 523 as well as a line connection 704 between the first terminal 701 of the measuring resistor 702 and the input 121 of the buffer amplifier 120 will then form the connecting contacts of this integrated circuit
TELEFUNKEN PLL SYNTHESIZER Digital phase control circuit including an auxiliary circuit
An electronically controllable tuning device includes a voltage controlled oscillator adapted to have an oscillation frequency controlled by a control voltage and simultaneously generate a fundamental wave of a predetermined frequency, a programmable frequency divider for dividing the fundamental wave frequency at a frequency division ratio corresponding to the control of a channel selection means and a phase locked loop adapted to compare the fundamental wave phase with the phase of the output of the programmable divider to generate a comparison output and feeding the comparison output back to the voltage controlled oscillator to control the output frequency of the voltage controlled oscillator. The tuning device further includes means for supplying as a local oscillation signal to an intermediate frequency generating mixer one of higher harmonic wave components of the fundamental wave.
A digital phase control circuit which includes a controllable oscillator, a programmable divider coupled to the oscillator, a reference frequency source, a phase discriminator coupled to the outputs of the programmable divider and reference frequency source and means coupling the output of the phase discriminator to a control input of the oscillator. In addition to these components, an auxiliary circuit is provided which has its input coupled to the output of the phase discriminator and first and second outputs coupled to the reference frequency source and the programmable divider. The auxiliary circuit generates a first signal at the input of the reference frequency source when the phase difference between the signals at the outputs of the programmable divider and the reference frequency source is in one direction and a second signal at the second input of the programmable divider when the phase difference is in the opposite direction. 1. In a digital phase control circuit including a controllable oscillator having a control input; a programmable first divider having first and second inputs, said first input being coupled to the output of said oscillator; a reference frequency source comprising a second divider having an input; a phase discriminator having first and second inputs coupled to the outputs of said programmable first divider and said second divider respectively, said phase discriminator further having output means; and means coupling the output means of said phase discriminator to the control input of said controllable oscillator, the frequency of said oscillator being controlled in a direction determined by the direction of the phase deviation between the signals applied to the first and second inputs of said phase discriminator and compared therein; the improvement comprising:
an auxiliary circuit having input means coupled to the output means of said phase discriminator, a first output coupled to the input of said second divider comprising said reference frequency source and a second output coupled to the second input of said programmable first divider, said auxiliary circuit generating a first synchronizing signal at the input of said second divider when the phase difference between the signals at the ou
tputs of said programmable first divider and said second divider is in one direction and generating a second synchronizing signal at the second input of said programmable first divider when the phase difference between the signals at the outputs of said programmable first divider and said second divider is in the opposite direction thereby setting either said programmable first divider or said second divider, respectively, to a predetermined initial phase position, the divider set to said predetermined initial phase position being maintained in said position until the other divider reaches its predetermined initial phase position.2. The phase control circuit defined by claim 1 wherein said auxiliary circuit comprises a clock pulse generator for generating a signal at a predetermined interval after generation of a signal at the output of said phase discriminator, an auxiliary circuit output signal being generated at the input of said second divider or at the input of said programmable first divider only if the signal at the output of said phase discriminator is generated for an interval longer than said predetermined interval. 3. The phase control circuit defined by claim 2 wherein the output of said phase discriminator and the output of said auxiliary circuit each comprise a plurality of sequential pulses having a leading edge and a trailing edge, the leading edges of the pulses at the output of said auxiliary circuit occurring later than the leading edges of the corresponding pulses at the output of said phase discriminator, and the trailing edges of the corresponding pulses at both the output of the auxiliary circuit and the output of the phase discriminator coinciding. 4. The phase control circuit defined by claim 2 wherein said clock pulse generator receives counting pulses at a constant frequency, means are provided for releasing said clock pulse generator to count said counting pulses from its predetermined initial position when a signal is generated at the output of said phase discriminator and means are provided for coupling the signal at the output of said clock pulse generator to a disable input thereof to stop said counter. 5. A phase control circuit as defined by claim 4 wherein the output means of said phase discriminator comprises a first output at which pulses appear when the frequency of said oscillator is increasing and a second output at which pulses appear when the frequency of said oscillator is decreasing, and wherein said auxiliary circuit further includes a first gating circuit having first and second inputs coupled to the first and second outputs of said phase discriminator and an output coupled to a reset terminal of said clock pulse generator, second and third gating circuits for coupling the output of said clock pulse generator to the input of said second divider and to the second input of said programmable first divider, respectively, and fourth and fifth gating circuits coupling the first and second outputs of said
phase discriminator to the inputs of said second and third gating circuits.
Description:
BACKGROUND OF THE INVENTION
This invention relates to digital phase control circuits and, in particular, to a phase control circuit which has improved transient response during its readjustment mode.
Digital phase control circuits are known which include a controllable oscillator, a programmable divider, a reference frequency source, a phase discriminator and a lowpass filter or integrating circuit. The output signal of the controllable oscillator is fed to one input of the phase discriminator via the programmable divider and the other input of the phase discriminator receives a signal from the reference frequency source. The low-pass filter circuit derives a control signal from the output of the phase discriminator so as to control the controllable oscillator.
The signals at the output of the phase discriminator have rectangular pulses. The average d.c. voltage of the rectangular pulses is obtained by means of the series-connected filter circuit which provides a setting voltage for the controllable oscillator. The circuit regulates itself in such a way that, in the steady-state, the signals applied to the phase discriminator coincide in frequency and phase.
In order to prevent excessive overshoot of the controllable oscillator, a minimum time constant is required in the filter circuit which may be designed, for example, as an active integrator. This results in a relatively long time constant for the entire system which can be detrimental in many cases. A long time constant may also increase the tendency toward resonance of the entire circuit.
It is an object of the present invention to provide a phase control circuit which is substantially improved with respect to its transient response during readjustment.
SUMMARY OF THE INVENTION
The present invention comprises a digital phase control circuit which includes a controllable oscillator, a programmable divider coupled to the oscillator, a reference frequency source, a phase discriminator coupled to the outputs of the programmable divider and reference frequency source and means coupling the output of the phase discriminator to a control input of the oscillator. In addition to these components, an auxiliary circuit is provided which has its input coupled to the output of the phase discriminator and first and second outputs coupled to the reference frequency source and the programmable divider. The auxiliary circuit generates a first signal at the input of the reference frequency source when the phase difference between the signals at the outputs of the programmable divider and the reference frequency source are in one direction and a second signal at the second input of the programmable divider when the phase difference is in the opposite direction.
Thus, in the present invention, an auxiliary circuit is provided in addition to the components of the prior art phase control circuit. This auxiliary circuit acts selectively on the programmable divider or the reference frequency source to reset the programmable divider or the reference frequency source, respectively, to a predetermined initial phase position at specific points in time. This initiates a comparison which begins at the predetermined initial phase position of the circuit. The comparison process beginning with the return of the predetermined initial position of the programmable divider or of the reference frequency source is repeated continuously. The invention operates such that, during every comparison cycle, a genuine phase or frequency comparison is effected between the two signals present at the phase discriminator. Each time at the start of the comparison cycle, the phase difference is defined as "zero." Therefore, the phase of frequency deviation present at the end of the comparison cycle between the two signals present at the phase discriminator is an exact measure of the phase deviation.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 shows a phase control circuit in accordance with the present invention.
FIGS. 2 and 3 show the output signals of a prior art phase control circuit for both directions of adjustment.
FIG. 4 is a pulse diagram of the signals in a phase control circuit including the features of the present invention for one direction of adjustment.
FIG. 5 shows signals corresponding to FIG. 4 for the other direction of adjustment.
FIG. 6 is a waveform diagram comparing the operation of the circuit with and without the auxiliary circuit of FIG. 1.
FIG. 7 shows an embodiment of the auxiliary circuit of FIG. 1.
FIG. 8 shows a television tuner constructed in accordance with the invention.
DESCRIPTION OF THE PREFERRED EMBODIMENTS
FIG. 1 is a block diagram showing a phase adjustment circuit which includes a voltage controllable oscillator 1 (VCO), a programmable divider 2, a reference source 4, a phase discriminator 3, a coupling circuit 6 and a l
owpass filter and amplifier circuit 5. These components are combined in a known manner to form a control loop. The programmable divider can be set to a selected dividing ratio which determines the initial frequency of the controllable oscillator 1. The programmable divider may also have fixed predividers (not shown) connected between it and the oscillator 1. The reference frequency source 4 includes a quartz oscillator 4a and a series-connected frequency divider 4b having, for example, a fixed dividing ratio. The output signal of the divider 4b is fed to the phase discriminator 3 to provide a reference signal.
Before describing auxiliary circuit 7 of FIG. 1, the operation of the prior art phase control circuit will be explained with the aid of FIGS. 2 and 3; that is, the circuit shown in FIG. 1 without the auxiliary circuit 7 will be described.
The output signal of the programmable divider 2 is shown at the top of FIG. 2. After each passage through the programmable divider 2, a negative pulse 8 appears at the output of this divider and is fed to the phase discriminator 3. In the second line of FIG. 2, the reference signal is shown which is fed to the other input of the phase discriminator 3.
The
phase discriminator 3 has an output 9 at which control pulses appear when the oscillator 1 is adjusted in the upward direction; that is, toward a higher frequency, and an output 10 at which pulses appear for an adjustment in the downward or lower frequency direction. The signals at outputs 9 and 10 are illustrated in the third and fourth lines of FIG. 2. The last line shows a so-called "tristate signal" which is obtained at the output of coupling circuit 6 and which is fed to the lowpass filter 5. The diagram shown in FIG. 2 is based on a so-called Type 4 phase discriminator which is described at page 19 of the book by Horst Geschwinde "Einfuhrung in die PLL-Technik" (Introduction to the PLL Technique), published by Vieweg. Each of the outputs 9 and 10 of the phase discriminator 3 has an associated output in a bistable circuit comprising the phase discriminator. In the illustrated case, the phase discrimin
ator 3 is designed so that the bistable circuits respond to the negative-going edge of the pulse 8 coming from the programmed divider 2. If there is a phase difference between the signals applied to the phase discriminator 3, pulses appear either at the "upward" output 9 or at the "downward" output 10, depending on the direction of the deviation. The bistable circuit associated with the "upward" output can be set by the edges 11 of the reference signal and reset by the pulses 8 coming from tne programmable divider 2. Conversely, the bistable circuit in the phase discriminator associated with the "downward" output can be set exactly oppositely by the pulses 8 coming from the programmable divider 2 and reset by the edges 11 of the reference signal.
FIG. 2 shows the signals for the case where at time t 0 the dividing ratio of the programmable divider 2 is switched to a higher value. Consequently, the frequency of the oscillator 1 is adjusted toward higher frequencies, which can be seen in FIG. 2 in that the pulses 8 at the output of the programmable divider jump toward a lower frequency after a new dividing ratio has been set into the programmable divider and thereafter are brought closer together by the adjustment process. Thus, at an interval indicated by the bracket 12, the frequency of the pulses coincides with the frequency of the reference signals but there still exists a phase deviation between the signals. This deviation can be overcome by temporarily increasing the frequency of the signal of oscillator 1 beyond the desired value. For that reason, the pulses at the "upward" output 9 continue to be generated. The prior art circuit thus exhibits an overshoot which is required by the system.
FIG. 3 is a pulse diagram in which the dividing ratio of the programmable divider 2 of FIG. 1 is set to a lower value at time t 0 . The time at w
hich coincidence with respect to frequency exists for the signals being compared in the phase discriminator is identified by a bracket 13. The operation of the prior art system under these conditions is analagous to the previously described operation under the conditions of FIG. 2.
The auxiliary circuit 7 of FIG. 1 resets the programmable divider 2 or the reference frequency source 4, to its initial position at specific points in time. The auxiliary circuit 7 is controlled by the signals at outputs 9 and 10 of the phase discriminator 3.
FIGS. 4 and 5 show how the auxiliary circuit of FIG. 1 controls the programmable divider 2 and the reference frequency source 4. FIG. 4 illustrates the operation of the circuit including auxiliary circuit 7 for a change in frequency corresponding to FIG. 2 wherein the oscillator frequency increases; that is, changes in the upward direction. It is assumed that the circuit has the same components as the circuits on which FIGS. 2 and 3 are based but that it includes in addition the auxiliary circuit 7.
The synchronizing signal A shown in the last line of FIG. 4 is generated by the auxiliary circuit 7. The synchronizing signal A includes pulses 14 and 17 which are fed to the reset input R of the reference frequency source. At time t 0 , a new dividing ratio is fed into the programmable divider 2 and at time t 1 the oscillator begins to increase its frequency so that the pulses 8 come closer together again. At time t 1 , the pulse 15 is initiated at the "upward" output 9 of the phase discriminator since the edge 11 of the reference signal appears earlier than the next pulse 8 from the programmable divider. The pulse 14 of the synchronizing signal A is derived from the pulse 15.
Pulse 14 is used initially to reset the divider 4b of the reference frequency source 4 which does not generate reference signal pulses as long as pulse 14 is present. At time t 2 , the pulse 15 and the output pulse 14 derived from pulse 15 are terminated. Thus, at time t 2 , the divider of the frequency source 4 is restarted from its basic position.
The frequency divider 4b may be a twelve bit divider consisting, for example, of two type CD4520 integrated circuits manufactured by RCA. This known divider is set to its basic position by a logical reset signal.
After a period T 1 of the reference signal, at time t 3 , a new control pulse 16 starts at the output 9 of the phase discriminator 3 since the edge 11 again appears earlier than the next pulse 8 from the programmable divider. A synchronizing pulse 17 is again generated which sets back the divider 4b of the reference frequency source 4 and stops it.
The adjustment is effected in the above-described manner until at time t 4 the signals being compared in the phase discriminator 3 coincide with respect to frequency and phase. As can be seen from a comparison of FIG. 4 with FIG. 2, this state is attained much faster than in the circuit without the auxiliary circuit 7. The control pulse terminated each time at the end of the comparison cycle provides a precise indication of the frequency deviation of the two signals applied to the phase discriminator, which is not the case in FIGS. 2 and 3.
Upon a change in the frequency of the oscillator in the opposite direction (downward), a synchronizing signal B is generated in the auxiliary circuit 7, as shown in FIG. 5, from the signal at "downward" output 10 of phase discriminator 3. With this synchronizing signal, the programmable divider 2 is controlled rather than the reference source 4 as shown in FIG. 4.
At time t 0 , as in FIG. 3, the dividing ratio of the programmable divider is reduced to correspond to the reduction in frequency of the oscillator 1. This initially effects an increase in the output frequency of the controllable oscillator. The synchronizing signal B is derived from the pulses 18 and 19 at the "downward" output 10 of the discriminator 3. This signal is fed to the load input L of the programmable divider 2. At time t 1 a pulse 8 from the programmable divider starts the pulse 18 at the output 10. The programmable divider is set by the synchronizing pulse 20 derived from pulse 18 and is kept in the initial position until time t 2 . At time t 2 , the edge 11 of the reference signal terminates the pulse 18. At the same time, the programmable divider begins to operate again. At t 3 , the pulse 19 at the output 10 is started because the next pulse 8 appears earlier than the next negative-going edge 11 of the reference signal. The synchronizing pulse 21 derived from pulse 19 again sets the programmable divider 2 and holds it in its initial position. At time t 4 the programmable divider 2 is released again and
the process continues.
The programmable divider 2 is a known component. For example, four type 74 LS169 integrated circuits manufactured by National Semiconductor may be used in series as a fourteen bit presettable down counter.
As is evident from the explanation of FIGS. 4 and 5, the reference frequency source 4 is controlled by the auxiliary circuit in one direction and the programmable divider 2, located between the oscillator 1 and the discriminator 3, in the other direction. The influenced circuit is controlled in accordance with the signals appearing at the output of the discriminator 3, which correspond to the phase or frequency error, so that at the beginning of each comparison cycle the phase error is assumed to be zero. In this way, adjustment of the circuit beyond the desired value is avoided. Thus, the described phase control circuit, including the auxiliary circuit 7, has very short transient periods.
FIGS. 4 and 5 show that the rising edge of the synchronizing signals A and B are shifted by the time τ with respect to the associated output signal of discriminator 3. By providing a predetermined delay period τ, the auxiliary circuit 7 is made effective for only a certain minimum width of the pulses of the output signal from discriminator 3. If the pulses at outputs 9 and 10 of the discriminator 3 fall below this minimum width, no synchronizing signals A or B are generated any longer. The circuit then operates in the customary manner, as described in connection with FIGS. 2 and 3. The delay period is advantageously selected to be greater than one period of the frequency of the reference oscillator so that the auxiliary circuit will not respond to the non-transient state.
If such a delay period is provided, the control circuit will be brought into a state, by means of the auxiliary circuit 7 provided to avoid overshooting, in which the signals present at the phase discriminator coincide with respect to frequency as well as phase. Then the auxiliary circuit 7 is no longer effective.
FIG. 6 shows the result obtained with the auxiliary circuit 7 by illustrating the control signal for oscillator 1. The top portion of FIG. 6 shows the signal obtained when an auxiliary circuit was used which operates in the manner described above under conditions of increasing frequency. The signal at the bott
om of FIG. 6 was obtained when the same circuit was used without auxiliary circuit 7. It can be seen that the auxiliary circuit 7 resulted in a significant improvement in the transient behavior.
FIG. 7 shows an embodiment of the auxiliary circuit 7 of FIG. 1. The auxiliary circuit includes a counter 22 and logic gates 23 to 27, the counter generating the fixed delay period λ. A typical counter which may be used for this purpose is the type CD4520 manufactured by RCA. The signals at the outputs 9 and 10 of the phase discriminator 3 are fed through an AND gate 23 to the reset input of the counter 22. The clock pulse input of the counter 22 receives, via an input terminal 30, counting pulses at a frequency of, for example, 1 MHz. If no pulse arrives from the outputs 9 and 10 of the phase discriminator, the reset input receives a reset signal and the clock pulses at the clock pulse input of the counter 22 are ineffective. The output Q n of the n th stage of the counter 22 is connected with a disable input D of the counter. That is, if the counter state Q n is reached, the counter stops itself. The synchronizing signals A and B are also derived from output Q n via gates 25 and 27. A signal is fed via inverters 24 and 26, to the gates 25 and 27 which act as gating circuits so as to indicate which one of the two gates 25 and 27 is to be enabled for the signal coming from output Q n . Gates 25 and 27 therefore control whether the programmable divider 2 or the reference frequency source 4 of FIG. 1 receives a synchronizing signal.
With reference to FIGS. 4 and 5, the circuit in FIG. 7 operates as follows: The pulse 15 in FIG. 4 is present at the input 9 and enables gate 27 via inverter 26 to provide a synchronizing signal. However, no pulse appears at output 29 because the output Q n of the counter 22 does not furnish a signal. Pulse 15 cancels the reset signal of counter 22 and counting pulses from input 30 are counted into the counter. After a delay period λ a signal jump appears at the output Q n , in accordance with the clock pulse frequency and the number of stages in the counter, which stops the counter 22 through the disable input. The change of signals at the output Q n also changes the logic state at the upper input of gate 27 so that the pulse 14 of FIG. 4 is formed. As soon as pulse 15 in FIG. 4 is completed, the AND condition for gate 27 is no longer met so that the pulse 14 is terminated simultaneously with pulse 15. The termination of pulse 15 causes the counter 22 to be reset to its starting position and held in that position.
When there is a pulse at input 10 of the circuit of FIG. 7, the circuit operates in a corresponding manner with the difference that gate 25 is enabled instead of gate 27. In this case, the synchronizing signal B is formed at output 28 and used to control the programmable divider 2. By selecting the frequency of the counting clock pulse at the input 30 it is possible to preselect the delay period λ.
It is also possible to obtain the delay period λ by means of circuit elements which operate in a different manner. For example, the delay of a plurality of series-connected gates (e.g., inverters) can be utilized.
FIG. 8 shows the complete circuit diagram of a tuner embodying the features of the present invention. At the top left of FIG. 1, block 31 is a tuner including the VCO 1. The signal from the VCO 1 travels through a predivider 32 included in the tuner to the programmable divider 2. At the beginning of a dividing cycle, the programmable divider is set to the preprogrammed value via a "load" input L and is then pulsed until it reaches the value zero. When it reaches the value zero, the load input receives a new charging pulse via a gate 33 with which the starting position of the programmable divider 2 is reset. The charging pulse of the programmable divider is fed to the input 35 of a phase discriminator 3 which is shown in dashed lines in FIG. 8. The other input 34 of the phase discriminator 3 receives a signal from the reference divider 4. The phase discriminator 3 which operates in a known manner, includes a plurality of gates.
At the lower right of FIG. 8, the coupling circuit 6 is shown. The auxiliary circuit 7 which has already been described in connection with FIG. 7 is shown in outline in FIG. 8. The synchronizing signal A is fed to the reset input of the reference divider 4 and the synchronizing signal B is fed to gate 33.
The auxiliary circuit 7 is also connected to a lock indicator which includes a counter 36, an AND gate 37 and an inverter 38. The counter 36 is set back with each synchronizing signal A and B via a reset input. Clock pulses at a relatively low frequency are fed to the clock pulse input of the counter 36 via an AND gate 37. These clock pulses are obtained from the output of the reference divider 4. From an output Q p , a lock signal is derived. This lock signal appears only if no synchronizing signal appears for a relatively long period of time. The supply of clock pulses through gate 37 is blocked as soon as the lock signal appears because of the feedback of the lock signal via an inverter 38. The lock signal remains in effect until a new synchronizing signal is formed.
The lower left of FIG. 8 shows the filter circuit 5 which includes an operational amplifier 39.
It will be understood that the above description of the present invention is susceptible to various modifications, changes and adaptations, and the same are intended to be comprehended within the meaning and range of equivalents of the appended claims.
This invention relates to digital phase control circuits and, in particular, to a phase control circuit which has improved transient response during its readjustment mode.
Digital phase control circuits are known which include a controllable oscillator, a programmable divider, a reference frequency source, a phase discriminator and a lowpass filter or integrating circuit. The output signal of the controllable oscillator is fed to one input of the phase discriminator via the programmable divider and the other input of the phase discriminator receives a signal from the reference frequency source. The low-pass filter circuit derives a control signal from the output of the phase discriminator so as to control the controllable oscillator.
The signals at the output of the phase discriminator have rectangular pulses. The average d.c. voltage of the rectangular pulses is obtained by means of the series-connected filter circuit which provides a setting voltage for the controllable oscillator. The circuit regulates itself in such a way that, in the steady-state, the signals applied to the phase discriminator coincide in frequency and phase.
In order to prevent excessive overshoot of the controllable oscillator, a minimum time constant is required in the filter circuit which may be designed, for example, as an active integrator. This results in a relatively long time constant for the entire system which can be detrimental in many cases. A long time constant may also increase the tendency toward resonance of the entire circuit.
It is an object of the present invention to provide a phase control circuit which is substantially improved with respect to its transient response during readjustment.
SUMMARY OF THE INVENTION
The present invention comprises a digital phase control circuit which includes a controllable oscillator, a programmable divider coupled to the oscillator, a reference frequency source, a phase discriminator coupled to the outputs of the programmable divider and reference frequency source and means coupling the output of the phase discriminator to a control input of the oscillator. In addition to these components, an auxiliary circuit is provided which has its input coupled to the output of the phase discriminator and first and second outputs coupled to the reference frequency source and the programmable divider. The auxiliary circuit generates a first signal at the input of the reference frequency source when the phase difference between the signals at the outputs of the programmable divider and the reference frequency source are in one direction and a second signal at the second input of the programmable divider when the phase difference is in the opposite direction.
Thus, in the present invention, an auxiliary circuit is provided in addition to the components of the prior art phase control circuit. This auxiliary circuit acts selectively on the programmable divider or the reference frequency source to reset the programmable divider or the reference frequency source, respectively, to a predetermined initial phase position at specific points in time. This initiates a comparison which begins at the predetermined initial phase position of the circuit. The comparison process beginning with the return of the predetermined initial position of the programmable divider or of the reference frequency source is repeated continuously. The invention operates such that, during every comparison cycle, a genuine phase or frequency comparison is effected between the two signals present at the phase discriminator. Each time at the start of the comparison cycle, the phase difference is defined as "zero." Therefore, the phase of frequency deviation present at the end of the comparison cycle between the two signals present at the phase discriminator is an exact measure of the phase deviation.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 shows a phase control circuit in accordance with the present invention.
FIGS. 2 and 3 show the output signals of a prior art phase control circuit for both directions of adjustment.
FIG. 4 is a pulse diagram of the signals in a phase control circuit including the features of the present invention for one direction of adjustment.
FIG. 5 shows signals corresponding to FIG. 4 for the other direction of adjustment.
FIG. 6 is a waveform diagram comparing the operation of the circuit with and without the auxiliary circuit of FIG. 1.
FIG. 7 shows an embodiment of the auxiliary circuit of FIG. 1.
FIG. 8 shows a television tuner constructed in accordance with the invention.
DESCRIPTION OF THE PREFERRED EMBODIMENTS
FIG. 1 is a block diagram showing a phase adjustment circuit which includes a voltage controllable oscillator 1 (VCO), a programmable divider 2, a reference source 4, a phase discriminator 3, a coupling circuit 6 and a l
owpass filter and amplifier circuit 5. These components are combined in a known manner to form a control loop. The programmable divider can be set to a selected dividing ratio which determines the initial frequency of the controllable oscillator 1. The programmable divider may also have fixed predividers (not shown) connected between it and the oscillator 1. The reference frequency source 4 includes a quartz oscillator 4a and a series-connected frequency divider 4b having, for example, a fixed dividing ratio. The output signal of the divider 4b is fed to the phase discriminator 3 to provide a reference signal. Before describing auxiliary circuit 7 of FIG. 1, the operation of the prior art phase control circuit will be explained with the aid of FIGS. 2 and 3; that is, the circuit shown in FIG. 1 without the auxiliary circuit 7 will be described.
The output signal of the programmable divider 2 is shown at the top of FIG. 2. After each passage through the programmable divider 2, a negative pulse 8 appears at the output of this divider and is fed to the phase discriminator 3. In the second line of FIG. 2, the reference signal is shown which is fed to the other input of the phase discriminator 3.
The
phase discriminator 3 has an output 9 at which control pulses appear when the oscillator 1 is adjusted in the upward direction; that is, toward a higher frequency, and an output 10 at which pulses appear for an adjustment in the downward or lower frequency direction. The signals at outputs 9 and 10 are illustrated in the third and fourth lines of FIG. 2. The last line shows a so-called "tristate signal" which is obtained at the output of coupling circuit 6 and which is fed to the lowpass filter 5. The diagram shown in FIG. 2 is based on a so-called Type 4 phase discriminator which is described at page 19 of the book by Horst Geschwinde "Einfuhrung in die PLL-Technik" (Introduction to the PLL Technique), published by Vieweg. Each of the outputs 9 and 10 of the phase discriminator 3 has an associated output in a bistable circuit comprising the phase discriminator. In the illustrated case, the phase discriminator 3 is designed so that the bistable circuits respond to the negative-going edge of the pulse 8 coming from the programmed divider 2. If there is a phase difference between the signals applied to the phase discriminator 3, pulses appear either at the "upward" output 9 or at the "downward" output 10, depending on the direction of the deviation. The bistable circuit associated with the "upward" output can be set by the edges 11 of the reference signal and reset by the pulses 8 coming from tne programmable divider 2. Conversely, the bistable circuit in the phase discriminator associated with the "downward" output can be set exactly oppositely by the pulses 8 coming from the programmable divider 2 and reset by the edges 11 of the reference signal. FIG. 2 shows the signals for the case where at time t 0 the dividing ratio of the programmable divider 2 is switched to a higher value. Consequently, the frequency of the oscillator 1 is adjusted toward higher frequencies, which can be seen in FIG. 2 in that the pulses 8 at the output of the programmable divider jump toward a lower frequency after a new dividing ratio has been set into the programmable divider and thereafter are brought closer together by the adjustment process. Thus, at an interval indicated by the bracket 12, the frequency of the pulses coincides with the frequency of the reference signals but there still exists a phase deviation between the signals. This deviation can be overcome by temporarily increasing the frequency of the signal of oscillator 1 beyond the desired value. For that reason, the pulses at the "upward" output 9 continue to be generated. The prior art circuit thus exhibits an overshoot which is required by the system.
FIG. 3 is a pulse diagram in which the dividing ratio of the programmable divider 2 of FIG. 1 is set to a lower value at time t 0 . The time at w
hich coincidence with respect to frequency exists for the signals being compared in the phase discriminator is identified by a bracket 13. The operation of the prior art system under these conditions is analagous to the previously described operation under the conditions of FIG. 2. The auxiliary circuit 7 of FIG. 1 resets the programmable divider 2 or the reference frequency source 4, to its initial position at specific points in time. The auxiliary circuit 7 is controlled by the signals at outputs 9 and 10 of the phase discriminator 3.
FIGS. 4 and 5 show how the auxiliary circuit of FIG. 1 controls the programmable divider 2 and the reference frequency source 4. FIG. 4 illustrates the operation of the circuit including auxiliary circuit 7 for a change in frequency corresponding to FIG. 2 wherein the oscillator frequency increases; that is, changes in the upward direction. It is assumed that the circuit has the same components as the circuits on which FIGS. 2 and 3 are based but that it includes in addition the auxiliary circuit 7.
The synchronizing signal A shown in the last line of FIG. 4 is generated by the auxiliary circuit 7. The synchronizing signal A includes pulses 14 and 17 which are fed to the reset input R of the reference frequency source. At time t 0 , a new dividing ratio is fed into the programmable divider 2 and at time t 1 the oscillator begins to increase its frequency so that the pulses 8 come closer together again. At time t 1 , the pulse 15 is initiated at the "upward" output 9 of the phase discriminator since the edge 11 of the reference signal appears earlier than the next pulse 8 from the programmable divider. The pulse 14 of the synchronizing signal A is derived from the pulse 15.
Pulse 14 is used initially to reset the divider 4b of the reference frequency source 4 which does not generate reference signal pulses as long as pulse 14 is present. At time t 2 , the pulse 15 and the output pulse 14 derived from pulse 15 are terminated. Thus, at time t 2 , the divider of the frequency source 4 is restarted from its basic position.
The frequency divider 4b may be a twelve bit divider consisting, for example, of two type CD4520 integrated circuits manufactured by RCA. This known divider is set to its basic position by a logical reset signal.
After a period T 1 of the reference signal, at time t 3 , a new control pulse 16 starts at the output 9 of the phase discriminator 3 since the edge 11 again appears earlier than the next pulse 8 from the programmable divider. A synchronizing pulse 17 is again generated which sets back the divider 4b of the reference frequency source 4 and stops it.
The adjustment is effected in the above-described manner until at time t 4 the signals being compared in the phase discriminator 3 coincide with respect to frequency and phase. As can be seen from a comparison of FIG. 4 with FIG. 2, this state is attained much faster than in the circuit without the auxiliary circuit 7. The control pulse terminated each time at the end of the comparison cycle provides a precise indication of the frequency deviation of the two signals applied to the phase discriminator, which is not the case in FIGS. 2 and 3.
Upon a change in the frequency of the oscillator in the opposite direction (downward), a synchronizing signal B is generated in the auxiliary circuit 7, as shown in FIG. 5, from the signal at "downward" output 10 of phase discriminator 3. With this synchronizing signal, the programmable divider 2 is controlled rather than the reference source 4 as shown in FIG. 4.
At time t 0 , as in FIG. 3, the dividing ratio of the programmable divider is reduced to correspond to the reduction in frequency of the oscillator 1. This initially effects an increase in the output frequency of the controllable oscillator. The synchronizing signal B is derived from the pulses 18 and 19 at the "downward" output 10 of the discriminator 3. This signal is fed to the load input L of the programmable divider 2. At time t 1 a pulse 8 from the programmable divider starts the pulse 18 at the output 10. The programmable divider is set by the synchronizing pulse 20 derived from pulse 18 and is kept in the initial position until time t 2 . At time t 2 , the edge 11 of the reference signal terminates the pulse 18. At the same time, the programmable divider begins to operate again. At t 3 , the pulse 19 at the output 10 is started because the next pulse 8 appears earlier than the next negative-going edge 11 of the reference signal. The synchronizing pulse 21 derived from pulse 19 again sets the programmable divider 2 and holds it in its initial position. At time t 4 the programmable divider 2 is released again and
the process continues. The programmable divider 2 is a known component. For example, four type 74 LS169 integrated circuits manufactured by National Semiconductor may be used in series as a fourteen bit presettable down counter.
As is evident from the explanation of FIGS. 4 and 5, the reference frequency source 4 is controlled by the auxiliary circuit in one direction and the programmable divider 2, located between the oscillator 1 and the discriminator 3, in the other direction. The influenced circuit is controlled in accordance with the signals appearing at the output of the discriminator 3, which correspond to the phase or frequency error, so that at the beginning of each comparison cycle the phase error is assumed to be zero. In this way, adjustment of the circuit beyond the desired value is avoided. Thus, the described phase control circuit, including the auxiliary circuit 7, has very short transient periods.
FIGS. 4 and 5 show that the rising edge of the synchronizing signals A and B are shifted by the time τ with respect to the associated output signal of discriminator 3. By providing a predetermined delay period τ, the auxiliary circuit 7 is made effective for only a certain minimum width of the pulses of the output signal from discriminator 3. If the pulses at outputs 9 and 10 of the discriminator 3 fall below this minimum width, no synchronizing signals A or B are generated any longer. The circuit then operates in the customary manner, as described in connection with FIGS. 2 and 3. The delay period is advantageously selected to be greater than one period of the frequency of the reference oscillator so that the auxiliary circuit will not respond to the non-transient state.
If such a delay period is provided, the control circuit will be brought into a state, by means of the auxiliary circuit 7 provided to avoid overshooting, in which the signals present at the phase discriminator coincide with respect to frequency as well as phase. Then the auxiliary circuit 7 is no longer effective.
FIG. 6 shows the result obtained with the auxiliary circuit 7 by illustrating the control signal for oscillator 1. The top portion of FIG. 6 shows the signal obtained when an auxiliary circuit was used which operates in the manner described above under conditions of increasing frequency. The signal at the bott
om of FIG. 6 was obtained when the same circuit was used without auxiliary circuit 7. It can be seen that the auxiliary circuit 7 resulted in a significant improvement in the transient behavior. FIG. 7 shows an embodiment of the auxiliary circuit 7 of FIG. 1. The auxiliary circuit includes a counter 22 and logic gates 23 to 27, the counter generating the fixed delay period λ. A typical counter which may be used for this purpose is the type CD4520 manufactured by RCA. The signals at the outputs 9 and 10 of the phase discriminator 3 are fed through an AND gate 23 to the reset input of the counter 22. The clock pulse input of the counter 22 receives, via an input terminal 30, counting pulses at a frequency of, for example, 1 MHz. If no pulse arrives from the outputs 9 and 10 of the phase discriminator, the reset input receives a reset signal and the clock pulses at the clock pulse input of the counter 22 are ineffective. The output Q n of the n th stage of the counter 22 is connected with a disable input D of the counter. That is, if the counter state Q n is reached, the counter stops itself. The synchronizing signals A and B are also derived from output Q n via gates 25 and 27. A signal is fed via inverters 24 and 26, to the gates 25 and 27 which act as gating circuits so as to indicate which one of the two gates 25 and 27 is to be enabled for the signal coming from output Q n . Gates 25 and 27 therefore control whether the programmable divider 2 or the reference frequency source 4 of FIG. 1 receives a synchronizing signal.
With reference to FIGS. 4 and
5, the circuit in FIG. 7 operates as follows: The pulse 15 in FIG. 4 is present at the input 9 and enables gate 27 via inverter 26 to provide a synchronizing signal. However, no pulse appears at output 29 because the output Q n of the counter 22 does not furnish a signal. Pulse 15 cancels the reset signal of counter 22 and counting pulses from input 30 are counted into the counter. After a delay period λ a signal jump appears at the output Q n , in accordance with the clock pulse frequency and the number of stages in the counter, which stops the counter 22 through the disable input. The change of signals at the output Q n also changes the logic state at the upper input of gate 27 so that the pulse 14 of FIG. 4 is formed. As soon as pulse 15 in FIG. 4 is completed, the AND condition for gate 27 is no longer met so that the pulse 14 is terminated simultaneously with pulse 15. The termination of pulse 15 causes the counter 22 to be reset to its starting position and held in that position. When there is a pulse at input 10 of the circuit of FIG. 7, the circuit operates in a corresponding manner with the difference that gate 25 is enabled instead of gate 27. In this case, the synchronizing signal B is formed at output 28 and used to control the programmable divider 2. By selecting the frequency of the counting clock pulse at the input 30 it is possible to preselect the delay period λ.
It is also possible to obtain the delay period λ by means of circuit elements which operate in a different manner. For example, the delay of a plurality of series-connected gates (e.g., inverters) can be utilized.
FIG. 8 shows the complete circuit diagram of a tuner embodying the features of the present invention. At the top left of FIG. 1, block 31 is a tuner including the VCO 1. The signal from the VCO 1 travels through a predivider 32 included in the tuner to the programmable divider 2. At the beginning of a dividing cycle, the programmable divider is set to the preprogrammed value via a "load" input L and is then pulsed until it reaches the value zero. When it reaches the value zero, the load input receives a new charging pulse via a gate 33 with which the starting position of the programmable divider 2 is reset. The charging pulse of the programmable divider is fed to the input 35 of a phase discriminator 3 which is shown in dashed lines in FIG. 8. The other input 34 of the phase discriminator 3 receives a signal from the reference divider 4. The phase discriminator 3 which operates in a known manner, includes a plurality of gates.
At the lower right of FIG. 8, the coupling circuit 6 is shown. The auxiliary circuit 7 which has already been described in connection with FIG. 7 is shown in outline in FIG. 8. The synchronizing signal A is fed to the reset input of the reference divider 4 and the synchronizing signal B is fed to gate 33.
The auxiliary circuit 7 is also connected to a lock indicator which includes a counter 36, an AND gate 37 and an inverter 38. The counter 36 is set back with each synchronizing signal A and B via a reset input. Clock pulses at a relatively low frequency are fed to the clock pulse input of the counter 36 via an AND gate 37. These clock pulses are obtained from the output of the reference divider 4. From an output Q p , a lock signal is derived. This lock signal appears only if no synchronizing signal appears for a relatively long period of time. The supply of clock pulses through gate 37 is blocked as soon as the lock signal appears because of the feedback of the lock signal via an inverter 38. The lock signal remains in effect until a new synchronizing signal is formed.
The lower left of FIG. 8 shows the filter circuit 5 which includes an operational amplifier 39.
It will be understood that the above description of the present invention is susceptible to various modifications, changes
and adaptations, and the same are intended to be comprehended within the meaning and range of equivalents of the appended claims. TELEFUNKEN Superheterodyne receiver frequency tracking circuit:
In a superheterodyne signal receiver including an input circuit arranged to be tuned to a frequency to be received and including a signal controllable variable reactance element presenting a reactan
ce whose value is adjusted by a tuning signal and determines the frequency to which the input circuit is tuned, and a controllable local oscillator producing an alternating signal to be mixed with a received signal to produce an intermediate frequency received signal, a tracking circuit composed of: a first frequency control circuit including the local oscillator; a second frequency control circuit including a controllable sampling oscillator and a member connected to respond to the frequency of the output from the sampling oscillator to derive a signal related thereto and supplying that signal, as the tuning signal, to the controllable element; and a control signal generating unit generating first and second control signals and connected for supplying the first control signal to the first frequency control circuit for adjusting the frequency of the signal produced by the local oscillator, and for supplying the second control signal to the second frequency control circuit for adjusting the value of the tuning signal to tune the input circuit to a selected frequency, the generating unit maintaining a relationship between the first and second control signals such that the output frequency of the local oscillator is adjusted to the value corresponding to the received signal frequency to which the input circuit is tuned. 1. In a superheterodyne signal receiver including an input circuit arranged to be tuned to a frequency to be received and including a signal controllable variable reactance element presenting a reactance whose value is adjusted by a tuning signal and determines the frequency to which the input circuit is tuned, and a controllable local oscillator producing an alternating signal to be mixed with a received signal to produce an intermediate frequency received signal, a synchronizing circuit comprising: a first frequency control circuit including said local oscillator; a second frequency control circuit including a controllable sampling oscillator and means connected to respond to the frequency of the output from said sampling oscillator to derive a signal related thereto and supplying that signal, as the tuning signal, to said controllable element; and control signal generating means generating first and second control signals and connected for supplying said first control signal to said first frequency control circuit for adjusting the frequency of the signal produced by said local oscillator, and for supplying said second control signal to said second frequency control circuit for adjusting the value of said tuning signal to tune said input circuit to a selected frequency, said generating means maintaining a relationship between said first and second control signals such that the output frequency of said local oscillator is adjusted to the value corresponding to the received signal frequency to which said input circuit is tuned, wherein each said frequency control circuit includes converter means connected to provide an output signal representative of the frequency of the signal produced by its associated oscillator, and oscillator control means having a first input connected to receive the output signal provided by its associated converter means, a second input connected to receive its respective control signal and an output connected to supply its associated oscillator with a setting signal which is dependent on a relation between the signals at its first and second inputs for establishing a linear relationship between its respective control signal and the frequency produced by its respective oscillator, said synchronizing circuit further comprises a source of an addition a.c. signal, and said converter means of at least one said circuit has at least two inputs one of which is connected to receive a signal derived from the signal at the output of its associated oscillator and the other of which is connected to receive the additional a.c. signal and acts to cause its output signal to be dependent on a relationship between the frequencies of the signals applied to its two inputs.
2. In a superheterodyne signal receiver input section including: an input circuit, arranged to be tuned to the frequency of a signal to be received and containing a controllable reactance the value of which is adjusted by a tuning signal and determines the frequency to which the input circuit is tuned; a controllable local oscillator producing an alternating signal to be mixed with a received signal supplied by the input circuit to produce an intermediate frequency received signal; a first frequency control loop composed of the local oscillator, a first converter connected to provide an output signal representative of the frequency of the signal produced by the local oscillator, and first oscillator control means having a first input connected to receive the output signal provided by the first converter, a second input connected to receive a first control signal and an output connected to supply the local oscillator with a setting signal to adjust the frequency of the signal produced by the local oscillator as a function of a relation between the first control signal and the output signal provided by the first converter, with the local oscillator, first converter and first oscillator control means being connected together in a loop; a second frequency control loop including a controllable sampling oscillator containing a controllable reactance the value of which determines the frequency of the signal produced by the sampling oscillator, a second converter connected to provide an output signal representative of the frequency of the signal produced by the sampling oscillator control means having a first input connected to receive the output signal provided by the second converter, a second input connected to receive a second control signal and an output connected to supply the sampling oscillator with a setting signal to adjust the frequency of the signal produced by the sampling oscillator as a function of a relation between the second control signal and the output signal provided by the second converter, and means connected to supply the tuning signal to the input circuit, the value of which tuning signal is a function of the frequency of the signal being produced by the sampling oscillator, with the sampling oscillator, second converter and second oscillator control means being connected together in a loop; and control signal generating means including a source of a reference signal and means for causing the first and second control signals to be functions of the reference signal and to be so related to one another that the input circuit is tuned to a received signal frequency corresponding to the output frequency of the local oscillator, the improvement wherein said reference signal source comprises a source of an a.c. reference frequency signal, and a third converter connected to receive the reference frequency signal and to provide said reference signal at its output for compensating undesirable changes in the output signals produced by said first and second converters as a result of external adverse influences.
3. Circuit arrangement as defined in claim 2 wherein said control signal generating means comprise a common control element constituting the source of both said first and second control signals.
4. Circ
uit arrangement as defined in claim 3 wherein said control signal generating means further comprise signal modifying means connected to subject the output of said common control element to arithmetic operations for giving said first control signal a value which causes the output frequency of said local oscillator to be offset from the corresponding received signal frequency by a constant amount corresponding to the intermediate frequency value and for giving said second control signal a value which causes said tuning signal to tune said input circuit to a frequency corresponding to the frequency of the output of said local oscillator and differing from said local oscillator frequency by the intermediate frequency. 5. Circuit arrangement as defined in claim 4 wherein each of said first and second converters includes means establishing a linear relationship between its respective control signal and the frequency produced by its respective oscillator.
6. Circuit arrangement as defined in claim 5 wherein at least one of said control signals is an analog signal.
7. Circuit arrangement as defined in claim 6 wherein at least one said oscillator control means comprises a comparator.
8. Circuit arrangement as defined in claim 7 wherein, in said at least one loop, said comparator has two inputs, one of which is connected to the output of said converter in the same loop, said comparator having an output connected to control the frequency of said oscillator associated with the same loop, and said control signal for said loop is supplied to the second input of said comparator.
9. Circuit arrangement as defined in claim 5 wherein said converter of at least one said loop has at least two inputs for receiving a signal from the oscillator associated with said loop and the a.c. reference frequency signal signals and acts to produce an output signal having a d.c. component which varies in dependence on a relationship between the frequencies of the two input signals.
10. Circuit arrangement as defined in claim 9 wherein said third converter is connected to said reference frequency source for producing an output signal having a d.c. component proportional to the reference frequency and constituting said reference signal.
11. Circuit arrangement as defined in claim 9 wherein said converter of said at least one loop produces an output signal which changes only when there is a change in the frequency relationship of the two a.c. input signals and in proportion to this relationship.
12. Circuit arrangement as defined in claim 11 wherein said converter of said at least one loop operates to reverse the frequency relationship to which the change in the direct component of the output signal is proportional when the connections of the input signals to the two inputs of said converter are interchanged.
13. Circuit arrangement as defined in claim 9 wherein said converter of said at least one loop has a further input connected to receive a further a.c. input signal for further controlling the d.c. component of the output signal of said converter as a function of the frequency of the further input signal.
14. Circuit arrangement as defined in claim 9 wherein variation in the d.c. component of the output signal of said converter of said at least one loop is proportional to changes in the duty ratio of at least one of its input signals.
15. Circuit arrangement as defined in claim 9 wherein the d.c. component of the output of said converter of said at least one loop varies according to the relationship V=K1 +K2.f1 /f2, where V is the value of the d.c. component, K1 and K2 are constants, f1 is the frequency of the output of its respective oscillator and f2 is the frequency of the output of said reference frequency source.
16. Circuit arrangement as defined in claim 2 wherein all of said converters are structurally and functionally identical.
17. Circuit arrangement as defined in claim 2 or 16 wherein said controllable reactances of said input circuit and said sampling oscillator are constituted such that the values of said reactances vary in a constant ratio to one another in response to changes in the value of said second control signal.
18. Circuit arrangement as defined in claim 17 wherein said controllable reactances of said input circuit and said sampling oscillator are identical in their design and response characteristics.
19. Circuit arrangement as defined in claim 18 further comprising a single semiconductor chip presenting two identically constructed semiconductor varactor diodes, and wherein each said diode constitutes a respective one of said controllable reactances.
20. Circuit arrangement as defined in claim 19 wherein the capacitances of said two diodes bear a constant ratio to one another and further comprising two capacitors each connected in parallel with a respective diode, the values of the capacitances of said capacitors being in said constant ratio to one another.
21. Circuit arrangement as defined in claim 18 wherein said controllable reactances present controllable capacitances having capacitance values which bear a constant ratio to one another and further comprising two capacitors each connected in parallel with a respective controllable capacitance, the values of the capacitances of said capacitors being in said constant ratio to one another.
22. Circuit arrangement as defined in claim 17 wherein said controllable reactances present controllable capacitances having capacitance values which bear a constant ratio to one another and further comprising two capacitors each connected in parallel with a respective controllable capacitance, the values of the capacitances of said capacitors being in said constant ratio to one another.
23. Circuit arrangement as defined in claim 17 further comprising a single semiconductor chip presenting two identically constructed semiconductor varactor diodes, and wherein each said diode constitutes a respective one of said controllable reactances.
24. Circuit arrangement as defined in claim 2 or 16 wherein said controllable reactances of said input circuit and said sampling oscillator are identical in their design and response characteristics.
25. Circuit arrangement as defined in claim 2 or 16 further comprising a single semiconductor chip presenting two identically constructed semiconductor varactor diodes, and wherein each said diode constitutes a respective one of said controllable reactances.
26. Circuit arrangement as defined in claim 2 or 16 wherein said controllable reactances present controllable reactances present controllable capacitances having capacitance values which bear a constant ratio to one another and further comprising two capacitors each connected in parallel with a respective controllable capacitance, the values of the capacitances of said capacitors being in said constant ratio to one another.
Description:
BACKGROUND OF THE INVENTION It is known that frequency synchronism must exist between the oscillator and the input circuit of a superheterodyne receiver.
In order to attain the required synchronism between oscillator and input circuit, various techniques are employed. For example, it can be attempted to achieve the desired synchronism by specially cutting the discs of the rotary tuning capacitor. However, for electronic tuning systems varactor diodes which have specially adapted capacitance/voltage characteristics are not available. For this reason, tuning systems with varactor diodes employ the known threepoint tracking which, however, permits optimum tracking, or synchronization only at three points of the frequency range. Even with precisely identical characteristics of the tuning elements or diodes, there occur synchronization deviations which result in sensitivity breaks within the tuning range. Moreover, inequality of the characteristics and deviations in the capacitance value of the padding capacitor produce additional deviations and thus increase the problem.
SUMMARY OF THE INVENTION
Objects of the present invention are to provide improved synchronization compared to the known tracking circuits and to eliminate the deviations which, when three-point synchronization is employed, inherently occur in such known circuits across the tuning frequency band.
This and other objects are achieved, according to the present invention, by the provision, in or for a superheterod
yne signal receiver including an input circuit arranged to be tuned to a frequency to be received and including a signal controllable variable reactance element presenting a reactance whose value is adjusted by a tuning signal and determines the frequency to which the input circuit is tuned, and a controllable local oscillator producing an alternating signal to be mixed with a received signal to produce an intermediate frequency received signal, of a tracking circuit composed of: a first frequency control circuit including the local oscillator; a second frequency control circuit including a controllable sampling oscillator and means connected to respond to the frequency of the output from the sampling oscillator to derive a signal related thereto and supplying that signal, as the tuning signal, to the controllable element; and control signal generating means generating first and second control signals and connected for supplying the first control signal to the first frequency control circuit for adjusting the frequency of the signal produced by the local oscillator, and for supplying the second control signal to the second frequency control circuit for adjusting the value of the tuning signal to tune the input circuit to a selected frequency, the control signal generating means maintaining a relationship between the first and second control signals such that the output frequency of the local oscillator is adjusted to the value corresponding to the received signal frequency to which the input circuit is tuned.
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