The CHASSIS D16 from PHILIPS is his most sophisticated and complex type.
It employs the DIGIVISION ITT DIGIT2000 Technology even when PHILIPS has developed his own 100HZ digital technology.
This is a great example of the Extreme flexibilty of the research & development of PHILIPS which was basically completely free to develop and design chassis technology without marketing obligations or any type of blocking circumstances in any field or aspect design.
The CHASSIS PHILIPS D16 Is a semi modular type and it has additional horizontal board for further device like audio processing and I/O selection / expansion including a D2B Bus connection feature.
Here described the functions featured:
D2B Bus :Domestic Digital Bus (D2B) SMARTwireX: D2B is an optical data bus system that was developed to connect audio, video, computer, and telephone components in a single ring structure within a vehicle. SMARTwireX defines a physical layer supporting the D2B networks running up to 25 Mb/sec and featuring automotive compatibility. It is an electrical physical solution for automotive networks.
The present invention D2B Bus :Domestic Digital Bus (D2B) SMARTwireX relates to a communication protocol for use in communication among AV (audio-video) equipments, communication among computers and communication among AV equipments and computers, for example.It is customary that the AV system is formed of a plurality of AV equipments, such as a TV (television receiver), an MDP (multi-media player), a VTR (video tape recorder), an AV center (switcher) or the like.
In the AV system, a plurality of AV equipments, such as TV, MDP, VTR and AV center, are connected together by means of video signal lines, audio signal lines and control signal lines (control buses). A variety of control signals and data (e.g., packets of predetermined formats) are supplied to the AV equipments via the control buses, whereby the respective AV equipments are operated in a ganged fashion.
Specifically, according to the AV system, when a play button of the VTR is operated, a packet is output to the TV and the AV center from the VTR, whereby the TV and the AV center are powered. Further, the AV center is switched such that the VTR and the TV are connected together, and image and sound reproduced by the VTR are output from the VTR.
The packets are communicated in the following procedure:
(T1) Routing information transmission
(T2) Command (CMD) transmission
(T3) Request (REQ) transmission
(T4) Get answer (GET-ANS) transmission.fwdarw.answer (ANS) reception
(T5) End (END) transmission
Initially, an AV equipment which transmits a packet first is set to "master apparatus" and an AV equipment which receives such packet is set to "slave apparatus". Routing information is transmitted from the master apparatus to the slave apparatus (T1). At that time, the slave apparatus is locked so that it is inhibited from receiving a packet transmitted from other AV equipment.
Then, a command (CMD) which turns on the power supply is transmitted from the master apparatus to the slave apparatus (T2). A request (REQ) which solicits the processing of the command is further transmitted from the master apparatus to the slave apparatus (T3).
Then, in order to obtain an answer (ANS) for REQ, the get answer (GET-ANS) is transmitted from the master apparatus to the slave apparatus (T4). The GET-ANS is repeatedly transmitted until the answer ANS is obtained from the slave apparatus. When the answer (ANS) is obtained from the slave apparatus, an end (END) representing the end of the processing is transmitted (T5). At that time, the slave apparatus which is set in the locked state is set in the unlock state. Therefore, the slave apparatus is set in a state that it can again receive a packet transmitted from the AV equipment.
As described above, the packet exchange procedure in the conventional AV system is cumbersome.
Since the GET-ANS is repeatedly transmitted until the answer ANS is obtained from the slave apparatus, the traffic on the control bus is increased. Furthermore, it is frequently observed that other AV equipments cannot use the control bus. There is then the problem that the overall processing speed of the system is lowered.When a packet is transmitted from the master apparatus to the slave apparatus, for example, the CMD transmission and the REQ transmission, the communication mode of the master apparatus is set in the master communication mode, and the communication mode of the slave apparatus is set in the slave reception mode. If on the other hand a packet is expected to be transmitted from the slave apparatus to the master apparatus, such as when the master apparatus does not receive the answer (ANS) from the slave apparatus, and therefore issues the GET-ANS, the communication mode of the master apparatus is set in the master reception mode and the communication mode of the slave apparatus is set in the slave transmission mode.
As described above, there are four communication modes such as the master transmission mode, the master reception mode, the slave transmission mode and the slave reception mode. Therefore, each AV equipment must exchange a packet by switching the four modes and a communication efficiency is low.
Further, each AV equipment needs four buffers including a master transmission buffer for latching a packet transmitted in the master transmission mode, a master reception buffer for latching a packet received in the master reception mode, a slave transmission buffer for latching a packet transmitted in the slave transmission mode and a slave reception buffer for latching a packet received in the slave reception mode. There is then the problem that the apparatus becomes large in size and expensive.
Furthermore, since the reception side cannot recognize a transmission error, there is then the problem that an error recovery processing required when a transmission error occurs becomes complex.
In addition, date of 3 frames must be transmitted at minimum in order to transmit pure data, e.g., OSD data. There is then the problem that a lot of time must be prepared and that the processing becomes complex.
SUMMARY OF THE INVENTION
In view of the aforesaid aspect, an object of the present invention is to provide a communication protocol for communicating data in which a communication can be efficiently made by a simple procedure.
According to a first aspect of the present invention, there is provided a communication protocol for communicating data by a serial format which is comprised of a command packet informing an operation command, a status request packet informing a status request of some apparatus, a data request packet informing a data request to some apparatus, a datum packet informing data, an answer packet informing answer datum for previous request, an automatic status sending packet informing a status of an apparatus, and a simulcast packet informing simulcast datum for a plurality of apparatus.
According to a second aspect of the present invention, there is provided a communication system for communicating data which is comprised of a command packet communicating member for communicating a command packet, a status request packet communicating member for communicating a status request packet. a data request packet communicating member for communicating a data request packet, a datum packet communicating member for communicating a datum packet, an answer packet communicating member for communicating an answer packet, an automatic status sending packet communicating member for communicating an automatic status sending packet, and a simulcast packet communicating member for communicating a simulcast packet.
In accordance with a third aspect of the present invention, there is provided a communication system for communicating data which is comprised of a master apparatus which comprises a command packet communicating member for communicating a command packet, a status request communicating member for communicating a status request packet, a data request packet communicating member for communicating a data request packet, a datum packet communicating member for communicating a datum packet, an answer packet communicating member for communicating an answer packet, an automatic status packet communicating member for communicating an automatic status sending packet, and a simulcast packet communicating member for communicating a simulcast packet, and a slave apparatus which comprises a command packet communicating member for communicating a command packet, a status request packet communicating member for communicating a status request packet, a data request packet communicating member for communicating a data request packet, a datum packet communicating member for communicating a datum packet, an answer packet communicating member for communicating an answer packet, an automatic status sending packet communicating member for communicating an automatic status sending packet, and a simulcast packet communicating member for communicating a simulcast packet.
The D16 Has even PIP functions but this section is SIEMENS Chipset based.
The idea of digitization of TV functions is not new. The time some companies have started to work on it, silicon technology was not really adequate for the needed computing power so that the most effective solutions were full custom designs. This forced the block-oriented architecture where the digital functions introduced were the one to one replacement of an existing analog function. In Figure 2 there is a simplified representation of the general concept.
Fig.2: Block Diagram of first generation digital TV set
The natural separation of video and audio resulted in some incompatibilities and duplication of primary functions. The emitting principle is not changed, redundancy is a big handicap, for example the time a SECAM channel is running, the PAL functions are not in operation. New generations of digital TV systems should re-think the whole concept top down before VLSI system partitioning.
In today’s state-of-the-art solution one can recognize all the basic functions of the analog TV set with, however, a modularity in the concept, permitting additional features becomes possible, some special digital possibilities are exploited, e.g. storage and filtering techniques to improve signal reproduction (adaptive filtering, 100 Hz technology), to integrate special functions (picture-in-picture, zoom, still picture) or to receive digital broadcasting standards (MAC, NICAM). The Figure 3 shows the ITT Semiconductors solution which was the first on the market in 1983 !! !!
Fig.3: The DIGIT2000 TV receiver block diagram
Description:
This invention relates generally to digital television receivers and, particularly, to digital television receivers arranged for economical interfacing with a plurality of auxiliary devices.
With the proliferation of low cost microprocessors and microprocessor controlled devices, television (TV) receivers are being designed to utilize digitized signals and controls. There are many advantages associated with digital TV receivers, including uniformity of product, precise control of signal parameters and operating conditions, elimination of mechanical switches and a potential for reliability that has been heretofore unknown. Digital television receivers include a high speed communication bus for interconnecting a central control unit microprocessor (CCU) with various TV function modules for processing a TV signal. These modules include a deflection processing unit (DPU), a video processing unit (VPU), an automatic phase control (APC), a video codec unit (VCU), an audio analog to digital converter (ADC) and an audio processing unit (APU). The CCU has associated with it a non-volatile memory, a hardware-generated clock signal source and a suitable interface circuit for enabling the CCU to control processing of the TV signal throughout the various TV function modules. The received TV signal is in analog form and suitable analog to digital (A/D) converters and digital to analog (D/A) converters are provided for converting the digital and analog signals for signal processing and for reconverting them after processing for driving a cathode ray tube (CRT) and suitable speakers. The CCU microprocessor is heavily burdened because of the high speed timing required to control the various TV function modules. To further complicate matters, modern TV receivers are increasingly being used with auxiliary devices for other than simple processing of TV signals. For example, the video cassette recorder (VCR) has enabled so-called "time-shifting" of program material by recording TV signals for later, more convenient viewing. The VCR is also extensively used with prerecorded material and with programs produced by users having access to a video camera. Other auxiliary devices providing features such as "Space Phone" whereby the user is enabled to make and receive telephone calls through his TV receiver, are desirable options. Additionally, a source selector auxiliary device enables a host of different signal sources, such as cable, over-the-air antenna, video disk, video games, etc. to be connected for use with the signal processing circuitry of the TV. In addition, all of these many auxiliary devices are preferably controllable from a remote position. A great deal of flexibility is available since each of the above auxiliary devices includes a microprocessor for internally controlling functioning of the device.
In the digital TV system described, the CCU microprocessor and the microprocessors in the auxiliary devices may be conventionally arranged to communicate over the main communication bus. Such a system would entail a specialized microprocessor with a hardware-generated clock signal in each auxiliary device in order to communicate at the high speeds used on the main communication bus. A specialized microprocessor, that is, one that is hardware configured, is significantly more expensive than an off-the-shelf microprocessor. Also, the auxiliary devices may not be required, or even desired, by all users and their low volume production cost becomes very important. It would therefore be desirable to provide a digital TV in which such auxiliary devices utilized off-the-shelf microprocessors for their control.
A digital TV system includes a CCU that is interconnected by a three-wire, high speed bus to a plurality of TV signal function modules for controlling operation thereof by means of a high speed hardware generated clock signal. A software generated clock signal in the CCU is supplied on a low speed two-wire auxiliary device bus which is connected to microprocessors in a plurality of auxiliary devices for performing functions ancillary to TV signal processing. The microprocessor in each auxiliary device is an off-the-shelf type that does not require any special hardware because the timing on the auxiliary device bus is sufficiently slow to enable software monitoring of the line and data transfer.
As mentioned, the three-wire IM bus 21 is a high speed bidirectional bus in which CCU 20 functions as the master and all of the interconnected TV signal processing function modules are slaves that communicate with the CCU in accordance with the protocol established for the system. CCU 20 is also indicated as including a software generated clock which supplies a two-wire auxiliary device bus 50. Two-wire bus 50 includes a clock lead 51 and a data lead 52 coupled to a plurality of auxiliary devices. A VCR 54, including an off-the-shelf microprocessor 55, is coupled to bus 50. A Source Selector 56, including an off-the-shelf microprocessor 57, is also coupled to bus 50. Source Selector 56 has access to four RF inputs, two baseband video and audio inputs and one separate baseband audio input. It will be appreciated that Source Selector 56 may have a greater or lesser number of signal sources to which it has access. Source Selector 56 outputs are coupled to VCR 54 and also to tuner 10 and supply, under control of CCU 20 and keyboard 44, the signal from the signal source selected by keyboard 44 or IR transmitter 46 for use with the digital TV. Auxiliary device bus 50 is also coupled to a Space Phone 58 which includes an off-the-shelf microprocessor 59 and a modem 60 that is connectable to a conventional telephone terminal.
Two-wire auxiliary device bus 50 is a relatively low speed bus and there is no need for separate hardware generated clock signals to be developed by the auxiliary device microprocessors. As mentioned above, this feature involves a significant savings in the cost and complexity of the auxiliary devices.
The protocol used on the two-wire auxiliary device bus consists of a 16 bit sequence, the first eight bits of which are used for bus address commands for the auxiliary devices. Each auxiliary device may respond to 16 addresses which allows the CCU to write into or read from various storage registers in the devices which are used for control or data storage. Thus, with this low cost system, as many as 16 auxiliary devices may be connected to the auxiliary device bus. The second eight bits of the 16 bit sequence contain data which is either transferred from the CCU to the auxiliary device addressed, or transferred from the auxiliary device to the CCU, based upon the bus address used. Thus, the various bus addresses to which a given auxiliary device will respond determine whether the auxiliary device will receive data from the CCU or send data to the CCU. The clock line timing, generated by software in CCU 20, is slow enough to permit software monitoring of the line and data reception by simple auxiliary device microprocessors that are not equipped with an external interrupt feature. The timing on the auxiliary device bus is made sufficiently fast to avoid too many instruction steps or the need for special registers in CCU 20. In the system described, data is clocked every 82.5 microseconds, thus permitting a 16 bit word to be clocked in 1.32 milliseconds. A pause of 277.5 microseconds between the first 8 bits and the second 8 bits permits the slave auxiliary device to process the bus address data contained in the first 8 bits. This timing fits into the 2 millisecond timing block structure used for the CCU in controlling the DIGIT 2000 digital TV. Two-2 millisecond timing blocks have been established in the CCU, which has a 20 millisecond timing loop divided into ten-2 millisecond timing blocks. Thus, two control words may be sent to an auxiliary device every 20 milliseconds, or a request by the CCU to receive data and the actual receipt of that data may take place in that time period.
Referring to the drawing, a digital TV includes a tuner 10 coupled to an IF/Detector 12 which has a pair of outputs 13 and 14 supplying video and audio signals, respectively. Control signals for tuner 10 are supplied through an interface circuit 16 from a CCU microprocessor 20 which functions as a single master control unit for the system. Microprocessor 20 is interconnected by means of a bidirectional three-wire IM (Intermetal) bus 21 to a DPU 22, a VPU 26, an APC 30, a TTX (teletext processor) 38, an APU 36, an ADC 32 and a non-volatile memory 24. A serial control line 29 interconnects a hardware generated clock 28, VPU 26 and VCU 34. VPU 26 and VCU 34 are also interconnected by a seven wire cable and TTX 38 is interconnected with a DRAM 42. DRAM 42 is a dynamic RAM in which TTX information is stored for display. VCU 34 is supplied with video signal and supplies a digitized 7 bit grey coded video signal to VPU 24 for processing and RGB color signals to a Video Drive 40 which, in turn, supplies a cathode ray tube (not shown). A keyboard 44 is coupled to CCU 20 and includes an IR detector that is responsive to coded IR signals supplied from an IR transmitter (IRX) 46. A resident microprocessor in keyboard 44 decodes the received IR signals and generated control commands and supplies appropriate outputs to CCU 20. The diagram, as described, is substantially identical to that for a "DIGIT" 2000 VLSI Digital TV System developed by ITT Intermetal and published in Edition 1984/85 Order No. 6250-11-2E
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By its very nature, computer technology is digital, while consumer electronics are geared to the analog world. Starts have been made only recently to digitize TV and radio broadcasts at the transmitter end (in form of DAB, DSR, D2-MAC, NICAM etc). The most difficult technical tasks involved in the integration of different media are interface matching and data compression [5].
After this second step in the integration of multimedia signals, an attempt was made towards standardization, namely, the integration of 16 identical high speed processors with communication and programmability concepts comprised in the architecture !
Many solutions proposed today (for MPEG 1 mainly) are derived from microprocessor architectures or DSPs, but there is a gap between today’s circuits and the functions needed for a real fully HDTV system. The AT&T hybrid codec [29], for instance, introduces a new way to design multimedia chips by optimizing the cost of the equipment considering both processing and memory requirements.
The concept is to provide generic architectures that can be applied to a wide variety of systems taking into account that certain functions have to be optimized and that some other complex algorithms have to be ported to generic processors.
Basics of current video coding standards
Compression methods take advantage of both data redundancy and the non-linearity of human vision. They exploit correlation in space for still images and in both space and time for video signals. Compression in space is known as intra-frame compression, while compression in time is called inter-frame compression. Generally, methods that achieve high compression ratios (10:1 to 50:1 for still images and 50:1 to 200:1 for video) use data approximations which lead to a reconstructed image not identical to the original.
Methods that cause no loss of data do exist, but their compression ratios are lower (no better than 3:1). Such techniques are used only in sensitive applications such as medical imaging. For example, artifacts introduced by a lossy algorithm into a X-ray radiograph may cause an incorrect interpretation and alter the diagnosis of a medical condition. Conversely, for commercial, industrial and consumer applications, lossy algorithms are preferred because they save storage and communication bandwidth.
Lossy algorithms also generally exploit aspects of the human visual system. For instance, the eye is much more receptive to fine detail in the luminance (or brightness) signal than in the chrominance (or color) signals. Consequently, the luminance signal is usually sampled at a higher spatial resolution. Second, the encoded representation of the luminance signal is assigned more bits (a higher dynamic) than are the chrominance signals. The eye is less sensitive to energy with high spatial frequency than with low spatial frequency [7]. Indeed, if the images on a personal computer monitor were formed by an alternating spatial signal of black and white, the human viewer would see a uniform gray instead of the alternating checkerboard pattern. This deficiency is exploited by coding the high frequency coefficients with fewer bits and the low frequency coefficients with more bits.
All these techniques add up to powerful compression algorithms. In many subjective tests, reconstructed images that were encoded with a 20:1 compression ratio are hard to distinguish from the original. Video data, even after compression at ratios of 100:1, can be decompressed with close to analog videotape quality.
Lack of open standards could slow the growth of this technology and its applications. That is why several digital video standards have been proposed:
- JPEG (Joint Photographic Expert Group) for still pictures coding
- H.261 at p times 64 kbit/s was proposed by the CCITT (Consultative Committee on International Telephony and Telegraphy) for teleconferencing
- MPEG-1 (Motion Picture Expert Group) up to 1,5 Mbit/s was proposed for full motion compression on digital storage media
- MPEG-2 was proposed for digital TV compression, the bandwith depends on the chosen level and profile [33].
Another standard, the MPEG-4 for very low bit rate coding (4 kbit/s up to 64 kbit/s) is currently being debated.
Digitalization of the fundamental TV functions is of great interest since more than 30 years. Several million of TV sets have been produced containing digital systems. However, the real and full digital system is for the future. A lot of work is done in this field today, the considerations are more technical than economical which is a normal situation for an emerging technology. The success of this new multimedia technology will be given by the applications running with this techniques.
The needed technologies and methodologies were discussed to emphasize the main parameters influencing the design of VLSI chips for Digital TV Applications like parallelization, electrical constraints, power management, scalability and so on...............................
Sound Processing Overview Description
The stereo pilot carrier is selectively decoupled from soundchannel TV ll and fed separately to Pin 8 for recognition of the
station operating mode.
The digitized output signals are then available as pulse-rate-
modulated signals PDM I and PDM ll at Pins 10 and 11. Digital
signal processing is then performed completely in APU 2470,
the audio processor IC 3201, to which of course all control
functions controlled via the IM Bus belong. At IC outputs 22 and
23, the processed signals are outputted as pulse-width-
modulated information, so that they can be reconverted into
their original analog form by simple integration (RC element).
The downstream lC’s TDA 2040 H (3401/3501) supply power
amplification for feed to the loudspeakers. A second pair of
analog outputs, Pins 19, 20 ofthe APU, followed by an
integrated amplifier stage, IC 3301 , TDA 2822 M, serves for
connection of earphones or a stereo system via cinch sockets.
This output is likewise controllable, and also suitable for the
listening to the alternative sound channel in dual-channel sound
mode. Pins 21 and 24 at ADC 2310 E are available for coupling
a second dual-channel analog sound source. The signals
concerned come from the SCART socket (PPT), and in sets with
picture-in-picture function are passed via the PIP decoder. In
the opposite direction, the ADC 2310 E supplies at Pins 22 and
23 analog output signals to the SCART socket, e.g. as required
for recording audio signals. All switch-over functions necessary
in this area are executed inside the IC and controlled via the IM
Bus. Detection of the station transmission mode (mono, stereo,
dual-sound) is performed in the lC’s in exactly the same way asthe corresponding switch-over to the operating mode being
transmitted. A muting stage in each of the two audio channels
(T 3401 and T 3501) provides an audio muting function by short-
circuiting the signal input Pin 1 at the power output stage lC’s.
This function can be controlled in two different ways:
1. Via ST 33 at the moment when the set is switched on, in
order to suppress the switch-on click.
2. From Pin 16 of ADC 2310 E, e.g. for noise suppression,
when no TV signal is being received.
ln the first case, the L signal, which is passed as a switch-on
signal from Pin 5 of the CCU via R 1505 to ST 33 of Stereo
Module B, and thus via R 3511 to the base of T 3510, will switch
the transistor to on-state and thus connect the muting line to
12 V. Since in this case the two switching transistors T 4301 and
T 3501 also become conducting, the signal inputs to the audio
output stages are then short-circuited. The second muting
branch from Pin 16 of ADC 2310 E is software-controlled, and
receives the switch-off information from the CCU via the IM
Bus.
PHILIPS DIGI 16 SWITCH MODE (SOPS) POWER SUPPLY DESCRIPTION:
Switched-mode self oscillating supply voltage circuit:
POWER SUPPLY (SOPS - Self Oscillating Power Supply)
A switched-mode self-oscillating supply voltage circuit for converting an input voltage into an output d.c. voltage which is substantially independent of variations of the input voltage and/or a load connected to the output voltage. The circuit comprises a first controllable switch connected in series with a transformer winding and a second controllable switch for turning-off the first switch. The conduction period of the first switch is controlled by means of a control voltage present on a control electrode of the second switch. The circuit can be switched-over to a stand-up state in which the energy supplied to the load is reduced to zero. A starting network is connected between the input voltage and the second switch so that the current therein flows through the second switch during the period of time this switch conducts and does not flow to the control electode of the first switch in the stand-by state.
1. A switched-mode self-oscillating supply voltage circuit for converting an input voltage into an output d.c. voltage which is substantially independent of variations of the input voltage and/or of a load connected to the terminals of the output voltage, comprising a transformer having a primary and a feedback winding, a first controllable switch connected in series with the primary winding, the series arrangement thus formed being coupled between terminals for the input voltage, a second controllable switch coupled via a turn-off capacitor to the control electrode of the first switch to turn it off, means coupling the feedback winding to said control electrode, a transformer winding being coupled via a rectifier to an output capacitor having terminals which supply the output voltage, an output voltage-dependent control voltage being present on a control electrode of the second switch for controlling the conduction period of the first switch, the circuit being switchable between an operating state and a stand-by state in which relative to the operating state the supply energy supplied to the load is considerably reduced, a starting network connected to a terminal for the input voltage, means for adjusting the control voltage in the stand-by state to a value at which the first controllable switch is cut-off, a connection which carries current during the conduction period for the second controllable switch being provided between the starting network and said second switch, and means providing a connection between the starting network and the control electrode of the first switch, which connection does not carry current in the stand-by state.
2. A supply voltage circuit as claimed in claim 1, further comprising a resistor included between the connection of the starting network to the second switch and a turn-off capacitor present in the connection to the control electrode of the first switch.
3. A supply voltage circuit as claimed in claim 2, characterized in that the second controllable switch comprises a thyristor having a main current path included in the control electrode connection of the first controllable switch, said thyristor having a first control gate electrode for adjusting the turn-off instant of the first switch and a second control electrode to which the starting network and the resistor are connected.
4. A supply voltage circuit as claimed in claim 1, characterized in that a resistor is included in the connection to the control electrode of the second controllable switch so that a current flows through said resistor in the stand-by state of a value sufficient to cut-off the first controllable switch.
Description:
The invention relates to a switched-mode self-oscillating supply voltage circuit for converting an input voltage into an output d.c. voltage which is substantially independent of variations of the input voltage and/or of a load connected to the terminals of the output voltage. This circuit comprises a transformer having a primary and a feedback winding and a first controllable switch arranged in series with the primary winding. The series arrangement thus formed is coupled between the terminals of the input voltage. A second controllable switch which is coupled via a turnoff capacitor to the control electrode of the first switch to turn it off. The feedback winding is coupled to this control electrode and the primary winding is coupled via a rectifier to an output capacitor the terminals of which are the terminals for the output voltage. An output voltage-dependent control voltage is present on a control electrode of the second switch for controlling the conduction period of the first switch. The circuit is switchable between an operating state and a stand-by state in which relative to the operating state the energy supplied to the load is considerably reduced, and the circuit further comprises a starting network connected to a terminal for the input voltage. Such a supply voltage circuit is disclosed in German Patent Application No. 2,651,196. With this prior art circuit supply energy can be applied in the operating state to the different portions of a television receiver. In the stand-by state the majority of the output voltages of the circuit are so low that the receiver is substantially in the switched-off condition. In the prior art circuit the starting network is formed by a resistor connected to the unstabilized input voltage and through which on turn-on of the circuit a current flows via the feedback winding to the control electrode of the first controllable switch, which is a switching transistor, and brings it to and maintains it in the conductive state, as a result of which the circuit can start.
The invention has for its object to provide an improved circuit of the same type in which in the stand-by state the supply energy applied to the load is reduced to zero. The prior art circuit cannot be improved in this respect without the use of mechanical switches, for example relays. According to the invention, the switched-mode self-oscillating supply voltage circuit does not comprise such relays and is characterized in that it further comprises means for adjusting the control voltage in the stand-by state to a value at which the first controllable switch is cut-off. A connection which carries current during the conduction period of the second controllable switch is provided between the starting network and said second switch while a connection present between the starting network and the control electrode of the first switch does not carry current in the stand-by state.
The invention is based on the recognition that the prior art supply voltage circuit cannot oscillate, so that the energy supplied by it is zero, if the control voltage obtains a value as referred to, while the starting network is connected in such a manner that in the stand-by state no current can flow through it to the control electrode of the first controllable switch.
It should be noted that in the said German Patent Application the starting network is in the form of a resistor which is connected to an unstabilized input d.c. voltage. It is, however, known, for example, from German Patent Specification No. 2,417,628 to employ for this purpose a rectifier network connected to an a.c. voltage from which the said input d.c. voltage is derived by rectification.
The invention will now be further described by way of example with reference to the accompanying drawing, which shows a basic circuit diagram of a switched-mode self-oscillating supply voltage circuit.
The self-oscillating supply circuit shown in the FIGURE comprises a npn-switching transistor Tr1 having its collector connected to the primary winding L1 of a transformer T, while the emitter is connected to ground via a small resistor R1, for example 1.5 Ohm. Resistor R1 is decoupled for the high frequencies by means of a 150 nF capacitor C1. One end of winding L1 is connected to a conductor which carries an unstabilized input d.c. voltage V B of, for example, 300 V. Voltage V B has a negative rail connected to ground and is derived from the electric power supply by rectification. One end of a feedback winding L2 is connected to the base of transistor Tr1 via the parallel arrangement of a small inductance L3 and a damping resistor R2. A terminal of a 47 μF capacitor C2 is connected to the junction of the elements L2, L3 and R2. The series arrangement of a diode D1 and a 2.2 Ohm-limiting resistor R3 is arranged between the other terminal of capacitor C2 and the other end of winding L2 and the series arrangement of a resistor R4 of 12 Ohm and a diode D2 is arranged between the same end of winding L2 and the emitter of transistor Tr1. A 150 nF capacitor C3 is connected in parallel with diode D2. The anode of diode D1 is connected to that end of winding L2 which is not connected to capacitor C2, while the anode of diode D2 is connected to the emitter of transistor Tr1. In the FIGURE the winding sense of windings L1 and L2 is indicated by means of dots.
The junction of capacitor C2 and resistor R3 is connected to a 100 Ohm resistor R5 and to the emitter of a pnp-transistor Tr2. The base of transistor Tr2 is connected to the other terminal of resistor R5 and to the collector of an npn-transistor Tr3, whose emitter is connected to ground. The base of Tr3 is connected to the collector of transistor Tr2. Transistors Tr2 and Tr3 form an artificial thyristor, i.e. a controllable diode whose anode is the emitter of transistor Tr2 while the cathode is the emitter of transistor Tr3. The base of transistor Tr2 is the anode gate and the base of transistor Tr3 is the cathode gate of the thyristor formed. Between the last-mentioned base and the emitter of transistor Tr1 there is arranged the series network of a 2.2 kOhm resistor R6 with the parallel arrangement of a 2.2 kOhm resistor R7 and a 100 μF capacitor C4. The series arrangement of a diode D11 and a 220 Ohm limiting resistor R19 is arranged between the junction of components R6, R7 and C4 and the junction of components C2, L2, R2 and L3. The cathode of diode D11 is connected to capacitor C2.
Because of the feedback the described circuit oscillates independently as soon as the steady state is achieved. It will be described hereinafter how this state is obtained. During the time transistor Tr1 conducts the current flowing through the resistor R1 increases linearly. The resistor R4 then partly determines the base current of transistor Tr1. Capacitor C4 and resistor R7 form a voltage source the voltage of which is subtracted from the voltage drop across resistor R1. As soon as the voltage on the base of transistor Tr3 is equal to approximately 0.7 V this transistor becomes conductive, as a result of which the thyristor formed by transistors Tr2 and Tr3 becomes rapidly conductive and remains so. Across capacitor C2 there is a negative voltage by means of which transistor Tr1 is turned off. The inverse base current thereof flows through thyristor Tr2, Tr3. This causes charge to be withdrawn from capacitor C2, while the charge carriers stored in transistor Tr1 are removed with the aid of inductance L3. As soon as the collector current of transistor Tr1 has been turned off, the voltage across winding L2 reverses its polarity, which current recharges the capacitor. Now the voltage at the junction of components C2, R3 and R5 is negative, causing thyristor Tr2, Tr3 to extinguish. Secondary windings L4, L5 and L6 are provided on the core of transformer T with the indicated winding senses. When transistor Tr1 is turned off, a current which recharges a smoothing capacitor C5, C6 or C7 via a rectifier D3, D4 or D5 flows through each of these windings. The voltages across these capacitors are the output voltages of the supply circuit for loads connectable thereto. These loads, which are not shown in the FIGURE, are, for example, portions of a television receiver.
In parallel with winding L1 there is the series network of a 2.2 nF tuning capacitor C8 and a 100 Ohm limiting resistor R8. The anode of a diode D6 is connected to the junction of components R8 and C8, while the cathode is connected to the other terminal of resistor R8. Winding L1 and capacitor C8 form a resonant circuit across which an oscillation is produced after windings L4, L5 and L6 have become currentless. At a later instant the current through circuit L1, C8 reverses its direction. As a result thereof a current is generated in winding L2 which flows via diode D2 and resistor R4 to the base of transistor Tr1 and makes this transistor conductive and maintains it in this state. The dissipation in resistor R8 is reduced by means of diode D6. A clamping network formed by the parallel arrangement of a 22 kOhm resistor R9 and a 120 nF capacitor C9 is arranged in series with a diode D7. This whole assembly is in parallel with winding L1 and cuts-off parasitic oscillations which would be produced during the period of time in which transistor Tr1 is non-conductive. The output voltages of the supply circuit are kept substantially constant in spite of variations of voltage V B and/or the loads, thanks to a control of the turning-on instant of thyrisistor Tr2, Tr3. For this purpose the emitter of a light-sensitive transistor Tr4 is connected to the base of transistor Tr3. The collector of transistor Tr4 is connected via a resistor R10 to the conductor which carries the voltage V B and to a Zener diode Z1 which has a positive voltage of approximately 7.5 V, while the base is unconnected. The other end of diode Z1 is connected to ground. A light-emitting diode D8, whose cathode is connected to the collector of an npn-transistor Tr5, is optically coupled to transistor Tr4. By means of a potentiometer R11 the base of transistor Tr5 can be adjusted to a d.c. voltage which is derived from the voltage V 0 of approximately 130 V across capacitor C6. The anode of diode D8 is connected to a d.c. voltage V 1 of approximately 13 V. A resistor R12 is also connected to voltage V 1 , the other end of the resistor being connected to the emitter of transistor Tr5, to the cathode of a Zener diode Z2 which has a voltage of approximately 7.5 V and to a smoothing capacitor C10. The other ends of diode Z2 and capacitor C10 are connected to ground. Voltage V1 can be generated by means of a transformer connected to the electric AC supply and a rectifier, which are not shown for the sake of simplicity, more specifically for a remote control to which constantly supply energy is always applied, even when the majority of the components of the receiver in what is referred to as the stand-by state are not supplied with supply energy. A portion of voltage V 0 is compared with the voltage of diode Z2 by means of transistor Tr5. The measured difference determines the collector current of transistor Tr5 and consequently the emitter current of transistor Tr4. This emitter current produces across resistor R6 a voltage drop whose polarity is the opposite of the polarity of the voltage source formed by resistor R7 and capacitor C4. Under the influence of this voltage drop the turn-on instant of thyristor Tr2, Tr3 is controlled as a function of voltage V 0 . If, for example, voltage V 0 tends to decrease owing to an increasing load thereon and/or in response to a decrease in voltage V B , then the collector current of transistor Tr5 decreases and consequently also the said voltage drop. Thyristor Tr2, Tr3 is turned on at a later instant than would otherwise be the case, causing transistor Tr1 to be cut-off at a later instant. The final value of the collector current of this transistor is consequently higher. Consequently, the ratio of the time interval in which transistor Tr1 is conductive to the entire period, commonly referred to as the duty cycle, increases, while the frequency decreases.
The circuit is protected from overvoltage. This is ensured by a thyristor which is formed by a pnp-transistor Tr6 and an npn-transistor Tr7. The anode of a diode D9 is connected to the junction of components R3 and C2 and the cathode to the base of transistor Tr6 and to the collector of transistor Tr7. The base of transistor Tr7, which base is connected to the collector of transistor Tr6, is connected via a zener diode Z3 to a voltage which, by means of a potentiometer R13 is adjusted to a value derived from the voltage across capacitor C7. The emitter of transistor Tr6 also is connected to the voltage of capacitor C7, more specifically via a resistor R14 and a diode D10. If this voltage increases to above a predetermined value then thyristor Tr6, Tr7 becomes conductive. Since the emitter of transistor Tr7 is connected to ground, the voltage at its collector becomes very low, as a result of which diode D9 becomes conductive, which keeps transistor Tr1 in the non-conducting state. This situation is maintained as long as thyristor Tr6, Tr7 continues to conduct. This conduction time is predominantly determined by the values of capacitor C7, resistor R14 and a resistor R15 connected between the base and the emitter of transistor Tr6. A thyristor is advantageously used here to render it possible to switch off a large current even with a low level signal and to obtain the required hysteresis.
The supply circuit can be brought into the stand-by state by making an npn-transistor Tr8, which is non-conductive in the operating state, conductive. The emitter of transistor Tr8 is connected to ground while the collector is connected to the collector of transistor Tr5 via a 1.8 kOhm resistor R17. A resistor R18 has one end connected to the base of transistor Tr8 and the other end, either in the operating state to ground, or in the stand-by state to a positive voltage of, for example, 5 V. Transistor Tr8 conducts in response to this voltage. An additional, large current flows through diode D8 and consequently also through transistor Tr4, resulting in thyristor Tr2, Tr3 being made conductive and transistor Tr1 being made non-conductive and maintained so. So to all appearances a large control current is obtained causing the duty cycle to be reduced to zero. A condition for a correct operation is that the emitter current of transistor Tr4 be sufficiently large in all circumstances, which implies that the voltage drop produced across resistor R6 by this current is always higher than the sum of the voltage across voltage source R7, C4, of the base-emitter threshold voltage of transistor Tr3 in the conductive state thereof, and of the voltage at the emitter of transistor Tr1. So the said voltage drop must be higher than the sum of the first two voltages, which corresponds to the worst dimensioning case in which the stand-by state is initiated while transistor Tr1 is in the non-conductive state.
If thyristor Tr2, Tr3 conducts, either in the operating state or in the stand-by state, current flows through resistor R16 via the collector emitter path of transistor Tr3 to ground. This current is too small to have any appreciable influence on the behaviour of the circuit. When thyristor Tr2, Tr3 does not conduct, the voltage on the left hand terminal of capacitor C2 is equal to approximately 1 V, while the voltage across the capacitor is approximately -4 V. So transistor Tr1 remains in the non-conductive state and a premature turn-on thereof cannot occur. If in the operating state transistor Tr1 conducts while thyristor Tr2, Tr3 is cut-off, then the current flows through resistor R16 in the same manner as it flows during the start to the base of transistor Tr1, but has relatively little influence as the base current caused by the energy stored in winding L2 is many times larger. If both transistor Tr1 and thyristor Tr2, Tr3 are non-conductive, then the current through resistor R16 flows through components R5, C2, L2, R4, C3 and R1. In this stand-by state capacitor C2 has indeed substantially no negative charge any longer but, in spite thereof, transistor Tr1 cannot become conductive since no current flows to its base. It will furthermore be noted that the circuit is protected in the event that thyristor Tr2, Tr3 has an interruption. Namely, in such a case the circuit cannot start.
In the foregoing a circuit is described which may be considered to be a switched-mode supply voltage circuit of the parallel ("flyback") type. It will be obvious that the invention may alternatively be used in supply voltage circuits of a different type, for example converters of the type commonly referred to as up-converters. It will also be obvious that transistor Tr1 may be replaced by an equivalent switch, for example a gate-turn-off switch. DEGAUSSING CIRCUIT IN A COLOR TELEVISION RECEIVER:
A degaussing circuit for a color television receiver, in
which the degaussing coil is in series with a PTC thermistor to which an
NTC thermistor is thermally coupled and which is at the same time a
protection resistance for a supply voltage circuit in the receiver.
1. A degaussing circuit for demagnetizing
ferromagnetic components in a colour television receiver, said circuit
comprising a rectifier circuit, the series arrangement of a degaussing
coil and a first thermistor with a positive temperature coefficient,
said series arrangement is connectable to at least one terminal of an
alternating current voltage source, and furthermore comprising a
resistance element means for contributing to heating of the first
thermistor and for protecting said rectifier circuit comprising a second
thermistor with a negative temperature coefficient which is connectable
to a terminal of the alternating current voltage source and which is
thermally coupled to the first thermistor with a positive temperature
coefficient, the second thermistor being connected to said rectifier
circuit in the receiver.
2. A circuit as claimed in claim 1,
wherein said rectifier circuit comprises a rectifier having a current
which also flows through the second thermistor, and the temperature of
the second thermistor in the final operating state exceeds the
temperature of the first thermistor.
3. A circuit as claimed in
claim 2, wherein the second thermistor is connected in series with the
rectifier circuit, the series arrangement thus formed being connected in
parallel with the series arrangement of the degaussing coil and the
first thermistor, and both series arrangements being connectable to the
terminals of the alternating current voltage source.
4. A circuit
as claimed in claim 2, wherein the series arrangement of the degaussing
coil and the first thermistor is connected in parallel with the
rectifier circuit, thereby forming two juctions, one of the junctions
being connectable to a first terminal of the alternating current voltage
source, the other juction being connected to the second thermistor,
said second thermistor being connectable to the second terminal of the
alternating current voltage source.
5. A circuit as claimed in
claim 4, wherein the rectifier circuit comprises the Graetz type and a
supply capacitor, and the product of the total ohmic resistance value of
said parallel circuit in the cold state by the capacitance of said
supply capacitor amounts to approximately 50% of the duration of the
cycle of the voltage supplied by the alternating current voltage source.
6.
A circuit as claimed in claim 2, wherein the second thermistor is
connected in parallel with the series arrangement of the degaussing coil
and the third thermistor, thereby forming a parallel circuit included
in a supply lead of the rectifier, said rectifier comprising a full-wave
rectifier of the type that substantially no direct current component
can flow through said supply lead.
7. A circuit as claimed in
claim 6, wherein the resistance value of the first thermistor in the
cold state is more than 20 times lower than the ohmic resistance value
of the degaussing coil.
8. A circuit as claimed in claim 6,
characterized in that the rectifier circuit is of the Graetz-type and in
that the product of the total ohmic resistance value of the said
parallel circuit in the cold state by the capacitance of a supply
capacitor being part of the rectifier circuit amounts to approximately
50% of the duration of the cycle of the voltage supplied by the a.c.
voltage source.
9. A circuit as claimed in claim 6 wherein the rectifier circuit comprises the Graetz type.
Description:
The
invention relates to a degaussing circuit for demagnetizing
ferromagnetic components in a colour television receiver, comprising the
series arrangement of a degaussing coil and a thermistor with a
positive temperature coefficient, which series arrangement is
connectable to at least one terminal of an a.c. voltage source and
furthermore comprising a resistance element for contributing to heating
of the thermistor.
Such a circuit is known from German Patent
Specification No. 1,282,679. In order to reduce the current which flows
through the degaussing coil at the end of the process, which current
might produce an unwanted magnetic residual field in the ferromagnetic
components to be demagnetized the thermistor is raised by means of a
resistance element already present in the receiver to a higher
temperature than the temperature which would be produced by the final
current alone. For this results in a further increase in the resistance
value of the thermistor.
In practice, in the known circuit a
wire-wound resistor with a high permissible power can be used as
resistance element, which wire-wound resistor is arranged in the
immediate vicinity of the thermistor. However, the drawback of this
measure is that the temperature of the wire-wound resistor cannot be
controlled so very well so that the difference between the maximum
permissible temperature of the thermistor and the ambient temperature
cannot be checked with certainty. Consequently, the risk of overheating,
which may be destructive to the thermistor, is not excluded. For this
reason the circuit is no longer used.
It is an object of the
invention to avoid said drawback of the known circuit whilst also the
costs can be reduced and to that end the circuit according to the
invention is characterized in that the resistance element is a (second)
thermistor with a negative temperature coefficient which is connectable
to a terminal of the a.c. voltage source and which is thermally coupled
to the (first) thermistor with a positive temperature coefficient, the
second thermistor being at the same time a protection resistance for a
rectifier circuit in the receiver.
By means of heat transfer from
the second to the first thermistor the latter attains, as wanted, a
higher temperature. As the current through the second thermistor soon
assumes a value which substantially does not depend on the degaussing
circuit and which cannot exceed a given maximum, an equilibrium
condition is obtained whereafter the temperature cannot increase to an
appreciable extent so that the circuit according to the invention is
safe. It will be noted that degaussing circuits having two thermally
intercoupled thermistors having temperature coefficients of the opposite
sign are known per se. U.S. Pat. No. 3,495,136 discloses a circuit
which includes such a combination. The publication "IEEE Transactions on
Broadcast and Television Receivers" Vol. BTR 1972, No. 1, pages 7 to 9
inclusive describes degaussing circuits in which a thermistor having a
negative temperature coefficient is included in series with a supply
voltage circuit. However, this thermistor is not thermally coupled to a
thermistor having a positive temperature coefficient.
The invention will be further explained by way of non-limitative example with reference to the accompanying figures wherein
FIG. 1 shows a first construction of the circuit according to the invention,
FIG. 2 is a characteristic curve for explaining the invention,
FIG. 3 shows a second construction of the circuit according to the invention,
FIG. 4 shows a third construction of the circuit according to the invention,
FIGS. 5a and 5b are waveforms occurring therein and
FIG. 6 shows a fourth construction of the circuit according to the invention.
In FIG. 1 a degaussing coil 1 of a partly shown colour television receiver having a display tube of the shadow mask type is in series with a thermistor 2. The series arrangement of a second thermistor 7 and a rectifier circuit 8 is in parallel with the series arrangement of coil 1 and thermistor 2. Thermistor 7 has a negative temperature coefficient, whilst thermistor 2 has a positive temperature coefficient. The thermistors are thermally coupled because they have been brought into intimate contact with one another which is indicated in FIG. 1 by means of a double arrow. The parallel circuit constituted by components 1, 2, 7 and 8 can be connected through a switch 6 to the terminals 3 and 4 of an A.C. voltage source 5, for example the electric power supply mains.
Rectifier circuit 8 is diagrammatically shown in FIG. 1 as the series arrangement of a rectifier 9 and the parallel arrangements of a supply capacitor 10 of a high capacitance and a load 11. In operation the rectifier 9, which may consist in known manner of one or more diodes, rectifies the mains voltage of source 5 so that a D.C. voltage is available across capacitor 10 for feeding further parts of the receiver. A direct current flows through these parts. So load 11 represents a resistance whose value is equal to the ratio of said d.c. voltage to this direct current. Of course the receiver may comprise further supply circuits, not shown, for example for generating D.C. voltages of different values as well as one or more mains transformers.
In the cold condition thermistor 2 has a comparatively low resistance value (of approximately 25 Ohm), whilst thermistor 7 has a comparatively high value (of approximately 70 Ohm). Immediately after switch-on of mains switch 6 a large current flows through the thermistor 2 and coil 1 of approximately 5 A (peak value) or more. Because the series arrangement of the thermistor 7 and rectifier circuit 8 is in parallel with the source 5 the current therethrough is at the start independent of the degaussing current which flows through the branch 1, 2. The currents through both thermistors are able to heat them in a rather short time (approximately 10 seconds).
FIG. 2 shows on a logarithmic scale the resistance value R of thermistor 2 plotted as a function of the temperature T. Above the so-called Curie-temperature To (approximately 75° C.) the specific resistance of the material from which the thermistor 2 consists and consequently also its resistance value increases very steeply. In the absence of thermistor 7 thermistor 2 would attain, owing to self-heating, a temperature T1 (approximately 130° C.) with a corresponding resistance value R1 of approximately 20 kOhm, the amplitude of the degaussing current would then be brought to a value of approximately 20 mA.
When the temperature increases the resistance value of thermistor 7 decreases. The current through this thermistor is mainly determined by the values of the voltage across and of the current through load 11, which values, in the warm condition, are substantially independent of the temperature of thermistors 2 and 7 and of the degaussing circuit. For, they only depend on the operating conditions of the various parts of the receiver which are provided with supply voltage by circuit 8. Said current cannot, for example owing to the action of a safety circuit, exceed a given maximum.
The final value of thermistor 7 is low, for example, approximately 1 Ohm and a current of 1.5 A (r.m.s. value) and a temperature of 175° C. Thermistor 7 is chosen such that even for the smallest possible current through it, depending on load 11, it attains a final temperature which is higher than T1. Consequently, thermistor 7 delivers heat to thermistor 2. As a portion of the heat radiated by the thermistor 7 yet goes to the environment the final temperature of thermistor 2 will be lower than that of thermistor 7. Owing to the heat transfer thermistor 7 attains a final temperature T2 which is approximately 20° to 30° C. higher than T1. An equilibrium condition occurs wherein the final temperature of thermistor 7 is lower than the final temparature without thermal coupling to thermistor 2 and wherein both thermistors are approximately kept at said final temperatures by the final currents. This situation is stable and, consequently, safe: for an increase in temperature T1 causes a decrease in the current through thermistor 2 which opposes the increase in the temperature. It also prevents the temperature from rising too high which might cause the resistance value R to decrease. The final value R2 of thermistor 2 is higher than R1, namely approximately 60 kOhm and the final amplitude of the current through coil 1 is reduced to the desired value, i.e. less than 5 mA.
In the preceding the dissipation in coil 1 in the final condition is assumed to be negligibly small with respect to that in thermistor 2. This is justified by the fact that the ohmic resistance value (approximately 20 Ohm) of coil 1 is much lower than value R2 so that the output voltage drop across coil 1 is negligibly small.
Thermistor 7 is a safety resistor for rectifier circuit 8. Because prior to switch-on of mains switch 6 capacitor 10 is still uncharged a very large current would flow through rectifier 9 and capacitor 10 after switch-on if thermistor 7 would be absent. This might cause damage to these components and also to switch 6. It would also be possible that a fuse 12 which in FIG. 1 is included between switch 6 and the junction point of thermistors 2 and 7 would melt. The starting current is limited by thermistor 7 whilst the thermistor substantially produces no voltage drop in the hot condition.
Compared with the case wherein thermistor 7 is replaced by a linear resistor the circuit according to the invention means a considerable saving in energy. For, the final value of thermistor 7 is lower than the value of the linear resistance i.e. the above-mentioned starting value (approximately 70 Ohm) of thermistor 7 whereas the value of the rectified voltage across capacitor 10 is only decreased during the warming up time of thermistor 7.
There is an additional advantage, namely the fact that after switch-on of mains switch 6 the current derived by circuit 8 from source 5 grows gradually and not suddenly which attenuates the jump produced by circuit 1, 2.
FIG. 3 shows a second construction of the circuit according to the invention, with the same reference numerals as in FIG. 1 wherein the rectifier circuit 8 is in parallel with the series arrangement of coil 1 and thermistor 2, whilst thermistor 7 is included between mains switch 6 and the junction of thermistor 2 and circuit 8. In this construction thermistor 7 limits the switch-on value also for the degaussing current so that for both thermistors types must be chosen which each have a lower starting value than in the case of FIG. 1. In the final state there is substantially no difference between the two constructions.
It will be noted that in the two described constructions of the circuit thermistor 7 has a dual function, namely protecting the rectifier circuit 8 and increasing the final value of thermistor 2 and, consequently, reducing the final degaussing current, which means a saving compared with the case where the degaussing circuit is constructed in a known manner, for example with two thermally inter-coupled thermistors with positive temperature-coefficients, whilst thermistor 7 or a linear resistor in the same position is not coupled herewith.
In
FIG. 4 thermistor 7 is in parallel with the series arrangement of
degaussing coil 1 and thermistor 2. The circuit constituted by
components 1, 2 and 7 can be connected through fuse 12 and switch 6 to
terminal 3 of a.c. voltage source 5. In this example rectifier 9 is of
the Graetz-type: four diodes 9a, 9b, 9c and 9d form a bridge in a
diagonal whereof components 10 and 11 are included, whilst a point of
the other diagonal is connected to that junction of series arrangement
1, 2 and thermistor 7 which is not connected to mains switch 6. The
other point of said diagonal is connectable through switch 6 to the
other terminal 4 of source 5.In the cold state thermistor 2 has a comparatively low resistance value (of approximately 4 Ohm), whereas thermistor 7 has a comparatively high value (of approximately 150 Ohm). Capacitor 10 has as yet no charge. In this circuit coil 1 has an ohmic resistance value of approximately 100 Ohm. Immediately after switch-on of mains switch 6, the voltage of the source 5 is substantially completely across the parallel circuit constituted by components 1, 2, 7. If this voltage has an effective value of 220 V then a current of approximately 3.1 A (peak value) flows through thermistor 2 and coil 1, whilst a current of approximately 2.1 A flows through thermistor 7 which in the beginning is independent of the degaussing current flowing through branch 1, 2.
FIG. 5a represents one cycle of the current which flows through rectifier 9, at the start of the procedure. Herein it is assumed that the frequency of the mains voltage is 50 Hz which corresponds to a cycle of 20 ms. When capacitor 10 is discharged diodes 9a and 9d or 9b and 9c respectively conduct during the entire half cycle, that is to say that opening angle thereof is equal to 10 ms.
After switch-on the degaussing current through coil 1 gradually decreases, on the one hand, because the resistance value of thermistor 2 becomes higher when the thermistor becomes warmer and on the other hand because capacitor 10 is being charged. In addition, when the temperature increases the resistance value of thermistor 7 decreases. The final value thereof is low, for example approximately 2 Ohm. As in FIG. 1 and 3, thermistor 2 attains a final temperature T2 which exceeds the final temperature T1 which would be attained by self-heating in the absence of thermistor 7, which causes the final valve of thermistor 2 to become higher. The final amplitude of the degaussing current is consequently reduced to the desired value. This final state is stable and, consequently, safe.
FIG. 5b represents one cycle of the current flowing through rectifier 9 at the end of the process. The value thereof depends on the value of load 11; in a given receiver a peak value of approximately 4A was measured at an opening angle for the rectifying diodes of approximately 3 ms. It will be noted that the degaussing current through coil 1 is substantially of the same form as the currents in FIG. 5a and 5b as the reactance of the coil at low frequencies may be neglected relative to the ohmic resistance value hereof. FIGS. 5a and 5b show that the shape of the current is substantially symmetrical relative to the zero value. A condition for this is that the decrease in the amplitude of the degaussing current does not take place too rapidly, which decrease is determined by the product of the resistance value of the circuit 1, 2, 7 and the capacitance of capacitor 10. Because the capacitance is determined by the permissible amplitude of the ripple voltage across load 11 said condition implies a minimum value for this resistance and, consequently, of the initial resistance value of thermistor 7 and of the ohmic resistance value of the degaussing coil, whilst maintaining the magnetic properties thereof. In the example of FIG. 4 capacitor 10 has a capacitance of 200 μuF whilst said resistance value is approximately 60 Ohm in the cold state so that said product is approximately equal to 12 ms, that is to say in the order of magnitude of 50 to 60 % of the duration of the cycle.
The reason why the shape of the current must be substantial symmetrical relative to the zero value, the negative and the positive peak values being consequently substantially equal to one another, is that the degaussing current should substantially not contain a direct current component, which component would generate an unwanted magnetic field. When using a Graetz-rectifier as is the case in FIG. 4, the degaussing current reverses its direction at each half cycle as the current alternatingly flows either through diodes 9b and 9c or through diodes 9d and 9a. A single-phase rectifier in which the current does not reverse may not be used for the construction of FIG. 4. FIG. 6 represents a rectifier of the voltage doubler type which may be used. Herein rectifier circuit 8 comprises two diodes 9a and 9b and two capacitors 10a and 10b. It is obvious that the degaussing current which also flows through capacitor 10b comprises no direct current component. It is also obvious that the circuit 1, 2, 7 may be included in the supply lead to terminal 4 which, of course, also applies to the construction in FIG. 4. It can be noted that the single-phase rectifier, shown in FIG. 3, produces a d.c. voltage drop across thermistor 7. Consequently, also in this construction, reference should be given a Graetz rectifier.
In FIGS. 4 and 6 the initial current is limited by components 1, 2 and, especially, 7. It will be noted that thermistor 2 always has a rather low voltage drop across it, both in FIG. 4 and in FIG. 6. For, at the beginning of the process the voltage of source 5 is found substantially fully across coil, 1, which has a much higher ohmic resistance value, whilst the voltage across the series circuit 1, 2 at the end of the process is low, as thermistor 7 which is now low-ohmic substantially short-circuits said series arrangement. The advantage thereof is that thermistor 2 may be much thinner than thermistor 2 in FIGS. 1 and 3, that is to say 0.5 to 0.7 mm instead of approximately 2 mm, which means a considerable saving in material. It is consequently cheaper. In addition, the dissipation is much lower and the loss of heat to the environment much lower. The preceding also applies with respect of thermistors which in known circuits are in series with the degaussing coil and which, at least at the beginning of degaussing must be able to withstand a high voltage.
PHILIPS 26CE2281 RUBENS CHASSIS 2A Composite thermistor component:
A component consisting of two coupled PTC thermistors with the first thermistor having a lower cold resistance than the second thermistor and the first thermistor having a higher resistance at the operating temperature than the second thermistor. According to the invention, the electric connection to the second thermistor is made directly by solely mechanical contacts to the surface of the ceramic thermistor body. This means a considerable simplification during manufacture, as the second thermistor need not be provided with electrode layers.
Inventors:
Belhomme, Charles J. G. (Brussels, BE) U.S. Philips Corporation (New York, NY)
1. A thermistor component comprising
a first positive temperature coefficient of resistance thermistor,
a second positive temperature coefficient of resistance thermistor thermally in contact with said first thermistor, said second thermistor having a resistance substantially higher than the resistance of said first thermistor in the unoperated condition, and said second thermistor having a resistance lower than the resistance of the first thermistor at an operating temperature, wherein said second thermistor contributes to heating of said first thermistor during operation,
electrical connection to said first thermistor applied through metallic contact layers on said first thermistor, and
electrical connection to said second thermistor applied solely by mechanical contacts to a surface of said second thermistor, wherein said first thermistor has contact layers at opposite major faces, and said second thermistor has opposite major faces free of contact layers.
2. A degaussing circuit having a thermistor component as claimed in claim 1, in which said first thermistor is connected in a series arrangement with a degaussing coil and an alternating mains supply, and said second thermistor is connected in parallel with said series arrangement.
3. A thermistor component comprising
a first positive temperature coefficient of resistance thermistor,
a second positive temperature coefficient of resistance thermistor thermally in contact with said first thermistor, said second thermistor having a resistance substantially higher than the resistance of said first thermistor in the unoperated condition, and said second thermistor having a resistance lower than the resistance of the first thermistor at an operating temperature, wherein said second thermistor contributes to heating of said first thermistor during operation,
electrical connection to said first thermistor applied through metallic contact layers on said first thermistor, and
electrical connection to said second thermistor applied solely by mechanical contacts to a surface of said second thermistor, wherein said mechanical contacts include contact springs in direct contact with a major face of said second thermistor, and wherein at least one of said contact springs is in contact with a contact layer on said first thermistor.
4. A thermistor component comprising
a first positive temperature coefficient of resistance thermistor,
a second positive temperature coefficient of resistance thermistor thermally in contact with said first thermistor, said second thermistor having a resistance substantially higher than the resistance of said first thermistor in the unoperated condition, and said second thermistor having a resistance lower than the resistance of the first thermistor at an operating temperature, wherein said second thermistor contributes to heating of said first thermistor during operation,
electrical connection to said first thermistor applied through metallic contact layers on said first thermistor, and
electrical connection to said second thermistor applied solely be mechanical contacts to a surface of said second thermistor, wherein said first and second thermistors each have a major face in contact with a feedthrough plate, wherein said mechanical contacts include contact springs in direct contact with a major face of said second thermistor, and wherein at least one of said contact springs is in contact with a contact layer on said first thermistor.
5. A thermistor component according to claim 1, wherein said first and second thermistors are ceramic.
6. A thermistor component according to claim 1, wherein said first thermistor has a Curie point of 75° C. and said second thermistor has a Curie point of 180° C.
7. A thermistor component comprising
a first positive temperature coefficient of resistance thermistor,
a second positive temperature coefficient of resistance thermistor thermally in contact with said first thermistor, said second thermistor having a resistance substantially higher than the resistance of said first thermistor in the unoperated condition, and said second thermistor having a resistance lower than the resistance of the first thermistor at an operating temperature, wherein said second thermistor contributes to heating of said first thermistor during operation,
electrical connection to said first thermistor applied through metallic contact layers on said first thermistor, and
electrical connection to said second thermistor applied solely by mechanical contacts to a surface of said second thermistor, wherein said first and second thermistors each have a major face in contact with a feedthrough plate, and wherein said first thermistor has contact layers at opposite major faces, and said second thermistor has opposite major faces free of contact layers.
Description:
The invention relates to a composite thermistor component comprising two thermistors having a positive temperature coefficient of the resistance, the thermistors being thermally coupled to one another, to a degaussing circuit in which the component is incorporated and to colour television receiver comprising a shadow-mask picture display tube and a degaussing circuit of this type.
Such a composite thermistor component, which is described in United Kingdom patent specification No. 1,531,277 comprises a first thermistor and a second thermistor which each have a positive temperature coefficient of resistance, the second thermistor having a resistance which is substantially higher than the resistance of the first thermistor when the thermistors are in the unoperated (cold) condition, the two thermistors being thermally coupled such that in operation the second thermistor contributes to the heating of the first thermistor and that the resistance of the second thermistor at the final operating temperature of the component is lower than the resistance of the first thermistor.
It is an object of the invention to considerably simplify the composite thermistor component and according to the invention it is characterized in that the electrical connection to the second thermistor is made directly by solely mechanical contacts to the surface of the ceramic thermistor body.
The present invention will be described without limitation by reference to the drawing figures wherein
FIG. 1 is a schematic representation of a circuit used for degaussing metal parts, and
FIG. 2 is a view of a structure in accordance with the present invention.
The composite thermistor component is inter alia used in a circuit for degaussing metal parts, particularly the inner shield and the shadow mask, of a colour television display tube. A first thermistor 2 is connected in a series arrangement with a degaussing coil 1 to a first (3) and second (4) terminal for an alternating mains supply (5) via a switch (6), the first thermistor having a positive temperature coefficient of resistance, and the second thermistor 7 has a positive temperature coefficient of resistance connected in parallel with the series arrangement of coil 1 and thermistor 2. The two thermistors are thermally coupled because they are in intimate contact with one another.
This is shown in FIG. 1 by means of an arrow.
The description and the drawing of the abovementioned United Kingdom patent specification give the impression that the two thermistors are contacted directly by means of the ceramic surfaces. For a person skilled in the art, the use of ceramic components having metallized areas of contact in an electrical circuit has, however, always been such a matter of course that the presence of such metallized areas of contact had been omitted from the description for the sake of simplicity.
As a matter of fact, contacting by way of the ceramic surface by mechanical contact only can only be effected on the parallel thermistor in the circuit, that is to say the thermistor which, in the unoperated condition, has the higher resistance, contributes to heating the other thermistor during operation and has at the prevailing temperature a resistance which is lower than that of the other thermistor.
The thermistor which is in series with the degaussing coil must be of a low resistance during the unoperated condition and the metallized layer which is in intimate contact therewith must be present on substantially the entire surface area. Contacting of the series thermistor body by solely mechanical contacts only directly to the surface of the thermistor body does not result in a useful component.
Relative to the component which is known from the United Kingdom patent specification No. 1,531,277, in which the second thermistor (7) is provided with a vacuum-deposited nickel-chromium nickel-chromium layer onto which a thin silver layer has been vacuum-deposited, which silver layer is reinforced with a silver paste, the second thermistor must be somewhat changed to obtain a composite component according to the invention having similar operating characteristics. The material must have a Curie point which is approximately 10° C. higher than that of the material used for the second thermistor in the United Kingdom patent specification No. 1,531,277 component in order to achieve this.
In FIG. 2, reference numerals 2 and 7 denote the thermistors which have been given the same reference numerals as in FIG. 1, that is to say 7 is the thermistor having a positive temperature coefficient and a resistance value which is higher than that of thermistor 2 when the thermistors are in the unoperated (cold) condition and a resistance value at the final operating temperature which is lower than the resistance value of thermistor 2.
Thermistor 2 is provided on each major surface by vacuum deposition with a 0.1 μm thick Ni-Cr layer, onto which a 0.3 μm thick silver layer and a 10 μm silver containing layer are deposited, the three superposed layers constituting a contact layer 11. Thermistor 7 is built-in without having been provided with a contact layer on either major surface. In the composite thermistor component, the major surface of the thermistor 7 which is opposed to the thermistor 2 bears directly against a silver-plated stainless steel plate 12, which is provided with a feed-through 9 to the circuit, and the silver-plated stainless plate 12 bears against the contact layer 11 on the opposed major surface of the thermistor 2. On both sides the silver-plated stainless steel contact springs 8 and 10 push against the thermistors, that is to say contact spring 8 is in direct contact with the ceramic surface of thermistor 7 and contact spring 10 is in direct contact with the contact layer 11 on thermistor 2.
In one embodiment thermistor 2 has a composition
Ba0,80 Ca0,10 Sr0,10 TiO3 +0,3 mole % TiO2 +0,4 mole % Sb2 O3 and 0,08 mole % MnO.
This thermistor has a resistance value of approximately 40 Ohm at 25° C., the Curie point being 75° C.
Thermistor 7 has the composition:
B0,70 Ca0,10 Pb0,20 TiO3 +3 mol % TiO2 +0,4 mol % Sb2 O3 +0,08 mol % MnO.
This material has a Curie point of 180° C. The resistance value of the thermistor at 25° C. was not determined without contact layers, which is difficult to achieve, but with vacuum-deposited contact layers, a resistance of 50 to 400 Ohm then been measured.
In the construction of the thermistor as described in United Kingdom patent specification No. 1,531,277, provided with vacuum-deposited NiCr+Ag and a silver-containing layer, material was used having a Curie point of 170° C. and a resistance of the thermistor at 25° C. of 800-4000 Ohm. The relevant composition was:
Ba0,72 Ca0,10 Pb0,18 TiO3 +0,3 mol % TiO2 +0,4 mole % Sb2 O3 +0,08 mole % MnO.
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