The CHASSIS D16 from PHILIPS is his most sophisticated and complex type.
It employs the DIGIVISION ITT DIGIT2000 Technology even when PHILIPS has developed his own 100HZ digital technology.
This is a great example of the Extreme flexibilty of the research & development of PHILIPS which was basically completely free to develop and design chassis technology without marketing obligations or any type of blocking circumstances in any field or aspect design.
The CHASSIS PHILIPS D16 Is a semi modular type and it has additional horizontal board for further device like audio processing and I/O selection / expansion including a D2B Bus connection feature.Here described the functions featured:
D2B Bus :Domestic Digital Bus (D2B) SMARTwireX: D2B is an optical data bus system that was developed to connect audio, video, computer, and telephone components in a single ring structure within a vehicle. SMARTwireX defines a physical layer supporting the D2B networks running up to 25 Mb/sec and featuring automotive compatibility. It is an electrical physical solution for automotive networks.
The present invention D2B Bus :Domestic Digital Bus (D2B) SMARTwireX relates to a communication protocol for use in communication among AV (audio-video) equipments, communication among computers and communication among AV equipments and computers, for example.
It is customary that the AV system is formed of a plurality of AV equipments, such as a TV (television receiver), an MDP (multi-media player), a VTR (video tape recorder), an AV center (switcher) or the like.
In the AV system, a plurality of AV equipments, such as TV, MDP, VTR and AV center, are connected together by means of video signal lines, audio signal lines and control signal lines (control buses). A variety of control signals and data (e.g., packets of predetermined formats) are supplied to the AV equipments via the control buses, whereby the respective AV equipments are operated in a ganged fashion.Specifically, according to the AV system, when a play button of the VTR is operated, a packet is output to the TV and the AV center from the VTR, whereby the TV and the AV center are powered. Further, the AV center is switched such that the VTR and the TV are connected together, and image and sound reproduced by the VTR are output from the VTR.
The packets are communicated in the following procedure:
(T1) Routing information transmission
(T2) Command (CMD) transmission
(T3) Request (REQ) transmission
(T4) Get answer (GET-ANS) transmission.fwdarw.answer (ANS) reception
(T5) End (END) transmission
Initially, an AV equipment which transmits a packet first is set to "master apparatus" and an AV equipment which receives such packet is set to "slave apparatus". Routing information is transmitted from the master apparatus to the slave apparatus (T1). At that time, the slave apparatus is locked so that it is inhibited from receiving a packet transmitted from other AV equipment.
Then, a command (CMD) which turns on the power supply is transmitted from the master apparatus to the slave apparatus (T2). A request (REQ) which solicits the processing of the command is further transmitted from the master apparatus to the slave apparatus (T3).
Then, in order to obtain an answer (ANS) for REQ, the get answer (GET-ANS) is transmitted from the master apparatus to the slave apparatus (T4). The GET-ANS is repeatedly transmitted until the answer ANS is obtained from the slave apparatus. When the answer (ANS) is obtained from the slave apparatus, an end (END) representing the end of the processing is transmitted (T5). At that time, the slave apparatus which is set in the locked state is set in the unlock state. Therefore, the slave apparatus is set in a state that it can again receive a packet transmitted from the AV equipment.
As described above, the packet exchange procedure in the conventional AV system is cumbersome.
Since the GET-ANS is repeatedly transmitted until the answer ANS is obtained from the slave apparatus, the traffic on the control bus is increased. Furthermore, it is frequently observed that other AV equipments cannot use the control bus. There is then the problem that the overall processing speed of the system is lowered.When a packet is transmitted from the master apparatus to the slave apparatus, for example, the CMD transmission and the REQ transmission, the communication mode of the master apparatus is set in the master communication mode, and the communication mode of the slave apparatus is set in the slave reception mode. If on the other hand a packet is expected to be transmitted from the slave apparatus to the master apparatus, such as when the master apparatus does not receive the answer (ANS) from the slave apparatus, and therefore issues the GET-ANS, the communication mode of the master apparatus is set in the master reception mode and the communication mode of the slave apparatus is set in the slave transmission mode.
As described above, there are four communication modes such as the master transmission mode, the master reception mode, the slave transmission mode and the slave reception mode. Therefore, each AV equipment must exchange a packet by switching the four modes and a communication efficiency is low.
Further, each AV equipment needs four buffers including a master transmission buffer for latching a packet transmitted in the master transmission mode, a master reception buffer for latching a packet received in the master reception mode, a slave transmission buffer for latching a packet transmitted in the slave transmission mode and a slave reception buffer for latching a packet received in the slave reception mode. There is then the problem that the apparatus becomes large in size and expensive.
Furthermore, since the reception side cannot recognize a transmission error, there is then the problem that an error recovery processing required when a transmission error occurs becomes complex.
In addition, date of 3 frames must be transmitted at minimum in order to transmit pure data, e.g., OSD data. There is then the problem that a lot of time must be prepared and that the processing becomes complex.
SUMMARY OF THE INVENTION
In view of the aforesaid aspect, an object of the present invention is to provide a communication protocol for communicating data in which a communication can be efficiently made by a simple procedure.
According to a first aspect of the present invention, there is provided a communication protocol for communicating data by a serial format which is comprised of a command packet informing an operation command, a status request packet informing a status request of some apparatus, a data request packet informing a data request to some apparatus, a datum packet informing data, an answer packet informing answer datum for previous request, an automatic status sending packet informing a status of an apparatus, and a simulcast packet informing simulcast datum for a plurality of apparatus.
According to a second aspect of the present invention, there is provided a communication system for communicating data which is comprised of a command packet communicating member for communicating a command packet, a status request packet communicating member for communicating a status request packet. a data request packet communicating member for communicating a data request packet, a datum packet communicating member for communicating a datum packet, an answer packet communicating member for communicating an answer packet, an automatic status sending packet communicating member for communicating an automatic status sending packet, and a simulcast packet communicating member for communicating a simulcast packet.
In accordance with a third aspect of the present invention, there is provided a communication system for communicating data which is comprised of a master apparatus which comprises a command packet communicating member for communicating a command packet, a status request communicating member for communicating a status request packet, a data request packet communicating member for communicating a data request packet, a datum packet communicating member for communicating a datum packet, an answer packet communicating member for communicating an answer packet, an automatic status packet communicating member for communicating an automatic status sending packet, and a simulcast packet communicating member for communicating a simulcast packet, and a slave apparatus which comprises a command packet communicating member for communicating a command packet, a status request packet communicating member for communicating a status request packet, a data request packet communicating member for communicating a data request packet, a datum packet communicating member for communicating a datum packet, an answer packet communicating member for communicating an answer packet, an automatic status sending packet communicating member for communicating an automatic status sending packet, and a simulcast packet communicating member for communicating a simulcast packet.The D16 Has even PIP functions but this section is SIEMENS Chipset based.
The idea of digitization of TV functions is not new. The time some companies have started to work on it, silicon technology was not really adequate for the needed computing power so that the most effective solutions were full custom designs. This forced the block-oriented architecture where the digital functions introduced were the one to one replacement of an existing analog function. In Figure 2 there is a simplified representation of the general concept.
Fig.2: Block Diagram of first generation digital TV set
The natural separation of video and audio resulted in some incompatibilities and duplication of primary functions. The emitting principle is not changed, redundancy is a big handicap, for example the time a SECAM channel is running, the PAL functions are not in operation. New generations of digital TV systems should re-think the whole concept top down before VLSI system partitioning.
In today’s state-of-the-art solution one can recognize all the basic functions of the analog TV set with, however, a modularity in the concept, permitting additional features becomes possible, some special digital possibilities are exploited, e.g. storage and filtering techniques to improve signal reproduction (adaptive filtering, 100 Hz technology), to integrate special functions (picture-in-picture, zoom, still picture) or to receive digital broadcasting standards (MAC, NICAM). The Figure 3 shows the ITT Semiconductors solution which was the first on the market in 1983 !! !!
Fig.3: The DIGIT2000 TV receiver block diagram
Description:This invention relates generally to digital television receivers and, particularly, to digital television receivers arranged for economical interfacing with a plurality of auxiliary devices.
With the proliferation of low cost microprocessors and microprocessor controlled devices, television (TV) receivers are being designed to utilize digitized signals and controls. There are many advantages associated with digital TV receivers, including uniformity of product, precise control of signal parameters and operating conditions, elimination of mechanical switches and a potential for reliability that has been heretofore unknown. Digital television receivers include a high speed communication bus for interconnecting a central control unit microprocessor (CCU) with various TV function modules for processing a TV signal. These modules include a deflection processing unit (DPU), a video processing unit (VPU), an automatic phase control (APC), a video codec unit (VCU), an audio analog to digital converter (ADC) and an audio processing unit (APU). The CCU has associated with it a non-volatile memory, a hardware-generated clock signal source and a suitable interface circuit for enabling the CCU to control processing of the TV signal throughout the various TV function modules. The received TV signal is in analog form and suitable analog to digital (A/D) converters and digital to analog (D/A) converters are provided for converting the digital and analog signals for signal processing and for reconverting them after processing for driving a cathode ray tube (CRT) and suitable speakers. The CCU microprocessor is heavily burdened because of the high speed timing required to control the various TV function modules.
To further complicate matters, modern TV receivers are increasingly being used with auxiliary devices for other than simple processing of TV signals. For example, the video cassette recorder (VCR) has enabled so-called "time-shifting" of program material by recording TV signals for later, more convenient viewing. The VCR is also extensively used with prerecorded material and with programs produced by users having access to a video camera. Other auxiliary devices providing features such as "Space Phone" whereby the user is enabled to make and receive telephone calls through his TV receiver, are desirable options. Additionally, a source selector auxiliary device enables a host of different signal sources, such as cable, over-the-air antenna, video disk, video games, etc. to be connected for use with the signal processing circuitry of the TV. In addition, all of these many auxiliary devices are preferably controllable from a remote position. A great deal of flexibility is available since each of the above auxiliary devices includes a microprocessor for internally controlling functioning of the device. In the digital TV system described, the CCU microprocessor and the microprocessors in the auxiliary devices may be conventionally arranged to communicate over the main communication bus. Such a system would entail a specialized microprocessor with a hardware-generated clock signal in each auxiliary device in order to communicate at the high speeds used on the main communication bus. A specialized microprocessor, that is, one that is hardware configured, is significantly more expensive than an off-the-shelf microprocessor. Also, the auxiliary devices may not be required, or even desired, by all users and their low volume production cost becomes very important. It would therefore be desirable to provide a digital TV in which such auxiliary devices utilized off-the-shelf microprocessors for their control.
A digital TV system includes a CCU that is interconnected by a three-wire, high speed bus to a plurality of TV signal function modules for controlling operation thereof by means of a high speed hardware generated clock signal. A software generated clock signal in the CCU is supplied on a low speed two-wire auxiliary device bus which is connected to microprocessors in a plurality of auxiliary devices for performing functions ancillary to TV signal processing. The microprocessor in each auxiliary device is an off-the-shelf type that does not require any special hardware because the timing on the auxiliary device bus is sufficiently slow to enable software monitoring of the line and data transfer.
As mentioned, the three-wire IM bus 21 is a high speed bidirectional bus in which CCU 20 functions as the master and all of the interconnected TV signal processing function modules are slaves that communicate with the CCU in accordance with the protocol established for the system. CCU 20 is also indicated as including a software generated clock which supplies a two-wire auxiliary device bus 50. Two-wire bus 50 includes a clock lead 51 and a data lead 52 coupled to a plurality of auxiliary devices. A VCR 54, including an off-the-shelf microprocessor 55, is coupled to bus 50. A Source Selector 56, including an off-the-shelf microprocessor 57, is also coupled to bus 50. Source Selector 56 has access to four RF inputs, two baseband video and audio inputs and one separate baseband audio input. It will be appreciated that Source Selector 56 may have a greater or lesser number of signal sources to which it has access. Source Selector 56 outputs are coupled to VCR 54 and also to tuner 10 and supply, under control of CCU 20 and keyboard 44, the signal from the signal source selected by keyboard 44 or IR transmitter 46 for use with the digital TV. Auxiliary device bus 50 is also coupled to a Space Phone 58 which includes an off-the-shelf microprocessor 59 and a modem 60 that is connectable to a conventional telephone terminal. Two-wire auxiliary device bus 50 is a relatively low speed bus and there is no need for separate hardware generated clock signals to be developed by the auxiliary device microprocessors. As mentioned above, this feature involves a significant savings in the cost and complexity of the auxiliary devices.
The protocol used on the two-wire auxiliary device bus consists of a 16 bit sequence, the first eight bits of which are used for bus address commands for the auxiliary devices. Each auxiliary device may respond to 16 addresses which allows the CCU to write into or read from various storage registers in the devices which are used for control or data storage. Thus, with this low cost system, as many as 16 auxiliary devices may be connected to the auxiliary device bus. The second eight bits of the 16 bit sequence contain data which is either transferred from the CCU to the auxiliary device addressed, or transferred from the auxiliary device to the CCU, based upon the bus address used. Thus, the various bus addresses to which a given auxiliary device will respond determine whether the auxiliary device will receive data from the CCU or send data to the CCU. The clock line timing, generated by software in CCU 20, is slow enough to permit software monitoring of the line and data reception by simple auxiliary device microprocessors that are not equipped with an external interrupt feature. The timing on the auxiliary device bus is made sufficiently fast to avoid too many instruction steps or the need for special registers in CCU 20. In the system described, data is clocked every 82.5 microseconds, thus permitting a 16 bit word to be clocked in 1.32 milliseconds. A pause of 277.5 microseconds between the first 8 bits and the second 8 bits permits the slave auxiliary device to process the bus address data contained in the first 8 bits. This timing fits into the 2 millisecond timing block structure used for the CCU in controlling the DIGIT 2000 digital TV. Two-2 millisecond timing blocks have been established in the CCU, which has a 20 millisecond timing loop divided into ten-2 millisecond timing blocks. Thus, two control words may be sent to an auxiliary device every 20 milliseconds, or a request by the CCU to receive data and the actual receipt of that data may take place in that time period.
Referring to the drawing, a digital TV includes a tuner 10 coupled to an IF/Detector 12 which has a pair of outputs 13 and 14 supplying video and audio signals, respectively. Control signals for tuner 10 are supplied through an interface circuit 16 from a CCU microprocessor 20 which functions as a single master control unit for the system. Microprocessor 20 is interconnected by means of a bidirectional three-wire IM (Intermetal) bus 21 to a DPU 22, a VPU 26, an APC 30, a TTX (teletext processor) 38, an APU 36, an ADC 32 and a non-volatile memory 24. A serial control line 29 interconnects a hardware generated clock 28, VPU 26 and VCU 34. VPU 26 and VCU 34 are also interconnected by a seven wire cable and TTX 38 is interconnected with a DRAM 42. DRAM 42 is a dynamic RAM in which TTX information is stored for display. VCU 34 is supplied with video signal and supplies a digitized 7 bit grey coded video signal to VPU 24 for processing and RGB color signals to a Video Drive 40 which, in turn, supplies a cathode ray tube (not shown). A keyboard 44 is coupled to CCU 20 and includes an IR detector that is responsive to coded IR signals supplied from an IR transmitter (IRX) 46. A resident microprocessor in keyboard 44 decodes the received IR signals and generated control commands and supplies appropriate outputs to CCU 20. The diagram, as described, is substantially identical to that for a "DIGIT" 2000 VLSI Digital TV System developed by ITT Intermetal and published in Edition 1984/85 Order No. 6250-11-2E
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By its very nature, computer technology is digital, while consumer electronics are geared to the analog world. Starts have been made only recently to digitize TV and radio broadcasts at the transmitter end (in form of DAB, DSR, D2-MAC, NICAM etc). The most difficult technical tasks involved in the integration of different media are interface matching and data compression [5].
After this second step in the integration of multimedia signals, an attempt was made towards standardization, namely, the integration of 16 identical high speed processors with communication and programmability concepts comprised in the architecture !
Many solutions proposed today (for MPEG 1 mainly) are derived from microprocessor architectures or DSPs, but there is a gap between today’s circuits and the functions needed for a real fully HDTV system. The AT&T hybrid codec [29], for instance, introduces a new way to design multimedia chips by optimizing the cost of the equipment considering both processing and memory requirements.
The concept is to provide generic architectures that can be applied to a wide variety of systems taking into account that certain functions have to be optimized and that some other complex algorithms have to be ported to generic processors.
Basics of current video coding standards
Compression methods take advantage of both data redundancy and the non-linearity of human vision. They exploit correlation in space for still images and in both space and time for video signals. Compression in space is known as intra-frame compression, while compression in time is called inter-frame compression. Generally, methods that achieve high compression ratios (10:1 to 50:1 for still images and 50:1 to 200:1 for video) use data approximations which lead to a reconstructed image not identical to the original.
Methods that cause no loss of data do exist, but their compression ratios are lower (no better than 3:1). Such techniques are used only in sensitive applications such as medical imaging. For example, artifacts introduced by a lossy algorithm into a X-ray radiograph may cause an incorrect interpretation and alter the diagnosis of a medical condition. Conversely, for commercial, industrial and consumer applications, lossy algorithms are preferred because they save storage and communication bandwidth.
Lossy algorithms also generally exploit aspects of the human visual system. For instance, the eye is much more receptive to fine detail in the luminance (or brightness) signal than in the chrominance (or color) signals. Consequently, the luminance signal is usually sampled at a higher spatial resolution. Second, the encoded representation of the luminance signal is assigned more bits (a higher dynamic) than are the chrominance signals. The eye is less sensitive to energy with high spatial frequency than with low spatial frequency [7]. Indeed, if the images on a personal computer monitor were formed by an alternating spatial signal of black and white, the human viewer would see a uniform gray instead of the alternating checkerboard pattern. This deficiency is exploited by coding the high frequency coefficients with fewer bits and the low frequency coefficients with more bits.
All these techniques add up to powerful compression algorithms. In many subjective tests, reconstructed images that were encoded with a 20:1 compression ratio are hard to distinguish from the original. Video data, even after compression at ratios of 100:1, can be decompressed with close to analog videotape quality.
Lack of open standards could slow the growth of this technology and its applications. That is why several digital video standards have been proposed:
- JPEG (Joint Photographic Expert Group) for still pictures coding
- H.261 at p times 64 kbit/s was proposed by the CCITT (Consultative Committee on International Telephony and Telegraphy) for teleconferencing
- MPEG-1 (Motion Picture Expert Group) up to 1,5 Mbit/s was proposed for full motion compression on digital storage media
- MPEG-2 was proposed for digital TV compression, the bandwith depends on the chosen level and profile [33].
Another standard, the MPEG-4 for very low bit rate coding (4 kbit/s up to 64 kbit/s) is currently being debated.
Digitalization of the fundamental TV functions is of great interest since more than 30 years. Several million of TV sets have been produced containing digital systems. However, the real and full digital system is for the future. A lot of work is done in this field today, the considerations are more technical than economical which is a normal situation for an emerging technology. The success of this new multimedia technology will be given by the applications running with this techniques.
The needed technologies and methodologies were discussed to emphasize the main parameters influencing the design of VLSI chips for Digital TV Applications like parallelization, electrical constraints, power management, scalability and so on...............................
The stereo pilot carrier is selectively decoupled from soundchannel TV ll and fed separately to Pin 8 for recognition of the
station operating mode.
The digitized output signals are then available as pulse-rate-
modulated signals PDM I and PDM ll at Pins 10 and 11. Digital
signal processing is then performed completely in APU 2470,
the audio processor IC 3201, to which of course all control
functions controlled via the IM Bus belong. At IC outputs 22 and
23, the processed signals are outputted as pulse-width-
modulated information, so that they can be reconverted into
their original analog form by simple integration (RC element).
The downstream lC’s TDA 2040 H (3401/3501) supply power
amplification for feed to the loudspeakers. A second pair of
analog outputs, Pins 19, 20 ofthe APU, followed by an
integrated amplifier stage, IC 3301 , TDA 2822 M, serves for
connection of earphones or a stereo system via cinch sockets.
This output is likewise controllable, and also suitable for the
listening to the alternative sound channel in dual-channel sound
mode. Pins 21 and 24 at ADC 2310 E are available for coupling
a second dual-channel analog sound source. The signals
concerned come from the SCART socket (PPT), and in sets withpicture-in-picture function are passed via the PIP decoder. In
the opposite direction, the ADC 2310 E supplies at Pins 22 and
23 analog output signals to the SCART socket, e.g. as required
for recording audio signals. All switch-over functions necessary
in this area are executed inside the IC and controlled via the IM
Bus. Detection of the station transmission mode (mono, stereo,
dual-sound) is performed in the lC’s in exactly the same way as
the corresponding switch-over to the operating mode being
transmitted. A muting stage in each of the two audio channels
(T 3401 and T 3501) provides an audio muting function by short-
circuiting the signal input Pin 1 at the power output stage lC’s.
This function can be controlled in two different ways:
1. Via ST 33 at the moment when the set is switched on, in
order to suppress the switch-on click.
2. From Pin 16 of ADC 2310 E, e.g. for noise suppression,
when no TV signal is being received.
ln the first case, the L signal, which is passed as a switch-on
signal from Pin 5 of the CCU via R 1505 to ST 33 of Stereo
Module B, and thus via R 3511 to the base of T 3510, will switch
the transistor to on-state and thus connect the muting line to
12 V. Since in this case the two switching transistors T 4301 and
T 3501 also become conducting, the signal inputs to the audio
output stages are then short-circuited. The second muting
branch from Pin 16 of ADC 2310 E is software-controlled, and
receives the switch-off information from the CCU via the IM
Bus.
PHILIPS DIGI 16 SWITCH MODE (SOPS) POWER SUPPLY DESCRIPTION:
Switched-mode self oscillating supply voltage circuit:
POWER SUPPLY (SOPS - Self Oscillating Power Supply)
A switched-mode self-oscillating supply voltage circuit for converting an input voltage into an output d.c. voltage which is substantially independent of variations of the input voltage and/or a load connected to the output voltage. The circuit comprises a first controllable switch connected in series with a transformer winding and a second controllable switch for turning-off the first switch. The conduction period of the first switch is controlled by means of a control voltage present on a control electrode of the second switch. The circuit can be switched-over to a stand-up state in which the energy supplied to the load is reduced to zero. A starting network is connected between the input voltage and the second switch so that the current therein flows through the second switch during the period of time this switch conducts and does not flow to the control electode of the first switch in the stand-by state.
1. A switched-mode self-oscillating supply voltage circuit for converting an input voltage into an output d.c. voltage which is substantially independent of variations of the input voltage and/or of a load connected to the terminals of the output voltage, comprising a transformer having a primary and a feedback winding, a first controllable switch connected in series with the primary winding, the series arrangement thus formed being coupled between terminals for the input voltage, a second controllable switch coupled via a turn-off capacitor to the control electrode of the first switch to turn it off, means coupling the feedback winding to said control electrode, a transformer winding being coupled via a rectifier to an output capacitor having terminals which supply the output voltage, an output voltage-dependent control voltage being present on a control electrode of the second switch for controlling the conduction period of the first switch, the circuit being switchable between an operating state and a stand-by state in which relative
to the operating state the supply energy supplied to the load is considerably reduced, a starting network connected to a terminal for the input voltage, means for adjusting the control voltage in the stand-by state to a value at which the first controllable switch is cut-off, a connection which carries current during the conduction period for the second controllable switch being provided between the starting network and said second switch, and means providing a connection between the starting network and the control electrode of the first switch, which connection does not carry current in the stand-by state.2. A supply voltage circuit as claimed in claim 1, further comprising a resistor included between the connection of the starting network to the second switch and a turn-off capacitor present in the connection to the control electrode of the first switch.
3. A supply voltage circuit as claimed in claim 2, characterized in that the second controllable switch comprises a thyristor having a main current path included in the control electrode connection of the first controllable switch, said thyristor having a first control gate electrode for adjusting the turn-off instant of the first switch and a second control electrode to which the starting network and the resistor are connected.
4. A supply voltage circuit as claimed in claim 1, characterized in that a resistor is included in the connection to the control electrode of the second controllable switch so that a current flows through said resistor in the stand-by state of a value sufficient to cut-off the first controllable switch.
Description:
The invention relates to a switched-mode self-oscillating supply voltage circuit for converting an input voltage into an output d.c. voltage which is substantially independent of variations of the input voltage and/or of a load connected to the terminals of the output voltage. This circuit comprises a transformer having a primary and a feedback winding and a first controllable switch arranged in series with the primary winding. The series arrangement thus formed is coupled between the terminals of the input voltage. A second controllable switch which is coupled via a turnoff capacitor to the control electrode of the first switch to turn it off. The feedback winding is coupled to this control electrode and the primary winding is coupled via a rectifier to an output capacitor the terminals of which are the terminals for the output voltage. An output voltage-dependent control voltage is present on a control electrode of the second switch for controlling the conduction period of the first switch. The circuit is switchable between an operating state and a stand-by state in which relative to the operating state the energy supplied to the load is considerably reduced, and the circuit further comprises a starting network connected to a terminal for the input voltage. Such a supply voltage circuit is disclosed in German Patent Application No. 2,651,196. With this prior art circuit supply energy can be applied in the operating state to the different portions of a television receiver. In the stand-by state the majority of the output voltages of the circuit are so low that the receiver is substantially in the switched-off condition. In the prior art circuit the starting network is formed by a resistor connected to the unstabilized input voltage and through which on turn-on of the circuit a current flows via the feedback winding to the control electrode of the first controllable switch, which is a switching transistor, and brings it to and maintains it in the conductive state, as a result of which the circuit can start.
The invention has for its object to provide an improved circuit of the same type in which in the stand-by state the supply energy applied to the load is reduced to zero. The prior art circuit cannot be improved in this respect without the use of mechanical switches, for example relays. According to the invention, the switched-mode self-oscillating supply voltage circuit does not comprise such relays and is characterized in that it further comprises means for adjusting the control voltage in the stand-by state to a value at which the first controllable switch is cut-off. A connection which carries current during the conduction period of the second controllable switch is provided between the starting network and said second switch while a connection present between the starting network and the control electrode of the first switch does not carry current in the stand-by state.
The invention is based on the recognition that the prior art supply voltage circuit cannot oscillate, so that the energy supplied by it is zero, if the control voltage obtains a value as referred to, while the starting network is connected in such a manner that in the stand-by state no current can flow through it to the control electrode of the first controllable switch.
It should be noted that in the said German Patent Application the starting network is in the form of a resistor which is connected to an unstabilized input d.c. voltage. It is, however, known, for example, from German Patent Specification No. 2,417,628 to employ for this purpose a rectifier network connected to an a.c. voltage from which the said input d.c. voltage is derived by rectification.
The invention will now be further described by way of example with reference to the accompanying drawing, which shows a basic circuit diagram of a switched-mode self-oscillating supply voltage circuit.
The self-oscillating supply circuit shown in the FIGURE comprises a npn-switching transistor Tr1 having its collector connected to the primary winding L1 of a transformer T, while the emitter is connected to ground via a small resistor R1, for example 1.5 Ohm. Resistor R1 is decoupled for the high frequencies by means of a 150 nF capacitor C1. One end of winding L1 is connected to a conductor which carries an unstabilized input d.c. voltage V B of, for example, 300 V. Voltage V B has a negative rail connected to ground and is derived from the electric power supply by rectification. One end of a feedback winding L2 is connected to the base of transistor Tr1 via the parallel arrangement of a small inductance L3 and a damping resistor R2. A terminal of a 47 μF capacitor C2 is connected to the junction of the elements L2, L3 and R2. The series arrangement of a diode D1 and a 2.2 Ohm-limiting resistor R3 is arranged between the other terminal of capacitor C2 and the other end of winding L2 and the series arrangement of a resistor R4 of 12 Ohm and a diode D2 is arranged between the same end of winding L2 and the emitter of transistor Tr1. A 150 nF capacitor C3 is connected in parallel with diode D2. The anode of diode D1 is connected to that end of winding L2 which is not connected to capacitor C2, while the anode of diode D2 is connected to the emitter of transistor Tr1. In the FIGURE the winding sense of windings L1 and L2 is indicated by means of dots.
The junction of capacitor C2 and resistor R3 is connected to a 100 Ohm resistor R5 and to the emitter of a pnp-transistor Tr2. The base of transistor Tr2 is connected to the other terminal of resistor R5 and to the collector of an npn-transistor Tr3, whose emitter is connected to ground. The base of Tr3 is connected to the collector of transistor Tr2. Transistors Tr2 and Tr3 form an artificial thyristor, i.e. a controllable diode whose anode is the emitter of transistor Tr2 while the cathode is the emitter of transistor Tr3. The base of transistor Tr2 is the anode gate and the base of transistor Tr3 is the cathode gate of the thyristor formed. Between the last-mentioned base and the emitter of transistor Tr1 there is arranged the series network of a 2.2 kOhm resistor R6 with the parallel arrangement of a 2.2 kOhm resistor R7 and a 100 μF capacitor C4. The series arrangement of a diode D11 and a 220 Ohm limiting resistor R19 is arranged between the junction of components R6, R7 and C4 and the junction of components C2, L2, R2 and L3. The cathode of diode D11 is connected to capacitor C2.
Because of the feedback the described circuit oscillates independently as soon as the steady state is achieved. It will be described hereinafter how this state is obtained. During the time transistor Tr1 conducts the current flowing through the resistor R1 increases linearly. The resistor R4 then partly determines the base current of transistor Tr1. Capacitor C4 and resistor R7 form a voltage source the voltage of which is subtracted from the voltage drop across resistor R1. As soon as the voltage on the base of transistor Tr3 is equal to approximately 0.7 V this transistor becomes conductive, as a result of which the thyristor formed by transistors Tr2 and Tr3 becomes rapidly conductive and remains so. Across capacitor C2 there is a negative voltage by means of which transistor Tr1 is turned off. The inverse base current thereof flows through thyristor Tr2, Tr3. This causes charge to be withdrawn from capacitor C2, while the charge carriers stored in transistor Tr1 are removed with the aid of inductance L3. As soon as the collector current of transistor Tr1 has been turned off, the voltage across winding L2 reverses its polarity, which current recharges the capacitor. Now the voltage at the junction of components C2, R3 and R5 is negative, causing thyristor Tr2, Tr3 to extinguish. Secondary windings L4, L5 and L6 are provided on the core of transformer T with the indicated winding senses. When transistor Tr1 is turned off, a current which recharges a smoothing capacitor C5, C6 or C7 via a rectifier D3, D4 or D5 flows through each of these windings. The voltages across these capacitors are the output voltages of the supply circuit for loads connectable thereto. These loads, which are not shown in the FIGURE, are, for example, portions of a television receiver.
In parallel with winding L1 there is the series network of a 2.2 nF tuning capacitor C8 and a 100 Ohm limiting resistor R8. The anode of a diode D6 is connected to the junction of components R8 and C8, while the cathode is connected to the other terminal of resistor R8. Winding L1 and capacitor C8 form a resonant circuit across which an oscillation is produced after windings L4, L5 and L6 have become currentless. At a later instant the current through circuit L1, C8 reverses its direction. As a result thereof a current is generated in winding L2 which flow
s via diode D2 and resistor R4 to the base of transistor Tr1 and makes this transistor conductive and maintains it in this state. The dissipation in resistor R8 is reduced by means of diode D6. A clamping network formed by the parallel arrangement of a 22 kOhm resistor R9 and a 120 nF capacitor C9 is arranged in series with a diode D7. This whole assembly is in parallel with winding L1 and cuts-off parasitic oscillations which would be produced during the period of time in which transistor Tr1 is non-conductive. The output voltages of the supply circuit are kept substantially constant in spite of variations of voltage V B and/or the loads, thanks to a control of the turning-on instant of thyrisistor Tr2, Tr3. For this purpose the emitter of a light-sensitive transistor Tr4 is connected to the base of transistor Tr3. The collector of transistor Tr4 is connected via a resistor R10 to the conductor which carries the voltage V B and to a Zener diode Z1 which has a positive voltage of approximately 7.5 V, while the base is unconnected. The other end of diode Z1 is connected to ground. A light-emitting diode D8, whose cathode is connected to the collector of an npn-transistor Tr5, is optically coupled to transistor Tr4. By means of a potentiometer R11 the base of transistor Tr5 can be adjusted to a d.c. voltage which is derived from the voltage V 0 of approximately 130 V across capacitor C6. The anode of diode D8 is connected to a d.c. voltage V 1 of approximately 13 V. A resistor R12 is also connected to voltage V 1 , the other end of the resistor being connected to the emitter of transistor Tr5, to the cathode of a Zener diode Z2 which has a voltage of approximately 7.5 V and to a smoothing capacitor C10. The other ends of diode Z2 and capacitor C10 are connected to ground. Voltage V1 can be generated by means of a transformer connected to the electric AC supply and a rectifier, which are not shown for the sake of simplicity, more specifically for a remote control to which constantly supply energy is always applied, even when the majority of the components of the receiver in what is referred to as the stand-by state are not supplied with supply energy. A portion of voltage V 0 is compared with the voltage of diode Z2 by means of transistor Tr5. The measured difference determines the collector current of transistor Tr5 and consequently the emitter current of transistor Tr4. This emitter current produces across resistor R6 a voltage drop whose polarity is the opposite of the polarity of the voltage source formed by resistor R7 and capacitor C4. Under the influence of this voltage drop the turn-on instant of thyristor Tr2, Tr3 is controlled as a function of voltage V 0 . If, for example, voltage V 0 tends to decrease owing to an increasing load thereon and/or in response to a decrease in voltage V B , then the collector current of transistor Tr5 decreases and consequently also the said voltage drop. Thyristor Tr2, Tr3 is turned on at a later instant than would otherwise be the case, causing transistor Tr1 to be cut-off at a later instant. The final value of the collector current of this transistor is consequently higher. Consequently, the ratio of the time interval in which transistor Tr1 is conductive to the entire period, commonly referred to as the duty cycle, increases, while the frequency decreases.
The circuit is protected from overvoltage. This is ensured by a thyristor which is formed by a pnp-transistor Tr6 and an npn-transistor Tr7. The anode of a diode D9 is connected to the junction of components R3 and C2 and the cathode to the base of transistor Tr6 and to the collector of transistor Tr7. The base of transistor Tr7, which base is connected to the collector of transistor Tr6, is connected via a zener diode Z3 to a voltage which, by means of a potentiometer R13 is adjusted to a value derived from the voltage across capacitor C7. The emitter of transistor Tr6 also is connected to the voltage of capacitor C7, more specifically via a resistor R14 and a diode D10. If this voltage increases to above a predetermined value then thyristor Tr6, Tr7 becomes conductive. Since the emitter of transistor Tr7 is connected to ground, the voltage at its collector becomes very low, as a result of which diode D9 becomes conductive, which keeps transistor Tr1 in the non-conducting state. This situation is maintained as long as thyristor Tr6, Tr7 continues to conduct. This conduction time is predominantly determined by the values of capacitor C7, resistor R14 and a resistor R15 connected between the base and the emitter of transistor Tr6. A thyristor is advantageously used here to render it possible to switch off a large current even with a low level signal and to obtain the required hysteresis.
The supply circuit can be brought into the stand-by state by making an npn-transistor Tr8, which is non-conductive in the operating state, conductive. The emitter of transistor Tr8 is connected to ground while the collector is connected to the collector of transistor Tr5 via a 1.8 kOhm resistor R17. A resistor R18 has one end connected to the base of transistor Tr8 and the other end, either in the operating state to ground, or in the stand-by state to a positive voltage of, for example, 5 V. Transistor Tr8 conducts in response to this voltage. An additional, large current flows through diode D8 and consequently also through transistor Tr4, resulting in thyristor Tr2, Tr3 being made conductive and transistor Tr1 being made non-conductive and maintained so. So to all appearances a large control current is obtained causing the duty cycle to be reduced to zero. A condition for a correct operation is that the emitter current of transistor Tr4 be sufficiently large in all circumstances, which implies that the voltage drop produced across resistor R6 by this current is always higher than the sum of the voltage across voltage source R7, C4, of the base-emitter threshold voltage of transistor Tr3 in the conductive state thereof, and of the voltage at the emitter of transistor Tr1. So the said voltage drop must be higher than the sum of the first two voltages, which corresponds to the worst dimensioning case in which the stand-by state is initiated while transistor Tr1 is in the non-conductive state.
If thyristor Tr2, Tr3 conducts, either in the operating state or in the stand-by state, current flows through resistor R16 via the collector emitter path of transistor Tr3 to ground. This current is too small to have any appreciable influence on the behaviour of the circuit. When thyristor Tr2, Tr3 does not conduct, the voltage on the left hand terminal of capacitor C2 is equal to approximately 1 V, while the voltage across the capacitor is approximately -4 V. So transistor Tr1 remains in the non-conductive state and a premature turn-on thereof cannot occur. If in the operating state transistor Tr1 conducts while thyristor Tr2, Tr3 is cut-off, then the current flows through resistor R16 in the same manner as it flows during the start to the base of transistor Tr1, but has relatively little influence as the base current caused by the energy stored in winding L2 is many times larger. If both transistor Tr1 and thyristor Tr2, Tr3 are non-conductive, then the current through resistor R16 flows through components R5, C2, L2, R4, C3 and R1. In this stand-by state capacitor C2 has indeed substantially no negative charge any longer but, in spite thereof, transistor Tr1 cannot become conductive since no current flows to its base. It will furthermore be noted that the circuit is protected in the event that thyristor Tr2, Tr3 has an interruption. Namely, in such a case the circuit cannot start.
In the foregoing a circuit is described which may be considered to be a switched-mode supply voltage circuit of the parallel ("flyback") type. It will be obvious that the invention may alternatively be used in supply voltage circuits of a different type, for example converters of the type commonly referred to as up-converters. It will also be obvious that transistor Tr1 may be replaced by an equivalent switch, for example a gate-turn-off switch. PHILIPS 33DC2080 /20R MATCHLINE RECEIVER VT CHASSIS D16 (DIGI 16) Switched-mode power supply having a standby state: PHILIPS SOPS SUPPLY ST-BY FEATURED.
switched-mode power supply circuit with having an operating state and a stand-by state in which the value of a first output voltage is considerably lower than in the operating state, whereas the value of a second output voltage is substantially the same. With the aid of a duration-determining circuit (Tr7, Tr8, R17, C12) which is controlled by a switch (Tr6) operative during the stand-by state, a low-frequency burst mode is maintained during this state in which the switch of the supply circuit conducts a number of consecutive times and subsequently becomes non-conductive during a given period. As a result the dissipation in the circuit is reduced.
1. A self-oscillating power supply circuit having an operating state and a stand-by state comprising: a pair of terminals for connection to a source of DC voltage, a transformer having a primary winding and at least first and second secondary windings, a first controllable switch connected in series arrangement with the primary winding of the transformer, means coupling said series arrangement to said pair of terminals, said first and second secondary windin
gs supplying first and second DC output
voltages, respectively, in the operating state of the power supply
circuit, a second controllable switch for controlling the power supply
circuit into the stand-by state wherein the first secondary winding
supplies a lower value of the first DC output voltage than in the
operating state, a third controllable switch coupled to the second
secondary winding and controlled by the second switch so that in the
stand-by state the second secondary winding maintains the second output
voltage at approximately the same value as in the operating state, a
comparison stage for comparing an output voltage with a reference
voltage and for generating a control signal for controlling the duration
of periodically occurring drive pulses applied to the first switch, and
a duration-determining circuit controlled by the second switch in the
stand-by state so as to maintain a burst oscillation mode in which the
first switch conducts a number of consecutive times and subsequently is
non-conductive for a given time period and with an oscillation frequency
much lower than the repetition frequency of said drive pulses.
2. A power supply circuit as claimed in claim 1 wherein the first switch comprises a transistor having a control electrode and the transformer further comprises a feedback winding, said power supply circuit further comprising, a turn-on path and a turn-off path coupled to said control electrode, said turn-on path comprising a first series circuit including a capacitor, said feedback winding and a diode, and said turn-off path comprises a second series circuit including said capacitor, a second transistor and an inductor.
3. A power supply circuit as claimed in claim 1 wherein said duration-determining circuit comprises a monostable multivibrator having an RC time constant network.
4. A power supply circuit as claimed in claim 1 wherein the transformer includes a further winding coupled to the second secondary winding via a diode that also rectifies the voltage generated in the second secondary winding thereby to develop said second DC output voltage, means coupling said third switch to said further winding so that operation of the third switch in the stand-by state provides a path for current to flow through the further winding, the turns ratio of the second secondary winding and the further winding being chosen so that said diode conducts during the operating state and is cut-off in the stand-by state of the power supply circuit.
5. A power supply circuit as claimed in claim 1 further comprising, a light emitting diode (LED) controlled by said duration-determining circuit, and a light-sensitive semiconductor element optically controlled by said LED and electrically coupled to a control electrode of the first switch so that the conduction periods of the first switch are determined by the LED in a sense so as to maintain the output voltages of the power supply circuit constant in spite of variations of the DC voltage at said pair of terminals and/or of loads coupled to the secondary windings.
6. A power supply circuit as claimed in claim 1 further comprising a capacitor coupled in parallel with said primary winding to form a parallel resonant circuit.
Description:
BACKGROUND OF THE INVENTION
This invention relates to a switched-mode power supply circuit having an operating state and a standby state and comprising a controllable first switch arranged in series with the primary winding of a transformer. The series arrangement thus formed is coupled to the terminals of a d.c. input voltage. The transformer has a first secondary winding for providing a first d.c. output voltage in the operating state and a second secondary winding for providing a second d.c. output voltage. The circuit also comprises a second switch for bringing the supply circuit into the stand-by state in which the value of the first output voltage is considerably lower than in the operating state, and a third switch controllable by means of the second switch and coupled to the second secondary winding for maintaining the second output voltage in the stand-by state at substantially the same value as in the operating state. The circuit further comprises a comparison stage for comparing an output voltage with a reference voltage and for generating a control signal for controlling the duration of periodically occurring drive pulses applied to the first switch.
A power supply circuit of this type is known from German Patent Application No. 3,223,756. In this known circuit, which is intended for use in a television receiver, both the first output voltage and other output voltages, which are derived from secondary windings of the transformer, have a lower value in the stand-by state than in the operating state so that the power consumption is smaller, while the second output voltage, to which a remote control is connected, has substantially the same value. In the stand-by state the first switch continues to operate normally, though every time with a shorter conduction period than in the operating state. This continuous operation at a high frequency, i.e. 25 to 30 kHz involves, however, quite a considerable power dissipation.
SUMMARY OF THE INVENTION
It is an object of the invention to provide a power supply circuit of the type described above having a lower dissipation relative to that of the known circuit. To this end the power supply circuit according to the invention is characterized in that a duration-determining element is coupled to the second secondary winding and to the comparison stage for maintaining an oscillation mode in the stand-by state. The first switch is conductive a number of consecutive times and subsequently becomes non-conductive during a given period under the influence of the control signal. The frequency of said oscillation is many times lower than the repetition frequency of the drive pulses applied to the first switch.
In accordance with this mode of oscillation the first switch conducts every time for only a short period during which energy is built up in the transformer, and subsequently the switch is rendered non-conducting. Since this is a low-frequency process, of t
he order of, for example,
100 to 200 Hz, the losses, predominantly the losses in the transformer
and in the switch, are fairly low. 
The circuit is advantageously characterized in that the second switch is coupled to the duration-determining element for controlling said element. The duration-determining element then comprises a time constant network. Thus, the second switch controls both the third switch and the duration-determining element.
The circuit according to the invention is preferably characterized in that the comparison stage is controllable by means of the second switch for comparing the second output voltage with a reference voltage during the stand-by state and for generating a control signal during a period determined by the time-constant network. This control signal is suitable for rendering the first switch non-conducting after the first output voltage has reached a given value. This measure ensures that the control circuit remains operative under all circumstances.
BRIEF DESCRIPTION OF THE DRAWINGS
The invention will be described in greater detail by way of example with reference to the accompanying drawing in which:
FIG. 1 is a basic circuit diagram of a power supply circuit according to the invention, and
FIG. 2 shows waveforms occurring therein.
DESCRIPTION OF THE PREFERRED EMBODIMENTS
The
self-oscillating power supply circuit of FIG. 1 comprises an npn power
switching transistor Tr1 whose collector is connected to the primary
winding L1 of a transformer T, while the emitter is connected to ground.
The other end of winding L1 is connected to the positive rail of an
unstabilized power supply source VB whose negative rail is
also connected to ground and which is, for example, a mains rectifier.
The turn-on path of transistor Tr1, which is connected between the base
of the transistor and ground, comprises a capacitor C1, a feedback
winding L2 of transformer T, a diode D1 and a resistor R1. The base
current flowing during the conduction period of transistor Tr1 produces a
negative voltage across capacitor C1. The turn-off path of transistor
Tr1, which is also connected to the base thereof, comprises capacitor
C1, the emitter-collector path of a pnp transistor Tr2 having a
base-emitter resistor R2, and an inductance L3. Upon turn-off a reverse
base current of transistor Tr1 flows through elements C1, Tr2 and L3 so
that the charge carriers stored in this transistor during the conduction
period are removed. A negative voltage for capacitor C1 is generated
with the aid of a further winding L4 of transformer T and a diode D2 in
case the forward base current of transistor Tr1 flows for too short a
time, under given circumstances, to build up a sufficiently constant
voltage across capacitor C1. FIG. 1 shows the winding sense of the
windings of transformer T by means of dots. One end of a winding L5 of transformer T is connected to a diode D3, the other end of which is connected to the series network of a resistor R3 and a capacitor C2. Winding L5 has such a winding sense and diode D3 has such a conductivity direction
that a charge current for capacitor C2 flows through resistor
R3 during the conduction period of transistor Tr1. The bottom end of
capacitor C2 is connected to the junction of capacitor C1, winding L2
and the collector of transistor Tr2. With respect to the d.c. voltage
level present at this junction, a sawtooth voltage is produced across
capacitor C2. This voltage is passed on to the base of an npn transistor
Tr4 via an RC parallel network R4, C3. The emitter of transistor Tr4 is
connected to the said junction, while the collector is connected to the
base of transistor Tr2. At a given instant the voltage at the base of
transistor Tr4 reaches a value at which the transistor is rendered
conducting. As a result transistor Tr2 is also rendered conducting. The
voltage at the emitter of this transistor assumes substantially the same
value as the negative voltage of approximately -5 V which is present
across capacitor C1, which initiates the turn-off of transistor Tr1.
During the period of time when transistor Tr1 is non-conductive,
capacitor C2 is discharged via a resistor R5, a diode D4 and winding L4,
while a reverse current flows through transistor Tr2 which current also
flows through resistor R1 and through a capacitor C4 which is connected
in parallel with diode D1. A starting resistor R6 having a high value is arranged between the positive rail of source VB and the base of transisor Tr2. When the circuit is turned on, a current flows through resistors R6 and R2 which also flows through capacitor C4 and winding L2 so that energy is built up in transformer T. Due to this current the voltage at the base of transistor Tr1 increases until a value is reached at which the transistor becomes conducting. Also during normal operation a current flows through resistor R6, but its value is too low to have a noticeable influence on the behaviour of the circuit.
Secondary windings are provided on t
he core of transformer T. FIG. 1 shows a
number of these windings, for example, L6 and L7. When transistor Tr1 is
turned off, a current for recharging smoothing capacitors C5 and C6
flows via rectifiers, for example, D5 and D6, respectively, through each
secondary winding. The other ends of capacitors C5 and C6 are connected
to ground. The voltages across these capacitors are the output voltages
of the supply circuit for loads connectable thereto. These loads, which
are not shown in FIG. 1, are, for example, parts of a television
receiver. A network comprising a tuning capacitor C7 and a damping resistor R7, as well as a clamping network with a diode D7 is arranged in parallel with winding L1. Winding L1 and capacitor C7, as well as parasitic capacitances, constitute a resonant circuit in which an oscillation is produced in the intervals when transistor Tr1 and rectifiers D5 and D6 carry no current. Parasitic oscillations which might be produced during the period of time when transistor Tr1 is non-conducting are reduced by means of the said clamping network.
The output voltages of the supply circuit are kept substantially constant in spite of variations of the voltage VB and/or of the loads by controlling the conduction periods of transistor Tr1. For this purpose the circuit includes a light-emitting diode D8 which is optically coupled to a light-sensitive npn-transistor Tr5 having an emitter resistor R8 which is connected in the base lead of transistor Tr4, as is the network R4, C3. A collector resistor R9 is connected to the source VB and the base is unconnected. The collector of transistor Tr5 is also connected via an RC parallel network R10, C8 to the junction of windings L2 and L4 and capacitor C1 and is further connected via a diode D9 to the junction of winding L2 and diode D1. A positive voltage is thus present at the said collector. If the current through diode D8 varies in a manner to be described hereinafter, the emitter current of transistor Tr5 also varies. An increase of this current, for example, involves an increase in the voltage at the base
of
transistor Tr4 so that transistor Tr1 is turned off at an earlier
instant than would otherwise be the case. The final value of transistor
Tr1 is thus lower, resulting in the output voltages of the circuit also
being lower. This control is also dependent on variations of the voltage
VB by means of a network comprising a Zener-diode D10 which
is connected between the junction of resistors R4 and R8 and the
junction of resistor R3 and diode D3. The foregoing is well known to those skilled in the art and does not require any further explanation. Further details are therefore not discussed. The same applies to safety precautions against overvoltages and overcurrents which are formed in known manner. For a better understanding of the operation of the circuit, FIG. 2 shows some idealized waveforms: FIG. 2a shows the variation as a function of time of the voltage V across winding L1, i.e. the same variation but for a d.c. level, more specifically that of source VB, as that of the voltage across the collector of transistor Tr1, and FIG. 2b shows the variation of the current i flowing through winding L1.
Transistor Tr1 is turned off at an instant to. Before this instant the current i increases linearly, while the voltage v has the value -VB. After instant to the voltage v increases in accordance with a sine function of time, whereas current i varies in accordance with a cosine function. At an instant t1 voltage v reaches the value of zero and the current i has a maximum value. Voltage v continues to increase until the value is reached at an instant t2 when the rectifi
ers on the secondary side start conducting. If the voltage across capacitor C5 is equal to Vo and if the tranformation ratio of windings L1 and L6 is n:1, voltage v remains equal to nVo after the instant t2, whereas the current i decreases linearly, more specifically until the value of zero is reached at an instant t3. After the instant t3
the rectifiers do not carry any current, and the voltage v decreases in
accordance with a sine function by at the same resonance frequency as
between the instants to and t2, but at a lower peak value, being nVo,
while the current i becomes negative. Current i flows to capacitor C7
and varies in accordance with a cosine function. Without any further
measures a current would thus be produced in winding L2 which would flow
through diode D1 to the base of transistor Tr1. FIGS. 1 and 2a show
that transistor Tr1 would thereby be rendered conducting at an instant
after instant t3 when the sum of the voltage across winding
L2 and the voltage across capacitors C1 and C4 will be lower than the
base-emitter threshold voltage of the transistor. This instant occurs
shortly after instant t3 before the voltage v becomes zero,
that is to say, upon turnon, the voltage at the collector of transistor
Tr1 would be slightly lower than the value VB +nVo. It appears from the foregoing that without any further measures the voltage at the collector of transistor Tr1 is fairly high upon turn-on which causes a considerable switching dissipation in transistor Tr1 and in resistor R7. To reduce the turn-on losses, the circuit of FIG. 1 includes an npn transistor Tr3 whose emitter is connected to the junction of capacitor C1 and winding L2 and whose collector is connected to the base of transistor Tr2 via a diode D11 having the same conductivity direction as the collector-emitter path of transistor Tr3. One end of winding L8 of transformer T is connected to the emitter of transistor Tr3 and the other end is connected to an integrating network consisting of a resistor R11 and a capacitor C9, said capacitor being arranged between resistor R11 and the said emitter. The junction of capacitor C9 and resistor R11 is connected via a limiting resistor R12 to the base of transistor Tr3. The winding sense of winding L8 is such that the voltage at the junction of resistor R11 has the same polarity as the voltage shown in FIG. 2a, that is to say, the voltage under consideration is negative before the instant t1 and positive after this instant. Under these circumstances the voltage v' across capacitor C9 which is proportional to the integral of the voltage at the last-mentioned junction has the same time variation as the current i in FIG. 2b but a polarity opposed thereto. In fact, current i is proportional to the integral of voltage v.
FIG. 2c shows the
variation of the voltage v'. Since both the voltage across winding L8
and the current through capacitor C9 have a mean value of zero over one
oscillation period, the mean value of the voltage v' is also zero. This
means that voltage v' reverses its polarity and becomes positive at an
instant t6 which is located earlier than instant t3.
The time constant of the RC network R11, C9 is chosen so that the
voltage v' will exceed the value of the base-emitter threshold voltage
of transistor Tr3 after instant t3. This shows that this transistor conducts after instant t3 and maintains transistor Tr1 in the non-conducting state in the same manner as transistor Tr4 does at the instant to,
more specifically because transistor Tr2 conducts. Since the base of
transistor Tr1 carries a negative voltage via the conducting transistor
Tr2, while the voltage at the base of transistor Tr3 is positive, a
current would flow through the base-collector diode of transistor Tr3,
which would cause a distortion of the waveforms. This is prevented by
the diode D11. At an instant t4 which occurs one fourth of the resonance period of winding L1 and capacitor C7 later than instant t3, voltage v becomes zero while the current i reaches a minimum value. At an instant t5 voltage v reaches a minimum value, while the current i again becomes zero and subsequently becomes positive. Instants t3 and t5 are symmetrical relative to instant t4 so that the minimum value of the voltage v is substantially equal to -nVo, while the minimum value of the voltage at the collector of transistor Tr1 is substantially equal to VB -nVo. Due to the symmetry, voltage v' decreases to a lower value than the threshold voltage of transistor Tr3 after the instant t5 so that this transistor is rendered non-conducting. The voltage at the base of transistor Tr2 becomes positive so that this transistor also becomes non-conductive resulting in transistor Tr1 being rendered conducting. The voltage at its collector then becomes substantially zero
and consequently voltage v becomes equal to -VB. This state
is maintained while the current i increases linearly until transistor
Tr1 is again rendered non-conducting under the influence of the control,
more specifically at an instant t7 which is located one oscillation period later than instant to, whereafter the variation described is repeated. It is evident from the foregoing that due to the operation of transistor Tr3 the turn-on instant of transistor Tr1 is delayed until the instant t5 when the voltage at the collector of transistor Tr1 has a minimum value. This involves a considerable saving in energy and also extends the life of the transistor. It will be obvious that the delay should be fairly accurate because the voltage v before and after the instant t5 is higher than the minimum value at this instant. In this respect an improvement is obtained by series arranging two diodes D12 and D13 having the same conductivity directions in parallel with capacitor C9, and with the anode of diode D12 connected to the junction of elements R11, R12 and C9. As a result the maximum value of voltage v' at the instant t4 is approximately equal to twice a diode threshold voltage, i.e. approximately 1.4 V. The maximum value of the base-emitter voltage of transistor Tr3 is therefore equal to one threshold voltage, more specifically during a given time interval starting before the instant t4 and ending after this instant. The circuit may be dimensioned in such a manner that this interval substantially coincides with the period between the instants t3 and t5. In one embodiment of the delay circuit the resistors R11 and R12 had values of 8.2 and 2.2 kOhm, respectively, while the capacitance of capacitor C9 was approximately 4.7 n
F, and the frequency of the
oscillation, i.e. the inverse of the period between the instants to and t7, could vary between 25 and 60 kHz. The foregoing description applies to the case where the supply circuit is dimensioned in such a manner that the voltage VB is lower than nVo, in which case the minimum value of the voltage at the collector of transistor Tr1 just before turning on the transistor is positive. In the opposite case the said voltage becomes zero at an instant which is located earlier than instant t5 whereafter a reverse current flows through the base-collector diode of transistor Tr1, while the said voltage is negative. At the instant t5 this current is switched off in the same manner as described above. If necessary, a diode may be connected in parallel with the collector-emitter path of transistor Tr1, which diode has its conductivity direction opposed to this path and through which the reverse current flows. To ensure that no reverse current flows through the transistor, a diode may be arranged in series with the transistor and with the same conductivity direction as this transistor, while the anti-parallel diode is arranged between the junction of the series diode with winding L1 and ground. It will be noted that the dissipation caused by the reverse current is smaller in this case, because the voltage at the collector is maintained at a low value by the conducting anti-parallel diode, than the dissipation caused by the forward current in FIG. 2 which is many times larger, namely proportional to 1/2Cv2 and to the oscillation frequency. In this case C is the capacitance which is effectively in parallel with transistor Tr1. In addition the said reverse current returns to the source VB.
The series arrangement of a diode D14 and a capacitor C10 is connected to a secondary winding L9 of transformer T with the anode of diode D14 connected to the end of winding L9 which is not connected to ground. One end of a further secondary winding L10 of transformer T, which has more turns than winding L9, is connected to the junction of diode D14 and capacitor C10 and the other end is connected to the cathode of a thyristor Th. The anode of thyristor Th is connected to ground. A series arrangement constituted by the emitter-collector path of a pnp transistor Tr6, a diode D15 and a voltage divider consisting of two resistors R13 and R14 is connected in parallel with capacitor C10. The emitter of transistor Tr6 is connected to the inp
ut
of a series control circuit S whose output voltage is smoothed by means
of a capacitor C11. The series arrangement of the emitter-collector path
of a pnp transistor Tr7, a resistor R15 and the above-mentioned
light-emitting diode D8 is connected in parallel with capacitor C11. The
base of an npn transistor Tr8 is connected to the junction of resistors
R13 and R14, while the collector is connected to the base of transistor
Tr7 and to a resistor R16 and the emitter is connected to the cathode
of a Zener-diode D16, the other end of which is connected to ground. The
other end of resistor R16 is connected to the output of circuit S. A
diode D17 is incorporated between the collector of transistor Tr6 and
the cathode-gate of thyristor Th. This diode has the same conductivity
direction as transistor Tr6. An RC-series network R17, C12 is
incorporated between the base of transistor Tr8 and the collector of
transistor Tr7. Finally, a resistor R18 connects the base of transistor
Tr6 to a terminal A. In the normal operating state transistor Tr6 does not conduct because terminal A is either not connected or is connected to a positive voltage. Diode D17 neither does not conduct and consequently thyristor Th does not conduct either. As a result winding L10 remains currentless and capacitor C10 carries a d.c. voltage of, for example, approximately 7 V which is derived from the voltage across winding L9 by means of diode D14. A voltage of, for example, 5 V for a microprocessor in the control section of the receiver and or remote control is present across capacitor C11. Transistors Tr7 and Tr8 also remain non-conducting.
For controlling the output voltages of the supply circuit, this circuit is provided with a further secondary winding L11 of the transformer T, a rectifier D18 and a smoothing capacitor C13. By means of a voltage divider arranged in parallel with capacitor C5 and consistng of resistors R19, R20, R21 and R22, the base of an npn transistor Tr9, which is connected to the junction of resistors R20 and R21, is adjusted to a d.c. voltage which is proportional to the output voltage Vo across capacitor C5. The emitter of transistor Tr9 is connected to a Zener diode D16. The voltage at the base is compared with the voltage of diode D16 by means of transistor Tr9. The difference measure
d determines the collector
current of a pnp transistor Tr10 whose emitter is connected to capacitor
C13 and whose collector is connected via a resistor R23 to the anode of
diode D8 and consequently determines the current through diode D8 and
therefore the emitter current of transistor Tr5. If, for example, the
output voltage increases as a result of a decreasing load and/or as a
result of an increase of voltage VB, the collector current of
transistor Tr9 and consequently the control current through diode D8
also increase. In the manner already explained this increase causes a
reduction in the conductivity period of transistor Tr1, which
counteracts the increase of the output voltage. An RC series network
R24, C14 is incorporated between the base and the collector of
transistor Tr10 for reducing the loop gain at a high frequency, thereby
improving the stability of the control. A diode D19 is arranged between
capacitor C6 and the junction of resistors R19 and R20 and provides a
safety feature in case the diode D5, with which the highest output
voltage Vo is generated, becomes defective. In this case,
when diode D5 is interrupted, the voltage across capacitor C5 becomes
zero. The control then attempts to increase this voltage, but this is
prevented because diode D19 starts conducting so that now the voltage
across capacitor C6 is controlled. By connecting terminal A to ground the supply circuit of FIG. 1 is brought into the stand-by state during which most parts of the television receiver receive very little supply energy. Transistor Tr6 then starts conducting so that current flows through diode D17 to the cathode gate of thyristor Th which also starts conducting, while diode D14 is rendered non-conducting as will be further explained. A current flows through diode D15 to the base of transistor
Tr8 which is rendered conducting so that transistor Tr7 also
becomes conducting. The increase of the voltage at the collector of
transistor Tr7 is passed on to the base of transistor Tr8 by the network
R17, C12. Thus, transistors Tr7 and Tr8 constitute a monostable
multivibrator which remains in its state reached during a period which
is determined, inter alia, by the time constant of network R17, C12,
even after the voltage V1 across capacitor C10 has become low. A part of the voltage V1
is compared with the voltage of Zener diode D16 by means of transistor
Tr8. The difference measured determines the collector current of
transistor Tr7, which current flows through diode D8. The part of the
circuit including winding L10 thus forms part of a control loop for
maintaining the voltage V1 substantially constant, which
control loop is put into operation by switching over to the stand-by
state by means of terminal A. The number of turns of winding L10 has been chosen to be such that during the stand-by state the output voltages of the supply circuit, that is to say, the direct voltages derived from the other secondary windings L6, L7 and L11 are reduced to low values with little power being dissipated in the loads. This may be explained with reference to the following figures. When, for example, winding L6 has 44 turns, L7 has 7 turns, L9 has 2 turns and L10 has 15 turns, respectively, and when the voltage Vo across capacitor C5 is approximately 140 V in the operating state, the voltage across capacitor C6 is ##EQU1## the voltage across cap
acitor C10 is ##EQU2##
and a direct voltage derived from winding L10 by rectification is
##EQU3## When voltage V1 is maintained at 8 V in the stand-by
state, a direct voltage derived from winding L9 by rectification would
be ##EQU4## which shows that diode D14 is not conducting, and the
voltage across capacitor C6 is ##EQU5## while the voltage across
capacitor C5 is ##EQU6## The latter two values are so low that a
synchronizing circuit connected to capacitor C6 and a line deflection
circuit connected to capacitor C5 cannot operate properly, which
produces a very low consumption. The output voltages are proportionally
reduced and the different loads need not be turned off, while the
voltage across capacitor C11 has substantially the same value as in the
operating state. Under these circumstances the conduction period of transistor Tr1, i.e. the interval between the instants t5 and t7
in FIG. 2 becomes increasingly shorter due to the operation of the
control after a switch-over to the stand-by state has been effected.
This conduction period has, however, a minimum value which is determined
by the storage period of the charge carriers in transistor Tr1. During
this period which cannot come, for example, below approximately 3 to 5
μs, the collector current of this transistor increases to a peak value
which depends on the said period and also on the voltage VB
and which, similar to the storage period, is subject to variations
caused by tolerances. Due to this current more energy is stored in
transformer T than is extracted from it so that the output voltages tend
to increase again after having been low. This is, however, prevented by
the control: diode D8 produces such a large control current that
transistor Tr1 is turned off and remains in the non-conducting state
because transistor Tr4 continuously remains conducting due to the large
emitter current of transistor Tr5. In the stand-by state transistor Tr5
has a collector voltage via resistor R9. The output voltages and also
the control current now decrease again because capacitors C5, C6, C10
and C13 are discharged, more specifically until the voltage V1
reaches a value at which the power supply circuit starts again.
Transistor Tr1 becomes conducting in the manner already described,
resulting in the capacitors on the secondary side of transformer T being
charged again. An intermittent current flows through thyristor Th so
that the voltage across capacitor C10 reaches a level at which
transistor Tr8 is rendered conducting again, which restores the control
loop. The process described is subsequently repeated. It is evident from the foregoing that in the stand-by state the supply circuit of FIG. 1 is in a state in which a burst mode is generated, i.e. with an oscillation which is interrupted periodically, in which state very short current pulses flow through transistor Tr1 while the secondary voltages increase, whereafter the transistor is non-conducting while the secondary voltages decrease slowly. The advantage of such a burst mode is that the efficiency is then favourable. In fact, if the supply circuit continuously operated with low or turned-off loads, the frequency of the oscillation would become high because the interval between the instants t2 and t3 in FIG. 2 would become very short. This would involve great losses in the transformer as well as great switching losses in transistor Tr1 and resistor R7. The burst mode is, however, not produced with certainty, particularly not if the value of voltage VB can vary within a large voltage range. Other reasons therefor may be: short storage time of the power transistor and high power consumption in the stand-by state. To ensure that the supply circuit continues to oscillate in the described manner in the stand-by state, that is to say, that it does not come into a continuous state, the monostable multivibrator make up of transistors Tr7 and Tr8 is provided, with which a hysteresis is obtained. Due to the hysteresis transistor Tr7 is maintained conducting for some time during which time a large current continues to flow through diode D8 so that transistor Tr1 remains non-conducting while the output voltages decrease. This "dead period" of the burst mode is determined by the time constant of the network R17, C12, the starting resistor R6 and the capacitor C4 through which the starting current flows. For this oscillation a low freque
ncy of approximately 100 Hz has been found
useful in practice. A substantially constant voltage is obtained with
the aid of a circuit S for the voltage across capacitor C11. The anode of a Zener diode D20 is connected to the cathode of diode D15 and the cathode of diode D20 is connected to capacitor C10. When at an instant when thyristor Th would become inoperative the connection of terminal A to ground is interrupted for switching to the operating state of the receiver, thyristor Th can still remain conducting for some time due to its inertia while the control loop is open. Under these circumstances voltage V1 would tend to increase, more specifically until the voltage across winding L10 reaches the above-mentioned value of 47.7 V. Thanks to diode D20 the voltage across capacitor C10 does not exceed a given value. The supply circuit thus remains in the burst mode for a short time until thyristor Th is extinguished, whereafter the voltage across capacitor C10 is again determined by diode D14.
A further refinement is to connect the
connection of resistor R6, which is not connected to transistor Tr2, to
the junction of two resistors which are not shown for the sake of
simplicity, instead of to source VB as is shown in FIG. 1.
The other connection of each of these resistors is connected to a
terminal of the mains voltage, the said junction being connected to
ground via a capacitor having a low capacitance. If without this measure
the supply is switched off by operating a mains switch while the
receiver is still in the stand-by state, the stand-by state is still
maintained for several seconds due to the burst mode before a signal
lamp is extinguished. This is prevented because the voltage across the
above-mentioned capacitor drops off rapidly so that the starting current
goes rapidly to zero. The supply circuit therefore does not leave the
"dead period" of the burst mode. It may be noted that the output voltages can also be decreased in the stand-by state by decreasing the Zener voltage with which a comparison is made. Compared to the above-described measure a drawback of this measure by which diode D16 is switched over, while the windings L9 and L10 and the components c
onnected thereto are omitted, is that the collector current of
transistor Tr9 is high during the decrease of the output voltages, which
causes a large control current through diode D8 and brings transistor
Tr1 into the non-conducting state. The result thereof is that the supply
circuit does not apply a voltage for quite some time to the remote
control and to the operating microprocessor, which is undesirable. It will be evident that variants which are within the scope of the invention will be apparent for the circuit described. This applies to, for example, transistor Tr1 which may be replaced by an equivalent power switch, for example, a gate turn-off switch. This also applies to a plurality of circuit-technical details, for example, the circuits for turning off transistor Tr1 or for turning on this transistor. Variants can also be considered for the switch-over from and to the stand-by state, for example, for the switch-over facility consisting of transistor Tr6 and thyristor Th which may have a different form, and for winding L9 which may be a winding of a line output transformer or which may be omitted altogether, while the anode of diode D14 is connected to, for example, capacitor C13, and variants can also be considered for the implementation of the mulivibrator made up of transistors Tr7 and Tr8 and of the time-constant network. This also applies to the number of common elements in the first control loop for maintaining the voltage Vo and the other output voltages constant in the operating state, and in the second control loop for maintaining the voltage V1 for the remote control constant in the stand-by state, while the other output voltages are greatly reduced. Similarly, the differential amplifier may be common in both control loops.
It will be evident that the manner in which the stand-by state is maintained, both in the circuit of FIG. 1 and in variants of this circuit, can also be used for other supply circuits: it is important that a circuit is concerned which is designed such that a large control current results in the power switch being switched off. Such a circuit has been described, for example, in U.S. Pat. No. 4,486,822 or in the U.S. Pat. No. 4,631,654. The latter circuit is not self-oscillating.
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