DESCRIPTIONS OF THE UNITS AND THEIR FUNCTIONS:
REX (ZANUSSI) 22RT411 "MADEIRA" CHASSIS BS400 UNITS VIEW:
- BS394.2 POWER SUPPLY WITH BU326A It converts the mains voltage in DC voltage available at five outputs with values of: +2OOV; +15OV; +27V (two outputs); +12.6V. These voltages are stabilized and separated from the mains
- BS395.1 LINE DEFLECTION OUTPUT UNIT WITH BU208A (MOTOROLA) This p.c.b. amplifies the pulse sequence at line frequency and drives a circuit operating as
an ON-OFF switch for supplying the deflection current to the horizontal yoke. It also
receives the parabolic signal which acts on the diodes modulator for E/W correction.
- BS396.3 SYNCHRONIZATION + E/W CORRECTION The p.c.b. processes the video
signal. Said process consists in separating the horizontal signals from the video composite
signal. The "pincushion correction" section receives a Sawtooth shaped signal and converts it into a parabolic shape for E/W correction.
- BS397.1 FRAME DEFLECTION WITH TDA1170 This p.c.b. generates a sawtooth
voltage at frame frequency which is used for driving the vertical deflection yoke. It supplies a
similar voltage to the "pincushion" section of the synchro. separator p.c.b. to obtain the E/W pincushion correction. It supplies a frame frequency pulse which is used for the luminance, chrominance and video amplifier p.c.b. blankings. It receives the vertical synchro.
from the synchro. separator p.c.b. and receives from the chassis a voltage proportional to the beam current.
- BS399.0 LUMINANCE AND CHROMINANCE + RGB AMPLIFIER This p.c.b. processes the
complete composite video signal coming from the IF p.c.b. andsupplies the R-G-B signals to
the picture tube.
- BS398 TUNER + AFC + IF Conversion of the RF signal into an IF signal
(video carrier:39.5 M z; audio carrier:33.5 MHZ).
Detection of the IF signal into low frequency video and audio signals.
- BS389 REMOTE CONTROL DECODER WITH ITT SAA1251 This p.c.b. enables remote
control of the following functions: selection of 16 programmes; "+" or "-" adjustment; brightness
saturation adjustment; silencing; TV receiver switching.
- BS388.2 TUNING MEMORY AND SEARCH Remote control p.c.b. The display indicates the programme selected. Furthermore,this p.c.b. includes all pushbuttons for clock
adjustment.No adjustments needed. Automatic searching of a TV station through a start command. Manual searching of a TV station through two commands (increment and decrement).
Inclusion-exclusion of the AFC circuit with LED display. Band indication displayed on
three LEDs. Tuning level indication with five LEDs. Memorization of 16 selected
programmes manually or remote control.
- BS392.2 ST-BY SUPPLY AND OPTOCOUPLER START STOP FEATURE. The p.c.b. includes circuits relevant to: mains filter, degaussing, remote control supply, start remote control.
Nc adjustments needed. It includes circuits for clock supply and for switch-ON
programming.
- BS401 This p.c.b. receives the audio signal (not adjusted in volume) coming from p.c.b. BS 398, it adjusts it in amplitude and tone, it amplifies it and sends it to drive the two receiver’s loudspeakers (tweeter and woofer).
DESCRIPTIONS OF THE UNITS AND THEIR FUNCTIONS:
- BS394.2 POWER SUPPLY WITH BU326A It
converts the mains voltage in DC voltage available at five outputs
with values of: +2OOV; +15OV; +27V (two outputs); +12.6V. These
voltages are stabilized and separated from the mains.SELECO (ZANUSSI) 22ST303 "BIG" CHASSIS BS400 Switching power supply, especially for a T.V. receiving apparatus:
SELECO (ZANUSSI) 22ST303 "BIG" CHASSIS BS400 Schaltnetzteil
(ZANUSSI BS394 SWITCH MODE POWER SUPPLY), IN GERMAN:
1. Schaltnetzteil,
insbesondere f·ur einen Fernsehempf·anger, mit einer Arbeitswicklung
(5), einem Schalttransistor (6), einer R·uckkopplungswicklung (7) und
einer Regelschaltung (ii) auf der Prim·arseite sowie mit Gleichrichtern
(15,16, 20) zur Erzeugung von Betriebsspannungen (U11U2#U3) auf der
Sekund·arseite eines Trenntransformators (1) gekenn zeichnet durch
folgende Merkmale: a) An eine Wicklung (19) ist ein Thyristor (24)
angeschlos sen, der f·ur die w·ahrend der siromf·uhrenden Phase der
Schalttransistoren (6) an der Wicklung (19) auftreten de Spannung in
Durchlassrichtung gepolt ist. b) An die Steuerelektrode des Thyristors
(24) ist eine der Betriebsspannungen (U2) in solcher H·ohe angelegt,
dass der Thyristor (24) im Normalbetrieb gesperrt bleibt und bei einem
unzul·assigen Anstieg der Betriebs spannung (U3) z·undet.
2. Netzteil nach Anspruch 1, dadurch gekennzeichnet, dass die Betriebsspannung (U3) ·uber einen Spannungsteiler (25,26) an die Steuerelektrode des Thyristors (24) angelegt ist.
3. Netzteil nach Anspruch 1, dadurch gekennzeichnet, dass die Wicklung (19) eine Sekund·arwicklung des Trenntransforma tors (1) ist.
Description:
Schaltnetzteil, insbesondere f·ur einen Fernsehempf·anger
Bei
Ger·aten der Nachrichtentechnik wie z.B. einem Fernsehempf·anger ist es
bekannt, die f·ur die einzelnen Stufen notwendigen Betriebsspannungen
mit einem Schaltnetzteil aus der Netzspannung zu erzeugen (Funkschau
1975, Heft 5, Seite 40-43). Ein Schaltnetzteil erm·oglicht die f·ur den
Anschluss ·ausserer Ger·ate und f·ur die Massnahmen zur Schutzisolierung
vorteilhafte galvanische Trennung der Empf·angerschaltung vom Netz. Da
ein Schaltnetzteil mit einer gegen·uber der Netzfrequenz hohen Frequenz
von ca. 30 kHz arbeitet, kann der zur galvanischen Trennung dienende
Trenntransformator gegen·uber einem Netztrafo f·ur 50 Hz wesentlich
kleiner und leichter ausgebildet sein. Durch mehrere Wicklungen oder
Wicklungsabgriffe und angeschlossene Gleichrichter k·onnen auf der
Sekund·arseite des Trenntransformators Betriebs~ spannungen
unterschiedlicher Gr·osse und Polarit·at erzeugt werden.
Ein solches Schaltnetzteil enth·alt eine Regelschaltung zur Stabilisierung der Amplitude der auf der Sekund·arseite erzeugten Betriebsspannungen. In dieser Regelschaltung wird eine durch Gleichrichtung der Impulsspannung am Trafo gewonnene Stellgr·osse erzeugt und mit einer Bezugsspannung verglichen. In Abh·angigkeit von der Abweichung wird der Schaltzeitpunkt des auf der Prim·arseite vorgesehenen elektronischen Schalters so gesteuert, dass die Amplitude der erzeugten Betriebsspannungen konstant bleibt.
Bei einem solchen Schaltnetzteil kann die genannte Regelschaltung z.B. durch ein fehlerhaftes Bauteil ausfallen. Die Regelung der Amplitude der erzeugten Betriebsspannungen ist dann unkontrolliert. Die Betriebsspannungen k·onnen dann auf den doppelten oder dreifachen Wert ansteigen. Dadurch besteht die Gefahr, dass das Schaltnetzteil oder die an die Betriebsspannungen angeschlossenen Verbraucher wie z.B. der Heizfaden der Bildr·ohre oder der Zeilenendstufentransistor zerst·ort werden. Der Anstieg der Betriebsspannungen kann dar·uberhinaus einen Anstieg der im Fernsehempf·anger erzeugten Hochspannung und dadurch eine R·ontgenstrahlung ausl·osen.
Es ist auch ein Schaltnetzteil bekannt (DE-OS 27 27 332), bei dem zum Schutz gegen einen zu starken Anstieg der erzeugten Betriebsspannungen aus der Impulsspannung an der Prim·arseite des Trafos eine Stellgr·osse gewonnen wird, die beim ·Uberschreiten eines Schwellwertes den R·uckkopplungsweg unwirksam steuert. Durch die Unterbrechung des R·uckkopplungsweges kann das Schaltnetzteil nicht mehr schwingen, so dass in erw·unschter Weise auch keine Betriebsspannungen mehr erzeugt werden. Diese Schaltung erfordert jedoch eine Vielzahl von Bauteilen und ist daher relativ teuer.
Der Erfindung liegt die Aufgabe zugrunde, eine sicher wirkende Schutzschaltung mit verringertem Schaltungsaufwand gegen
die oben
beschriebenen Gefahren zu schaffen.
Diese Aufgabe wird durch die im Anspruch 1 beschriebene Erfindung gel·ost. Vorteilhafte Weiterbildungen der Erfindung sind in den Unteranspr·uchen beschrieben.
Die Erfindung beruht auf folgender ·Uberlegung: Der Schalttransistor auf der Prim·arseite wird von der prim·arseitigen R·uckkopplungswicklung w·ahrend seiner stromleitenden Phase mit einem Basisstrom angesteuert. Wenn jetzt eine Sekund·arwicklung w·ahrend dieser stromleitenden Phase stark belastet, z.B. ·uber den Thyristor kurzgeschlossen wird, bricht auch die Spannung an der prim·arseitigen R·uckkopplungswicklung zusammen. Diese Wicklung kann dann f·ur den Schalttransistor nicht mehr einen f·ur den leitenden Betrieb ausreichenden Basis strom liefern. Das Schaltnetzteil schwingt dann nicht mehr, so dass die sekund·arseitigen Betriebsspannungen in erw·unschter Weise zusammenbrechen. Der schaltungstechni- sche Aufwand ist gering. Er besteht vorzugsweise aus einem Thyristor und zwei Widerst·anden.
Ein Ausf·uhrungsbeispiel der Erfindung wird anhand der Zeichnung erl·autert. Darin zeigen Figur 1 ein erfindungsgem·ass ausgebildetes Schaltnetzteil und Figur 2 Kurven zur Erl·auterung der Wirkungsweise. Dabei zeigen die kleinen Buchstaben, an welchen Punkten in Figur 1 die Spannungen gem·ass Figur 2 stehen.
Das
Schaltnetzteil gem·ass Figur 1 enth·alt auf der Prim·arseite des
Trenntransformators 1 den Netzgleichrichter 2, den Ladekondensator 3,
den Strom-Messwiderstand 4, die Prim·arwicklung 5 den Schalttransistor
6, die zur Schwingungserzeugung dienende R·uckkopplungswicklung 7, den
zur Steuerung des Schalttransistors 6 dienenden Thyristor 8, die
Regelwicklung 9, den zur Erzeugung der Regelspannung dienenden
Gleichrichter 10 sowie die zur Stabilisierung der Betriebsspannungen
dienende Regelschaltung 11 mit dem Transistor 12 und der eine
Referenzspannung lieferndenZenerdiode 13. Die Sekund·arwicklung 14
liefert ·uber den Gleichrichter 15 eine erste Betriebsspannung U1 von
150 V. Ein Abgriff der Wicklung 14 liefert ·uber den Gleichrichter 16
eine zweite Betriebsspannung U2 von 12 V f·ur einen
Fernbedienungsempf·anger.
Eine weitere Sekund·arwicklung 19 liefert ·uber den Gleichrichter 20 eine dritte Betriebsspannung U3 von 12 V. Die Polung der Wicklungen 14,19 und der Gleichrichter 15,16,20 ist derart, dass die Gleichrichter 15,16,20 w·ahrend der Sperrphase des Schalttransistors 6 durch die sekund·arseitig auftretenden Impulsspannungen leitend gesteuert sind und die angeschlossenen Ladekondensatoren aufladen.
An das untere Ende der Wicklung 19 ist zus·atzlich der Thyristor 24 angeschlossen. An die Steuerelektrode b des Thyristors 24 ist die Betriebs spannung U2 ·uber den Spannungsteiler 25,26 angelegt.
Die Wirkungsweise der Schaltung wird anhand der Figur 2 erl·autert. Es sei angenommen, dass das Schaltnetzteil im Zeitpunkt tl in Betrieb genommen wird. Mit der Diode 21 wird aus der Netzspannung am Punkt d ein positiver Impuls erzeugt. Dieser gelangt ·uber den Kondensator 23 auf die Basis des Schalttransistors 6 und steuert diesen leitend. Dadurch beginnt das Schaltnetzteil zu schwingen, wobei die Schwingung durch die R·uckkopplungswicklung 7
aufrechterhalten wird. Am Punkt a entsteht dann eine m·aanderf·ormige
Wechselspannung mit einer Frequenz von etwa 25-30 kHz.
Die daraufhin in den Sekund·arwicklungen 14,19 erzeugten Impulse erzeugen in der beschriebenen Weise die Betriebsspannungen U1,U2,U3. Der Spannungsteiler 25,26 ist so bemessen, dass der Thyristor 24 gesperrt bleibt, d.h. die Spannung am Punkt 6 jst kleiner als 0,7 V. Der Thyristor 24 hat dann keine Wirkung. Dir Amplitude der Spannungen Ui,U2,U3 wird ·uber die Regelschaltung 11 stabilisiert.
Es sei jetzt angenommen, dass durch einen Fehler in der Regelschaltung 11, z.B. durch Ausfall eines Bauteiles, die Regelung zur Stabilisierung der Betriebsspannungen U1,U2,U3 nicht mehr wirkt und diese Betriebsspannungen stark ansteigen. Dadurch steigt auch die Spannung am Punkt b an.
Im Zeitpunkt t2 erreicht diese Spannung den Wert von 0,7 V, so dass der Thyristor 24 z·undet. Der untere Teil der Wicklung 19 ist jetzt praktisch kurzgeschlossen. Das Netzteil ist dadurch sekund·arseitig so stark belastet, dass die R·uck kopplungswicklung 7 keinen ausreichenden Basisstrom zur Steuerung des Schalttransistors 6 in seine stromleitende Phase mehr liefert. Im Zeitpunkt t2 bricht die Schwingung des Schaltnetzteiles ab, so dass auch die Wechselspannung am Punkt a auf null abf·allt. Den Ladekondensatoren der Gleichrichter 15,16,20 wird kein Strom mehr zugef·uhrt, so dass die Betriebspannungen U1,U2,U3 nicht weiter ansteigen k·onnen, sondern entsprechend den wirksamen Entladezeitkonstanten abfallen. Das Schaltnetzteil w·urde auf diese Weise an sich beliebig lange ausgeschaltet bleiben.
Im Zeitpunkt t3 erscheint am Punkt b der n·achste aus der Netzspannung gewonnene Startimpuls, der den Schalttransistor 6 wieder leitend steuert, so dass die Wechselspannung am Punkt a wieder auftritt. Das Schaltnetzteil geht also in einen getakteten Betrieb ·uber, bei dem die ·ubertragene Leistung entsprechend dem Zeitverh·altnis zwischen Einschaltphase und Ausschaltphase der Spannung am Punkt a betr·achtlich verringert ist. Die Betriebsspannungen U11U2,U3 k·onnen nicht mehr unzul·assig hohe Werte annehmen.
Ein solches Schaltnetzteil enth·alt eine Regelschaltung zur Stabilisierung der Amplitude der auf der Sekund·arseite erzeugten Betriebsspannungen. In dieser Regelschaltung wird eine durch Gleichrichtung der Impulsspannung am Trafo gewonnene Stellgr·osse erzeugt und mit einer Bezugsspannung verglichen. In Abh·angigkeit von der Abweichung wird der Schaltzeitpunkt des auf der Prim·arseite vorgesehenen elektronischen Schalters so gesteuert, dass die Amplitude der erzeugten Betriebsspannungen konstant bleibt.
Bei einem solchen Schaltnetzteil kann die genannte Regelschaltung z.B. durch ein fehlerhaftes Bauteil ausfallen. Die Regelung der Amplitude der erzeugten Betriebsspannungen ist dann unkontrolliert. Die Betriebsspannungen k·onnen dann auf den doppelten oder dreifachen Wert ansteigen. Dadurch besteht die Gefahr, dass das Schaltnetzteil oder die an die Betriebsspannungen angeschlossenen Verbraucher wie z.B. der Heizfaden der Bildr·ohre oder der Zeilenendstufentransistor zerst·ort werden. Der Anstieg der Betriebsspannungen kann dar·uberhinaus einen Anstieg der im Fernsehempf·anger erzeugten Hochspannung und dadurch eine R·ontgenstrahlung ausl·osen.
Es ist auch ein Schaltnetzteil bekannt (DE-OS 27 27 332), bei dem zum Schutz gegen einen zu starken Anstieg der erzeugten Betriebsspannungen aus der Impulsspannung an der Prim·arseite des Trafos eine Stellgr·osse gewonnen wird, die beim ·Uberschreiten eines Schwellwertes den R·uckkopplungsweg unwirksam steuert. Durch die Unterbrechung des R·uckkopplungsweges kann das Schaltnetzteil nicht mehr schwingen, so dass in erw·unschter Weise auch keine Betriebsspannungen mehr erzeugt werden. Diese Schaltung erfordert jedoch eine Vielzahl von Bauteilen und ist daher relativ teuer.
Der Erfindung liegt die Aufgabe zugrunde, eine sicher wirkende Schutzschaltung mit verringertem Schaltungsaufwand gegen
die oben
beschriebenen Gefahren zu schaffen.Diese Aufgabe wird durch die im Anspruch 1 beschriebene Erfindung gel·ost. Vorteilhafte Weiterbildungen der Erfindung sind in den Unteranspr·uchen beschrieben.
Die Erfindung beruht auf folgender ·Uberlegung: Der Schalttransistor auf der Prim·arseite wird von der prim·arseitigen R·uckkopplungswicklung w·ahrend seiner stromleitenden Phase mit einem Basisstrom angesteuert. Wenn jetzt eine Sekund·arwicklung w·ahrend dieser stromleitenden Phase stark belastet, z.B. ·uber den Thyristor kurzgeschlossen wird, bricht auch die Spannung an der prim·arseitigen R·uckkopplungswicklung zusammen. Diese Wicklung kann dann f·ur den Schalttransistor nicht mehr einen f·ur den leitenden Betrieb ausreichenden Basis strom liefern. Das Schaltnetzteil schwingt dann nicht mehr, so dass die sekund·arseitigen Betriebsspannungen in erw·unschter Weise zusammenbrechen. Der schaltungstechni- sche Aufwand ist gering. Er besteht vorzugsweise aus einem Thyristor und zwei Widerst·anden.
Ein Ausf·uhrungsbeispiel der Erfindung wird anhand der Zeichnung erl·autert. Darin zeigen Figur 1 ein erfindungsgem·ass ausgebildetes Schaltnetzteil und Figur 2 Kurven zur Erl·auterung der Wirkungsweise. Dabei zeigen die kleinen Buchstaben, an welchen Punkten in Figur 1 die Spannungen gem·ass Figur 2 stehen.
Eine weitere Sekund·arwicklung 19 liefert ·uber den Gleichrichter 20 eine dritte Betriebsspannung U3 von 12 V. Die Polung der Wicklungen 14,19 und der Gleichrichter 15,16,20 ist derart, dass die Gleichrichter 15,16,20 w·ahrend der Sperrphase des Schalttransistors 6 durch die sekund·arseitig auftretenden Impulsspannungen leitend gesteuert sind und die angeschlossenen Ladekondensatoren aufladen.
An das untere Ende der Wicklung 19 ist zus·atzlich der Thyristor 24 angeschlossen. An die Steuerelektrode b des Thyristors 24 ist die Betriebs spannung U2 ·uber den Spannungsteiler 25,26 angelegt.
Die Wirkungsweise der Schaltung wird anhand der Figur 2 erl·autert. Es sei angenommen, dass das Schaltnetzteil im Zeitpunkt tl in Betrieb genommen wird. Mit der Diode 21 wird aus der Netzspannung am Punkt d ein positiver Impuls erzeugt. Dieser gelangt ·uber den Kondensator 23 auf die Basis des Schalttransistors 6 und steuert diesen leitend. Dadurch beginnt das Schaltnetzteil zu schwingen, wobei die Schwingung durch die R·uckk
opplungswicklung 7
aufrechterhalten wird. Am Punkt a entsteht dann eine m·aanderf·ormige
Wechselspannung mit einer Frequenz von etwa 25-30 kHz.Die daraufhin in den Sekund·arwicklungen 14,19 erzeugten Impulse erzeugen in der beschriebenen Weise die Betriebsspannungen U1,U2,U3. Der Spannungsteiler 25,26 ist so bemessen, dass der Thyristor 24 gesperrt bleibt, d.h. die Spannung am Punkt 6 jst kleiner als 0,7 V. Der Thyristor 24 hat dann keine Wirkung. Dir Amplitude der Spannungen Ui,U2,U3 wird ·uber die Regelschaltung 11 stabilisiert.
Es sei jetzt angenommen, dass durch einen Fehler in der Regelschaltung 11, z.B. durch Ausfall eines Bauteiles, die Regelung zur Stabilisierung der Betriebsspannungen U1,U2,U3 nicht mehr wirkt und diese Betriebsspannungen stark ansteigen. Dadurch steigt auch die Spannung am Punkt b an.
Im Zeitpunkt t2 erreicht diese Spannung den Wert von 0,7 V, so dass der Thyristor 24 z·undet. Der untere Teil der Wicklung 19 ist jetzt praktisch kurzgeschlossen. Das Netzteil ist dadurch sekund·arseitig so stark belastet, dass die R·uck kopplungswicklung 7 keinen ausreichenden Basisstrom zur Steuerung des Schalttransistors 6 in seine stromleitende Phase mehr liefert. Im Zeitpunkt t2 bricht die Schwingung des Schaltnetzteiles ab, so dass auch die Wechselspannung am Punkt a auf null abf·allt. Den Ladekondensatoren der Gleichrichter 15,16,20 wird kein Strom mehr zugef·uhrt, so dass die Betriebspannungen U1,U2,U3 nicht weiter ansteigen k·onnen, sondern entsprechend den wirksamen Entladezeitkonstanten abfallen. Das Schaltnetzteil w·urde auf diese Weise an sich beliebig lange ausgeschaltet bleiben.
Im Zeitpunkt t3 erscheint am Punkt b der n·achste aus der Netzspannung gewonnene Startimpuls, der den Schalttransistor 6 wieder leitend steuert, so dass die Wechselspannung am Punkt a wieder auftritt. Das Schaltnetzteil geht also in einen getakteten Betrieb ·uber, bei dem die ·ubertragene Leistung entsprechend dem Zeitverh·altnis zwischen Einschaltphase und Ausschaltphase der Spannung am Punkt a betr·achtlich verringert ist. Die Betriebsspannungen U11U2,U3 k·onnen nicht mehr unzul·assig hohe Werte annehmen.
- BS395.1 LINE DEFLECTION OUTPUT UNIT WITH BU208A (MOTOROLA) This p.c.b. amplifies the pulse sequence at line frequency and drives a circuit operating asan ON-OFF switch for supplying the deflection current to the horizontal yoke. It also
receives the parabolic signal which acts on the diodes modulator for E/W correction.
- BS396.3 SYNCHRONIZATION + E/W CORRECTION The p.c.b. processes the videosignal. Said process consists in separating the horizontal signals from the video composite
signal. The "pincushion correction" section receives a Sawtooth shaped signal and converts it into a parabolic shape for E/W correction.
- BS397.1 FRAME DEFLECTION WITH TDA1170 This p.c.b. generates a sawtoothvoltage at frame frequency which is used for driving the vertical deflection yoke. It supplies a
similar voltage to the "pincushion" section of the synchro. separator p.c.b. to obtain the E/W pincushion correction. It supplies a frame frequency pulse which is used for the luminance, chrominance and video amplifier p.c.b. blankings. It receives the vertical synchro.
from the synchro. separator p.c.b. and receives from the chassis a voltage proportional to the beam current.TDA1170 vertical deflection FRAME DEFLECTION INTEGRATED CIRCUITGENERAL DESCRIPTION f The TDA1170 and TDA1270 are monolithic integrated
circuits designed for use in TV vertical deflection systems. They are manufactured using
the Fairchild Planar* process.
Both devices are supplied in the 12-pin plastic power package with the heat sink fins bent
for insertion into the printed circuit board.
The TDA1170 is designed primarily for large and small screen black and white TV
receivers and industrial TV monitors. The TDA1270 is designed primarily for driving
complementary vertical deflection output stages in color TV receivers and industrial
monitors.
APPLICATION INFORMATION (TDA1170)
The vertical oscillator is directly synchronized by the sync pulses (positive or negative); therefore its free
running frequency must be lower than the sync frequency. The use of current feedback causes the yoke
current to be independent of yoke resistance variations due to thermal effects, Therefore no thermistor is
required in series with the yoke. The flyback generator applies a voltage, about twice the supply voltage, to
the yoke. This produces a short flyback time together with a high useful power to dissipated power
ratio.
- BS399.0 LUMINANCE AND CHROMINANCE + RGB AMPLIFIER This p.c.b. processes thecomplete composite video signal coming from the IF p.c.b. andsupplies the R-G-B signals to
the picture tube.
- BS398 TUNER + AFC + IF Conversion of the RF signal into an IF signal(video carrier:39.5 M z; audio carrier:33.5 MHZ).
Detection of the IF signal into low frequency video and audio signals.
- BS389 REMOTE CONTROL DECODER WITH ITT SAA1251 This p.c.b. enables remotecontrol of the following functions: selection of 16 programmes; "+" or "-" adjustment; brightness
saturation adjustment; silencing; TV receiver switching.
- BS388.2 TUNING MEMORY AND SEARCH
Remote control p.c.b. The display indicates the programme selected.
Furthermore,this p.c.b. includes all pushbuttons for clockadjustment.No adjustments needed. Automatic searching of a TV station through a start command. Manual searching of a TV station through two commands (increment and decrement).
Inclusion-exclusion of the AFC circuit with LED display. Band indication displayed on
three LEDs. Tuning level indication with five LEDs. Memorization of 16 selected
programmes manually or remote control.
- BS392.2 ST-BY SUPPLY AND OPTOCOUPLER START STOP FEATURE. The p.c.b. includes circuits relevant to: mains filter, degaussing, remote control supply, start remote control.Nc adjustments needed. It includes circuits for clock supply and for switch-ON
programming.
- BS401 This p.c.b. receives the audio signal (not adjusted in volume) coming from p.c.b. BS 398, it adjusts it in amplitude and tone, it amplifies it and sends it to drive the two receiver’s loudspeakers (tweeter and woofer).
BU208A (MOTOROLA). Silicon NPN
npn transistors,pnp transistors,transistorsCategory: NPN Transistor, Transistor
MHz: <1 MHz
Amps: 5A
Volts: 1500V
HIGH VOLTAGE CAPABILITY
JEDEC TO-3 METAL CASE.
DESCRIPTION
The BU208A, BU508A and BU508AFI are
manufactured using Multiepitaxial Mesa
technology for cost-effective high performance
and use a Hollow Emitter structure to enhance
switching speeds.
APPLICATIONS:
* HORIZONTAL DEFLECTION FOR COLOUR TV With 110° or even 90° degree of deflection angle.
ABSOLUTE MAXIMUM RATINGS
Symbol Parameter Value Unit
VCES Collector-Emit ter Voltage (VBE = 0) 1500 V
VCEO Collector-Emit ter Voltage (IB = 0) 700 V
VEBO Emitter-Base Voltage (IC = 0) 10 V
IC Collector Current 8 A
ICM Collector Peak Current (tp < 5 ms) 15 A
TO - 3 TO - 218 ISOWATT218
Ptot Total Dissipation at Tc = 25 oC 150 125 50 W
Tstg Storage Temperature -65 to 175 -65 to 150 -65 to 150 oC
Tj Max. Operating Junction Temperature 175 150 150 °C
REX (ZANUSSI) 22RT411 "MADEIRA" CHASSIS BS400 UNITS VIEW
CHASSIS BS400 Television receiver with an automatic station finding arrangement:
The present invention relates to a television tuning device, comprising a circuit for continuously scanning at least one band of receivable frequencies, and having control means for starting and stopping the said scanning procedure and a terminal for applying a switch signal for switching from a first band-scanning speed to a second band-scanning speed slower than the first.
The name usually applied to a unit consisting of circuits of this type for selecting and memorising a given number of preferred channels is "station memory".
Many types of station memories are already being sold on the market which can be divided into two main groups: those with automatic and those with manual television channel searching.
The automatic types are fitted with electronic searching circuits which locate television channels automatically when started by the user. This is done by scanning a given band (VHF or UHF, for example) and stopping on the located channel. Data relative to the located channel can then be memorised by the user in a memory circuit and the same channel recalled whenever required by simply pressing a button which recalls the said data from the memory and supplies it to the channel selection circuit.
This type of circuit is also fitted with components which sense, during search, if a television channel has been tuned into and disable automatic searching to prevent television band scanning from continuing. Most of these circuits are fitted with a phase detector which senses the coincidence between the sync signals received and those regenerated in the receiver (in particular, the flyback signal).
Manual station memories, on the other hand, are fitted with controls which, when activated by the user, start a device for scanning a given television band. These controls also stop the said device when required by the user. When the user sees the required channel appear on the screen, the device is stopped to disable search and enable the channel to be memorised in the appropriate circuit.
In these cases, the simplest way of starting and stopping the search is to fit the circuits with a button which, when pressed, supplies a search-start signal and, when released, stops the searching operation. For best tuning, two buttons are usually provided for band scanning in both directions.
Both the types discussed up to now present drawbacks. In the case of automatic station memories, for example, tuning quality depends on correct operation of all the search-stop circuits and the automatic tuning circuit (AFC=automatic frequency control). Even in cases where these circuits are operating correctly, tuning could still be impaired by noise or amplitude distortion on the received signal.
Tuning quality on manual station memories, on the other hand, depends on the tuning ability of the user. Television receivers can be manipulated by anybody not all of whom are gifted with this ability. A further drawback of manual station memories is that the user has very little time in which to decide whether the received channel is the right one and to estimate tuning quality. If the whole television band is to be scanned in a reasonable length of time (let us say, the UHF band in one minute) band-scanning speed needs to be fairly high. Consequently, if the user is not quick enough in sending out the search-stop control signal, it is more than likely that the control will be sent when the required television channel has been overshot. If, by chance, there are two channels close to one another, the searching device may even stop on the second of the two, thus confusing the user who will not know which of the two channels he has tuned into.
The aim of the present invention is to provide a tuning device to overcome these problems.
With this aim in view, the present invention provides a television tuning device comprising a circuit for continuously scanning at least one band of receivable frequencies, manual control means for starting and stopping the said scanning procedure, a terminal for applying a switch signal for switching from a first band-scanning speed to a second band-scanning speed lower than the first, and detection means for detecting the presence of a television channel by comparing the received sync signals with local signals generated in the television receiver, and applying a switch signal to the said terminal for switching from the said first scanning speed to the said second scanning speed in the presence of the said switch signal, so that the band scanning continues at said lower speed until the manual control means produce the stopping scanning procedure.
MOTOROLA TUNING MEMORY / MEMOTRONIC SYSTEM TECHNOLOGY.
UAA1008A-DP + MC14426P + MC14429P-A
In a radio or television receiver containing an automatic station finder with a digital counter, a clock generator, and a digital-to-analog converter forming the tuning voltage for the varactors, a recall memory consisting of two series-connected parallel memories is connected in parallel with the digital counter. At a stop signal from the
1. A receiver having automatic station finding capability, comprising:
means for tuning said receiver in response to an applied voltage;
a controllable pulse generator;
means for starting said pulse generator;
circulating counter means having parallel inputs and outputs, a stepping input and a set input, said stepping input connected to and responsive to pulses from said pulse generator for providing a variable digital output;
digital-to-analog convert
means for sensing a received signal and for providing a stop signal to the pulse generator in response thereto, whereby said generator stops providing pulses and the analog voltage remains constant keeping the receiver tuned to the received signal;
memory means having parallel inputs connected to the parallel outputs of said counter means and parallel outputs connected to the parallel inputs of said counter means;
means associated with said memory means for causing the memory means to store a particular digital output from said counter means; and
means associated with the set input of said counter means for selectively causing the digital signal at the counter input to be transferred to the counter output.
2. A receiver as described in claim 1, wherein the memory means comprises: two series connected parallel memories each having a transfer input, a first of said parallel memories having parallel inputs connected to the parallel outputs of the counter means and having the transfer input connected to the stop signal means, a second of said parallel memories having parallel outputs connected to the parallel inputs of the counter means and having the transfer input connected to the means for starting said pulse generator.
3. A receiver as described in claim 2, wherein each of said parallel memories comprises a plurality of semiconductor voltage flip-flops.
4. A receiver as described in claim 2, wherein the two series connected parallel memories are incorporated in an integrated circuit module with the counter means.
5. A receiver as described in claim 2, wherein the transfer input of the first parallel memory is also connected to the means associated with the set input of the counter means.
6. A receiver as described in claim 1, additionally comprising:
an additional memory means having parallel inputs and outputs;
means for connecting the inputs of said additional memory means to the counter means output and the outputs of said additional memory means to the counter inputs;
means for causing said additional memory means to store a digital output; and
means for transferring the stored digital output to the counter means input through the connecting means.
7. A receiver as described in claim 6, additionally comprising gate means disposed at the outputs of the memory means and the additional memory means for selectively connecting either the additional memory means or the memory means to the input of the counter.
8. A receiver as described in claim 6, wherein the additional memory means comprises a plurality of memories and the connecting means comprises a plurality of station switches corresponding in number to the number of additional memories.
9. A receiver as described in claim 1, wherein each memory means comprises a number of flip-flops corresponding to the number of digits to be stored.
Description:
The p
resent invention relates to a radio or television receiver with an automatic station finding arrangement which contains a pulse generator, a circulating counter formed from semiconductor counting flip-flops and having parallel inputs, a digital-to-analog converter converting the count of the counter to a tuning voltage, and a start-stop circuit acting on the flow of counting pulses and controlled over a start and at least one stop line, and with a parallel memory connected between the parallel outputs and parallel inputs of the counter.
Such a radio receiver is known from, e.g., the journal "Funkschau 1971", pp. 535 to 538 and 587 to 589. With the aid of the free-running pulse generator, the up-counter, and the digital-to-analog converter, the automatic station finding arrangement generates a sawtoothlike tuning voltage for the varactors contained as frequency-setting tuning elements in the resonant circuits of the receiver's radio-frequency portion. If a transmitter is received which meets the receiving criteria set in the receiver, the pulse generator is stopped so that the tuning voltage now remains constant until the operator continues the automatic station finding operation by actuating a start switch.
It is frequently desirable to tune in once again the station at which the start switch for automatic station finding was actuated last - either for comparison or because of the more interesting program. To do this in the case of a receiver with provision for unidirectional automatic station search, the entire search range must be scanned once or several times by repeatedly actuating the start switch, depending on whether the desired station is detected immediately or not.
It is the object of the invention to provide measures for a receiver of the kind referred to by way of introduction which permit the transmitter received before the actuation of the start switch to be found again with a high degree of safety by simple manipulation.
The invention is characterized in that the parallel memory consists of two series-connected parallel memories having one transfer input each, that the transfer input of the (first) parallel memory, whose parallel inputs are connected to the parallel outputs of the counter, are connected directly or indirectly to the stop line, that the transfer input of the (second) parallel memory, whose parallel outputs are connected to the parallel inputs of the counter, is connected directly or indirectly to the start line, that the counter has a set input for through-connecting the parallel inputs of the counter to the flip-flops of the counter, and that a recall switch is connected to the set input of the counter.
Particularly advantageously, the memory locations of the two series-connected parallel memories are storage flip-flops using semiconductor technology. In that case it is possible to arrange the counter and the parallel memories on a common chip of an integrated-circuit module. Such a module has only two terminals more than a module formed by the counter only.
The measures characterized by the invention thus require, aside from an additional recall switch, no additional space and involve nearly no additional expense. To recall the station previously tuned in it is only necessary to depress a button, for example, whereby the receiver is safely tuned to the station's carrier wave even if at the instant of the depression the local received field strength is temporarily too low for sufficient reception.
The invention will now be described in more detail with reference to the accompanying drawing, showing, by way of example, two embodiments of the invention, and wherein:
FIG. 1 is a block diagram showing the radio- and intermediate-frequency portions of a receiver with an automatic station finding arrangement and a recall arrangement;
FIG. 2 shows diagrams a to g explaining the operation of the recall storage, and
FIG. 3 shows a receiver similar to the one of FIG. 1 in which the automatic station finding counter and the recall memories are arranged together on the chip of an integrated-circuit module.
The receivers shown in the block diagrams of FIGS. 1 and 3 have a radio-frequency-receiving section 1, an intermediate-frequency amplif
ier 2, and a demodulator section 3, to whose output 4 are connected the arrangements processing the modulation frequency. The tunable resonant circuits of the radio-frequency section contain varactors as tuning elements. Connected to the radio-frequency section is an automatic station finding arrangement in which a digital-to-analog converter 5 generates from the count of a digital counter 7, which receives signals at a stepping input T and advances at the rate of a pulse generator 6, a nearly sawtooth-shaped tuning voltage for the varactors. With a sufficient received field strength at the antenna 8 of the receiver a signal is formed in the demodulator section 3 which signal can be used as stop signal 9 to change the state of a start-stop circuit 10 which may be a flip flop. In the "stop" state the start-stop circuit interrupts the pulse generation or the pulse flow in the pulse generator so that the receiver remains tuned to the station being received. By operating a start-button switch 11 a start signal 12 is generated in the receiver which signal places the start-stop circuit in the "automatic station finding" state and thus continues the automatic station finding operation until next station meeting the receiver's receiving requirements is received.
In the embodiment of FIG. 1, two series-connected parallel memories 15 and 16 are connected, respectively, over two groups of lines 13 and 14 consisting of n lines each, between the n outputs Q 11 to Q n1 and the parallel inputs A 11 to A n1 of the digital counter 7 containing n counting flip-flops. Each parallel memory contains n storage flip-flops and, besides the parallel bit inputs and outputs B and X, a transfer input S. If a transfer signal appears at the transfer input, the parallel memory records the bit word applied its parallel inputs B 1 to B n , which erases the previously entered bit word and now, in turn, appears at the memory outputs X 1 to X n .
The transfer input S of the parallel memory 15, whose parallel inputs are connected over the group of lines 13 to the outputs of the counter 7, is connected to the stop line 17, while the transfer input S of the parallel memory 16, whose parallel outputs are connected over the group of lines 14 to the parallel inputs of the counter 7, is connected to the start line 18.
Connected to a set input P of the digital counters 7 is a switch 19 whose operation generates a set signal. The set signal sets the counter to a count which is equal to the bit word at the parallel inputs A 1 to A n of the counter. At the same time, the set signal acts over the line 20 and via an OR circuit provided for isolation on the transfer input S of the first parallel memory 15.
The diagrams a to g of FIG. 2 explain the operation of the automatic station finding arrangement in conjunction with the recall memories. In diagram a each of the blocks II, III, etc. represents the bit word for a count of the digital counter 7. The blocks in the diagrams b and c are the bit words which are stored in the parallel memories 15 and 16 and can be taken off the latter's parallel outputs, the blocks with equal Roman numerals (e.g. V) representing equal bit words. The diagram d shows the counting pulses 22 for the digital counter 7, the diagram e the stop pulses 9, the diagram f the start pulses 12, and the diagram g the set pulse 23 triggered by the recall switch 19.
The respective count from which the digital-to-analog converter 5 forms the tuning voltage for the varactors is applied simultaneously to the input of the digital-to-analog converter and, as a bit word (e.g. II, III, IV . . . , diagram a), to the input of the first parallel memory 15. At the occurence of a stop signal 9 during the automatic station finding operation, the stop signal 9 acts as a transfer signal on the first par
allel memory 15, and the count (e.g. V, diagram a) at which the stop pulse (e.g. 9a) was generated is entered into the first parallel memory 15 (V in diagram b). At the next start pulse 12a triggered via the start-button switch 11 the automatic station finding operation begins anew, starting from the instantaneous count (e.g. V, diagram a) of the counter. The start signal (12a in diagram f) acts as a transfer signal on the transfer input S of the second parallel memory 16, whereby the second parallel memory takes over the bit word (e.g. V) of the first. The next stop signal (e.g. 9b, diagram e) at a new count (e.g. VIII, diagram a) stops the automatic station search and enters the new count as a bit word (e.g. VIII, diagram b) into the first parallel memory 15.
If the operator operates the recall switch 19 so as to recall the setting to the previously received station, the set pulse 23 triggered by the recall switch sets the counter 7 to the count (e.g. V, diagram a) of the bit word (e.g. V, diagram c) stored in the second parallel memory 16, and the newly set count is entered into the first parallel memory 15 (e.g. V, diagram b). The next start signal (e.g. 12b, diagram f) initiates the automatic station finding operation as described.
In the embodiment of FIG. 3, the two series-connected parallel memories 15 and 16 are incorporated on the chip of an integrated-circuit module 25 which also comprises the circulating digital counter 7 and, for exam
ple, the circuit 26 of a station memory device. The station memory device has the memory inputs D 1 to D n and the memory outputs Y 1 to Y n of its circuit 26 connected in parallel with the digital counter 7 in the same manner as the recall memory consisting of the two series-connected parallel memories 15 and 16. Therefore, gate circuits 27 and 28 are inserted between the parallel outputs of these memories and the parallel inputs A 1 to A n of the digital counter. The gate circuit 27 between the recall memory and the counter is opened by the set signal of the recall switch 19. The gate circuit 28 between the station memory and the counter is opened by the set signal of a switch 29 for calling the bit word of a station preselected by the station buttons 30. In front of the set input 8 of the digital counter the two set signals are separated from one another in an OR circuit 31.
In the embodiment of FIG. 3, the start-stop circuit 10 is designed in the manner of a flip-flop and can assume a "stop" state and an "automatic station finding" state. The transfer inputs S of the recall memory's parallel memories 15 and 16 are connected via the lines 32 and 33 to the outputs of the start-stop circuit. Since the signals at the outputs of the start-stop circuit are continuous signals, the lines 32 and 33 to the transfer inputs include pulse shapers 34 and 35, respectively.
In embodiments corresponding to FIG. 3 and having no station memory device, besides the circuit 26, the gate circuits 27 and 28 and the OR circuit 31 are omitted.
Such a radio receiver is known from, e.g., the journal "Funkschau 1971", pp. 535 to 538 and 587 to 589. With the aid of the free-running pulse generator, the up-counter, and the digital-to-analog converter, the automatic station finding arrangement generates a sawtoothlike tuning voltage for the varactors contained as frequency-setting tuning elements in the resonant circuits of the receiver's radio-frequency portion. If a transmitter is received which meets the receiving criteria set in the receiver, the pulse generator is stopped so that the tuning voltage now remains constant until the operator continues the automatic station finding operation by actuating a start switch.
It is frequently desirable to tune in once again the station at which the start switch for automatic station finding was actuated last - either for comparison or because of the more interesting program. To do this in the case of a receiver with provision for unidirectional automatic station search, the entire search range must be scanned once or several times by repeatedly actuating the start switch, depending on whether the desired station is detected immediately or not.
It is the object of the invention to provide measures for a receiver of the kind referred to by way of introduction which permit the transmitter received before the actuation of the start switch to be found again with a high degree of safety by simple manipulation.
The invention is characterized in that the parallel memory consists of two series-connected parallel memories having one transfer input each, that the transfer input of the (first) parallel memory, whose parallel inputs are connected to the parallel outputs of the counter, are connected directly or indirectly to the stop line, that the transfer input of the (second) parallel memory, whose parallel outputs are connected to the parallel inputs of the counter, is connected directly or indirectly to the start line, that the counter has a set input for through-connecting the parallel inputs of the counter to the flip-flops of the counter, and that a recall switch is connected to the set input of the counter.
Particularly advantageously, the memory locations of the two series-connected parallel memories are storage flip-flops using semiconductor technology. In that case it is possible to arrange the counter and the parallel memories on a common chip of an integrated-circuit module. Such a module has only two terminals more than a module formed by the counter only.
The measures characterized by the invention thus require, aside from an additional recall switch, no additional space and involve nearly no additional expense. To recall the station previously tuned in it is only necessary to depress a button, for example, whereby the receiver is safely tuned to the station's carrier wave even if at the instant of the depression the local received field strength is temporarily too low for sufficient reception.
The invention will now be described in more detail with reference to the accompanying drawing, showing, by way of example, two embodiments of the invention, and wherein:
FIG. 1 is a block diagram showing the radio- and intermediate-frequency portions of a receiver with an automatic station finding arrangement and a recall arrangement;
FIG. 2 shows diagrams a to g explaining the operation of the recall storage, and
FIG. 3 shows a receiver similar to the one of FIG. 1 in which the automatic station finding counter and the recall memories are arranged together on the chip of an integrated-circuit module.
The receivers shown in the block diagrams of FIGS. 1 and 3 have a radio-frequency-receiving section 1, an intermediate-frequency amplif
ier 2, and a demodulator section 3, to whose output 4 are connected the arrangements processing the modulation frequency. The tunable resonant circuits of the radio-frequency section contain varactors as tuning elements. Connected to the radio-frequency section is an automatic station finding arrangement in which a digital-to-analog converter 5 generates from the count of a digital counter 7, which receives signals at a stepping input T and advances at the rate of a pulse generator 6, a nearly sawtooth-shaped tuning voltage for the varactors. With a sufficient received field strength at the antenna 8 of the receiver a signal is formed in the demodulator section 3 which signal can be used as stop signal 9 to change the state of a start-stop circuit 10 which may be a flip flop. In the "stop" state the start-stop circuit interrupts the pulse generation or the pulse flow in the pulse generator so that the receiver remains tuned to the station being received. By operating a start-button switch 11 a start signal 12 is generated in the receiver which signal places the start-stop circuit in the "automatic station finding" state and thus continues the automatic station finding operation until next station meeting the receiver's receiving requirements is received. In the embodiment of FIG. 1, two series-connected parallel memories 15 and 16 are connected, respectively, over two groups of lines 13 and 14 consisting of n lines each, between the n outputs Q 11 to Q n1 and the parallel inputs A 11 to A n1 of the digital counter 7 containing n counting flip-flops. Each parallel memory contains n storage flip-flops and, besides the parallel bit inputs and outputs B and X, a transfer input S. If a transfer signal appears at the transfer input, the parallel memory records the bit word applied its parallel inputs B 1 to B n , which erases the previously entered bit word and now, in turn, appears at the memory outputs X 1 to X n .
The transfer input S of the parallel memory 15, whose parallel inputs are connected over the group of lines 13 to the outputs of the counter 7, is connected to the stop line 17, while the transfer input S of the parallel memory 16, whose parallel outputs are connected over the group of lines 14 to the parallel inputs of the counter 7, is connected to the start line 18.
Connected to a set input P of the digital counters 7 is a switch 19 whose operation generates a set signal. The set signal sets the counter to a count which is equal to the bit word at the parallel inputs A 1 to A n of the counter. At the same time, the set signal acts over the line 20 and via an OR circuit provided for isolation on the transfer input S of the first parallel memory 15.
The diagrams a to g of FIG. 2 explain the operation of the automatic station finding arrangement in conjunction with the recall memories. In diagram a each of the blocks II, III, etc. represents the bit word for a count of the digital counter 7. The blocks in the diagrams b and c are the bit words which are stored in the parallel memories 15 and 16 and can be taken off the latter's parallel outputs, the blocks with equal Roman numerals (e.g. V) representing equal bit words. The diagram d shows the counting pulses 22 for the digital counter 7, the diagram e the stop pulses 9, the diagram f the start pulses 12, and the diagram g the set pulse 23 triggered by the recall switch 19.
The respective count from which the digital-to-analog converter 5 forms the tuning voltage for the varactors is applied simultaneously to the input of the digital-to-analog converter and, as a bit word (e.g. II, III, IV . . . , diagram a), to the input of the first parallel memory 15. At the occurence of a stop signal 9 during the automatic station finding operation, the stop signal 9 acts as a transfer signal on the first par
If the operator operates the recall switch 19 so as to recall the setting to the previously received station, the set pulse 23 triggered by the recall switch sets the counter 7 to the count (e.g. V, diagram a) of the bit word (e.g. V, diagram c) stored in the second parallel memory 16, and the newly set count is entered into the first parallel memory 15 (e.g. V, diagram b). The next start signal (e.g. 12b, diagram f) initiates the automatic station finding operation as described.
In the embodiment of FIG. 3, the two series-connected parallel memories 15 and 16 are incorporated on the chip of an integrated-circuit module 25 which also comprises the circulating digital counter 7 and, for exam
ple, the circuit 26 of a station memory device. The station memory device has the memory inputs D 1 to D n and the memory outputs Y 1 to Y n of its circuit 26 connected in parallel with the digital counter 7 in the same manner as the recall memory consisting of the two series-connected parallel memories 15 and 16. Therefore, gate circuits 27 and 28 are inserted between the parallel outputs of these memories and the parallel inputs A 1 to A n of the digital counter. The gate circuit 27 between the recall memory and the counter is opened by the set signal of the recall switch 19. The gate circuit 28 between the station memory and the counter is opened by the set signal of a switch 29 for calling the bit word of a station preselected by the station buttons 30. In front of the set input 8 of the digital counter the two set signals are separated from one another in an OR circuit 31. In the embodiment of FIG. 3, the start-stop circuit 10 is designed in the manner of a flip-flop and can assume a "stop" state and an "automatic station finding" state. The transfer inputs S of the recall memory's parallel memories 15 and 16 are connected via the lines 32 and 33 to the outputs of the start-stop circuit. Since the signals at the outputs of the start-stop circuit are continuous signals, the lines 32 and 33 to the transfer inputs include pulse shapers 34 and 35, respectively.
In embodiments corresponding to FIG. 3 and having no station memory device, besides the circuit 26, the gate circuits 27 and 28 and the OR circuit 31 are omitted.
An automatic fine tuning (AFT) circuit is provided which generates an AFT control signal in response to a video intermediate frequency (I.F.) signal. The I.F. signal is supplied to the inputs of two buffer amplifiers, which couple signals of like phase relationship to two inputs of a discriminator network. The discriminator network is tuned to the desired frequency of the video I.F. signal, and is responsive to the buffered I.F. signals for causing respective signal voltages to be developed at its inputs which vary differentially in magnitude in response to the frequency deviation of the I.F. signals from the desired I.F. frequency. The differentially related signals are detected by two peak detector networks for use as AFT control signals. The buffer amplifiers and peak detectors may be conveniently fabricated on a single I.C. chip. The discriminator network is coupled to the buffer amplifiers by two external I.C. terminals.
1. In an automatic fine tuning circuit including an integrated circuit chip having first and second contact areas for coupling to discrete circuit elements located external to said integrated circuit chip, apparatus comprising:
means located on said integrated circuit chip for supplying input signals having a frequency within a band including a predetermined reference frequency to said first and second contact areas;
a discriminator network, located external to said integrated circuit chip and coupled to said first and second contact areas, and responsive to said input signals for providing respective signals at said first and second contact areas which vary differentially in magnitude in response to the frequency deviation of said input signals from said reference frequency; and
first and second detector networks located on said integrated circuit chip and having respective input terminals direct current coupled to said first and second contact areas for detecting the magnitudes of said differentially varying signals.
2. In a television receiver, including a source of tuning voltage, and a tuner, including a reactive element responsive to said tuning voltage and an automatic frequency control signal, for producing a mixing signal to convert radio frequency television signals to intermediate frequency television signals within a band including a predetermined reference frequency, an automatic frequency control signal generator comprising:
first and second amplifiers, each having an input terminal for receiving a common intermediate frequency television signal having a frequency within a band including said predetermined reference frequency and an output terminal; said amplifiers supplying respective signal currents of like phase relationship to said output terminals in response to said common input signal;
a discriminator network coupled to said output terminals of said first and second amplifiers for causing respective signal voltages developed at said output terminals of said first and second amplifiers to vary differentially in magnitude in response to the frequency deviation of said intermediate frequency television signal from said reference frequency;
first and second detector networks respectively coupled to said output terminals of said first and second amplifiers for detecting the magnitudes of said differentially varying signal voltages;
a differential amplifier for developing output signals which vary differentially in sense and magnitude in response to the magnitudes of the signals detected by said first and second detector networks; and
means coupled to said differential amplifier for combining said output signals to develop an automatic frequency control signal which varies in sense and magnitude in response to the frequency deviation of said intermediate frequency signal from said predetermined reference frequency,
wherein said amplifiers, said detector networks, said differential amplifier, and said combining means and couplings therebetween are realized in integrated circuit form on a common monolithic integrated circuit chip, wherein each of said output terminals comprises an external connection terminal of said integrated circuit chip, wherein said discriminator network comprises components separate from said chip and coupled to said chip terminals, and wherein said automatic frequency control signal is coupled to said reactive element at a third chip terminal to control the frequency of said mixing signal.
3. The automatic frequency control signal generator of claim 2, further comprising:
a controllable current source having an input responsive to said tuning voltage and having an output coupled to said differential amplifier for varying the magnitude of the sum of said output signals for a given deviation of said intermediate frequency signals from said reference frequency, wherein said current source is located on said integrated circuit chip and said input is coupled to a fourth chip terminal to receive said tuning voltage.
4. In an automatic frequency control signal circuit including an integrated circuit chip having first, second and third contact areas for coupling to discrete circuit elements located external to said integrated circuit chip, apparatus comprising:
means located on said integrated circuit chip for supplying input signals having a frequency within a band including a predetermined reference frequency to said first and second contact areas;
a discriminator network, located external to said integrated circuit chip and coupled to said first and second contact areas, and responsive to said input signals for providing respective signals at said first and second contact areas which vary differentially in magnitude in response to the frequency deviation of said input signals from said reference frequency;
first and second detector networks located on said integrated circuit chip and having respective input terminals coupled to said first and second contact areas for detecting the magnitudes of said differentially varying signals;
a differential amplifier located on said integrated circuit chip and coupled to said detector networks for developing output signals which vary differentially in sense and magnitude in response to the detected magnitudes of said differentially varying signals; and
means located or said integrated circuit chip and coupled to said differential amplifier for combining said output signals to develop an automatic frequency control signal at said third contact area which varies in sense and magnitude in response to the frequency deviation of said input signals from said predetermined reference frequency.
5. The automatic frequency control signal circuit of claim 4, further comprising:
a controllable current source located on said integrated circuit chip and having an input coupled to a fourth contact area and an output coupled to said differential amplifier; and
means external to said integrated circuit chip and coupled to said fourth contact area for varying the magnitude of the sum of said output signals for a given deviation of said input signals from said predetermined reference frequency.
6. Frequency discriminating apparatus comprising:
means for supplying input signals having a frequency within a band including a predetermined reference frequency;
a discriminator network, coupled to said input signal means, which provides respective signals which vary differentially in magnitude in response to the frequency deviation of said input signals from said reference frequency;
means for detecting the respective magnitudes of said discriminator network signals;
an amplifier coupled to said detecting means for developing first and second output currents respectively representative of said respective signal magnitudes;
means for combining said first and second output currents to develop a difference current which is related in sense and magnitude to the frequency deviation of said input signals from said reference frequency; and
a controllable current source coupled to said amplifier for controlling the magnitude of the sum of said first and second output currents for a given frequency deviation of said input signals from said reference frequency.
7. Frequency discriminating apparatus comprising:
means for supplying input signals having a frequency within a band including a predetermined reference frequency;
a discriminator network, coupled to said input signal means, which provides respective signals which vary differentially in magnitude in response to the frequency deviation of said input signals from said reference frequency;
means for detecting the respective magnitudes of said discriminator network signals;
an amplifier coupled to said detecting means for developing first and second output currents respectively representative of said respective signal magnitudes;
means for combining said first and second output currents to develop a difference current which is related in sense and magnitude to the frequency deviation of said input signals from said reference frequency; and
first and second transistors each disposed in a common base amplifier configuration to receive one of said respective output currents from said amplifier and having respective output electrodes coupled to said current combining means.
8. Frequency discriminating apparatus comprising:
means for supplying input signals having a frequency within a band including a predetermined reference frequency;
first and second terminals;
first and second transistors each having an input electrode coupled to said input signal supplying means and respective output electrodes coupled to said first and second terminals for supplying signals of like phase relationship at said terminals;
a discriminator network coupled to said first and second terminals for causing the signals developed at said first and second terminals to vary differentially in magnitude in response to the frequency deviation of said input signals from said reference frequency;
means for detecting the magnitudes of said differentially varying signals; and
a differential amplifier responsive to the detected magnitudes of said differentially varying signals for developing an output signal which varies in sense and magnitude in response to the frequency deviation of said input signals from said reference frequency,
wherein said discriminator network is tuned to said reference frequency and comprises:
a first parallel combination of a capacitor and an intermediate tapped inductor, coupled between said first and second terminals; and
a second parallel combination of a capacitor and an inductor, coupled between said intermediate tap of said inductor of said first parallel combination, and a source of supply voltage.
9. In a television receiver, automatic frequency control apparatus for providing an automatic frequency control signal which varies in response to the frequency deviation of an intermediate frequency signal from a predetermined reference frequency, comprising:
means responsive to said intermediate frequency signal for providing first and second input signals of like phase relationship;
a discriminator network, coupled to said input signal means, and responsive to said first and second input signals, for causing said input signals to vary differentially in magnitude in response to the frequency deviation of said input signals from said reference frequency;
means coupled to the junction of said input signal means and said discriminator network for detecting the magnitudes of said differentially varying signals;
a differential amplifier coupled to said detecting means for developing output signals which vary in sense and magnitude in response to the detected magnitudes of said differentially varying signals; and
a current mirror circuit coupled to said differential amplifier for combining said output signals to develop an automatic frequency control signal which varies in sense and magnitude in response to the frequency deviation of said intermediate frequency signal from said predetermined reference frequency, wherein said automatic frequency control signal may be used to control the frequency of said intermediate frequency signal.
a controllable current source coupled to said differential amplifier and having an input for controlling the magnitude of the sum of the output signals developed by said differential amplifier for a given deviation of said intermediate frequency signal from said reference frequency.
11. In a television receiver, including a source of tuning voltage, and a tuner, including a reactive element responsive to said tuning voltage and an automatic frequency control signal, for producing a mixing signal to convert radio frequency television signals to intermediate frequency television signals within a band including a predetermined reference frequency, an automatic frequency control signal generator comprising:
means responsive to said intermediate frequency signals for developing signals which vary differentially in magnitude in response to the frequency deviation of said intermediate frequency signals from said reference frequency;
a differential amplifier for developing output signals which vary differentially in sense and magnitude in response to the magnitudes of the signals developed by said differential signal means; and
means coupled to said differential amplifier for combining said output signals to develop an automatic frequency control signal which varies in sense and magnitude in response to the frequency deviation of said intermediate frequency signal from said predetermined reference frequency, wherein said automatic frequency control signal is coupled to said reactive element to control the frequency of said mixing signal.
12. The automatic frequency control signal generator of claim 11, further comprising:
a controllable current source responsive to said tuning voltage and having an output coupled to said differential amplifier for varying the magnitude of the sum of said output signals for a given deviation of said intermediate frequency signals from said reference frequency.
Description:
This invention relates to automatic frequency control apparatus in general, and, in particular, to such apparatus for deriving a frequency dependent error-correction signal to control the tuning of a local oscillator in a superheterodyne receiver.
It is the function of a television tuner to select a narrow range of frequencies from among the many broadcast frequencies in the radio frequency band. A conventional television tuner performs this function through the use of a radio frequency amplifier, a mixer, and a local heterodyne oscillator. The output of this oscillator is compared to, or beat with, the radio frequency television signal received from the receiver antenna by the mixer. This beating action creates both the sum and difference frequencies of the original radio frequency and local oscillator frequencies. All but the difference frequencies, called intermediate frequencies (I.F.), are filtered out. These I.F. frequencies are amplified and detected by the television receiver to recreate the desired sound and picture information.
In order to provide the optimum image on the television screen, together with accurate sound reproduction, it is necessary that the receiver local oscillator be adjusted so that the picture and sound carriers are located at the correct points in the I.F. passband of the television receiver. This is especially true in the tuning of color television receivers. Not only must the picture and sound carriers be situated at their proper positions in the I.F. passband but the color subcarrier must also be properly positioned in order that the colors will be reproduced by the kinescope with proper hue and saturation characteristics. If the local oscillator is for any reason not set at the proper frequency, the intermediate frequencies will be incorrect, and may deleteriously affect the reproduced sound and picture. As is well known, this mistuning may be due to improper fine tuning by the television viewer, local oscillator drift, or inaccurate resetability of the detenting action of a mechanical tuner. In order to overcome these problems, conventional receivers are provided with means for compensating for variations in the intermediate frequencies.
This compensation is normally accomplished by deriving an automatic fine tuning (AFT) voltage from the output of the I.F. amplifying stage of the receiver. The AFT voltage is representative of the sense and degree that the I.F. signal departs from the desired I.F. signal. The AFT voltage is applied to a voltage responsive reactance device in the local oscillator to correct the mistuning of the oscillator and thereby optimize the sound and picture reproduction.
There are presently two types of AFT circuits in general use: the quadrature detector type and the differential envelope detector type. The quadrature detector type AFT circuit converts frequency shifts of a frequency modulated signal to differentially phase-shifted signals by applying the frequency modulated signal to a filter network, which develops two differentially phase-shifted, or delayed, signals at its output ports. The differentially phase-shifted signals are coupled to a quadrature, or phase, detector, which converts the relative phase difference between the signals at the filter output ports to an amplitude-varying AFT control signal. The differential envelope detector type AFT circuit, such as that described in the present application, utilizes a linear filter network to convert frequency shifts of a frequency modulated signal to differentially related, amplitude varying signals. These signals are coupled to envelope detectors, which convert the amplitude varying signals to AFT control signals. The differential envelope detector AFT circuit generally requires fewer components than the quadrature detector type, and is preferred in many applications because of its ability to produce a narrower, more precisely controlled AFT bandwidth. The narrower bandwidth reduces the effect of I.F. noise on the AFT control system and produces sharper AFT response in the vicinity of the I.F. picture carrier being controlled by the system.
In order to minimize the size and number of components required to construct an AFT circuit, it is desirable to fabricate the circuit in integrated circuit form on a single monolithic integrated circuit chip. However, certain AFT circuit elements, specifically, the reactive components used to construct the discriminator network necessary to convert frequency shifts of the I.F. signal to amplitude modulated signals, do not readily lend themselves to integrated circuit fabrication and must be located external to the I.C. chip. The I.C. chip has only a limited number of external connection points, or terminals, for connection to external components. Hence, it is desirable to construct the AFT circuit in a manner which reduces the number of required connections to external components.
In accordance with the principles of the present invention, an AFT circuit is provided which generates AFT control signals in response to a video I.F. signal. The I.F. signal is supplied to the inputs of two buffer amplifiers, which couple parallel signals of like phase relationship to two inputs of a discriminator network. The discriminator network is tuned to the desired I.F. frequency, and is responsive to the buffered I.F. signals for providing respective signals at its inputs which vary differentially in sense and degree with the frequency deviation of the buffered I.F. signals from the desired I.F. frequency. The differentially related signals are detected by two peak detector networks for use as AFT control signals. The buffer amplifiers and peak detector networks may be conveniently fabricated on a single I.C. chip. The discriminator network is coupled to the buffer amplifiers and peak detectors through two external I.C. terminals.
The peak detected signals may be combined and amplified to produce an AFT signal for application to the local oscillator. However, a circuit with an AFT signal which varies over a fixed voltage range is restricted to operation with local oscillators which respond to the specific voltage range of that circuit. Such an AFT circuit can be used with a wide variety of local oscillators of differing characteristics only if additional interfacing circuitry is interposed between the AFT circuit and the local oscillator. Such interfacing circuitry can add undesirable delays and complexity to the AFT system.
In accordance with a further aspect of the present invention, the detected, differentially related signals are combined by a differential amplifier and coupled to a current mirror circuit to provide an AFT current signal. The current mirror circuit is contained on the same I.C. chip as the buffer amplifiers and detector networks. Through the use of a suitable external load resistor, the AFT current signal may be used to produce a wide variety of AFT voltage ranges. In addition, means are provided for varying the magnitude of the AFT current signal to permit accurate matching of the AFT circuit to the signal requirements of the local oscillator. The magnitude of the AFT current signal may be modified during operation of the television receiver, for example, to provide continuously variable AFT current signal ranges over the full range of television channels.
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