METZ 7345 MALLORCA COLOR QC CHASSIS 682 G UNITS VIEW.

 
TDA3501 VIDEO CONTROL COMBINATIONThe TDA3501 is a monolithic integrated circuit performing the control functions in a PAL/SECAM
decoder which additionally comprises the integrated circuits TDA3510 (PAL decoder) and/or
TDA3520 (SECAM decoder).
The required input signals are: luminance and colour difference -(R-Y) and -(B-Y). while linear RGB
signals can be inserted from an external source.
RGB signals are provided at the output to drive the video output stages.
The TDA3501 has the following features:
I capacitive coupling of the input signals
0 linear saturation control
0 (G-Y) and RGB matrix
0 insertion possibility of linear RGB signals, e.g. video text, video games, picture-in-picture, camera or
slidescanner
0 equal black level for inserted and matrixed signals by clamping
0 3 identical channels for the RGB signals
0 linear contrast and brightness control, operating on both the inserted and matrixed RGB signals
I horizontal and vertical blanking (black and ultra-black respectively) and black-level clamping
obtained via a 3-level sandcastle pulse
O differential amplifiers with feedback-inputs for stabilization of the RGB output stages
0 2 d.c. gain controls for the green and blue output signals (white point adjustment)
O beam current limiting possibility
QUICK REFERENCE DATA
Supply voltage V524 typ. 12 V
Supply current I5 typ. 100 mA
Luminance input signal (peak-to-peak value) V15_24(p_p) typ. 0,45 V
Luminance input resistance R15_24 typ. 12 kS`L
Colour difference input signals (peak-to-peak values)
-(B-Y) V1g_24(p_p) typ. 1,33 V
-(R-Y) V17_24(p_p) typ. 1,05 V
Inserted RGB signals (peak-to-peak values) V12,13,-|4_24(p_p) typ. 1 V
Threelevel sandcastle pulse detector V10_24 typ. 2,5/4,5/8,0 V
Control voltage ranges
brightness V20_24 1 to 3 V
contrast V19_24 2 to 4 V
saturation V15_24 2,1 to 4 VSAB3034 COMPUTER INTERFACE FOR TUNING AND CONTROL (CITAC)

GENERAL DESCRIPTION
The SAB3034 provides closed-loop digital tuning of TV receivers, with or without a.f.c., as required. lt
also controls up to 8 analogue functions, 4 general purpose I/O ports and 4 high-current outputs for
tuner band selection.
The IC is used in conjunction with a microcomputer from the MAB84OO family and is controlled via a two-wire, bidirectional I2 C bus.
Featu res
Combined analogue and digital circuitry minimizes the number of additional interfacing components
required
Frequency measurement with resolution of 50 KHz
Selectable prescaler divisor of 64 or 256
32 V tuning voltage amplifier
4 high-current outputs for direct band selection
8 static digital to analogue converters (DACSI for control of analogue functions
Four general purpose input/output (l/O) ports
Tuning with control of speed and direction
Tuning with or without a.f.c.
Single-pin, 4 MHZ on-chip oscillator
I2 C bus slave transceiver

FUNCTIONAL DESCRIPTION
The SAB3034 is a monolithic computer interface which provides tuning and control functions and
operates in conjunction with a microcomputer via an I2 C bus.
Tuning
This is performed using frequency-locked loop digital control. Data corresponding to the required tuner
frequency is stored in a 15-bit frequency buffer. The actual tuner frequency, divided by a factor of 256
(or by 64) by a prescaler, is applied via a gate to a 15-bit frequency counter. This input (FDIV) is
measured over a period controlled by a time reference counter and is compared with the contents of the frequency buffer. The result of the comparison is used to control the tuning voltage so that the tuner frequency equals the contents of the frequency buffer multiplied by 50 kHz within a programmable tuning window (TUW).

The system cycles over a period of 6,4 ms (or 2,56 ms), controlled by the time reference counter which is clocked by an on-chip 4 lVlHz reference oscillator. Regulation of the tuning voltage is performed by a charge pump frequency-locked loop system. The charge IT flowing into the tuning voltage amplifier is controlled by the tuning counter, 3-bit DAC and the charge pump circuit. The charge IT is linear with the frequency deviation Af in steps of 50



TDA2545A Quasi-split-sound circuitGENERAL DESCRIPTION The TDA2545A is a monolithic integrated circuit for quasi-split-sound processing in television receivers. Features · 3-stage gain controlled i.f. amplifier · A.G.C. circuit · Reference amplifier and limiter amplifier for vision carrier (V.C.) processing · Linear multiplier for quadrature demodulation.


TDA2541 IF AMPLIFIER WITH DEMODULATOR AND AFC
DESCRIPTION
The TDA2540 and 2541 are IF amplifier and A.M.
demodulator circuits for colour and black and white
televisionreceiversusingPNPorNPNtuners. They
are intended for reception of negative or positive
modulation CCIR standard.
They incorporate the following functions : .Gain controlled amplifier .Synchronous demodulator .White spot inverter .Video preamplifier with noise protection .Switchable AFC .AGC with noise gating .Tuner AGC output (NPN tuner for 2540)-(PNP
tuner for 2541) .VCR switch for video output inhibition (VCR
play back).



TDA2006 12W AUDIO AMPLIFIER

DESCRIPTION
The TDA2006 is a monolithic integrated circuit in
Pentawatt package, intended for use as a low
frequency class ”AB” amplifier. At ±12V, d = 10 %
typically it provides12Woutput poweron a 4W load
and 8W on a 8W . The TDA2006 provides high
output current and has very low harmonic and
cross-over distortion. Further the device incorporates
anoriginal (and patented)short circuit protection
system comprising an arrangement for
automatically limiting the dissipated power so as to
keep the working point of the output transistors
within their safe operating area. A conventional
thermal shutdown system is also included. The
TDA2006 is pin to pin equivalent to theTDA2030.

SHORT CIRCUIT PROTECTION

The TDA2006 has an original circuit which limits
the current of the output transistors.
This function can thereforebe considered as being
peak power limiting rather than simple current limiting.
It reduces the possibility that the device gets damaged
during an accidental short circuit from AC
output to ground.
THERMALSHUT DOWN
The presence of a thermal limiting circuit offers the
following advantages :
1) an overload on the output (even if it is
permanent), or an above l imi t ambient
temperature can be easily supported since the
Tj cannot be higher than 150°C.
2) the heatsink can have a smaller factor of safety
compared with that of a conventional circuit.
There is no possibility of device damage due to
high junction temperature.
If for any reason, the junction temperature increases
up to 150 °C, the thermal shutdown simply
reduces the power dissipation and the current consumption.
The maximum allowable power dissipation depends
upon the size of the external heatsink (i.e.
its thermal resistance)


Switched mode power supply

Supply is based on TDA4600 (SIEMENS).

Power supply Description based on TDA4601d (SIEMENS)

TDA4601 Operation. * The TDA4601 device is a single in line, 9 pin chip. Its predecessor was the TDA4600 device, the TDA4601 however has improved switching, better protection and cooler running. The (SIEMENS) TDA4601 power supply is a fairly standard parallel chopper switch mode type, which operates on the same basic principle as a line output stage. It is turned on and off by a square wave drive pulse, when switched on energy is stored in the chopper transformer primary winding in the form of a magnetic flux; when the chopper is turned off the magnetic flux collapses, causing a large back emf to be produced. At the secondary side of the chopper transformer this is rectified and smoothed for H.T. supply purposes. The advantage of this type of supply is that the high chopping frequency (20 to 70 KHz according to load) allows the use of relatively small H.T. smoothing capacitors making smoothing easier. Also should the chopper device go short circuit there is no H.T. output. In order to start up the TDA4601 I.C. an initial supply of 9v is required at pin 9, this voltage is sourced via R818 and D805 from the AC side of the bridge rectifier D801, also pin 5 requires a +Ve bias for the internal logic block. (On some sets pin 5 is used for standby switching). Once the power supply is up and running, the voltage on pin 9 is increased to 16v and maintained at this level by D807 and C820 acting as a half wave rectifier and smoothing circuit. PIN DESCRIPTIONS Pin 1 This is a 4v reference produced within the I.C. Pin 2 This pin detects the exact point at which energy stored in the chopper transformer collapses to zero via R824 and R825, and allows Q1 to deliver drive volts to the chopper transistor. It also opens the switch at pin 4 allowing the external capacitor C813 to charge from its external feed resistor R810. Pin 3 H.T. control/feedback via photo coupler D830. The voltage at this pin controls the on time of the chopper transistor and hence the output voltage. Normally it runs at Approximately 2v and regulates H.T. by sensing a proportion of the +4v reference at pin 1, offset by conduction of the photo coupler D830 which acts like a variable resistor. An increase in the conduction of transistor D830 and therefor a reduction of its resistance will cause a corresponding reduction of the positive voltage at Pin 3. A decrease in this voltage will result in a shorter on time for the chopper transistor and therefor a lowering of the output voltage and vice versa, oscillation frequency also varies according to load, the higher the load the lower the frequency etc. should the voltage at pin 3 exceed 2.3v an internal flip flop is triggered causing the chopper drive mark space ratio to extend to 244 (off time) to 1 (on time), the chip is now in over volts trip condition. Pin 4 At this pin a sawtooth waveform is generated which simulates chopper current, it is produced by a time constant network R810 and C813. C813 charges when the chopper is on and is discharged when the chopper is off, by an internal switch strapping pin 4 to the internal +2v reference, see Fig 2. The amplitude of the ramp is proportional to chopper drive. In an overload condition it reaches 4v amplitude at which point chopper drive is reduced to a mark-space ratio of 13 to 1, the chip is then in over current trip. The I.C. can easily withstand a short circuit on the H.T. rail and in such a case the power supply simply squegs quietly. Pin 4 is protected by internal protection components which limit the maximum voltage at this pin to 6.5v. Should a fault occur in either of the time constant components, then the chopper transistor will probably be destroyed. Pin 5 This pin can be used for remote control on/off switching of the power supply, it is normally held at about +7v and will cause the chip to enter standby mode if it falls below 2v. Pin 6 Ground. Pin 7 Chopper switch off pin. This pin clamps the chopper drive voltage to 1.6v in order to switch off the chopper. Pin 8 Chopper base current output drive pin. Pin 9 L.T. pin, approximately 9v under start-up conditions and 16v during normal running, Current consumption of the I.C. is typically 135mA. The voltage at this pin must reach 6.7v in order for the chip to start-up.
Semiconductor circuit for supplying power to electrical equipment, comprising a transformer having a primary winding connected, via a parallel connection of a collector-emitter path of a transistor with a first capacitor, to both outputs of a rectifier circuit supplied, in turn, by a line a-c voltage; said transistor having a base controlled via a second capacitor by an output of a control circuit acted upon, in turn by the rectified a-c line voltage as actual value and by a reference voltage; said transformer having a first secondary winding to which the electrical equipment to be supplied is connected; said transformer having a second secondary winding with one terminal thereof connected to the emitter of said transistor and the other terminal thereof connected to an anode of a first diode leading to said control circuit; said transformer having a third secondary winding with one terminal thereof connected, on the one hand, via a series connection of a third capacitor with a first resistance, to the other terminal of said third secondary winding and connected, on the other hand, to the emitter of said transistor, the collector of which is connected to said primary winding; a point between said third capacitor and said first resistance being connected to the cathode of a second diode; said control circuit having nine terminals including a first terminal delivering a reference voltage and connected, via a voltage divider formed of a third and fourth series-connected resistances, to the anode of said second diode; a second terminal of said control circuit serving for zero-crossing identification being connected via a fifth resistance to said cathode of said second diode; a third terminal of said control-circuit serving as actual value input being directly connected to a divider point of said voltage divider forming said connection of said first terminal of said control circuit to said anode of said second diode; a fourth terminal of said control circuit delivering a sawtooth voltage being connected via a sixth resistance to a terminal of said primary winding of said transformer facing away from said transistor; a fifth terminal of said control circuit serving as a protective input being connected, via a seventh resistance to the cathode of said first diode and, through the intermediary of said seventh resistance and an eighth resistance, to the cathode of a third diode having an anode connected to an input of said rectifier circuit; a sixth terminal of said control circuit carrying said reference potential and being connected via a fourth capacitor to said fourth terminal of said control circuit and via a fifth capacitor to the anode of said second diode; a seventh terminal of said control circuit establishing a potential for pulses controlling said transistor being connected directly and an eighth terminal of said control circuit effecting pulse control of the base of said transistor being connected through the intermediary of a ninth resistance to said first capacitor leading to the base of said transistor; and a ninth terminal of said control circuit serving as a power supply input of said control circuit being connected both to the cathode of said first diode as well as via the intermediary of a sixth capacitor to a terminal of said second secondary winding as well as to a terminal of said third secondary winding.

Description:

The invention relates to a blocking oscillator type switching power supply for supplying power to electrical equipment, wherein the primary winding of a transformer, in series with the emitter-collector path of a first bipolar transistor, is connected to a d-c voltage obtained by rectification of a line a-c voltage fed-in via two external supply terminals, and a secondary winding of the transformer is provided for supplying power to the electrical equipment, wherein, furthermore, the first bipolar transistor has a base controlled by the output of a control circuit which is acted upon in turn by the rectified a-c line voltage as actual value and by a set-point transmitter, and wherein a starting circuit for further control of the base of the first bipolar transistor is provided.
Such a blocking oscillator switching power supply is described in the German periodical, "Funkschau" (1975) No. 5, pages 40 to 44. It is well known that the purpose of such a circuit is to supply electronic equipment, for example, a television set, with stabilized and controlled supply voltages. Essential for such switching power supply is a power switching transistor i.e. a bipolar transistor with high switching speed and high reverse voltage. This transistor therefore constitutes an important component of the control element of the control circuit. Furthermore, a high operating frequency and a transformer intended for a high operating frequency are provided, because generally, a thorough separation of the equipment to be supplied from the supply naturally is desired. Such switching power supplies may be constructed either for synchronized or externally controlled operation or for non-synchronized or free-running operation. A blocking converter is understood to be a switching power supply in which power is delivered to the equipment to be supplied only if the switching transistor establishing the connection between the primary coil of the transformer and the rectified a-c voltage is cut off. The power delivered by the line rectifier to the primary coil of the transformer while the switching transistor is open, is interim-stored in the transformer and then delivered to the consumer on the secondary side of the transformer with the switching transistor cut off.
In the blocking converter described in the aforementioned reference in the literature, "Funkschau" (1975), No. 5, Pages 40 to 44, the power switching transistor is connected in the manner defined in the introduction to this application. In addition, a so-called starting circuit is provided. Because several diodes are generally provided in the overall circuit of a blocking oscillator according to the definition provided in the introduction hereto, it is necessary, in order not to damage these diodes, that due to the collector peak current in the case of a short circuit, no excessive stress of these diodes and possibly existing further sensitive circuit parts can occur.
Considering the operation of a blocking oscillator, this means that, in the event of a short circuit, the number of collector current pulses per unit time must be reduced. For this purpose, a control and regulating circuit is provided. Simultaneously, a starting circuit must bring the blocking converter back to normal operation when the equipment is switched on, and after disturbances, for example, in the event of a short circuit. The starting circuit shown in the literature reference "Funkschau" on Page 42 thereof, differs to some extent already from the conventional d-c starting circuits. It is commonly known for all heretofore known blocking oscillator circuits, however, that a thyristor or an equivalent circuit replacing the thyristor is essential for the operation of the control circuit.
It is accordingly an object of the invention to provide another starting circuit. It is a further object of the invention to provide a possible circuit for the control circuit which is particularly well suited for this purpose. It is yet another object of the invention to provide such a power supply which is assured of operation over the entire range of line voltages from 90 to 270 V a-c, while the secondary voltages and secondary load variations between no-load and short circuit are largely constant.
With the foregoing and other objects in view, there is provided, in accordance with the invention, a blocking oscillator-type switching power supply for supplying power to electrical equipment wherein a primary winding of a transformer, in series with an emitter-collector path of a first bipolar transistor, is connected to a d-c voltage obtained by rectification of a line a-c voltage fed-in via two external supply terminals, a secondary winding of the transformer being connectible to the electrical equipment for supplying power thereto, the first bipolar transistor having a base controlled by the output of a control circuit acted upon, in turn, by the rectified a-c line voltage as actual value and by a set-point transmitter, and including a starting circuit for further control of the base of the first bipolar transistor, including a first diode in the starting circuit having an anode directly connected to one of the supply terminals supplied by the a-c line voltage and a cathode connected via a resistor to an input serving to supply power to the control circuit, the input being directly connected to a cathode of a second diode, the second diode having an anode connected to one terminal of another secondary winding of the transformer, the other secondary winding having another terminal connected to the emitter of the first bipolar transmitter.
In accordance with another feature of the invention, there is provided a second bipolar transistor having the same conduction type as that of the first bipolar transistor and connected in the starting circuit with the base thereof connected to a cathode of a semiconductor diode, the semiconductor diode having an anode connected to the emitter of the first bipolar transistor, the second bipolar transistor having a collector connected via a resistor to a cathode of the first diode in the starting circuit, and having an emitter connected to the input serving to supply power to the control circuit and also connected to the cathode of the second diode which is connected to the other secondary winding of the transformer.
In accordance with a further feature of the invention, the base of the second bipolar transistor is connected to a resistor and via the latter to one pole of a first capacitor, the anode of the first diode being connected to the other pole of the first capacitor.
In accordance with an added feature of the invention, the input serving to supply power to the control circuit is connected via a second capacitor to an output of a line rectifier, the output of the line rectifier being directly connected to the emitter of the first bipolar transistor.
In accordance with an additional feature of the invention, the other secondary winding is connected at one end to the emitter of the first bipolar transistor and to a pole of a third capacitor, the third capacitor having another pole connected, on the one hand, via a resistor, to the other end of the other secondary winding and, on the other hand, to a cathode of a third diode, the third diode having an anode connected via a potentiometer to an actual value input of the control circuit and, via a fourth capacitor, to the emitter of the first bipolar transistor.
In accordance with yet another feature of the invention, the control circuit has a control output connected via a fifth capacitor to the base of the first bipolar transistor for conducting to the latter control pulses generated in the control circuit.
In accordance with a concomitant feature of the invention, there is provided a sixth capacitor shunting the emitter-collector path of the first transistor.
Other features which are considered as characteristic for the invention are set forth in the appended claim.
Although the invention is illustrated and described herein as embodied in a blocking oscillator type switching power supply, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.

The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings, in which:

FIGS. 1 and 2 are circuit diagrams of the blocking oscillator type switching power supply according to the invention; and

FIG. 3 is a circuit diagram of the control unit RS of FIGS. 1 and 2.

Referring now to the drawing and, first, particularly to FIG. 1 thereof, there is shown a rectifier circuit G in the form of a bridge current, which is acted upon by a line input represented by two supply terminals 1' and 2'. Rectifier outputs 3' and 4' are shunted by an emitter-collector path of an NPN power transistor T1 i.e. the series connection of the so-called first bipolar transistor referred to hereinbefore with a primary winding I of a transformer Tr. Together with the inductance of the transformer Tr, the capacitance C1 determines the frequency and limits the opening voltages of the switch embodied by the first transistor T1. A capacitance C2, provided between the base of the first transistor T1 and the control output 7,8 of a control circuit RS, separates the d-c potentials of the control or regulating circuit RS and the switching transistor T1 and serves for addressing this switching transistor T1 with pulses. A resistor R1 provided at the control output 7,8 of the control circuit RS is the negative-feedback resistor of both output stages of the control circuit RS. It determines the maximally possible output pulse current of the control circuit RS. A secondary winding II of the transformer Tr takes over the power supply of the control circuit, in steady state operation, via the diode D1. To this end, the cathode of this diode D1 is directly connected to a power supply input 9 of the control circuit RS, while the anode thereof is connected to one terminal of the secondary winding II. The other terminal of the secondary winding II is connected to the emitter of the power switching transistor T1.

The cathode of the diode D1 and, therewith, the power supply terminal 9 of the control circuits RS are furthermore connected to one pole of a capacitor C3, the other pole of which is connected to the output 3' of the rectifier G. The capacitance of this capacitor C3 thereby smoothes the positive half-wave pulses and serves simultaneously as an energy storage device during the starting period. Another secondary winding III of the transformer Tr is connected by one of the leads thereof likewise to the emitter of the first transistor T1, and by the other lead thereof via a resistor R2, to one of the poles of a further capacitor C4, the other pole of which is connected to the first-mentioned lead of the other secondary winding III. This second pole of the capacitor C4 is simultaneously connected to the output 3' of the rectifier circuit G and, thereby, via the capacitor C3, to the cathode of the diode D1 driven by the secondary winding II of the transformer Tr as well as to the power supply input 9 of the control circuit RS and, via a resistor R9, to the cathode of a second diode D4. The second pole of the capacitor C4 is simultaneously connected directly to the terminal 6 of the control circuit RS and, via a further capacitor C 6, to the terminal 4 of the control circuit RS as well as, additionally, via the resistor R6, to the other output 4' of the rectifier circuit G. The other of the poles of the capacitor C4 acted upon by the secondary winding II is connected via a further capacitor C5 to a node, which is connected on one side thereof, via a variable resistor R4, to the terminals 1 and 3 of the control circuit RS, with the intermediary of a fixed resistor R5 in the case of the terminal 1. On the other side of the node, the latter and, therefore, the capacitor C5 are connected to the anode of a third diode D2, the cathode of which is connected on the one hand, to the resistor R2 mentioned hereinbefore and leads to the secondary winding III of the transformer Tr and, on the other hand, via a resistor R3 to the terminal 2 of the control circuit RS.

The nine terminals of the control circuit RS have the following purposes or functions:

Terminal 1 supplies the internally generated reference voltage to ground i.e. the nominal or reference value required for the control or regulating process;

Terminal 2 serves as input for the oscillations provided by the secondary winding III, at the zero point of which, the pulse start of the driving pulse takes place;

Terminal 3 is the control input, at which the existing actual value is communicated to the control circuit RS, that actual value being generated by the rectified oscillations at the secondary winding III;

Terminal 4 is responsive to the occurrence of a maximum excursion i.e. when the largest current flows through the first transistor T1 ;

Terminal 5 is a protective input which responds if the rectified line voltage drops too sharply; Terminal 6 serves for the power supply of the control process and, indeed, as ground terminal;

Terminal 7 supplies the d-c component required for charging the coupling capacitor C2 leading to the base of the first transistor T1 ;

Terminal 8 supplies the control pulse required for the base of the first transistor T1 ; and

Terminal 9 serves as the first terminal of the power supply of the control circuit RS.

Further details of the control circuit RS are described hereinbelow.

The capacity C3 smoothes the positive half-wave pulses which are provided by the secondary winding II, and simultaneously serves as an energy storage device during the starting time. The secondary winding III generates the control voltage and is simultaneously used as feedback. The time delay stage R2 /C4 keeps harmonics and fast interference spikes away from the control circuit RS. The resistor R3 is provided as a voltage divider for the second terminal of the control circuit RS. The diode D2 rectifies the control pulses delivered by the secondary winding III. The capacity C5 smoothes the control voltage. A reference voltage Uref, which is referred to ground i.e. the potential of terminal 6 is present at the terminal 1 of the control circuit RS. The resistors R4 and R5 form a voltage divider of the input-difference control amplifier at the terminal 3. The desired secondary voltage can be set manually via the variable resistor R4. A time-delay stage R6 /C6 forms a sawtooth rise which corresponds to the collector current rise of the first bipolar transistor T1 via the primary winding I of the transformer Tr. The sawtooth present at the terminal 4 of the control circuit RS is limited there between the reference voltage 2 V and 4 V. The voltage divider R7 /R8 (FIG. 2), brings to the terminal 5 of the control circuit RS the enabling voltage for the drive pulse at the output 8 of the control circuit RS.

The diode D4, together with the resistor R9 in cooperation with the diode D1 and the secondary winding II, forms the starting circuit provided, in accordance with the invention. The operation thereof is as follows:

After the switching power supply is switched on, d-c voltages build up at the collector of the switching transistor T1 and at the input 4 of the control circuit RS, as a function in time of the predetermined time constants. The positive sinusoidal half-waves charge the capacitor C3 via the starting diode D4 and the starting resistor R9 in dependence upon the time constant R9.C3. Via the protective input terminal 5 and the resistor R11 not previously mentioned and forming the connection between the resistor R9 and the diode D1, on the one hand, and the terminal 5 of the control circuit RS, on the other hand, the control circuit RS is biased ready for switching-on, and the capacitor C2 is charged via the output 7. When a predetermined voltage value at the capacitor C3 or the power supply input 9 of the control circuit RS, respectively, is reached, the reference voltage i.e. the nominal value for the operation of the control voltage RS, is abruptly formed, which supplies all stages of the control circuit and appears at the output 1 thereof. Simultaneously, the switching transistor T1 is switched into conduction via the output 8. The switching of the transistor T1 at the primary winding T of the transformer Tr is transformed to the second secondary winding II, the capacity C3 being thereby charged up again via the diode D1. If sufficient energy is stored in the capacitor C3 and if the re-charge via the diode D1 is sufficient so that the voltage at a supply input 9 does not fall below the given minimum operating voltage, the switching power supply then remains connected, so that the starting process is completed. Otherwise, the starting process described is repeated several times.

In FIG. 2, there is shown a further embodiment of the circuit for a blocking oscillator type switching power supply, according to the invention, as shown in FIG. 1. Essential for this circuit of FIG. 2 is the presence of a second bipolar transistor T2 of the type of the first bipolar transistor T1 (i.e. in the embodiments of the invention, an npn-transistor), which forms a further component of the starting circuit and is connected with the collector-emitter path thereof between the resistor R9 of the starting circuit and the current supply input 9 of the control circuit RS. The base of this second transistor T2 is connected to a node which leads, on the one hand, via a resistor R10 to one electrode of a capacitor C7, the other electrode of which is connected to the anode of the diode D4 of the starting circuit and, accordingly, to the terminal 1' of the supply input of the switching power supply G. On the other hand, the last-mentioned node and, therefore, the base of the second transistor T2 are connected to the cathode of a Zener diode D3, the anode of which is connected to the output 3' of the rectifier G and, whereby, to one pole of the capacitor C3, the second pole of which is connected to the power supply input 9 of the control circuit RS as well as to the cathode of the diode D1 and to the emitter of the second transistor T2. In other respects, the circuit according to FIG. 2 corresponds to the circuit according to FIG. 1 except for the resistor R11 which is not necessary in the embodiment of FIG. 2, and the missing connection between the resistor R9 and the cathode of the diode D1, respectively, and the protective input 5 of the control circuit RS.

Regarding the operation of the starting circuit according to FIG. 2, it can be stated that the positive sinusoidal half-wave of the line voltage, delayed by the time delay stage C7, R10 drives the base of the transistor T2 in the starting circuit. The amplitude is limited by the diode D3 which is provided for overvoltage protection of the control circuit RS and which is preferably incorporated as a Zener diode. The second transistor T2 is switched into conduction. The capacity C3 is charged, via the serially connected diode D4 and the resistor R9 and the collector-emitter path of the transistor T2, as soon as the voltage between the terminal 9 and the terminal 6 of the control circuit RS i.e. the voltage U9, meets the condition U9 <[UDs -UBE (T2)].

Because of the time constant R9.C3, several positive half-waves are necessary in order to increase the voltage U9 at the supply terminal 9 of the control circuit RS to such an extent that the control circuit RS is energized. During the negative sine half-wave, a partial energy chargeback takes place from the capacitor C3 via the emitter-base path of the transistor T2 of the starting circuit and via the resistor R10 and the capacitor C7, respectively, into the supply network. At approximately 2/3 of the voltage U9, which is limited by the diode D3, the control circuit RS is switched on. At the terminal 1 thereof, the reference voltage Uref then appears. In addition, the voltage divider R5 /R4 becomes effective. At the terminal 3, the control amplifier receives the voltage forming the actual value, while the first bipolar transistor T1 of the blocking-oscillator type switching power supply is addressed pulsewise via the terminal 8.

Because the capacitor C6 is charged via the resistor R6, a higher voltage than Uref is present at the terminal 4 if the control circuit RS is activated. The control voltage then discharges the capacitor C6 via the terminal 4 to half the value of the reference voltage Uref, and immediately cuts off the addressing input 8 of the control circuit RS. The first driving pulse of the switching transistor T1 is thereby limited to a minimum of time. The power for switching-on the control circuit RS and for driving the transistor T1 is supplied by the capacitor C3. The voltage U9 at the capacitor C3 then drops. If the voltage U9 drops below the switching-off voltage value of the control circuit RS, the latter is then inactivated. The next positive sine half-wave would initiate the starting process again.

By switching the transistor T1, a voltage is transformed in the secondary winding II of the transformer Tr. The positive component is rectified by the diode D1, recharing of the capacitor C3 being thereby provided. The voltage U9 at the output 9 does not, therefore, drop below the minimum value required for the operation of the control circuit RS, so that the control circuit RS remains activated. The power supply continues to operate in the rhythm of the existing conditions. In operation, the voltage U9 at the supply terminal 9 of the control circuit RS has a value which meets the condition U9 >[UDs -UBE (T2)], so that the transistor T2 of the starting circuit remains cut off.

For the internal layout of the control circuit RS, the construction shown, in particular, from FIG. 3 is advisable. This construction is realized, for example, in the commercially available type TDA 4600 (Siemens AG).

The block diagram of the control circuit according to FIG. 3 shows the power supply thereof via the terminal 9, the output stage being supplied directly whereas all other stages are supplied via Uref. In the starting circuit, the individual subassemblies are supplied with power sequentially. The d-c output voltage potential of the base current gain i.e. the voltage for the terminal 8 of the control circuit RS, and the charging of the capacitor C2 via the terminal 7 are formed even before the reference voltage Uref appears. Variations of the supply voltage U9 at terminal 9 and the power fluctuations at the terminal 8/terminal 7 and at the terminal 1 of the control circuit RS are leveled or smoothed out by the voltage control. The temperature sensitivity of the control circuit RS and, in particular, the uneven heating of the output and input stages and input stages on the semiconductor chip containing the control circuit in monolithically integrated form are intercepted by the temperature compensation provided. The output values are constant in a specific temperature range. The message for blocking the output stage, if the supply voltage at the terminal 9 is too low, is given also by this subassembly to a provided control logic.

The outer voltage divider of the terminal 1 via the resistors R5 and R4 to the control tap U forms, via terminal 3, the variable side of the bridge for the control amplifier formed as a differential amplifier. The fixed bridge side is formed by the reference voltage Uref via an internal voltage divider. Similarly formed are circuit portions serving for the detection of an overload short circuit and circuit portions serving for the "standby" no-load detection, which can be operated likewise via terminal 3.

Within a provided trigger circuit, the driving pulse length is determined as a function of the sawtooth rise at the terminal 4, and is transmitted to the control logic. In the control logic, the commands of the trigger circuit are processed. Through the zero-crossing identification at input 2 in the control circuit RS, the control logic is enabled to start the control input only at the zero point of the frequency oscillation. If the voltages at the terminal 5 and at the terminal 9 are too low, the control logic blocks the output amplifier at the terminal 8. The output amplifier at the terminal 7 which is responsible for the base charge in the capacitor C2, is not touched thereby.

The base current gain for the transistor T1 i.e. for the first transistor in accordance with the definition of the invention, is formed by two amplifiers which mutually operate on the capacitor C2. The roof inclination of the base driving current for the transistor T1 is impressed by the collector current simulation at the terminal 4 to the amplifier at the terminal 8. The control pulse for the transistor T1 at the terminal 8 is always built up to the potential present at the terminal 7. The amplifier working into the terminal 7 ensures that each new switching pulse at the terminal 8 finds the required base level at terminal 7.

Supplementing the comments regarding FIG. 1, it should also be mentioned that the cathode of the diode D1 connected by the anode thereof to the one end of the secondary winding II of the transformer Tr is connected via a resistor R11 to the protective input 5 of the control circuit RS whereas, in the circuit according to FIG. 2, the protective input 5 of the control circuit RS is supplied via a voltage divider R8, R7 directly from the output 3', 4' of the rectifier G delivering the rectified line a-c voltage, and which obtains the voltage required for executing its function. It is evident that the first possible manner of driving the protective input 5 can be used also in the circuit according to FIG. 2, and the second possibility also in a circuit in accordance with FIG. 1.

The control circuit RS which is shown in FIG. 3 and is realized in detail by the building block TDA 4600 and which is particularly well suited in conjunction with the blocking oscillator type switching power supply according to the invention has 9 terminals 1-9, which have the following characteristics, as has been explained in essence hereinabove:

Terminal 1 delivers a reference voltage Uref which serves as the constant-current source of a voltage divider R5.R4 which supplies the required d-c voltages for the differential amplifiers provided for the functions control, overload detection, short-circuit detection and "standby"-no load detection. The dividing point of the voltage divider R5 -R4 is connected to the terminal 3 of the control circuit RS. The terminal 3 provided as the control input of RS is controlled in the manner described hereinabove as input for the actual value of the voltage to be controlled or regulated by the secondary winding III of the transformer Tr. With this input, the lengths of the control pulses for the switching transistor T1 are determined.

Via the input provided by the terminal 2 of the control circuit RS, the zero-point identification in the control circuit is addressed for detecting the zero-point of the oscillations respectively applied to the terminal 2. If this oscillation changes over to the positive part, then the addressing pulse controlling the switching transistor T1 via the terminal 8 is released in the control logic provided in the control circuit.

A sawtooth-shaped voltage, the rise of which corresponds to the collector current of the switching transistor T1, is present at the terminal 4 and is minimally and maximally limited by two reference voltages. The sawtooth voltage serves, on the one hand as a comparator for the pulse length while, on the other hand, the slope or rise thereof is used to obtain in the base current amplification for the switching transistor T1, via the terminal 8, a base drive of this switching transistor T1 which is proportional to the collector current.

The terminal 7 of the control circuit RS as explained hereinbefore, determines the voltage potential for the addressing pulses of the transistor T2. The base of the switching transistor T1 is pulse-controlled via the terminal 8, as described hereinbefore. Terminal 9 is connected as the power supply input of the control circuit RS. If a voltage level falls below a given value, the terminal 8 is blocked. If a given positive value of the voltage level is exceeded, the control circuit is activated. The terminal 5 releases the terminal 8 only if a given voltage potential is present.

Foreign References:
DE2417628A1 1975-10-23 363/37
DE2638225A1 1978-03-02 363/49
Other References:
Grundig Tech. Info. (Germany), vol. 28, No. 4, (1981).
IBM Technical Disclosure Bulletin, vol. 19, No. 3, pp. 978, 979, Aug. 1976.
German Periodical, "Funkschau", (1975), No. 5, pp. 40 to 44.

Inventors:

Peruth, Gunther (Munich, DE) Siemens Aktiengesellschaft (Berlin and Munich, DE)







METZ 7345 MALLORCA COLOR QC  CHASSIS  682 G Automatic bias control system with compensated sense point:In an automatic kinescope bias (AKB) control system for a television receiver, a voltage representative of kinescope bias is derived from a sensing point coupled to the television signal processing channel and to AKB signal processing circuits. A switching network attenuates large white-going television signal amplitude components at the sensing point during picture information intervals, to preclude sense point voltage levels which could otherwise ultimately disrupt the operation of the AKB signal processing circuits during AKB operating intervals.


1. In a system including a video signal channel for processing video signals including image and blanking intervals, apparatus comprising:
means coupled to a sensing point in said video channel for deriving a signal representative of an operating characteristic of said video channel during image blanking intervals;
signal processing means responsive to said derived representative signal for providing a control signal to said video channel for maintaining a desired condition of said operating characteristic; and
means, coupled to said sensing point and responsive to video signals during image intervals, for attenuating amplitude excursions manifested by video signals at said sensing point during image intervals when said amplitude excursions exceed a given threshold level.
2. Apparatus according to claim 1, wherein:
said video signal amplitude excursions exceeding said threshold level are within a range of normally expected video signal amplitude excursions.
3. Apparatus according to claim 1, wherein
said attenuating means comprises switching means for providing selective attenuation of said video signal amplitude excursions at said sensing point during image intervals.
4. In a system including a video signal channel for processing video signals including image and blanking intervals, apparatus comprising:
means coupled to a sensing point in said video channel for deriving a signal representative of an operating characteristic of said video channel during image blanking intervals;
signal processing means responsive to said derived representative signal for providing a control signal to said video channel for maintaining a desired condition of said operating characteristic; and
means for attenuating amplitude excursions manifested by video signals at said sensing point during image intervals when said amplitude excursions exceed a given threshold level; wherein
said signal deriving means comprises an impedance coupled to said video signal channel, said impedance exhibiting a voltage thereacross which is related to amplitude excursions of said video signals during image intervals, and which is related to said operating characteristic of said video channel during said image blanking intervals; and
said attenuating means limits the voltage developed across said impedance in response to said video signal amplitude excursions exceeding said threshold level during said image intervals.
5. Apparatus according to claim 4, wherein
said attenuating means comprises switching means coupled to said impedance.
6. Apparatus according to claim 5, wherein
said switching means is coupled across said impedance.
7. Apparatus according to claim 6, wherein
said switching means comprises a normally non-conductive diode subject to being rendered conductive in response to said video signal amplitude excursions during image intervals.
8. In a video signal processing system including an image display device; and a video signal channel, including a video signal amplifier, for providing video signals including image and blanking intervals to said image display device; apparatus comprising:
means coupled to a sensing point in said video channel for deriving a signal representative of the magnitude of black image current conducted by said image display device during image blanking intervals;
signal processing means responsive to said derived representative signal for providing a bias control signal to said image display device for maintaining a desired level of black current; and
means, coupled to said sensing point and responsive to video signals during image intervals, for attenuating amplitude excursions manifested by video signals at said sensing point during image intervals when said amplitude excursions exceed a given threshold level.
9. Apparatus according to claim 8, wherein:
said video signal amplitude excursions exceeding said threshold level are within a range of normally expected video signal amplitude excursions; and
said attenuating means does not disrupt the display of video information by said display device in response to video signals provided via said video channel.
10. In a video signal processing system including an image display device; and a video signal channel, including a video signal amplifier, for providing video signals including image and blanking intervals to said image display device; apparatus comprising:
means coupled to a sensing point in said vide channel for deriving a signal representative of the magnitude of black image curretn conducted by said image display device during image blanking intervals;
signal processing means responsive to said derived representative signal for providing a bias control signal to said image display device for maintaining a desired level of black current; and
means for attenuating amplitude excursions manifested by video signal at said sensing point during image intervals when said amplitude excursions exceed a given threshold level; wherein
said attenuating means comprises switching means for providing selective attenuation of said video signal amplitude excursions at said sensing point during image intervals.
11. In a video signal processing system including an image display device; and a video signal channel, including a video signal amplifier, for providing video signals including image and blanking intervals to said image display device; apparatus comprising:
means coupled to a sensing point in said video channel for deriving a signal representative of the magnitude of black image current conducted by said image display device during image blanking intervals;
signal processing means responsive to said derived representative signal for providing a bias control signal to said image display device for maintaining a desired level of black current; and
means for attenuating amplitude excursions manifested by video signals at said sensing point during image intervals when said amplitude excursions exceed a given threshold level; wherein
said signal deriving means comprises an impedance coupled to said video signal channel, said impedance exhibiting a voltage thereacross which is related to amplitude excursions of said video signals during image intervals, and which is representative of the magnitude of said black current during said image blanking intervals; and
said attenuating means limits the voltage developed across said impedance in response to said video signal amplitude excursions exceeding said threshold level during said image intervals.
12. Apparatus according to claim 11, wherein
said attenuating means comprises switching means coupled to said impedance.
13. Apparatus according to claim 12, wherein
said switching means is coupled across said impedance.
14. Apparatus according to claim 13, wherein
said switching means comprises a normally non-conductive diode subject to being rendered conductive in response to said video signal amplitude excursions during image intervals.
15. Apparatus according to claims 11, 12, 13 or 14, wherein
said impedance is included in a signal conduction path of said video amplifier.
16. Apparatus according to claim 15, wherein
said video amplifier corresponds to a driver amplifier for supplying video output signals to said image display device.
17. In a video signal processing system including an image display device; and a video signal channel, including a video signal amplifier, for providing video signals including image and blanking intervals to said image display device; apparatus comprising:
means coupled to a sensing point in said video channel for deriving a signal representative of the magnitude of black image current conducted by said image display device during image blanking intervals;
signal processing means responsive to said derived representative signal for providing a bias control signal to said image display device for maintaining a desired level of black current; and
means for attenuating amplitude excursions manifested by video signals at said sensing point during image intervals when said amplitude excursions exceed a given threshold level; wherein
said video amplifier corresponds to a driver amplifier for supplying video output signals to said image display device, comprising
a first terminal for receiving video signals to be amplified, a second terminal coupled to an intensity control electrode of said image display device for supplying amplified video signals thereto, and a third terminal coupled to a reference potential and with said second terminal defining a main current conduction path of said video amplifier; and
feedback means coupled from said second terminal to said first terminal of said video amplifier;
said signal deriving means comprises a sensing impedance for receiving, via said feedback means, current variations representative of black current variations manifested at said second terminal of said amplifier means so that said impedance develops a voltage thereacross representative of black current variations; and
said attenuating means is coupled to said impedance for limiting video signal amplitude excursions across said impedance during image intervals.
18. Apparatus according to claim 17, wherein
said attenuating means comprises switching means coupled to said impedance for selectively attenuating said video signal amplitude excursions during image intervals.
19. Apparatus according to claim 18, wherein
said switching means is coupled across said impedance.
20. Apparatus according to claim 19, wherein
said switching means comprises a normally non-conductive diode subject to being rendered conductive in response to said video signal amplitude excursions during image intervals.
21. Apparatus according to claims 17, 18, 19 or 20, wherein said video amplifier comprises a cascode amplifier including:
a first transistor with a first electrode for receiving video signals to be amplified, a second electrode, and a third electrode coupled to a reference potential;
a second transistor with a first electrode coupled to a bias voltage, a second electrode coupled to an operating voltage supply via a load impedance and coupled to an intensity control electrode of said image display device for supplying amplified video signals thereto, and a third electrode coupled to said second electrode of said first transistor; and wherein
said feedback means is coupled from said second electrode of said second transistor to said first electrode of said first transistor; and
said sensing impedance is coupled between said second electrode of said first transistor and said third electrode of said second transistor.
22. A video signal processing system including an image display device; a video signal channel including a video signal amplifier for providing amplified video signals having image and blanking intervals to said image display device; and apparatus for automatically controlling the level of black image current conducted by said image display device, said control apparatus being operative during control intervals within image blanking intervals, and comprising:
means coupled to a sensing point in said video channel for deriving a signal representative of the magnitude of black image current conducted by said image display device during image blanking intervals;
signal sampling means coupled to said sensing point for receiving said representative signal at a signal input, for providing an output bias control signal to said image display device for maintaining a desired black current level;
a charge storage device coupled to said signal sampling means;
means operative during a reference interval within said control interval for establishing a reference bias voltage on said charge storage device and a corresponding reference bias condition for said signal sampling means; and
means for attenuating amplitude excursions manifested by video signals at said sensing point during image intervals when said amplitude excursions exceed a given threshold level.
23. Apparatus according to claim 22, wherein
said charge storage device comprises a capacitor for coupling said representative signal from said sensing point to said signal input of said signal sampling means, said capacitor having a first terminal coupled to said sensing point, and a second terminal coupled to said signal input of said sampling means;
said reference voltage is established at said second terminal of said capacitor; and
said signal input of said sampling means corresponds to an input of an integrated circuit device incorporating said sampling means.
24. Apparatus according to claim 23, wherein
said signal deriving means comprises an impedance coupled to said video signal channel, said impedance exhibiting a voltage thereacross which varies with amplitude excursions of said video signals during image intervals, and said impedance exhibiting a voltage thereacross which is representative of the magnitude of said black current during image blanking intervals; and
said attenuating means comprises switching means coupled to said impedance for selectively limiting the voltage developed across said impedance in response to video signal amplitude excursions exceeding said threshold level during said image intervals.
25. Apparatus according to claim 24, wherein
said switching means is coupled across said impedance.
26. Apparatus according to claim 25, wherein
said switching means comprises a normally non-conductive diode subject to being rendered conductive in response to said video signal amplitude excursions during image intervals.
27. Apparatus according to claim 24, 25 or 26, wherein
said impedance is included in a signal conduction path of said video amplifier.
28. In a video signal processing system including an image display device responsive to video signals applied thereto, a driver amplifier for said display device comprising:
a first terminal for receiving video signals to be amplified, a second terminal coupled to an an operating potential via an output load impedance and to an intensity control electrode of said image display device for supplying amplified video signals thereto, and a third terminal coupled to an operating potential and with said second terminal defining a main video signal current conduction path of said video amplifier;
a sensing impedance coupled to said main current conduction path remote from said output impedance;
means for conveying to said sensing impedance a signal representative of the bias condition of said image display device during image blanking intervals, for developing at a sensing point coupled to said sensing impedance a voltage related to said bias condition; and
means, coupled to said sensing point and responsive to video signals during image intervals, for attenuating amplitude excursions manifested by video signals at said sensing point during image intervals when said amplitude excursions exceed a given threshold level.
29. An amplifier according to claim 28, wherein
said sensing impedance is coupled in series with said main current conduction path; and
said conveying means comprises feedback means coupled from said second terminal to said first terminal.
30. In a video signal processing system including an image display device responsive to video signals applied thereto, a driver amplifier for said display device comprising:
a first terminal for receiving video signals to be amplified, a second terminal coupled to an operating potential via an output load impedance and to an intensity control electrode of said image display for supplying amplified video signals thereto, and a third terminal coupled to an operating potential and with said second terminal defining a main video signal current conduction path of said video amplifier;
a sensing impedance coupled to said main current conduction path remote from said output impedance;
means for conveying to said sensing impedance a signal representative of the bias condition of the said image display device during image blanking intervals for developing at a sensing point coupled to said sensing impedance a voltage related to said bias condition; and
means for attenuating amplitude excursions manifested by video signals at said sensing point during image intervals when said amplitude excursions exceed a given threshold level; wherein
said sensing impedance is coupled in series with said main current conduction path;
said conveying means comprises feedback means coupled from said second terminal to said first terminal; and
said attenuating means comprises switching means coupled to said impedance means, said switching means being rendered conductive for attenuating said video signal amplitude excursions at said sensing point during image intervals.
31. An amplifier according to claim 30, wherein
said switching means comprises a diode.
32. In a video signal processing system including an image display device responsive to video signals applied thereto, a driver amplifier for said display device comprising;
A first terminal for receiving video signals to be amplified, a second terminal coupled to an operating potential via an output load impedance and to an intensity control electrode of said image display device for supplying amplified video signals thereto, and a third terminal coupled to an operating potential and with said second terminal defining a main video signal current conduction path of said video amplifier;
a sensing impedance coupled to said main current conduction path remote from said output impedance;
means for conveying to said sensing impedance a signal representative of the bias condition of said image display device during image blanking intervals, for developing at a sensing point coupled to said sensing impedance a voltage related to said bias condition; and
means for attenuating amplitude excursions manifested by video signals at said sensing point during image intervals when said amplitude excursions exceed a given threshold level; wherein
said video signal amplitude excursions exceeding said threshold level are within a range of normally expected video signal amplitude excursions; and
said attenuating means does not disrupt the display of video information by said display device in response to video signal provided via said driver amplifier.

Description:

This invention concerns a system for sensing and automatically controlling a characteristic of a signal processing network. In particular, this invention concerns a system for sensing and automatically controlling the black image current conducted by a video signal image reproducing device, wherein compensation is provided for potentially distruptive video signal components appearing at the sensing point during intervals when the control system is inactive.
Color television receivers sometimes employ an automatic kinescope bias (AKB) control system for automatically establishing proper black image representative current levels for each electron gun of a color kinescope associated with the receiver. As a result of this operation, pictures reproduced by the kinescope are prevented from being adversely affected by variations of kinescope operating parameters (e.g., due to aging and temperature effects).
An AKB system typically operates during image blanking intervals, at which time each electron gun of the kinescope conducts a small black image representative blanking current in response to a reference voltage representative of black video signal information. This current is processed by the AKB system to generate a signal which is representative of the currents conducted during the blanking intervals, and which is used to maintain a desired black current level.
In one type of AKB system control circuits respond to a periodically derived pulse signal with a magnitude representative of the cathode black current level. The derived signal is processed by control circuits including clamping and sampling networks for developing a kinescope bias correction signal which increases or decreases in magnitude and is coupled to the kinescope for maintaining a correct black current level. The clamping network includes a clamping capacitor for establishing a reference condition for the signal information to be sampled. The reference condition is established by applying a reference voltage to the clamping capacitor which is coupled to the sampling network during the clamping interval. An AKB system of this type is described in U.S. Pat. No. 4,331,981 of R. P. Parker, for example.
In the automatic control system disclosed herein, a bias representative signal is derived at a sensing point during video signal blanking intervals. The sensing point exhibits voltage variations related to amplitude variations of the video signal during video signal image intervals when signal processing circuits of the control system are inactive.
It is herein recognized that the presence of large amplitude video signals at the sensing point can have a disruptive effect on the operation of the signal processing circuits of the control system, particularly when such circuits are constructed in the form of an integrated circuit. Accordingly, a control system disclosed herein includes means for attenuating large video signal amplitude components which can appear at the control system sensing point during video signal picture intervals when the signal processing circuits of the control system are inactive.
In the drawing:
FIG. 1 shows a portion of a color television receiver with an automatic kinescope bias control system including a sensing circuit according to the principles of the present invention; and
FIG. 2 illustrates signal waveforms associated with the operation of the system in FIG. 1.
In FIG. 1, television signal processing circuits 10 provide separated luminance (Y) and chrominance (C) components of a composite color television signal to a luminance-chrominance signal processing network 12. Processor 12 includes luminance and chrominance gain control circuits, DC level setting circuits (e.g, comprising keyed black level clamping circuits), color demodulators for developing r-y, g-y and b-y color difference signals, and matrix amplifiers for combining the latter signals with processed luminance signals to provide low level color image representative signals r, g and b. These signals are amplified and otherwise processed by circuits within video output signal processing networks 14a, 14b and 14c, respectively, which supply high level amplified color image signals R, G and B to respective cathode intensity control electrodes 16a, 16b and 16c of a color kinescope 15. Network 14a, 14b and 14c also perform functions related to the automatic kinescope bias (AKB) control function, as will be discussed. Kinescope 15 is of the self-converging in-line gun type with a commonly energized control grid 18 associated with each of the electron guns comprising cathode electrodes 16a, 16b and 16c.
Since output signal processors 14a, 14b and 14c are similar in this embodiment, the following discussion of the operation of processor 14a also applies to processors 14b and 14c.
Processor 14a includes a kinescope driver stage comprising an input transistor 20 configured as a common emitter amplifier which receives video signal R from processor 12 via an input resistor 21, and an output high voltage transistor 22 configured as a common base ampifier which together with transistor 20 forms a cascode video driver amplifier. High level video signal R, suitable for driving kinescope cathode 16a, is developed across a load resistor 24 in the collector output circuit of transistor 22. Direct current negative feedback for driver 20, 22 is provided by means of a resistor 25. The signal gain of cascode amplifier 20, 22 is primarily determined by the ratio of the value of feedback resistor 25 to the value of input resistor 21.
A sensing resistor 30 DC coupled in series with and between the collector-emitter paths of transistor 20, 22 serves to develop a voltage, at a relatively low voltage sensing node A, representing the level of kinescope cathode black current conducted during kinescope blanking intervals. A normally non-conductive Zener Diode 40 is coupled across sensing resistor 30. Resistor 30 and Zener Diode 40 operate in conjunction with the AKB system of the receiver, which will now be described.
A timing signal generator 40 containing combinational and sequential logic control circuits as well as level shifting circuits responds to periodic horizontal synchronizing rate signals (H) and to periodic vertical synchronizing rate signals (V), both derived from deflection circuits of the receiver for generating timing signals V _B , V _S , V _C , V _P and V _G which control the operation of the AKB function during periodic AKB intervals. Each AKB interval begins shortly after the end of the vertical retrace interval within the vertical blanking interval, and encompasses several horizontal line intervals also within the vertical blanking interval and during which video signal image information is absent. These timing signals are illustrated by the waveforms in FIG. 2.
Referring to FIG. 2 for the moment, timing signal V _B , used as a video blanking signal, comprises a positive pulse generated soon after the vertical retrace interval ends at time T ₁ , as indicated by reference to signal waveform V. Blanking signal V _B exists for the duration of the AKB interval and is applied to a blanking control input terminal of luminance-chrominance processor 12 for casing the r, g and b outputs of processor 12 to exhibit a black image representative DC reference level at the signal outputs of processor 12. Timing signal V _G , used as a positive grid drive pulse, encompasses three horizontal line intervals within the vertical blanking interval. Timing signal V _C is used to control the operation of a clamping circuit associated with the signal sampling function of the AKB system. Timing signal V _S , used as a sampling control signal, occurs after signal V _C and serves to time the operation of a sample and hold circuit which develops a DC bias control signal for controlling the kinescope cathode black current level. Signal V _S encompasses a sampling interval the beginning of which is slightly delayed relative to the end of the clamping interval encompassed by signal V _C , and the end of which substantially coincides with the end of the AKB interval. A negative-going auxiliary pulse V _P coincides with the sampling interval. Signal timing delays T _D indicated in FIG. 2 are on the order of 200 nanoseconds.
Referring again to FIG. 1, during the AKB interval positive pulse V _G (e.g., on the order of +10 volts) biases grid 18 of the kinescope for causing the electron gun comprising cathode 16a and grid 18 to increase conduction. At times other than the AKB intervals, signal V _G provides the normal, less positive, bias for grid 18. In response to positive grid pulse V _G , a similarly phased, positive current pulse appears at cathode 16a during the grid pulse interval. The amplitude of the cathode output current pulse so developed is proportional to the level of cathode black current conduction (typically a few microamperes).
The induced positive cathode output pulse appears at the collector of transistor 22, and is coupled to the base input of transistor 20 via feedback resistor 25, causing the current conduction of transistor 20 to increase proportionally while the cathode pulse is present. The increased current conducted by transistor 20 causes a related voltage to be developed across sensing resistor 30. This voltage is in the form of a negative-going voltage change which appears at sensing node A and which is proportional in magnitude to the magnitude of the black current representative cathode output pulse. The magnitude of the voltage perturbation at node A is determined by the product of the value of resistor 30 times the magnitude of the perturbation current flowing through resistor 30. The operation of sensing resistor 30 in combination with kinescope driver 20, 22 is described in detail in copending U.S. patent application Ser. No. 394,422 of R. P. Parker, now U.S. Pat. No. 4,463,385 titled "Kinescope Black Level Current Sensing Apparatus", incorporated herein by reference. The voltage change at node A is coupled via a small resistor 31 to a node B at which a voltage change V ₁ , essentially corresponding to the voltage change at node A, is developed. Node B is coupled to a bias control voltage processing network 50.
Network 50 performs signal clamping and sampling functions. The clamping function is performed during a clamping interval within each AKB interval by means of a feedback clamping network comprising an input AC coupling capacitor 51, an amplifier 52, and an electronic switch 56. The sampling function is performed during a sampling interval, following the clamping interval during each AKB interval, by means of a network comprising amplifier 52, an electronic switch 57, and an average responding charge storage capacitor 58.
A kinescope bias correction voltage is developed across capacitor 58 and is coupled via a translating circuit comprising a resistor network 60, 62, 64 to the kinescope driver via a bias control input at the base of transistor 20. The correction voltage developed across capacitor 58 serves to automatically maintain a desired correct level of kinescope black current conduction. The bias correction voltage developed across storage capacitor 58 is a function of both voltage change V ₁ developed at node B during the clamping interval, and a voltage change V ₂ developed at node B during the subsequent sampling interval, as will be discussed in greater detail subsequently in connection with the waveforms shown in FIG. 2.
During the clamping set-up reference interval, switch 56 is rendered conductive in response to clamping control signal V _C . At this time switch 57 is non-conductive so that the charge on storage capacitor 58 remains unaffected during the clampling interval. As a consequence of the feedback action during the clamping interval, the negative terminal (-) of capacitor 51 is reference to (i.e., clamped to) a reference voltage V _R which is a function of a fixed reference voltage V _REF applied to an input of amplifier 52, for establishing an input reference bias condition at a signal input of amplifier 52 at a node C. At this time the voltage V ₃ across input capacitor 51 is a function of the level of voltage change V ₁ developed at node B, and the clamping reference voltage V _R provided via the feedback action.
During the following sampling interval when voltage channel V ₂ is developed at node B, switch 56 is rendered non-conductive, and switch 57 is rendered conductive in response to sampling control signal V _S . The magnitude of voltage change V ₂ is indicative of the magnitude of the kinescope black current level, and is sampled by means of amplifier 52 (with respect to reference voltage V _R ) to develop a corresponding voltage across storage capacitor 58. Network 50 can include circuits of the types described in U.S. Pat. No. 4,331,981 of R. P. Parker, and in a copending U.S. patent application of P. Filliman Ser. No. 437,827 titled "Signal Sampling Network with Reduced Offset Error". Amplifier 52 is preferably rendered non-conductive during picture intervals when the AKB clamping and sampling functions are not being performed. This can be accomplished by disabling the operating current source of amplifier 52 in response to a keying signal coincident with the picture intervals.
Zener diode 40 serves to attenuate large amplitude video signal components, and particularly video signal peaking components, which otherwise appear with significant magnitude at sensing node A during field scanning picture information intervals. In the absence of the attenuation provided by Zener Diode 40, large amplitude video signal appearing at sensing node A can ultimately disrupt the AKB signal processing function, particularly with respect to the development of clamping reference voltage V _R , when the AKB signal processor including amplifier 52 is constructed in the form of an integrated circuit with an input at node C, as follows.
Sensing node A and node B exhibit a nominal DC voltage (V _DC ) of approximately +8.8 volts for black video signal conditions during picture intervals, as well as during AKB intervals (except when voltage change V ₂ is generated during AKB sampling intervals as will be discussed subsequently). At the end of the AKB clamping reference interval, voltage V ₃ across clamp capacitor 51 is equal to V _DC -V _R , where V _DC is the nominal black level voltage (+8.8 volts) and V _R is the reference voltage (e.g., +6 volts) developed at the negative terminal of capacitor 51 during the clamping interval.
During the field scanning picture interval which begins at the end of the vertical blanking interval, video signals applied to kinescope driver 20, 22 can cause large voltage transitions to be developed at the collector output of driver transistor 22 and at the kinescope cathode. A large video input signal r (e.g., a 100 IRE peak white signal) can cause the collector output voltage of driver transistor 22 to decrease by about 130 volts. A heavily peaked video signal with accentuated white-going amplitude transitions can increase the effective video signal peak white level by 20%, causing the collector output voltage of driver transistor 22 to decrese by an additional 20%. The effective peak white level of the video signal can be increased by more than 20% in receivers which do not include circuits for automatically limiting the amount of peaking present in the video signal.
A version of such peak white amplitude transitions appears at AKB sense point A, and can cause a significant and potentially troublesome negative-going transient decrease in the voltage at sense point A. This transient voltage decrease can be as great as 7.28 volts (or even greater in receivers without peak limiting circuits) according to the expression ΔV _A =R ₃₀ /R ₂₄ (ΔV _K )
where
ΔV _A corresponds to the transient voltage decrease at sensing point A;
R ₃₀ and R ₂₄ correspond to the values of resistors 30 and 24, respectively; and
ΔV _K corresponds to the amount by which the kinescope cathode voltage decreases in response to large white-going video signal amplitude transitions including peaking effects (e.g., 130 volts×1.2).
The voltage at input node C of the AKB signal processor is given by V _A -V ₃ , where V _A is the voltage at sense point A and V ₃ is the voltage across capacitor 51. More specifically, the voltage at input node C is given by (V _DC -ΔV _A )-(V _DC -V _R )
where
V _DC is the nominal black level voltage at sense point A (+8.8 volts);
ΔV _A is the transient voltage at sense point A; and
V _R is the clamping reference voltage developed on and stored at the negative terminal of capacitor 51 (+6.0 volts).
Thus in this instance large white-going video signal amplitude transitions can cause a negative voltage of -1.28 volts to appear at input node C of the AKB signal processor.
This negative voltage at node C is large enough to forward bias the integrated circuit substrate-to-ground semiconductor junction at the input of the AKB signal processor. A diode D _S represents the substrate-to-ground semiconductor junction, and is forward biased into conduction since the -1.28 volt negative voltage transient at node C exceeds the threshold conduction level (0.7 volts) of substrate diode D _S . If this were to occur, the voltage at node C would be clamped to -0.7 volts and the negative terminal of clamp capacitor 51 would rapidly discharge to a distorted reference level which might impair the subsequent AKB clamping and sampling functions. This condition could be difficult to recover from during succeeding AKB operating intervals, and the distorted reference level could persist for a relatively long time, depending on the nature of the video signal picture information, its peaking content and duration. As a consequence, proper AKB operation could be distrupted such that an abnormally high kinescope black current level would result with an associated unwanted visible increase in picture brightness.
Zener diode 40 prevents the described objectionable effects caused by large amplitude video signals during the picture interval. Specifically, the action of diode 40 prevents clamping reference voltage V _R from being disturbed from one AKB interval to another, by preventing picture interval video signal amplitude excursions of significant magnitude from being developed at AKB sensing point A, as follows.
The emitter voltage of driver transistor 22 is substantially constant (+10.5 volts), and is equal to the fixed base bias voltage of transistor 22 (+11.2 volts) minus the base-emitter junction voltage drop of transistor 22 (+0.7 volts). During AKB intervals, the collector voltage of transistor 20 and thereby the voltage at sense point A vary in response to the perturbation current conducted to the base of video signal amplifier transistor 20 via feedback resistor 25, as a function of the induced kinescope output current pulse developed as discussed previously. The voltage across sense resistor 30 changes with variations in the current conduction of transistor 20 during both AKB intervals and video information picture intervals.
Zener diode 40 is normally non-conductive, but conducts whenever the conduction of transistor 20 causes the voltage across sense resistor 30 to exceed the Zener threshold conduction voltage of diode 40. When Zener diode 40 conducts, the collector current of transistor 20 flows through Zener diode 40 rather than through sense resistor 30. At this time the voltage across resistor 30 is clamped to the fixed voltage developed across Conductive Zener diode 40, whereby the voltage across resistor 30 and the voltage at sense point A do not change. Accordingly, the amount by which the voltage at sense point A can decrease in response to a large amplitude white-going video signal is limited as a function of the voltage developed across diode 40 when conducting.
The lowest voltage capable of being developed at sense point A is equal to the substantially fixed emitter voltage of transistor 22 (+10.5 volts), minus the substantially fixed Zener voltage drop across diode 40. When diode 40 exhibits a +6.2 volt Zener voltage, the maximum voltage decrease at point A (i.e., the most negative-going transient voltage ΔV _A ) is limited to +4.3 volts. In such case the voltage at input node C of the AKB signal processor exhibits a corresponding minimum voltage of +1.7 volts, whereby the input substrate to ground semiconductor junction represented by diode D _S is prevented from becoming forward biased. Accordingly, reference voltage V _R and the AKB signal processing function remain undisturbed in the presence of large peak white video signal amplitude transitions during picture intervals.
The video output signal developed at the output of driver transistor 22 and coupled to the kinescope advantageously is not disturbed when Zener diode 40 conducts during picture intervals. This results because the emitter current of driver transistor 22 does not change when diode 40 conducts. When diode 40 conducts, the signal current which would otherwise flow through resistor 30 flows instead through conductive diode 40.
Other embodiments of the disclosed invention can be developed. For example, an electronic switch can be coupled across resistor 30 and keyed such that the switch is conductive during picture intervals and non-conductive during AKB intervals.
Following is a more detail discussion of the clamping and sampling operation of network 50, made with reference to the waveforms of FIG. 2.
Auxiliary signal V _p is applied to circuit node B in FIG. 1 via a diode 35 and a voltage translating impedance network comprising resistors 32 and 34. Signal V _P exhibits a given positive DC level at all times except during the AKB sampling interval, for maintaining diode 35 conductive so that a DC bias voltage is developed at node B. When the positive DC component of signal V _P is present, the junction of resistors 32 and 34 is clamped to a voltage equal to the positive DC component of signal V _P , minus the voltage drop across diode 35. Signal V _P manifests a negative-going, less positive fixed amplitude pulse component during the AKB sampling interval. Diode 35 is rendered non-conductive in response to negative pulse V _P , whereby the junction of resistors 32 and 34 is unclamped. Resistor 31 causes insignificant attenuation of the voltage change (V ₁ ) developed at node B since the value of resistor 31 is small relative to the values of resistors 32 and 34.
Prior to the clamping interval but during the AKB interval, the pre-existing nominal DC voltage (V _DC ) appearing at node B charges the positive terminal of capacitor 51. During the clamping interval when grid drive pulse V _G is developed, the voltage at node A decreases in response to pulse V _G by an amount representative of the black current level. This causes the voltage at node B to decrease to a level substantially equal to V _DC -V ₁ . Also during the clamping interval, timing signal V _C renders clamping switch 56 conductive, whereby via feedback action reference voltage V _R is developed at the negative terminal of clamp capacitor 51 as discussed. During the clamping interval, voltage V ₃ across capacitor 51 is a function of reference set-up voltage V _R at the negative terminal of capacitor 51, and a voltage at the positive terminal of capacitor 51 corresponding to the difference between the described pre-existing nominal DC level (V _DC ) at node B and voltage change V ₁ developed at node B during the clamping interval. Thus voltage V ₃ across capacitor 51 during the clamping reference interval is a function of the level of black current representative voltage change V ₁ , which may vary. Voltage V ₃ can be expressed as (V _DC -V ₁ )-V _R .
During the immediately following sample interval, positive grid drive pulse V _G is absent, causing the voltage at node B to increase positively to the pre-existing nominal DC level V _DC that appeared prior to the clamping interval. Simultaneously, negative pulse V _P appears, reverse biasing diode 35 and perturbing (i.e., momentarily changing) the normal voltage translating and coupling action of resistors 32, 34 such that the voltage at node B is reduced by an amount V ₂ as indicated in FIG. 2. At the same time, clamping switch 56 is rendered non-conductive and switch 57 conducts in response to signal V _S .
Thus during the sampling interval the voltage applied to the signal input of amplifier 52 is equal to the difference between the voltage at node B and voltage V ₃ across input capacitor 51. The input voltage applied to amplifier 52 is a function of the magnitude of voltage change V ₁ , which can vary with changes in the kinescope black current level.
The voltage on output storage capacitor 58 remains unchanged during the sampling interval when the magnitude of voltage change V ₁ developed during the clamping interval equals the magnitude of voltage change V ₂ developed during the sampling interval, indicating a correct kinescope black current level. This results because during the sampling interval, voltage change V ₁ at node B increases in a positive direction (from the clamping set-up reference level) when the grid drive pulse is removed, and voltage change V ₂ causes a simultaneous negative-going voltage perturbation at node B. When kinescope bias is correct, positive-going voltage change V ₁ and negative-going voltage change V ₂ exhibit equal magnitudes whereby these voltage changes mutually cancel during the sampling interval, leaving the voltage at node B unchanged.
When the magnitude of voltage change V ₁ is less than the magnitude of voltage change V ₂ , amplifier 52 proportionally charges storage capacitor 58 via switch 57 in a direction for increasing cathode black current conduction. Conversely, amplifier 52 proportionally discharges storage capacitor 58 via switch 57 for causing decreased cathode black current conduction when the magnitude of voltage change V ₁ is greater than the magnitude of voltage change V ₂ .
As more specifically shown by the waveforms of FIG. 2, the amplitude "A" of voltage change V ₁ is assumed to be approximately three millivolts when the cathode black current level is correct, and varies over a range of a few millivolts (±Δ) as the cathode black current level increases and decreases relative to the correct level as the operating characteristics of the kinescope change. Thus the clamping interval set-up reference voltage across capacitor 51 varies with changes in the magnitude of voltage V ₁ as the cathode black current level changes. Voltage change V ₂ at node B exhibits an amplitude "A" of approximately three millivolts, which corresponds to amplitude "A" associated with voltage change V ₁ , when the black current level is correct.
As indicated by waveform V _COR in FIG. 2, corresponding to a condition of correct kinescope bias, the voltage at the signal input of amplifier 52 remains unchanged during the sampling interval when voltages V ₁ and V ₂ are both of amplitude "A". However, as indicated by waveform V _H , the signal input voltage of amplifier 52 increases by an amount Δ when voltage change V ₁ exhibits amplitude "A+Δ", corresponding to a high black current level. In this event output storage capacitor 58 is discharged so that the bias control voltage applied to the base of transistor 20 causes the collector voltage of transistor 22 to increase, whereby the cathode black current decreases toward the correct level.
Conversely, and as indicated by waveform V _L , the signal input voltage of amplifier 52 decreases by an amount Δ during the sampling interval when voltage change V ₁ exhibits amplitude "A-Δ", corresponding to a low black current level. In this case output storage capacitor 58 charges, causing the collector voltage of transistor 22 to decrease whereby the cathode black current increases toward the correct level. In either case, several sampling intervals may be required to achieve the correct black current level.
The described combined-pulse sampling technique employing voltage changes V ₁ and V ₂ is discussed in greater detail in a copending U.S. patent application Ser. No. 434,314 of R. P. Parker titled "Signal Processing Network For An Automatic Kinescope Bias Control System", incorporated herein by reference. This copending application also discloses additional information concerning the arrangement including auxiliary control signal V _P , as well as disclosing a suitable arrangement for timing signal generator 40.