PHILIPS 16P3291 /1 CHASSIS TVC12 (B.T.90°) INTERNAL VIEW.

The PHILIPS CHASSIS TVC12 is a outsider compared to the common known Kxx series present in that era of time.

The Technology and structure of development is different than the others even because it was developed for small screen format screens combining multistandard features toghether with stereo sound and spatial stereo effects and further sophisticated digital tuning search system (PHILIPS TRD4)

The set (as any respectable tellye) is almost full of circuits;

- Bottom: power supply,

- Right side cabinet : Sound power amplifier and tone controls.

- The chassis is semi modular carrying almost all functions of the receiver and even by it's
form is remembering the K40 the chassis TVC12 it's completely different.


CIRCUITS DESCRIPTIONS.


PHILIPS  16P3291 /1  CHASSIS TVC12  (B.T.90°) TEA1039 Control circuit for switched-mode power supply.

GENERAL DESCRIPTION
The TEA1039 is a bipolar integrated circuit intended for the control of a switched-mode power supply. Together with an
external error amplifier and a voltage regulator (e.g. a regulator diode) it forms a complete control system. The circuit is
capable of directly driving the SMPS power transistor in small SMPS systems.
It has the following features:
· Suited for frequency and duty factor regulation.
· Suited for flyback converters and forward converters.
· Wide frequency range.
· Adjustable input sensitivity.
· Adjustable minimum frequency or maximum duty factor limit.
· Adjustable overcurrent protection limit.
· Supply voltage out-of-range protection.
· Slow-start facility.


FUNCTIONAL DESCRIPTION
The TEA1039 produces pulses to drive the transistor in a
switched-mode power supply. These pulses may be varied
either in frequency (frequency regulation mode) or in width
(duty factor regulation mode).
The usual arrangement is such that the transistor in the
SMPS is ON when the output of the TEA1039 is HIGH, i.e.
when the open-collector output transistor is OFF. The duty
factor of the SMPS is the time that the output of the
TEA1039 is HIGH divided by the pulse repetition time.
Supply VCC (pin 9)
The circuit is usually supplied from the SMPS that it
regulates. It may be supplied either from its primary d.c.
voltage or from its output voltage. In the latter case an
auxiliary starting supply is necessary.
The circuit has an internal VCC out-of-range protection. In
the frequency regulation mode the oscillator is stopped; in
the duty factor regulation mode the duty factor is made
zero. When the supply voltage returns within its range, the
circuit is started with the slow-start procedure.
When the circuit is supplied from the SMPS itself, the
out-of-range protection also provides an effective
protection against any interruption in the feedback loop.
Mode input M (pin 6)
The circuit works in the frequency regulation mode when
the mode input M is connected to ground (VEE, pin 7). In
this mode the circuit produces output pulses of a constant
width but with a variable pulse repetition time.
The circuit works in the duty factor regulation mode when
the mode input M is left open. In this mode the circuit
produces output pulses with a variable width but with a
constant pulse repetition time.
Oscillator resistor and capacitor connections RX and
CX (pins 4 and 5)
The output pulse repetition frequency is set by an oscillator
whose frequency is determined by an external capacitor
C5 connected between the CX connection (pin 5) and
ground (VEE, pin 7), and an external resistor R4 connected
between the RX connection (pin 4) and ground. The
capacitor C5 is charged by an internal current source,
whose current level is determined by the resistor R4. In the
frequency regulation mode these two external components determine the minimum frequency; in the
duty factor regulation mode they determine the working
frequency (see Fig.4). The output pulse repetition
frequency varies less than 1% with the supply voltage over
the supply voltage range.
In the frequency regulation mode the output is LOW from
the start of the cycle until the voltage on the capacitor
reaches 2 V. The capacitor is further charged until its
voltage reaches the voltage on either the feedback input
FB or the limit setting input LIM, provided it has exceeded
2,2 V. As soon as the capacitor voltage reaches 5,9 V the
capacitor is discharged rapidly to 1,3 V and a new cycle is
initiated (see Figs 5 and 6).
For voltages on the FB and LIM inputs lower than 2,2 V,
the capacitor is charged until this voltage is reached; this
sets an internal maximum frequency limit.
In the duty factor regulation mode the capacitor is charged
from 1,3 V to 5,9 V and discharged again at a constant
rate. The output is HIGH until the voltage on the capacitor
exceeds the voltage on the feedback input FB; it becomes
HIGH again after discharge of the capacitor (see Figs 7
and 8). An internal maximum limit is set to the duty factor
of the SMPS by the discharging time of the capacitor.
Feedback input FB (pin 3)
The feedback input compares the input current with an
internal current source whose current level is set by the
external resistor R4. In the frequency regulation mode, the
higher the voltage on the FB input, the longer the external
capacitor C5 is charged, and the lower the frequency will
be. In the duty factor regulation mode external capacitor
C5 is charged and discharged at a constant rate, the
voltage on the FB input now determines the moment that
the output will become LOW. The higher the voltage on the
FB input, the longer the output remains HIGH, and the
higher the duty factor of the SMPS.
Limit setting input LIM (pin 2)
In the frequency regulation mode this input sets the
minimum frequency, in the duty factor regulation mode it
sets the maximum duty factor of the SMPS. The limit is set
by an external resistor R2 connected from the LIM input to
ground (pin 7) and by an internal current source, whose
current level is determined by external resistor R4.
A slow-start procedure is obtained by connecting a
capacitor between the LIM input and ground. In the
frequency regulation mode the frequency slowly
decreases from fmax to the working frequency. In the duty
factor regulation mode the duty factor slowly increases
from zero to the working duty factor.
Overcurrent protection input CM (pin 1)
A voltage on the CM input exceeding 0,37 V causes an
immediate termination of the output pulse. In the duty
factor regulation mode the circuit starts again with the
slow-start procedure.
Output Q (pin 8)
The output is an open-collector n-p-n transistor, only
capable of sinking current. It requires an external resistor
to drive a n-p-n transistor in the SMPS (see Figs 9 and 10).
The output is protected by two diodes, one to ground and
one to the supply.
At high output currents the dissipation in the output
transistor may necessitate a heatsink.


PHILIPS  16P3291 /1  CHASSIS TVC12  (B.T.90°) TDA2593 SYNCHRO AND HORIZONTAL DEFLECTION CONTROL FOR COLOR TV SET

DESCRIPTION
The TDA2593 isa circuit intended for the horizontal
deflectionof color TVsets, suppliedwith transistors
or SCR’S.

.LINE OSCILLATOR(two levels switching) .PHASE COMPARISON BETWEEN SYNCHRO-
PULSE AND OSCILLATOR VOLTAGE
Ø 1, ENABLED BY AN INTERNAL PULSE,
(better parasitic immunity) .PHASE COMPARISON BETWEEN THE FLYBACK
PULSES AND THE OSCILLATORVOLTAGE
Ø2 .COINCIDENCE DETECTOR PROVIDING A
LARGE HOLD-IN-RANGE .FILTER CHARACTERISTICS AND GATE
SWITCHING FOR VIDEO RECORDER APPLICATION
.NOISE GATED SYNCHRO SEPARATOR .FRAME PULSE SEPARATOR .BLANKING AND SAND CASTLE OUTPUT
PULSES .HORIZONTAL POWER STAGE PHASE LAGGING
CIRCUIT .SWITCHING OF CONTROL OUTPUT PULSE
WIDTH .SEPARATED SUPPLY VOLTAGE OUTPUT
STAGE ALLOWING DIRECT DRIVE OF
SCR’S CIRCUIT .SECURITY CIRCUIT MAKES THE OUTPUT
PULSE SUPPRESSED WHEN LOW SUPPLY
VOLTAGE.




GENERAL DESCRIPTION
The TDA3560A is a decoder for the PAL colour television standard. It combines all functions required for the identification
and demodulation of PAL signals. Furthermore it contains a luminance amplifier, an RGB-matrix and amplifier. These
amplifiers supply output signals up to 5 V peak-to-peak (picture information) enabling direct drive of the discrete output
stages. The circuit also contains separate inputs for data insertion, analogue as well as digital, which can be used for
text display systems (e.g. (Teletext/broadcast antiope), channel number display, etc. Additional to the TDA3560, the
circuit includes the following features:
· The peak white limiter is only active during the time that the 9,3 V level at the output is exceeded. The start of the
limiting function is delayed by one line period. This avoids peak white limiting by test patterns which have abrupt
transitions from colour to white signals.
· The brightness control is obtained by inserting a variable pulse in the luminance channel. Therefore the ratio of
brightness variation and signal amplitude at the three outputs will be identical and independent of the difference in gain
of the three channels. Thus discolouring due to adjustment of contrast and brightness is avoided.
· Improved suppression of the internal RGB signals when the device is switched to external signals, and vice versa.
· Non-synchronized external RGB signals do not disturb the black level of the internal signals.
· Improved suppression of the residual 4,4 MHz signal in the RGB output stages.
· Cascoded stages in the demodulators and burst phase detector minimize the radiation of the colour demodulator
inputs.
· High current capability of the RGB outputs and the chrominance output.

APPLICATION INFORMATION
The function is described against the corresponding pin
number.
1. + 12 V power supply
The circuit gives good operation in a supply voltage range
between 8 and 13,2 V provided that the supply voltage for
the controls is equal to the supply voltage for the
TDA3561A. All signal and control levels have a linear
dependency on the supply voltage. The current taken by
the device at 12 V is typically 85 mA. It is linearly
dependent on the supply voltage.
2. Control voltage for identification
This pin requires a detection capacitor of about 330 nF for
correct operation. The voltages available under various
signal conditions are given in the specification.
3. Chrominance input
The chroma signal must be a.c.-coupled to the input.
Its amplitude must be between 55 mV and 1100 mV
peak-to-peak (25 mV to 500 mV peak-to-peak burst
signal). All figures for the chroma signals are based on a
colour bar signal with 75% saturation, that is the
burst-to-chroma ratio of the input signal is 1 : 2,25.
4. Reference voltage A.C.C. detector
This pin must be decoupled by a capacitor of about 330
nF. The voltage at this pin is 4,9 V.
5. Control voltage A.C.C.
The A.C.C. is obtained by synchronous detection of the
burst signal followed by a peak detector. A good noise
immunity is obtained in this way and an increase of the
colour for weak input signals is prevented. The
recommended capacitor value at this pin is 2,2 mF.
6. Saturation control
The saturation control range is in excess of 50 dB.
The control voltage range is 2 to 4 V. Saturation control is
a linear function of the control voltage.
When the colour killer is active, the saturation control
voltage is reduced to a low level if the resistance of the
external saturation control network is sufficiently high.
Then the chroma amplifier supplies no signal to the
demodulator. Colour switch-on can be delayed by proper
choice of the time constant for the saturation control
setting circuit.
When the saturation control pin is connected to the power
supply the colour killer circuit is overruled so that the colour
signal is visible on the screen. In this way it is possible to
adjust the oscillator frequency without using a frequency
counter (see also pins 25 and 26).
7. Contrast control
The contrast control range is 20 dB for a control voltage
change from + 2 to + 4 V. Contrast control is a linear
function of the control voltage. The output signal is
suppressed when the control voltage is 1 V or less. If one
or more output signals surpasses the level of 9 V the peak
white limiter circuit becomes active and reduces the output
signals via the contrast control by discharging C2 via an
internal current sink.
8. Sandcastle and field blanking input
The output signals are blanked if the amplitude of the input
pulse is between 2 and 6,5 V. The burst gate and clamping
circuits are activated if the input pulse exceeds a level of
7,5 V.
The higher part of the sandcastle pulse should start just
after the sync pulse to prevent clamping of video signal on
the sync pulse. The width should be about 4 ms for proper
A.C.C. operation.
9. Video-data switching
The insertion circuit is activated by means of this input by
an input pulse between 1 V and 2 V. In that condition, the
internal RGB signals are switched off and the inserted
signals are supplied to the output amplifiers. If only normal
operation is wanted this pin should be connected to the
negative supply. The switching times are very short
(< 20 ns) to avoid coloured edges of the inserted signals
on the screen.
10. Luminance signal input
The input signal should have a peak-to-peak amplitude of
0,45 V (peak white to sync) to obtain a black-white output
signal to 5 V at nominal contrast. It must be a.c.-coupled to
the input by a capacitor of about 22 nF. The signal is
clamped at the input to an internal reference voltage.
A 1 kW luminance delay line can be applied because the
luminance input impedance is made very high.
Consequently the charging and discharging currents of the
coupling capacitor are very small and do not influence the
signal level at the input noticeably. Additionally the
coupling capacitor value may be small.


TDA3591A SECAM-PAL transcoder

GENERAL DESCRIPTION
The TDA3591A transcoder circuit converts SECAM input signals into true PAL signals, and can be used in combination
with all types of PAL decoder.
Features
· Limiter input for chrominance signal
· SECAM demodulator
· Clamp circuits and de-emphasis for colour difference
signals
· Modulator to provide true PAL signals
· 4,43 MHz oscillator
· Sandcastle pulse detector
· Identification circuit for horizontal and vertical SECAM
identification
· Can be used with all types of PAL decoder
· Power-saving feature operates when supply voltage
falls to (typ.) 5 V:
SECAM processing shuts down but
SECAM signal path remains active.

PINNING

1. Ground.
2. Limiter feedback.
3. Limiter input: chrominance input SECAM; identification input SECAM/SECAM.
4. Identification selection input using a DC level to preset the identification mode.
At V4< 2,9 V the TDA3591A is preset for frame identification.
At V4 > 4,1 V the TDA3591A is preset for line identification.
5. Storage capacitor input for floating level identification.
6. Storage capacitor input to SECAM/SECAM identification circuit.
7. Double time-constant input to SECAM/SECAM identification circuit.
8. 4,43 MHz oscillator.
9. Sequentially modulated output.
10. Decoupling capacitor for miller integrator feedback circuit.
11. Direct input chrominance signal.
12. Delayed input chrominance signal.
13. PAL/PAL input signal from PAL decoder.
14. Chrominance output signal.
15. Luminance output signal.
16. Luminance/SECAM input signal.
17. Positive supply voltage (Vp).
18. Decoupled positive supply voltage.
19. Three-level sandcastle pulse input.
20. De-emphasis circuit connection: R = 560 W; C = 1 nF.
21. Storage capacitor connection for (R-Y) clamp.
22. Storage capacitor connection for (B-Y) clamp.
23. Demodulator reference tuned circuit: nominal frequency = 4,33 MHz; nominal QL = 2,45.
24. As for pin 23.

FUNCTIONAL DESCRIPTION
Demodulation
The chrominance and identification demodulators of the TDA3591A both share the same reference tuned circuit (pins 23
and 24). The identification circuit automatically detects whether the incoming signal is SECAM or SECAM (NTSC, PAL
or black-and-white).
When the incoming signals are PAL they are diverted via pin 16 to the chrominance output at pin 14 and no signal
demodulation takes place. The delay line connected to pin 16 delays the signals to equalize the delay of the SECAM-PAL
transcoding process. When SECAM signals are received, the PAL signal path is switched off.
Incoming SECAM signals are applied to pin 3 via an external bell filter. The signals are amplified, limited and then
demodulated. Only one demodulator is necessary as the colour difference signals are available sequentially. After
demodulation the colour difference signals are separated by an H/2 switch and then applied to (R-Y) and (B-Y) clamp
circuits where the black levels are clamped to the same DC level. With all conditions at pin 4, artificial black levels are
inserted during the horizontal blanking periods. This is done because of the possibility of horizontal burst signals not
being available. The artificial levels may not be identical to the detected black level due to circuit spread but this can be
corrected by detuning the reference tuned circuit.


The two colour difference signals are combined again after clamping and then applied to the modulator via de-emphasis,
blanking and reinsertion circuits. The ratio of (R-Y) to (B-Y) at the de-emphasis output (pin 20) is 1,78.
Modulation
A burst signal is reinserted into the combined SECAM signal at the input to the PAL modulator. At this input the phase
relationship for magenta colour is +(R-Y) and -(B-Y). The modulation carriers for the (R-Y) and (B-Y) signals are 90° out
of phase; for a magenta colour the modulated (R-Y) component has the same phase position as the (R-Y) burst. The
(B-Y) burst is modulated 180° out of phase with respect to the (B-Y) component of a magenta-coloured input signal.
Identification SECAM/SECAM
Identification of the SECAM signal is performed using the fact that only SECAM signals have a line-to-line difference in
voltage level. The identification circuit compares the phase of the demodulated voltage difference waveform with the
phase of the flip-flop output. If the phase relationship is not correct, the flip-flop is reset by an extra pulse from the flip-flop
trigger generator. For horizontal identification the phase comparison is performed during the period of pulse ‘B’ (see
Fig.2). When vertical identification is selected, the comparison is performed only during the horizontal scan of the vertical
blanking. The SECAM identification circuits operate when selected by the voltage on pin 4; this may be horizontal, vertical
or combined horizontal and vertical identification, depending on the switching arrangements of pin 4.
These are as follows:
· Horizontal identification preset when V4-1 < 2,9 V;
· Vertical identification preset when V4-1 > 4,1 V;
· Horizontal/vertical combination when sandcastle pulse is present on pin 4.
Information obtained from the identification detector is also used for colour killing and, if required, for switching to PAL.

Sandcastle pulse detection
The sandcastle pulse detector requires a three-level sandcastle pulse to provide horizontal blanking, vertical blanking
and burst gate pulses. The detector burst gate pulse triggers a pulse generator which produces two timing pulses, pulse
‘A’ and pulse ‘B’ (see Fig.2). Pulse ‘A’ is used to time the PAL modulator burst and to sample the (R-Y) and (B-Y)
clamping pulse generators. A (R-Y) clamping pulse is generated only during a red line and a (B-Y) clamping pulse only
during a blue line. Pulse ‘B’ times the SECAM horizontal identification.

Carrier generation
The carrier signal for the PAL modulator is obtained from a 4,43 MHz oscillator. An internal Miller integrator operates in
conjunction with the decoupling capacitor at pin 10 to provide the required 90° phase shift.
PAL matrix
The signal output from the PAL modulator at pin 9 is sequentially modulated with (R-Y) burst phased in the +(R-Y)
direction, and (B-Y) burst phased in the -(B-Y) direction. This PAL signal is applied directly to pin 11 and via a 64 ms
delay to pin 12. A true PAL signal is constructed in the PAL matrix by means of an additional/substraction process (in a
correct H/2 sequence) using the delayed and undelayed inputs.

Coupling of identification systems:
Coupling of a TDA3591A and a PAL decoder can be performed to obtain an optimum identification system. The system
operates using the functions of pins 13, 6 and 7: the voltage level at pin 13 is controlled by the PAL/PAL detection of the
PAL decoder; and the voltage level at pins 6 and 7 are functions of SECAM/SECAM detection in the TDA3591A.
The circuit action is as follows and is summarized in Table 1.
Table 1 System operating modes
System priorities
When TDA3591A pin 13 is connected to the PAL/PAL output of a PAL decoder, the system will give PAL priority in signal
identification. Connecting TDA3591A pin 13 to ground will give SECAM priority.
Luminance and chrominance signal paths
The signal input at pin 16 is clamped by a circuit which detects the top of the luminance signal sync pulse. This clamp,
the luminance signal path to pin 15 and the SECAM signal path to pin 14 remain active when the supply voltage falls to
(typ.) 5 V. At this level of supply voltage the SECAM processing circuits are switched off, giving a reduction in total power
dissipation.
Channel switching During channel switching pin 6 is taken rapidly to a high voltage (± 10,2 V), this corresponds
to the SECAM mode of the TDA3591A.
PAL The high voltage level at pin 6 caused by channel switching is maintained by the TDA3591A
when it recognizes the signal as SECAM (this condition is maintained even if reflected PAL
signals are present). The PAL decoder recognizes the signal as PAL and takes pin 13 of
TDA3591A to a voltage greater than 1,7 V. The TDA3591A is now held in the SECAM
condition by an internal current source at pin 6.
SECAM The initial high voltage level (+ 10,2 V) at pin 6 caused by channel switching sets the
TDA3591A in the SECAM mode and during this time the PAL decoder detects a PAL signal.
This causes a voltage at pin 13 of < 1,1 V which prevents the internal current source of
TDA3591A maintaining the high voltage level of pin 6 which, in turn, allows the TDA3591A to
detect SECAM. The initiation of SECAM detection is delayed by the action of the external
circuit at pins 6 and 7 and commences as pin 6 approaches 7,0 V. The SECAM signals are
converted by TDA3591A to PAL signals at pin 14, which results in the PAL decoder switching
to the PAL mode (the TDA3591A remains in the SECAM mode).
Black-and-white The TDA3591A is initially set in the SECAM mode as previously described. The PAL decoder
detects PAL and the TDA3591A detects SECAM which results in a system operation in the colour-killing mode.



SAB3034 COMPUTER INTERFACE FOR TUNING AND CONTROL (CITAC)

GENERAL DESCRIPTION
The SAB3034 provides closed-loop digital tuning of TV receivers, with or without a.f.c., as required. lt
also controls up to 8 analogue functions, 4 general purpose I/O ports and 4 high-current outputs for
tuner band selection.
The IC is used in conjunction with a microcomputer from the MAB84OO family and is controlled via a two-wire, bidirectional I2 C bus.
Featu res
Combined analogue and digital circuitry minimizes the number of additional interfacing components
required
Frequency measurement with resolution of 50 KHz
Selectable prescaler divisor of 64 or 256
32 V tuning voltage amplifier
4 high-current outputs for direct band selection
8 static digital to analogue converters (DACSI for control of analogue functions
Four general purpose input/output (l/O) ports
Tuning with control of speed and direction
Tuning with or without a.f.c.
Single-pin, 4 MHZ on-chip oscillator
I2 C bus slave transceiver

FUNCTIONAL DESCRIPTION
The SAB3034 is a monolithic computer interface which provides tuning and control functions and
operates in conjunction with a microcomputer via an I2 C bus.
Tuning
This is performed using frequency-locked loop digital control. Data corresponding to the required tuner
frequency is stored in a 15-bit frequency buffer. The actual tuner frequency, divided by a factor of 256
(or by 64) by a prescaler, is applied via a gate to a 15-bit frequency counter. This input (FDIV) is
measured over a period controlled by a time reference counter and is compared with the contents of the frequency buffer. The result of the comparison is used to control the tuning voltage so that the tuner frequency equals the contents of the frequency buffer multiplied by 50 kHz within a programmable tuning window (TUW).

The system cycles over a period of 6,4 ms (or 2,56 ms), controlled by the time reference counter which is clocked by an on-chip 4 lVlHz reference oscillator. Regulation of the tuning voltage is performed by a charge pump frequency-locked loop system. The charge IT flowing into the tuning voltage amplifier is controlled by the tuning counter, 3-bit DAC and the charge pump circuit. The charge IT is linear with the frequency deviation Af in steps of 50



TDA2545A Quasi-split-sound circuit
GENERAL DESCRIPTION The TDA2545A is a monolithic integrated circuit for quasi-split-sound processing in television receivers. Features · 3-stage gain controlled i.f. amplifier · A.G.C. circuit · Reference amplifier and limiter amplifier for vision carrier (V.C.) processing · Linear multiplier for quadrature demodulation.

D8049AH 8-Bit Microcontroller-Microcomputer - Over 96 instructions, all 1-2 cycles

Intel
8-Bit Microcontrollers
Clock Frequency - Max. (Hz)=11.0M
Clock Frequency - Min. (Hz)=1.0M
Min Instruction Length (bits)=8
Max Instruction Length (bits)=16
Memory Addressing Range=64k
Number of Addressing Modes=5
On-Chip RAM (Bytes)=128
On-Chip ROM (bytes)=2k
Number of Interrupt Lines=1
No. of Non-Maskable Interrupts=0
Number of Maskable Interrupts=1
Number of I/O Lines=16
No. of I/O Ports=2
Vsup Nom.(V) Supply Voltage=5.0
Package=DIP
Pins=40
Military=N
Technology=NMOS



ER1400 M5G1400 1400 BIT ELECTRICALLY ALTERABLE ROM (MITSUBISHI)


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The RC-5 infrared remote protocol was developed by Philips in the late 1980s as a semi-proprietary consumer IR (infrared) remote control communication protocol for consumer electronics. However, it was also adopted by most European manufacturers, as well as many US manufacturers of specialty audio and video equipment.

The advantage of the RC-5 protocol is that (when properly followed) any CD handset (for example) may be used to control any brand of CD player using the RC-5 protocol.

Protocol Details

The basics of the protocol are well known. The handset contains a keypad and a transmitter integrated circuit (IC) driving an IR LED. The command data is a bi-phase encoded bitstream modulating a 36 kHz carrier. (Often the carrier used is 38 kHz or 40 kHz, apparently due to misinformation about the actual protocol.) The IR signal from the transmitter is detected by a specialized IC with an integral photo-diode, and is amplified, filtered, and demodulated so that the receiving device can act upon the received command. RC-5 only provides a one-way link, with information traveling from the handset to the receiving unit.
The command comprises 14 bits:

• A start bit, which is always logic 1 and allows the receiving IC to set the proper gain.
• A field bit, which denotes whether the command sent is in the lower field (logic 1 = 0 to 63 decimal) or the upper field (logic 0 = 64 to 127 decimal). The field bit was added later by Philips when it was realized that 64 commands per device were insufficient. Previously, the field bit was combined with the start bit. Many devices still use this original system.
• A control bit, which toggles with each button press. This allows the receiving device to distinguish between two successive button presses (such as "1", "1" for "11") as opposed to the user simply holding down the button and the repeating commands being interrupted by a person walking by, for example.
• A five-bit system address, that selects one of 32 possible systems.
• A six-bit command, that (in conjunction with the field bit) represents one of the 128 possible RC-5 commands.

The 36 kHz carrier frequency was chosen to render the system immune to interference from TV scan lines. Since the repetition of the 36 kHz carrier is 27.778 μs and the duty factor is 25%, the carrier pulse duration is 6.944 μs. Since the high half of each symbol (bit) of the RC-5 code word contains 32 carrier pulses, the symbol period is 64 x 27.778 μs = 1.778 ms, and the 14 symbols (bits) of a complete RC-5 code word takes 24.889 ms to transmit. The code word is repeated every 113.778 ms (4096 / 36 kHz) as long as a key remains pressed. (Again, please note that these timings are not strictly followed by all manufacturers, due to a lack of widespread distribution of accurate information on the RC-5 protocol.)

System and Command Codes

While the RC-5 protocol is well known and understood, what is not so well documented are the system number allocations and the actual RC-5 commands used for each system. The information provided below is the most complete and accurate information available at this time. It is from a printed document from Philips dated December 1992 that is unfortunately not available in electronic format (e.g., PDF), nor is an updated version available. This information is provided so that companies that wish to use the RC-5 protocol can use it properly, and avoid conflicts with other equipment that may or may not be using the correct system numbers and commands.

This code has an instruction set of 2048 different instructions and is divided into 32 address
of each 64 instructions. Every kind of equipment use his own address,
so this makes it possible to change the volume of the TV without change the volume of the hifi.
The transmitted code is a dataword wich consists of 14 bits and is defined as:


2 startbits for the automatic gain control in the infrared receiver.
1 toggle bit (change everytime when a new button is pressed on the ir transmitter)
5 address bits for the systemaddress
6 instructionbits for the pressed key.













The Philips RC5 IR transmission protocol uses Manchester encoding of the message bits. Each pulse burst (mark – RC transmitter ON) is 889us in length, at a carrier frequency of 36kHz (27.7us). Logical bits are transmitted as follows:

• Logical '0' – an 889us pulse burst followed by an 889us space, with a total transmit time of 1.778ms

• Logical '1' – an 889us space followed by an 889us pulse burst, with a total transmit time of 1.778ms

The pulse/pause ratio of the 36kHz carrier frequency is 1/3 or 1/4, which reduces power consumption.

When a key is pressed on the remote controller, the message frame transmitted consists of the following 14 bits, in order:

• two Start bits (S1 and S2), both logical '1'.

• a Toggle bit (T). This bit is inverted each time a key is released and pressed again.

• the 5-bit address for the receiving device

• the 6-bit command.

The address and command bits are each sent most significant bit first. Figure 1 illustrates the format of a Philips RC5 IR transmission frame, for an address of 05h (00101b) and a command of 35h (110101b).



Figure 1. Example message frame using the Philips RC5 IR transmission protocol.
From Figure 1 we can see that it takes:

• 5.334ms to transmit the Start and Toggle bits (S1, S2 and T). Notice that, as the first half-bit of S1 is a space, the receiver will only notice the real start of the message frame after 889us.

• 8.89ms to transmit the 5 bits for the address

• 10.668ms to transmit the 6 bits for the command

• 24.892ms to fully transmit the actual message frame.

The Toggle bit (T) is used by the receiver to distinguish weather the key has been pressed repeatedly, or weather it is being held depressed. As long as the key on the remote controller is kept depressed, the message frame will be repeated every 114ms. The Toggle bit will retain the same logic level during all of these repeated message frames. It is up to the receiver software to interpret this auto-repeat feature of the protocol.