Digital Board B, Video Signal Processing
The entire video signal processing function for PAL and
SECAM, the videotext decoder and the deflection signal
generator, are located together on one board, the Digital
Board B-
This contains the VCU 2133 as an analog-digital converter for
the video signals, the PVPU 2203 and SPU 2220 for PAL and
SECAM signal processing respectively, the DTI 2222 for
improved reproduction of colour transitions, the TPU 2732 with
page buffer IC 645 for videotext decoding, the deflection
processor DPU 2543 and clock pulse generator MCU 2600 for
generating the working clock pulse for all processors.
Digital Board B has 2 separate inputs for video signals. The
internal FBAS (composite colour) signal is fed from the RF
module via plug connector DV 4 to impedance converter T 660,
and further from the emitter ofT 660 to Pin 35 of VCU 2133, IC
650. If a video signal is fed in at the SCART socket, this
passes
through DV 7 and T 680 as an impedance converter to Pin 37 of
the VCU. To clamp the porch levels each to 5.5 V, the DPU
delivers specially generated clamping pulses from its Pins 21
and 4 to input Pins 35 and 37 of the VCU. Switch-over to the
desired signal source is performed inside the VCU, and is
controlled via the IM Bus.
After conversion of the FBAS (composite colour) signal selected
into digital form (7-bit gray code), this is passed from output
Pins 2-8 ofthe VCU to SPU 2220, IC 630, to TPU 2732, IC 640
and to DPU 2540.
The further path of the video signal leads first to the SECAM
processor SPU 2220. Here the signal standard is identified and
appropriately switched. In the case of a PAL signal, the input
information is passed unaltered to the video output (Pins 14-20),
and thus on to the input of PVPU 2203, Pins 5-11.
For further processing of the PAL signal, it is first split inside the
IC into luminance and chroma components. The conditioned
luminance signal, extended by 1 bit, appears on the output side
at Pins 32-39, and passes from here to DTI 2222, Pins 6-13.
The chroma signal component is demodulated, decoded and
converted into the colour difference signals in PVPU 2203;
these signals are then also passed (in multiplex mode, together
with picture tube beam current measured data), via output Pins
27-30 to DTI 2222, Pins 17-20.
At this point, the SECAM chroma signal path from SPU 2220,
output Pins 23-26, rejoins the main path. If the input signal is
identified as a SECAM signal in the SPU, the SECAM decoder
is activated, and the decoded signal appears at the output in the
same form as with the PAL processor.
In this case, the luminance signal component is passed through
an integrated delay circuit of 3.7 us, in order to compensate for
the corresponding travel time in the SECAM colour decoder,
and is then fed on the same path as the PAL signal (Pins 14-20,
SPU 2220, PVPU 2203) to DTI 2222, Pins 6-13. All adjustment
functions required for the signals, such as contrast, brightness,
colour intensity, etc. are of course controlled inside the IC via
the IM Bus.
Integrated circuit DTI 2222 serves solely to improve
reproduction of colour transitions on the screen. Since (owing to
the smaller transmission bandwidth with chroma) the signal
leading edges are very flat compared with Y-signals, a clear
improvement in the quality of colour reproduction can be
achieved by electronically increasing the steepness of the
edges. Since the signal manipulation involved increases travel
times in the chroma channel, this must be compensated by a
corresponding delay in the luminance channel. This function is
contained in DTI 2222, so that there are no differences in travel
time at the outputs of this circuit (Pins 27-34 for Y and Pins 22-25 for chroma).
Chassis DIGI B-E 110° FST. Modular Parts.
Digital Video Processing Modul:
Digiboard B/2T MULTIContains DIGIT2000 Digital Video Processing ChipSet.
VCU 2133 A (ITT VCU2133 A) (Video Codec Decodec Unit)
DPU 2543 (ITT DPU2543) (Digital Deflection Processor Unit)
PVPU 2203 (ITT PVPU2203) (PAL and Video Processor Unit)
DTI 2222 (ITT DTI2222) (Digital Transient Improvement [Chroma])
TPU 2732 (ITT TPU2732) (Teletext Processor Unit)
MCU 2600 (ITT MCU2600) (Main Clock Unit)
ITT DIGIVISION CHIPSET FUNCTIONS.
DIGITAL CRT TUBE Cathode RAY CURRENT CONTROL / Cut OFF / Drive and processing.
In this IC set, the dark currents and the white levels of the three electron guns, the leakage currents of the cathodes, and a light-detector current are measured during four successive vertical blanking intervals. The cathode leakage currents and the dark currents are measured in the first half of the vertical blanking interval, and the light-detector current and the white level currents are measured at the end of this interval. From these measured data and alignment data stored in a reprogrammable memory (ps), a microprocessor (mp) contained together with the memory (ps) in an integrated circuit (ic2) derives operating data for the picture tube (b) as well as further data. These operating data are transferred over a wire of a chroma bus (cb), over which chroma signals are transferred during the vertical sweep, into a shift register (sr) of a further integrated circuit (ic3) at the beginning of each vertical blanking interval, from where they are passed on to the picture tube (b) in groups via digital-to-analog converters and analog amplifiers. By the use of the chroma bus for a dual purpose, and the successive measurements of the above-mentioned picture-tube data, a saving of external terminals of the integrated circuits (ic1, ic2, ic3) is achieved.1. Set of three integrated circuits(ic1, ic2, ic3) for digital video-signal processing in color-television receivers,
wherein the first integrated circuit (ic1) contains an analog-to-digital converter (ad) followed by a first bus interface circuit (if1) for a serial data bus (sb), and a first multiplexer (mx1) following the first bus interface circuit (if1), the analog-to-digital converter (ad) being fed with measured data corresponding to the cathode currents of the picture tube (b) flowing at "black" (="dark current") and "white" (="white level") in each of the three electron guns, and with the signal of an ambient-light detector (ls) via a second multiplexer (mx) in the vertical blanking interval, and the first multiplexer (mx1) being fed with the processed digital chrominance signals (cs),
wherein the second integrated circuit (ic2) contains a microprocessor (mp), an electrically reprogrammable memory (ps), and a second serial-data-bus interface circuit (if2) corresponding to the first bus interface circuit (if1), the memory (ps) holding alignment data and nominal dark-current/white-level data of the picture tube used (b) which were entered by the manufacturer of the color-television receiver and, together with the measured data, are used by the microprocessor (mp) to generate video-signal-independent operating data for the picture tube (b), and wherein the third integrated circuit (ic3) contains a demultiplexer (dx), an analog RGB matrix (m), and three analog amplifiers (vr, vg, vb) each designed to drive one of the electron guns via an external video output stage (ve), the dark current of the picture tube (b) being adjusted via the operating point of the respective analog amplifier, and the white level of the picture tube (b) being adjusted by adjusting the gain of the respective amplifier after digital-to-analog conversion, and with the demultiplexer (dx) connected to the first multiplexer (mx1)of the first integrated circuit (ic1) via a chroma bus (cb),
Characterized by the Following Features:
The first multiplexer (mx1) consists of three electronic switches (s1, s2, s3),
the first of which (s1) has its input grounded through a first resistor (r1) and connected to the collectors of external transistors (tr, tg, tb) which are each associated with one of the electron guns and the base of each of which is driven by the associated video output stage, while the emitter is connected to the associated electron gun system, and the output of the first switch (s1) is connected to the input of the analog-to-digital converter (ad);
the second of which (s2) has its input connected to the light detector (ls), while its output is coupled with the input of the analog-to-digital converter (ad), and
the third of which (s3) has its input connected to the input of the first electronic switch (s1) via a second resistor (r2), and its output is grounded, the value of the second resistor (r2) being about one order of magnitude smaller than that of the first resistor (r1);
the three electronic switches (s1, s2, s3) have the following positions:
| ______________________________________ |
| s1 s2 s3 |
| ______________________________________ |
during vertical closed open closed sweep during vertical closed/open open/closed open/closed retrace: for leakage/light- det. current meas. for white level closed open closed measurement for dark current closed open open measurement |
| ______________________________________ |
to this end, the cathodes are connected at one end to a voltage for blacker than black (us), and at the other end to a voltage for black (ud) and then to a voltage for white (uw) in accordance with the following table:
| ______________________________________ |
| Measurement in the first at about the Vertical half of the end of the blanking vertical vertical interval blanking blanking Cathode No. interval interval red green blue |
| ______________________________________ |
1 Leakage cur- Light-detect- us us us rents of the or current cathodes 2 Dark current White level ud/uw us us red red 3 Dark current White level us ud/uw us green green 4 Dark current White level us us ud/uw blue blue |
| ______________________________________ |
the measured data are transferred from the analog-to-digital converter (ad) to the microprocessor (mp) of the second integrated circuit (ic2) via the two interface circuits (if1, if2) and the data bus (sb) at an appropriate instant, and the video-signal-independent operating data for the picture tube (b), which are generated by the microprocessor (mp), are transferred from the second integrated circuit (ic2) via the two interface circuits (if1, if2) and a line (db) to the first multiplexer (mx1) of the first integrated circuit (ic1) at an appropriate instant, and from there over a wire of the chroma bus (cb) into a shift register (sr) of the third integrated circuit (ic3) shortly after the beginning of the next vertical blanking interval, the parallel outputs of which shift register (sr) are combined in groups each assigned to one type of operating value, and each of the groups is connected to one digital-to-analog converter (dh, ddr, ddg, ddd, dwr, dwg, dwb) which drives the RGB matrix (m) or the respective analog amplifier (vr, vg, vb).
. 2. An integrate
d-circuit set as claimed in claim 1, characterized in that the voltage for blacker than black (us) is applied to the cathodes of the picture tube (b) during the data transfer to the shift register (sr). 3. An integrated-circuit set as claimed in claim 2, characterized in that the microprocessor (mp) determines the appropriate instant for the measured-data transfer, and that, if a measurement has not yet been finished at that instant, the measured data of the corresponding earlier measurement are transferred. 4. An integrated-circuit set as claimed in claim 3, characterized in that the measurement performed in a vertical blanking interval is not enabled until the data of the preceding measurement have been transferred to the microprocessor (mp). 5. An integrated-circuit set as claimed in claim 2, characterized in that the measurement performed in a vertical blanking interval is not enabled until the data of the preceding measurement have been transferred to the microprocessor (mp). 6. An integrated-circuit set as claimed in claim 1, characterized in that the microprocessor (mp) determines the appropriate instant for the measured-data transfer, and that, if a measurement has not yet been finished at that instant, the measured data of the corresponding earlier measurement are transferred. 7. An integrated-circuit set as claimed in claim 6, characterized in that the measurement performed in a vertical blanking interval is not enabled until the data of the preceding measurement have been transferred to the microprocessor (mp). 8. An integrated-circuit set as claimed in claim 1, characterized in that the measurement performed in a vertical blanking interval is not enabled until the data of the preceding measurement have been transferred to the microprocessor (mp).
Description:
The present invention relates to a set of three integrated circuits for digital video signal processing in color-television receivers as is set forth in the preamble of claim 1. An IC set of this kind is described in a publication by INTERMETALL entitled "Eine neue Dimension-VLSI-Digital-TV-System", Freiburg im Breisgau, September 1981, on pages 6 to 11 (see also the corresponding English edition entitled "A new dimension-VLSI Digital TV System", also dated September 1981).
The first integrated circuit, designated in the above-mentioned publications by "MAA 2200" and called "Video Processor Unit" (VPU), includes an analog-to-digital converter followed by a first serial-data-bus interface circuit which, in turn, is followed by a first multiplexer. During the vertical blanking interval, the analog-to-digital converter is fed, via a second multiplexer, with measured data corresponding to the cathode currents of the picture tube flowing at "black" (="dark current") and "white" ("white level") in each of the three electron guns, and with the signal of an ambient-light detector. The processed digital chrominance signals are applied to the first multiplexer.
The second integrated circuit, designated by "MAA 2000" and called "central control unit" (CCU) in the above publications, contains a microprocessor, an electrically reprogrammable memory, and a second serial-data-bus interface circuit. The memory holds alignment data and nominal dark-current/white-level data entered by the manufacturer of the color-television receiver. From these data and the measured data, the microprocessor derives video-signal-independent operating data for the picture tube.
The third integrated circuit, designated by "MAA 2100" and called "video-codec unit" (VCU) in the above publications, includes a demultiplexer, an analog RGB matrix, and three analog amplifiers each designed to drive one of the electron guns via an external video output stage. After digital-to-analog conversion, the dark current of the picture tube is adjusted via the operating point of the respective analog amplifier, and the white level of the picture tube is adjusted by adjusting the gain of the respective analog amplifier. The demultiplexer is connected to the first multiplexer of the first integrated circuit via a chroma bus.
As to the prior art concerning such digital color-television receiver systems, reference is also made to the journal "Elektronik", Aug. 14, 1981 (No. 16), pages 27 to 35, and the journal "Electronics", Aug. 11, 1981, pages 97 to 103.
During the further development of the prior art system following the above-mentioned publication dates, the developers were faced with the problem of how to accomplish the dark-current/white-level control of the picture tube within the existing system, particularly with respect to measured-data acquisition and transfer and to the transfer of the operating data to the picture tube.
Another requirement imposed during the further development of the prior art system was that the leakage currents of the electron guns of the picture tube be measured and processed within the existing system. The solution of these problems is to take into account the requirement that the number of external terminals of the individual integrated circuits be kept to a minimum.
The object of the invention as claimed is to solve the problems pointed out. The essential principles of the solution, which directly give the advantages of the invention, are, on the one hand, the division of the measurement to four successive vertical blanking intervals and, on the other hand, the utilization of one wire of the chroma bus at the beginning of the next vertical blanking interval as well as the measurement of the ambient light by means of the light detector and the measurement of the leakage currents during a single vertical blanking interval.
The invention will now be explained in more detail with reference to the accompanying drawing, which is a block diagram of one embodiment of the IC set in accordance with the invention. It shows the first, second, and third integrated circuits ic1, ic2, and ic3, which are drawn as rectangles bordered by heavy lines. The first integrated circuit ic1 includes the analog-to-digital converter ad, which converts the measured dark-current, white-level, ambient-light, and leakage-current data into digital signals, which are fed to the first bus interface circuit if1. The latter is connected via the line db to the first multiplexer mx1, which interleaves data from the first bus interface circuit if1 with digital chrominance signals cs produced in the first integrated circuit ic1, and places the interleaved signals on the chroma bus cb. The generation of the digital chrominance signals cs is outside the scope of the present invention and is disclosed in the references cited above.
The first integrated circuit ic1 further includes the second multiplexer mx2, which consists of the three electronic switches s1, s2, s3, and represents a subcircuit which is essential for the invention. The input of the first switch s1 is grounded through the first resistor r1, and connected to the collectors of the external transistors tr, tg, tb, each of which is associated with one of the electron guns. Via the base-emitter paths of these transistors, the cathodes of the three electron guns are driven by the video output stages ve. The final letters r, g, and b in the reference characters tr, tg, and tb and in the reference characters explained later indicate the assignment to the electron gun for RED (r), GREEN (g), and BLUE (b), respectively. The output of the first switch s1 is connected to the input of the analog-to-digital converter ad.
The input of the second switch s2 is connected to the light detector ls, which has its other terminal connected to a fixed voltage u and combines with the grounded resistor r3 to form a voltage divider. The input of the second switch s2 is thus connected to the tap of this voltage divider, while the output of this switch, too, is coupled to the input of the analog-to-digital converter ad.
The input of the third switch s3 is connected to the input of the first switch s1 via the second resistor r2, while the output of the third switch s3 is grounded. The value of the resistor r1 is about one order of magnitude greater than that of the resistor r2.
For the whole duration of the picture shown on the screen of the picture tube b, and throughout the vertical sweep, the first switch s1 and the third switch s3 are closed, and the second switch s2 is open. During the vertical retrace interval, for the white-level measurement, the switches s1, s3 are closed, and the switch s2 is open; for the dark-current measurement and the leakage-current measurement, the switch s1 is closed, and the switches s2, s3 are open, and for the light-detector-current measurement, the switches s2, s3 are closed, and the switch s1 is open.
The measurements of the dark current and the white level of each electron gun and the measurements of the light-detector current and the leakage currents are made in four successive vertical blanking intervals. One end of the respective cathode is connected to a voltage us for blacker-than-black, and the other end is connected to a voltage ud for black and then to a voltage uw for white, in accordance with the following table:
The voltage ud for black is, as usual, a voltage which just causes no brightness on the screen of the picture tube b, i.e., a voltage just below the dark threshold of the picture tube. The voltage us for blacker-than-block is then a cathode voltage lying further in the black direction than the voltage for black. The voltage for white is the voltage for the screen brightness to be measured; the brightness of the screen is generally below the maximum permissible value.
Thus, two measurements are made during each vertical blanking interval, namely one in the first half, preferably at one-third of the pulse duration of the vertical blanking interval, and the other at about the end of the first half. During the four successive vertical blanking intervals, the first measurement determines the leakage currents of the cathodes and the dark currents for red, green, and blue. The second measurements determine the light-detector current and the white levels for red, green, and blue. During the measurement of the cathode leakage currents and the light-detector current, all three cathodes are at the voltage us. During the measurements of the dark current and the white level of the respective cathode, the latter is connected to the respective dark-current cathode voltage ud and white-level cathode voltage uw, respectively, while the cathodes of the two other electron guns, which are not being measured, are at the voltage us.
The second integrated circuit circuit ic2 contains the microprocessor mp, the electrically reprogrammable memory ps, and the second bus interface circuit if2, which is associated with the serial data bus sb in this integrated circuit and also connects the microprocessor mp and the memory ps with one another and with itself. The memory ps holds alignment data and nominal dark-current/white-value data of the picture tube used, which were entered by the manufacturer. From this alignment and nominal data and from the measured data obtained via the second multiplexer mx2 and the analog-to-digital converter ad of the first integrated circuit ic1, the microprocessor mp derives video-signal-independent operating data for the picture tube.
The derivation of these operating data is also outside the scope of the invention; it should only be mentioned that with respect to the operating data of the picture tube, the microprocessor performs a control function in accordance with a predetermined control characteristic.
The third integrated circuit ic3 includes the demultiplexer dx, which is connected to the first multiplexer mx1 of the first integrated circuit ic1 via the chroma bus cb and separates the chrominance signals cs and the operating data of the picture tube from the interleaved signals transferred over the chroma bus. While the transfer of measured data from the analog-to-digital converter ad to the microprocessor mp of the second integrated circuit ic2 takes place via the two interface circuits if1, if2 and the data bus sb at an appropriate instant, the video-signal-independent operating data for the picture tube b, which are derived by the microprocessor mp, are transferred from the second integrated circuit ic2 via the two interface circuits if1, if2 and the line db to the first multiplexer mx1 at an appropriate instant, and from the first multiplexer mx1 over a wire of the chroma bus cb into the shift register sr of the third integrated circuit ic3 shortly after the beginning of the next vertical blanking interval. To accomplish this, the first interface circuit if1 also includes a shift register from which the operating data are read serially.
During this data transfer into the shift register sr, the cathodes of the picture tube b are preferably at the voltage us in order that this data transfer does not become visible on the screen.
The appropriate instant for the transfer of measured data to the microprocessor mp is determined by the latter itself, i.e., depending on the program being executed in the microprocessor, and on the time needed therefor, the measured data are called for from the interface circuits not at the time of measurement but at a selectable instant within the working program of the microprocessor mp. If the measurement currently being performed should not yet be finished at the instant at which the measured data are called for, in a preferred embodiment of the invention, the stored data of the previous measurement will be transferred to the microprocessor mp.
As mentioned previously, the operating data for the picture tube b are transferred into the shift register sr at the beginning of a vertical blanking interval. The parallel outputs of this shift register are combined in groups each assigned to one operating value, and each group has one of the digital-to-analog converters dh, ddr, ddg, ddb, dwr, dwg, dwb associated with it. In the figure, the division of the shift register into groups is indicated by broken lines. The shift register sr performs a serial-to-parallel conversion in the usual manner, and the operating data are entered by the demultiplexer dx into the shift register in serial form and are then available at the parallel outputs of the shift register.
The digital-to-analog converter dh provides the analog brightness control signal, which is applied to the RGB matrix m in the integrated circuit ic3. Also applied to the RGB matrix m are the analog color-difference signals r-y, b-y and the luminance signal y. The formation of these signals is outside the scope of the invention and is known per se from the publications cited at the beginning.
The three analog-to-digital converters ddr, ddg, ddb provide the dark-current-adjusting signals for the three cathodes, which are currents and are applied to the inverting inputs--of the analog amplifiers vr, vg, vb. Also connected to these inputs is a resistor network which is adjustable in steps in response to the digitalwhite-level-adjusting signals at the respective group outputs of the shift register sr. The resistors serve as digital-to-analog converters dwr, dwg, dwb and establish the connection between the inverting inputs--and the outputs of the analog amplifiers vr, vg, vb.
In an arrangement according to the invention which has proved good in practice, each of the three dark-current-adjusting signals is a seven-digit signal, and each of the three white-level-adjusting signals and the brightness control signal are five-digit signals. The voltages us and ud/uw of the three cathodes are assigned a three-digit identification signal in accordance with the above table, which signal is also fed into the shift register sr in the implemented circuit. Finally, a three-digit contrast control signal is provided in the implemented circuit for the Teletext mode of the color-television receiver. These nine data blocks are transferred in the implemented circuit from the demultiplexer dx to the shift register sr in the following order, with the least significant bit transmitted first, and with the specified number of blanks: identification signal, white-level signal blue, three blanks, white-level signal green, three blanks, white-level signal red, one blank, dark-current signal blue, one blank, dark-current signal green, one blank, dark-current signal red, contrast signal Teletext, and brightness control signal. These are seven eight-digit data blocks which are assigned to 56 pulses of a 4.4-MHz clock frequency, which is the frequency of the shift clock signal of the shift register sr.
It should be noted that the data sequence just described does not correspond to the order of the groups of the shift register sr in the figure. The order in the figure was chosen only for the sake of clarity.
The outputs of the three analog amplifiers vr, vg, vb are coupled to the inputs of the video output stage ve, whose outputs, as explained previously, are connected to the bases of the transistors pr, tg, td, so that the cathodes of the picture tube b are driven via the base-emitter paths of these transistors.
In another preferred embodiment of the invention, the measurement performed during a vertical blanking interval is not enabled until the data of the previous measurement has been transferred into the microprocessor mp. In this manner, no measurement will be left out.
It is also possible to omit the digital-to-analog converter dh if the analog RGB matrix m is replaced with a digital one.
One advantage of the invention is that the use of the chroma bus for the transfer of operating data facilitates the implementation of the third integrated circuit ic3 using bipolar technology, because an additional bus interface circuit, which could be used there, would occupy too much chip area.
The first integrated circuit, designated in the above-mentioned publications by "MAA 2200" and called "Video Processor Unit" (VPU), includes an analog-to-digital converter followed by a first serial-data-bus interface circuit which, in turn, is followed by a first multiplexer. During the vertical blanking interval, the analog-to-digital converter is fed, via a second multiplexer, with measured data corresponding to the cathode currents of the picture tube flowing at "black" (="dark current") and "white" ("white level") in each of the three electron guns, and with the signal of an ambient-light detector. The processed digital chrominance signals are applied to the first multiplexer. The second integrated circuit, designated by "MAA 2000" and called "central control unit" (CCU) in the above publications, contains a microprocessor, an electrically reprogrammable memory, and a second serial-data-bus interface circuit. The memory holds alignment data and nominal dark-current/white-level data entered by the manufacturer of the color-television receiver. From these data and the measured data, the microprocessor derives video-signal-independent operating data for the picture tube.
The third integrated circuit, designated by "MAA 2100" and called "video-codec unit" (VCU) in the above publications, includes a demultiplexer, an analog RGB matrix, and three analog amplifiers each designed to drive one of the electron guns via an external video output stage. After digital-to-analog conversion, the dark current of the picture tube is adjusted via the operating point of the respective analog amplifier, and the white level of the picture tube is adjusted by adjusting the gain of the respective analog amplifier. The demultiplexer is connected to the first multiplexer of the first integrated circuit via a chroma bus. As to the prior art concerning such digital color-television receiver systems, reference is also made to the journal "Elektronik", Aug. 14, 1981 (No. 16), pages 27 to 35, and the journal "Electronics", Aug. 11, 1981, pages 97 to 103.
During the further development of the prior art system following the above-mentioned publication dates, the developers were faced with the problem of how to accomplish the dark-current/white-level control of the picture tube within the existing system, particularly with respect to measured-data acquisition and transfer and to the transfer of the operating data to the picture tube.
Another requirement imposed during the further development of the prior art system was that the leakage currents of the electron guns of the picture tube be measured and processed within the existing system. The solution of these problems is to take into account the requirement that the number of external terminals of the individual integrated circuits be kept to a minimum.
The object of the invention as claimed is to solve the problems pointed out. The essential principles of the solution, which directly give the advantages of the invention, are, on the one hand, the division of the measurement to four successive vertical blanking intervals and, on the other hand, the utilization of one wire of the chroma bus at the beginning of the next vertical blanking interval as well as the measurement of the ambient light by means of the light detector and the measurement of the leakage currents during a single vertical blanking interval.
The invention will now be explained in more detail with reference to the accompanying drawing, which is a block diagram of one embodiment of the IC set in accordance with the invention. It shows the first, second, and third integrated circuits ic1, ic2, and ic3, which are drawn as rectangles bordered by heavy lines. The first integrated circuit ic1 includes the analog-to-digital converter ad, which converts the measured dark-current, white-level, ambient-light, and leakage-current data into digital signals, which are fed to the first bus interface circuit if1. The latter is connected via the line db to the first multiplexer mx1, which interleaves data from the first bus interface circuit if1 with digital chrominance signals cs produced in the first integrated circuit ic1, and places the interleaved signals on the chroma bus cb. The generation of the digital chrominance signals cs is outside the scope of the present invention and is disclosed in the references cited above.
The first integrated circuit ic1 further includes the second multiplexer mx2, which consists of the three electronic switches s1, s2, s3, and represents a subcircuit which is essential for the invention. The input of the first switch s1 is grounded through the first resistor r1, and connected to the collectors of the external transistors tr, tg, tb, each of which is associated with one of the electron guns. Via the base-emitter paths of these transistors, the cathodes of the three electron guns are driven by the video output stages ve. The final letters r, g, and b in the reference characters tr, tg, and tb and in the reference characters explained later indicate the assignment to the electron gun for RED (r), GREEN (g), and BLUE (b), respectively. The output of the first switch s1 is connected to the input of the analog-to-digital converter ad.
The input of the second switch s2 is connected to the light detector ls, which has its other terminal connected to a fixed voltage u and combines with the grounded resistor r3 to form a voltage divider. The input of the second switch s2 is thus connected to the tap of this voltage divider, while the output of this switch, too, is coupled to the input of the analog-to-digital converter ad.
The input of the third switch s3 is connected to the input of the first switch s1 via the second resistor r2, while the output of the third switch s3 is grounded. The value of the resistor r1 is about one order of magnitude greater than that of the resistor r2.
For the whole duration of the picture shown on the screen of the picture tube b, and throughout the vertical sweep, the first switch s1 and the third switch s3 are closed, and the second switch s2 is open. During the vertical retrace interval, for the white-level measurement, the switches s1, s3 are closed, and the switch s2 is open; for the dark-current measurement and the leakage-current measurement, the switch s1 is closed, and the switches s2, s3 are open, and for the light-detector-current measurement, the switches s2, s3 are closed, and the switch s1 is open. The measurements of the dark current and the white level of each electron gun and the measurements of the light-detector current and the leakage currents are made in four successive vertical blanking intervals. One end of the respective cathode is connected to a voltage us for blacker-than-black, and the other end is connected to a voltage ud for black and then to a voltage uw for white, in accordance with the following table:
| ______________________________________ |
| Measurement in the first at about the Vertical half of the end of the blanking vertical vertical interval blanking blanking Cathode No. interval interval red green blue |
| ______________________________________ |
1 Leakage cur- Light-detect- us us us rents of the or current cathodes 2 Dark current White level ud/uw us us red red 3 Dark current White level us ud/uw us green green 4 Dark current White level us us ud/uw blue blue |
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Thus, two measurements are made during each vertical blanking interval, namely one in the first half, preferably at one-third of the pulse duration of the vertical blanking interval, and the other at about the end of the first half. During the four successive vertical blanking intervals, the first measurement determines the leakage currents of the cathodes and the dark currents for red, green, and blue. The second measurements determine the light-detector current and the white levels for red, green, and blue. During the measurement of the cathode leakage currents and the light-detector current, all three cathodes are at the voltage us. During the measurements of the dark current and the white level of the respective cathode, the latter is connected to the respective dark-current cathode voltage ud and white-level cathode voltage uw, respectively, while the cathodes of the two other electron guns, which are not being measured, are at the voltage us.
The second in
tegrated circuit circuit ic2 contains the microprocessor mp, the electrically reprogrammable memory ps, and the second bus interface circuit if2, which is associated with the serial data bus sb in this integrated circuit and also connects the microprocessor mp and the memory ps with one another and with itself. The memory ps holds alignment data and nominal dark-current/white-value data of the picture tube used, which were entered by the manufacturer. From this alignment and nominal data and from the measured data obtained via the second multiplexer mx2 and the analog-to-digital converter ad of the first integrated circuit ic1, the microprocessor mp derives video-signal-independent operating data for the picture tube. The derivation of these operating data is also outside the scope of the invention; it should only be mentioned that with respect to the operating data of the picture tube, the microprocessor performs a control function in accordance with a predetermined control characteristic.
The third integrated circuit ic3 includes the demultiplexer dx, which is connected to the first multiplexer mx1 of the first integrated circuit ic1 via the chroma bus cb and separates the chrominance signals cs and the operating data of the picture tube from the interleaved signals transferred over the chroma bus. While the transfer of measured data from the analog-to-digital converter ad to the microprocessor mp of the second integrated circuit ic2 takes place via the two interface circuits if1, if2 and the data bus sb at an appropriate instant, the video-signal-independent operating data for the picture tube b, which are derived by the microprocessor mp, are transferred from the second integrated circuit ic2 via the two interface circuits if1, if2 and the line db to the first multiplexer mx1 at an appropriate instant, and from the first multiplexer mx1 over a wire of the chroma bus cb into the shift register sr of the third integrated circuit ic3 shortly after the beginning of the next vertical blanking interval. To accomplish this, the first interface circuit if1 also includes a shift register from which the operating data are read serially.
During this data transfer into the shift register sr, the cathodes of the picture tube b are preferably at the voltage us in order that this data transfer does not become visible on the screen.
The appropriate instant for the transfer of measured data to the microprocessor mp is determined by the latter itself, i.e., depending on the program being executed in the microprocessor, and on the time needed therefor, the measured data are called for from the interface circuits not at the time of measurement but at a selectable instant within the working program of the microprocessor mp. If the measurement currently being performed should not yet be finished at the instant at which the measured data are called for, in a preferred embodiment of the invention, the stored data of the previous measurement will be transferred to the microprocessor mp.
As mentioned previously, the operating data for the picture tube b are transferred into the shift register sr at the beginning of a vertical blanking interval. The parallel outputs of this shift register are combined in groups each assigned to one operating value, and each group has one of the digital-to-analog converters dh, ddr, ddg, ddb, dwr, dwg, dwb associated with it. In the figure, the division of the shift register into groups is indicated by broken lines. The shift register sr performs a serial-to-parallel conversion in the usual manner, and the operating data are entered by the demultiplexer dx into the shift register in serial form and are then available at the parallel outputs of the shift register.
The digital-to-analog converter dh provides the analog brightness control signal, which is applied to the RGB matrix m in the integrated circuit ic3. Also applied to the RGB matrix m are the analog color-difference signals r-y, b-y and the luminance signal y. The formation of these signals is outside the scope of the invention and is known per se from the publications cited at the beginning.
The three analog-to-digital converters ddr, ddg, ddb provide the dark-current-adjusting signals for the three cathodes, which are currents and are applied to the inverting inputs--of the analog amplifiers vr, vg, vb. Also connected to these inputs is a resistor network which is adjustable in steps in response to the digital
white-level-adjusting signals at the respective group outputs of the shift register sr. The resistors serve as digital-to-analog converters dwr, dwg, dwb and establish the connection between the inverting inputs--and the outputs of the analog amplifiers vr, vg, vb. In an arrangement according to the invention which has proved good in practice, each of the three dark-current-adjusting signals is a seven-digit signal, and each of the three white-level-adjusting signals and the brightness control signal are five-digit signals. The voltages us and ud/uw of the three cathodes are assigned a three-digit identification signal in accordance with the above table, which signal is also fed into the shift register sr in the implemented circuit. Finally, a three-digit contrast control signal is provided in the implemented circuit for the Teletext mode of the color-television receiver. These nine data blocks are transferred in the implemented circuit from the demultiplexer dx to the shift register sr in the following order, with the least significant bit transmitted first, and with the specified number of blanks: identification signal, white-level signal blue, three blanks, white-level signal green, three blanks, white-level signal red, one blank, dark-current signal blue, one blank, dark-current signal green, one blank, dark-current signal red, contrast signal Teletext, and brightness control signal. These are seven eight-digit data blocks which are assigned to 56 pulses of a 4.4-MHz clock frequency, which is the frequency of the shift clock signal of the shift register sr.
It should be noted that the data sequence just described does not correspond to the order of the groups of the shift register sr in the figure. The order in the figure was chosen only for the sake of clarity.
The outputs of the three analog amplifiers vr, vg, vb are coupled to the inputs of the video output stage ve, whose outputs, as explained previously, are connected to the bases of the transistors pr, tg, td, so that the cathodes of the picture tube b are driven via the base-emitter paths of these transistors.
In another preferred embodiment of the invention, the measurement performed during a vertical blanking interval is not enabled until the data of the previous measurement has been transferred into the microprocessor mp. In this manner, no measurement will be left out.
It is also possible to omit the digital-to-analog converter dh if the analog RGB matrix m is replaced with a digital one.
One advantage of the invention is that the use of the chroma bus for the transfer of operating data facilitates the implementation of the third integrated circuit ic3 using bipolar technology, because an additional bus interface circuit, which could be used there, would occupy too much chip area.
Color-television receiver having integrated circuit for the luminance signal and the chrominance signals:
VIDEO CODEC UNIT (VCU).
The invention permits an n bit resolution to be achieved with an n-1 bit converter. In a color television receiver the analog-to-digital converter is a parallel analog-to-digital converter with p=2r -1 differential amplifiers as comparators, where r is the number of binary digits of the output signal of the analog-to-digital converter minus one. The composite color signal is then applied as the input signal to the noninverting (or inverting) inputs of all p differential amplifiers and the inverting (noninverting) inputs of the differential amplifiers being connected successively to the taps of a resistive voltage divider which contains equal-value resistors and is fed with a reference voltage (Ur).For the duration of every second line, either the reference voltage or the input signal is shifted by ΔU=0.5 Ur/2r.
1. A color-television receiver comprising at least one integrated circuit for separating and conditioning the luminance signal and the chrominance signals from the composite color signal, said integrated circuit containing: a chrominance-subcarrier oscillator,
a chrominance-subcarrier band-pass filter,
a synchronous demodulator,
a PAL switch,
a color matrix, and, if necessary,
an R--G--B matrix, and being characterized by the following subcircuits for conditioning digital signals:
the chrominance-subcarrier oscillator is a squarewave clock generator providing four clock signals the first of which has four times the chrominance-subcarrier frequency and the second to fourth of which have the chrominance-subcarrier frequency, with the first and second clock signals having a pulse duty factor of 0.5, and the third and fourth clock signals each consisting of two consecutive, T/2-long pulses separated by T/2 within each 4T-long period (T=period of the first clock signal);
an analog-to-digital converter clocked by the first clock signal, whose analog input is presented with the composite color signal, and which forms as its output signal a parallel binary word from the amplitude of the composite color signal (F) at the instants the respective amplitudes of the undemodulated chrominance signal are equal to the amplitudes of the respective color-difference signal;
a first binary arithmetic stage which multiplies the output signal of the analog-to-digital converter by a binary overall-contrast control signal;
a two-stage delay line which delays the output signal of the first binary arithmetic stage by T/2;
a second binary arithmetic stage which forms the arithmetic mean of the delayed and undelayed output signals of the first binary arithmetic stage;
a third binary arithmetic stage which subtracts the output signal of the second binary arithmetic stage from the output signal of the first delay stage;
a buffer-memory arrangement which temporarily stores the output signal of the third binary arithmetic stage, and whose enable input is fed with the third clock signal;
a shift-register arrangement consisting of n parallel shift registers (n=number of bits at the output of the third binary arithmetic stage) each of which provides a delay of one line period and whose serial inputs are connected to the parallel outputs of the buffer-memory arrangement, while their clock inputs are fed with the fourth clock signal;
a fourth binary arithmetic stage which forms the arithmetic mean of the input and output signals of the shift-register arrangement;
a fifth binary arithmetic stage which subtracts the input signal of the shift-register arrangement from the output signal of this arrangement and then divides the difference by two;
a sixth binary arithmetic stage which, controlled by the PAL switch, either leaves the output signal of the fifth binary arithmetic stage unchanged or forms its absolute value;
a seventh binary arithmetic stage which forms the green color-difference signal from the output signals of the fourth and sixth binary arithmetic stages;
the outputs of the second, fourth, sixth and seventh binary arithmetic stages are connected to the binary R-G-B matrix each of whose outputs is coupled to one of three digital-to-analog converters for deriving the analog signals for controlling the R-G-B values of the picture tube, or
the outputs of the second, fourth, sixth and seventh binary arithmetic stages are each connected to one of four digital-to-analog converters for deriving the analog signals for controlling the color-difference value of the picture tube;
the improvement wherein
the analog-to-digital converter is a parallel analog-to-digital converter with p=2r -1 differential amplifiers as comparators, where r is the number of binary digits of the output signal of the analog-to-digital converter minus one, the composite color signal being applied as the input signal to one of the noninverting or inverting inputs of all p differential amplifiers and the other of the inverting or noninverting inputs of the differential amplifiers being connected successively to the taps of a resistive voltage divider which contains equal-value resistors and is fed with a reference voltage (Ur), and
for the duration of every second line, either the reference voltage (Ur) or the input signal (F) is shifted by ΔU=0.5 Ur/2r.
Description:
Color-television receivers comprising at least one integrated circuit for separating and conditioning the luminance signal and the chrominance signals from the composite color signal are known in the art. The particular color-television receiver of such a known type comprises at least one integrated circuit for separating and conditioning the luminance signal and the chrominance signals from the composite color signal. This integrated circuit contains a chrominance-subcarrier oscillator, a chrominance-subcarrier band-pass filter, a synchronous demodulator, a PAL switch, a color matrix, and, if necessary, an R-G-B matrix. Additionally, such a color-television receiver contains the following subcircuits for conditioning digital signals; (1) the chrominance-subcarrier oscillator is a square-wave clock generator providing four clock signals the first of which has four times the chrominance-subcarrier frequency and the second to fourth of which have the chrominance-subcarrier frequency, with the first and second clock signals having a pulse duty factor of 0.5, and the third and fourth clock signals each consisting of two consecutive, T/2-long pulses separated by T/2 within each 4T-long period (T=period of the first clock signal); (2) an analog-to-digital converter clocked by the first clock signal, whose analog input is presented with the composite color signal, and which forms as its output signal a parallel binary word from the amplitude of the composite color signal (F) at the instants the respective amplitudes of the undemodulated chrominance signal are equal to the amplitudes of the respective color-difference signal; (3) a first binary arithmetic stage which multiplies the output signal of the analog-to-digital converter by a binary overall-contrast control signal; (4) a two stage delay line which delays the output signal of the first binary arithmetic stage by T/2; (5) a second binary arithmetic stage which forms the arithmetic means of the delayed and undelayed output signals of the first binary arithmetic stage; (6) a third binary arithmetic stage, which subtracts the output signal of the second binary arithmetic stage from the output signal of the first delay stage; (7) a buffer-memory arrangement which temporarily stores the output signal of the third binary arithmetic stage, and whose enable input is fed with the third clock signal; (8) a shift-register arrangement consisting of n parallel shift registers (n=number of bits at the output of the third binary arithmetic stage) each of which provides a delay of one line period and whose serial inputs are connected to the parallel outputs of the buffer-memory arrangement, while their clock inputs are fed with the fourth clock signal; (9) a fourth binary arithmetic stage which forms the arithmetic mean of the input and output signals of the shift-register arrangement; (10) a fifth binary arithmetic stage which subtracts the input signal of the shift-register arrangement from the output signal of this arrangement and then divides the difference by two; (11) a sixth binary arithmetic stage which, controlled by the PAL switch, either leaves the output signal of the fifth binary arithmetic stage unchanged or forms its absolute value; (12) a seventh binary arithmetic stage which forms the green color-difference signal from the output signals of the fourth and sixth binary arithmetic stages; (13) the outputs of the second, fourth, sixth and seventh binary arithmetic stages are connected to the binary R-G-B matrix each of whose outputs is coupled to one of three digital-to-analog converters for deriving the analog signals for controlling the R-G-B values of the picture tube, or (14) the outputs of the second, fourth, sixth and seventh binary arithmetic stages are each connected to one of four digital-to-analog converters for deriving the analog signals for controlling the color-difference values of the picture tube. An essential feature of such a receiver is the use of an analog-to-digital converter whose analog input is presented with the composite color signal and which is clocked by a clock signal at four times the chrominance-subcarrier frequency, so that a parallel binary word is obtained from the amplitudes of the composite color signal at the instants the respective amplitudes of the undemodulated chrominance signal are equal to the amplitudes of the respective color-difference signal. Thus, because of the high frequencies to be be processed, a parallel analog-to-digital converter is needed. Such fast parallel analog-to-digital converters are well known (cf. D. F. Hoeschele, "Analog-to-Digital/Digital-to-Analog Conversion Techniques", New York, 1968, p. 10) and contain 2 s -1 differential amplifiers as comparators, where s is the number of binary digits of the digital converter output signal. The noninverting (or inverting) inputs of all differential amplifiers are presented with the composite color signal, while the inverting (or noninverting) inputs are connected successively to the taps of a resistive voltage divider inserted between a constant reference voltage and ground and consisting of 2 s or 2 s -1 equal-value resistors. A 6-bit parallel analog-to-digital converter thus has 63 comparators and 63 resistors. A 7-bit converter has 127 comparators and resistors, and an 8-bit converter even has 255 comparators and resistors. It is readily apparent that as the number of digits increases, the implementation of such converters using integrated circuit techniques quickly becomes uneconomical. In particular, a reduction by one digit would result in the component count being halved.
Accordingly, the object of the invention is to reduce the number of comparators and resistors in an arrangement as set forth hereinbefore to one half without adversely affecting the digital resolution. In other words, the invention is to permit a 6-bit resolution, for example, to be achieved with a 5-bit converter. This is done by using the means set forth above recourse being had to the principle described in the above-cited book on pp. 413 to 415 as follows: In color-television receiver described above, the analog-to-digital converter is a parallel analog-to-digital converter with p=2 r -1 differential amplifiers as comparators, where r is the number of binary digits of the output signal of the analog-to-digital converter minus one. The composite color signal is then applied as the input signal to the noninverting (or inverting) inputs of all p differential amplifiers and the inverting (noninverting) inputs of the differential amplifiers being connected successively to the taps of a resistive voltage divider which contains equal-value resistors and is fed with a reference voltage (Ur). For the duration of every second line, either the reference voltage or the input signal is shifted by ΔU=0.5 Ur/2 r .
The invention will now be explained in more detail with reference to the accompanying drawings, in which:
FIG. 1 shows the block diagram of a color-television receiver of a known type.
FIGS. 2a-h, k, l, and p-t show various waveforms occurring in the arrangement of FIG. 1, and, in tabular form, signals occurring at given points of the circuit at given times, and
FIG. 3 is a block diagram of a preferred embodiment of the invention.
At the outset, FIG. 1, will be explained to permit a better understanding of the invention.
In the block diagrams shown in FIGS. 1 to 3, like parts are designated by like reference characters. In addition to interconnections indicated by solid lines as is usual in circuit diagrams, these figures contain interconnections indicated by stripes. These stripes mark connections between digital parallel outputs of the delivering portion of the circuit and digital parallel inputs of the receiving portion. The interconnections indicated by stripes, therefore, consist of at least as many wires as there are bits in the binary word to be transferred. Thus, the signals transferred over the lines indicated by stripes in FIGS. 1 to 3 are all binary signals whose instantaneous binary value corresponds to the instantaneous analog value of the composite color signal and of other signals. 
Like in conventional color-television receivers, the composite color signal F, derived in the usual manner controls the chrominance-subcarrier oscillator, which, according to the invention, is designed as a squarewave clock generator 1. By means of the so-called burst contained in the composite color signal F, the clock generator 1 is synchronized to the transmitted chrominance-subcarrier frequency. The clock generator 1 generates the clock signal F1, whose frequency is four times the chrominance-subcarrier frequency, i.e. about 17.73 MHz (precisely 17.734475 MHz) in the case of the CCIR standard. The clock generator 1 also generates the square-wave clock signal F2 having the frequency of the chrominance subcarrier. The first and second clock signals F1, F2 have a pulse duty factor of 0.5 (cf. FIGS. 2a and 2b). In addition, the clock generator 1 generates the third clock signal F3 and the fourth clock signal F4, each of which consists of two consecutive, T/2-long pulses separated by T/2 within each 4T-long period, where T is the period of the first clock signal F1. The third and fourth clock signals F3, F4 are shown in FIGS. 2b and 2g.
The individual clock signals are generated within the clock generator 1 in the usual manner using conventional digital techniques. The clock signal F1, for instance, may be generated by means of a suitable 17.73--MHz crystal, and the clock signals F2, F3, F4 may be derived therefrom by frequency division and suitable elimination of pulses. Like in conventional color-television receivers, the clock generator 1 is also fed with a pulse Z from the horizontal output stage during which the clock generator 1 is sychronized by the burst.
The composite color signal F is also applied to the analog input of the analog-to-digital converter 2, which is clocked by the first clock signal F1 and, (at the beginning of each pulse of the first clock signal F1) forms from the amplitude of this pulse a parallel binary word and delivers it as an output signal. These leading edges of the pulses of the first clock signal F1 thus occur at the instants the respective amplitudes of the undemodulated chrominance signal contained in the composite color signal are equal to the amplitudes of the respective color-difference signal. These parallel binary words then remain unchanged for the respective period T of the first clock signal F1, i.e., they are held like in a sample-and-hold circuit. The signals appearing at the output of the analog-to-digital converter 2 are given in tabular form in FIG. 2c, where the vertical lines symbolize the respective clock periods of the first clock signal F1. The letter c of FIG. 2 is also shown in FIG. 1 (encircled).
According to FIG. 2c, successive signals Y+V, Y-U, Y-V, and Y+U are obtained in a line m during one period of the second clock signal F2, where U, V and Y have the formal meanings given in the above-mentioned book, namely U=B-Y, V=R-Y, B=blue chrominance signal, R=red chrominance signal, and Y=luminance signal, but designate here the corresponding digitized signals, i.e., the corresponding binary words. The second line in the Table of FIG. 2c gives the corresponding binary signals in the line m+1, namely the signals Y-V, Y-U and Y+U, occurring during that period of the clock signal F2 which is under consideration.
This output signal of the analog-to-digital converter 2 is applied to one of the two inputs of the first binary arithmetic stage 10, which multiplies this output signal by a binary overall-contrast control signal GK. This overall contrast control signal thus corresponds to the analog overall-contrast control signal present in conventional color-television receivers. In present day color-television receivers, the binary overall contrast control signal GK, just as the binary color-saturation control signal FK and the binary brightness control signal H to be explained below, is available in digital form, because remote-control units and digital controls are usually present which provide these signals.
An advantage of the present application is, therefore, seen in the fact that these signals need no longer be conditioned in analog form in their place of action.
The output signal of the first binary arithmetic stage 10 is fed to the second binary arithmetic stage 20 and to the two-stage delay line 3, which delays this output signal by T/2. The second binary arithmetic stage 20 forms the arithmetic mean of the delayed and undelayed signals. The underlying idea is that if a sinusoidal signal, namely the chrominance subcarrier, is sampled at double frequency, the mean of two successive sample values will always be zero. Thus, by forming the arithmetic means in the second binary arithmetic stage 20, the chrominance subcarrier is suppressed and the luminance signal Y is obtained in digital form.
The output signal of the f
irst binary arithmetic stage 10, delayed in the first stage 31 of the delay line 3 by half the delay provided by this stage, i.e., by T/4, and the output signal of the second binary arithmetic stage 20 are then fed to the third binary arithmetic stage 30, which subtracts the latter signal, i.e., the Y signal, from the former signal. As a result, the output of the third binary arithmetic stage 30 provides the color-difference signal, made up of the successive components B-Y, R-Y, -(B-Y) and -(R-Y), as shown in FIG. 2d in tabular form for the lines m and m+1. These signals are fed to the buffer-memory arrangement 4, whose enable input is fed with the third clock signal F3, which is shown in FIG. 2e. This buffer memory operates in such a manner that the binary word fed to the input at the beginning of each pulse of the third clock signal F3 appears at the output when the next clock pulse occurs. Thus, the instantaneous output signals given in FIG. 2f in tabular form for the lines m and m+1 are obtained. The individual stages of the buffer-memory arrangement may be so-called D flip-flops, for example.
The output signal of the buffer-memory arrangement 4 is applied to the shift-register arrangement 5, which consists of n parallel shift registers, where n is the number of bits at the ouput of the third binary arithmetic stage 30. The delay provided by the n parallel shift registers is equal to the duration of one line, i.e., 64 μs in the case of PAL television sets. The clock inputs of the n parallel shift registers are fed with the fourth clock signal F4, which is shown in FIG. 2g. The output signal of the shift-register arrangement is given in tabular form in FIG. 2h for the lines m and m+1.
This output signal, together with the input signal of the shift-register arrangement 5 is fed to the fourth binary arithmetic stage 40, which forms the arithmetic means of the two signals, so that its output provides the signal B-Y in digital form, which is given in tabular form in FIG. 2k. The input and output signals of the shift-register arrangement 5 are also fed to the fifth binary arithmetic stage 50, which subtracts the input signal from the output signal and divides the difference by two. By the division, a sort of averaging is performed as well.
The output signal of the fifth binary arithmetic stage 50 is given in tabular form in FIG. 21, again for the lines m and m+1. This output signal is fed to the sixth binary arithmetic stage 60, which, in response to the output signal of the PAL switch 12, leaves it unchanged in one line and forms its absolute value in the other. "To form the absolute value" is used here first of all in the mathematical sense i.e., the negative sign of a negative number is suppressed and only the positive value of this negative number is taken into account. Within the scope of the present invention, however, "absolute value" also means "value with respect to a constant number". By this it is meant that for a number A below the constant X, the "absolute value with respect to X" is 2X-A. Thus, for the number 30, the "absolute value with respect to 50" is 70. The output of the sixth binary arithmetic stage 60 thus provides the PAL compensated signal R-Y in digital form, i.e., the red color-difference signal, which is given in tabular form in FIG. 2p for the lines m and m+1.
The output signals of the fourth binary arithmetic stage 40 and of the sixth binary arithmetic stage 60 are fed to the seventh binary arithmetic stage 70, which forms the green color-difference signal G-Y by the well-known formula Y=0.3R+0.59G+0.11B.
The subcircuits 5, 40, 50, 60 and 70, together with the PAL switch 12, represent the portion for correcting the phase of the received signal by the PAL method.
The output signals of the second, fourth, sixth and seventh binary arithmetic stages 20, 40, 60, 70, i.e., the luminance signal Y and the color-difference signals B-Y, R-Y, and G-Y, are then fed to the binary R-G-B matrix 6, which forms therefrom the binary chrominance signals R, G, B by the above formula. Each of these binary chrominance signals is then fed to one of the three digital-to-analog converters 7, 8, 9, which convert the binary chrominance signals to the analog chrominance signals R', G', B' necessary for R-G-B control of the picture tube.
In the embodiment of FIG. 1, each of thes digital-to-analog converters is also fed with the color-saturation control signal FK and the brightness control signal H, both in binary form. The PAL switch 12 is fed with the second clock signal F2, i.e., a signal having the chrominance-subcarrier frequency locked to the burst, with the composite color signal F, and with the reference pulse Z from the horizontal output stage.
FIG. 3 shows the block diagram of an embodiment of the invention. The analog-to-digital converter 2 is designed as a parallel analog-to-digital converter 2' and contains the differential amplifiers D1, D2, D3, Dp-1, Dp which are used as comparators, the resistors R1, R2, R3, Rp-1, Rp, RO, connected in series to form a voltage divider, and the decoder 21, which changes the output signals of the comparators into corresponding binary words. That portion of FIG. 3 located on the right-hand side of the decoder 21 is a greatly simplified representation of the units designated by like reference characters in FIG. 1.
The parallel analog-to-digital converter 2' contains p=2 r -1 differential amplifiers and a corresponding number of resistors, where r is the number of binary digits of the output signal of the analog-to-digital converter 2 of FIG. 1 minus one. If the analog-to-digital converter is to provide 8 bits, for example, then r is 7. The resistors R2 to Rp are alike and have a value of R, while the resistors RO, R1 have a value of 0.5 R.
According to the invention, the reference voltage applied to the comparators, in the embodiment of FIG. 3 to all inverting inputs, is shifted by ΔU=0.5 Ur/2 r during every second line as electronic switches S1 and S2 in parallel with resistors R1 and RO, respectively, are opened and closed alternately. Their control signal comes from one of the outputs Q, Q of the binary divider BT, which is fed with the horizontal synchronizing or horizontal flyback pulses Z.
Instead of shifting the reference voltage Ur as described, the amount of change ΔU may be added to the composite color signal in an analog adding stage during every second line. The reference voltage UR then remains constant.
By influencing the reference voltage Ur during every second line, and with the fourth or fifth binary arithmetic stage 40, 50 and the shift-register arrangement 5, which acts as a delay stage providing a delay of exactly one line period, the intended effect is produced, i.e., the number of comparators required is reduced to one half, while the resolution corresponds to that achieved with an additional binary digit since the average of the signals of two successive lines is taken at the output of the fourth or fifth binary arithmetic stage 40,50.
The principle explained with the aid of FIG. 3 can also be applied to the luminance channel if a comb filter and a delay arrangement providing a delay of one line period are provided in this channel.
Digital integrated chrominance-channel circuit with gain control:
(Pal) Video Processing Unit (VPU - PVPU)
An improved digital integrated chrominance-channel circuit having gain control for color-television receivers includes at least one integrated circuit for digitally processing the composite color signal. The circuit includes a first limiter inserted between a parallel multiplier and a burst-amplitude-measuring stage, and a control stage including a parallel subtracter whose minuend input is fed with a reference signal, and whose subtrahend input is connected to the output of the burst-amplitude-measuring stage. A digital accumulator whose enable input is presented with a signal derived from the trailing edge of a burst gating signal is used as an integrator.1. A digital integrated chrominance-channel circuit with gain control for color-television receivers, comprising:
at least one integrated circuit for digitally processing the composite color signal, wherein a digital chrominance signal appearing at an output of a digital chroma filter is applied to a first input of a parallel multiplier, and a digital gain control signal is applied to a second input of the parallel multiplier, the output of the parallel multiplier is connected to an input of a digital chroma demodulator with a color killer stage and to an input of a burst-amplitude-measuring stage whose output signal is compared with a reference signal in a control stage, the output signal of the control stage passes through an integrator whose output signal is the gain control signal;
a square-wave clock generator used as a chrominance subcarrier oscillator generates at least a first clock signal, whose frequency is four times that of the chrominance subcarrier, and a second clock signal, whose frequency is equal to that of the chrominance subcarrier; and
a first limiter is inserted between the parallel multiplier and the burst-amplitude-measuring stage, the control stage is a parallel subtracter whose minuend input is presented with the reference signal, and whose subtrahend input is connected to the output of the burst-amplitude-measuring stage and the integrator is a digital accumulator whose enable input is fed with a signal derived from the trailing edge of a burst gating signal.
2. A chrominance-channel circuit as claimed in claim 1, wherein the output signal from the first limiter is applied to the input of a first buffer memory and, through a delay element which provides a delay equal to the period of the first clock signal, to the input of a second buffer memory, the second clock signal being applied to the enable inputs of the first and second buffer memories during the burst gating signal, the output signals from the first buffer memory and the second buffer memory are fed, respectively, to a first absolute-value former and a second absolute-value former which have their outputs connected to the first and the second input, respectively, of a first parallel adder, the output of the first parallel adder is connected via a second limiter to the input of a third buffer memory and to the minuend input of a parallel comparator whose minuend-greater-than-subtrahend output is coupled to the enable input of the third buffer memory through the first input-output path of an AND gate whose second input is fed with the second clock signal, and the output of the third buffer memory is coupled to the subtrahend input of the parallel comparator, the output of the third buffer memory is connected to the input of a fourth buffer memory whose output is coupled to the subtrahend input of the parallel subtracter, and whose enable input is fed with a signal derived from the leading edges of horizontal-frequency pulses not coinciding with the burst gating signal, and the clear input of the third buffer memory is fed with a signal derived from the trailing edges of the pulses not coinciding with the burst gating signal. 3. A chrominance-channel circuit as claimed in claim 1, wherein the output signal from the parallel subtracter is applied to the first input of a second parallel adder having its output connected via a third limiter to the input of a fifth buffer memory whose output is coupled to the second input of the second parallel adder, and which has normalizing-data inputs and the enable input of the accumulator. 4. A chrominance-channel circuit as claimed in claim 2, wherein the output signal from the parallel subtracter is applied to the first input of a second parallel adder having its output connected via a third limiter to the input of a fifth buffer memory whose output is coupled to the second input of the second parallel adder, and which has normalizing-data inputs and the enable input of the accumulator. 5. A chrominance-channel circuit as claimed in claim 1, additionally comprising:
a first bus switch having its path from the break-contact input to the output inserted between the output of the chroma filter and the associated input of the parallel multiplier and its make-contact input connected to the input of the chroma filter;
a second bus switch having its path from the break-contact input to the output inserted between the output of the first limiter and the input of the chroma demodulator and its make-contact input connected to the input of the chroma filter;
a first test enable signal and a second test enable signal, which does not overlap the first test enable signal, being applied to the control input of the first bus switch and to the control input of the second bus switc
h, respectively; an actuating signal being applied to the input of the color killer stage during the second test enable signal;
a normalizing signal being applied to the enable input of the fifth buffer memory during a third test enable signal; and
in addition to the usual contact pads, there is a contact pad via which the test-result signals of the individual subcircuits are accessible.
6. A chrominance-channel circuit as claimed in claim 2, additionally comprising:
a first bus switch having its path from the break-contact input to the output inserted between the output of the chroma filter and the associated input of the parallel multiplier and its make-contact input connected to the input of the chroma filter;
a second bus switch having its path from the break-contact input to the output inserted between the output of the first limiter and the input of the chroma demodulator and its make-contact input connected to the input of the chroma filter;
a first test enable signal and a second test enable signal, which does not overlap the first test enable signal, being applied to the control input of the first bus switch and to the control input of the second bus switch, respectively;
an actuating signal being applied to the input of the color killer stage during the second test enable signal;
a normalizing signal being applied to the enable input of the fifth buffer memory during a third test enable signal; and
in addition to the usual contact pads, there is a contact pad via which the test-result signals of the individual subcircuits are accessible.
7. A chrominance-channel circuit as claimed in claim 3, additionally comprising:
a first bus switch having its path from the break-contact input to the output inserted between the output of the chroma filter and the associated input of the parallel multiplier and its make-contact input connected to the input of the chroma filter;
a second bus switch having its path from the break-contact input to the output inserted between the output of the first limiter and the input of the chroma demodulator and its make-contact input connected to the input of the chroma filter;
a first test enable signal and a second test enable signal, which does not overlap the first test enable signal, being applied to the control input of the first bus switch and to the control input of the second bus switch, respectively;
an actuating signal being applied to the input of the color killer stage during the second test enable signal;
a normalizing signal being applied to the enable input of the fifth buffer memory during a third test enable signal; and
in addition to the usual contact pads, there is a contact pad via which the test-result signals of the individual subcircuits are accessible.
8. A chrominance-channel circuit as claimed in claim 4, additionally comprising:
a first bus switch having its path from the break-contact input to the output inserted between the output of the chroma filter and the associated input of the parallel multiplier and its make-contact input connected to the input of the chroma filter;
a second bus switch having its path from the break-contact input to the output inserted between the output of the first limiter and the input of the chroma demodulator and its make-contact input connected to the input of the chroma filter;
a first test enable signal and a second test enable signal, which does not overlap the first test enable signal, being applied to the control input of the first bus switch, respectively;
an actuating signal being applied to the input of the color killer stage during the second test enable signal;
a normalizing signal being applied to the enable input of the fifth buffer memory during a third test enable signal; and
in addition to the usual contact pads, there is a contact pad via which the test-result signals of the individual subcircuits are accessible.
9. A method of testing a chrominance-channel circuit as claimed in claim 5, characterized by the following features:
in a first step, the chroma demodulator is tested by applying the second test enable signal to the control input of the second bus switch, the actuating signal to the input of the color killer stage, and a known data sequence to the input of the chroma filter;
in a second step, the parallel multiplier is tested by applying the first test enable signal to the control input of the first bus switch, the third test enable signal and the normalizing signal to the enable input of the accumulator, the normalizing data to the normalizing-data input of the accumulator, and a known data sequence to the input of the chroma filter;
in further steps, the absolute-value formers the first adder, and the parallel comparator are tested by applying the first test enable signal to the control input of the first bus switch, and known data sequences to the input of the chroma filter, and
in the last step, the accumulator is tested by applying the first test enable signal to the control input of the first bus switch, the third test enable signal and the normalizing signal to the enable input of the accumulator, the normalizing data to the normalizing data to the normalizing-data input of the accumulator, a trigger signal to the second limiter, and known data sequences to the minuend input of the parallel sub- tracter.
10. A method
of testing a chrominance-channel circuit as claimed in claim 6, characterized by the following features: in a first step, the chroma demodulator is tested by applying the second test enable signal to the control input of the second bus switch, the actuating signal to the input of the color killer stage, and a known data sequence to the input of the chroma filter;
in a second step, the parallel multiplier is tested by applying the first test enable signal to the control input of the first bus switch, the third test enable signal and the normalizing signal to the enable input of the accumulator, the normalizing data to the normalizing-data input of the accumulator, and a known data sequence to the input of the chroma filter;
in further steps, the absolute-value formers the first adder, and the parallel comparator are tested by applying the first test enable signal to the control input of the first bus switch, and known data sequences to the input of the chroma filter, and
in the last step, the accumulator is tested by applying the first test enable signal to the control input of the first bus switch, the third test enable signal and the normalizing signal to the enable input of the accumulator, the normalizing data to the normalizing-data input of the accumulator, a trigger signal to the second limiter, and known data sequences to the minuend input of the parallel subtracter.
11. A method of testing a chrominance-channel circuit as claimed in claim 7, characterized by the following features:
in a first step, the chroma demodulator is tested by applying the second test enable signal to the control input of the second bus switch, the actuating signal to the input of the color killer stage, and a known data sequence to the input of the chroma filter;
in a second step, the parallel multiplier is tested by applying the first test enable signal to the control input of the first bus switch, the third test enable signal and the normalizing signal to the enable input of the accumulator, the normalizing data to the normalizing-data input of the accumulator, and a known data sequence to the input of the chroma filter;
in further steps, the absolute-value formers the first adder, and the parallel comparator are tested by applying the first test enable signal to the control input of the first bus switch, and known data sequences to the input of the chroma filter, and
in the last step, the accumulator is tested by applying the first test enable signal to the control input of the first bus switch, the third test enable signal and the normalizing signal to the enable input of the accumulator, the normalizing data to the normalizing-data input of the accumulator, a trigger signal to the second limiter, and known data sequences to the minuend input of the parallel subtracter.
12. A method of testing a chrominance-channel circuit as claimed in claim 8, characterized by the following features:
in a first step, the chroma demodulator is tested by applying the second test enable signal to the control input of the second bus switch, the actuating signal to the input of the color killer stage, and a known data sequence to the input of the chroma filter;
in a second step, the parallel multiplier is tested by applying the first test enable signal to the control input of the first bus switch, the third test enable signal and the normalizing signal to the enable input of the accumulator, the normalizing data to the normalizing-data input of the accumulator, and a known data sequence to the input of the chroma filter;
in further steps, the absolute-value formers the first adder, and the parallel comparator are tested by applying the first test enable signal to the control input of the first bus switch, and known data sequences to the input of the chroma filter, and
in the last step, the accumulator is tested by applying the first test enable signal to the control input of the first bus switch, the third test enable signal and the normalizing signal to the enable input of the accumulator, the normalizing data to the normalizing-data input of the accumulator, a trigger signal to the second limiter, and known data sequences to the minuend input of the parallel subtracter.
Description:
1. Field of the Invention
The present invention relates to a digital integrated chrominance-channel circuit with gain control for color-television receivers containing at least one integrated circuit for digitally processing the composite color signal.
2. Description of the Prior Art
A chrominance-channel circuit is disclosed in the published patent application EP 51075 Al. (U.S. application Ser. No. 311,218, Oct. 11, 1981).
Practical tests of color-television receivers with digital signal processing circuitry have shown that the prior art chrominance-channel circuit still has a few disadvantages. For example, the burst-amplitude-measuring circuit is not yet optimal because it is possible in the prior art arrangement that the burst signals are sampled, i.e., measured, near or at the zero crossing. As these measured values are small, so that the digitized values formed therefrom are small numbers, the measurement error is large.
Another disadvantage of the prior art arrangement is that it has two set points for the gain control, namely a lower and an upper threshold level in the form of corresponding numbers entered into two read-only memories. Finally, the integration of the control signal is implemented with two counters, so that the time constant of this "integrator" is determined only by the clock signals for the counters and by the count lengths of these counters. As to the prior art, reference is also made to the journal "Fernseh- und Kino-Technik", 1981, pages 317 to 323, particularly FIG. 9 on page 321. However, the digital chrominance-channel circuit shown there works on the principle of feed-forward control, while both the invention and the above-mentioned prior art use a feedback control system, so that the arrangement disclosed in that journal lies further away from the present invention, the more so since in that prior art arrangement, the set point is implemented only with the concrete circuit (hardware).
The invention as claimed eliminates the above disadvantages and, thus, has for its object to improve the prior art digital integrated chrominance-channel circuit with gain control in such a way that error-free burst amplitude measurement is ensured, that a single set point can be generated, and that the integration of the control signal is implemented in optimum fashion. Another object of the invention is to modify the chrominance-channel circuit so that the automatic control system can be opened for measuring purposes.
FIG. 1 is a block diagram of the chrominance channel in accordance with the invention.
FIG. 2 is a block diagram of a preferred embodiment of the burst-amplitude-measuring stage and the digital accumulator.
FIG. 3 is a block diagram of another embodiment of the invention with the aforementioned measuring facility.
The block diagram of FIG. 1 includes a digital chroma filter cf, which derives a digital chrominance signal cs from a digitized composite color signal. The digital chrominance signal cs is applied to a first input of a parallel multiplier m, whose second input is fed with a digital gain control signal st. The output of the parallel multiplier m is connected to an input of a first limiter b1, which limits the output signals from the parallel multiplier m to a predetermined value. This can be done by arranging, for example, that at least one of the high-order digits of the output signal from the parallel multiplier is indicated by the interconnecting lead between these two subcircuits in FIG. 1. In the figures of the accompanying drawing, the lines interconnecting the signal inputs and outputs of the individual subcircuits are shown as stripelike connections (buses), while the solid lines commonly used to indicate interconnections in discrete-component circuits are used for interconnections over which only individual bits or clock and/or noise signals are transferred. The stripelike lines thus interconnect parallel inputs and parallel outputs, i.e., inputs to which complete binary words are applied, which are transferred in parallel into the subcircuit at a given time, and outputs which provide complete binary words.
An output signal bs of the first limiter b1 is applied to the input of a burst-amplitude-measuring stage bm, which has its output coupled to a subtrahend input (-) of a parallel subtracter sb, while its minuend input (+) is fed with the reference signal rs, i.e., the set point. The output of the parallel subtracter sb is connected to the input of a digital accumulator ak, which provides the digital gain control signal st, which is applied to the second input of the parallel multiplier m, as mentioned above. A signal rb derived from the trailing edge of the burst gating signal (keying pulse) is applied to an enable input eu of the accumulator ak.
It is also indicated in FIG. 1 that a square-wave clock generator os, used as a chrominance-subcarrier oscillator, forms part of the invention. It provides at least the first clock signal f1, whose frequency is four times that of the chrominance subcarrier, and a second clock signal f2, having the same frequency as the chrominance subcarrier.
FIG. 2 is a block diagram of a preferred embodiment of the burst-amplitude-measuring stage bm and the digital accumulator ak of FIG. 1. The burst-amplitude-measuring stage in FIG. 2 comprises all subcircuits ahead of the subtrahend input (-) of the parallel subtracter sb, while the accumulator consists of the subcircuits following the output of the parallel subtracter sb. The output signal bs from the first limiter b1 of FIG. 1 is applied in FIG. 2 to the input of a first buffer memory p1 and, through a delay element v, which provides a delay equal to the period of the first clock signal f1, i.e., to one quarter or 90° of the chrominance-subcarrier frequency, to an input of a second buffer memory p2.
The second clock signal f2 is applied to the enable inputs eu of these two buffer memories p1, p2 during the burst gating signal ki, which is indicated in FIG. 2 by the logical term f2.ki. During the keying pulse ki, whose duration usually equals about 10 periods of the chrominance-subcarrier frequency, a corresponding number of digital values are thus transferred successively from the first limiter b1 into the two buffer memories p1, p2, the values transferred into the second buffer memory p2 differing in phase from those transferred into the first buffer memory p1 by the aforementioned 90°; thus, two zero-crossing values are never evaluated at the same time.
The outputs of the two buffer memories p1, p2 are connected to the inputs of a first absolute-value former bb1 and a second absolute-value former bb2, respectively, whose outputs are coupled to a first and a second input, respectively, of a first adder a1. The absolute-value formers bb1, bb2 provide digital values without the sign of the input value, i.e., without the sign bit, for example. They thus contain a subcircuit which converts negative numbers in one's or two's complement notation into the corresponding positive number, i.e., they include complement reconverters.
The first adder a1 is followed by the second limiter b2, whose limiting action is controlled by at least one of the high-order digits of the first adder a1.
The output signal from the second limiter b2 is applied to the input of a third buffer memory p3 and to a minuend input a of a parallel comparator k, which has its subtrahend input b connected to the output of the third buffer memory p3.
In the present description, the two inputs of the parallel comparator k, too, are referred to as "minuend input" and "subtrahend input", respectively, which is considered justifiable in view of the fact that, purely formally, the arithmetic operation performed by comparators is more closely related to subtraction than to addition by means of an adder, even though the internal circuit of a comparator resembles that of an adder more than that of a subtracter, cf. the corresponding mathematical operations a-b and a b as opposed to a+b.
The minuend-greater-than-subtrahend output a>b of the parallel comparator k is connected to the enable input eu of the third buffer memory p3 via the first input-output path of the AND gate u, while the second clock signal f2 is applied to the second input of the AND gate u. The output of the third buffer memory p3 is also connected to an input of a fourth buffer memory p4, which has its output coupled to the subtrahend input (-) of the parallel subtracter sb. The enable input eu of the fourth buffer memory p4 is presented with a signal vz derived from the trailing edges of horizontal-frequency pulses zf, which, however, do not coincide with the burst gating signal ki, while a signal rz derived from the trailing edges of the horizontal-frequency pulses zf not coinciding with the burst gating signal ki is applied to the clear input el of the third buffer memory p3.
The derivation of the two signals rz, vz from the horizontal-frequency pulses zf is indicated in FIG. 2 by a pulse-shaper stage if. The section consistin
g of the two buffer memories p3, p4, the parallel comparator k, the AND gate u, and the pulse shaper if determines, for each line of the television picture, the maximum value of the burst amplitude from the--possibly limited--output signal of the first adder a1, and feeds this maximum value to the subtrahend input (-) of the parallel subtracter sb. This is achieved essentially by transferring only those words of the output signal of the second limiter b2 into the third buffer memory p3 which are greater than any word already stored in the third buffer memory p3. This is done line by line during the keying pulse ki. As mentioned, a preferred embodiment of the accumulator ak of FIG. 1 is shown in the lower portion of FIG. 2. The output signal from the parallel subtracter sb is applied to a first input of a second parallel adder a2, which has its output connected to an input of a fifth buffer memory p5 through the third limiter b3. To realize the adding function, the output of the fifth buffer memory p5 is connected to the second input of the second adder a2. The buffer memory p5 has, in addition to the enable input eu, which is the enable input of the accumulator ak of FIG. 1, the normalizing-data inputs ne, through which normalizing data nd, i.e., known data, can be entered if necessary. The enable input eu is presented with the signal rb derived from the trailing edge of the burst gating signal ki. With the trailing edge of the keying pulse, the output signal from the third limiter b3 is thus transferred into the fifth buffer memory p5 and simultaneously transferred to the output. With the trailing edge of each keying pulse, the sum of the value from the preceding line and the set-point deviation calculated in the measured line by the parallel subtracter sb is thus produced line by line as the control signal st.
Thus, the essential advantages of the invention follow directly from the solution of the problem, namely particularly the line-by-line subtraction of the maximum burst amplitude, which is integrated in the accumulator ak to form the control signal st for the automatic control system, from the reference signal rs.
FIG. 3, a block diagram like FIGS. 1 and 2, shows a preferred embodiment of the invention which makes it possible to test the digital automatic control system after the fabrication of the integrated circuit, and to make the test-result signals accessible. The testing is necessary because the automatic control system contains several subcircuits each of which may be faulty. The test procedure and the design of the overall circuit must therefore be adapted to one another in such a way that all subcircuits of the automatic control system can be tested with little additional circuitry. To this end, the path from a break-contact input to an output of a first bus switch bu1, whose make-contact input is connected to the input of the chroma filter cf, is interposed between the output of this chroma filter and the associated input of the parallel multiplier m, as shown in the block diagram of FIG. 3. For the graphic representation of the bus switch bu1, the symbol of a mechanical transfer switch has been chosen, with the above mentioned stripelike interconnecting lines, i.e., buses, connected to the signal inputs and the output of the switch. It is thus clear that the bus switch consists of as many individual electronic switches as there are wires in the buses.
Inserted between the output of the first limiter b1 and the input of the chroma demodulator cd, which is also present in FIG. 1, where it "demodulates" the output signal bs of the first limiter b1 into the chroma signal cs, is a path from a break-contact input to an output of a second bus switch bu2, which has its make-contact input am connected to the input of the chroma filter cf. Viewed in the direction of signal flow, the second bus switch bu2 lies behind the junction point where the signal bs for the burst-amplitude-measuring circuit is taken off. What was said on the circuit design and the graphic representation of the first bus switch bu1 applies analogously to the second bus switch bu2.
The first test enable signal t1 and the second test enable signal t2, which does not overlap the first test enable signal t1, are applied to the control input of the first bus switch bu1 and to the control input of the second bus switch bu2, respectively. Thus, when the second bus switch bu2 is in its "make" position, the first bus switch bu2 is in its "break" position, and vice versa.
During the first test enable signal t1, an actuating signal db is applied to the input ec of the color killer stage ck of the chroma demodulator cd, so that the latter is active during the testing of the automatic control system although the circuit is not in its normal mode of operation but only in a test mode.
The enable input eu of the accumulator ak, i.e., the enable input eu of the fifth buffer memory p5 in FIG. 3, may be fed with a normalizing signal ns during the third test enable signal t3. During testing and measurement, instead of the signal rb, derived from the trailing edge of the keying pulse and applied in the normal mode of operation, the normalizing signal ns is applied to the enable input eu of the fifth buffer memory p5 and causes the normalizing data nd to be transferred into this buffer.
In addition to the usual contact pads of the integrated circuit, through part of which the output signal cs of the chroma demodulator cd is coupled out, a contact pad is provided via which test-result signals of individual subcircuits are accessible, i.e., transferred out of the integrated circuit. These test-result signals are advantageously coupled to this additional contact pad through transfer transistors which, in turn, are driven by the above-mentioned test enable signals or corresponding additional signals of this kind or by signals derived by performing simple logic operations on the signals just mentioned. In this manner, only the respective subcircuit to be tested is connected to the additional contact pad.
An advantageous method of testing the chrominance-channel circuit according to the invention consists in the following time sequence of test steps. In the first step, the chroma demodulator cd is tested. This is necessary because, throughout the testing of the chrominance-channel circuit, signals are transferred out through the chroma demodulator cd and must not be falsified by the latter.
This first test step is performed by applying the second test enable signal t2 to the control input of the second bus switch bu2, the actuating signal db to the input ec of the color killer stage ck, and a known data sequence, i.e., a test-data sequence, to the input of the chroma filter cf. The application of the actuating signal db to the input ec of the color killer stage ck is necessary because an actual actuating signal coming from other stages of the chrominance-channel circuit is applied to the color killer only during normal operation of the chrominance-channel circuit, cf. the above-mentioned printed publication EP 0 051 075 Al.
In response to the application of the second test enable signal t2 to the second bus switch bu2, the input signals of the chroma filter cf are transferred directly to the input of the chroma demodulator cd, so that, if a known test-data sequence is used, the performance of the chroma demodulator cd can be checked by means of the output signals.
In the second step, the parallel multiplier m is tested. This is done by applying the first test enable signal t1 to the control input of the first
bus switch bu1, the third test enable signal t3 and the normalizing signal ns to the enable input of the accumulator ak, i.e., to the enable input of the fifth buffer memory p5, for example; the normalizing data nd are applied to the normalizing-data input ne of the fifth buffer memory p5, and a known data sequence, i.e., a test-data sequence, is applied to the input of the chroma filter cf. As in the first test, the first test enable signal t1 causes the test-data sequence to bypass the chroma filter cf, so that the test data are applied directly to one input of the parallel multiplier m. This bypassing of the chroma filter cf is necessary because the chroma filter is generally a dynamic subcircuit, which is not suitable for being included in the individual tests for this reason alone.
As a result of the entry of normalizing data into the accumulator ak or into the fifth buffer memory p5 as a subcircuit of the accumulator, known data are also applied to the second input of the parallel multiplier m, so that the output signal of the latter is predeterminable, which makes it possible to check the correct functioning of the multiplier. Since the chroma demodulator cd was tested already in the first test step, the data appearing at its output during the second test step are the unchanged output data of the parallel multiplier m if the chroma demodulator cd was found to operate correctly.
Further tests may now be performed on the absolute-value formers bb1, bb2, the first adder a1, and the parallel comparator k. To do this, the first test enable signal t1 is applied to the control input of the first bus switch bu1, and known data sequences are applied to the input of the chroma filter cf, the individual test results being accessible via the above-mentioned additional contact pad and being generally present in the form of a go/no-go decision.
The last test to be performed is that of the accumulator ak. To this end, the first test enable signal t1 is applied to the control input of the first bus switch bu1; the third test enable signal t3 and the normalizing signal ns are applied to the enable input of the accumulator ak, i.e., to the corresponding input of the fifth buffer memory p5, for example; a trigger signal is applied to the second limiter b2, and known data sequences are fed to the minuend input (+) of the parallel subtracter sb. With the second limiter sb2 triggered, one of the input signals of the accumulator is predetermined and, thus, known because the output data of the subtracter sb are known as well. The accumulator ak can thus be tested by varying the reference data rs.
The reference data rs, the above-mentioned various test-data sequences, and the normalizing data nd may come from a microprocessor.
Digital horizontal-deflection circuit:
Digital deflection Processor (DPU)
Instead of fine-controlling the horizontal deflection signal in a digital television receiver by means of two phase-locked loops and gate-delay stages as is done in prior art arrangements, in the horizontal-deflection circuit according to the invention, a first digital word delivered by a first phase-locked loop and representative of the horizontal frequency is added in an adder to a suitably amplified third digital word delivered by a phase comparator of a second phase-locked loop. The output of the adder is fed to the control input of a digital sine-wave generator which drives a frequency divider. The latter delivers the horizontal deflection signal, which drives the horizontal output stage. The phase comparator is fed with the horizontal flyback signal, which is derived from the horizontal deflection signal, and a second digital word generated by the first phase-locked loop and representative of the desired phase position of the flyback signal.
What is claimed is: 1. A digital horizontal-deflection circuit for generating an analog horizontal deflection signal driving the horizontal output stage of a digital television receiver clocked with a system clock, comprising:
a first digital phase-locked loop which synchronizes the horizontal deflection signal with the horizontal synchronizing signal separated from the composite color signal and delivers for each line of video signal a first digital word representative of the horizontal frequency and a second digital word representative of the desired phase position of the horizontal flyback signal;
a second phase-locked loop which uses a digital phase comparator to generate a third digital word representative of the phase deviation of the horizontal flyback signal from the desired position and shifts the horizontal deflection signal in time so that the horizontal flyback signal takes up the desired phase position;
an adder having a first input to which said first digital word is fed and a second input to which said third digital word is fed via a multiplier serving as an amplifier;
a digital sine-wave generator having a control input to which the output of said adder is fed; and
a frequency divider to which the output of said digital sine-wave generator is supplied, the output of said frequency divider providing the horizontal deflection signal.
2. A horizontal-deflection circuit as defined in claim wherein said first digital word is representative of the period of the horizontal deflection signal, and additionally comprising a digital period-to-frequency converter connected between said first phase-locked loop and said first input of said adder. 3. A horizontal-deflection circuit as defined in claims 1 or 2, additionally comprising a protection circuit coupled between the output of said digital sine-wave generator and the input of said frequency divider, said protection circuit providing a sine-wave signal of a desired frequency if the frequency of said sine-wave generator departs from a desired-value range. 4. A horizontal-deflection circuit as defined in claim 3, wherein said protection circuit is an analog phase-locked loop.
a first digital phase-locked loop which synchronizes the horizontal deflection signal with the horizontal synchronizing signal separated from the composite color signal and delivers for each line of video signal a first digital word representative of the horizontal frequency and a second digital word representative of the desired phase position of the horizontal flyback signal;
a second phase-locked loop which uses a digital phase comparator to generate a third digital word representative of the phase deviation of the horizontal flyback signal from the desired position and shifts the horizontal deflection signal in time so that the horizontal flyback signal takes up the desired phase position;
an adder having a first input to which said first digital word is fed and a second input to which said third digital word is fed via a multiplier serving as an amplifier;
a digital sine-wave generator having a control input to which the output of said adder is fed; and
a frequency divider to which the output of said digital sine-wave generator is supplied, the output of said frequency divider providing the horizontal deflection signal.
2. A horizontal-deflection circuit as defined in claim wherein said first digital word is representative of the period of the horizontal deflection signal, and additionally comprising a digital period-to-frequency converter connected between said first phase-locked loop and said first input of said adder. 3. A horizontal-deflection circuit as defined in claims 1 or 2, additionally comprising a protection circuit coupled between the output of said digital sine-wave generator and the input of said frequency divider, said protection circuit providing a sine-wave signal of a desired frequency if the frequency of said sine-wave generator departs from a desired-value range. 4. A horizontal-deflection circuit as defined in claim 3, wherein said protection circuit is an analog phase-locked loop.
Description:
The present invention relates to a digital horizontal-deflection circuit for generating an analog horizontal deflection signal driving the horizontal output stage of a digital television receiver clocked with a system clock. A digital horizontal-deflection circuit of this kind is described in a data book of Intermetall, "DIGIT 2000 VLSI Digital TV System," 1984/5, pages 112 to 114, which deal with the integrated circuit DPU 2500.
In the prior art arrangement, the phase variation which is necessary for the digital generation of the horizontal deflection signal and must be stepped in fractions of the period of the system clock is achieved essentially by the use of gate-delay stages or chains as are described, for example, in the European Patent Applications EP-A Nos. 0,059,802; 0,080,970; and 0,116,669, which essentially utilize the inherent delay of inverters. It turned out, however, that with these arrangements, it is not possible to completely control all operating conditions which may occur.
It is, therefore, the object of the invention to modify and improve the digital horizontal-deflection circuit described in the above prior art in such a way that the gate-delay stages can be dispensed with.
The invention will now be explained in more detail with reference to the single FIGURE of the accompanying drawing, which is a block diagram of an embodiment of the invention. The block diagram shows that portion of a digital television receiver, i.e., of a television receiver in which the analog signal received via the antenna is processed digitally, which is of interest in connection with the invention. Thus, all subcircuits for digital-to-analog conversion, sync separation, chrominance-signal and luminance-signal processing or sound-signal processing have been omitted; the overall circuit concept of digital television receivers has been well known for some time. The first digital phase-locked loop (PLL) p1 is supplied with the (digital) horizontal synchronizing signal hs, which was separated from the composite color signal, and the system clock st, and derives therefrom, in the manner described in the prior art, the first digital word d1, which is representative of the horizontal frequency, and the second digital word d2, which is representative of the desired phase position of the horizontal flyback signal fy. The signal fy comes from the receiver's horizontal output stage ps, which supplies the necessary sawtooth current to the deflection coil 1. The phase position of the flyback signal fy relative to the horizontal deflection signal ps is dependent on the switching properties of the horizontal output stage ps and is also influenced by the video signal applied to the picture tube.
By means of the second PLL p2, indicated in the FIGURE by the large rectangle bounded by a broken line, these dependences are compensated in the manner described in the prior art. The phase comparator pv generates the third digital word d3, which is representative of the phase deviation of the flyback signal fy from its desired position, and the second PLL p2 shifts the horizontal deflection signal ds in time so that the flyback signal fy takes up the desired phase position.
The first digital word d1 is fed to the first input of the adder ad, and the third digital word d3 is fed to the second input of this adder via the multiplier m, which serves as an amplifier. The second input of the multiplier m is fed with the signal k determining the gain of the second PLL p2, so that the transient response of the latter can be optimally adjusted by the manufacturer of the television receiver.
The output of the adder ad is fed to the control input of the digital sine-wave generator s, which may be designed as an accumulator followed by a sine looker table (ROM). If an n-bit word d4 is applied to its control input, this arrangement, which is known in principle, delivers a sine-wave of frequency (d4)fs/2 n , where fs is the frequency of the system clock st.
The output of the digital sine-wave generator sg is fed to the frequency divider ft, which provides the horizontal deflection signal ds, a square-wave signal as usual. The frequency divider ft thus not only divides the frequency of the signal delivered by the sine-wave generator sg, but also converts the sine-wave signal into the above-mentioned square-wave signal; this can be done in a suitable sine-to-square wave converter stage at the input of the frequency divider ft.
Two stages which can be added to the arrangement singly or in combination are indicated in the FIGURE by rectangles bounded by broken lines. The period-to-frequency converter fw between the output of the first PLL pl for the first digital word d1 and the corresponding input of the adder ad is necessary if the first digital word d1, generated by the first PLL p1, represents the period of the horizontal deflection signal ds (if this word represents the frequency of the horizontal deflection signal, the stage fw is not necessary).
Between the output of the digital sine-wave generator sg and the input of the frequency divider ft, the protection circuit sc may be inserted. It is preferably an analog phase-locked loop which provides a sine-wave signal of the desired frequency if the frequency of the sine-wave generator sg departs from a predetermined desired-value range. This may be to advantage during the start-up phase after the turning on of the television receiver or may serve to afford protection in the event of a failure of one or both of the PLL's p1, p2.
In the FIGURE, the stripe-like connecting leads represent signal paths over which digital signals are transferred in parallel, i.e., on these buses, the individual (parallel) digital words follow one after the other at the pulse repetition rate of the system clock st. The fact that the individual stages of the second PLL p2--where necessary and appropriate--and the period-to-frequency converter fw are clocked with the system clock st, too, is indicated by the respective clock input lines. The digital horizontal-deflection circuit in accordance with the invention is preferably realized using monolithic integrated circuit techniques, particularly MOS technology. It may form part of a larger integrated circuit but can also be implemented as a separate integrated circuit.
Digital circuit for steepening color-signal transitions:
Digital Transient Improvement Processor (DTI)
This circuit arrangement is designed for use in digital color-television receivers or the like and contains for each of the two digital color-difference signals a slope detector to which both a digital signal defining an amplitude threshold value and a digital signal defining a time threshold value are applied. At least one intermediate value occurring during an edge to be steepened is stored, and at the same time value of the steepened edge, it is "inserted" into the latter. This is done by means of memories switches, output registers, and a sequence controller.
What is claimed is: 1. A circuit arrangement for steepening color-signal transitions, comprising:
first and second circuit branches, said first branch receiving a first color difference digital signal from a first color difference channel and said second branch receiving a second color difference digital signal from a second color difference channel, each of said branches comprising:
a digital slope detector for generating a control signal at an output when the respective one of said first or second color difference digital signals has a predetermined relationship to predetermined amplitude and time thresholds;
a first delay element receiving and delaying said respective one color difference digital signal by a time equal to the delay of said digital slope detector;
at least one memory having its input connected to the output of said first delay element;
a switch having first and second inputs connected to the outputs of said delay element and said at least one memory, respectively; and
an output register having its input connected to the output of said switch;
and
a sequence controller coupled to the outputs of said digital slope detectors in said first and second circuit branches, and receiving a clock signal having a predetermined frequency relationship to a chrominance subcarrier frequency, and receiving a digital signal determining the hold time equal to the known system rise time of said first and second color difference channels, said sequence controller providing sequence control signals for controlling said at least one memory, said switch and said output register in both of said first and second circuit branches such that:
a color difference signal value occurring at an intermediate value of said hold time is read into said memory, said color difference signal value stored in said memory is read via said switch into said output rergister at the corresponding intermediate value of the steepened leading edge of said color-signal, the input of said output register being connected to the output of said delay element at all times except at said intermediate value of said steepened leading edge.
2. A circuit arrangement in accordance with claim 1, wherein each said slope detector comprises:
a first digital differentiator receiving the respective color difference digital signal;
a digital absolute value stage coupled to said first digital differentiator output;
a first digital comparator having a minuend input coupled to said digital absolute value stage output, a subtrahend input supplied with a digital signal corresponding to said amplitude threshold value, and an output;
a second digital differentiator having an input coupled to said comparator output;
a counter for counting pulses of said clock signal, said counter having an enable input coupled to said comparator output, and having a reset input coupled to the output of said second digital differentiator;
a fifth memory having its inputs coupled to the count outputs of said counter and an enable input coupled to said second digital differentiator output;
a second digital comparator having a minuend input coupled to the output of said fifth memory, a subtrahend input supplied with a digital signal corresponding to said time threshold value; and
gate means for combining the output of said comparator and the output of said second digital differentiator to provide said control signal when the output of said comparator and the output of said second digital differentiator are both active.
3. A circuit arrangement in accordance with claim 2,
wherein each of said first and second circuit branches further comprises a second memory having its input connected to said first delay element output, said switch having a third input coupled to said second memory output; and
wherein said sequence controller comprises:
a counter for counting pulses of said clock signal; and
a decoder for decoding the count output of said counter to provide said sequence control signals, said sequence control signals also controlling each said second memory,
said sequence controller operating such that color difference signal values occurring at the end of the first third of said hold time are written into said at least one memory, and color difference signal values occurring at the end of the second third of said hold time are written into said second memory; and
wherein:
in said first circuit branch the contents of said at least one memory and said second memory are written via said switch into said output register at the end of the first third and at the end of the second third, respectively, of said steepened leading edge;
in said second circuit branch the contents of said at least one memory and said second memory are written via said switch into said output register at the end of the first third and the second third, respectively, of said steepened leading edge; and
the input of the respective output register of each of said first and second circuit branches is connected to the output of the respective first delay element at all times except at the end of said first third and said second third or said steepened leading edge.
4. A circuit arrangement in accordance with claim 1,
wherein each of said first and second circuit branches further comprises a second memory having its input connected to said first delay element output, said switch having a third input coupled to said second memory output;
wherein said sequence controller comprises:
a counter for counting pulses of said clock signal; and
a decoder for decoding the count output of said counter to provide said sequence control signals, said sequence control signals also controlling each said second memory,
said sequence controller operating such that color difference signal values occurring at the end of the first third of said hold time are written into said at least one memory, and color difference signal values occurring at the end of the second third of said hold time are written into said second memory; and
wherein:
in said first circuit branch the contents of said at least one memory and said second memory are written via said switch into said output register at the end of the first third and at the end of said second third, respectively, of said steepened leading edge;
in said second circuit branch the contents of said at least one memory and said second memory are written via said switch into said output register at the end of the first third and the second third, respectively, of said steepened leading edge; and
the input of the respective output register of each of said first and second circuit branches is connected to the output of the respective first delay element at all times except at the end of said first third and said second third of said steepened leading edge.
first and second circuit branches, said first branch receiving a first color difference digital signal from a first color difference channel and said second branch receiving a second color difference digital signal from a second color difference channel, each of said branches comprising:
a digital slope detector for generating a control signal at an output when the respective one of said first or second color difference digital signals has a predetermined relationship to predetermined amplitude and time thresholds;
a first delay element receiving and delaying said respective one color difference digital signal by a time equal to the delay of said digital slope detector;
at least one memory having its input connected to the output of said first delay element;
a switch having first and second inputs connected to the outputs of said delay element and said at least one memory, respectively; and
an output register having its input connected to the output of said switch;
and
a sequence controller coupled to the outputs of said digital slope detectors in said first and second circuit branches, and receiving a clock signal having a predetermined frequency relationship to a chrominance subcarrier frequency, and receiving a digital signal determining the hold time equal to the known system rise time of said first and second color difference channels, said sequence controller providing sequence control signals for controlling said at least one memory, said switch and said output register in both of said first and second circuit branches such that:
a color difference signal value occurring at an intermediate value of said hold time is read into said memory, said color difference signal value stored in said memory is read via said switch into said output rergister at the corresponding intermediate value of the steepened leading edge of said color-signal, the input of said output register being connected to the output of said delay element at all times except at said intermediate value of said steepened leading edge.
2. A circuit arrangement in accordance with claim 1, wherein each said slope detector comprises:
a first digital differentiator receiving the respective color difference digital signal;
a digital absolute value stage coupled to said first digital differentiator output;
a first digital comparator having a minuend input coupled to said digital absolute value stage output, a subtrahend input supplied with a digital signal corresponding to said amplitude threshold value, and an output;
a second digital differentiator having an input coupled to said comparator output;
a counter for counting pulses of said clock signal, said counter having an enable input coupled to said comparator output, and having a reset input coupled to the output of said second digital differentiator;
a fifth memory having its inputs coupled to the count outputs of said counter and an enable input coupled to said second digital differentiator output;
a second digital comparator having a minuend input coupled to the output of said fifth memory, a subtrahend input supplied with a digital signal corresponding to said time threshold value; and
gate means for combining the output of said comparator and the output of said second digital differentiator to provide said control sign
al when the output of said comparator and the output of said second digital differentiator are both active.3. A circuit arrangement in accordance with claim 2,
wherein each of said first and second circuit branches further comprises a second memory having its input connected to said first delay element output, said switch having a third input coupled to said second memory output; and
wherein said sequence controller comprises:
a counter for counting pulses of said clock signal; and
a decoder for decoding the count output of said counter to provide said sequence control signals, said sequence control signals also controlling each said second memory,
said sequence controller operating such that color difference signal values occurring at the end of the first third of said hold time are written into said at least one memory, and color difference signal values occurring at the end of the second third of said hold time are written into said second memory; and
wherein:
in said first circuit branch the contents of said at least one memory and said second memory are written via said switch into said output register at the end of the first third and at the end of the second third, respectively, of said steepened leading edge;
in said second circuit branch the contents of said at least one memory and said second memory are written via said switch into said output register at the end of the first third and the second third, respectively, of said steepened leading edge; and
the input of the respective output register of each of said first and second circuit branches is connected to the output of the respective first delay element at all times except at the end of said first third and said second third or said steepened leading edge.
4. A circuit arrangement in accordance with claim 1,
wherein each of said first and second circuit branches further comprises a second memory having its input connected to said first delay element output, said switch having a third input coupled to said second memory output;
wherein said sequence controller comprises:
a counter for counting pulses of said clock signal; and
a decoder for decoding the count output of said counter to provide said sequence control signals, said sequence control signals also controlling each said second memory,
said sequence controller operating such that color difference signal values occurring at the end of the first third of said hold time are written into said at least one memory, and color difference signal values occurring at the end of the second third of said hold time are written into said second memory; and
wherein:
in said first circuit branch the contents of said at least one memory and said second memory are written via said switch into said output register at the end of the first third and at the end of said second third, respectively, of said steepened leading edge;
in said second circuit branch the contents of said at least one memory and said second memory are written via said switch into said output register at the end of the first third and the second third, respectively, of said steepened leading edge; and
the input of the respective output register of each of said first and second circuit branches is connected to the output of the respective first delay element at all times except at the end of said first third and said second third of said steepened leading edge.
Description:
The invention pertains to a circuit for steepening color-signal transitions in color television receivers or the like.
A circuit arrangement of this kind includes a slope detector which, when a predetermined amplitude threshold value is exceeded, delivers a switching signal which causes a substitute signal to appear at the respective output of the two color-difference channels for the duration of the system rise time of said channels. One circuit arrangement of this kind, which provides a chroma transient improvement, is described in a publication by VALVO entitled "Technische Information 840228 (Feb. 28, 1984): Versteilerung von Farbsignalsprungen and Leuchtdichtesignal-Verzogerung mit der Schaltung TDA 4560".
The bandwidth of the color-difference channel is very small compared with the bandwidth of the luminance channel, namely only about 1/5 that of the luminance channel in the television standards now in use. This narrow bandwidth leads to blurred color transitions ("color edging") in case of sudden color-signal changes, e.g., at the edges of the usual color-bar test signal, because, compared with the associated luminance-signal transition, an approximately fivefold duration of the color-signal transition results from the narrow transmission bandwidth.
In the prior circuit arrangement, the relatively slowly rising color-signal edges are steepened by suitably delaying the color-difference signals and the luminance signal and steepening the edges of the color-difference signals at the end of the delay by suitable analog circuits. The color-difference signals and the luminance signal are present and processed in analog form as usual.
The problem to be solved by the invention is to modify the principle of the prior art analog circuits in such a way that it can be used in known color-television receivers with digital signal-processing circuitry (cf. "Electronics", Aug. 11, 1981, pages 97 to 103), with the slope detector responding not only to one criterion, namely a predeterminable amplitude threshold value as in the prior art arrangement, but to an additional criterion.
In accordance with the invention a circuit arrangement provides a fully digital solution for chroma transient improvement. The circuit arrangement contains a slope detector, a memory, a switch-over switch and a timing control stage for the processing of each color difference signal. A time period threshold signal and an amplitude threshold signal are fed to the slope detector. If the amplitude threshold is exceeded and the time threshold is not being reached, the slope is improved.
This circuit arrangement is designed for use in digital color-television receivers or the like and contains for each of the two digital color-difference signals a slope detector to which both a digital signal defining an amplitude threshold value and a digital signal defining a time threshold value are applied. At least one intermediate value occurring during an edge to be steepened is stored, and at the same time value of the steepened edge, it is "inserted" into the latter. This is done by means of memories, switches, output registers, and a sequence controller.
The invention will be better understood from a reading of the following detailed description in conjunction with the drawing in which:
FIG. 1 is a block diagram of a first embodiment of the invention;
FIG. 2 is a block diagram of a second form of the arrangement of FIG. 1;
FIG. 3 is a block diagram of an embodiment of the slope detectors of FIGS. 1 and 2;
FIGS. 4a-c shows various waveforms to explain the basic operation of the invention; and
FIGS. 5a and 5b shows waveforms to explain the operation of the improved arrangement of FIG. 2.
In the block diagram of FIG. 1, the digital color-difference signals yr, yb are present in the baseband at the frequency of the clock signal f, which is four times the chrominance-subcarrier frequency, i.e., the individual data words appear one after the other at this frequency. If a subharmonic of the clock signal f, i.e., the chrominance-subcarrier frequency itself, for example, is chosen for the color-difference-signal demodulation as may be the case in known digital color-television receivers, these digital signals must be brought to the aforementioned repetition frequency of the clock signal f by digital interpolation. In FIG. 1, there are two branches for the two color-difference signal yr and yb, respectively. They are of the same design, with the branch z1 assigned to the red-minus-luminance channel, and the branch z2 to the blue-minus-luminance channel. In the branch z1, the red-minus-luminance signal yr is applied to the inputs of the first delay element v1 and the first digital slope detector fs1. The output of the first delay element v1 is fed to the input of the first memory s1 and to one of the inputs of the first switch us1, whereas the output of the first memory s1 is connected to the other input of the first switch us1, whose output is coupled to the input of the first output register r1.
The second branch z2, to which the blue-minus-luminance signals yb are applied, is of the same design as the first branch z1 as far as the individual circuits and their interconnections are concerned, and contains the second digital slope detector fs2, the second delay element v2, the second memory s2, the second switch us2, and the second output register r2.
The output signals of the two slope detectors fs1, fs2 are applied, respectively, to the first and second inputs of the OR gate og, whose output is connected to the first input of the sequence controller ab. The second input of the latter is presented with the clock signal f, and the third input with the digital signal hz, by which the hold time equal to the system rise time of the color-difference channels can be preset. The outputs of the sequence controller ab are connected to the enable inputs en of the first and second memories s1, s2 and of the first and second output registers r1, r2 and to the control inputs of the two switches us1, us2.
The sequence controller ab controls these subcircuits as follows. A red-minus-luminance signal value yr1 and a blue-minus-luminance signal value yb1 occurring at an intermediate value of the hold time are read into the memories s1 and s2, respectively. This intermediate value of the hold time lies preferably in the middle of the hold time. Furthermore, the sequence controller causes the contents of the memories s1 and s2 to be transferred via the associated switches us1 and us2 into the associated output registers r1 and r2, respectively, at the corresponding intermediate value, preferably one-half, of the steepened leading edge, while at all times other than the instant of the intermediate value of the steepened leading edge, the inputs of the associated output registers are connected to the outputs of the delay elements v1 and v2, respectively.
The block diagram of FIG. 2 shows an improved version of the arrangement of FIG. 1. The improvement is that the first and second memories s1 and s2 of FIG. 1 have been supplemented with the third and fourth memories s3 and s4, respectively, each of which is connected in parallel with the associated memory, and that the two switches us1 and us2 of FIG. 1 have been expanded into multiposition switches us1' and us2' each having one additional input connected to the output of the third memory s3 and the output of the fourth memory s4, respectively. This improved portion of FIG. 2 concerns the sequence controller ab of FIG. 1. In FIG. 2, the latter consists of the counter c2, which counts the pulses of the clock signal s, the decoder dc, and the AND gate u2. The start input st of the counter c2 is connected to the output of the OR gate og, whereas the stop input sp is controlled by the decoder dc. The digital signal hz is fed to the decoder dc, cf. FIG. 1.
The counts of the counter c2 are decoded by reading the red- and blue-minus-luminance signal values occurring at the end of the first third of the hold time, i.e., the values yr1' and yb1', into the first memory s1 and the second memory s2, respectively, and the red- and blue-minus-luminance signal values occurring at the end of the second third of the hold time, i.e., the values yr2 and yb2, into the third memory s3 and the fourth memory s4, respectively. At the end of the first third and second third, respectively, of the steepened leading edge, the contents of the memories s1 and s3, respectively, are transferred through the switch us1' into the output register r1, and at the end of the first third and second third, respectively of that edge, the contents of the memories s2 and s4, respectively, are transferred through the switch us2' into the output register r2. The inputs of the two outputs registers are connected to the outputs of the first and second delay elements v1 and v2, respectively, except at the end of the first and second thirds, respectively, of the steepened leading edge.
The clock signal f is applied to one of the inputs of the AND gate u2, whose other input is connected to one of the outputs of the decoder dc, and whose output is coupled to the enable inputs en of the first and second output registers r1, r2.
The block diagram of FIG. 3 shows a preferred embodiment of the circuit of the slope detectors fs1, fs2. The input for the color-difference signal yr, yb is followed by the series combination of the first digital differentiator d1, the digital absolute-value stage bb, and the minuend input m of the first digital comparator k1. The subtrahend input s of the latter is presented with the digital signal corresponding to the amplitude threshold value, the signal ta. The absolute-value stage bb delivers digital values which are unsigned, i.e., which have no sign bit, for example.
Accordingly, the absolute-value stage bb contains a subcircuit which changes negative binary numbers in, e.g., one's or two's complement representation into the corresponding positive binary number, i.e., a recomplementer.
The term "comparator" as used herein means a digital circuit which compares the two digital signals appearing at the two inputs to determine which of the two signals is greater. Since, purely formally, such a comparison is closer to the arithmetic operation of subtraction than to that of addition although the concrete internal circuitry of such comparators is more similar to that of adders than to that of subtracters, the two inputs of the comparator are called "minuend input" and "subtrahend input" as in the case of a subtracter. The three logic output signals are "minuend greater than subtrahend", "subtrahend greater than minuend", and "minuend equal to subtrahend". Thus, in positive logic, the more positive logic level will appear at the minuend-greater-than-subtrahend output of a comparator if and as long as the minuend is greater than the subtrahend. If needed, the more negative logic level appearing at this output may serve to signal the "minuend-smaller-than-subtrahend" function, i.e., it is also possible to use negative logic.
In the slope detector of FIG. 3, the enable input eb of the first clock-pulse counter c1 and one of the inputs of the second digital differentiator d2 are connected to the minuend-greater-than-subtrahend output ms of the first comparator k1. The count outputs of the first counter c1 are coupled to the input of the fifth memory s5, which has its output connected to the minuend input m of the second digital comparator k2. The subtrahend input s of the latter is presented with a digital signal corresponding to the time threshold value, the signal tt.
The reset input re of the first counter c1, the enable input en of the fifth memory s5, and the first input of the first AND gate u1 are connected to the output of the second differentiator d2. The subtrahend-greater-than-minuend output sm of the second comparator k2 is connected to the second input of the second AND gate u2, whose output is fed to the OR gate of FIGS. 1 or 2. The subcircuits d1, bb, k1, d2, and, as mentioned above, c1 are clocked by the clock signal f.
FIGS. 4a-c and 5a and b serve to illustrate the operation of the circuit arrangement in accordance with the invention. FIG. 4a shows the assumed shape of one of the two color-difference signals yr, yb; it should be noted that, in those figures, the representation commonly used for analog signals has been chosen for simplicity. FIG. 4b shows the output signal of the absolute-value stage bb and the amplitude threshold value corresponding to the digital signal ta. Also shown is the time threshold value corresponding to the digital signal tt. FIG. 4c shows the shape of the assumed color-difference signal of FIG. 4a as it appears at the output of the output register r1, r2 of FIG. 1 or FIG. 2. A comparison between FIGS. 4a and 4c shows that the last edge on the right has been steepened since, during this edge, both the amplitude threshold value is exceeded and the time threshold value is not reached (cf. the use of the subtrahend-greater-than-minuend output sm of the second comparator k2), the steepening function becomes effective. The first comparator k1 provides a signal at the minuend-greater-than-subtrahend output ms as long as the output signal of the absolute-value stage bb is greater than the amplitude threshold value. During that time, the first counter c1 can count the clock pulses until it is reset by a signal derived by the second differentiator d2 from the trailing edge of the output signal of the first comparator k1. The previous count of the counter c1 is transferred into the fifth memory s5 and compared with the time threshold value by the second comparator k2. If the time threshold value is greater than the period measured by the counter c1, the above-mentioned function will be initiated.
FIGS. 5a and 5b serve to explain how the steepened edge is formed. Curve a of FIG. 5a shows a slowly rising edge used for the explanation. The distances between the points in curves a and b of FIG. 5a are to illustrate the period of the clock signal f. FIG. 5b shows the waveform at the enable inputs en of the output registers r1, r2. At the arrow shown on the left between curves a and b of FIG. 5a, the signal periodically applied to these inputs at the repetition rate of the clock signal f is stopped, so to speak, so that no signals are transferred to the output registers r1, r2 over several clock periods, but the signal read in at the "clocking" of the enable inputs en is retained in those registers. After the "clocking" of the enable inputs of the output registers r1, r2 has resumed at the beginning of the edge to be steepened, the signal values yr1', yb1' and yr2, yb2 read into the memories s1, s2 and s3, s4 at the end of the first third and the second third, respectively, of the slowly rising edge of curve a of FIG. 5a are transferred into the output registers r1, r2 at the end of the first third and the second third, respectively, of this edge. The arrow shown on the right between curves a and b of FIG. 5a is to indicate that, at the end of the slowly rising edge of curve a, the steepened edge of curve b has reached the desired signal value.
The period for which the "clocking" of the enable inputs en of the output registers r1, r2 is "interrupted" is equal to the duration of the digital signal hz fed to the sequence controller ab of FIG. 1 or to the decoder dc of FIG. 2.
The circuit arrangement in accordance with the invention can be readily implemented in monolithic integrated form. As it uses exclusively digital circuits, it is especially suited for integration using insulated-gate field-effect transistors, i.e., MOS technology.
VCU 2133 Video Codec UNIT
High-speed cod
er/decoder IC for analog-to-digital and di-gital-to-analog conversion of the video signal in digital TV
receivers based on the DIGIT 2000 concept. The VCU 2133
is a VLSI circuit in Cl technology, housed in a 40-pin Dil
plastic package. One single silicon chip combines the fol-
lowing functions and circuit details (Fig. 1):
- two input video amplifiers
- one A/D converter for the composite video signal
- the noise inverter
- one D/A converter for the luminance signal
- two D/A converters for the color difference signals
- one RGB matrix for converting the color difference sig-
nals and the luminance signal into RGB signals
- three RGB output amplifiers
- programmable auxiliary circuits for blanking, brightness
adjustment and picture tube alignment
- additional clamped RGB inputs for text and other analog
RGB signals
- programmable beam current limiting
1. Functional Description
The VCU 2133 Video Codec is intended for converting the
analog composite video signal from the video demodulator
into a digital signal. The latter is further processed
digitally
in the VPU 2203 Video Processor and in the DPU 2553 De-
flection Processor. After processing in the VPU 2203 (color
demodulation, PAL compensation, etc.), the VPU‘s digital
output signals (luminance and color difference) are recon-
verted into analog signals in the VCU 2133. From these an-
alog signals are derived the RGB signals by means of the
RGB matrix, and, after amplification in the integrated RGB
amplifiers, the RGB signals drive the RGB output amplifiers
of the color T\/ set.
For TV receivers using the NTSC standard the VPU 2203
may be replaced by the CVPU 2233 Comb Filter Video Pro-
cessor which is pin-compatible with the VPU 2203, but of-
fers better video performance. In the case of SECAM, the
SPU 2220 SECAM Chroma Processor must be connected
in parallel to the VPU 2203 for chroma processing, while
the luma processing remains inthe VPU 2203.
In a more sophisticated CTV receiver according to the Dl-
GIT 2000 concept, after the VPU Video Processor may be
placed the DTI 2223 Digital Transient Improvement Proces-
sor which serves for sharpening color transients on the
screen. The output signals of the DTI are fed to the VCU’s
luma and chroma inputs. To achieve the desired transient
improvement, the R-Y and B-Y D/A converters of the VCU
must be stopped for a certain time which is done by the
hold pulse supplied by the DTI and fed to the Reset pin 23
of the VCU. The pulse detector following this pin seperates
the (capacitively-coupled) hold pulse from the reset signal.
In addition, the VCU 2133 carries out the functions:
- brightness adjustment
- automatic CRT spot-cutoff control (black level)
- white balance control and beam current limiting
Further, the VCU 2133 offers direct inputs for text or other
analog RGB signals including adjustment of brightness and
contrast for these signals.
The RGB matrix and RGB amplifier circuits integrated in
the VCU 2133 are analog. The CRT spot-cutoff control is
carried out via the RGB amplifiers’ bias, and the white bal-
ance control is accomplished by varying the gain of these
amplifiers. The VCU 2133 is clocked by a 17.7 or 14.3 MHz
clock signal supplied by the MCU 2632 Clock Generator IC.
1.1. The A/D Converter with Input Amplifiers and Bit
Enlargement
The video signal is input to the VCU 2133 via pins 35 and 37
which are intended for normal TV video signal (pin 35) and
for VCR or SCART video signal (pin 37) respectively. The
video amplifier whose action is required, is activated by the
CCU 2030, CCU 2050 or CCU 2070 via the IM bus by soft-
ware. The amplification of both video amplifiers is doubled
during the undelayed horizontal blanking pulse (at pin 36)
in order to obtain a higher digital resolution of the color
synchronization signal (burst). At D 2-MAC reception, the
doubled gain is switched off by means of bit p = 1 (Fig. 8).
The A/D converter is of the flash type, a circuit of 2" com-
parators connected in parallel. This means that the number
of comparators must be doubled if one additional bit is
needed. Thus it is important to have as few bits as possi-
ble. For a slowly varying video signal, 8 bits are required.
ln
order to achieve an 8-bit picture resolution using a 7-bit
converter, a trick is used: during every other line the refer-
ence voltage of the A/D converter is changed by an
amount corresponding to one half of the least significant
bit. ln this procedure, a grey value located between two 7-
bit steps is converted to the next lower value during one
line and to the next higher value during the next line. The
two grey values on the screen are averaged by the viewer’s
eye, thus producing the impression of grey values with
8-bit resolution. Synchronously to the changing reference
voltage of the A/D converter, to the output signal of the Y
D/A converter is added a half-bit step every second line.
The bit enlargement just described must be switched off in
the case of using the D2-MAC standard (q = 1 and r = 1
in Fig. 8). ln the case of using the comb filter CVPU instead
of the VPU, the half-bit adding in the Y D/A converter must
be switched off (r = 1 in Fig. 8).
The A/D converter’s sampling frequency is 17.7 MHZ for
PAL and 14.3 MHz for NTSC, the clock being supplied by
the MCU 2632 Clock Generator IC which is common to all
circuits for the digital T\/ system. The converter’s resolu-
tion is 1/2 LSB of 8 bits. Its output signal is Gray-coded to
eliminate spikes and glitches resulting from different com-
parator speeds or from the coder itself. The output is fed to
the VPU 2203 and to the DPU 2553 in parallel form.
1.2. The Noise Inverter
The digitized composite video signal passes the noise in-
verter circuit before it is put out to the VPU 2203 and to the
DPU 2553. The noise inverter serves for suppressing bright
spots on the screen which can be generated by noise
VCU 2133
pulses, p. ex. produced by ignition sparks of cars etc. The
function of the noise inverter can be seen in Fig. 2. The
maximum white level corresponds with step 126 of the A/D
converter’s output signal (that means a voltage of 7 V at
pin 35). lf, due to an unwanted pulse on the composite
video signal, the voltage reaches 7.5 V (what means step
127 in digital) or more, the signal level is reduced by such
an amount, that a medium grey is obtained on the screen
(about 40 lFiE). The noise inverter circuit can be switched
off by software (address 16 in the VPU 2203, see there).
1.3. The Luminance D/A Converter (Y)
After h
aving been processed in the VPU 2203 (color de-modulation, PAL compensation, etc.), the different parts of
the digitized video signal are fed back to the VCU 2133 for
further processing to drive the RGB output amplifiers. The
luminance signal (Y) is routed from the VPU’s contrast mul-
tiplier to the Y D/A converter in the VCU 2133 in the form of
a parallel 8-bit signal with a resolution of 1/2 LSB of 9
bits.
This bit range provides a sufficient signal range for contrast
as well as positive and negative overshoot caused by the
peaking filter (see Fig. 3 and Data Sheet VPU 2203).
The luminance D/A converter is designed as an R-2R lad-
der network. lt is clocked with the 17.7 or the 14.3 MHz
clock signal applied to pin 22. The cutoff frequency of the
luminance signal is determined by the clock frequency.
1.4. The D/A Converters for the Color Difference Signals
R-Y and B-Y
ln order to save output pins at the VPU 2203 and input pins
at the VCU 2133 as well as connection lines, the two digital
color difference signals R-Y and B-Y are transferred in time
multiplex operation. This is possible because these signals’
bandwidth is only 1 MHZ and the clock is a 17.7 or 14.3
MHz signal.
The two 8-bit D/A converters R-Y and B-Y are also built as
R-2R ladder networks. They are clocked with ‘A clock fre-
quency, but the clock for the multiplex data transfer is 17.7
or 14.3 MHz. Four times 4 bits are transferred sequentially,
giving a total of 16 bits. A sync signal coordinates the
multi-
plex operations in both the VCU 2133 and the VPU 2203.
Thus, only four lines are needed for 16 bits. Fig. 4 shows
the timing diagram of the data transfer described.
ln a CTV receiver with digital transient improvement (DTI
2223), the R-Y and B-Y D/A converters are stopped by the
hold pulse supplied by the DTI, and their output signal is
kept constant for the duration of the hold pulse. Thereafter,
the output signal jumps to the new value, as described in
the DTl’s data sheet.
Fig. 4:
Timing diagram of the multiplex data transfer of the chroma
channel between VPU 2203, VCU 2133 and SPU 2220
a) main clock signal QSM
b) valid data out of the VCU 2133’s video A/D converter.
AIAD is the delay time of this converter, about 40 ns.
c) valid data out of the VPU 2203.
d) MUX data transfer of the chroma signals from VPU 2203
to VCU 2133, upper line: sync pulse from pin 27 VPU to
pin 21 VCU during sync time in vertical blanking time,
see Fig. 8; lower line: valid data from pins 27 to 30
(VPU) to pins 18 to 21 (VCU)
1.5. The RGB Matrix and the RGB Output Amplifiers
ln the RGB matrix, the signals Y, R-Y and B-Y are dema-
trixed, the reduction coefficients of 0.88 and 0.49 being tak-
en into account. In addition, the matrix is supplied with a
signal produced by an 8-bit D/A converter for setting the
brightness of the picture. The brightness adjustment range
corresponds to 1/2 of the luminance signal range (see Fig.
3). It can be covered in 255 steps. The brightness is set by
commands fed from the CCU 2030, CCU 2050 or CCU 2070
Central Control Unit to the VPU 2203 via the IM bus.
There are available four different matrices: standard PAL,
matrix 2, 3 and 4, the latter for foreign markets. 'The re-
quired matrix must be mask-programmed during produc-
tion. The matrices are shown in Table 1, based on the for-
mulas:
R = r1~(R-Y)+ l'2~(B-Y) +Y
G = Q1-(Ft-Y)+ Q2 - (B-Y) +Y
B = b1-(Ft-Y)+ bg - (B-Y) +Y
The three RGB output amplifiers are impedance converters
having a low output impedance, an output voltage swing of
6 V (p-p), thereof 3 V for the video part and 3 V for bright-
ness and dark signal. The output current is 4 mA. Fig. 5
shows the recommended video output stage configuration.
For the purpose of white-balance control, the amplification
factor of each output amplifier can be varied stepwise in
127 steps (7 bits) by a factor of 1 to 2. Further, the CRT
spot-cutoff control is accomplished via these amplifiers’ bi-
as by adding the output signal of an 8-bit D/A converter to
the intelligence signal. The amplitude of the output signal
corresponds to one half of the luminance range. The eight
bits make it possible to adjust the dark voltage in 0.5 %
steps. By means of this circuit, the factory-set values for
the dark currents can be maintained and aging of the pic-
ture tube compensated.
1.6. The Beam Current and Peak Beam Current Limiter
The principle of this circuitry may be explained by means of
Fig. 6. Both facilities are carried out via pin 34 of the VCU
2133. For beam current limiting and peak beam current li-
miting, contrast and brightness are reduced by reducing
the reference voltages for the D/A converters Y, Ft-Y and
B-Y. At a voltage of more than +4 V at pin 34, contrast and
brightness are not affected. In the range of +4 V to +3 V,
the contrast is continuously reduced. At +3 V, the original
contrast is reduced to a programmable level, which is set
by the bits of address 16 of the VPU as shown in Table 2. A
further decrease of the voltage merely reduces brightness,
the contrast remains unchanged. At 2 V, the brightness is
reduced to zero. At voltages lower than 2 V, the output
goes to ultra black. This is provided for security purposes.
The beam current limiting is sensed at the ground end of
the EHT circuit, where the average value of the beam cur-
rent produces a certain voltage drop across a resistor in-
serted between EHT circuit and ground. The peak beam
current limiting can be provided additionally to avoid
“blooming” of white spots or letters on the screen. For
this, a fast peak current limitation is needed which is
sensed by three sensing transistors inserted between the
RGB amplifiers and the cathodes of the picture tube. One
of these three transistors is shown in Fig. 6. The sum of the
picture tube’s three cathode currents produces a voltage
drop across resistor R1. If this voltage exceeds that gen-
erated by the divider R2, B3 plus the base emitter voltage
of T2, this transistor will be turned on and the voltage at
pin
34 of the VCU 2133 sharply reduced. Time constants for
both beam current
limiting and peak beam current limitingcan be set by the capacitors C1 and C2.
1.7. The Blanking Circuit
The blanking circuit coordinates blanking during vertical
and horizontal flyback. During the latter, the VCU 2133's
output amplifiers are switched to “ultra black”. Such
switching is different during vertical flyback, however, be-
cause at this time the measurements for picture tube align-
ment are Carried out. During vertical flyback, only the ca-
thode to be measured is switched to “black” during mea-
suring time, the other two are at ultra black so that only the
dark current of one cathode is measured at the same time.
For measuring the leakage current, all three cathodes are
switched to ultra black.
The sequence described is controlled by three code bits
contained in a train of 72 bits which is transferred from the
VPU 2203 to the VCU 2133 during each vertical blanking in-
terval. This transfer starts with the vertical blanking pulse.
During the transfer all three cathodes of the picture tube
are biased to ultra black. In the same manner, the white-
balance control is done.
The blanking circuit is controlled by two pulse combina-
tions supplied by the DPU 2553 Deflection Processor
(“sandcastle pulses"). Pin 39 of the VCU 2133 receives the
combined vertical blanking and delayed horizontal blanking
pulse from pin 22 of the DPU (Fig. 7 b), and pin 36 of the
VCU gets the combined undelayed horizontal blanking and
color key pulse from pin 19 of the DPU (Fig. 7 a). The two
outputs of the DPU are tristate-controlled, supplying the
output levels max. 0.4 V (low), min. 4.0 V (high), or high-im-
pedance, whereby the signal level in the high-impedance
mode is determined by the VCU’s input configuration, a
voltage divider of 3.6 KS! and 5 KQ between the +5 V sup-
ply and ground, to 2_8 V. The VCU’s input amplifier has two
thresholds of 2.0 V and 3.4 V for detecting the three levels
of the combined pulses. ln this way, two times two pulses
are transferred via only two lines.
1.8. The Circuitry for Picture Tube Alignment
During vertical flyback, a number of measurements are tak-
en and data is exchanged between the VCU 2133, the VPU
2203 and the CCU 2030 or CCU 2050. These measure-
ments deal with picture tube alignment, as white level and
dark current adjustment, and with the photo current sup-
plied by a photo resistor (Fig. 5) which serves for adapting
Fig. 8:
Data sequence during the transfer of test results from the
VPU 2203 to the VCU 2133. Nine Bytes are transferred, in
each case the LSB first. These 9 Bytes, 8 bits each, coin-
cide with the 72 pulses of 4.4 MHz that are transferred dur-
ing vertical flyback from pin 27 of the VPU 2203 to pin 21 of
the VCU 2133 (see Fig. 9).
l and mi beam current limiter range
l<: noise inverter on/off
n: video input switching bit
S: SECAM chroma sync bit; S = 1 means that the chroma
demultiplexer is synchronized every line. The switch-over
time from C0 to demux counter begins with the end of the
undelayed horizontal blanking pulse and remains valid for a
time of 12 Q M clock periods.
6
the contrast of the picture to the light in the room where
the TV set is operated. The circuitry for transferring the
pic-
ture tube alignment data, the sensed beam currents and
the photo current is clocked in compliance with the VPU
2203 by the vertical blanking pulse and the color key pulse.
To carry out the measurements, a quadruple cycle is pro-
vided (see Table 3). The timing of the data transfer during
the vertical flyback is shown in Fig. 9, and Fig. 8 shows the
data sequence during that data transfer.
Ft, G, B: code bits
p=1; no doubled gain in the input amplifier during horizon-
tal blanking (see section 1.1.)
q=1: no changing of the A/D converter’s reference vol-
tage during every other line (see section 1.1.)
r=1: when operating with the DMA D2-MAC decoder or
the CVPU comb filter video processor, the adding of
a step of ‘/2 LSB to the output signal of the Y D/A
converter is switched off (see section 1.1.).
s=1; the blankirig pulse in the analog video output signal
at pins 26 to 28 is switched off, as is required in
stand-alone applications.
1.9. The Additional RGB Inputs
The three additional analog RGB inputs are provided for
inputting text or other analog RGB signals. They are con-
nected to fast voltage-to-current converters whose output
current can be altered in 64 steps (6 bits) for contrast set-
ting between 100 % and 30 %. The three inputs are
clamped to a DC black level which corresponds to the level
of 31 steps in the luminance channel, by means of the color
key pulse. So, the same brightness level is achieved for
normal and for external RGB signals. The output currents
ofthe converters are then fed to the three RGB output am-
plifiers. Switchover to the external video signal is also
fast.
1.10. The Reset Circuit and Pulse Detector
The reset pulse produced by the external reset RC network
in common for the whole DIGIT 2000 system, switches the
RGB outputs to ultra black during the power-on routine of
the TV set. At other times, high level must be applied to the
reset input pin 23.
There is an additional facility with pin 23 which is used only
in conjunction with the DTl 2223 Digital Transient Improve-
ment Processor. The hold pulse produced by the latter
which serves for stopping the R-Y and B-Y D/A converters,
is also fed to pin 23, capacitively-coupled. The pulse detec-
tor responds on positive pulses which exceed the 5 V sup-
ply by about 1 V. The two DACs are stopped as long as the
hold pulse lasts, and supply a constant output signal of the
amplitude at the begin of the hold pulse.
5. Description of the Connections and the Signals
Pins 1, 9, and 25 - Supply Voltage, +5 V
The supply voltage is +5 V. Pins 1 and 25 supply the ana-
log part and must be filtered separately.
Pins 2 to 8 - Outputs V0 to V6
Via these pins the VCU 2133 supplies the digitized video
signal in a parallel 7-bit Gray code to the VPU 2203 and the
DPU 2553. The output configuration is shown in Fig. 16.
Pins 10 to 17 - Inputs L7 to L0
Fig. 17 shows these inputs’ configuration. Via these pins,
the VCU 2133 receives the digital luminance signal from the
VPU 2203 in a paraliel 8-bit code.
Pins 18 to 21 - Inputs C0 to C3
Via these inputs, whose circuitry and data correspond to
those of pins 10 to 17, the VCU 2133 is fed with the digi-
tized color difference signals R-Y and B-Y and with the
control and alignment signals described in section 1.8., in
multiplex operation. Pin 21 is additionally used for the
multi-
plex sync signal.
Pin 22 - QSM Main Clock Input
Via this pin, whose circuitry is shown in Fig. 18, the VCU
2133 is supplied with the clock signal QSM produced by the
MCU 2600 or MCU 2632 Clock Generator IC. The clock fre-
quency is 17.7 MHz for PAL and SECAM and 14.3 MHz for
NTSC. The clock signal must be DC-coupled.
Pin 23 - Reset and Hold Pulse Input (Fig. 19)
Via this pin, the VCU 2133 is supplied with the reset and
hold signals which are supplied by pin 21 of the DTI 2223
Digital Transient Improvement Processor for stopping the
R-Y and B-Y D/A converters, and for Reset.
Pins 24 and 29 - Analog Ground, 0
These pins serve as ground connections for the supply and
for the analog signals (GND pin 24 for RGB).
Pins 26 to 28 - RGB Outputs
These three analog outputs deliver an analog signal suit-
able for driving the RGB output transistors. Their diagram
is shown in Fig. 20. The output voltage swing is 6 V total,
3 V for the black-to-white signal and 3 V for adjusting
the brightness and the black level.
Pins 30 to 32 - Additional Analog Inputs R, G and B
Fig. 21 shows the configuration of these inputs. They serve
to feed analog RGB signals, for example for Teletext or si-
milar applications, and they are clamped during the color
key pulse. At a 1 V input, full brightness is reached. The
bandwidth extends from 0 to 8 MHz.
Pin 33 - Fast Switching Input
This input is connected as shown in Fig. 22. It ser\/es for
fast switchover of the video channel between an internally-
produced video signal and an externally-applied video sig-
nal via pins 30 to 32. With 0 V at pin 33, the RGB outputs
will supply the internal video signal, and at a 1 V input
level,
the RGB outputs are switched to the external video signal.
Bandwidth is 0 to 4 MHz, and input impedance 1 KQ mini-
mum.
Pin 34 - Beam Current Limiter Input
The diagram of pin 34 is shown in Fig. 25. The input voltage
may be between +5 V and 0 V. The input impedance is 100
kQ. The function of pin 34 is described in section 1.6.
Pin 35 - Composite Video Signal Input 1
To fully drive the video A/D converter the following ampli-
tudes are required at pin 35: +5 V = sync pulse top level,
all bits low; +7 V = peak white, all bits high. Fig. 24 shows
the configuration of pin 35.
Pin 36 - Undelayed Horizontal Blanking and Color Key
Pulse Input
The circuitry of this pin is shown in Fig. 23. Pin 36 receives
the combined undelayed horizontal blanking and color key
pulse which are “sandcastled” and are supplied by pin 19
of the DPU 2553 Deflection Processor. During the undelay-
ed horizontal blanking pulse, the input amplifiers’ gain is
doubled, and the bit enlargement circuit is also switched
by this pulse, and the counter for the data transmission
gap started. The color key pulse is used for clamping the
RGB inputs pins 30 to 32.
Pin 37 - Composite Video Signal Input 2
This pin has the same function and properties as pin 35,
except the gain of the input amplifier which is twice the
gain as that of the amplifier at pin 35. This means an input
voltage range of +5 V to +6 V.
Pin 38 - Supply Voltage, +12 V »
The 12 V supply is needed for certain circuit parts to obtain
the required input or output voltage range, as the video in-
put and the RGB outputs (see Figs. 20 and 24).
Pin 39 - Vertical Blanking and Delayed Horizontal Blanking
Input
This pin receives the combined vertical blanking and delay-
ed horizontal blanking. pulse from pin 22 of the DPU 2553
Deflection Processor. Both pulses are “sandcastled” so
that only one connection is needed for the transfer of two
pulses. These two pulses are separated in the input circui-
try of the VCU 2133, and are used for blanking the picture
during vertical and horizontal flyback. Fig. 23 shows the cir-
cuitry of pin 39.
Pin 40 - Digital Ground, O
This pin is used as GND connection in conjunction with the
pins 2 to 8 and 10 to 21 which carry digital signals.
DPU 2553, DPU 2554 Deflection Processors UNITNote: lf not otherwise designated, the pin numbers
mentioned refer to the 40-pin Dil package.
1. Introduction
These programmable VLSI circuits in n-channel mOS
technology carry out the deflection functions in digital
colorTV receivers based onthe DiGiT 2000 system and
are also suitable for text and D2~mAC application. The
three types are basically identical, but are modified ac-
cording to the intended application:
DPU 2553
normal-scan horizontal deflection, standard CTV re-
ceivers, also equipped with Teletext and D2-mAC fa-
cility
DPU 2554
double-scan horizontal deflection, for CTV receivers
equipped with double-frequency horizontal deflection
and double-~frequency vertical deflection for improved
picture quality. At power-up, this version starts with
double horizontal frequency.
1.1. General Description
The DPU 2553/54 Deflection Processors contain the fol-
lowing circuit functions on one single silicon chip:
- video clamping
- horizontal and vertical sync separation
~ horizontal synchronization
- normal horizontal deflection
-east-west correction, also for flat-screen picture
tubes
- vertical synchronization
- normal vertical deflection
~ sawtooth generation
-text display mode with increased deflection frequen-
cies (18.7 kHz horizontal and 60 Hz vertical)
- D2-mAC operation mode
and for DPU 2554 only:
- double-scan horizontal deflection
- normal and double-scan vertical deflection
ln this data sheet, all information given for double~scan
mode is available with the DPU 2554 only. Type DPU
2553 starts the horizontal deflection with 15.5 kHz ac-
cording to the normal TV standard, whereas type DPU
2554 starts with 31 kHz according to the double-scan
system.
The following characteristics are programmable:
~ selection ofthe TV standard (PAL, D2-mAC or NTSC)
- selection ofthe deflection standard (Teletext, horizon-
tal and vertical double-scan, and normal scan)
- filter time»constant for horizontal synchronization
- vertical amplitude, S correction, and vertical position
for in-line, flat-screen and Trinitron picture tubes
- east-west parabola, horizontal width, and trapezoidal
correction for in-line, flat-screen and Trinitron picture
tubes
- switchover characteristics between the different syn-
chronization modes
~characteristic of the synchronism detector for PLL
switching and muting
1.2. Environment
Fig. 1-1 showsthe simplified block diagram ofthe video
and deflection section of a digital TV receiver based on
the DIGIT 2000 system. The analog video signal derived
from the video detector is digitized in the VCU 2133,
VCU 2134 or VCU 2136 Video Codec and supplied in a
parallel 7 bit Gray code. This digital video signal is fed to
the video section (PVPU, CVPU, SPU and DmA) and to
the DPU 2553/54 Deflection Processorwhich carries out
all functions required in conjunction with deflection, from
sync separation to the control of the deflection power
stages, as described in this data sheet.
3. Functional Description
3.1. Block Diagram
The DPU 2553 and DPU 2554 Deflection Processors
perform all tasks associated with deflection in TV sets;
- sync separation
- generation and synchronization of the horizontal and
the vertical deflection frequencies
-the various eastevvest corrections
- vertical savvtooth generation including S correction
as described hereafter. The DPU communicates, viathe
bidirectional serial lm bus, with the CCU 2050 or CCU
2070 Central Control Unit and, via this bus, is supplied
with the picture-correction alignment information stored
in the mDA 2062 EEPROM during set production, vvhen
the set is turned on. The DPU is normally clocked with
a trapezoidal 17.734 mHz (PAL or SECAm), or 14.3 mhz
(NTSC) or 20.25 mHz (D2-mAC) clock signal supplied
by the mCU 2600 or mCU 2632 Clock Generator IC.
The functional diagram of the DPU is shovvn in Fig. 3-1.
3.2. The Video Clamping Circuit and the Sync Pulse
Separation Circuit
The digitized composite video signal delivered as a 7»bit
parallel signal by the VCU 2133, VCU 2134 or VCU 2136
Video Codec is first noise-filtered by a 1 mHz digital lovv-
pass filter and, to improve the noise immunity ofthe
clamping circuit, is additionally filtered by a 0.2 mHz low-
pass filter before being routed to the minimum and back
porch level detectors (Fig. 3-3).
The DPU has tvvo different clamping outputs, no. 1 and
No. 2, one of vvhich supplies the required clamping
pulses to the video input of the VCU as shovvn in Fig.
3-1. The following values forthe clamping circuit apply
for Video Amp. l. since the gain of Video Amp. ll istwice
th at of Video Amp l, all clamping and signal levels of Vid-
eo Amp ll are halt those of Video Amp l referred to +5 V.
Afterthe TV set is switched on,thevideo clamping circuit
first of all ensures by means of horizontal-frequency
current pulses from the clamping output of the DPU to
the coupling capacitor of the analog composite video
signal, that the video signal atthe VCU’s input is optimal-
ly biased for the operation range of the A/D converter of
5 to 7 V. For this, the sync top level is digitally measured
and set to a constant level of 5.125 V by these current
pulses. The horizontal and vertical sync pulses are novv
separated by a fixed separation level of 5.250 V so that
the horizontal synchronization can lock to the correct
phase (see section 3.3. and Figs. 3-2 and 3-3).
vvith the color key pulse which is now present in syn-
chronism with the composite video signal, the video
clamping circuit measures the DC voltage level of the
porch and by means of the pulses from pin 21 (or pin4),
sets the DC level ofthe porch at a constant 5.5 V (5.25 V
for Video Amp ll). This level is also the reference black
to Video Processorffeletext Processor, D2-MAC Processor tc.
level for the PVPU 2204 or CvPU 2270 Video Proces-
sors.
When horizontal synchronization is achieved, the slice
level for the sync pulses is set to 50 % of the sync pulse
amplitude by averaging sync top and black level. This
ensures optimum pulse separation, even with small
sync pulse amplitudes (see application notes, section
4).
3.3. Horizontal Synchronization
Two operating modes are provided for in horizontal syn-
chronization. The choice of mode depends on whether
or not the Tv station is transmitting a standard PAL or
NTSC signal, in which there is a fixed ratio between color
subcarrier frequency and horizontal frequency. ln the
first case we speak of “color-locked” operation and in
the second case of “non-color-locked” operation (e.g.
black-and-white programs). Switching between thetwo
modes is performed automatically by the standard sig-
nal detector.
3.3.1. Non-Color-Locked Operation
ln the non»locked mode,which is needed in the situation
where there is no standard fixed ratio between the color
subcarrier frequency and the horizontal frequency ofthe
transmitter, the horizontal frequency is produced by subdemding the clock frequency (1 7.7 mHz for PAL and SECAM, 14.3
mHz for NTSC) in the programmable fre-
quency dmder (Fig. 3-4) until the correct horizontal
frequency is obtained. The correct adjustment of fre-
quency and phase is ensured by phase comparator l.
This determines the frequency and phase deviation by
means of a digital phase comparison between the sepa-
rated horizontal sync pulses and the output signal of the
programmable dmder and corrects the dmder accordingly. For
optimum adjustment of phase iitter, capture
behavior and transient response of the horizontal PLL
circuit, the measured phase deviation is filtered in a digi-
lowpass filter (PLL phase filter). ln the case of non-
OZMH synchronized horizontal PLL, this filter is set to
wideband PLL response with a pull-in range of 1800 Hz. if the
- sync sync PLL circuit is locked, the PLL filter is
automatically switched to narrow-band response by an internal
synchronism detector in order to limit the phase jitter to a
minimum, even in the case of weak and noisy signals.
A calculator circuit in phase comparator , which analyzes the
edges of the horizontal sync pulses, increases
the resolution of the phase measurement from 56 ns at
Fig. 3-3: Principle ofvideo clamping and pulse separa- 17.7
mHz clock frequency to approx. 6 ns, or from 70 ns
NON at 14.3 MHz clock frequency to approx. 2.2 ns.
The various key and gating pulses such as the color key
pulse (tKe(,), the normal-scan (1 H) and double-scan
(2H) horizontal blanking pulse (tAZ(/) and the 1 H hori-
zontal undelayed gating pulse (t/(Z) are derived from the
output signals ofthe programmable dmder and an addi-
tional counter forthe2H signals and the 1 H and 2H skew
data output. These pulses retain a fixed phase position
with respect to the 1 H inputvideo signal andthe double-
scan output video signal from the CvPU 2270 Video Pro-
cessor
Forthe purpose of equalizing phase changes in the hori-
zontal output stage due to switching response toler-
ances or video influence, a second phase control loop
is used which generates the horizontal output pulse at
pin 31 to drivethe horizontal output stage. ln phase com-
parator li (Fig. 3~4), the phase difference between the
output signal of the programmable dmder and the lead-
ing edge (or the center) of the horizontal flyback pulse
(pin 23) is measured by means of a balanced gate delay
line. The deviation from the desired phase difference is
used as an input to an adder. ln this, the information on
the horizontal frequency derived from phase com-
parator l is added to the phase deviation originating form
phase comparator ll. The result of this addition controls
a digital on-chip sinewave generator (about 1 mHz)
which acts as a phase shifter with a phase resolution of
1/128 of one main clock period
By means of control loop ll the horizontal output pulse
(pin 31) is shifted such that the horizontal flyback pulse
(pin 23) acquiresthe desired phase position with respect
to the output signal of the programmable dmder which,
in turn, due to phase comparator l, retains a fixed phase
position with respect to the video signal. The horizontal
output pulse itself is generated by dmding the frequency
ofthe 1 mHz sinewave oscillator by a fixed ratio of 64 in
the case of norm al scan and of 32 in the case of double-
scan operation.
3.3.2. Color-Locked Operation
When in the color~locked operating mode, after the
phase position has been set in the non-color-locked
mode, the programmable dmder is set to the standard
dmsion ratio (1135:1 for PAL, 91O:1 for NTSC) and
phase comparator is disconnected so that interfering
pulses and noise cannot influence the horizontal deflec-
tion. Because phase comparator ll is still connected,
phase errors ofthe horizontal output stage are also cor-
rected in the color»locKed operating mode. The stan-
dard signal detector is so designed that it only switches
to color-locked operation when the ratio between color
subcarrier frequency and horizontal frequency deviates
no more than 1O'7 from the standard dmsion ratio. To
ascertain this requires about 8 s (NTSC). Switching off
color-locked operation takes place automatically, in the
_ case of a change of program for example, within approx-
imately 67 ms (e.g. two NTSC fields, 60 Hz).
3.3.3. Skew Data Output and Field Number Informa-
tion
with non-standard input signals, the TPU 2735 or TPU
2740 Teletext Processor produce a phase error vvith re-
spect to the deflection phase.
The DPU generates a digital data stream (skevv data,
pin 7 ofthe DPU), which informs the PSP and TPU on
the amount of phase delay (given in 2.2 ns increments)
used in the DPU for the 1H and 2h output pulse com-
pared With the Fm main clock signal of 17.7 mHz (PAL
or SECAm) or 14.3 mhz (NTSC), see also Figs. 3-6 to
3-8. The skew data is used by the PSP and by the TPU
to adjust the double-scan video signal to the 1 H and 2H
phase of the horizontal deflection to correct these phase
errors.
For the vmC processor the skew data contains three additional
bits for information about frame number, 1 V
sync and 2 V sync start.
3.3.4. Synchronism Detector for PLL and Muting
Signal
To evaluate locking ofthe horizontal PLL and condition
of the signal, the DPU’s HSP high-speed processor
(Fig. 3~1) receives two items of information from the hor-
izontal PLL circuit (see Fig. 3-11).
a) the overall pulsevvidth of the separated sync pulses
during a 6.7 us phase window centered to the horizontal
sync pulse (value A in Fig. 3-11).
b) the overall pulsevvidth of the separated sync pulse
during one horizontal line but outside the phase window
(value B in Fig. 3-11).
Based on a) and b) and using the selectable coefficients
KS1 and KS2 and a digital lovi/pass filter, the HSP pro-
cessor evaluates an 8-bit item of information “SD” (see
Fig. 3-12). By means of a comparator and a selectable
level SLP, the switching threshold for the PLL signal
“UN” is generated. UN indicates Whether the PLL is in
the synchronous or in the asynchronous state.
To produce a muting signal in the CCU, the data SD can
be read by the CCU. The range ot SD extends from O
(asynchronous) to +127 (synchronous). Typical values
torthe comparator levels and their hysteresis B1 = 30/20
and for muting 40/30 (see also HSP Bam address Table
5-6).
DPU 2553, DPU 2554
3.4. Start Oscillator and Protection Circuit
To protect the horizontal output stage of the TV set dur-
ing changing the standard and for using the DPU as a
low power start oscillator, an additional oscillator is pro-
vided on-chip (Fig. 3-4), with the output connected to
pin 31. This oscillator is controlled by a 4 mHz signalin-
dependent trom the Fm main clock produced by the
MCU 2600 or mCU 2632 C
ered by a separate supply connected to pin 35. Thefunc-
tion ofthis circuitry depends on the external standard se-
lection input pin 33 and on the start oscillator select input
pin 36, as described in Table 3-3. Using the protection
circuit as a start oscillator, the following operation modes
are available (see Table 3-3).
With pin 33 open-circuit, pin 36 at high potential (con-
nected to pin 35) and a 4 mHz clock applied to pin 34,
the protection circuit acts as a start oscillator. This pro-
duces a constant-frequency horizontal output pulse of
15.5 kHz in the case of DPU 2553, and of 31 khz in the
case of DPU 2554 while the Beset input pin 5 is at low
potential. The pulsewidth is 30 us with DPU 2553, and
16 us with DPU 2554. main clock at pin 2 or main power
supplies at pins 8, 32 and 40 are not required for this start
oscillator After the main power supply is stabilized and
the main clock generator has started, the reset input pin
5 must be switched to the high state. As long as the start
values from the CCU are invalid, the start oscillator will
continuously supply the output pulses of constant fre-
quency to pin 31 _ By means of the start values given by
the CCU via the lm bus, the register FL must be set to
zero to enable the stan oscillator to be triggered by the
horizontal PLL circuit. After that, the output frequency
and phase are controlled by the horizontal PLL only.
It the external standard selection input pin 33 is con-
nected to ground or to +5 V, the start oscillator is
switched off as soon as it ls in phase with PLL circuit. Pin
33to ground selects PAL or SECAm standard (17.7 mHz
main clock), and pin 33 to +5 V selects NTSC standard
(14.3 MHz main clock). After the main power supplies to
pins 8, 32 and 40 are stabilized, the start oscillator can
be used as a separate horizontal oscillator with a con-
stant frequency of 15.525 khz. For this option, pin 33
must be unconnected. By means ofthe lm bus register
SC the start oscillator can be switched on (SC = 0) or oft
(SC = 1). Setting SC =1 is recommended.
By means of pin 29 (horizontal output polarity selectin-
put and start oscillator pulsewidth select input), the out-
put pulsewidth and polarity ofthe start oscillator and pro-
tection circuit can be hardware-selected. Pin 29 at low
potential gives 30 us for DPU 2553 and 16 us for DPU
2554,with positive output pulses. Pin 29 at high potential
gives 36 us for DPU 2553 and 18 its for DPU 2554, with
negative output pulses. Both apply forthetime period in
which no start values are valid from the CCU. If pin 29
is intended to be in the high state, it must be connected
to pin 35 (standby power). Pin 29 must be connected to
ground or to +5 V in both cases.
Table 3-3: Operation modes ofthe start oscillator and
protection circuit
Operation Mode Pins
33 34 35 36
Horizontal output stage protected not connected 4 mHz Clock at
+5 V at ground
during main clock frequency changing
(for PAL and NTSC)
Horizontal output stage protected not connected 4 MHz Clock +5
V with connected to
and start oscillator function start oscilla- pin 35
(for PAL and NTSC) tor supply
Only start oscillator function with at +5 V 4 mHz Clock +5 V
with connected to
NTSC standard after Beset start oscilla- pin 35
tor supply
Only start oscillator function with at ground 4 mHz Clock +5 V
with connected to
PAL or SECAM standard after Beset start oscilla~ pin 35
5 tor supply
_ with 17.7 mHz clock at ground at ground at +5 V at ground
without protection.
3.5. Blanking and Color Key Pulses
Pin 19 supplies a combination ofthe color key pulse and
the undelayed horizontal blanking pulse in the form of a
three-level pulse as shown in Fig. 3-13. The high level
(4 V min.) and the low level (0.4 V max.) are controlled
by the DPU. During the low time of the undelayed hori-
zontal blanking pulse, pin 19 of the DPU i sin the high--
impedance mode and the output level at pin 19 is set to
2.8 V by the VCU.
At pin 22, the delayed horizontal blanking pulse in com-
bination with the vertical blanking pulse is available as
athree-level pulse as shown in Fig. 3-13. Output pin 22
is in high-impedance mode during the delayed horizon-
tal blanking pulse.
ln double-scan operation mode (DPU 2554), pin 22 sup-
plies the double-scan (2H) horizontal blanking pulse in-
stead ofthe 1H blanking pulse (DPU 2553). ln text dis-
play mode with increased deflection frequencies (see
section 1.), pin 22 ofthe respective DPU (DPU 2553, as
defined by register ZN) delivers the horizontal blanking
pulse with 18.7 kHz and the vertical blanking pulse with
60 Hz according to the display. At pin 24 the undelayed
horizontal blanking pulse is output.
normally,pin3suppliesthe samevertical blanking pulse
as pin 22. However, with“DVS” = 1, pin 3 will be in the
single-scan mode also with double-scan operation of
the system. The pulsewidth of the single-scan vertical
blanking pulse at pin 3 will be the same as.that of the
double-scan vertical blanking pulse at pin 22. The out-
put pulse of pin 3 is only valid if the COU register “VBE”
is set to 1 . The default value is set to 0 (high-impedance
state of pin 3).
Fig. 3-13: Shape of the output pulses at pins 19 and 22
*) The output level is externally defined
3.6. Output for Switching the Horizontal Power
Stage Between 15.6 kHz (PAL/NTSC) and 18 kHz
(Text Display)
This output (pin 37) is designed as a tristate output. High
levels (4 V mln.) and low levels (0.4 V max.) are con-
trolled bythe DPU. During high-impedance state an ex-
ternal resistor network defines the output level,
For changing the horizontal frequency from 15 kHz to
18 kHz, the following sequence of output levels is
derived at pin 37 (see Fig. 3-14).
After register ZN is set from ZN = 2 (15 kHz) to ZN = 0
(18 kHz) by the CCU, pin 37 is switched from High level
to high-impedance state synchronously with the fre-
quency change at pin 31. Following a delay of 20ms, pin
37 is set to Low level and remains in this state forthetime
the horizontal frequency remains 18 kHz (with ZN == 0).
This 20 ms delay is required for switching-over the hori-
zontal power stage.
To change the horizontal frequency in the opposite di-
rection, from 18 kHz to 15.6 kHz, the sequence de-
scribed is reversed.
3.7. Text Display Mode with Increased Deflection
Frequencies
As already mentioned, the DPU 2553 provides the fea-
ture of increased deflection frequencies for text display
for improved picture quality in this mode of operation. To
achieve this, the processor acting as deflection proces-
sor has its register Zn set to 0. The horizontal output fre-
quency at pin 31 is then switched to a frequency of
18746.802 Hz which is generated by dmding the Fm
main clock frequency by 946 i 46. The horizontal PLL is
then able to synchronize to an external composite sync
signal offH = 18.746 kHzi 46. The horizontal PLL isthen
able to synchronizeto an external composite sync signal
of fH = 18.746 kHzi 5 % and f\, = 60 Hz i 10 % and can
be set to an independent horizontal and vertical sync
generator by setting register VE = 1 and register VB = 0.
That means a constant dmder of 946 for horizontal fre-
quency and constant 312 lines per frame.
The DPU working in this mode supplies the TPU 2740
Teletext Processor or the respective Viewdata Proces-
sor with the 18.7 kHz horizontal blanking pulses form pin
24 and the 60 Hz vertical blanking pulses form pin 22
(see Fig. 3-8).
To be able to receive and store data from an IF video sig-
nal at the same time, the Teletext or Viewdata Processor
requires horizontal and vertical sync pulses from this IF
signal. Therefore, the second DPU provides video
clamping and sync separation forthe external signal and
supplies the horizontal sync pulses (pin 24) and the ver-
tical sync pulses (pin 22) to the Teletext or viewdata Pro-
cessor. For this, the second DPU is set to the PAL stan-
dard by register ZN = 2, and the clamping pulses of the
other DPU are disabled by CLD = 1.
To change the output frequency ofthe DPU acting as de-
flection processor from 18.7 kHz to 15.6 kHz, the control
switch output pin 37 prepares the horizontal output
stage for 15.6 khz operation (pin 37 is in the high-impe-
dance state) beforethe DPU changesthe horizontal out-
put frequencyto 15.6 kHz, after a minimum delay of one
vertical period. Switching the horizontal deflection fre-
quency from 15.6 kHzto 18.7 kHz is done in the reverse
sequence. Firstly, the horizontaloutput frequency of pin
31 is switched to 1 8.7 khz, and after a delay of one verti-
cal period, pin 37 is set low.
3.8. D2-MAC Operation Mode
When receiving Tv signals having the D2-mAC stan-
dard (direct satellite reception), register ZN is set to 3.
The programmable dmder is set to a dmsion ratio of
1296 i48 to generate a horizontal frequency of 15.625
khz with the clock rate of 20.25 mHz used in the
D2-mAC standard. ln this operation mode, pin 6 acts as
input forthe composite sync signal supplied by the DmA
2271 D2-mAC Decoder. The DPU is synchronized to
this sync signal, and after locking-in (status register
UN = 0), the CCU switches the DPU to a clock-locked
mode between clock signal and horizontal frequency
(f
clock by 1024, during the vertical sync signal separated
from the received video signal. To use an 8-bit register,
the result of the count is dmded by 2 and given to the
DPU status register. ln the CCU, the vertical frequency
can be evaluated using the following equation:
fv I __lL1’_l\
1024- vP- 2
with
fm), = 17.734475 mHz with PAL and SECAm
fq,M =14.31818 mHz with NTSC
rw = 2o_25 MHZ with D2-mAc
VP = status value, read from DPU.
The interlace control output pin 39 supplies a 25 Hz (for
PAL and SECAm) or 80 Hz (for NTSC) signal for control-
ling an external interlace-off switch, which is required
with A.C.-coupled vertical output stages, becausethese
are not able to handle the internal interlace-off proce-
dure using register “ZS”.
For operation with the vmC Processor the DPU 2554
hasthree interlace control modes in double vertical scan
mode (DVS = 1). These options can be selected with the
register “IOP” and can be used together with the control
output pin 39 only. This output has to be connected to the
vertical output stage, so that the vertical phase can be
shifted by 16 us (or 32 us with DPU 2553).
Chassis DIGI B-E 110° FST. Modular Parts. Digital Sound Modul: SEL Stereo Modul DIGI. B
Viewing of Digital Audio - Sound Processing: ADC 2310 (ITT ADC2310) and APU 2470 (ITT APU247
Chassis DIGI B-E 110° FST. Modular Parts. Digital Sound Modul: SEL Stereo Modul DIGI. B
Viewing of Digital Audio - Sound Processing: ADC 2310 (ITT ADC2310) and APU 2470 (ITT APU2470)
Stereo Modul DIGI. B
Plug connectors ST 23 and ST 25 constitute the AF signal inputs
for the TV I and TV ll signals coming from the RF module. Each
of these signals is then passed (via 2 impedance converters
and 1 notch filter for suppressing interference frequency
components) to Pins 4 and 5 ofthe audio signal converter ADC
2310 E, IC 3101.
The stereo pilot carrier is selectively decoupled from sound
channel TV ll and fed separately to Pin 8 for recognition of the
station operating mode.
The digitized output signals are then available as pulse-rate-
modulated signals PDM I and PDM ll at Pins 10 and 11. Digital
signal processing is then performed completely in APU 2470,
the audio processor IC 3201, to which of course all control
functions controlled via the IM Bus belong. At IC outputs 22 and
23, the processed signals are outputted as pulse-width-
modulated information, so that they can be reconverted into
their original analog form by simple integration (RC element).
The downstream lC’s TDA 2040 H (3401/3501) supply power
amplification for feed to the loudspeakers. A second pair of
analog outputs, Pins 19, 20 ofthe APU, followed by an
integrated amplifier stage, IC 3301 , TDA 2822 M, serves for
connection of earphones or a stereo system via cinch sockets.
This output is likewise controllable, and also suitable for the
listening to the alternative sound channel in dual-channel sound
mode. Pins 21 and 24 at ADC 2310 E are available for coupling
a second dual-channel analog sound source. The signals
concerned come from the SCART socket (PPT), and in sets with
picture-in-picture function are passed via the PIP decoder. In
the opposite direction, the ADC 2310 E supplies at Pins 22 and
23 analog output signals to the SCART socket, e.g. as required
for recording audio signals. All switch-over functions necessary
in this area are executed inside the IC and controlled via the IM
Bus. Detection of the station transmission mode (mono, stereo,
dual-sound) is performed in the lC’s in exactly the same way as
the corresponding switch-over to the operating mode being
transmitted. A muting stage in each of the two audio channels
(T 3401 and T 3501) provides an audio muting function by short-
circuiting the signal input Pin 1 at the power output stage lC’s.
This function can be controlled in two different ways:
1. Via ST 33 at the moment when the set is switched on, in
order to suppress the switch-on click.
2. From Pin 16 of ADC 2310 E, e.g. for noise suppression,
when no TV signal is being received.
ln the first case, the L signal, which is passed as a switch-on
signal from Pin 5 of the CCU via R 1505 to ST 33 of Stereo
Module B, and thus via R 3511 to the base of T 3510, will switch
the transistor to on-state and thus connect the muting line to
12 V. Since in this case the two switching transistors T 4301 and
T 3501 also become conducting, the signal inputs to the audio
output stages are then short-circuited. The second muting
branch from Pin 16 of ADC 2310 E is software-controlled, and
receives the switch-off information from the CCU via the IM
Bus.
The stereo module also houses the SCART socket (PPT).
Tuner HF-MOD.OS.OPT.FS.5,6 MHz RF-IF Module Os. 5829 01 18
Tuner HF-MOD.OS.OPT.FS.5,6 MHz RF-IF Module Os. 5829 01 18 Details:
TDA5030A OSC + Mixer
TDA2556 Stereo IF AMP - Demod
TDA4427A VIF VIDEO IF AMPL - Demod
U664B Prescaler
OFW G 3251 SAW Filter.
TDA2556 QUASI-SPLIT-SOUND CIRCUIT WITH DUAL SOUND DEMODULATORS
GENERAL DESCRIPTION
The TDA2556 is a monolithic integrated circuit for quasi-split-sound processing, including two FM
demodulators, for two carrier stereo TV receivers and VTR.
Features
First IF (vision carrier plus sound carrier).
0 3 stage gain controlled IF amplifier
0 AGC circuit
0 Reference amplifier and limiter amplifier for vision carrier (V.C.) processing
0 Linear multiplier for quadrature demodulation
Second IF (two separate channels for both FM sound signals).
0 4-stage-limiting amplifier
0 Ouadrature demodulator
0 AF amplifier with de-emphasis
O Output buffer
0 Muting for one or both AF outputs
TDA 4427 VIDEO IF CIRCUIT
Technology: Bipolar
Features:
o Very high input sensitivity
0 Very low intermodulation
products
0 Minimum differential error
o Constant input impedance
independent of AGC
o Fixed video output, voltage
with small tolerance range
o Negative video signal hardly
affected by supply voltage
variations
o Very few external components
TDA 4427 A: For ceramic sound traps
Extreme fast AGC action - gating
largely independent of pulse shape
and amplitude
Positive as well as neg. video signal
available from low-impedance outputs
Positive or negative going gating pulse
Large AFC output current swing
(push-pull output)
Switchable AFC
Connecting and basic circuitry compa-
tible to the TELEFUNKEN electronic
video IF type programme - permits
building block system for video IF
module.
Television receiver with multipicture display PIP DIGIVISION ITT DIGIT2000:
CHASSIS DIG B-E PIP DECODER UNIT:
The output signal of one tuner or of other TV signal sources in the base band are digitized and stored in a part of a memory. After automatic switching over to another TV-channel, this new signal is stored in another part of the memory and so on. The whole memory is then read out continuously and produces the displayed multipicture on the screen.
What is claimed is:
1. A television receiver in which a single video signal can be reproduced simultaneously in at least two subareas of a picture screen, or at least two different video signals can each be reproduced in different subareas, with each subarea displaying either a reduced size picture or part of the picture supplied by a video signal source, said receiver comprising:
a digital signal processing circuit for receiving signals from a plurality of video signal sources and converting said signals to picture data comprising luminance and color data for each picture element;
a random access memory for storing picture data for an entire screen;
a control unit for controlling the writing of picture data into an area of said random access memory, the area being selected depending on how many of said different video signals are to be reproduced on said picture screen and also depending upon an order by which lines of picture data are read from said random access memory, only selected lines being transferred from said video signal sources into associated areas of said random access memory;
a digital to analog converter which receives picture data read from said random access memory and which generates therefrom analog red, green and blue signals;
line counters, each having its respective count outputs coupled to said control unit, said line counters each being associated with one of said video signal sources and each being advanced between received periods such that at the beginning of a receive period it has a count corresponding to the line being received from the respective video signal source;
a sensing circuit for sensing horizontal and vertical synchronizing pulses received in receive periods of said video signal sources to synchronize said line counters; and
a signal source counter connected to said control unit that causes said control unit to periodically switch between selected ones of said video signal sources.
2. A television receiver in accordance with claim 1, comprising:
a single radio-frequency receiver receiving at least two television channels originating as video signals from a single video-signal source
said radio frequency receiver being switched by said control unit to a frequency range of a corresponding television channel for the duration of one receive period which starts with the beginning of a complete scanning line, lasts at least one line period, and, if all receive periods of a switching cycle are approximately equally long, does not exceed the duration of a received field.
3. A television receiver in accordance with claim 1, wherein: a field stored in a memory area is composed of parts originating at a receiving end from odd-and even-numbered fields the size and the arrangement of the various parts of the field changing at most only slightly within a few multipicture display periods.
4. A television receiver in accordance with claim 1, wherein said control unit causes at least one video signal to be displayed in a selected subarea of the screen to be skipped and displays a still picture in said selected subarea.
5. A television receiver in accordance with claim 1, wherein:
a frequency at which switching of video signals of at least one subarea is adjustable to obtain a lower frame frequency.
6. A television receiver in accordance with claim 1 wherein:
said random access memory comprises at least one DRAM having a common bidirectional data bus and a common address bus for providing write addresses and read addresses to said DRAM to select a storage location within said DRAM, and at least one first FIFO (first-in first-out) buffer and one second FIFO buffer;
said bidirectional data bus being connected to a data output of said first FIFO buffer and to a data input of second FIFO buffer;
said first FIFO buffer having a data input supplied with picture data, and having clock input receiving a write signal;
said second FIFO buffer having an output which delivers picture data which is read out under control of a read signal and wherein
during writing into and reading from said DRAM, data is transferred block by block over said bidirectional data bus, respective write addresses and read addresses are applied over said common address bus, and a read/write signal is supplied to said DRAM.
7. A television receiver in accordance with claim 1, wherein said plurality of video signal sources indicate at least one television channel.
1. A television receiver in which a single video signal can be reproduced simultaneously in at least two subareas of a picture screen, or at least two different video signals can each be reproduced in different subareas, with each subarea displaying either a reduced size picture or part of the picture supplied by a video signal source, said receiver comprising: a digital signal processing circuit for receiving signals from a plurality of video signal sources and converting said signals to picture data comprising luminance and color data for each picture element;
a random access memory for storing picture data for an entire screen;
a control unit for controlling the writing of picture data into an area of said random access memory, the area being selected depending on how many of said different video signals are to be reproduced on said picture screen and also depending upon an order by which lines of picture data are read from said random access memory, only selected lines being transferred from said video signal sources into associated areas of said random access memory;
a digital to analog converter which receives picture data read from said random access memory and which generates therefrom analog red, green and blue signals;
line counters, each having its respective count outputs coupled to said control unit, said line counters each being associated with one of said video signal sources and each being advanced between received periods such that at the beginning of a receive period it has a count corresponding to the line being received from the respective video signal source;
a sensing circuit for sensing horizontal and vertical synchronizing pulses received in receive periods of said video signal sources to synchronize said line counters; and
a signal source counter connected to said control unit that causes said control unit to periodically switch between selected ones of said video signal sources.
2. A television receiver in accordance with claim 1, comprising:
a single radio-frequency receiver receiving at least two television channels originating as video signals from a single video-signal source
said radio frequency receiver being switched by said control unit to a frequency range of a corresponding television channel for the duration of one receive period which starts with the beginning of a complete scanning line, lasts at least one line period, and, if all receive periods of a switching cycle are approximately equally long, does not exceed the duration of a received field.
3. A television receiver in accordance with claim 1, wherein: a field stored in a memory area is composed of parts originating at a receiving end from odd-and even-numbered fields the size and the arrangement of the various parts of the field changing at most only slightly within a few multipicture display periods.
4. A television receiver in accordance with claim 1, wherein said control unit causes at least one video signal to be displayed in a selected subarea of the screen to be skipped and displays a still picture in said selected subarea.
5. A television receiver in accordance with claim 1, wherein:
a frequency at which switching of video signals of at least one subarea is adjustable to obtain a lower frame frequency.
6. A television receiver in accordance with claim 1 wherein:
said random access memory comprises at least one DRAM having a common bidirectional data bus and a common address bus for providing write addresses and read addresses to said DRAM to select a storage location within said DRAM, and at least one first FIFO (first-in first-out) buffer and one second FIFO buffer;
said bidirectional data bus being connected to a data output of said first FIFO buffer and to a data input of second FIFO buffer;
said first FIFO buffer having a data input supplied with picture data, and having clock input receiving a write signal;
said second FIFO buffer having an output which delivers picture data which is read out under control of a read signal and wherein
during writing into and reading from said DRAM, data is transferred block by block over said bidirectional data bus, respective write addresses and read addresses are applied over said common address bus, and a read/write signal is supplied to said DRAM.
7. A television receiver in accordance with claim 1, wherein said plurality of video signal sources indicate at least one television channel.
Description:
The invention pertains to a television receiver. More specifically, the present invention pertains to a television receiver with a multipicture display. In a television receiver with multipicture display a single video signal can be reproduced simultaneously in two or more subareas, or two or more different video signals can each be reproduced in associated subareas. Each of the subareas can display either a reduced-size picture or a part of the picture supplied by a video-signal source. A digital signal-processing circuit converts the signals from the video-signal source to picture data consisting of luminance and color data for each picture element. A random-access memory (RAM) holds the picture data of the entire screen. A control unit controls the writing of the picture data into an area of the RAM depending on the number of video signals to be reproduced and the line-by-line readout, with only selected lines being transferred from the video-signal source into the associated memory area. A digital-to-analg converted which is furnished with the picture data read from the RAM delivers the analog red, green, and blue signals.
A television receiver of this kind is described in a printed publication by Intermetall Semiconductors ITT, "VMC Video Memory Controller", August 1985.
That television receiver circuit uses random-access memories (RAMs). For the multipicture display, the screen is divided into up to nine equal-sized subareas which each contain a part of a picture of normal size or a complete picture of reduced size. In that mode, successively produced "snapshots" of up to nine different video signals can be displayed simultaneously. The switching of the video signals takes place manually.
Offenlegungsschrift DE No. 24 13 839 A1 describes a circuit for a television receiver with a facility for simultaneously reproducing two or more programs. In a part of the picture of the directly received main program, the secondary program, received with a single switchable tuner, is stored in a memory with a reduced number of lines and is called up line by line when the electron beam of the picture tube sweeps across the predetermined part of the picture. The disadvantage of this method lies in horizontal grating-like interference in the main picture which results from the fact that lines of the main picture are missing at regular intervals when the tuner has been switched to the secondary program, and which can only be incompletely compensated.
Accordingly, the problem to be solved by the invention is to provide a circuit of the above kind with which the grating-like interference caused during reproduction using the above-described single-tuner switching method is eliminated.
The output signal of one tuner or of other TV signal sources in the base band are digitize and stored in part of a memory. After automatic switching over to another TV-channel, this new signal is stored in another part of the memory and so on.
The whole memory is then read out continuously and produces the multi-picture display on the screen. Another advantage consists in the fact that, for the construction of the whole screen picture, all picture data are withdrawn from the RAM, so that the usual picture-improvement techniques can be applied. By fast readout from the memory rows, the displayed picture is freed from both line flicker and background flicker.
By changing the sampling rates of the different video-signal sources, it is readily possible to monitor the latter, nearly up to the still picture. In an arrangement in accordance with the invention digital picture processing and digital storage are used thereby permitting the circuit to process analog or digital signals,from video signal sources.
The invention will be better understood from a reading of the following detailed description in conjunction with the drawing in which:
FIG. 1 is a block diagram of a simplified embodiment of a television receiver with multipicture display in accordance with the invention;
FIG. 2 illustrates the division of the screen in the multipicture display mode;
FIG. 3a shows the sampling scheme for two television channels each consisting of an alternating sequence of even-and odd-numbered fields;
FIG. 3b shows schematically the division of the RAM if the sampling scheme of FIG. 3a is used,and
FIG. 4 is a block diagram of RAM.
In the simplified block diagram of FIG. 1, the video-signal sources suitable for the multipicture display are as follows: q1 is the respective signal of a television channel k1 . . . kn which is the output signal of the inermediate-frequency amplifier 112, which follows the radio-frequency receiver 114, that contains a single tuner and is supplied with the antenna signal hf; q2 is the output signal of 120 the video recorder; q3 is the output signal of 124 the video camera; q4 and q5 are the output signal of two further terminals (not shown) to which a source such as computer or a videotext set can be connected; q6 is the output signal of the teletext decoder 132. The video-signal q1 can provide alternately different television channels k1, k2 . . . if the tuner is switched in a suitable manner. The video-signals q1 . . . q5 are connected to the input sockets of the analog signal switch 134. The output of the teletext decoder 132 is connected internally to one input of the data switch 136. The signal switch 134 and the data switch 136 are controlled via the control bus 138, which carries the control data sd derived by the control unit 142.
The selection of the different television channels contained in the antenna signal hf takes place in the radio-frequency receiver 114, which contains a frequency-programable tuner. Control data sd which designates the respective television channel to be selected is fed to the tuner over the control bus 138 and prepares the tuner for switching. The actual and very fast switching of the tuner is effected by the tuner switching signal ts, which is produced by the control unit 142. A corresponding switching signal, the switching signal sus, is applied to the signal switch, and an additional signal from the control unit, the digital switching signal dss, controls the switching of the data switch 136. With switching signals ts, sus, and dss, accurate and fast switching is possible.
The composite color signal output f of the signal switch 134, is fed to the input of the digital signal-processing circuit 150. The latter delivers the picture data bd, consisting of the (R-Y) signal and the (B-Y) signal (R=red, B=blue, Y=luninance). The picture data bd from the digital signal processing circuit 150 and the picture data bd' from the teletext decoder 132 are fed respectively to two inputs of the data switch 136. The latter has two outputs a1, a2, which are switched by the control unit 142. In the normal mode, without multipicture display, the output signals of the data switch 136 are transferred from the output a1 directly to the digital-to-analog converter 162, which also contains the R-G-B matrix and delivers the analog R, G, and B signals (G=green), which are fed to the output amplifiers and then to the individual color cathodes of the picture tube. In the multipicture display mode, the digital-to-analog converter 162 is fed with the picture data br read from the RAMs, the latter being designed to have the capability of being written into and read from simultaneously.
The other output a2 of the data switch 136 feeds the RAM 164, which is divided into four areas 166, 168, 170, 172 in this embodiment. The division is only an imaginary or address-related division and is to illustrate a four-picture display. The simultaneous writing and reading of the picture data bd, bd' into and out of the RAM 164 is controlled by the control unit 142, which transfers addresses w and read addresses r over separate address buses. The control unit 142 also supplies the RAM 164 with the write signal tw and the read signal tr, which may differ in frequency. This depends on whether, in the multipicture display mode, the video-signal sources are to be presented reduced in size, as a section in the same picture size, or even as an enlarged section. In addition, the clock frequency depends on whether, during a multipicture display, the picture is to be flicker-free, because the individual television lines are then written on the screen at an increased scanning speed, which necessitates reading the individual lines from the RAM 164 at a correspondingly higher speed.
A further output signal of the digita
l signal-processing circuit 150, which corresponds to the digital composite color signal f', is fed to the teletext decoder 132 and the sensing circuit 182. The latter separates the horizontal synchronizing pulses and any vertical synchronizing pulses from the digital composite color signal f' in the respective receive cycle and feeds a line pulse h to one of the line counters 186 associated with the respective video-signal source or television channel. The contents of the selected one of the line counters 186 are fed to the control unit 142. The line counters 186 are advanced during the different receive periods so that, at the beginning of a receive period, the respective line counter has the count which corresponds to the line being received. This advance is controlled by the control unit 142. In this manner, line synchronism with the respective video-signal source or the television channel is achieved which is independent of whether the video-signal source or the television channel is connected to the RAM 164. Only with this exact synchronism is it possible to ensure that, despite the video-signal-source or television-channel switching, the corresponding scanning line is written at the correct location of the RAM 164 and that the beginning of this line is placed at the beginning of the respective memory-area row. A receive period thus starts with the beginning of a complete scanning line and continues at least for the duration of that line. If the respective receive period contains a vertical synchronizing pulse, the sensing circuit 182 supplies the vertical pulse v to the respective one of the line counters 186 which uses it to synchronize the counting of the individual lines.
The control unit 142 is also suppied with the contents of the signal-source counter 190, which is advanced with the switching of the video signals. The signal-source counter 190 is a sort of ring counter whose number of states is equal to the number of video signals to be reproduced.
If either alternate even and odd-numbered fields or only like fields are to be tranferred into the respective memory area ss . . . , the signal-source counter 190 may be designed accordingly, e.g., by increasing the number of counter states to an even-or-odd-number value.
During the multipicture display, line flicker or background flicker can be eliminated by suitable techniques, as described in the above prior art. Jerky movements of the picture content in the case of video signals with moving picture content are unavoidable. However, this impairment is reduced by the reduced-size display of the video signals in subareas 192, 194, 196, 198 of the screen 200. However, the effect increases as the number of video signals contributing to the construction of the picture increases. It is therefore an advantage if the average receive periods of the video signals are not equal to each other but are individually adjustable. With this, a less important video-signal q3, which originates from a camera, or a less important channel k . . . can be switched to the signal switch 134 only at a very low repetition rate. The receive periods thus remaining vacant can be used for another video-signal source, which can then provide a nearly jerk-free picture. For this specific control, a signal-source counter 190 in connection with the control unit 142 is required. The signal-source counter 190 thus has its input connected to the control bus 138 and is supplied with a switching signal, here the switching signal sus, and its output is fed to the control unit 142.
The durations of the individual receive periods, which are normally about equally long within a switching cycle and do not exceed the duration of a received field, are changed by the individual switch over so that individual receive periods occur which may comprise more than one field. In exchange, receive periods for other video signals become shorter or even are skipped completely.
Between the digital signal-processing circuit 150 and the RAM 164 a filter circuit may be provided which compresses the picture data bd, whereby the size of the RAM 164 can be reduced.
Another advantage of such filter circuits is a horizontal and vertical interpolation of the selected scanning lines of the respective video signal, which permits improved picture reproduction in the subareas 192, 194, 196, 198 and horizontal structures occur in the respective video signal, these structures may be present or absent in the read-out picture data br as a result of the selection of the picture elements stored in the memory area 166, 168, 170, 172, thus interfering with the picture reproduction. The interpolation eliminates this interference, which may also appear as moire.
FIG. 2 shows a typical multipicture display on the screen 200 of a television set which is divided into four subareas 192, 194, 196, 198 in accordance with the embodiment of FIG. 1. In the first subarea 192 and the second subarea 194, pictures of two different television channels k1, k2 are shown. The third subarea 196 shows a videotext page as is delivered by the video-signal q6, while in the fourth subarea 198, the recorded signal of the video recorder 120 is being reproduced. In all four subareas, the images of the different video-signal sources are reduced in size. In the display in the second subarea 194, the frame frequency can be reduced, for this area only serves to check when a particular program, e.g., a film, begins. The videotext page in the third subarea 196 can be stored as a still picture; the frame frequency is thus increased for the first and fourth subareas 192, 198.
FIG. 3a shows an embodiment of the sampling scheme of two television channels k1, k2 of a 625-line standard with 25 blanked lines per field. The respective fields h1, h2 are shown one above the other, with the odd-numbered field h1 containing the odd-numbered lines, and the even-numbered field h2 the even-numbered lines. The schematic course of the sampling of the two television channels k1, k2 is indicated by the meander line bd*, which runs between the two television channels k1, k2. The first memory area 166 is used for the first television channel k1, and the fourth memory area 172 for the second television channel k2. The receive period is 20 ms, after which the received televisions channel is switched to the other channel. The sampling beginnings with line 1 in the odd-numbered field h1 of the television channel k1, and lines 47 to 451 of this field are stored. Then, the television channel k2 is turned on, whose phase position is such that the 121st line of the odd-numbered field h1 can just be written in. This field h1 is stored until line 619 inclusive. During the retrace period, no storage takes place. Of the even-numbered field h2, the 46th to the 120th lines are then stored at the corresponding locations of the fourth memory area 172. Another switchover to the television channel k1 finds the line 452 in the even-numbered field h2, after which this field is written in until line 618 inclusive. During the retrace period, no storage takes place. The new odd-numbered field h1 is again written in with line 47, and the sampling process continues periodically in this manner. For simplicity, in FIG. 3a, only the area between the line 46, 47 and 618, 619 has been included in the storage process. The memory area required for the video signal sources thus decreases by the retrace lines without picture information.
FIG. 3b shows schematically how the storage process of FIG. 3a takes place in the RAM 164. The first memory area 166 shows a stored line combination from the odd-numbered field h1 and the even-numbered field h2 of the first television channel k1. In the fourth memory area 172, the corresponding stored lines of the television channel k2 are shown, again a combination from the odd-numbered field h1 and the even-numbered field h2. The memory areas ss2, ss3 contain "old" picture data and are not involved in the above-described video-signals switching but may contain, for example, a previously taken "snapshot" or a still picture which is then presented as part of the multipicture display.
The sampling scheme of FIG. 3a is the associated memory content of FIG. 3b also show that the size and arrangement of the different parts of the picture which are stored in the individual memory areas 166, 168, 170, 172 change only slightly, if at all, within a few multipicture display periods. This results if the phases of the video signals involved drift past each other, so that the relative phase position of the fields h1, h2 of the video signals gradually changes.
Unlike the circuit described in Offenlegungsschrift DE No. 24 13 839, all video signals to be reproduced are first written into a memory area 166, 168, 170, 172 and then read out for display. No distinction is made between a main program and a secondary program. The respective picture reproduction in the subareas 192, 194, 196 and 198 corresponds to the picture data read from the respective memory areas 166, 168, 170, and 172. The switching and storage process has thus become highly variable in time, for the duration of the receive periods is variable within a wide range-from the duration of a line up to the duration of a field-without this resulting in a superposed interference pattern on the screen because of missing lines or missing line blocks. The more video signals are to be reproduced, the clearer the improvement over the method disclosed in the above Offenlegungsschrift, in which the number of missing lines in the main picture would increase intolerably if there were several secondary pictures. Therefore, that method is applicable in practice to a single secondary picture at best.
The RAM 162 shown in the schematic presentation of FIG. 1 is a "dual-port RAM" with separate read and write cycles, which has a data bus for the picture data to be stored, bd, or bd', a data bus 210 for the picture data read out, a data bus 212 for the write addresses, a data bus 214 for the read addresses, an input 216 for the write signal tw, and an input 218 for the read signal tr.
Direct realization of this arrangement with currently availably RAMs, particularly with the currently standardized and, therefore, less expensive dynamic RAMs (dynamic RAM=DRAM) is not possible because the above described function separation is not provided for.
With the specific "dual-port DRAM" MB 81461-12, the function separation is possible in a slightly modified form, for this commercially available memory module includes all separate functional units except a separate address bus. In addition, this dual-port DRAM permits fast reloading of stored data blocks from the actual memory area to an integrated buffer. From the latter, the stored picture data br for the multipicture display are then read strictly sequentially, so that the common address bus is free for the loading process during that time.
FIG. 4 shows a somewhat more sophisticated realization with two so-called first-in, first-out buffers (FIFO buffers) 230, 232, which, however, allows the use of standardized DRAMs 234 with a common address bus 236 and a common data bus 238. Such FIFO buffers 230, 232 (example of a commercially available type: TDC 1030) convert the bidirectional data bus 238 functionally into two isolated data busses for simultaneous write-in and readout of data.
The output of the first FIFO buffer 230 and the input of the second FIFO buffer 232 are connected to the bidirectional data bus 238 of the DRAM 234. The first FIFO buffer 230 is supplied with the write signal tw, and the second FIFO buffer 232 with the read signal tr. The writing of the picture data bd, bd' into the first FIFO buffer 230 and the reading of the stored picture data br from the second FIFO buffer 232 are thus isolated from each other.
The fast block-by-block reloading of the data stored in the first FIFO buffer 230 into the DRAM 234 takes place via the bidirectional data bus 238, with the write addresses w entered as block addresses over the address bus of the DRAM 234, and thus represents the actual loading process of the DRAM 234. The clock signal supplied to the DRAM 234 is the read/write signal twr.
Data is read out of the DRAM 234 over the bidirectional data bus 238 in blocks which are temporarily stored in the second FIFO buffer 232, with the read addresses r entered as block addresses over the address bus 236 of the DRAM 234, and the clock signal being the rear/write signal twr. For the multipicture display, the readout of the stored picture data br from the second FIFO buffer 232 then takes place strictly sequentially for the scanning lines to be displayed. Technology Overview:
Picture-in-picture means the insertion of a second programs picture on the screen of a CTV receiver (at reduced size) simultaneously with the full-size main picture. The second, smail picture may origine from anofher TV"transmitter, from a video recorder, a monitor camera or another source. It allows monitoring of the second channel while watching the main channel. Main requirementfor picture-in-picture is to store the content of the small picture when it is supplied by its source, and to deliver the content at the proper Instant when it must be inserted into the main picture which is received and displayed continuously. For storing the content of the second, small picture, two standard 64 K dynamic RAMs (16 x 4) are used, thus makingthe storage simple and economic. Todays picture-in-picture fits neatless Into the wellknown DIGIT2000 system, but is also suitable for stand-alone applications. The PIP2250 is a fast signal processor in CMOS technology which is used to filter (for anti-aliasing) and to decimate the digital Y, R-Yand B-Y signal supplied by the VSP2850 VideoSync Processor, to control the DRAMs for storing the small pictures content and for reading the same at the proper time for display. Further, a border generator supplies the borderline for the small picture
Digit 2000 VLSI Digital TV System DIGIVISION ITT Intermetal Timing correction for a picture-in-picture television system
System performance of picture-in-picture video display systems is dependent on critical timing relationships between the incoming signals and the clock signals used to sample and display both the large picture and small picture signals. Video signals from various sources, e.g. VTR's, tend to have jittering time bases which may cause the small image to appear jagged or tilted. This distortion in the small image may be reduced by effecting adaptive signal delays in the small picture signal responsive to the relative phase of the system clock signal with respect to the horizontal synchronizing pulses of the large and/or small picture signal. One phase measure is used to control an interpolator which combines successive samples of the small picture signal in proportions to develop sample values corresponding to samples that would have occurred had the small picture signal been sampled by a clock properly aligned to the small picture horizontal synchronizing pulses. A second phase measure is used to delay the clock signal used to display the small picture so that the clock pulses that define the edges of the small picture occurs with the same timing relative to the large picture horizontal synchronizing pulses form line-to-line.1. In a video signal processing system including a source of first video signal having a periodic horizontal line synchronizing signal component and a memory for holding sampled data representing a second video signal, apparatus for processing said sampled data in synchronism with said first video signal comprising:
means coupled to said source for developing horizontal synchronizing pulses representing the horizontal line synchronizing signal component of said first video signal:
a terminal for applying a clock pulse signal wherein the occurrence of clock pulses possibly exhibits varying amounts of skew relative to said horizontal synchronizing pulses;
skew measuring means coupled to said clock signal terminal and responsive to said horizontal synchronizing pulses for generating a control signal corresponding to the difference in time, as a proper fraction of the period of said clock pulse signal, between the occurrence of a horizontal synchronizing pulse and a pulse of said clock signal;
means coupled to said clock signal terminal, for controlling the reading of the sampled data from said memory; and
skew correcting means coupled to said clock signal terminal, to said memory and to said skew measuring means for effecting a time displacement of the signal represented by the sampled data read from said memory, the magnitude of said time displacement being determined by said control signal.
2. The apparatus set forth in claim 1 wherein said skew correcting means comprises:
means coupled to said clock signal terminal and responsive to said control signal for effecting a time displacement of said clock signal to develop a skew corrected clock signal; and
means for applying said skew corrected clock signal to said means for controlling the reading of sampled data from said memory.
3. The apparatus set forth in claim 2 wherein:
said skew measuring means includes means for measuring the time interval between the center point of a pulse of said horizontal line synchronizing signal and a transition of the pulse of said clock signal which occurs in time immediately prior to said center point.
4. The apparatus set forth in claim 1 wherein said skew correcting means comprises:
means for generating samples corresponding to the sums of first and second consecutive samples read from said memory and scaled by respective first and second scale factors proportional to said control signal.
5. The apparatus set forth in claim 1 wherein said skew correcting means comprises:
m
eans for scaling the values of first and second consecutive samples read from said memory by first and second mutually complementary scale factors proportional to said control signal; and means for combining the first and second scaled samples to develop samples representing said time displaced signal.
6. In a video signal processing system including a source of first video signal having a horizontal line synchronizing component and a source of second video signal having a horizontal line synchronizing component, apparatus for processing said second video signal in synchronism with said first video signal comprising:
means coupled to said source of first video signal for developing first horizontal synchronizing pulses representing the horizontal synchronizing component of said first video signal;
means coupled to said source of second video signal for developing second horizontal synchronizing pulses representing the horizontal line synchronizing component of said second video signal;
a terminal for applying a clock pulse signal, wherein the occurrence of clock pulses possibly exhibits respectively different varying amounts of skew relative to said first and second horizontal sync pulses;
first skew measuring means coupled to said clock signal terminal and responsive to said second horizontal synchronizing pulses for generating a first control signal corresponding to the time difference between the occurrence of one of said second horizontal synchronizing pulses and a pulse of said clock pulse signal;
first skew correcting means responsive to said first control signal and coupled to said sampling means for modifiying the values of samples provided thereby to effect a time displacement of the signal represented by said samples, the magnitude of said time displacement being determined by said first control signal;
memory means coupled to said skew correcting means for storing samples representing said time displaced second signal;
second skew measuring means responsive to said clock signal and to said first horizontal synchronizing pulses for generating a second control signal corresponding to the time difference between the occurrence of one of said first horizontal synchronizing pulses and a pulse of said clock signal;
means coupled to said clock signal terminal for controlling the reading of the sampled data from said memory means; and
second skew correcting means coupled to said clock signal terminal, to said memory and to said skew measuring means for effecting a time displacement of the signal represented by the sampled data read from said memory, the magnitude of said time displacement being determined by said second control signal.
7. The apparatus set forth in claim 6 wherein said second skew correcting means comprises:
means coupled to said clock signal terminal and responsive to said second control signal for effecting a time displacement of said clock signal to develop a skew corrected clock signal; and
means for applying said skew corrected clock signal to said means for controlling the reading of sampled data from said memory.
8. The apparatus set forth in claim 6 wherein said second skew correcting means comprises:
means for generating samples corresponding to the sums of first and second consecutive samples read from said memory and scaled by respective first and second scale factors proportional to said second control signal.
9. The apparatus set forth in claim 6 wherein said second skew correcting means comprises:
means for scaling the values of first and second consecutive samples read from said memory by first and second mutually complementary scale factors proportional to said second control signal; and
means for combining the first and second scaled samples to develop samples representing said time displaced signal.
10. The apparatus set forth in claim 6 wherein:
said first skew measuring means comprises means for measuring the time interval, as a proper fraction of a period of said clock signal, between a predetermined point on a pulse of said second horizontal line synchronizing signal and a transition of a pulse of said clock signal which is adjacent in time to said predetermined point; and
said second skew measuring means comprises means for measuring the time interval, as a proper fraction of a period of said clock signal, between a predetermined point on a pulse of said first horizontal line synchronizing signal and a transition of a pulse of said clock signal which is adjacent in time to said predetermined point.
11. The apparatus set forth in claim 10 wherein said first skew correcting means includes means for scaling the values of first and second consecutive samples representing said second signal by a factor proportional to said first control signal and by a factor proportional to the complement of said first control signal respectively and means for adding the first and second scaled samples to develop a first sample representing said time displaced signal. 12. In a picture-in-picture television display system including a source of first video signal having a periodic horizontal line synchronizing signal component and a source of second video signal having a periodic horizontal line synchronzing signal component, apparatus for processing said second video signal in synchronism with said first video signal comprising:
means including a memory for processing said second video signal to develop sampled data in said memory representing said second video signal;
a terminal for applying a clock pulse signal wherein the occurrence of pulses of said clock signal possibly exhibits varying amounts of skew relative to the horizontal synchronizing pulses of said first video signal;
skew measuring means coupled to said clock signal terminal and responsive to said horizontal synchronizing pulses of said first signal for generating a control signal corresponding to the amount time, as a proper fraction of the period of said clock signal, between the occurrence of a horizontal synchronizing pulse and a pulse of said clock signal;
skew correcting means coupled to said clock signal terminal and responsive to said control signal for effecting a time displacement of said clock signal to develop a skew corrected clock signal:
means coupled to said skew correcting means and to said memory for extracting the sampled data therefrom in synchronism with said skew corrected clock signal; and
multiplexing means coupled to said sampled data extracting means and to said source of first video signal for selectively providing signals from said source of first video signal and from said memory to a display device.
13. The apparatus set forth in claim 12 wherein:
said skew measuring means includes means for measuring the time interval between a predetermined point on a pulse of said horizontal line synchronizing signal and a transition of the pulse of said clock signal which occurs immediately prior to said predetermined point; and
said skew correcting means includes means for delaying said clock signal by an amount of time approximately equal to said time interval to develop said skew corrected clock signal.
14. The apparatus set forth in claim 12 wherein said means for processing said second video signal comprises:
means coupled to said source of second video signal for developing further horizontal synchronizing pulses representing the horizontal line synchronizing signal component of said second video signal;
means coupled to said source of second video signal for developing samples representing said second video signal at instants in time determined by said clock signal;
further skew measuring means coupled to said clock signal terminal and responsive to said further horizontal synchronizing pulses for generating a further control signal corresponding to the amount of time, as a proper fraction of the period of said clock signal, between the occurrence of a further horizontal sync pulse and a pulse of said clock signal; further skew correcting means coupled to said sample developing means and to said clock signal terminal and responsive to said further control signal for effecting a time displacement of the signal represented by the samples provided by said sample developing means;
means coupled to said further skew correcting means for applying selected ones of the samples provided thereby to said memory.
15. The apparatus set forth in claim 14 wherein,
said second video signal may include a color synchronizing burst signal component; and
the clock pulse signal applied to said clock terminal is synchronized in frequency and phase to said color synchronizing burst signal component.
16. The apparatus set forth in claim 14, wherein:
said first and second video signals include respective first and second chrominance signal components including respective first and second color synchronizing burst signal components;
the clock pulse signal applied to said clock terminal is synchronized in frequency and phase to said first color synchronizing burst signal component;
the chrominance signal components of the samples provided by said sample providing means tend to have phase errors relative to the samples which would be provided if the clock signal were locked in frequency and phase to the second color synchronizing burst signal component; and
means coupled to said sample providing means and responsive to said second color synchronizing burst signal component for substantially correcting said phase errors.
17. In a picture-in-picture television display apparatus including a source of first video signal having a periodic horizontal line synchronizing component, means for applying a clock pulse signal wherein the occurrence of clock pulses may exhibit varying amounts of skew relative to said horizontal line synchronizing component, a memory for holding sampled data representing a second video signal, means for displaying the image represented by said first video signal and means for reading the sampled data from said memory and for displaying the image represented by said samples as an inset in the image represented by said second video signal, wherein the improvement comprises:
skew measuring means responsive to said clock signal and to said horizontal synchronizing pulses for generating a control signal corresponding to the difference in time, as a proper fraction of the period of said clock signal between the occurrence of a horizontal synchronizing pulse and a pulse of said clock signal; and
skew correcting means responsive to said clock signal and coupled to said memory and to said skew measuring means for effecting a time displacement of the sampled data read from said memory, the magnitude of said time displacement being determined by said control signal.
Description:
This invention relates to apparatus for reducing the visibility of timing errors in the inset image of a picture in picture (PIP) television display system.
In a PIP system, two images from possibly unrelated sources are displayed simultaneously as one image. The composite image includes a full size primary image and a reduced size secondary image displayed as an inset. The subjective quality of the inset portion of the composite image may be affected by timing errors in either the primary or secondary signals.
The timing errors relevant to the present invention occur when either the primary or secondary signal is a nonstandard signal. As used in this application, the term nonstandard signal means a video signal having a horizontal line period which may vary in width by, for example, 4 ns or more from the horizontal line period set by the signal standard to which the video signal nominally conforms (e.g. NTSC, PAL, or SECAM).
To understand how these timing errors may affect the inset image, it is helpful to know how the secondary signal is processed and displayed. In a conventional PIP display system, the secondary signal is sampled at instants determined by a sampling clock signal which, desirably, bears a fixed relationship to the horizontal line scanning frequency of the secondary signal. To aid separation of the luminance and chrominance components of color television signals, the sampling clock signal has a frequency that is a multiple of the chrominance subcarrier frequency which is itself a harmonic of one-half the horizontal line scanning frequency. This sampling clock signal may be developed by a phase locked loop which locks the clock signal to the color reference burst component of the composite video signals.
The secondary signals are separated into their component parts, generally a luminance signal and two color difference signals, and then subsampled both vertically and horizontally to develop signals which represent a reduced-size image. The lines of samples taken during one field of the secondary signal are stored in a memory. These samples are then read from the memory for display using a clock signal which is desirably related to the horizontal line scanning frequency of the primary signal.
When the secondary signal originates from a video tape recorder (VTR), video disk player or home computer, the frequency of the color burst signal may be relatively stable while the frequency of the horizontal line scanning signal may vary significantly from line to line. This variation may be caused by stretching of the tape, defects in the disk, motor speed variations in either the VTR or disk player, or inaccuracies in the frequencies used by the home computer. Since the sampling clock signal is locked to the burst signal, corresponding sampling points on successive lines may be shifted or skewed relative to each other. When these lines of samples are displayed in synchronism with the primary signal, the corresponding samples do not line up vertically. Consequently vertical lines in the inset image may appear jagged, if the timing errors randomly change the period of the horizontal sync signal, or tilted if there is a fixed error in the horizontal sync period. Assuming a 3:1 reduction in the secondary image, a timing difference of 12 ns or more in successive horizontal line periods of the secondary signal may produce noticeable skew distortion in the inset image.
Timing errors in the primary signals change the relative time difference between primary horizontal sync pulses, which define the edges of the primary image, and the first samples in lines of the inset image. Primary signal timing errors that cause the periods of successive horizontal sync pulses to vary from the applicable signal standard by 4 ns or more may produce noticeable skew distortion in the inset image. This distortion causes the entire inset image to appear jagged or tilted.
To gain a better understanding of skew and the methods which may be used to compensate for it, consider the waveforms shown in FIG. 1. The waveform A represents a portion of one horizontal line of, e.g. luminance signal, including the horizontal synchronizing pulse (note the waveforms of FIG. 1 are not drawn to scale). Waveforms B, C and C' represent sampling (system) clock waveforms. The pulses of waveform B are assumed to occur at the points in time that a subcarrier locked clock, locked to a standard signal, would occur. Put another way, if waveform A corresponds to n lines of an image, then waveform B represents the desired sampling (system) clock for each successive line, i.e. without skew. A clock signal having constant skew may also be desirable. In either a zero skew or a constant skew system, the sampling clock pulse r always occurs at the same point in time relative to the HSYNC pulse. This point in time is represented by the sample S2 on waveform A. Waveform C represents a subcarrier locked clock which exhibits a degree of skew. The number of pulses per line period contained in waveform C may not be constant from line-to-line. Generally, the difference in the number of whole clock pulses in a line period can be compensated for in the phase locked loop which generates the horizontal synchronizing signal. The sampling phase error (skew) which is a fractional portion of a clock period, however, may only be corrected by operation on the samples themselves or on the sampling clock signal.
One method of correction is to adjust the sample values on a line-by-line basis so that the adjusted samples conform to samples that would be taken by a clock with zero skew or with some constant skew. For example, the sample values generated by the clock signal of waveform C may be adjusted to equal or approximate corresponding sample values that would be generated by the clock signal of waveform B. In the FIG. 1, clock pulse r' of waveform C is assumed to correspond to clock pulse r of waveform B. Clock pulse r' is advanced in time or skewed by one-half of one clock period, TS, with respect to clock pulse r. Clock pulse r' generates a sample value S1. Desirably, clock pulse r' should occur coincident with clock pulse r and generate the sample value S2.
Replacing the sample taken coincident with clock pulse r' with a sample having a value approximately equal to S2 effectively advances the timing of the signal taken with the sampling clock signal C so that it matches the signal which would have been taken had the zero-skew sampling clock signal B been used. Neglecting the complications of chrominance decoding, an alternative method of skew correction is to adjust the phase of the sampling clock signal on a line-by-line basis so that it approximately matches the phase of the desired clock signal B or some other clock signal which exhibits equal skew from line to line. The waveform C' represents the clock signal C delayed an amount of time substantially equal to the skew. Samples taken with this delayed clock signal approximate samples taken with the desired clock signal, B.
The first skew correction method may be used to correct skew errors in the secondary signal since it does not affect the phase of the sampling clock signal. It is recalled that the phase of this clock signal cannot be changed without affecting the processing of the secondary chrominance signal components. The second skew correction method may be used to compensate for skew errors in the primary signal when the samples representing the separated luminance and color difference signal components of the secondary image are retrieved from the secondary field memory for display.
SUMMARY OF THE INVENTION
The present invention is embodied in apparatus which compensates for timing errors in a first video signal relative to a second, stored video signal. This apparatus includes circuitry for measuring the time interval between a horizontal synchronizing pulse of the first signal and a pulse of the clock signal which controls the retrieval and display of the second signal. The apparatus further includes circuitry with changes the timing of the second signal relative to the horizontal sync component of the first signal, as the second signal is displayed, to compensate for any variations in the measured time intervals from line-to-line.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a timing diagram useful in describing skew and methods of skew correction.
FIG. 2 is a block diagram of a PIP television display system incorporating the present invention.
FIG. 3 is a block diagram of a digital PIP television display system incorporating the present invention.
FIGS. 4 and 5 are a block diagrams showing skew correction circuitry which may be used in the display devices shown in FIGS. 2 and 3.
FIG. 6 is a block diagram of alternative skew correcting apparatus which may be used in the display devices shown in FIGS. 2 and 3.
DETAILED DESCRIPTION OF THE INVENTION
In the drawings, broad arrows represent busses for multiple-bit parallel digital signals and line arrows represent connections carrying analog signals or single bit digital signals. Depending on the processing speed of the devices, compensating delays may be required in certain of the signal paths. One skilled in the art of digital signal processing circuit design would know where such delays would be needed in a particular system.
FIG. 2 is a block diagram of a PIP display device in which the primary signal is processed using conventional analog apparatus and the secondary signal is processed digitally. This circuitry uses a single clock signal, synchronized to the secondary burst signal, both for sampling and processing the secondary signal and for displaying the secondary image as an inset in the main image.
A source of primary composite video signals 10 applies the primary video signals to a Y/C separation filter 12. Filter 12, which may include conventional low-pass and high-pass filters, separates the composite video signals into primary luminance signals, YP, and primary chrominance signals Cp. The primary luminance and chrominance signals are applied to a primary chroma/luma processor 14 which may include, for example, band shaping filters for peaking the high frequency components of the luminance signals to develop a signal Y'P and a chrominance signal demodulator for deriving the baseband color difference signals (R-Y)P and (B-Y)P from the primary chrominance signals, CP. The signals Y'P, (R-Y)P, and (B-Y)P applied to a matrix 16 which combines the signals to develop the color signals RP, GP and BP. These signals are applied to one set of signal input terminals of an analog multiplexer 26, the output of which drives a cathode ray tube (CRT) 28. The color signals RS, GS and BS developed from the secondary signal are applied to a second set of signal input terminals of the multiplexer 26. These signals are developed by apparatus described below.
A source of secondary composite video signals 50, which may include the tuner, IF amplifier and video detector of a conventional color television receiver, provides secondary composite video signals to an analog-to-digital converter (ADC) 52. ADC 52 samples and digitizes the secondary composite video signals at instants determined by the sampling clock signal CK. A phase-locked-loop (PLL) 56, described below, generates the signal, CK, which has a frequency 4fc substantially equal to four times the chrominance subcarrier frequency, fc. The signal CK is phase locked to the color synchronizing burst component of the secondary video signals.
ADC 52 provides digitized secondary video signals to a Y/C separation filter 54. Filter 54 may be a conventional digital filter having a clock input terminal coupled to receive the signal CK. Filter 54 may include, for example, an FIR filter which passes the chrominance signal components of composite video signal to the relative exclusion of luminance signal components and a subtracter for subtracting the chrominance signal components from the composite signal to develop luminance signal components.
ADC 52 also provides secondary composite video signals to a deflection processing unit (DPU) 60, which includes sync separator circuitry 58 and skew error measuring circuitry 59. The sync separator circuitry 58 and skew measuring circuitry 59 in the illustrated embodiment are components in a phase-locked-loop which produces a horizontal synchronizing signal, SHS, that is phase-locked to the horizontal synchronizing signal component of the secondary signal. Sync separator circuitry 58 applies the signal SHS and a digital value (HSP) containing an integer part and a fractional part representing the period of the signal SHS in units of one-sixteenth of the sampling clock period (1/16 Ts) to the skew measuring circuitry 59. The sync separator circuitry 58 also develops the vertical synchronization signals, SVS, and a burst gate signal, BG, from the digitized secondary composite video signals. The burst gate signal, BG, and the separated chrominance signals from filter 54 are applied to PLL 56. PLL 56 is, for example, a circuit similar to that described in U.S. Pat. No. 4,291,332 entitled "Phase Locked Circuit" which is hereby incorporated by reference.
The clock signal CK is applied to the skew measuring circuitry 59. Exemplary skew measuring circuitry 59 accumulates the fractional part of the horizontal skew period values, HSP, provided by the sync separator circuitry 58 to develop a secondary skew signal, SSK. The integer part of the signal SSK is fed back to the sync separator circuitry 58, where it is used in the phase-locked-loop to update the horizontal sync period measurement. The fractional part of the signal SSK is retained in the accumulator of the skew measuring circuitry 59 and applied as skew values to the skew correcting circuitry 62. As used in the present embodiment, the fractional part of the signal SSK represents the time interval between the center of the respective phase locked horizontal sync pulse and the leading edge of the clock pulse which occurs immediately before the center of the respective horizontal sync pulse. This interval is measured with a resolution substantially equal to one-sixteenth of the period of the signal CK. The sync separator circuitry 58 and the skew measuring circuitry 59 are of the type contained in the integrated circuit DPU 2532 manufactured by ITT Intermetall GmbH and which is described at pages 47-72 of the data book "Digit 2000 NTSC Double-scan VLSI Digital TV System" edition 1985/5 of ITT Intermetall, Freiburg, W. Germany.
Exem
plary skew error correcting circuitry 62 is shown in FIG. 4. This circuitry interpolates between successive input samples to provide output samples that are substantially equivalent to the samples which would have been taken synchronous with a sampling clock signal having zero skew. The circuitry shown in FIG. 4 may be divided into two parts, a linear interpolator and a correction circuit. Luminance samples YS are applied to a delay element 410, which delays the samples by one period of the clock signal CK. The delayed samples are applied to a multiplier 412 which scales the samples by a factor K. The factor K may be a value between zero and one and is provided by a read only memory (ROM) 424 in response to the secondary skew signal SSK. Luminance samples YS are also applied to a multiplier 414 which scales these undelayed samples by a factor 1-K, also provided by ROM 424. The samples provided by the multipliers 412 and 414 are summed in adder 416.
The samples provided by adder 416 are linearly interpolated samples. If the frequency components of the sampled signals YS are an order of magnitude or more lower than the sampling frequency, the apparent delay of the interpolated samples is given by the product KTS, where TS is the period of the sampling clock signal CK. As the frequency components of the sampled signals approach the sampling frequency, however, the amount by which Ys appears to have been delayed becomes a function of the levels of its higher frequency components as well as of K. The correction circuit, which includes filter 422, multiplier 428 and adder 420 compensates for the frequency induced delay components. Luminance signals YS are applied to the filter 422 which has the transfer function T422 =-1+Z-1 +Z-2 -Z-3 expressed in Z transform notation. The samples provided by filter 422 are scaled by a factor C in multiplier 428. The factor C is provided by ROM 424 in response to the secondary skew signal, SSK. The samples developed by adder 416 are applied to a delay element 418 which compensates for the processing time through filter 422. These delayed samples are then added to the samples from multiplier 428 by an adder 420.
The combination of the linear interpolator and the correcting filter produce signals having an apparent delay of (1+K)Ts where the signals to be delayed have components with frequencies as high as one-third of the frequency of the sampling clock signal. In the NTSC system, for example, where the sampling clock frequency is approximately 14.3 MHz this skew correcting circuit provides uniformly spaced delays for luminance signals which may have frequency components up to 4.2 MHz. I defines the contents of ROM 424 to achieve delay steps of one-sixteenth of a sampling clock period.
The samples provided by this skew correcting circuit 62 have apparent delays of between 17TS /16 and 2TS. The delay is only apparent because the actual timing of the samples has not been changed. The skew correcting circuit 62 adjusts the sample values in each line of secondary luminance signals so they appear to have been generated using a sampling clock signal which had negligible skew.
The chrominance samples provided by Y/C separation filter 54 are applied to delay element 63 which provides a two sample period delay to compensate for the delay through the skew correcting circuitry 62. Because the chrominance signal has a smaller bandwidth than the luminance signal and because the eye is less sensitive to color transitions than to changes in brightness, skew errors in the chrominance signal are not as noticeable as skew errors in the luminance signal. Accordingly, the apparatus shown in FIG. 1 does not correct skew errors in the chrominance signal. It will be appreciated, however, that delay element 63 may be replaced with a skew correcting circuit similar to circuit element 62.
The luminance samples from skew correcting circuitry 62 and the chrominance samples from delay element 63 are applied to a secondary chroma/luma processor 64. Processor 64 may include, for example, an FIR band shaping filter for peaking the frequency spectrum of the digital luminance signals to provide a modified secondary luminance signal YS ' and a digital chrominance demodulator for developing samples which represent the baseband secondary color difference signals (R-Y)S and (B-Y)S.
The signals YS ', (R-Y)S and (B-Y)S are applied to PIP field memory 68 where they are subsampled and stored under control of the write address generator circuitry 70. Memory 68 may be a conventional random access memory having a sufficient number of storage cells to hold one field of the subsampled secondary signal. This memory may be organized as three separate field memories, one for the luminance signal and one for each of the two color difference signals, or it may be organized as a single field memory with the sampled luminance and color difference signals combined into a single sampled signal. For example, these signals may be combined by alternately concatenating samples of the two color difference signals to samples of the luminance signal.
Data from the secondary chroma/luma processor 64 is written into the field memory 68 under control of the memory address generator circuity 70. The circuitry 70 develops write address signals, WADDR, and other control signals WCS, as may be needed from the clock signal CK, and the secondary vertical and horizontal sync signals SVS and SHS respectively. The write address generator circuitry 70 operates to subsample the secondary signal in, for example, a three-to-one ratio both vertically and horizontally by providing address values and control signals for the memory 68 at appropriate times.
Samples representing lines of the subsampled secondary image are read from the PIP field memory 68 under control of the read address generator circuitry 24. The signals applied to circuitry 24 are the primary vertical and horizontal sync signals, PVS and PHS respectively, and a skew corrected clock signal CK'. The circuitry 24 may for example, count pulses of the horizontal sync signal, PHS, relative to the vertical sync pulses, PVS, and pulses of the signal CK' relative to the primary horizontal sync pulses to determine when to initiate read operations for the memory 68 and when to switch the multiplexer 26 between providing primary and secondary drive signals to the display device 28. Read address generator 24 provides a read address signal, RADDR, and read control signals RCS, to the field memory 68 and a primary/secondary image selection signal, P/S to the multiplexer 26.
The write address generator circuitry 70, read address generator circuitry 24 and field memory 68 are not a part of the present invention and, so, are not described in detail. Exemplary circuitry for subsampling, storing, and retrieving the signal which produces the insert image is described in the U.S. Pat. Nos. 4,249,213 entitled "Picture-in-Picture Television Receiver" and 4,139,860 entitled "Television Receiver Equipped for Simultaneously Showing Several Programs" which are hereby incorporated by reference.
The Read address generator 24, it is recalled, operates in synchronism with the skew corrected clock signal CK'. This signal is generated as follows. Primary composite video signals from source 10 are applied to an ADC 17 which is clocked by the signal CK provided by the PLL 56. ADC 17 applies the sampled primary composite video signals to a DPU 20. DPU 20, which includes sync separator 18 and skew measuring circuitry 19 may be identical to the DPU 60 described above. The sync separator 18 develops the primary vertical sync signal, PVS, and the primary horizontal sync signal, PHS, from the primary composite video signals. The signal PHS, the horizontal sync period value HSP, and the clock signal CK are applied to the skew measuring circuitry 19. Circuitry 19 is functionally identical to the skew measuring circuitry 59 described above. It measures the time difference between the center of each pulse of the signal PHS and the leading edge of the immediately preceding pulse of the clock signal CK. The fractional part of the signal, PSK, provided by the skew measuring circuitry 19 is a four bit value indicating the skew for each primary horizontal scan line in units of one-sixteenth of the period of the clock signal CK. The integer part of the signal PSK is applied to the sync separator 18 as set forth above in reference to DPU 60. The fractional part of the signal PSK and the signal CK are applied to the skew correcting circuitry 22. Circuitry 22 may be a programmable delay element similar to that shown in FIG. 5.
In FIG. 5, the clock signal CK is applied to the input termnal of an inverter I1 which is the first inverter in a chain of thirty series-connected inverters. The inverter chain is organized as fifteen pairs of inverters, I1 and I1 ' through I15 and I15 '. The input terminal to the inverter I1 and the output terminals of all of the pairs, i.e. I1 ', I2 ' . . . I15 ' are connected to respectively different data input terminals of the multiplexer 500. The control input port of multiplexer 500 is coupled to receive the fractional part of the primary skew signal, PSK, provided by the skew measuring circuitry 19. Each pair of inverters in the chain has a signal propogation delay of approximately one-sixteenth of the period of clock signal CK so the output terminals of each of the pairs provide clock signals delayed by between one-sixteenth and fifteen-sixteenths of a clock period. The multiplexer 500 is conditioned by the fractional part of the signal PSK to provide, as its output signal CK', the signal CK when PSK is zero, the signal at the output terminal of inverter of I1 ' when PSK is one, the signal at the output terminal of inverter I2 ' when PSK is two, and so on, providing the signal at the output terminal of inverter I15 ' when PSK is fifteen. Accordingly, the signal CK' provided by the skew correcting circuitry 22 is a clock signal CK delayed by an amount of time approximately equal to the value of the fractional part of PSK times one-sixteenth of the period of the signal CK. As set forth above, in reference to FIG. 1, this signal is a skew corrected clock signal, which is to say a clock signal aligned with the horizontal sync signal PHS from line-to-line.
The samples provided by the memory 68 in synchronism with the skew corrected clock signal CK' are applied to a digital-to-analog converter (DAC) 72 which is clocked by the skew corrected clock signal CK'. DAC 72 provides analog signals representing the secondary luminance and (R-Y) and (B-Y) color difference signals to the matrix 74. Matrix 74 is a conventional analog matrix which converts secondary luminance and color difference signals into the color signals RS, GS, and BS for application to the multiplexer 26 as set forth above.
The analog multiplexer 26 is controlled by the image selection signal P/S provided by the read address generator 24 to apply either primary or secondary signals to the display device 28 to develop composite PIP images.
FIG. 6 is a block diagram showing a
ternative circuitry to correct for skew in the primary signal. This embodiment uses an interpolation scheme which is the same as is used to correct for the skew of the secondary signal. The read address generator circuitry 24' is clocked by the signal CK but is otherwise the same as the circuitry 24 described in reference to FIG. 2. From the clock signal CK and the primary horizontal and vertical sync signals PHS and PVS, read address generator circuitry 24' develops the read address signal RADDR and the read control signals RCS which control the reading of the subsampled secondary luminance and color difference signals from the PIP field memory 68. The luminance samples, Yss, are applied to skew correcting circuitry 22' which is responsive to the fractional part of the signal PSK. Circuitry 22' may be identical to the skew correcting circuitry 62 described above in reference to FIG. 2. Circuitry 22' interpolates between successive ones of the samples Yss to provide samples having values representing a signal delayed by the skew value. In other words, substantially the same signal as would be represented by the samples read from the memory in synchronism with a skew corrected clock signal. The luminance samples developed by the skew correcting circuitry 22' are applied to a DAC 72'. The (R-Y) and (B-Y) color difference samples provided by the field memory 68' are applied to the DAC 72' via the compensating delay elements 602 and 604 respectively. Delay elements 602 and 604 compensate for processing delay in the skew correcting circuitry 22'. As set forth in reference to the skew correcting circuitry 62, only the luminance signals need skew correction since the eye is less sensitive to changes in color than to changes in brightness. Nonetheless, it is contemplated that the delay elements 602 and 604 may be replaced by skew correcting circuitry similar to the circuitry 22' if skew correction of the color difference samples is found to be desirable. The DAC 72' is clocked by the uncorrected clock signal CK but is otherwise the same as the DAC 72 described with reference to FIG. 2. DAC 72' provides analog luminance and color difference signals representing the reduced secondary signal to the matrix 74.
F
IG. 3 is a block diagram of an alternative embodiment of the invention in which both the primary and secondary signals are processed digitally. A single clock signal, PCK, which is phase locked to the primary color synchronizing burst signal, is used for both the primary and secondary processing circuitry. Since the secondary signals are sampled by a clock which is not phase locked to the secondary color burst signal, this embodiment of the invention includes circuitry to adjust the phase of the secondary chrominance signals to ensure proper color reproduction.
In the PIP system shown in FIG. 3, analog composite video signals from a source of primary composite video signals 310 are applied to an ADC 317. ADC 317 is responsive to the primary burst locked clock signal PCK to provide digital samples representing the analog primary video signals. These samples are applied to a Y/C separation filter 312 and to the DPU 320. DPU 320 is, for example, identical to the DPUs 20 and 60 described above. It provides the primary vertical and horizontal synchronization signals, PHS and PVS, a primary burst gate signal, PBG, and a signal, PSK, representing the skew of the clock signal, PCK, relative to the primary horizontal sync signal, PHS, as a proper fraction of the clock period. The Y/C separation filter 312, which may be identical to the filter 54, separates the luminance and chrominance components from the primary composite video signals.
The primary chrominance signals from filter 312 and the burst gate signal PBG from sync separator 318 are applied to the PLL 321. PLL 321, which may contain circuitry identical to that used by the PLL 56, generates the clock signal PCK having a frequency of substantially 4fc that is phase-locked to the color burst component of the primary signal.
The primary luminance and chrominance signal components are applied to the primary chroma/luma processor 314. Chroma/luma processor 314 provides processed luminance signals and (R-Y) and (B-Y) color difference signals to the DAC 315. DAC 315 converts the digital luminance and color difference signals into analog form and applies the analog signals to an RGB matrix 316. Matrix 316 develops the red, green, and blue color signals which represent the primary image, and applies them to a first set of signal input terminals of a multiplexer 326. Multiplexer 326, selects between the color signals representing the primary image and color signals representing the secondary image, which are applied to a second set of signal input terminals, to drive the display device 328. Apparatus which generates the color signals for the secondary image and which generates the selection signal, P/S, for the multiplexer 326 is described below.
Analog composite video signals from a source of secondary composite video signals 350 are applied to an ADC 352. ADC 352 is responsive to the primary sampling clock signal PCK for providing samples representing secondary composite video signals to the Y/C separation filter 354 and to the DPU 360. DPU 360, for example, is identical to the DPUs 20 and 60 described above. It provides the secondary horizontal and vertical synchronization signals, SHS and SVS respectively, a secondary burst gate signal SBG, and a signal, SSK, representing the skew of the clock signal PCK relative to the secondary horizontal sync signal SHS as a proper fraction of the clock period.
Y/C separation filter 354, separates the secondary composite video samples into a luminance signal component and a chrominance signal component. The luminance signal component and the signal SSK from skew measuring circuitry 359 are applied to skew correcting circuitry 362. The circuitry 362 may be identical to the circuitry described with reference to FIG. 4. It produces luminance samples having equal skew from line-to-line relative to the secondary horizontal sync signal SHS. These samples are applied to the secondary chroma/luma processor 364. The chrominance samples from filter 354 are applied to the processor 364 via the delay element 363. Delay element 363 compensates for the processing delays incurred by the luminance samples in the skew correction circuitry 362 by delaying the chrominance samples by two sample periods.
The secondary luma/chroma processor 364 processes the luminance signal and demodulates the chrominance signal into two quadrature phase related color difference signals. In this instance, however, the color difference signals provided by the processor 364 may not be (R-Y) and (B-Y) signals. The demodulator in the chroma/luma processor 364 will provide (R-Y) and (B-Y) signals only when the sampling clock signal has a frequency of 4fc and is phase locked to the color burst component of the secondary signal. In this embodiment, the sampling clock signal used to develop the secondary samples is phase locked to the primary color burst component. Since the primary and secondary signals may be from different sources, there may be phase and frequency differences between their respective color burst signals. Consequently, there may be phase errors in the demodulated color difference signals provided by the processor 364 relative to the (R-Y) and (B-Y) phases of the secondary signal. The present embodiment includes chrominance phase error correction circuitry 365 to detect and correct phase errors in the color difference signals provided by processor 364. This circuit is not a part of the present invention. Suitable circuitry 365 may be built by one skilled in the art from the teachings of the patent application Ser. No. 567,190 entitled "A Digital Video Signal Processing System Using Asynchronous A-to-D Encoding", which is hereby incorporated by reference. Briefly, the circuitry 365 converts the two color difference signals into a phase angle signal and an amplitude signal. The phase signal is compared against a reference phase during the secondary burst interval. The difference between the burst phase and the reference phase is used to correct the phase and amplitude signals in a closed loop control system. The corrected phase and amplitude signals are then processed to develop at least two color difference signals (e.g. (R-Y) and (B-Y)).
The phase corrected color difference signals provided by the circuitry 365 and the luminance signal provided by processor 364 via compensating delay element 367 are applied to the PIP field memory 368. The PIP field memory 368, memory write address generator circutry 370 and memory read address generator circuitry 324 may be similar to the respective field memory 68, and memory write and read address generator circutry 70 and 24 of FIG. 2. The circuitry 370 and 324 are responsive to the clock signal PCK and skew corrected clock signal PCK' respectively, but otherwise operate identically to the circuitry described above.
The skew corrected clock signal PCK' is developed by the skew correction circuitry 322. Circuitry 322,which may be similar to the circuitry 22, delays the clock signal PCK by the measured skew value times one-sixteenth of the period of PCK, to produce a skew corrected clock signal PCK'. It is contemplated that circuitry similar to that shown in FIG. 6 may be used in place of the skew correcting circuitry 622 to correct for the skew of the primary signal.
The samples provided by the PIP field memory 368 under control of the memory output address and timing control circuitry are applied to a DAC 372. DAC 372, synchronous with the skew corrected clock signal PCK', develops analog luminance and (R-Y) and (B-Y) color difference signals representing the secondary image and applies these samples to the matrix 374. Matrix 374 converts these luminance and color difference signals into red, green and blue color signals. These color signals, which represent the secondary image, are applied to the second set of signal input terminals of the analog multiplexer 326 as described above.
Although the embodiments described above use digital processing circuitry and use random access memory for the field store, it is contemplated that similar skew correction circuitry could be used with analog sampled data signals and that analog or digital shift register memories could be used for the field store.
The timing errors relevant to the present invention occur when either the primary or secondary signal is a nonstandard signal. As used in this application, the term nonstandard signal means a video signal having a horizontal line period which may vary in width by, for example, 4 ns or more from the horizontal line period set by the signal standard to which the video signal nominally conforms (e.g. NTSC, PAL, or SECAM).
To understand how these timing errors may affect the inset image, it is helpful to know how the secondary signal is processed and displayed. In a conventional PIP display system, the secondary signal is sampled at instants determined by a sampling clock signal which, desirably, bears a fixed relationship to the horizontal line scanning frequency of the secondary signal. To aid separation of the luminance and chrominance components of color television signals, the sampling clock signal has a frequency that is a multiple of the chrominance subcarrier frequency which is itself a harmonic of one-half the horizontal line scanning frequency. This sampling clock signal may be developed by a phase locked loop which locks the clock signal to the color reference burst component of the composite video signals.
The secondary signals are separated into their component parts, generally a luminance signal and two color difference signals, and then subsampled both vertically and horizontally to develop signals which represent a reduced-size image. The lines of samples taken during one field of the secondary signal are stored in a memory. These samples are then read from the memory for display using a clock signal which is desirably related to the horizontal line scanning frequency of the primary signal.
When the secondary signal originates from a video tape recorder (VTR), video disk player or home computer, the frequency of the color burst signal may be relatively stable while the frequency of the horizontal line scanning signal may vary significantly from line to line. This variation may be caused by stretching of the tape, defects in the disk, motor speed variations in either the VTR or disk player, or inaccuracies in the frequencies used by the home computer. Since the sampling clock signal is locked to the burst signal, corresponding sampling points on successive lines may be shifted or skewed relative to each other. When these lines of samples are displayed in synchronism with the primary signal, the corresponding samples do not line up vertically. Consequently vertical lines in the inset image may appear jagged, if the timing errors randomly change the period of the horizontal sync signal, or tilted if there is a fixed error in the horizontal sync period. Assuming a 3:1 reduction in the secondary image, a timing difference of 12 ns or more in successive horizontal line periods of the secondary signal may produce noticeable skew distortion in the inset image.
Timing errors in the primary signals change the relative time difference between primary horizontal sync pulses, which define the edges of the primary image, and the first samples in lines of the inset image. Primary signal timing errors that cause the periods of successive horizontal sync pulses to vary from the applicable signal standard by 4 ns or more may produce noticeable skew distortion in the inset image. This distortion causes the entire inset image to appear jagged or tilted.
To gain a better understanding of skew and the methods which may be used to compensate for it, consider the waveforms shown in FIG. 1. The waveform A represents a portion of one horizontal line of, e.g. luminance signal, including the horizontal synchronizing pulse (note the waveforms of FIG. 1 are not drawn to scale). Waveforms B, C and C' represent sampling (system) clock waveforms. The pulses of waveform B are assumed to occur at the points in time that a subcarrier locked clock, locked to a standard signal, would occur. Put another way, if waveform A corresponds to n lines of an image, then waveform B represents the desired sampling (system) clock for each successive line, i.e. without skew. A clock signal having constant skew may also be desirable. In either a zero skew or a constant skew system, the sampling clock pulse r always occurs at the same point in time relative to the HSYNC pulse. This point in time is represented by the sample S2 on waveform A. Waveform C represents a subcarrier locked clock which exhibits a degree of skew. The number of pulses per line period contained in waveform C may not be constant from line-to-line. Generally, the difference in the number of whole clock pulses in a line period can be compensated for in the phase locked loop which generates the horizontal synchronizing signal. The sampling phase error (skew) which is a fractional portion of a clock period, however, may only be corrected by operation on the samples themselves or on the sampling clock signal.
One method of correction is to adjust the sample values on a line-by-line basis so that the adjusted samples conform to samples that would be taken by a clock with zero skew or with some constant skew. For example, the sample values generated by the clock signal of waveform C may be adjusted to equal or approximate corresponding sample values that would be generated by the clock signal of waveform B. In the FIG. 1, clock pulse r' of waveform C is assumed to correspond to clock pulse r of waveform B. Clock pulse r' is advanced in time or skewed by one-half of one clock period, TS, with respect to clock pulse r. Clock pulse r' generates a sample value S1. Desirably, clock pulse r' should occur coincident with clock pulse r and generate the sample value S2. Replacing the sample taken coincident with clock pulse r' with a sample having a value approximately equal to S2 effectively advances the timing of the signal taken with the sampling clock signal C so that it matches the signal which would have been taken had the zero-skew sampling clock signal B been used. Neglecting the complications of chrominance decoding, an alternative method of skew correction is to adjust the phase of the sampling clock signal on a line-by-line basis so that it approximately matches the phase of the desired clock signal B or some other clock signal which exhibits equal skew from line to line. The waveform C' represents the clock signal C delayed an amount of time substantially equal to the skew. Samples taken with this delayed clock signal approximate samples taken with the desired clock signal, B.
The first skew correction method may be used to correct skew errors in the secondary signal since it does not affect the phase of the sampling clock signal. It is recalled that the phase of this clock signal cannot be changed without affecting the processing of the secondary chrominance signal components. The second skew correction method may be used to compensate for skew errors in the primary signal when the samples representing the separated luminance and color difference signal components of the secondary image are retrieved from the secondary field memory for display.
SUMMARY OF THE INVENTION
The present invention is embodied in apparatus which compensates for timing errors in a first video signal relative to a second, stored video signal. This apparatus includes circuitry for measuring the time interval between a horizontal synchronizing pulse of the first signal and a pulse of the clock signal which controls the retrieval and display of the second signal. The apparatus further includes circuitry with changes the timing of the second signal relative to the horizontal sync component of the first signal, as the second signal is displayed, to compensate for any variations in the measured time intervals from line-to-line.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a timing diagram useful in describing skew and methods of skew correction.
FIG. 2 is a block diagram of a PIP television display system incorporating the present invention.
FIG. 3 is a block diagram of a digital PIP television display system incorporating the present invention.
FIGS. 4 and 5 are a block diagrams showing skew correction circuitry which may be used in the display devices shown in FIGS. 2 and 3.
FIG. 6 is a block diagram of alternative skew correcting apparatus which may be used in the display devices shown in FIGS. 2 and 3.
DETAILED DESCRIPTION OF THE INVENTION
In the drawings, broad arrows represent busses for multiple-bit parallel digital signals and line arrows represent connections carrying analog signals or single bit digital signals. Depending on the processing speed of the devices, compensating delays may be required in certain of the signal paths. One skilled in the art of digital signal processing circuit design would know where such delays would be needed in a particular system.
FIG. 2 is a block diagram of a PIP display device in which the primary signal is processed using conventional analog apparatus and the secondary signal is processed digitally. This circuitry uses a single clock signal, synchronized to the secondary burst signal, both for sampling and processing the secondary signal and for displaying the secondary image as an inset in the main image. A source of primary composite video signals 10 applies the primary video signals to a Y/C separation filter 12. Filter 12, which may include conventional low-pass and high-pass filters, separates the composite video signals into primary luminance signals, YP, and primary chrominance signals Cp. The primary luminance and chrominance signals are applied to a primary chroma/luma processor 14 which may include, for example, band shaping filters for peaking the high frequency components of the luminance signals to develop a signal Y'P and a chrominance signal demodulator for deriving the baseband color difference signals (R-Y)P and (B-Y)P from the primary chrominance signals, CP. The signals Y'P, (R-Y)P, and (B-Y)P applied to a matrix 16 which combines the signals to develop the color signals RP, GP and BP. These signals are applied to one set of signal input terminals of an analog multiplexer 26, the output of which drives a cathode ray tube (CRT) 28. The color signals RS, GS and BS developed from the secondary signal are applied to a second set of signal input terminals of the multiplexer 26. These signals are developed by apparatus described below.
A source of secondary composite video signals 50, which may include the tuner, IF amplifier and video detector of a conventional color television receiver, provides secondary composite video signals to an analog-to-digital converter (ADC) 52. ADC 52 samples and digitizes the secondary composite video signals at instants determined by the sampling clock signal CK. A phase-locked-loop (PLL) 56, described below, generates the signal, CK, which has a frequency 4fc substantially equal to four times the chrominance subcarrier frequency, fc. The signal CK is phase locked to the color synchronizing burst component of the secondary video signals.
ADC 52 provides digitized secondary video signals to a Y/C separation filter 54. Filter 54 may be a conventional digital filter having a clock input terminal coupled to receive the signal CK. Filter 54 may include, for example, an FIR filter which passes the chrominance signal components of composite video signal to the relative exclusion of luminance signal components and a subtracter for subtracting the chrominance signal components from the composite signal to develop luminance signal components.
The clock signal CK is applied to the skew measuring circuitry 59. Exemplary skew measuring circuitry 59 accumulates the fractional part of the horizontal skew period values, HSP, provided by the sync separator circuitry 58 to develop a secondary skew signal, SSK. The integer part of the signal SSK is fed back to the sync separator circuitry 58, where it is used in the phase-locked-loop to update the horizontal sync period measurement. The fractional part of the signal SSK is retained in the accumulator of the skew measuring circuitry 59 and applied as skew values to the skew correcting circuitry 62. As used in the present embodiment, the fractional part of the signal SSK represents the time interval between the center of the respective phase locked horizontal sync pulse and the leading edge of the clock pulse which occurs immediately before the center of the respective horizontal sync pulse. This interval is measured with a resolution substantially equal to one-sixteenth of the period of the signal CK. The sync separator circuitry 58 and the skew measuring circuitry 59 are of the type contained in the integrated circuit DPU 2532 manufactured by ITT Intermetall GmbH and which is described at pages 47-72 of the data book "Digit 2000 NTSC Double-scan VLSI Digital TV System" edition 1985/5 of ITT Intermetall, Freiburg, W. Germany.
Exem
plary skew error correcting circuitry 62 is shown in FIG. 4. This circuitry interpolates between successive input samples to provide output samples that are substantially equivalent to the samples which would have been taken synchronous with a sampling clock signal having zero skew. The circuitry shown in FIG. 4 may be divided into two parts, a linear interpolator and a correction circuit. Luminance samples YS are applied to a delay element 410, which delays the samples by one period of the clock signal CK. The delayed samples are applied to a multiplier 412 which scales the samples by a factor K. The factor K may be a value between zero and one and is provided by a read only memory (ROM) 424 in response to the secondary skew signal SSK. Luminance samples YS are also applied to a multiplier 414 which scales these undelayed samples by a factor 1-K, also provided by ROM 424. The samples provided by the multipliers 412 and 414 are summed in adder 416. The samples provided by adder 416 are linearly interpolated samples. If the frequency components of the sampled signals YS are an order of magnitude or more lower than the sampling frequency, the apparent delay of the interpolated samples is given by the product KTS, where TS is the period of the sampling clock signal CK. As the frequency components of the sampled signals approach the sampling frequency, however, the amount by which Ys appears to have been delayed becomes a function of the levels of its higher frequency components as well as of K. The correction circuit, which includes filter 422, multiplier 428 and adder 420 compensates for the frequency induced delay components. Luminance signals YS are applied to the filter 422 which has the transfer function T422 =-1+Z-1 +Z-2 -Z-3 expressed in Z transform notation. The samples provided by filter 422 are scaled by a factor C in multiplier 428. The factor C is provided by ROM 424 in response to the secondary skew signal, SSK. The samples developed by adder 416 are applied to a delay element 418 which compensates for the processing time through filter 422. These delayed samples are then added to the samples from multiplier 428 by an adder 420.
The combination of the linear interpolator and the correcting filter produce signals having an apparent delay of (1+K)Ts where the signals to be delayed have components with frequencies as high as one-third of the frequency of the sampling clock signal. In the NTSC system, for example, where the sampling clock frequency is approximately 14.3 MHz this skew correcting circuit provides uniformly spaced delays for luminance signals which may have frequency components up to 4.2 MHz. I defines the contents of ROM 424 to achieve delay steps of one-sixteenth of a sampling clock period.
| TABLE I |
| ______________________________________ |
| DELAY TOTAL SSK K 1-K C CHANGE DELAY |
| ______________________________________ |
15 1/16 15/16 1/32 TS /16 17TS /16 14 2/16 14/16 1/32 2TS /16 18TS /16 13 3/16 13/16 2/32 3TS /16 19TS /16 12 4/16 12/16 2/32 4TS /16 20TS /16 11 5/16 11/16 2/32 5TS /16 21TS /16 10 6/16 10/16 3/32 6TS /16 22TS /16 9 7/16 9/16 3/32 7TS /16 23TS /16 8 8/16 8/16 3/32 8TS /16 24TS /16 7 9/16 7/16 3/32 9TS /16 25TS /16 6 10/16 6/16 3/32 10TS /16 26TS /16 5 11/16 5/16 3/32 11TS /16 27TS /16 4 12/16 4/16 2/32 12TS /16 28TS /16 3 13/16 3/16 2/32 13TS /16 29TS /16 2 14/16 2/16 1/32 14TS /16 30TS /16 1 15/16 1/16 1/32 15TS /16 31TS /16 0 1 0 0 TS 2TS |
| ______________________________________ |
The luminance samples from skew correcting circuitry 62 and the chrominance samples from delay element 63 are applied to a secondary chroma/luma processor 64. Processor 64 may include, for example, an FIR band shaping filter for peaking the frequency spectrum of the digital luminance signals to provide a modified secondary luminance signal YS ' and a digital chrominance demodulator for developing samples which represent the baseband secondary color difference signals (R-Y)S and (B-Y)S.
The signals YS ', (R-Y)S and (B-Y)S are applied to PIP field memory 68 where they are subsampled and stored under control of the write address generator circuitry 70. Memory 68 may be a conventional random access memory having a sufficient number of storage cells to hold one field of the subsampled secondary signal. This memory may be organized as three separate field memories, one for the luminance signal and one for each of the two color difference signals, or it may be organized as a single field memory with the sampled luminance and color difference signals combined into a single sampled signal. For example, these signals may be combined by alternately concatenating samples of the two color difference signals to samples of the luminance signal.
Data from the secondary chroma/luma processor 64 is written into the field memory 68 under control of the memory address generator circuity 70. The circuitry 70 develops write address signals, WADDR, and other control signals WCS, as may be needed from the clock signal CK, and the secondary vertical and horizontal sync signals SVS and SHS respectively. The write address generator circuitry 70 operates to subsample the secondary signal in, for example, a three-to-one ratio both vertically and horizontally by providing address values and control signals for the memory 68 at appropriate times. Samples representing lines of the subsampled secondary image are read from the PIP field memory 68 under control of the read address generator circuitry 24. The signals applied to circuitry 24 are the primary vertical and horizontal sync signals, PVS and PHS respectively, and a skew corrected clock signal CK'. The circuitry 24 may for example, count pulses of the horizontal sync signal, PHS, relative to the vertical sync pulses, PVS, and pulses of the signal CK' relative to the primary horizontal sync pulses to determine when to initiate read operations for the memory 68 and when to switch the multiplexer 26 between providing primary and secondary drive signals to the display device 28. Read address generator 24 provides a read address signal, RADDR, and read control signals RCS, to the field memory 68 and a primary/secondary image selection signal, P/S to the multiplexer 26.
The write address generator circuitry 70, read address generator circuitry 24 and field memory 68 are not a part of the present invention and, so, are not described in detail. Exemplary circuitry for subsampling, storing, and retrieving the signal which produces the insert image is described in the U.S. Pat. Nos. 4,249,213 entitled "Picture-in-Picture Television Receiver" and 4,139,860 entitled "Television Receiver Equipped for Simultaneously Showing Several Programs" which are hereby incorporated by reference.
The Read address generator 24, it is recalled, operates in synchronism with the skew corrected clock signal CK'. This signal is generated as follows. Primary composite video signals from source 10 are applied to an ADC 17 which is clocked by the signal CK provided by the PLL 56. ADC 17 applies the sampled primary composite video signals to a DPU 20. DPU 20, which includes sync separator 18 and skew measuring circuitry 19 may be identical to the DPU 60 described above. The sync separator 18 develops the primary vertical sync signal, PVS, and the primary horizontal sync signal, PHS, from the primary composite video signals. The signal PHS, the horizontal sync period value HSP, and the clock signal CK are applied to the skew measuring circuitry 19. Circuitry 19 is functionally identical to the skew measuring circuitry 59 described above. It measures the time difference between the center of each pulse of the signal PHS and the leading edge of the immediately preceding pulse of the clock signal CK. The fractional part of the signal, PSK, provided by the skew measuring circuitry 19 is a four bit value indicating the skew for each primary horizontal scan line in units of one-sixteenth of the period of the clock signal CK. The integer part of the signal PSK is applied to the sync separator 18 as set forth above in reference to DPU 60. The fractional part of the signal PSK and the signal CK are applied to the skew correcting circuitry 22. Circuitry 22 may be a programmable delay element similar to that shown in FIG. 5.
In FIG
. 5, the clock signal CK is applied to the input termnal of an inverter I1 which is the first inverter in a chain of thirty series-connected inverters. The inverter chain is organized as fifteen pairs of inverters, I1 and I1 ' through I15 and I15 '. The input terminal to the inverter I1 and the output terminals of all of the pairs, i.e. I1 ', I2 ' . . . I15 ' are connected to respectively different data input terminals of the multiplexer 500. The control input port of multiplexer 500 is coupled to receive the fractional part of the primary skew signal, PSK, provided by the skew measuring circuitry 19. Each pair of inverters in the chain has a signal propogation delay of approximately one-sixteenth of the period of clock signal CK so the output terminals of each of the pairs provide clock signals delayed by between one-sixteenth and fifteen-sixteenths of a clock period. The multiplexer 500 is conditioned by the fractional part of the signal PSK to provide, as its output signal CK', the signal CK when PSK is zero, the signal at the output terminal of inverter of I1 ' when PSK is one, the signal at the output terminal of inverter I2 ' when PSK is two, and so on, providing the signal at the output terminal of inverter I15 ' when PSK is fifteen. Accordingly, the signal CK' provided by the skew correcting circuitry 22 is a clock signal CK delayed by an amount of time approximately equal to the value of the fractional part of PSK times one-sixteenth of the period of the signal CK. As set forth above, in reference to FIG. 1, this signal is a skew corrected clock signal, which is to say a clock signal aligned with the horizontal sync signal PHS from line-to-line. The samples provided by the memory 68 in synchronism with the skew corrected clock signal CK' are applied to a digital-to-analog converter (DAC) 72 which is clocked by the skew corrected clock signal CK'. DAC 72 provides analog signals representing the secondary luminance and (R-Y) and (B-Y) color difference signals to the matrix 74. Matrix 74 is a conventional analog matrix which converts secondary luminance and color difference signals into the color signals RS, GS, and BS for application to the multiplexer 26 as set forth above.
The analog multiplexer 26 is controlled by the image selection signal P/S provided by the read address generator 24 to apply either primary or secondary signals to the display device 28 to develop composite PIP images.
FIG. 6 is a block diagram showing a
ternative circuitry to correct for skew in the primary signal. This embodiment uses an interpolation scheme which is the same as is used to correct for the skew of the secondary signal. The read address generator circuitry 24' is clocked by the signal CK but is otherwise the same as the circuitry 24 described in reference to FIG. 2. From the clock signal CK and the primary horizontal and vertical sync signals PHS and PVS, read address generator circuitry 24' develops the read address signal RADDR and the read control signals RCS which control the reading of the subsampled secondary luminance and color difference signals from the PIP field memory 68. The luminance samples, Yss, are applied to skew correcting circuitry 22' which is responsive to the fractional part of the signal PSK. Circuitry 22' may be identical to the skew correcting circuitry 62 described above in reference to FIG. 2. Circuitry 22' interpolates between successive ones of the samples Yss to provide samples having values representing a signal delayed by the skew value. In other words, substantially the same signal as would be represented by the samples read from the memory in synchronism with a skew corrected clock signal. The luminance samples developed by the skew correcting circuitry 22' are applied to a DAC 72'. The (R-Y) and (B-Y) color difference samples provided by the field memory 68' are applied to the DAC 72' via the compensating delay elements 602 and 604 respectively. Delay elements 602 and 604 compensate for processing delay in the skew correcting circuitry 22'. As set forth in reference to the skew correcting circuitry 62, only the luminance signals need skew correction since the eye is less sensitive to changes in color than to changes in brightness. Nonetheless, it is contemplated that the delay elements 602 and 604 may be replaced by skew correcting circuitry similar to the circuitry 22' if skew correction of the color difference samples is found to be desirable. The DAC 72' is clocked by the uncorrected clock signal CK but is otherwise the same as the DAC 72 described with reference to FIG. 2. DAC 72' provides analog luminance and color difference signals representing the reduced secondary signal to the matrix 74. F
IG. 3 is a block diagram of an alternative embodiment of the invention in which both the primary and secondary signals are processed digitally. A single clock signal, PCK, which is phase locked to the primary color synchronizing burst signal, is used for both the primary and secondary processing circuitry. Since the secondary signals are sampled by a clock which is not phase locked to the secondary color burst signal, this embodiment of the invention includes circuitry to adjust the phase of the secondary chrominance signals to ensure proper color reproduction. In the PIP system shown in FIG. 3, analog composite video signals from a source of primary composite video signals 310 are applied to an ADC 317. ADC 317 is responsive to the primary burst locked clock signal PCK to provide digital samples representing the analog primary video signals. These samples are applied to a Y/C separation filter 312 and to the DPU 320. DPU 320 is, for example, identical to the DPUs 20 and 60 described above. It provides the primary vertical and horizontal synchronization signals, PHS and PVS, a primary burst gate signal, PBG, and a signal, PSK, representing the skew of the clock signal, PCK, relative to the primary horizontal sync signal, PHS, as a proper fraction of the clock period. The Y/C separation filter 312, which may be identical to the filter 54, separates the luminance and chrominance components from the primary composite video signals.
The primary chrominance signals from filter 312 and the burst gate signal PBG from sync separator 318 are applied to the PLL 321. PLL 321, which may contain circuitry identical to that used by the PLL 56, generates the clock signal PCK having a frequency of substantially 4fc that is phase-locked to the color burst component of the primary signal.
The primary luminance and chrominance signal components are applied to the primary chroma/luma processor 314. Chroma/luma processor 314 provides processed luminance signals and (R-Y) and (B-Y) color difference signals to the DAC 315. DAC 315 converts the digital luminance and color difference signals into analog form and applies the analog signals to an RGB matrix 316. Matrix 316 develops the red, green, and blue color signals which represent the primary image, and applies them to a first set of signal input terminals of a multiplexer 326. Multiplexer 326, selects between the color signals representing the primary image and color signals representing the secondary image, which are applied to a second set of signal input terminals, to drive the display device 328. Apparatus which generates the color signals for the secondary image and which generates the selection signal, P/S, for the multiplexer 326 is described below.
Analog composite video signals from a source of secondary composite video signals 350 are applied to an ADC 352. ADC 352 is responsive to the primary sampling clock signal PCK for providing samples representing secondary composite video signals to the Y/C separation filter 354 and to the DPU 360. DPU 360, for example, is identical to the DPUs 20 and 60 described above. It provides the secondary horizontal and vertical synchronization signals, SHS and SVS respectively, a secondary burst gate signal SBG, and a signal, SSK, representing the skew of the clock signal PCK relative to the secondary horizontal sync signal SHS as a proper fraction of the clock period.
Y/C separation filter 354, separates the secondary composite video samples into a luminance signal component and a chrominance signal component. The luminance signal component and the signal SSK from skew measuring circuitry 359 are applied to skew correcting circuitry 362. The circuitry 362 may be identical to the circuitry described with reference to FIG. 4. It produces luminance samples having equal skew from line-to-line relative to the secondary horizontal sync signal SHS. These samples are applied to the secondary chroma/luma processor 364. The chrominance samples from filter 354 are applied to the processor 364 via the delay element 363. Delay element 363 compensates for the processing delays incurred by the luminance samples in the skew correction circuitry 362 by delaying the chrominance samples by two sample periods.
The secondary luma/chroma processor 364 processes the luminance signal and demodulates the chrominance signal into two quadrature phase related color difference signals. In this instance, however, the color difference signals provided by the processor 364 may not be (R-Y) and (B-Y) signals. The demodulator in the chroma/luma processor 364 will provide (R-Y) and (B-Y) signals only when the sampling clock signal has a frequency of 4fc and is phase locked to the color burst component of the secondary signal. In this embodiment, the sampling clock signal used to develop the secondary samples is phase locked to the primary color burst component. Since the primary and secondary signals may be from different sources, there may be phase and frequency differences between their respective color burst signals. Consequently, there may be phase errors in the demodulated color difference signals provided by the processor 364 relative to the (R-Y) and (B-Y) phases of the secondary signal. The present embodiment includes chrominance phase error correction circuitry 365 to detect and correct phase errors in the color difference signals provided by processor 364. This circuit is not a part of the present invention. Suitable circuitry 365 may be built by one skilled in the art from the teachings of the patent application Ser. No. 567,190 entitled "A Digital Video Signal Processing System Using Asynchronous A-to-D Encoding", which is hereby incorporated by reference. Briefly, the circuitry 365 converts the two color difference signals into a phase angle signal and an amplitude signal. The phase signal is compared against a reference phase during the secondary burst interval. The difference between the burst phase and the reference phase is used to correct the phase and amplitude signals in a closed loop control system. The corrected phase and amplitude signals are then processed to develop at least two color difference signals (e.g. (R-Y) and (B-Y)). The phase corrected color difference signals provided by the circuitry 365 and the luminance signal provided by processor 364 via compensating delay element 367 are applied to the PIP field memory 368. The PIP field memory 368, memory write address generator circutry 370 and memory read address generator circuitry 324 may be similar to the respective field memory 68, and memory write and read address generator circutry 70 and 24 of FIG. 2. The circuitry 370 and 324 are responsive to the clock signal PCK and skew corrected clock signal PCK' respectively, but otherwise operate identically to the circuitry described above.
The skew corrected clock signal PCK' is developed by the skew correction circuitry 322. Circuitry 322,
which may be similar to the circuitry 22, delays the clock signal PCK by the measured skew value times one-sixteenth of the period of PCK, to produce a skew corrected clock signal PCK'. It is contemplated that circuitry similar to that shown in FIG. 6 may be used in place of the skew correcting circuitry 622 to correct for the skew of the primary signal. The samples provided by the PIP field memory 368 under control of the memory output address and timing control circuitry are applied to a DAC 372. DAC 372, synchronous with the skew corrected clock signal PCK', develops analog luminance and (R-Y) and (B-Y) color difference signals representing the secondary image and applies these samples to the matrix 374. Matrix 374 converts these luminance and color difference signals into red, green and blue color signals. These color signals, which represent the secondary image, are applied to the second set of signal input terminals of the analog multiplexer 326 as described above.
Although the embodiments described above use digital processing circuitry and use random access memory for the field store, it is contemplated that similar skew correction circuitry could be used with analog sampled data signals and that analog or digital shift register memories could be used for the field store.
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