This chassis is fully transistorized closing the THYRISTOR technology phase of previous chassis types and version.
This chassis is a high performance type giving high beam current pictures and high durability and reliability (runs warm)
As any METZ is sophisticated and highly engineered and not easy.
METZ 7285 MALLORCA COLOR CHASSIS 681G Switched mode power supply
Supply is based on TDA4600 (SIEMENS).
Power supply Description based on TDA4601d (SIEMENS)
TDA4601 Operation. * The TDA4601 device is a single in line, 9 pin chip. Its predecessor was the TDA4600 device, the TDA4601 however has improved switching, better protection and cooler running. The (SIEMENS) TDA4601 power supply is a fairly standard parallel chopper switch mode type, which operates on the same basic principle as a line output stage. It is turned on and off by a square wave drive pulse, when switched on energy is stored in the chopper transformer primary winding in the form of a magnetic flux; when the chopper is turned off the magnetic flux collapses, causing a large back emf to be produced. At the secondary side of the chopper transformer this is rectified and smoothed for H.T. supply purposes. The advantage of this type of supply is that the high chopping frequency (20 to 70 KHz according to load) allows the use of relatively small H.T. smoothing capacitors making smoothing easier. Also should the chopper device go short circuit there is no H.T. output. In order to start up the TDA4601 I.C. an initial supply of 9v is required at pin 9, this voltage is sourced via R818 and D805 from the AC side of the bridge rectifier D801, also pin 5 requires a +Ve bias for the internal logic block. (On some sets pin 5 is used for standby switching). Once the power supply is up and running, the voltage on pin 9 is increased to 16v and maintained at this level by D807 and C820 acting as a half wave rectifier and smoothing circuit. PIN DESCRIPTIONS Pin 1 This is a 4v reference produced within the I.C. Pin 2 This pin detects the exact point at which energy stored in the chopper transformer collapses to zero via R824 and R825, and allows Q1 to deliver drive volts to the chopper transistor. It also opens the switch at pin 4 allowing the external capacitor C813 to charge from its external feed resistor R810. Pin 3 H.T. control/feedback via photo coupler D830. The voltage at this pin controls the on time of the chopper transistor and hence the output voltage. Normally it runs at Approximately 2v and regulates H.T. by sensing a proportion of the +4v reference at pin 1, offset by conduction of the photo coupler D830 which acts like a variable resistor. An increase in the conduction of transistor D830 and therefor a reduction of its resistance will cause a corresponding reduction of the positive voltage at Pin 3. A decrease in this voltage will result in a shorter on time for the chopper transistor and therefor a lowering of the output voltage and vice versa, oscillation frequency also varies according to load, the higher the load the lower the frequency etc. should the voltage at pin 3 exceed 2.3v an internal flip flop is triggered causing the chopper drive mark space ratio to extend to 244 (off time) to 1 (on time), the chip is now in over volts trip condition. Pin 4 At this pin a sawtooth waveform is generated which simulates chopper current, it is produced by a time constant network R810 and C813. C813 charges when the chopper is on and is discharged when the chopper is off, by an internal switch strapping pin 4 to the internal +2v reference, see Fig 2. The amplitude of the ramp is proportional to chopper drive. In an overload condition it reaches 4v amplitude at which point chopper drive is reduced to a mark-space ratio of 13 to 1, the chip is then in over current trip. The I.C. can easily withstand a short circuit on the H.T. rail and in such a case the power supply simply squegs quietly. Pin 4 is protected by internal protection components which limit the maximum voltage at this pin to 6.5v. Should a fault occur in either of the time constant components, then the chopper transistor will probably be destroyed. Pin 5 This pin can be used for remote control on/off switching of the power supply, it is normally held at about +7v and will cause the chip to enter standby mode if it falls below 2v. Pin 6 Ground. Pin 7 Chopper switch off pin. This pin clamps the chopper drive voltage to 1.6v in order to switch off the chopper. Pin 8 Chopper base current output drive pin. Pin 9 L.T. pin, approximately 9v under start-up conditions and 16v during normal running, Current consumption of the I.C. is typically 135mA. The voltage at this pin must reach 6.7v in order for the chip to start-up.
Semiconductor circuit for supplying power to electrical equipment, comprising a transformer having a primary winding connected, via a parallel connection of a collector-emitter path of a transistor with a first capacitor, to both outputs of a rectifier circuit supplied, in turn, by a line a-c voltage; said transistor having a base controlled via a second capacitor by an output of a control circuit acted upon, in turn by the rectified a-c line voltage as actual value and by a reference voltage; said transformer having a first secondary winding to which the electrical equipment to be supplied is connected; said transformer having a second secondary winding with one terminal thereof connected to the emitter of said transistor and the other terminal thereof connected to an anode of a first diode leading to said control circuit; said transformer having a third secondary winding with one terminal thereof connected, on the one hand, via a series connection of a third capacitor with a first resistance, to the other terminal of said third secondary winding and connected, on the other hand, to the emitter of said transistor, the collector of which is connected to said primary winding; a point between said third capacitor and said first resistance being connected to the cathode of a second diode; said control circuit having nine terminals including a first terminal delivering a reference voltage and connected, via a voltage divider formed of a third and fourth series-connected resistances, to the anode of said second diode; a second terminal of said control circuit serving for zero-crossing identification being connected via a fifth resistance to said cathode of said second diode; a third terminal of said control-circuit serving as actual value input being directly connected to a divider point of said voltage divider forming said connection of said first terminal of said control circuit to said anode of said second diode; a fourth terminal of said control circuit delivering a sawtooth voltage being connected via a sixth resistance to a terminal of said primary winding of said transformer facing away from said transistor; a fifth terminal of said control circuit serving as a protective input being connected, via a seventh resistance to the cathode of said first diode and, through the intermediary of said seventh resistance and an eighth resistance, to the cathode of a third diode having an anode connected to an input of said rectifier circuit; a sixth terminal of said control circuit carrying said reference potential and being connected via a fourth capacitor to said fourth terminal of said control circuit and via a fifth capacitor to the anode of said second diode; a seventh terminal of said control circuit establishing a potential for pulses controlling said transistor being connected directly and an eighth terminal of said control circuit effecting pulse control of the base of said transistor being connected through the intermediary of a ninth resistance to said first capacitor leading to the base of said transistor; and a ninth terminal of said control circuit serving as a power supply input of said control circuit being connected both to the cathode of said first diode as well as via the intermediary of a sixth capacitor to a terminal of said second secondary winding as well as to a terminal of said third secondary winding.
Description:
The invention relates to a blocking oscillator type switching power supply for supplying power to electrical equipment, wherein the primary winding of a transformer, in series with the emitter-collector path of a first bipolar transistor, is connected to a d-c voltage obtained by rectification of a line a-c voltage fed-in via two external supply terminals, and a secondary winding of the transformer is provided for supplying power to the electrical equipment, wherein, furthermore, the first bipolar transistor has a base controlled by the output of a control circuit which is acted upon in turn by the rectified a-c line voltage as actual value and by a set-point transmitter, and wherein a starting circuit for further control of the base of the first bipolar transistor is provided. Such a blocking oscillator switching power supply is described in the German periodical, "Funkschau" (1975) No. 5, pages 40 to 44. It is well known that the purpose of such a circuit is to supply electronic equipment, for example, a television set, with stabilized and controlled supply voltages. Essential for such switching power supply is a power switching transistor i.e. a bipolar transistor with high switching speed and high reverse voltage. This transistor therefore constitutes an important component of the control element of the control circuit. Furthermore, a high operating frequency and a transformer intended for a high operating frequency are provided, because generally, a thorough separation of the equipment to be supplied from the supply naturally is desired. Such switching power supplies may be constructed either for synchronized or externally controlled operation or for non-synchronized or free-running operation. A blocking converter is understood to be a switching power supply in which power is delivered to the equipment to be supplied only if the switching transistor establishing the connection between the primary coil of the transformer and the rectified a-c voltage is cut off. The power delivered by the line rectifier to the primary coil of the transformer while the switching transistor is open, is interim-stored in the transformer and then delivered to the consumer on the secondary side of the transformer with the switching transistor cut off. 
In the blocking converter described in the aforementioned reference in the literature, "Funkschau" (1975), No. 5, Pages 40 to 44, the power switching transistor is connected in the manner defined in the introduction to this application. In addition, a so-called starting circuit is provided. Because several diodes are generally provided in the overall circuit of a blocking oscillator according to the definition provided in the introduction hereto, it is necessary, in order not to damage these diodes, that due to the collector peak current in the case of a short circuit, no excessive stress of these diodes and possibly existing further sensitive circuit parts can occur. Considering the operation of a blocking oscillator, this means that, in the event of a short circuit, the number of collector current pulses per unit time must be reduced. For this purpose, a control and regulating circuit is provided. Simultaneously, a starting circuit must bring the blocking converter back to normal operation when the equipment is switched on, and after disturbances, for example, in the event of a short circuit. The starting circuit shown in the literature reference "Funkschau" on Page 42 thereof, differs to some extent already from the conventional d-c starting circuits. It is commonly known for all heretofore known blocking oscillator circuits, however, that a thyristor or an equivalent circuit replacing the thyristor is essential for the operation of the control circuit.
It is accordingly an object of the invention to provide another starting circuit. It is a further object of the invention to provide a possible circuit for the control circuit which is particularly well suited for this purpose. It is yet another object of the invention to provide such a power supply which is assured of operation over the entire range of line voltages from 90 to 270 V a-c, while the secondary voltages and secondary load variations between no-load and short circuit are largely constant.
With the foregoing and other objects in view, there is provided, in accordance with the invention, a blocking oscillator-type switching power supply for supplying power to electrical equipment wherein a primary winding of a transformer, in series with an emitter-collector path of a first bipolar transistor, is connected to a d-c voltage obtained by rectification of a line a-c voltage fed-in via two external supply terminals, a secondary winding of the transformer being connectible to the electrical equipment for supplying power thereto, the first bipolar transistor having a base controlled by the output of a control circuit acted upon, in turn, by the rectified a-c line voltage as actual value and by a set-point transmitter, and including a starting circuit for further control of the base of the first bipolar transistor, including a first diode in the starting circuit having an anode directly connected to one of the supply terminals supplied by the a-c line voltage and a cathode connected via a resistor to an input serving to supply power to the control circuit, the input being directly connected to a cathode of a second diode, the second diode having an anode connected to one terminal of another secondary winding of the transformer, the other secondary winding having another terminal connected to the emitter of the first bipolar transmitter. In accordance with another feature of the invention, there is provided a second bipolar transistor having the same conduction type as that of the first bipolar transistor and connected in the starting circuit with the base thereof connected to a cathode of a semiconductor diode, the semiconductor diode having an anode connected to the emitter of the first bipolar transistor, the second bipolar transistor having a collector connected via a resistor to a cathode of the first diode in the starting circuit, and having an emitter connected to the input serving to supply power to the control circuit and also connected to the cathode of the second diode which is connected to the other secondary winding of the transformer.
In accordance with a further feat
ure of the invention, the base of the second bipolar transistor is connected to a resistor and via the latter to one pole of a first capacitor, the anode of the first diode being connected to the other pole of the first capacitor. In accordance with an added feature of the invention, the input serving to supply power to the control circuit is connected via a second capacitor to an output of a line rectifier, the output of the line rectifier being directly connected to the emitter of the first bipolar transistor.
In accordance with an additional feature of the invention, the other secondary winding is connected at one end to the emitter of the first bipolar transistor and to a pole of a third capacitor, the third capacitor having another pole connected, on the one hand, via a resistor, to the other end of the other secondary winding and, on the other hand, to a cathode of a third diode, the third diode having an anode connected via a potentiometer to an actual value input of the control circuit and, via a fourth capacitor, to the emitter of the first bipolar transistor.
In accordance with yet another feature of the invention, the control circuit has a control output connected via a fifth capacitor to the base of the first bipolar transistor for conducting to the latter control pulses generated in the control circuit.
In accordance with a concomitant feature of the invention, there is provided a sixth capacitor shunting the emitter-collector path of the first transistor.
Other features which are considered as characteristic for the invention are set forth in the appended claim.
Although the invention is illustrated and described herein as embodied in a blocking oscillator type switching power supply, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings, in which:
FIGS. 1 and 2 are circuit diagrams of the blocking oscillator type switching power supply according to the invention; and
FIG. 3 is a circuit diagram of the control unit RS of FIGS. 1 and 2.
Referring now to the drawing and, first, particularly to FIG. 1 thereof, there is shown a rectifier circuit G in the form of a bridge current, which is acted upon by a line input represented by two supply terminals 1' and 2'. Rectifier outputs 3' and 4' are shunted by an emitter-collector path of an NPN power transistor T1 i.e. t
he
series connection of the so-called first bipolar transistor referred to
hereinbefore with a primary winding I of a transformer Tr. Together
with the inductance of the transformer Tr, the capacitance C1 determines
the frequency and limits the opening voltages of the switch embodied by
the first transistor T1. A capacitance C2, provided between the base of
the first transistor T1 and the control output 7,8 of a control circuit
RS, separates the d-c potentials of the control or regulating circuit
RS and the switching transistor T1 and serves for addressing this
switching transistor T1 with pulses. A resistor R1 provided at the
control output 7,8 of the control circuit RS is the negative-feedback
resistor of both output stages of the control circuit RS. It determines
the maximally possible output pulse current of the control circuit RS. A
secondary winding II of the transformer Tr takes over the power supply
of the control circuit, in steady state operation, via the diode D1. To
this end, the cathode of this diode D1 is directly connected to a power
supply input 9 of the control circuit RS, while the anode thereof is
connected to one terminal of the secondary winding II. The other
terminal of the secondary winding II is connected to the emitter of the
power switching transistor T1.The cathode of the diode D1 and, therewith, the power supply terminal 9 of the control circuits RS are furthermore connected to one pole of a capacitor C3, the other pole of which is connected to the output 3' of the rectifier G. The capacitance of this capacitor C3 thereby smoothes the positive half-wave pulses and serves simultaneously as an energy storage device during the starting period. Another secondary windi
ng
III of the transformer Tr is connected by one of the leads thereof
likewise to the emitter of the first transistor T1, and by the other
lead thereof via a resistor R2, to one of the poles of a further
capacitor C4, the other pole of which is connected to the
first-mentioned lead of the other secondary winding III. This second
pole of the capacitor C4 is simultaneously connected to the output 3' of
the rectifier circuit G and, thereby, via the capacitor C3, to the
cathode of the diode D1 driven by the secondary winding II of the
transformer Tr as well as to the power supply input 9 of the control
circuit RS and, via a resistor R9, to the cathode of a second diode D4.
The second pole of the capacitor C4 is simultaneously connected directly
to the terminal 6 of the control circuit RS and, via a further
capacitor C 6, to the terminal 4 of the control circuit RS as well as,
additionally, via the resistor R6, to the other output 4' of the
rectifier circuit G. The other of the poles of the capacitor C4 acted
upon by the secondary winding II is connected via a further capacitor C5
to a node, which is connected on one side thereof, via a variable
resistor R4, to the terminals 1 and 3 of the control circuit RS, with
the intermediary of a fixed resistor R5 in the case of the terminal 1.
On the other side of the node, the latter and, therefore, the capacitor
C5 are connected to the anode of a third diode D2, the cathode of which
is connected on the one hand, to the resistor R2 mentioned hereinbefore
and leads to the secondary winding III of the transformer Tr and, on the
other hand, via a resistor R3 to the terminal 2 of the control circuit
RS.The nine terminals of the control circuit RS have the following purposes or functions:
Terminal 1 supplies the internally generated reference voltage to ground i.e. the nominal or reference value required for the control or regulating process;
Terminal 2 serves as input for the oscillations provided by the secondary winding III, at the zero point of which, the pulse start of the driving pulse takes place;
Terminal 3 is the control input, at which the existing actual value is communicated to the control circuit RS, that actual value being generated by the rectified oscillations at the secondary winding III;
Terminal 4 is responsive to the occurrence of a maximum excursion i.e. when the largest current flows through the first transistor T1 ;
Terminal 5 is a protective input which responds if the rectified line voltage drops too sharply; Terminal 6 serves for the power supply of the control process and, indeed, as ground terminal;
Terminal 7 supplies the d-c component required for charging the coupling capacitor C2 leading to the base of the first transistor T1 ;
Terminal 8 supplies the control pulse required for the base of the first transistor T1 ; and
Terminal 9 serves as the first terminal of the power supply of the control circuit RS.
Further details of the control circuit RS are described hereinbelow.
The capacity C3 smoothes the positive half-wave pulses which are provided by the secondary winding II, and simultaneously serves as an energy storage device during the starting time. The secondary winding III generates the control voltage and is simultaneously used
as
feedback. The time delay stage R2 /C4 keeps harmonics and fast
interference spikes away from the control circuit RS. The resistor R3 is
provided as a voltage divider for the second terminal of the control
circuit RS. The diode D2 rectifies the control pulses delivered by the
secondary winding III. The capacity C5 smoothes the control voltage. A
reference voltage Uref, which is referred to ground i.e. the potential
of terminal 6 is present at the terminal 1 of the control circuit RS.
The resistors R4 and R5 form a voltage divider of the input-difference
control amplifier at the terminal 3. The desired secondary voltage can
be set manually via the variable resistor R4. A time-delay stage R6 /C6
forms a sawtooth rise which corresponds to the collector current rise of
the first bipolar transistor T1 via the primary winding I of the
transformer Tr. The sawtooth present at the terminal 4 of the control
circuit RS is limited there between the reference voltage 2 V and 4 V.
The voltage divider R7 /R8 (FIG. 2), brings to the terminal 5 of the
control circuit RS the enabling voltage for the drive pulse at the
output 8 of the control circuit RS.The diode D4, together with the resistor R9 in cooperation with the diode D1 and the secondary winding II, forms the starting circuit provided, in accordance with the invention. The operation thereof is as follows:
After the switching power supply is switched on, d-c voltages build up at the collector of the switching transistor T1 and at the input 4 of the control circuit RS, as a function in time of the predetermined time constants. The positive sinusoidal half-waves charge the capacitor C3 via the starting diode D4 and the starting resistor R9 in dependence upon the time constant R9.C3. Via the protective input terminal 5 and the resisto
r
R11 not previously mentioned and forming the connection between the
resistor R9 and the diode D1, on the one hand, and the terminal 5 of the
control circuit RS, on the other hand, the control circuit RS is biased
ready for switching-on, and the capacitor C2 is charged via the output
7. When a predetermined voltage value at the capacitor C3 or the power
supply input 9 of the control circuit RS, respectively, is reached, the
reference voltage i.e. the nominal value for the operation of the
control voltage RS, is abruptly formed, which supplies all stages of the
control circuit and appears at the output 1 thereof. Simultaneously,
the switching transistor T1 is switched into conduction via the output
8. The switching of the transistor T1 at the primary winding T of the
transformer Tr is transformed to the second secondary winding II, the
capacity C3 being thereby charged up again via the diode D1. If
sufficient energy is stored in the capacitor C3 and if the re-charge via
the diode D1 is sufficient so that the voltage at a supply input 9 does
not fall below the given minimum operating voltage, the switching power
supply then remains connected, so that the starting process is
completed. Otherwise, the starting process described is repeated several
times.In FIG. 2, there is shown a further embodiment of the circuit for a blocking oscillator type switching power supply, according to the invention, as shown in FIG. 1. Essential for this circuit of FIG. 2 is the presence of a second bipolar transistor T2 of the type of the first bipolar transistor T1 (i.e. in the embodiments of the invention, an npn-transistor), which forms a further component of the starting circuit and is connected with the collector-emitter path thereof between the resistor R9 of the starting circuit and the current supply input 9 of the control circuit RS. The base of this second transistor T2 is connected to a node which leads, on the one hand, via a resistor R10 to one electrode of a capacitor C7, the other electrode of which is connected to the anode of the diode D4 of the starting circuit and, accordingl
y,
to the terminal 1' of the supply input of the switching power supply G.
On the other hand, the last-mentioned node and, therefore, the base of
the second transistor T2 are connected to the cathode of a Zener diode
D3, the anode of which is connected to the output 3' of the rectifier G
and, whereby, to one pole of the capacitor C3, the second pole of which
is connected to the power supply input 9 of the control circuit RS as
well as to the cathode of the diode D1 and to the emitter of the second
transistor T2. In other respects, the circuit according to FIG. 2
corresponds to the circuit according to FIG. 1 except for the resistor
R11 which is not necessary in the embodiment of FIG. 2, and the missing
connection between the resistor R9 and the cathode of the diode D1,
respectively, and the protective input 5 of the control circuit RS.Regarding the operation of the starting circuit according to FIG. 2,
it can be stated that the positive sinusoidal half-wave of the line
voltage, delayed by the time delay stage C7, R10 drives the base of the
transistor T2 in the starting circuit. The amplitude is limited by the
diode D3 which is provided for overvoltage protection of the control
circuit RS and which is preferably incorporated as a Zener diode. The
second transistor T2 is switched into conduction. The capacity C3 is
charged, via the serially connected diode D4 and the resistor R9 and the
collector-emitter path of the transistor T2, as soon as the voltage
between the terminal 9 and the terminal 6 of the control circuit RS i.e.
the voltage U9, meets the condition U9 <[UDs -UBE (T2)].Because of the time constant R9.C3, several positive half-waves are necessary in order to increase the voltage U9 at the supply terminal 9 of the control circuit RS to such an extent that the control circuit RS is energized. During the negative sine half-wave, a partial energy chargeback takes place from the capacitor C3 via the emitter-base path of the transistor T2 of the starting circuit and via the resistor R10 and the capacitor C7, respectively, into the supply network. At approximately 2/3 of the voltage U9, which is limited by the diode D3, the control circuit RS is switched on. At the terminal 1 thereof, the reference voltage Uref then appears. In addition, the voltage divider R5 /R4 becomes effective. At the terminal 3, the control amplifier receives the voltage forming the actual value, while the first bipolar transistor T1 of the blocking-oscillator type switching power supply is addressed pulsewise via the terminal 8.
Because the capacitor C6 is charged via the resistor R6, a higher voltage than Uref is present at the terminal 4 if the control circuit RS is activated. The control voltage then discharges the capacitor C6 via the terminal 4 to half the value of the reference voltage Uref, and immediately cuts off the addressing input 8 of the control circuit RS. The first driving pulse of the switching transistor T1 is thereby limited to a minimum of time. The power for switching-on the control circuit RS and for driving the transistor T1 is supplied by the capacitor C3. The voltage U9 at the capacitor C3 then drops. If the voltage U9 drops below the switching-off voltage value of the control circuit RS, the latter is then inactivated. The next positive sine half-wave would initiate the starting process again.
By switching the transistor T1, a voltage is transformed in the secondary winding II of the transformer Tr. The positive component is rectified by the diode D1, recharing of the capacitor C3 being thereby provided. The voltage U9 at the output 9 does not, therefore, drop below the minimum value required for the operation of the control circuit RS, so that the control circuit RS remains activated. The power supply continues to operate in the rhythm of the existing conditions. In operation, the voltage U9 at the supply terminal 9 of the control circuit RS has a value which meets the condition U9 >[UDs -UBE (T2)], so that the transistor T2 of the starting circuit remains cut off.
For the internal layout of the control circuit RS, the construction shown, in particular, from FIG. 3 is advisable. This construction is realized, for example, in the commercially available type TDA 4600 (Siemens AG).
The block diagram of the control circuit according to FIG. 3
shows
the power supply thereof via the terminal 9, the output stage being
supplied directly whereas all other stages are supplied via Uref. In the
starting circuit, the individual subassemblies are supplied with power
sequentially. The d-c output voltage potential of the base current gain
i.e. the voltage for the terminal 8 of the control circuit RS, and the
charging of the capacitor C2 via the terminal 7 are formed even before
the reference voltage Uref appears. Variations of the supply voltage U9
at terminal 9 and the power fluctuations at the terminal 8/terminal 7
and at the terminal 1 of the control circuit RS are leveled or smoothed
out by the voltage control. The temperature sensitivity of the control
circuit RS and, in particular, the uneven heating of the output and
input stages and input stages on the semiconductor chip containing the
control circuit in monolithically integrated form are intercepted by the
temperature compensation provided. The output values are constant in a
specific temperature range. The message for blocking the output stage,
if the supply voltage at the terminal 9 is too low, is given also by
this subassembly to a provided control logic.The outer voltage divider of the terminal 1 via the r
esistors
R5 and R4 to the control tap U forms, via terminal 3, the variable side
of the bridge for the control amplifier formed as a differential
amplifier. The fixed bridge side is formed by the reference voltage Uref
via an internal voltage divider. Similarly formed are circuit portions
serving for the detection of an overload short circuit and circuit
portions serving for the "standby" no-load detection, which can be
operated likewise via terminal 3.Within a provided trigger circuit, the driving pulse length is determined as a function of the sawtooth rise at the terminal 4, and is transmitted to the control logic. In the control logic, the commands of the trigger circuit are processed. Through the zero-crossing identification at input 2 in the control circuit RS, the control logic is enabled to start the control input only at the zero point of the frequency oscillation. If the voltages at the terminal 5 and at the terminal 9 are too low, the control logic blocks the output amplifier at the terminal 8. The output amplifier at the terminal 7 which is responsible for the base charge in the capacitor C2, is not touched thereby.
The base current gain for the transistor T1 i.e. for the first transistor in accordance with the definition of the invention, is formed by two amplifiers which mutually operate on the capacitor C2. The roof inclination of the base driving current for the transistor T1 is impressed by the collector current simulation at the terminal 4 to the amplifier at the terminal 8. The control pulse for the transistor T1 at the terminal 8 is always built up to the potential present at the terminal 7. The amplifier working into the terminal 7 ensures that each new switching pulse at the terminal 8 finds the required base level at terminal 7.
Supplementing the comments regarding FIG. 1, it should also be mentioned that the cathode of the diode D1 connected by the anode thereof to the one end of the secondary winding II of the transformer Tr is connected via a resistor R11 to the protective input 5 of the control circuit RS whereas, in the circuit according to FIG. 2, the protective input 5 of the control circuit RS is supplied via a voltage divider R8, R7 directly from the output 3', 4' of the rectifier G delivering the rectified line a-c voltage, and which obtains the voltage required for executing its function. It is evident that the first possible manner of driving the protective input 5 can be used also in the circuit according to FIG. 2, and the second possibility also in a circuit in accordance with FIG. 1.
The control circuit RS which is shown in FIG. 3 and is realized in detail by the building block TDA 4600 and which is particularly well suited in conjunction with the blocking oscillator type switching power supply according to the invention has 9 terminals 1-9, which have the following characteristics, as has been explained in essence hereinabove:
Terminal 1 delivers a reference voltage Uref which serves as the constant-current source of a voltage divider R5.R4 which supplies the required d-c voltages for the differential amplifiers provided for the functions control, overload detection, short-circuit detection and "standby"-no load detection. The dividing point of the voltage divider R5 -R4 is connected to the terminal 3 of the control circuit RS. The terminal 3 provided as the control input of RS is controlled in the manner described hereinabove as input for the actual value of the voltage to be controlled or regulated by the secondary winding III of the transformer Tr. With this input, the lengths of the control pulses for the switching transistor T1 are determined.
Via the input provided by the terminal 2 of the control circuit RS, the zero-point identification in the control circuit is addressed for detecting the zero-point o
f
the oscillations respectively applied to the terminal 2. If this
oscillation changes over to the positive part, then the addressing pulse
controlling the switching transistor T1 via the terminal 8 is released
in the control logic provided in the control circuit.A sawtooth-shaped voltage, the rise of which corresponds to the collector current of the switching transistor T1, is present at the terminal 4 and is minimally and maximally limited by two reference voltages. The sawtooth voltage serves, on the one hand as a comparator for the pulse length while, on the other hand, the slope or rise thereof is used to obtain in the base current amplification for the switching transistor T1, via the terminal 8, a base drive of this switching transistor T1 which is proportional to the collector current.
The terminal 7 of the control circuit RS as explained hereinbefore, determines the voltage potential for the addressing pulses of the transistor T2. The base of the switching transistor T1 is pulse-controlled via the terminal 8, as described hereinbefore. Terminal 9 is connected as the power supply input of the control circuit RS. If a voltage level falls below a given value, the terminal 8 is blocked. If a given positive value of the voltage level is exceeded, the control circuit is activated. The terminal 5 releases the terminal 8 only if a given voltage potential is present.
Forei
gn References:DE2417628A1 1975-10-23 363/37
DE2638225A1 1978-03-02 363/49
Other References:
Grundig Tech. Info. (Germany), vol. 28, No. 4, (1981).
IBM Technical Disclosure Bulletin, vol. 19, No. 3, pp. 978, 979, Aug. 1976.
German Periodical, "Funkschau", (1975), No. 5, pp. 40 to 44.
Inventors:
Peruth, Gunther (Munich, DE) Siemens Aktiengesellschaft (Berlin and Munich, DE)TDA2594 HORIZONTAL COMBINATIONThe TDA2594 is a monolithic integrated circuit intended for use in colour television receivers.
The circuit incorporates the following functions:
0 Horizontal oscillator based on the threshold switching principle.
0 Phase com
parison between sync pulse and oscillator voltage (tp1).0 Internal key pulse for phase detector (-D) fYP~ ‘I V
V3-1elp-pl WP- 1° V
* Permissible range: 1 t
TDA3501 VIDEO CONTROL COMBINATIONThe TDA3501 is a monolithic integrated circuit performing the control functions in a PAL/SECAM
decoder which additionally comprises the integrated circuits TDA3510 (PAL decoder) and/or
TDA3520 (SECAM decoder).
The required input signals are: luminance and colour difference -(R-Y) and -(B-Y). while linear RGB
signals can be inserted from an external source.
RGB signals are provided at the output to drive the video output stages.
The TDA3501 has the following features:
I capacitive coupling of the input signals
0 linear saturation control
0 (G-Y) and RGB matrix
0 insertion possibility of linear RGB signals, e.g. video text, video games, picture-in-picture, camera or
slidescanner
0 equal black level for inserted and matrixed signals by clamping
0 3 identical channels for the RGB signals
0 linear contrast and brightness control, operating on both the inserted and matrixed RGB signals
I horizontal and vertical blanking (black and ultra-black respectively) and black-level clamping
obtained via a 3-level sandcastle pulse
O differential amplifiers with feedback-inputs for stabilization of the RGB output stages
0 2 d.c. gain controls for the green and blue output signals (white point adjustment)
O beam current limiting possibility
QUICK REFERENCE DATA
Supply voltage V524 typ. 12 V
Supply curre
nt I5 typ. 100 mALuminance input signal (peak-to-peak value) V15_24(p_p) typ. 0,45 V
Luminance input resistance R15_24 typ. 12 kS`LColour difference input signals (peak-to-peak values)
-(B-Y) V1g_24(p_p) typ. 1,33 V
-(R-Y) V17_24(p_p) typ. 1,05 V
Inserted RGB signals (peak-to-peak values) V12,13,-|4_24(p_p) typ. 1 V
Threelevel sandcastle pulse detector V10_24 typ. 2,5/4,5/8,0 V
Control voltage ranges
brightness V20_24 1 to 3 V
contrast V19_24 2 to 4 V
saturation V15_24 2,1 to 4 V
SAB3034 COMPUTER INTERFACE FOR TUNING AND CONTROL (CITAC)
GENERAL DESCRIPTION
The SAB3034 provides closed-loop digital tuning of TV receivers, with or without a.f.c., as required. lt
also controls up to 8 analogue functions, 4 general purpose I/O ports and 4 high-current outputs for
tuner band selection.
The IC is used in conjunction with a microcomputer from the MAB84OO family and is controlled via a two-wire, bidirectional I2 C bus.
Featu res
Combined analogue and digital circuitry minimizes the number of additional interfacing components
required
Frequency measurement with resolution of 50 KHz
Selectable prescaler divisor of 64 or 256
32 V tuning voltage amplifier
4 high-current outputs for direct band selection
8 static digital to analogue converters (DACSI for control of analogue functions
Four general purpose input/output (l/O) ports
Tuning with control of speed and direction
Tuning with or without a.f.c.
Single-pin, 4 MHZ on-chip oscillator
I2 C bus slave transceiver
FUNCTIONAL DESCRIPTION
The SAB3034 is a monolithic computer interface which provides tuning and control functions and
operates in conjunction with a microcomputer via an I2 C bus.
Tuning
This is performed using frequency-locked loop digital control. Data cor
responding to the required tunerfrequency is stored in a 15-bit frequency buffer. The actual tuner frequency, divided by a factor of 256
(or by 64) by a prescaler, is applied via a gate to a 15-bit frequency counter. This input (FDIV) is
measured over a period controlled by a time reference counter and is compared with the contents of the frequency buffer. The result of the comparison is used to control the tuning voltage so that the tuner frequency equals the contents of the frequency buffer multiplied by 50 kHz within a programmable tuning window (TUW).
The system cycles over a period of 6,4 ms (or 2,56 ms), controlled by the time reference counter which is clocked by an on-chip 4 lVlHz reference oscillator. Regulation of the tuning voltage is performed by a charge pump frequency-locked loop system. The charge IT flowing into the tuning voltage amplifier is controlled by the tuning counter, 3-bit DAC and the charge pump circuit. The charge IT is linear with the frequency deviation Af in steps of 50
METZ 7285 MALLORCA COLOR CHASSIS 681G Frequency synthesizer tuning system for television receivers:
" A method for tuning a television receiver having automatic frequency control to the carrier frequency of a selected broadcast channel with an associated channel number including generating a variable frequency signal by means of a local oscillator, generating a reference frequency signal by means of a reference oscillator, and generating a local oscillator correction signal for matching an intermediate frequency signal derived from said local oscillator signal and the carrier frequency signal with a predetermined nominal intermediate frequency signal, said method being characterized by the use of a microcomputer and comprising:
generating binary signals representing first and second digital tune words, said digital tune words representing a selected channel;
storing said first and second digital tune words in a first data memory in said microcomputer;
reading said first and second digital tune words from said first memory and generating a divided-down local oscillator frequency by the use of said first digital tune word and a divided-down reference oscillator frequency by the use of said second digital tune word;
comparing said divided-down local oscillator and reference frequencies and generating a control signal representative of the difference in frequency of said divided-down local oscillator and reference frequencies;
coupling said control signal to said local oscillator for causing it to be locked to the frequency of said received carrier signal;
mixing the local oscillator frequency signal and the carrier frequency signal to generate an intermediate frequency signal;
comparing said intermediate frequency signal with said predetermined nominal intermediate frequency signal and providing a tuning voltage to said microcomputer, said tuning voltage being indicative of the magnitude and direction of a tuning error between said intermediate frequency signal and said predetermined nominal intermediate frequency signal;
incrementally adjusting the reference oscillator frequency by means of a tuning signal provided to said reference oscillator by said microcomputer in response to said tuning voltage;
detecting when the incrementally changing, divided-down reference oscillator frequency causes the intermediate frequency signal to pass said predetermined nominal intermediate frequency signal; and
incrementally stepping the divided-down reference oscillator frequency back a predetermined number of steps following the passage of said predetermined nominal intermediate frequency signal by said intermediate frequency signal in tuning said television receiver to the selected channel.
"
1. A tuning system for the tuner of a television receiver capable of receiving a composite television signal and including frequency discriminator (AFT) circuit means, said system including in combination:
a reference oscillator providing a reference signal at a predetermined frequency;
a local oscillator in the tuner providing a variable output frequency in response to the application of a control signal thereto;
a programmable frequency divider means having first and second inputs coupled respectively to the output of said reference oscillator and said local oscillator for producing signals on first and second outputs having frequencies which are a programmable fraction of the frequency of the signals applied to the inputs thereto;
phase comparator means having one input coupled with the first output of said programmable frequency divider means and having another input coupled with the second output of said programmable frequency divider means for developing a control signal and applying such control signal to said local oscillator for controlling the output frequency thereof;
counter circuit means coupled with said programmable frequency divider means for initially setting said divider means to a predetermined division ratio and operating to change the programmable fraction of division thereof in accordance with changes in the count in said counter circuit means;
control circuit means coupled with the output of said frequency discriminator means and further coupled with said counter circuit means for causing said counter circuit means to count at a first rate in a predetermined direction determined by the state of the output signal from said discriminator means in the absence of a predetermined signal output from said frequency discriminator means until a predetermined maximum count is attained, thereupon resetting said counter circuit means to a count which is a predetermined amount less than said maximum predetermined count and continuing to count at said first rate in the same predetermined direction from said new count to continuously change the programmable fraction of said frequency divider means in accordance with the state of operation of said counter circuit means, said control means operating in response to said predetermined signal output from the frequency discriminator means for terminating operation of said counter circuit means; and
further means for terminating operation of said counter circuit means at said first rate and causing operation thereof at a second slower rate.
2. The combination according to claim 1 wherein said further means includes timing means initiated into operation simultaneously with the setting of said divider means to a predetermined division ratio, and after a predetermined time interval said timing means producing an output signal applied to said counter circuit means to cause operation thereof to take place at said second slower rate. 3. The combination according to claim 1 wherein said counter circuit means includes a reversible digital counter coupled with said programmable frequency divider, means and said control circuit means causes said counter circuit means to count in said predetermined direction when the output of said frequency discriminator is of a first state and to count in the opposite direction when the output of said frequency discriminator is of second state; and said further means comprises means coupled with the output of said frequency discriminator and with said counter circuit means to take place at said second slower rate in response to a predetermined number of changes of state of frequency discriminator. 4. The combination according to claim 3 further including means responsive to the selection of a new channel in said television receiver for resetting said further means to an initial condition of operation. 5. The combination according to claim 4 wherein said further means comprises a search termination counter means operative to provide an output signal applied to said counter circuit means in response to a count thereby of a predetermined number of changes of state of said frequency discriminator to cause said counter circuit means to be operated at said second slower rate.
Description:
BACKGROUND OF THE INVENTION
Both of the above mentioned patents are directed to frequency synthesizer tuning systems for use with television receivers to enable operation of the receivers with minimal viewer fine tuning adjustments. By the utilization of the frequency synthesizer tuning systems of these patents, the fine tuning adjustment which is necessary with conventional types of television receiver tuning systems has been substantially eliminated. The system employed in the '953 patent permits utilization of a frequency synthesizer tuning system which correctly tunes to a desired television station or channel even if the transmitted signals from that station are not precisely maintained at the proper frequencies. The '535 patent is directed to a signal seek tuning system adaptation of the frequency synthesizer tuning system of the '953 patent which still permits implementation of all of the desired wide-band pull in range of the frequency synthesizer system of the '953 patent.
The systems of the foregoing patents operate effectively to correct automatically for frequency offsets in a frequency synthesizer tuning system without affecting the operation of the conventional frequency synthesizer used in the system. The systems of these patents are in widespread use commercially and permit direct selection, with automatic fine tuning adjustment, of any desired VHF channel which the viewer wishes to observe. In addition, the signal seek adaptation disclosed in the '535 patent couples all of the advantages of the frequency synthesizer tuning system of the '953 patent with the desirability of providing bidirectional signal seek operation.
While the systems disclosed in the foregoing patents operate in a highly satisfactory manner to accomplish the desired results of accurate tuning without the necessity of fine tuning adjustments, the circuitry for accomplishing the desired results is somewhat complex. It is desirable to reduce the circuit complexity and the number of signal detectors for accomplishing these results without compromising the accuracy of operation of the system.
SUMMARY OF THE INVENTION
Accordingly, it is an object of this invention to provide an improved tuning system for a television receiver.
It is an additional object of this invention to provide an improved frequency synthesizer tuning system for a television receiver.
It is another object of this invention to provide an improved frequency synthesizer tuning system for a television receiver which includes a provision for adjusting the synthesizer loop for frequency offsets in the received signal with a minimum number of signal detectors.
It is a further object of this invention to tune the local RF oscillator of a television receiver to the correct frequency for a selected channel with a frequency synthesizer tuning system, and automatically to change the reference frequency of the synthesizer system, or adjust the count of a programmable divider that produces a signal that divides the frequency of the local oscillator of the tuner, if the AFT signal produced by the AFT frequency discriminator of the receiver is outside a predetermined range corresponding to correct tuning.
It is still another object of this invention to provide an improved frequency synthesizer tuning system for a television receiver which operates to adjust the synthesizer loop for frequency offsets in the received signal over a relatively wide pull in range in response to the output of the receiver frequency discriminator by changing the division ratio of a programmable frequency divider in the reference oscillator leg or local oscillator leg of the synthesizer loop at a first relatively high rate from an initial nominal value to a pre-established maximum in one direction, and then resetting the division ratio to a second nominal value once the maximum is reached and continuing to incrementally change the division ratio in the same direction from the second nominal value until a properly tuned condition is indicated by the output of the receiver AFT frequency discriminator, followed by control at a lower rate of operation to maintain tuning during transmitting station drifts.
In accordance with a preferred embodiment of this invention, the frequency synthesizer tuning system for a television receiver includes a stable reference oscillator and a voltage controlled local oscillator in the tuner. A programmable frequency divider is connected between the output of the reference oscillator and one input to a phase comparator, the other input of which is supplied by the output of the local oscillator. The output of the phase comparator then comprises a control signal which is supplied to the local oscillator to control the frequency of its operation.
A counter circuit is connected to the programmable frequency divider for initially setting the divider to a predetermined division ratio upon selection of a desired channel by the viewer. The counter then operates to change the programmable fraction of the division ratio at a first relatively high rate in a direction controlled by the output from the receiver picture carrier discriminator in the absence of a predetermined signal output derived from the discriminator. A control means causes the counter circuit to count in this direction until it is determined that a station is tuned or a predetermined maximum count is attained if no station is correctly tuned, thereupon resetting the counter circuit to a count which is a predetermined amount less than the maximum predetermined count. Counting is continued in the same predetermined direction from the new lesser count to continuously change the programmable fraction of the frequency divider in accordance with the state of operation of the counter.
The high rate operation of the counter is terminated by the control means in response to a predetermined signal from the output of the discriminator, indicating that a station is correctly tuned, or after a fixed time-out interval; so that the system automatically adjusts for frequency offsets of the received signal which otherwise would cause the station to be mistuned if a conventional frequency synthesizer tuning system were used. After termination of the high rate operation of the counter, it is switched to a lower rate operation for maintaining tuning during transmitting station drifts.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a block diagram of a television receiver employing a preferred embodiment of the invention;
FIG. 2 is a detailed block diagram of a portion of the circuit of the preferred embodiment shown in FIG. 1;
FIG. 3 is a detailed circuit diagram of a portion of a circuit shown in FIG. 1;
FIG. 4 is a flow chart of the control sequence of operation of the circuit shown in FIG. 1 and 2; and
FIG. 5 shows a waveform and time/frequency chart, respectively, useful in explaining the operation of the circuit shown in FIGS. 1, 2 and 3.
DETAILED DESCRIPTION
Referring now to the drawings, the same reference numbers are used throughout the several figures to designate the same or similar components.
FIG. 1 is a block diagram of a television receiver, which may be a black and white or color television receiver. Mo
st of the circuitry of this receiver is conventional, and for that reason it has not been shown in FIG. 1. Added to the conventional television receiver circuitry of FIG. 1, however, is a frequency synthesizer tuning system, in accordance with a preferred embodiment of the invention, which is capable of automatically changing the reference frequency when a frequency offset exists in the received signal for a particular channel.
Transmitted composite television signals, either received over the air or distributed by means of a master antenna TV distribution system, are received by an antenna 10 or on antenna input terminals to the receiver. As is well known, these composite signals include picture and sound carrier components and synchronizing signal components, with the composite signal applied to an RF and tuner stage 11 of the receiver. The stage 11 includes the conventional RF amplifiers and tuner sections of the receiver, including a VHF oscillator section and a UHF oscillator section. Preferably, the UHF and VHF oscillators are voltage controlled oscillators, the freuency of operation of which are varied in response to a tuning voltage applied to them to effect the desired tuning of the receiver.
The output of the RF and tuner stages 11 is applied to the remainder of the television receiver 14, which includes the IF amplifier stages for supplying conventional picture (video) and sound IF signals to the video and sound processing stages of the receiver 14. The circuitry of the receiver 14 may be of any conventional type used to separate, amplify and otherwise process the signals for application to a cathode ray tube 16 and to a loudspeaker 17 which reproduce the picture and sound components, respectively, of the received signal.
The receiver 14 also includes a conventional AFT or automatic fine tuning discriminator circuit and additionally may include a synch separator circuit for producing an output in response to the presence of vertical synchronizatin pulses, a picture carrier detection circuit, and an automatic gain control (AGC) amplifier. Outputs representative of these sensor components are shown as being coupled over a group of lead 20 to sensory circuitry 22, which in turn couples outputs representative of the operation of these various sensor circuits to a microprocessor unit 23 for controlling the operation of the microprocessor unit.
The microprocessor unit 23 is utilized in the system of FIG. 1 for controlling the operation of a frequency synthesizer tuning system capable of automatic offset correction. When the viewer desires to select a new channel, he enters the desired channel number into a channel selection keyboard 25. There are a number of different keyboards which may be employed to accomplish this function, and the particular design is not important to this invention. The channel selector keyboard 25 also may include switches or keys for initiating a signal seek function in either the "up" or "down" direction.
Information represented by the selection of channel numbers on the keyboard 25 is supplied to the microprocessor unit 23 which provides output signals over a corresponding set of leads 27 to the tuners (local oscillators) 11 to effect the appropriate band switching control for the tuners 11 in accordance with the particular channel which has been selected. In addition, the keyboard 25, operating through the microprocessor unit 23, provides output signals which operate a channel number display 29 to provide an appropriate display of the selected channel number to the viewer.
The microprocessor M3870 unit 23 also processes the signals which are used to operate the channel number display 29 through a multiplexing circuit operation to decode the selected channel number into a parallel encoded signal. This signal is applied to corresponding inputs of the count-down counter or programmable frequency divider 31 to cause the division number of the divider 31 to relate to the divided down frequency of the tuner local oscillators connected to the input of the divider 31 through a prescaler divider circuit 32 to the frequency of the reference oscillator 34. Thus, the division number or division ratio of the local oscillator frequency obtained from the output of the programmable divider 31 is appropriately related to the frequency of the reference crystal oscillator 34.
The output of the oscillator 34 also is applied through a countdown circuit or programmable frequency divider 35. Conventional frequency synthesizer techniques are employed; and the microprocessor unit 23 automatically compensates, through appropriate code converter circuitry, for the non-uniform channel spacing of the television signals. It has been found most convenient to cause the programmable frequency divider 31 to divide by numbers corresponding directly to the oscillator frequency of the selected channel, for example, 101, 107, 113 . . . up to 931.
In accordance with the time division multiplex operation of the microprocessor 23, the count of the programmable frequency divider 35 initially is adjusted to a fixed count by the application of appropriate output signals from the microprocessor unit 23 to a point selected to be at or near the mid-point of the operating range of the programmable frequency divider 35. Thus, the output of the divider 35 is a stable reference frequency (because the input is from the reference crystal oscillator 34) which is used to establish initially and to maintain tuning of the receiver to the selected channel.
The output of the programmable divider 35 is applied to one of two inputs of a phase comparator circuit 37. The other input to the phase comparator circuit 37 is supplied from the selected one of the VHF or UHF oscillators in the tuner stages 11 through the programmable frequency divider 31. The phase comparator circuit 37 operates in a conventional manner to supply a DC tuning control signal through a phase locked loop filter circuit 39 and over a lead 40 to the oscillators in the tuner system 11 to change and maintain their operating frequency.
With the exception of the use of the microprocessor unit 23, the operation of the system which has been described thus far is that of a relatively conventional frequency synthesizer system incorporated into a television receiver. This system is similar to the system of the '953 patent. As in the system of that patent, the system shown in FIG. 1, when the transmitted station or station received on a master antenna distribution system provides the station or channel signals at the proper frequency, operates as a relatively conventional frequency synthesizer system. If, however, there is a frequency offset in the received signal to cause the carrier of the received signal to be displaced from the frequency which it should have to some other frequency, it is possible that the system would give the appearance of mistuning to the received station. The microprocessor 23, operating in conjunction with the sensory circuitry 22, is employed in conjunction with the countdown or programmable frequency divider circuit 35 to eliminate this disadvantage and still retain the advantages of frequency synthesizer tuning.
Reference now should be made to FIG. 2 which shows details of t
he interface between the keyboard 25, the microprocessor unit 23, and the circuitry used in the frequency synthesizer portions of the system. A commercially available microprocessor which has been used for the microprocessor 23, and which forms the basis for the diagramatic representation of the microprocessor in FIG. 2, is the Matsushita Electronics Corporation MN1402 four-bit single-chip microcomputer. This microcomputer has two, four-bit parallel input ports labeled "A" and "B". In addition, three output ports, a five-bit output port "C" and two four-bit output ports "D" and "E" are provided. The internal configuration of the microcomputer 23 includes an arithmetic logic unit (ALU), a read only memory (ROM) for storing instructions and constants, and a random access memory (RAM) used for data memory, arranged into four files, each file containing 16 four-bit words. These words are selected by X and Y registers and this memory is used, for example, for timers, counters, etc., and also is used to hold intermediate results. To facilitate an understanding of the operation of the system, a portion of this memory is shown in FIG. 2 as a clock 81 and a reversible counter 82 connected between the "B" input port and the "D" output port. The microcomputer 23 is programmed to permit it to operate in conjunction with the remainder of the circuits shown in FIG. 2. The programming techniques are standard, and the microcomputer 23 itself is a standard commercially available circuit component.
There are several system parameters that must be selected in the operation of the system shown in FIG. 2. The selection of the nominal frequency of the two signals that feed the phase comparator circuit 37 is an example. Channel selection is provided by changing the frequency division ratio of the selector counter 31 which divides the local oscillator signal after this signal is passed through a prescaler circuit 32 and a divide-by-two divider circuit 41. The nominal frequency from the programmable frequency divider 31 (selector counter) is selected so that the local oscillator (tuner) 11 can be set exactly on frequency for all channels.
Since the frequency divider 31 is able to divide only by integer numbers, one distinct frequency possibility in the range of one KHz is obtained, another in the range of two KHz, etc. A choice must be made as to which of these values is optimum. Each value yields the nominal frequency of all of the 82 channels by simply multiplying by an appropriate integer for each channel. To simplify the phase locked loop filtering problem by the filter 39, it is desirable that the frequencies of the signals supplied to the phase comparator 37 are as high as possible. This permits rapid acquisition of a new channel along with a very clean DC control signal to adjust the local oscillator. A trade-off for this, however, must be made to permit fine tunning adjustment of the local oscillator automatically to correctly tune in stations which are off their assigned frequency, or to manually provide this feature, if desired. The two-speed operation of the system in accordance with the present invention allows a better trade-off to be made by allowing rapid acquisition and then a slower speed for precise tuning.
A compromise solution which is utilized in the circuit of FIG. 2 is to cause the frequency division chain from the local oscillator 11 in the tuner to the phase comparator 37 to be composed of the fixed divide-by-256 prescaler 32, and a fixed divide-by-4 division, which is accomplished by the divider 41 at the input of the counter 31 and a second divider 42 at the output of the counter 31. The variable frequency divider counter 31 then is loaded by means of three latch circuits 44, 45 and 46 at an appropriate time by the time division multiplex operation of the microcomputer 23 and a number that programs the programmable frequency divider counter 31 to divide by the numerical value of the frequency of the local oscillator in MHz for the channel selected. For example, if the receiver is to be tuned to channel 2, which has a nominal local oscillator frequency of 101 MHz, the programmable frequency divider 31 is set to divide by 101. If the receiver is to be tuned to channel 83, which has a nominal local oscillator frequency of 931 MHz, the programmable frequency divider 31 is set to divide by 931. In both cases, the variable divider 31 produces a 1 MHz signal. However, because of the fixed divide-by-256 and the two fixed divide-by-two dividers in series with the programmable divider 31, an output frequency of 976.5625 Hz is supplied from the output of the divider 42 to the upper input of the phase comparator 37.
The division ratio of the selector counter 31 is established by appropriate output signals from the latch circuits 44, 45 and 46, as mentioned above. The initial operation for changing, or maintaining, the division ratio of the divider 31 is established by an entry of the two digits of the selected channel number in the keyboard 25. The microcomputer 23 operates as a time division multiplex system for continuously monitoring the input ports and the output ports to control the operation of the remainder of the system. The selection of the two digits of the desired channel number is affected by a time division multiplex iscanning of the outputs of the D output port of microcomputer 23 and providing that information at the A input port. From here the information is translated again to the D output ports to the appropriate drivers of the channel number display circuit 29 and to the latches 44, 45 and 46, and to a pair of similar four bit latches 49 and 50 which control the divider ratio of the counter 35.
Although the D output ports of the microcomputer 23 are connected in common to all of these various portions of the circuit, the selection of which of the latches are enabled to respond to the particular output signals appearing on the D output ports at any given time is effected through the C and E output ports of the microcomputer 23 in a time division multiplex fashion. A decoder circuit 52, connected to the lowermost three outputs of the E output port of the microcomputer 23, is used to apply unique decoding signals at different times in the time division multiplex sequence of operation of the microcomputer 23 to the five latch circuits 44, 45, 46, 49 and 50, respectively. At any given time in the sequence, only one of these latch circuits is enabled for operation. A latch load signal is applied from the upper output (EO3) at each cycle of operation of the signals appearing on the E output port to set the latch circuit which is enabled by the output of the decoding circuit 52 with the data appearing on the other inputs to the latch circuit. This data simultaneously appears on the four outputs of the D output port of the microcomputer 23.
Thus, in rapid sequence, the latch circuits 44, 45 and 46 are set to store the division number corresponding to the selected channel entered onto the keyboard 25, and the latch circuits 49 and 50 are each operated to set the programmable divider reference counter 35 to a center or nominal count, which is always the same upon the selection of a new channel on the keyboard 25. Similarly, the two right-hand outputs of the C output port (CO6 and CO5) enter the two digits of the selected channel number in the drivers of the display circuit 29 at the proper time in the binary encoded sequence when these digits appear on the four-bit binary encoded representation of the D output port. This results in a visual display of the channel number selected.
In addition to the selection of a channel number directly by the keyboard 25, the keyboard also may include an additional switch 56, which is scanned in the time division multiplex sequence to determine if the receiver is placed in a "seek" mode of operation (when the signal seek capability is incorporated into such a receiver). Operating in conjunction with the signal seek switch 56 are a pair of "up" and "down" seek direction input switches shown with a graphic representation of the seek directions on the keyboard 25. A further provision is provided by two keys labeled "U" and "D", which are used for "manual" fine tuning of the receiver in the "up" or "down" directions depending upon which of the two keys U or D has been operated. The keyboard 25 includes one additional switch 58 which may be used to disable the automatic fine tuning (AFT) portion of the circuit by rendering the microcomputer insensitive to the signal output from the AFT circuit, in a manner described more fully subsequently.
As is apparent from the foregoing, the microcomputer 23 provides the intelligence, decision making, and control for the system operation. It is a complete self contained computer. The decisions or signal inputs upon which the microcomputer 23 bases its operation include, in addition to the inputs from the keyboard 25, inputs on sensory inputs into the B input port and into the SNS1 and SNS0 inputs as shown in FIG. 2. These input signals are used to provide an indication to the microcomputer 23 of the presence or absence of a received signal; and if the presence of such a signal is indicated, the inputs provide a further indication of the accuracy of the tuning of the receiver to that signal. If the system is being operated solely in a manual mode of operation (AFT switch 58 open), the microcomputer 23 disregards all of this sensory information and tunes to the frequency allocation of the channel selected in the manner described above. The system will stay tuned to this condition, operating as a conventional frequency synthesizer, whether or not a station is present in the received signal.
When the system is placed in its automatic mode of operation (similar to the mode of operation of the above mentioned '953 patent), the counter 82, integrally formed as part of the microcomputer 23, continuously adds or subtracts one number at a time from the nominal value or programmable division fraction entered into the programmable frequency divider 35 at the outset of each new channel number selection when frequency offset (mistuning) is present. The counter 82 is driven at a relatively high counting rate by clock pulses from the clock 81 during this initial or forced search mode of operation. Thus, automatic offset correction is provided for any channel which is off its assigned frequency. The offset correction automatically adjusts the frequency of the local oscillator by changing the division ratio of the signal from the reference oscillator 35 applied to the lower input of the phase comparator 37. By doing this, the output of the phase comparator 37 applied to the local oscillator 11 varies to cause the oscillator to be tuned in the proper direction to compensate for the transmitting station mistuning.
When the system is operating in its automatic mode of operation, the microcomputer 23 responds to the sensor information applied to it on its B input ports and on the S1 input port shown in FIG. 2. These inputs are obtained from the various outputs of the operational amplifiers shown connected to the corresponding input ports in the detailed circuit of FIG. 3. Depending upon whether the receiver is provided with a signal seek feature or not, one or more of the sensory inputs of the circuit of FIG. 3 are used. The s
ystem shown in the drawings has a capability of correcting for frequency offsets larger than 1.5 MHz on channels 2 and 7 and approximately 2 MHz on channels 6 and 13. The remainder of the channels have a range between these two values.
If the receiver is not tuned properly, the micromputer 23 executes the localized search of the tuning range mentioned above. Since there is a necessary settling down time for the tuning of a television receiver immediately following selection of a new channel, a time interval of 250 milliseconds has been selected to prevent any localized search or offset frequency correction until the expiration of this "settling down" time period. If, at the end of this 250 millisecond time interval, a properly tuned station is present, this is indicated by the sensory outputs from the television receiver and no localized search is effected to change the division ratio or programmable divider count in the reference counter 35 for a system that also has signal seek.
A system with no signal seek capability is described later that requires less sensory input but which uses a time period where a forced search is required directly after the settling time interval.
Upon termination of the 250 millisecond settling down period, the microcomputer 23 is rendered responsive to the sensory input signals on its sensory input signal ports. In the simplest form, only the output of the frequency discriminator 60 (FIG. 3) applied to three comparators 61, 62 and 63 is used to provide the necessary tuning information to the microcomputer 23. The outputs of these comparators are applied to the B12 and B11 inputs of the microcomputer.
The comparator 61 simply is a conventional comparator for determining whether or not the output of the frequency discriminator is positive or negative, as indicated in the upper waveform of FIG. 5. The comparators 62 and 63 are each adjusted with appropriate reference input levels to provide a narrow window centered about the center tuning frequency (fc) of the receiver. If the tuning of the receiver, as indicated by the output of the frequency discriminator 60, is outside this window on either side of the central axis shown in FIG. 5, one output condition is indicated on the input terminal B11 of the microcomputer. Only when the tuning frequency is within the tuning window, indicative of a properly tuned receiver, is the appropriate input applied to the microcomputer input terminal B11. This input overrides any other input that may be present on the input terminal B12 and is indicative of a properly tuned receiver. The input from the frequency discriminator 60, as applied to the microcomputer on its input port B12, is used to determine the direction of operation of the counter 82 of the microcomputer for the localized search count signals applied to the latch circuits 49 and 50 to change the count of the reference programmable divider counter 35 on a step-by-step basis.
The lower graph of FIG. 5 plots the relative frequency of the local oscillator 11 to the received signal frequency with respect to time. The various arrows are used to indicate the manner of operation of the counter 82 in the microcomputer 23 in conjunction with the reference counter 35 for adjusting for any mistuning conditions which may exist after the initial station selection has been effected in the manner described above.
If the receiver is properly tuned, the outputs from the comparators 62 and 63 of FIG. 3 which are combined together and applied to the input port B11 of the microcomputer 23, provide an indication that the tuning is within the properly tuned center frequency window. As a consequence, no further operation of the microcomputer to change any of the outputs applied to the latch circuits 49 and 50 for the duration of this condition is effected. On the other hand, if the receiver is mistuned on either side of the proper tuning frequency, the various operating characteristics shown in FIG. 5 are effected.
Assume initially that the receiver is capable of making tuning adjustments over a range of fc plus Δf to fc minus Δf, as indicated in the top waveform of FIG. 5. Three specific examples of mistuning will then be considered. Initially, assume that the local oscillator is mistuned relative to the received signal to a frequency f1 as shown in the lower graph of FIG. 5. In this condition, the outout of the frequency discriminator 60 is positive since this signal frequency lies to the lefthand side of the center or properly tuned region of operation of the discriminator. Under this condition of theoperation, the input signal applied to the sensor port B12 of the microcomputer 23 is such that the microcomputer counter 82 is caused to advance in a positive direction to change the programmable division ratio or count of the reference counter 35 in a manner to force the output of the phase comparator 37 to adjust the frequency of the local oscillator until the proper tuning indicated at point B in the lower graph of FIG. 5 is reached. The time interval for accomplishing this result is measured from the upper end of the arrow representative of the frequency f1 to the point B.
Now assume that the receiver mistuning is to a frequency f2 which as shown in FIG. 5 as located on the righthand-side of the center axis fc. In this condition, the discriminator output is negative. This is reflected in the output of the comparator 61 applied to the input port B12 of the microcomputer 23. The polarity of this signal is identified by the microcomputer 23 to cause the counter 82 in it to operate in the reverse direction. As this count is applied on a step-by-step basis through the latch circuits 49 and 50 to the reference counter 35, the division ratio or count of the reference counter (divider) 35 is changed. As a result, the reference oscillator signal applied to the phase comparator 37 causes the phase comparator 37 output to drive the local oscillator frequency in a direction opposite to that considered in the first example. This is shown by the vector interconnecting the top of the arrow representative of f2 to point A on the time/frequency graph of FIG. 5.
As discussed in the general discussion above, whenever the tuning frequency reaches the narrow window on either side of fc, the outputs of the comparators 62 and 63 provide the necessary indication on the sensory input port terminal B11 to cause termination of the operation of the counter 82 in the microcomputer 23. Then the reference counter 35 remains set to the count attained just prior to the appearance of this input signal on the input port B11 of the microcomputer 23.
A third mistuning condition can exist, and ordinarily this condition results in an ambiguity which cannot be corrected simply by responding to the signal polarity at the output of the frequency discriminator. This is indicated by the mistuned condition where the difference between the local oscillator frequency f3 and the transmitter frequency is such that the signal f3 lies in the range to the right of the negative portion of the discriminator output shown in the upper waveform of FIG. 5. In this condition, the associated sound causes the discriminator output to be positive; so that the television receiver normally would attempt to tune toward the next adjacent channel and away from the properly tuned center frequency of the channel which is desired. The output of the discriminator 60 in this situation is the same as it was in th
e first example considered for frequency f1; so that the counter 82 of the microprocessor 23 operates to change the count in the reference counter 35 in a manner to cause the local oscillator frequency to go higher toward a frequency f3 +Δf, as shown in FIG. 5.
A predetermined number of counts of the counter 82 in the microcomputer 23 are necessary for the microcomputer to count through the frequency range Δf, and this range is selected to be within the pull in or operating range of the system. Once this count has been attained, the microcomputer counter 82 immediately is reset back to a count which corresponds to a frequency 2 Δf lower than the frequency attained by the maximum count. This is indicated in FIG. 5 by the frequency f3-Δf. Because the microcomputer counter 82 is limited to counting a number of counts equal to Δf, this new frequency now is on the lefthand side of the center line fc, shown in both waveforms of FIG. 5. This places the local oscillator frequency at a point such that the frequency discriminator output is the positive output shown on the lefthand-side of the upper waveform of FIG. 5. Counting continues in the same direction as previously. This time, however, it is in a proper direction to bring about correct tuning; and when the center frequency is reached, the output of the comparators 62 and 63 cause the microcomputer 23 to stop its count. The proper tuning point attained is indicated at point C on the graph of the lower part of FIG. 5.
Because the counter 82 of the microcomputer is limited to a maximum count equivalent to Δf above its initial count and thereupon is reset to a new count equivalent to 2 Δf lower than the maximum count, it is not necessary to utilize any other sensory inputs in order to properly tune the receiver over a wide pull in range (as much as plus or minus 2 MHz). Only the output of the conventional frequency discriminator 60 is used to provide the necessary sensory inputs.
The counter 82 of the microcomputer 23 is operated by the clock 81 during the foregoing sequence of operation, immediately following the selection of a new channel by the operation of the keyboard 25, at a fast or high speed operation. Typically, the counter steps are 10 milliseconds per step; so that there are no initial visual effects which can be noticed by an observer of the television screen of the receiver being tuned. The maximum forced search period is approximately 900 milliseconds in duration. At the end of this time interval, a timer in the microcomputer 23 causes a signal to be applied through the outputs of the E output port to the decoder circuit 52 indicative of the completion of this time interval. The decoder 52 then applies a pulse on an output lead connected to the B13 input of the B input port of the microcomputer 23. This pulse is sensed by the microcomputer 23 and is applied to the clock 81 to change the clock rate to a much slower rate, approximately one-third (1/3) or one-fourth (1/4) the rate used previously during the forced search mode of operation. This then permits the system to accomodate station drifts which normally occur at a very slow rate during the transmission and reception of a television signal. As a consequence, it is possible to use more filtering in the filter 39 on the tuning line (FIG. 1) and employ a smaller frequency window for the channel verification sensed by the circuitry shown in FIG. 3. The result is a more precise tuning from the receiver than is otherwise possible if only a high speed operation of the clock 81 is utilized.
When the channel once again is changed by operation of the keys in the keyboard 25 or operation of the channel selection circuitry from a remote control unit, this new channel input is sensed by the microcomputer 23 from the signals applied to the A input port and the clock 81 is reset to its fast time or the forced search mode of operation; and the process resumes.
Instead of employing an additional decoding function in the decoder 52, a separate decoder also could be connected to the outputs of the D output ports to feed back the signal to the B13 input terminal of the B input port of the microcomputer 23. The operation of the system to change the rate or frequency of the pulses applied by the clock 81 to the counter 82 otherwise is the same as described above.
Although applicant has found that it is preferable to correct for mistuning or frequency offsets by adjusting the count or division ratio of the counter 35, such offset adjustments also could be effected by adjusting the count in the counter 31 in the local oscillator signal line. The operation in such a case is the same as described above for adjusting the count in the counter 35.
If the receiver is to be used with an automatic signal seek mode of operation, however, additional sensory inputs are necessary. These inputs operate in conjunction with the output of the frequency discriminator 60. The operation of the microcomputer 23 in controlling the count of the reference programmable frequency counter divider 35 is the same as described above. The additional sensory inputs simply are used in conjunction with the outputs of the comparators 62 and 63 to signal the microcomputer 23 to assure that tuning is to a picture channel rather than an adjacent sound channel. This is accomplished by utilizing the output of the synchronizing signal separator 65 which is applied to a comparator 67 to produce an output signal to the SNS1 sensory input of the microcomputer 23 only when vertical synchronizing signal components are present.
In addition, the output of a picture carrier detector 69 is applied to the input of a comparator 70 to produce an output to the B10 sensory input of the microcomputer 23. If the picture carrier detector 69 is producing an output indicative of the presence of a carrier, but no output is being obtained from the vertical synch separator 65 at the same time, the system is mistuned to a sound carrier and the microcomputer 23 is permitted to continue its localized search until a properly tuned station is found. Only when there is coincidence of signals from the picture carrier detector 69, the synch signal separator 65, and the automatic frequency discriminator window as determined by the comparators 62 and 63, is the microcomputer operation terminated to indicate that a properly tuned channel is present.
Further insurance of tuning the receiver only to a strong signal also can be provided by the addition of an AGC amplifier 72. This is connected to a comparator 74 coupled to the B10 input port along with the output of the picture carrier detector comparator 70. When the AGC amplifier 72 is used as a sensory input, the microcomputer operation, when the system is used in a signal seek mode, is only terminated to indicate reception of a valid signal when that signal is strong enough to produce the desired output from the comparator 74. The signal level which is acceptable is set by a potentiometer 75.
It should be noted that when the system is operated in a signal seek mode, the sensory inputs must indicate the reception of a properly tuned signal within a pre-established time period. If no signal is sensed by the various sensory input circuits operating in conjunction with one another as described above, the microcomputer 23 automatically steps to the next channel number and repeats the sequence of operation described above. This is when it is placed in its signal seek mode of operation. If signal seek is not employed, the additional sensory circuits 65, 69 and 72 are not necessary, and the inputs to the microcomputer which are provided from these sensory circuits are not utilized. The sensory signal input which is used both for a receiver without a signal seek capability of operation and for a receiver which has a signal seek mode of operation in it, is the output of the frequency discriminator 60 operating in conjunction with the comparators 61, 62 and 63 as described above.
As indicated above, the wideband method of tuning precisely to an incoming signal that is at the wrong frequency described here only needs the frequency discriminator sensory information. The method that uses the additional sensors described above is needed to make this system operate compatibly with signal seek but it is not restricted to seek operation.
For a system that does not use signal seek operation, only the frequency discriminator sensory input is required for proper operation. The discriminator 60 is used for both fine tuning direction information and to produce a frequency window to indicate the presence of a correctly tuned station (channel verification). Initially, after a channel change, there is a 250 millisecond settling time, the same as the operation described above with compatible seek. After that, however, comes a period of time where a forced localized search is produced by the microcomputer 23. The forced search is needed to insure that the system will correctly tune to stations that initially may be tuned to the undesired zero voltage crossover in the right half of the upper curve of FIG. 5. Such signals may be within the frequency window of the discriminator 60; and if a search is not forced, this system will not correctly tune. The compatible seek system described previously correctly tunes the local oscillator without a forced search, because the picture carrier detector and vertical detector do not give an output for this situation and the system automatically goes into its search mode of operation. However, the non-seek system does not have a picture carrier sensor input and must be forced to search for an initial period of time sufficient to allow the system to tune up to its maximum frequency and then reset (loop) back to a frequency of 2 Δf lower. Then it is tuned to the positive left half portion of the discriminator curve (FIG. 5) and the frequency window created by the discriminator 60 is sufficient to insure proper tuning. If the discriminator output produced by the desired incoming signal created an initial situation that produces the correct tuning direction information, i.e., in the left half of the curve of FIG. 5, or in the right half portion that gives the correct direction and
frequency window information, the forced search would not be needed. However, the forced search will produce a correct tuning situation anyway. In these cases, the tuning either is correct to begin with or correct tuning is reached quickly. Then, even though the forced search is active, it simply alternates up and down through the correct tuning point because each time the receiver is tuned a little high in frequency, it produces a negative output from the discriminator 60; and the tuning direction signal causes the system to tune down in frequency.
Then, a positive discriminator output is produced, and the system tunes up in frequency. This continues until the forced search is removed by time-out of the microcomputer 23 (a fraction of a second). At such time, the receiver is correctly tuned by the frequency window of the discriminator to be very near fc. The system cannot tune to the undesired discriminator crossover shown in the right half portion of FIG. 5 because the polarity of the tuning direction signal always causes it to tune away from that point.
The fast time or forced search operation of the system can be terminated in a different way other than the preestablished time-out period described above in conjunction with the operation of the circuit shown in FIG. 2. Generally, it is desirable to build into the system (or program into the system by means of software) such a maximum time-out period to effect the operation which has been described above to terminate the search and cause the clock 81 thereafter to operate in a low speed mode of operation. Termination also can be accomplished by sensing the number of changes in the direction sensor input applied to the B12 terminal of the B input port to cause the search to be terminated when this direction changes three times (or more). By doing this, any flicker that might be observed on the screen of the television receiver is minimized, since the forced search still takes place at the high rate of application of clock pulses from the clock 81 to the counter 82 in the same manner described above.
Termination of the search, however, also may be effected by means of a search terminate counter 78 (FIG. 3), which is advanced by pulses applied to it each time the output of the comparator 61 changes its sign (indicative of a change in direction for the counter 82) as applied to it through the B12 input port, as described earlier. After three of these changes, or some other number if desired, an output pulse is obtained from the search terminate counter 78 and is applied to the SNS0 input of the microcomputer 23. This causes the operation of the clock 81 to be switched to its low speed mode of operation to terminate the fast or "forced search" mode of operation. The next time a new channel number is entered on the keyboard 25, a reset pulse is applied to the search terminate counter 78 to reset it to its original or zero count, thereby readying it for another sequence of operation. It is apparent that the search terminate counter 78 may not always be operated to terminate the count, since the time-out interval which is sensed by the decode circuit 52 and applied to the B13 input port of the microcomputer 23 may occur before there are three changes of direction of the search. In any event, the next time a new channel number is entered into the keyboard 25, the search terminate counter 78 is reset; so that it is irrelevant whether this counter reaches a full count or not to effect the termination of the forced search operation of the system.
FIG. 4 shows the control sequence of the system which is stored in the ROM (Read Only Memory) of the microcomputer 23. The microcomputer 23 operates by always running through the flow sequence, via loops L1, L2 and L3. Loop L1 corresponds to a new channel selection by two digit number entry. Loop L2 corresponds to channel number increment or decrement by an up or down key operation, respectively, or by seek operation. Loop L3 corresponds to fine tuning, either manual or automatic. To obtain exact timing for system control, the microcomputer 23 receives a standard timing pulse from the output of the reference counter 35 divided in a divide-by-five counter 80 and applied to the A13 input port of the microcomputer 23. The control functions which are programmed into the microcomputer 23, as indicated in the flow chart of FIG. 4, are outlined in the following paragraphs.
Channel Number Correction: An invalid two digit channel number entry (0, 1, 84, 99) is corrected. When the operation of the receiver is in the signal seek mode, the next channel up from 83 is channel 2, and the next lower channel from channel 2 is 83.
PLL Control I: For a given channel number, a corresponding binary code for the PLL selector counter 31 is derived as described previously. For UHF channels, the local oscillator frequency separation between two adjacent channels is 6 MHz and the code for PLL is generated by the microcomputer 23 through means of a simple calculation. This code then is transferred from the microcomputer 23 to the latches 44, 45 and 46 as described previously.
PLL Control II: This routine of the microcomputer 23 is used to transfer the fine tuning data to the latches 49 and 50 which control the count of the reference counter 35 in the PLL circuit.
Channel Number Display: The channel number is transferred from the microcomputer 23 to the driver latches of the display driver circuit 29.
Key Input Detection: The keyboard is arranged as the matrix circuit shown in FIG. 2. ROM programming for scanning and acknowledging a keyboard entry only after successive indications provides protection against false entry due to contact bounce. The four data output lines of the D output port of the microcomputer 23 are used to transfer data to the phase lock loop section of the circuit and to the display circuit 29, as well as for scanning the keyboard matrix circuit.
Time Count: The microcomputer 23 receives a basic timing pulse of approximately 200 Hz from the output of the divider 80 and performs various controls for each timing pulse. By way of example, sensing for the vertical synch input (when the system is used with a signal seek capability) on the input port SNS1 takes place every 2.5 milliseconds. Automatic seek timing is selected to be 133 milliseconds for UHF channels. All of these timing pulses are derived from the basic synchronization timing pulse applied to the microcomputer on the A13 input port from the output of the divider 80. Various other timing values used in the microcomputer to properly time multiplex sequence the operation are derived from this basic timing pulse.
Sensor Input Detection: As described previously, the output of the comparators shown in FIG. 3 reflect the status of the tuning of the television receiver. If no signal seek mode of operation is used, only the frequency discriminator or AFT discriminator 60 is necessary. When a system is being used in a signal seek mode, a proper television signal receipt is indicated by the presence of a vertical synch signal at the output of the synch signal separator 65 and corresponding outputs are applied to the input leads B10 and B11 (high level input signals) indicative of tuning to the "correct tuned" frequency discriminator window and reception of a picture carrier. As stated previously, the signal present on the B12 input lead is used to determine the direction of tuning when the receiver is operated in its automatic mode.
Mode Detection: The status of the seek and automatic/manual (A/M) switches are detected. If the A/M switch (not shown) is in its automatic position, automatic seek and offset correction are active. If only the seek switch is on, only seek is performed. If the A/M switch is in manual, manual fine tuning (MFT) is active.
Automatic Mode: If the TV receiver is not properly tuned for VHF channels in automatic, the local oscillator frequency is shifted automatically toward proper tuning. The fine tuning data is generated in the microcomputer 23 and is transferred to the latches 49 and 50 for the reference counter 35 in the PLL circuit.
Manual Fine Tuning (MFT) Control: The local oscillator frequency is shifted by pushing the fine tuning up (U) or down (D) pushbutton or switch. This MFT control can be applied to VHF channels as well as to UHF channels.
Channel Up/Down: When a channel up (upward pointing arrow) or down (downward pointing arrow) key closure in the keyboard 25 is detected, or upon a direct access to an unused channel, this routine is activated and the system will advance to the next channel in the selected direction.
The foregoing embodiment of the invention which has been described above and which is illustrated in the drawings is to be considered illustrative of the inventi
on, which is not limited to the specific embodiment selected for this purpose. For example, hard-wired logic could be used to achieve the various circuit operations which are accomplished by the microcomputer 23 in conjunction with the other portions of the system. The relative ease of programming and debugging the microcomputer 23, however, make it much simpler to implement the system operation with the microcomputer than with hard-wired logic. With respect to the sensor circuit inputs to the system, an added degree of operating assurance can be provided by the addition of a sound carrier sensor in addition to the picture carrier sensor shown in FIG. 3. If this feature is desired, the output of the comparator for the sound carrier is combined with the outputs of the comparators 70 and 74 at the input terminal B10 of the B input port of the microcomputer 23. Because of the manner of the circut operation which has been described previously, however, the addition of a sound carrier detector to the system is not considered necessary, even for a system operating in the signal seek mode of operation. This is in contrast to conventional television receivers having a signal seek operation, in which detection of the sound carrier generally is a necessity to insure that mistuning of the receiver to an adjacent sound carrier does not take place.
Both of the above mentioned patents are directed to frequency synthesizer tuning systems for use with television receivers to enable operation of the receivers with minimal viewer fine tuning adjustments. By the utilization of the frequency synthesizer tuning systems of these patents, the fine tuning adjustment which is necessary with conventional types of television receiver tuning systems has been substantially eliminated. The system employed in the '953 patent permits utilization of a frequency synthesizer tuning system which correctly tunes to a desired television station or channel even if the transmitted signals from that station are not precisely maintained at the proper frequencies. The '535 patent is directed to a signal seek tuning system adaptation of the frequency synthesizer tuning system of the '953 patent which still permits implementation of all of the desired wide-band pull in range of the frequency synthesizer system of the '953 patent.
The systems of the foregoing patents operate effectively to correct automatically for frequency offsets in a frequency synthesizer tuning system without affecting the operation of the conventional frequency synthesizer used in the system. The systems of these patents are in widespread use commercially and permit direct selection, with automatic fine tuning adjustment, of any desired VHF channel which the viewer wishes to observe. In addition, the signal seek adaptation disclosed in the '535 patent couples all of the advantages of the frequency synthesizer tuning system of the '953 patent with the desirability of providing bidirectional signal seek operation.
While the systems disclosed in the foregoing patents operate in a highly satisfactory manner to accomplish the desired results of accurate tuning without the necessity of fine tuning adjustments, the circuitry for accomplishing the desired results is somewhat complex. It is desirable to reduce the circuit complexity and the number of signal detectors for accomplishing these results without compromising the accuracy of operation of the system.
SUMMARY OF THE INVENTION
Accordingly, it is an object of this invention to provide an improved tuning system for a television receiver.
It is an additional object of this invention to provide an improved frequency synthesizer tuning system for a television receiver.
It is another object of this invention to provide an improved frequency synthesizer tuning system for a television receiver which includes a provision for adjusting the synthesizer loop for frequency offsets in the received signal with a minimum number of signal detectors.
It is still another object of this invention to provide an improved frequency synthesizer tuning system for a television receiver which operates to adjust the synthesizer loop for frequency offsets in the received signal over a relatively wide pull in range in response to the output of the receiver frequency discriminator by changing the division ratio of a programmable frequency divider in the reference oscillator leg or local oscillator leg of the synthesizer loop at a first relatively high rate from an initial nominal value to a pre-established maximum in one direction, and then resetting the division ratio to a second nominal value once the maximum is reached and continuing to incrementally change the division ratio in the same direction from the second nominal value until a properly tuned condition is indicated by the output of the receiver AFT frequency discriminator, followed by control at a lower rate of operation to maintain tuning during transmitting station drifts.
In accordance with a preferred embodiment of this invention, the frequency synthesizer tuning system for a television receiver includes a stable reference oscillator and a voltage controlled local oscillator in the tuner. A programmable frequency divider is connected between the output of the reference oscillator and one input to a phase comparator, the other input of which is supplied by the output of the local oscillator. The output of the phase comparator then comprises a control signal which is supplied to the local oscillator to control the frequency of its operation.
A counter circuit is connected to the programmable frequency divider for initially setting the divider to a predetermined division ratio upon selection of a desired channel by the viewer. The counter then operates to change the programmable fraction of the division ratio at a first relatively high rate in a direction controlled by the output from the receiver picture carrier discriminator in the absence of a predetermined signal output derived from the discriminator. A control means causes the counter circuit to count in this direction until it is determined that a station is tuned or a predetermined maximum count is attained if no station is correctly tuned, thereupon resetting the counter circuit to a count which is a predetermined amount less than the maximum predetermined count. Counting is continued in the same predetermined direction from the new lesser count to continuously change the programmable fraction of the frequency divider in accordance with the state of operation of the counter.The high rate operation of the counter is terminated by the control means in response to a predetermined signal from the output of the discriminator, indicating that a station is correctly tuned, or after a fixed time-out interval; so that the system automatically adjusts for frequency offsets of the received signal which otherwise would cause the station to be mistuned if a conventional frequency synthesizer tuning system were used. After termination of the high rate operation of the counter, it is switched to a lower rate operation for maintaining tuning during transmitting station drifts.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a block diagram of a television receiver employing a preferred embodiment of the invention;
FIG. 2 is a detailed block diagram of a portion of the circuit of the preferred embodiment shown in FIG. 1;
FIG. 3 is a detailed circuit diagram of a portion of a circuit shown in FIG. 1;
FIG. 4 is a flow chart of the control sequence of operation of the circuit shown in FIG. 1 and 2; and
FIG. 5 shows a waveform and time/frequency chart, respectively, useful in explaining the operation of the circuit shown in FIGS. 1, 2 and 3.
DETAILED DESCRIPTION
Referring now to the drawings, the same reference numbers are used throughout the several figures to designate the same or similar components.
FIG. 1 is a block diagram of a television receiver, which may be a black and white or color television receiver. Mo
st of the circuitry of this receiver is conventional, and for that reason it has not been shown in FIG. 1. Added to the conventional television receiver circuitry of FIG. 1, however, is a frequency synthesizer tuning system, in accordance with a preferred embodiment of the invention, which is capable of automatically changing the reference frequency when a frequency offset exists in the received signal for a particular channel.Transmitted composite television signals, either received over the air or distributed by means of a master antenna TV distribution system, are received by an antenna 10 or on antenna input terminals to the receiver. As is well known, these composite signals include picture and sound carrier components and synchronizing signal components, with the composite signal applied to an RF and tuner stage 11 of the receiver. The stage 11 includes the conventional RF amplifiers and tuner sections of the receiver, including a VHF oscillator section and a UHF oscillator section. Preferably, the UHF and VHF oscillators are voltage controlled oscillators, the freuency of operation of which are varied in response to a tuning voltage applied to them to effect the desired tuning of the receiver.
The output of the RF and tuner stages 11 is applied to the remainder of the television receiver 14, which includes the IF amplifier stages for supplying conventional picture (video) and sound IF signals to the video and sound processing stages of the receiver 14.
The circuitry of the receiver 14 may be of any conventional type used to separate, amplify and otherwise process the signals for application to a cathode ray tube 16 and to a loudspeaker 17 which reproduce the picture and sound components, respectively, of the received signal.The receiver 14 also includes a conventional AFT or automatic fine tuning discriminator circuit and additionally may include a synch separator circuit for producing an output in response to the presence of vertical synchronizatin pulses, a picture carrier detection circuit, and an automatic gain control (AGC) amplifier. Outputs representative of these sensor components are shown as being coupled over a group of lead 20 to sensory circuitry 22, which in turn couples outputs representative of the operation of these various sensor circuits to a microprocessor unit 23 for controlling the operation of the microprocessor unit.
The microprocessor unit 23 is utilized in the system of FIG. 1 for controlling the operation of a frequency synthesizer tuning system capable of automatic offset correction. When the viewer desires to select a new channel, he enters the desired channel number into a channel selection keyboard 25. There are a number of different keyboards which may be employed to accomplish this function, and the particular design is not important to this invention. The channel selector keyboard 25 also may include switches or keys for initiating a signal seek function in either the "up" or "down" direction.
Information represented by the selection of channel numbers on the keyboard 25 is supplied to the microprocessor unit 23 which provides output signals over a corresponding set of leads 27 to the tuners (local oscillators) 11 to effect the appropriate band switching control for the tuners 11 in accordance with the particular channel which has been selected. In addition, the keyboard 25, operating through the microprocessor unit 23, provides output signals which operate a channel number display 29 to provide an appropriate display of the selected channel number to the viewer.
The output of the oscillator 34 also is applied through a countdown circuit or programmable frequency divider 35. Conventional frequency synthesizer techniques are employed; and the microprocessor unit 23 automatically compensates, through appropriate code converter circuitry, for the non-uniform channel spacing of the television signals. It has been found most convenient to cause the programmable frequency divider 31 to divide by numbers corresponding directly to the oscillator frequency of the selected channel, for example, 101, 107, 113 . . . up to 931.
In accordance with the time division multiplex operation of the microprocessor 23, the count of the programmable frequency divider 35 initially is adjusted to a fixed count by the application of appropriate output signals from the microprocessor unit 23 to a point selected to be at or near the mid-point of the operating range of the programmable frequency divider 35. Thus, the output of the divider 35 is a stable reference frequency (because the input is from the reference crystal oscillator 34) which is used to establish initially and to maintain tuning of the receiver to the selected channel.
The output of the programmable divider 35 is applied to one of two inputs of a phase comparator circuit 37. The other input to the phase comparator circuit 37 is supplied from the selected one of the VHF or UHF oscillators in the tuner stages 11 through the programmable frequency divider 31. The phase comparator circuit 37 operates in a conventional manner to supply a DC tuning control signal through a phase locked loop filter circuit 39 and over a lead 40 to the oscillators in the tuner system 11 to change and maintain their operating frequency.
With the exception of the use of the microprocessor unit 23, the operation of the system which has been described thus far is that of a relatively conventional frequency synthesizer system incorporated into a television receiver. This system is similar to the system of the '953 patent. As in the system of that patent, the system shown in FIG. 1, when the transmitted station or station received on a master antenna distribution system provides the station or channel signals at the proper frequency, operates as a relatively conventional frequency synthesizer system. If, however, there is a frequency offset in the received signal to cause the carrier of the received signal to be displaced from the frequency which it should have to some other frequency, it is possible that the system would give the appearance of mistuning to the received station. The microprocessor 23, operating in conjunction with the sensory circuitry 22, is employed in conjunction with the countdown or programmable frequency divider circuit 35 to eliminate this disadvantage and still retain the advantages of frequency synthesizer tuning.
Reference now should be made to FIG. 2 which shows details of t
he interface between the keyboard 25, the microprocessor unit 23, and the circuitry used in the frequency synthesizer portions of the system. A commercially available microprocessor which has been used for the microprocessor 23, and which forms the basis for the diagramatic representation of the microprocessor in FIG. 2, is the Matsushita Electronics Corporation MN1402 four-bit single-chip microcomputer. This microcomputer has two, four-bit parallel input ports labeled "A" and "B". In addition, three output ports, a five-bit output port "C" and two four-bit output ports "D" and "E" are provided. The internal configuration of the microcomputer 23 includes an arithmetic logic unit (ALU), a read only memory (ROM) for storing instructions and constants, and a random access memory (RAM) used for data memory, arranged into four files, each file containing 16 four-bit words. These words are selected by X and Y registers and this memory is used, for example, for timers, counters, etc., and also is used to hold intermediate results. To facilitate an understanding of the operation of the system, a portion of this memory is shown in FIG. 2 as a clock 81 and a reversible counter 82 connected between the "B" input port and the "D" output port. The microcomputer 23 is programmed to permit it to operate in conjunction with the remainder of the circuits shown in FIG. 2. The programming techniques are standard, and the microcomputer 23 itself is a standard commercially available circuit component.There are several system parameters that must be selected in the operation of the system shown in FIG. 2. The selection of the nominal frequency of the two signals that feed the phase comparator circuit 37 is an example. Channel selection is provided by changing the frequency division ratio of the selector counter 31 which divides the local oscillator signal after this signal is passed through a prescaler circuit 32 and a divide-by-two divider circuit 41. The nominal frequency from the programmable frequency divider 31 (selector counter) is selected so that the local oscillator (tuner) 11 can be set exactly on frequency for all channels.
A compromise solution which is utilized in the circuit of FIG. 2 is to cause the frequency division chain from the local oscillator 11 in the tuner to the phase comparator 37 to be composed of the fixed divide-by-256 prescaler 32, and a fixed divide-by-4 division, which is accomplished by the divider 41 at the input of the counter 31 and a second divider 42 at the output of the counter 31. The variable frequency divider counter 31 then is loaded by means of three latch circuits 44, 45 and 46 at an appropriate time by the time division multiplex operation of the microcomputer 23 and a number that programs the programmable frequency divider counter 31 to divide by the numerical value of the frequency of the local oscillator in MHz for the channel selected. For example, if the receiver is to be tuned to channel 2, which has a nominal local oscillator frequency of 101 MHz, the programmable frequency divider 31 is set to divide by 101. If the receiver is to be tuned to channel 83, which has a nominal local oscillator frequency of 931 MHz, the programmable frequency divider 31 is set to divide by 931. In both cases, the variable divider 31 produces a 1 MHz signal. However, because of the fixed divide-by-256 and the two fixed divide-by-two dividers in series with the programmable divider 31, an output frequency of 976.5625 Hz is supplied from the output of the divider 42 to the upper input of the phase comparator 37.
propriate output signals from the latch circuits 44, 45 and 46, as mentioned above. The initial operation for changing, or maintaining, the division ratio of the divider 31 is established by an entry of the two digits of the selected channel number in the keyboard 25. The microcomputer 23 operates as a time division multiplex system for continuously monitoring the input ports and the output ports to control the operation of the remainder of the system. The selection of the two digits of the desired channel number is affected by a time division multiplex iscanning of the outputs of the D output port of microcomputer 23 and providing that information at the A input port. From here the information is translated again to the D output ports to the appropriate drivers of the channel number display circuit 29 and to the latches 44, 45 and 46, and to a pair of similar four bit latches 49 and 50 which control the divider ratio of the counter 35.Although the D output ports of the microcomputer 23 are connected in common to all of these various portions of the circuit, the selection of which of the latches are enabled to respond to the particular output signals appearing on the D output ports at any given time is effected through the C and E output ports of the microcomputer 23 in a time division multiplex fashion. A decoder circuit 52, connected to the lowermost three outputs of the E output port of the microcomputer 23, is used to apply unique decoding signals at different times in the time division multiplex sequence of operation of the microcomputer 23 to the five latch circuits 44, 45, 46, 49 and 50, respectively. At any given time in the sequence, only one of these latch circuits is enabled for operation. A latch load signal is applied from the upper output (EO3) at each cycle of operation of the signals appearing on the E output port to set the latch circuit which is enabled by the output of the decoding circuit 52 with the data appearing on the other inputs to the latch circuit. This data simultaneously appears on the four outputs of the D output port of the microcomputer 23.
Thus, in rapid sequence, the latch circuits 44, 45 and 46 are set to store the division number corresponding to the selected channel entered onto the keyboard 25, and the latch circuits 49 and 50 are each operated to set the programmable divider reference counter 35 to a center or nominal count, which is always the same upon the selection of a new channel on the keyboard 25. Similarly, the two right-hand outputs of the C output port (CO6 and CO5) enter the two digits of the selected channel number in the drivers of the display circuit 29 at the proper time in the binary encoded sequence when these digits appear on the four-bit binary encoded representation of the D output port. This results in a visual display of the channel number selected.
In addition to the selection of a channel number directly by the keyboard 25, the keyboard also may include an additional switch 56, which is scanned in the time division multiplex sequence to determine if the receiver is placed in a "seek" mode of operation (when the signal seek capability is incorporated into such a receiver). Operating in conjunction with the signal seek switch 56 are a pair of "up" and "down" seek direction input switches shown with a graphic representation of the seek directions on the keyboard 25. A further provision is provided by two keys labeled "U" and "D", which are used for "manual" fine tuning of the receiver in the "up" or "down" directions depending upon which of the two keys U or D has been operated. The keyboard 25 includes one additional switch 58 which may be used to disable the automatic fine tuning (AFT) portion of the circuit by rendering the microcomputer insensitive to the signal output from the AFT circuit, in a manner described more fully subsequently.
As is apparent from the foregoing, the microcomputer 23 provides the intelligence, decision making, and control for the system operation. It is a complete self contained computer. The decisions or signal inputs upon which the microcomputer 23 bases its operation include, in addition to the inputs from the keyboard 25, inputs on sensory inputs into the B input port and into the SNS1 and SNS0 inputs as shown in FIG. 2. These input signals are used to provide an indication to the microcomputer 23 of the presence or absence of a received signal; and if the presence of such a signal is indicated, the inputs provide a further indication of the accuracy of the tuning of the receiver to that signal. If the system is being operated solely in a manual mode of operation (AFT switch 58 open), the microcomputer 23 disregards all of this sensory information and tunes to the frequency allocation of the channel selected in the manner described above. The system will stay tuned to this condition, operating as a conventional frequency synthesizer, whether or not a station is present in the received signal.
When the system is placed in its automatic mode of operation (similar to the mode of operation of the above mentioned '953 patent), the counter 82, integrally formed as part of the microcomputer 23, continuously adds or subtracts one number at a time from the nominal value or programmable division fraction entered into the programmable frequency divider 35 at the outset of each new channel number selection when frequency offset (mistuning) is present. The counter 82 is driven at a relatively high counting rate by clock pulses from the clock 81 during this initial or forced search mode of operation. Thus, automatic offset correction is provided for any channel which is off its assigned frequency. The offset correction automatically adjusts the frequency of the local oscillator by changing the division ratio of the signal from the reference oscillator 35 applied to the lower input of the phase comparator 37. By doing this, the output of the phase comparator 37 applied to the local oscillator 11 varies to cause the oscillator to be tuned in the proper direction to compensate for the transmitting station mistuning.When the system is operating in its automatic mode of operation, the microcomputer 23 responds to the sensor information applied to it on its B input ports and on the S1 input port shown in FIG. 2. These inputs are obtained from the various outputs of the operational amplifiers shown connected to the corresponding input ports in the detailed circuit of FIG. 3. Depending upon whether the receiver is provided with a signal seek feature or not, one or more of the sensory inputs of the circuit of FIG. 3 are used. The s
ystem shown in the drawings has a capability of correcting for frequency offsets larger than 1.5 MHz on channels 2 and 7 and approximately 2 MHz on channels 6 and 13. The remainder of the channels have a range between these two values.If the receiver is not tuned properly, the micromputer 23 executes the localized search of the tuning range mentioned above. Since there is a necessary settling down time for the tuning of a television receiver immediately following selection of a new channel, a time interval of 250 milliseconds has been selected to prevent any localized search or offset frequency correction until the expiration of this "settling down" time period. If, at the end of this 250 millisecond time interval, a properly tuned station is present, this is indicated by the sensory outputs from the television receiver and no localized search is effected to change the division ratio or programmable divider count in the reference counter 35 for a system that also has signal seek.
A system with no signal seek capability is described later that requires less sensory input but which uses a time period where a forced search is required directly after the settling time interval.
The lower graph of FIG. 5 plots the relative frequency of the local oscillator 11 to the received signal frequency with respect to time. The various arrows are used to indicate the manner of operation of the counter 82 in the microcomputer 23 in conjunction with the reference counter 35 for adjusting for any mistuning conditions which may exist after the initial station selection has been effected in the manner described above.
If the receiver is properly tuned, the outputs from the comparators 62 and 63 of FIG. 3 which are combined together and applied to the input port B11 of the microcomputer 23, provide an indication that the tuning is within the properly tuned center frequency window. As a consequence, no further operation of the microcomputer to change any of the outputs applied to the latch circuits 49 and 50 for the duration of this condition is effected. On the other hand, if the receiver is mistuned on either side of the proper tuning frequency, the various operating characteristics shown in FIG. 5 are effected.
Assume initially that the receiver is capable of making tuning adjustments over a range of fc plus Δf to fc minus Δf, as indicated in the top waveform of FIG. 5. Three specific examples of mistuning will then be considered. Initially, assume that the local oscillator is mistuned relative to the received signal to a frequency f1 as shown in the lower graph of FIG. 5. In this condition, the outout of the frequency discriminator 60 is positive since this signal frequency lies to the lefthand side of the center or properly tuned region of operation of the discriminator. Under this condition of the
operation, the input signal applied to the sensor port B12 of the microcomputer 23 is such that the microcomputer counter 82 is caused to advance in a positive direction to change the programmable division ratio or count of the reference counter 35 in a manner to force the output of the phase comparator 37 to adjust the frequency of the local oscillator until the proper tuning indicated at point B in the lower graph of FIG. 5 is reached. The time interval for accomplishing this result is measured from the upper end of the arrow representative of the frequency f1 to the point B.Now assume that the receiver mistuning is to a frequency f2 which as shown in FIG. 5 as located on the righthand-side of the center axis fc. In this condition, the discriminator output is negative. This is reflected in the output of the comparator 61 applied to the input port B12 of the microcomputer 23. The polarity of this signal is identified by the microcomputer 23 to cause the counter 82 in it to operate in the reverse direction. As this count is applied on a step-by-step basis through the latch circuits 49 and 50 to the reference counter 35, the division ratio or count of the reference counter (divider) 35 is changed. As a result, the reference oscillator signal applied to the phase comparator 37 causes the phase comparator 37 output to drive the local oscillator frequency in a direction opposite to that considered in the first example. This is shown by the vector interconnecting the top of the arrow representative of f2 to point A on the time/frequency graph of FIG. 5.
As discussed in the general discussion above, whenever the tuning frequency reaches the narrow window on either side of fc, the outputs of the comparators 62 and 63 provide the necessary indication on the sensory input port terminal B11 to cause termination of the operation of the counter 82 in the microcomputer 23. Then the reference counter 35 remains set to the count attained just prior to the appearance of this input signal on the input port B11 of the microcomputer 23.
A third mistuning condition can exist, and ordinarily this condition results in an ambiguity which cannot be corrected simply by responding to the signal polarity at the output of the frequency discriminator. This is indicated by the mistuned condition where the difference between the local oscillator frequency f3 and the transmitter frequency is such that the signal f3 lies in the range to the right of the negative portion of the discriminator output shown in the upper waveform of FIG. 5. In this condition, the associated sound causes the discriminator output to be positive; so that the television receiver normally would attempt to tune toward the next adjacent channel and away from the properly tuned center frequency of the channel which is desired. The output of the discriminator 60 in this situation is the same as it was in th
e first example considered for frequency f1; so that the counter 82 of the microprocessor 23 operates to change the count in the reference counter 35 in a manner to cause the local oscillator frequency to go higher toward a frequency f3 +Δf, as shown in FIG. 5.A predetermined number of counts of the counter 82 in the microcomputer 23 are necessary for the microcomputer to count through the frequency range Δf, and this range is selected to be within the pull in or operating range of the system. Once this count has been attained, the microcomputer counter 82 immediately is reset back to a count which corresponds to a frequency 2 Δf lower than the frequency attained by the maximum count. This is indicated in FIG. 5 by the frequency f3-Δf. Because the microcomputer counter 82 is limited to counting a number of counts equal to Δf, this new frequency now is on the lefthand side of the center line fc, shown in both waveforms of FIG. 5. This places the local oscillator frequency at a point such that the frequency discriminator output is the positive output shown on the lefthand-side of the upper waveform of FIG. 5. Counting continues in the same direction as previously. This time, however, it is in a proper direction to bring about correct tuning; and when the center frequency is reached, the output of the comparators 62 and 63 cause the microcomputer 23 to stop its count. The proper tuning point attained is indicated at point C on the graph of the lower part of FIG. 5.
The counter 82 of the microcomputer 23 is operated by the clock 81 during the foregoing sequence of operation, immediately following the selection of a new channel by the operation of the keyboard 25, at a fast or high speed operation. Typically, the counter steps are 10 milliseconds per step; so that there are no initial visual effects which can be noticed by an observer of the television screen of the receiver being tuned. The maximum forced search period is approximately 900 milliseconds in duration. At the end of this time interval, a timer in the microcomputer 23 causes a signal to be applied through the outputs of the E output port to the decoder circuit 52 indicative of the completion of this time interval. The decoder 52 then applies a pulse on an output lead connected to the B13 input of the B input port of the microcomputer 23. This pulse is sensed by the microcomputer 23 and is applied to the clock 81 to change the clock rate to a much slower rate, approximately one-third (1/3) or one-fourth (1/4) the rate used previously during the forced search mode of operation. This then permits the system to accomodate station drifts which normally occur at a very slow rate during the transmission and reception of a television signal. As a consequence, it is possible to use more filtering in the filter 39 on the tuning line (FIG. 1) and employ a smaller frequency window for the channel verification sensed by the circuitry shown in FIG. 3. The result is a more precise tuning from the receiver than is otherwise possible if only a high speed operation of the clock 81 is utilized.
When the channel once again is changed by operation of the keys in the keyboard 25 or operation of the channel selection circuitry from a remote control unit, this new channel input is sensed by the microcomputer 23 from the signals applied to the A input port and the clock 81 is reset to its fast time or the forced search mode of operation; and the process resumes.
Instead of employing an additional decoding function in the decoder 52, a separate decoder also could be connected to the outputs of the D output ports to feed back the signal to the B13 input terminal of the B input port of the microcomputer 23. The operation of the system to change the rate or frequency of the pulses applied by the clock 81 to the counter 82 otherwise is the same as described above.
Although applicant has found that it is preferable to correct for mistuning or frequency offsets by adjusting the count or division ratio of the counter 35, such offset adjustments also could be effected by adjusting the count in the counter 31 in the local oscillator signal line. The operation in such a case is the same as described above for adjusting the count in the counter 35.
If the receiver is to be used with an automatic signal seek mode of operation, however, additional sensory inputs are necessary. These inputs operate in conjunction with the output of the frequency discriminator 60. The operation of the microcomputer 23 in controlling the count of the reference programmable frequency counter divider 35 is the same as described above. The additional sensory inputs simply are used in conjunction with the outputs of the comparators 62 and 63 to signal the microcomputer 23 to assure that tuning is to a picture channel rather than an adjacent sound channel. This is accomplished by utilizing the output of the synchronizing signal separator 65 which is applied to a comparator 67 to produce an output signal to the SNS1 sensory input of the microcomputer 23 only when vertical s
ynchronizing signal components are present.In addition, the output of a picture carrier detector 69 is applied to the input of a comparator 70 to produce an output to the B10 sensory input of the microcomputer 23. If the picture carrier detector 69 is producing an output indicative of the presence of a carrier, but no output is being obtained from the vertical synch separator 65 at the same time, the system is mistuned to a sound carrier and the microcomputer 23 is permitted to continue its localized search until a properly tuned station is found. Only when there is coincidence of signals from the picture carrier detector 69, the synch signal separator 65, and the automatic frequency discriminator window as determined by the comparators 62 and 63, is the microcomputer operation terminated to indicate that a properly tuned channel is present.
Further insurance of tuning the receiver only to a strong signal also can be provided by the addition of an AGC amplifier 72. This is connected to a comparator 74 coupled to the B10 input port along with the output of the picture carrier detector comparator 70. When the AGC amplifier 72 is used as a sensory input, the microcomputer operation, when the system is used in a signal seek mode, is only terminated to indicate reception of a valid signal when that signal is strong enough to produce the desired output from the comparator 74. The signal level which is acceptable is set by a potentiometer 75.
It should be noted that when the system is operated in a signal seek mode, the sensory inputs must indicate the reception of a properly tuned signal within a pre-established time period. If no signal is sensed by the various sensory input circuits operating in conjunction with one another as described above, the microcomputer 23 automatically steps to the next channel number and repeats the sequence of operation described above. This is when it is placed in its signal seek mode of operation. If signal seek is not employed, the additional sensory circuits 65, 69 and 72 are not necessary, and the inputs to the microcomputer which are provided from these sensory circuits are not utilized. The sensory signal input which is used both for a receiver without a signal seek capability of operation and for a receiver which has a signal seek mode of operation in it, is the output of the frequency discriminator 60 operating in conjunction with the comparators 61, 62 and 63 as described above.
As indicated above, the wideband method of tuning precisely to an incoming signal that is at the wrong frequency described here only needs the frequency discriminator sensory information. The method that uses the additional sensors described above is needed to make this system operate compatibly with signal seek but it is not restricted to seek operation.
frequency window information, the forced search would not be needed. However, the forced search will produce a correct tuning situation anyway. In these cases, the tuning either is correct to begin with or correct tuning is reached quickly. Then, even though the forced search is active, it simply alternates up and down through the correct tuning point because each time the receiver is tuned a little high in frequency, it produces a negative output from the discriminator 60; and the tuning direction signal causes the system to tune down in frequency.
The fast time or forced search operation of the system can be terminated in a different way other than the preestablished time-out period described above in conjunction with the operation of the circuit shown in FIG. 2. Generally, it is desirable to build into the system (or program into the system by means of software) such a maximum time-out period to effect the operation which has been described above to terminate the search and cause the clock 81 thereafter to operate in a low speed mode of operation. Termination also can be accomplished by sensing the number of changes in the direction sensor input applied to the B12 terminal of the B input port to cause the search to be terminated when this direction changes three times (or more). By doing this, any flicker that might be observed on the screen of the television receiver is minimized, since the forced search still takes place at the high rate of application of clock pulses from the clock 81 to the counter 82 in the same manner described above.
Termination of the search, however, also may be effected by means of a search terminate counter 78 (FIG. 3), which is advanced by pulses applied to it each time the output of the comparator 61 changes its sign (indicative of a change in direction for the counter 82) as applied to it through the B12 input port, as described earlier. After three of these changes, or some other number if desired, an output pulse is obtained from the search terminate counter 78 and is applied to the SNS0 input of the microcomputer 23. This causes the operation of the clock 81 to be switched to its low speed mode of operation to terminate the fast or "forced search" mode of operation. The next time a new channel number is entered on the keyboard 25, a reset pulse is applied to the search terminate counter 78 to reset it to its original or zero count, thereby readying it for another sequence of operation. It is apparent that the search terminate counter 78 may not always be operated to terminate the count, since the time-out interval which is sensed by the decode circuit 52 and applied to the B13 input port of the microcomputer 23 may occur before there are three changes of direction of the search. In any event, the next time a new channel number is entered into the keyboard 25, the search terminate counter 78 is reset; so that it is irrelevant whether this counter reaches a full count or not to effect the termination of the forced search operation of the system.FIG. 4 shows the control sequence of the system which is stored in the ROM (Read Only Memory) of the microcomputer 23. The microcomputer 23 operates by always running through the flow sequence, via loops L1, L2 and L3. Loop L1 corresponds to a new channel selection by two digit number entry. Loop L2 corresponds to channel number increment or decrement by an up or down key operation, respectively, or by seek operation. Loop L3 corresponds to fine tuning, either manual or automatic. To obtain exact timing for system control, the microcomputer 23 receives a standard timing pulse from the output of the reference counter 35 divided in a divide-by-five counter 80 and applied to the A13 input port of the microcomputer 23. The control functions which are programmed into the microcomputer 23, as indicated in the flow chart of FIG. 4, are outlined in the following paragraphs.
Channel Number Correction: An invalid two digit channel number entry (0, 1, 84, 99) is corrected. When the operation of the receiver is in the signal seek mode, the next channel up from 83 is channel 2, and the next lower channel from channel 2 is 83.
PLL Control I: For a given channel number, a corresponding binary code for the PLL selector counter 31 is derived as described previously. For UHF channels, the local oscillator frequency separation between two adjacent channels is 6 MHz and the code for PLL is generated by the microcomputer 23 through means of a simple calculation. This code then is transferred from the microcomputer 23 to the latches 44, 45 and 46 as described previously.PLL Control II: This routine of the microcomputer 23 is used to transfer the fine tuning data to the latches 49 and 50 which control the count of the reference counter 35 in the PLL circuit.
Channel Number Display: The channel number is transferred from the microcomputer 23 to the driver latches of the display driver circuit 29.
Key Input Detection: The keyboard is arranged as the matrix circuit shown in FIG. 2. ROM programming for scanning and acknowledging a keyboard entry only after successive indications provides protection against false entry due to contact bounce. The four data output lines of the D output port of the microcomputer 23 are used to transfer data to the phase lock loop section of the circuit and to the display circuit 29, as well as for scanning the keyboard matrix circuit.
Time Count: The microcomputer 23 receives a basic timing pulse of approximately 200 Hz from the output of the divider 80 and performs various controls for each timing pulse. By way of example, sensing for the vertical synch input (when the system is used with a signal seek capability) on the input port SNS1 takes place every 2.5 milliseconds. Automatic seek timing is selected to be 133 milliseconds for UHF channels. All of these timing pulses are derived from the basic synchronization timing pulse applied to the microcomputer on the A13 input port from the output of the divider 80. Various other timing values used in the microcomputer to properly time multiplex sequence the operation are derived from this basic timing pulse.
Sensor Input Detection: As described previously, the output of the comparators shown in FIG. 3 reflect the status of the tuning of the television receiver. If no signal seek mode of operation is used, only the frequency discriminator or AFT discriminator 60 is necessary. When a system is being used in a signal seek mode, a proper television signal receipt is indicated by the presence of a vertical synch signal at the output of the synch signal separator 65 and corresponding outputs are applied to the input leads B10 and B11 (high level input signals) indicative of tuning to the "correct tuned" frequency discriminator window and reception of a picture carrier. As stated previously, the signal present on the B12 input lead is used to determine the direction of tuning when the receiver is operated in its automatic mode.
Mode Detection: The status of the seek and automatic/manual (A/M) switches are detected. If the A/M switch (not shown) is in its automatic position, automatic seek and offset correction are active. If only the seek switch is on, only seek is performed. If the A/M switch is in manual, manual fine tuning (MFT) is active.
Automatic Mode: If the TV receiver is not properly tuned for VHF channels in automatic, the local oscillator frequency is shifted automatically toward proper tuning. The fine tuning data is generated in the microcomputer 23 and is transferred to the latches 49 and 50 for the reference counter 35 in the PLL circuit.
Manual Fine Tuning (MFT) Control: The local oscillator frequency is shifted by pushing the fine tuning up (U) or down (D) pushbutton or switch. This MFT control can be applied to VHF channels as well as to UHF channels.
Channel Up/Down: When a channel up (upward pointing arrow) or down (downward pointing arrow) key closure in the keyboard 25 is detected, or upon a direct access to an unused channel, this routine is activated and the system will advance to the next channel in the selected direction.
The foregoing embodiment of the invention which has been described above and which is illustrated in the drawings is to be considered illustrative of the inventi
TDA2545A Quasi-split-sound circuitGENERAL DESCRIPTION The TDA2545A is a monolithic integrated circuit for quasi-split-sound processing in television receivers. Features · 3-stage gain controlled i.f. amplifier · A.G.C. circuit · Reference amplifier and limiter amplifier for vision carrier (V.C.) processing · Linear multiplier for quadrature demodulation.
TDA2541 IF AMPLIFIER WITH DEMODULATOR AND AFC
DESCRIPTION
The TDA2540 and 2541 are IF amplifier and A.M.
demodulator circuits for colour and black and white
televisionreceiversusingPNPorNPNtuners. They
are intended for reception of negative or positive
modulation CCIR standard.
They incorporate the following functions : .Gain controlled amplifier .Synchronous demodulator .White spot inverter .Video preamplifier with noise protection .Switchable AFC .AGC with noise gating .Tuner AGC output (NPN tuner for 2540)-(PNP
tuner for 2541) .VCR switch for video output inhibition (VCR
play back).
TDA2006 12W AUDIO AMPLIFIER
DESCRIPTION
The TDA2006 is a monolithic integrated circuit in
Pentawatt package, intended for use as a low
frequency class ”AB” amplifier. At ±12V, d = 10 %
typically it provides12Woutput poweron a 4W load
and 8W on a 8W . The TDA2006 provides high
output current and has very low harmonic and
cross-over distortion. Further the device incorporates
anoriginal (and patented)short circuit protection
system comprising an arrangement for
automatically limiting the dissipated power so as to
keep the working point of the output transistors
within their safe operating area. A conventional
thermal shutdown system is also included. The
TDA2006 is pin to pin equivalent to theTDA2030.
SHORT CIRCUIT PROTECTION
The TDA2006 has an original circuit which limits
the current of the output transistors.
This function can thereforebe considered as being
peak power limiting rather than simple current limiting.
It reduces the possibility that the device gets damaged
during an accidental short circuit from AC
output to ground.
THERMALSHUT DOWN
The presence of a thermal limiting circuit offers the
following advantages :
1) an overload on the output (even if it is
permanent), or an above l imi t ambient
temperature can be easily supported since the
Tj cannot be higher than 150°C.
2) the heatsink can have a smaller factor of safety
compared with that of a conventional circuit.
There is no possibility of device damage due to
high junction temperature.
If for any reason, the junction temperature increases
up to 150 °C, the thermal shutdown simply
reduces the power dissipation and the current consumption.
The maximum allowable power dissipation depends
upon the size of the external heatsink (i.e.
its thermal resistance)
METZ CHASSIS 681G Blanking voltage generator for a cathode ray tube:
The circuit senses the cut-off voltage of each gun during the blanking interval, and uses a voltage equal to the cut-off voltage to energize the driver and bias the gun during the video field. The effect is to standardize the emission of each of the three guns against variation in gun cut-off voltage and to produce improved gray scale accuracy at the lowest emission levels. Since the gray scale adjustment is optimized at the lowest emission levels, where the eye is most intolerant to error in hue, one may avoid the need for manual adjustment of the cut-off point, and in cases where the gain does not vary widely from gun to gun, avoid the need for separate gain adjustment. Thus, the circuit may be used either to simplify or eliminate the color set up process at the factory when the receiver is manufactured. It may also reduce or avoid the need for readjustment after periods of use.
Apparatus is disclosed for generating a blanking voltage for electron guns in cathode ray tubes, as used, for example, in color television displays. Apparatus utilizes circuitry including a video voltage amplifier having a control input. A feedback loop, connected between the junction of the cathode and video voltage amplifier output at one terminal, and the control input at the other, modifies the blanking voltage in response to samples of the cathode current taken when the video signal is zero.1. Apparatus for generation of a blanking voltage for a cathode ray tube usable for display of television signals and having an electron gun, including a cathode, comprising means sensitive to intensity of cathode current and sampling meand connected for enabling said means sensitive to intensity of cathode current at periods during which a video signal applied to said cathode is equal to zero, and control means for modifying said blanking voltage according to said intensity in such a manner as to blank the beam current when the video signal is equal to zero, characterized by:
(a) a video voltage amplifier means for applying said video voltage and said blanking voltage signals to the cathode of said electron gun, said video voltage amplifier having an output and a control input, the control means comprising:
(i) means for servo-control of said blanking voltage including a feedback loop between: (a) a connection joining the output of said video voltage amplifier to said cathode, and (b) said control input of said video voltage amplifier means,
(ii) said feedback loop comprising a current amplifier means for increasing the cathode current,
(iii) said current ampl
ifier means having an input and an output and further having an output impedance that is high in relation to the output impedance of said video voltage amplifier means, the input circuit of said current amplifier means being connected to the connection joining said cathode to the output of said video voltage amplifier means; and (b) memory storage means having an input connected to the output of said current amplifier means, and an output connected to said control input of said video voltage amplifier means, to maintain a control signal at said control input between successive sampling periods.2. Apparatus in accordance with claim 1, further comprising controlled interruptor means, connected to said current amplifier means, for inhibiting operation of said feedback loop upstream to said memory storage means, at times other than said sampling periods.
3. Apparatus in accordance with claim 2 wherein said interruptor means is connected in short-circuiting relationship to the input of the current amplifier to short-circuit the latter at times other than said sampling periods.
4. Apparatus in accordance with claim 3, further comprising generating means for controlling said interruptor means, said generating means generated current pulses during said sampling periods or during complementary periods, said generating means having an output impedance high in relation to the output impedance of said video voltage amplifier means, and circuit means providing a circuit path for said current pulses and including the output of the video voltage amplifier means.
5. Apparatus in accordance with claim 4, further comprising control signal generating means for opening said interruptor means in case of abnormal operating conditions of said means for generating current pulses, including a condition of permanent absence of such pulses.
6. Apparatus in accordance with claims 4 or 5, wherein said means for generating current pulses comprises converting means for converting voltage pulses, generated during the sampling periods or the complementary periods, into current pulses.
7. Apparatus in accordance with claim 1 wherein said video voltage amplifier means is of the active load type.
8. Apparatus in accordance with claim 2 wherein said interruptor means is connected in short-circuiting relationship to said memory storage means for short-circuiting said memory storage means at times other than said sampling periods.
9. Apparatus in accordance with claim 8 wherein said interruptor means is connected between: (i) a connection joining the output of said current amplifier means to said memory storage means, and (ii) a point of constant potential.
10. Apparatus in accordance with claims 8 or 9, wherein said cathode ray tube comprises three electron guns for display of color images, ea
ch one of said electron guns corresponding to a separate one of said control means and connected thereto; and Further comprising means common to the three control means for generation of voltage pulses during sampling periods or during complementary periods, and for controlling said interruptor means thereby.
11. Apparatus in accordance with claim 10 wherein said means common comprises, in common to the three control means, means for the generation of a control signal for opening said interruptor means in case of abnormal operating conditions of the means for the generation of voltage signals, including a condition of permanent absence of such pulses.
12. Apparatus in accordance with claim 1, further including television receiver means connected to said cathode ray tube.
13. Apparatus in accordance with claim 12 wherein said cathode ray tube includes three electron guns for color display of television signals on a single cathode ray tube face, each of said three electron guns connected to a separate control means for modifying the blanking voltage thereof according to the intensity of cathode current thereof.
Description:
The present invention relates to a device for the generation of a blanking voltage for a cathode ray tube, and more particularly for generation of such a blanking voltage for a color television or display.
It is well-known that a television receiver comprises a cathode ray tube in which one or more electron guns are disposed. Electrons are beamed from the guns onto a screen composed of phosphors responsive to electron bombardment, and on which visual displays are thus created when the electron beam(s) scan(s) the screen. This scanning is effected along essentially parallel lines on th
e screen. The light intensity at each point scanned on the screen depends on the intensity of the electron beam; more precisely, if the intensity of the electron beam is equal to zero the display is black; when this intensity exceeds a certain level the display is white (in the case of black-and-white television). The intensity of the electron beam generated by the gun of a television tube depends on the potential or voltage of the gun's various electrodes. In order to vary the intensity of the electron beam and, thus, the light intensity at each point scanned, it is generally the potential of only one electrode that is made to vary in the gun, most frequently that of the cathode, the potential of the other electrodes then remaining constant. The potential applied to this electrode presents a steady-value component on which is superimposed a component whose amplitude varies as a function of the intensity of the image to be reproduced. The variable potential is called the video voltage signal. The constant-value component is called the "blanking voltage" in the present description and makes it possible to produce a black display bordering on gray when the video signal is equal to zero. It should be stressed at this point that this constant-value component is a continuous component which must not be confused with the mean value of the video signal which is also frequently called "continuous component."
The blanking voltage must be equal to the extinction voltage of the tube and has a well-defined value: the precise value needed for a blank display. If the blanking voltage is not at that precise level, the display will be too light or too dark. For example, if the video signal is applied to the cathode and if the blanking voltage has a high positive value, the display will be permanently blank.
It is well-known that the value of the extinction voltage can be altered by several causes, in particular the aging of the television tube. In addition, the devices used for the generation of the blanking voltage can be subject to drift. If the blanking voltage is not modified in accordance with the changes in the extinction voltage and in accordance with said drift, the display will be affected, the latter then being, as stated above, either too bright or too dark; and in the case of color television it is the color that would be affected. That is why television receivers are generally equipped with devices that make it possible to vary the blanking voltage.
In black-and-white television receivers, this correction is the one called "brightness control" and it is performed manually, for example by turning the control knob of a potentiometer.
Color television receivers comprise three electron guns and in their case three blanking voltages must be generated. However, these blanking voltages can all vary by the same amount; this is a "common mode" variation and the correction for this variation can be performed manually by means of a "brightness control" knob, just as in the black-and-white television receivers. These variations may also be of a differential type, however. I.e., the variations may not be of identical value for the three guns. Such differential variation, in actual practice, cannot be corrected manually.
A device for generating the blanking voltage for a color television tube is known which makes it possible to obtain the correct value of this blanking voltage for each of the electron guns at any given moment. In this apparatus devices are provided to measure the intensity of the cathode current (i.e., the intensity of the electron beam) during line scanning, in the course of which a zero-value is imposed on the video signal. The result of this measurement is used in order to impose on the blanking voltage, applied to so-called "G 1 " grids in the tube, the threshold value for which the intensity of the cathode current is equal to zero when there is zero video signal. Now, in most television receivers, particularly those for color reception, the video signal is applied to the cathodes of the three electron guns. The use of such a device thus requires significant modifications in the television receivers; in particular, it is necessary to provide a feed of non-customary polarity, and all the cathodes of the electron guns in a receiver equipped with this device are raised to the same potential; consequently, the guns have a feeble slope.
Another familiar solution for imposin
g the correct value to the blanking voltage consists in stabilizing the potentials applied to all the electrodes of the electron gun(s). It has been demonstrated, however, that this solution is not satisfactory after prolonged use of the tube. Still another well-known system is known for automatic compensation of the cut-off current, applicable especially to cathode tubes where the video modulation is applied to the cathodes.
The operation of this device is summarized as follows: at each raster flyback the cut-off correction is always composed of a preparation phase and a measurement and adjustment phase. The preparation phase permits isolation of the modulation, or its "disconnection". This phase is required in such a system in order to suppress the modulation component and to allow the circuits to stabilize in this state. Consequently, at the end of this preparation phase, only the cut-off voltage source is connected to the cathode. An integrated circuit makes it possible to "memorize" the value of this cut-off voltage source at the end of the preparation phase, until the next measurement is made. Then, during the measurement and adjustment phase, this memorized voltage is used to modify accordingly the bias in the video amplifier, in order always to return to the cut-off point during the next normal scanning interval when the video modulation is again connected to the cathode. Thus, the basic concept developed in this prior art consists in defining a testing procedure which entails a particular treatment of the signals transmitted to the cathodes during the raster flyback. In consequence, the drawback is that two pulses must be generated during the raster flyback interval, a preparation pulse whose function is to "disconnect" the video, and a pulse initiating the actual testing.
Accordingly, the object of the present invention is to obviate the drawbacks listed above, and especially to provide a device for the generation of blanking voltage for television receivers, particularly those for color reception, which is capable of generating such a blanking voltage automatically without need for manual adjustment, and which is readily adaptable, at little cost, to most of the television receivers now being produced.
The present invention comprises devices that are sensitive to the intensity of the cathode current during sampling periods when the video signal is equal to zero. Regulating devices are used to modify the blanking voltage as a function of this intensity, so as to cancel out the latter when there is zero video signal. Accordingly, the invention is characterized by a video voltage and blanking voltage signals applied to the cathode of the electron gun(s) in the tube by means of a video voltage amplifier, and comprises a feedback loop inserted between the connection joining the output of said video voltage amplifier to the corresponding cathode and a control input in said video voltage amplifier, for the control of the blanking voltage. The feedback loop comprises a current amplifier designed to increase the cathode current and having a high output impedance in relation to the output impedance of the video voltage amplifier, the input circuit of said current amplifier being joined with said connection. Memory storage devices are provided whose input is connected to the output of said current amplifier and whose output is connected to said control input.
The video amplifier is so designed that there appears at its output, so as to be superimposed on the amplified video signal, a continuous voltage (superimposed on the increased video signal) of definite value. If the signal applied to the control input corresponds to an intensity of the cathode current that is not equal to zero, the corresponding continuous voltage at the output of the video amplifier increases in value; and since an increase in the voltage applied to the cathode causes a drop
in the intensity of the cathode current, the object of the desired control is achieved. The preferred embodiment of the invention comprises a cathode current amplifier featuring a high output impedance in relation to the output impedance of the video amplifier. The output of the current amplifier is connected to the input of the memory storage devices. The group is wired in such a manner that the cathode current entering into the current amplifier is led to ground by means of the input stage of the current amplifier and of the low-impedance output of the video amplifier. Moreover, the amplified current output at the high-impedance terminal of the current amplifier returns to the amplifier by passing through the low-impedance output of the video amplifier.
As described in the specification, with such wiring, which is particularly simple, the variations in the video voltage signal proper (i.e., not comprising the continuous blanking voltage component) and those in the intensity of the cathode current during the sampling periods, have no effect on one another.
Preferably, in this latter embodiment, in order to store in memory only the cathode current during the sampling periods, interrupton devices are provided to short-circuit the input of the current amplifier outside these sampling periods. If these sampling periods are the scanning flyback intervals, in order to control the operation of these interruptor devices, voltage pulses are preferably used that are generated during the normal scanning. In order for these pulses not to affect the video voltage signal, they are converted into current pulses by means of a converter featuring an output impedance that is high in relation to the output impedance of the video amplifier. The control current pulses are led back to the ground means of the low impedance output of the video amplifier.
In the case of a television receiver (or more generally of a display device) for color transmission that comprises three electron tubes, a device in accordance with the invention is provided, regardless of its particular embodiment, for each electron gun.
In one embodiment, the interruptor devices can be wired so as to short-circuit the input memory storage devices outside the sampling period.
Since these interruptor devices are thus insulated from the cathode, the voltage pulses used for their control are in no danger of affecting the video signal; the control circuit for these interruptor devices can therefore be particularly simple.
CHASSIS 681G Automatic bias control system with compensated sense point:In an automatic kinescope bias (AKB) control system for a television receiver, a voltage representative of kinescope
bias is derived from a sensing point coupled to the television signal processing channel and to AKB signal processing circuits. A switching network attenuates large white-going television signal amplitude components at the sensing point during picture information intervals, to preclude sense point voltage levels which could otherwise ultimately disrupt the operation of the AKB signal processing circuits during AKB operating intervals. 1. In a system including a video signal channel for processing video signals including image and blanking intervals, apparatus comprising:
means coupled to a sensing point in said video channel for deriving a signal representative of an operating characteristic of said video channel during image blanking intervals;
signal processing means responsive to said derived representative signal for providing a control signal to said video channel for maintaining a desired condition of said operating characteristic; and
means, coupled to said sensing point and responsive to video signals during image intervals, for attenuating amplitude excursions manifested by video signals at said sensing point during image intervals when said amplitude excursions exceed a given threshold level.2. Apparatus according to claim 1, wherein:
said video signal amplitude excursions exceeding said threshold level are within a range of normally expected video signal amplitude excursions.
3. Apparatus according to claim 1, wherein
said attenuating means comprises switching means for providing selective attenuation of said video signal amplitude excursions at said sensing point during image intervals.
4. In a system including a video signal channel for processing video signals including image and blanking intervals, apparatus comprising:
means coupled to a sensing point in said video channel for deriving a signal representative of an operating characteristic of said video channel during image blanking intervals;
signal processing means responsive to said derived representative signal for providing a control signal to said video channel for maintaining a desired condition of said operating characteristic; and
means for attenuating amplitude excursions manifested by video signals at said sensing point during image intervals when said amplitude excursions exceed a given threshold level; wherein
said signal deriving means comprises an impedance coupled to said video signal channel, said impedance exhibiting a voltage thereacross which is related to amplitude excursions of said video signals during image intervals, and which is related to said operating characteristic of said video channel during said image blanking intervals; and
said attenuating means limits the voltage developed across said impedance in response to said video signal amplitude excursions exceeding said threshold level during said image intervals.
5. Apparatus according to claim 4, wherein
said attenuating means comprises switching means coupled to said impedance.
6. Apparatus according to claim 5, wherein
said switching means is coupled across said impedance.
7. Apparatus according to claim 6, wherein
said switching means comprises a normally non-conductive diode subject to being rendered conductive in response to said video signal amplitude excursions during image intervals.
8. In a video signal processing system including an image display device; and a video signal channel, including a video signal amplifier, for providing video signals including image and blanking intervals to said image display device; apparatus comprising:
means coupled to a sensing point in said video channel for deriving a signal representative of the magnitude of black image current conducted by said image display device during image blanking intervals;
signal pr
ocessing means responsive to said derived representative signal for providing a bias control signal to said image display device for maintaining a desired level of black current; and means, coupled to said sensing point and responsive to video signals during image intervals, for attenuating amplitude excursions manifested by video signals at said sensing point during image intervals when said amplitude excursions exceed a given threshold level.
9. Apparatus according to claim 8, wherein:
said video signal amplitude excursions exceeding said threshold level are within a range of normally expected video signal amplitude excursions; and
said attenuating means does not disrupt the display of video information by said display device in response to video signals provided via said video channel.
10. In a video signal processing system including an image display device; and a video signal channel, including a video signal amplifier, for providing video signals including image and blanking intervals to said image display device; apparatus comprising:
means coupled to a sensing point in said vide channel for deriving a signal representative of the magnitude of black image curretn conducted by said image display device during image blanking intervals;
signal processing means responsive to said derived representative signal for providing a bias control signal to said image display device for maintaining a desired level of black current; and
means for attenuating amplitude excursions manifested by video signal at said sensing point during image intervals when said amplitude excursions exceed a given threshold level; wherein
said attenuating means comprises switching means for providing selective attenuation of said video signal amplitude excursions at said sensing point during image intervals.
11. In a video signal processing system including an image display device; and a video signal channel, including a video signal amplifier, for providing video signals including image and blanking intervals to said image display device; apparatus comprising:
means coupled to a sensing point in said video channel for deriving a signal representative of the magnitude of black image current conducted by said image display device during image blanking intervals;
signal processing means responsive to said derived representative signal for providing a bias control signal to said image display device for maintaining a desired level of black current; and
means for attenuating amplitude excursions manifested by video signals at said sensing point during image intervals when said amplitude excursions exceed a given threshold level; wherein
said signal deriving means comprises an impedance coupled to said video signal channel, said impedance exhibiting a voltage thereacross which is related to amplitude excursions of said video signals during image intervals, and which is representative of the magnitude of said black current during said image blanking intervals; and
said attenuating means limits the voltage developed across said impedance in response to said video signal amplitude excursions exceeding said threshold level during said image intervals.
12. Apparatus according to claim 11, wherein
said attenuating means comprises switching means coupled to said impedance.
13. Apparatus according to claim 12, wherein
said switching means is coupled across said impedance.
14. Apparatus according to claim 13, wherein
said switching means comprises a normally non-conductive diode subject to being rendered conductive in response to said video signal amplitude excursions during image intervals.
15. Apparatus according to claims 11, 12, 13 or 14, wherein
said impedance is included in a signal conduction path of said video amplifier.
16. Apparatus according to claim 15, wherein
said video amplifier corresponds to a driver amplifier for supplying video output signals to said image display device.
17. In a video signal processing system including an image display device; and a video signal channel, including a video signal amplifier, for providing video signals including image and blanking intervals to said image display device; apparatus comprising:
means coupled to a sensing point in said video channel for deriving a signal representative of the magnitude of black image current conducted by said image display device during image blanking intervals;
signal processing means responsive to said derived representative signal for providing a bias control signal to said image display device for maintaining a desired level of black current; and
means for attenuating amplitude excursions manifested by video signals at said sensing point during image intervals when said amplitude excursions exceed a given threshold level; wherein
said video amplifier corresponds to a driver amplifier for supplying video output signals to said image display device, comprising
a first terminal for receiving video signals to be amplified, a second terminal coupled to an intensity control electrode of said image display device for supplying amplified video signals thereto, and a third terminal coupled to a reference potential and with said second terminal defining a main current conduction path of said video amplifier; and
feedback means coupled from said second terminal to said first terminal of said video amplifier;
said signal deriving means comprises a sensing impedance for receiving, via said feedback means, current variations representative of black current variations manifested at said second terminal of said amplifier means so that said impedance develops a voltage thereacross representative of black current variations; and
said attenuating means is coupled to said impedance for limiting video signal amplitude excursions across said impedance during image intervals.
18. Apparatus according to claim 17, wherein
said attenuating means comprises switching means coupled to said impedance for selectively attenuating said video signal amplitude excursions during image intervals.
19. Apparatus according to claim 18, wherein
said switching means is coupled across said impedance.
20. Apparatus according to claim 19, wherein
said switching means comprises a normally non-conductive diode subject to being rendered conductive in response to said video signal amplitude excursions during image intervals.
21. Apparatus according to claims 17, 18, 19 or 20, wherein said video amplifier comprises a cascode amplifier including:
a first transistor with a first electrode for receiving video signals to be amplified, a second electrode, and a third electrode coupled to a reference potential;
a second transistor with a first electrode coupled to a bias voltage, a second electrode coupled to an operating voltage supply via a load impedance and coupled to an intensity control electrode of said image display device for supplying amplified video signals thereto, and a third electrode coupled to said second electrode of said first transistor; and wherein
said feedback means is coupled from said second electrode of said second transistor to said first electrode of said first transistor; and
said sensing impedance is coupled between said second electrode of said first transistor and said third electrode of said second transistor.
22. A video signal processing system including an image display device; a video signal channel including a video signal amplifier for providing amplified video signa
ls having image and blanking intervals to said image display device; and apparatus for automatically controlling the level of black image current conducted by said image display device, said control apparatus being operative during control intervals within image blanking intervals, and comprising: means coupled to a sensing point in said video channel for deriving a signal representative of the magnitude of black image current conducted by said image display device during image blanking intervals;
signal sampling means coupled to said sensing point for receiving said representative signal at a signal input, for providing an output bias control signal to said image display device for maintaining a desired black current level;
a charge storage device coupled to said signal sampling means;
means operative during a reference interval within said control interval for establishing a reference bias voltage on said charge storage device and a corresponding reference bias condition for said signal sampling means; and
means for attenuating amplitude excursions manifested by video signals at said sensing point during image intervals when said amplitude excursions exceed a given threshold level.
23. Apparatus according to claim 22, wherein
said charge storage device comprises a capacitor for coupling said representative signal from said sensing point to said signal input of said signal sampling means, said capacitor having a first terminal coupled to said sensing point, and a second terminal coupled to said signal input of said sampling means;
said reference voltage is established at said second terminal of said capacitor; and
said signal input of said sampling means corresponds to an input of an integrated circuit device incorporating said sampling means.
24. Apparatus according to claim 23, wherein
said signal deriving means comprises an impedance coupled to said video signal channel, said impedance exhibiting a voltage thereacross which varies with amplitude excursions of said video signals during image intervals, and said impedance exhibiting a voltage thereacross which is representative of the magnitude of said black current during image blanking intervals; and
said attenuating means comprises switching means coupled to said impedance for selectively limiting the voltage developed across said impedance in response to video signal amplitude excursions exceeding said threshold level during said image intervals.
25. Apparatus according to claim 24, wherein
said switching means is coup
led across said impedance.26. Apparatus according to claim 25, wherein
said switching means comprises a normally non-conductive diode subject to being rendered conductive in response to said video signal amplitude excursions during image intervals.
27. Apparatus according to claim 24, 25 or 26, wherein
said impedance is included in a signal conduction path of said video amplifier.
28. In a video signal processing system including an image display device responsive to video signals applied thereto, a driver amplifier for said display device comprising:
a first terminal for receiving video signals to be amplified, a second terminal coupled to an an operating potential via an output load impedance and to an intensity control electrode of said image display device for supplying amplified video signals thereto, and a third terminal coupled to an operating potential and with said second terminal defining a main video signal current conduction path of said video amplifier;
a sensing impedance coupled to said main current conduction path remote from said output impedance;
means for conveying to said sensing impedance a signal representative of the bias condition of said image display device during image blanking intervals, for developing at a sensing point coupled to said sensing impedance a voltage related to said bias condition; and
means, coupled to said sensing point and responsive to video signals during image intervals, for attenuating amplitude excursions manifested by video signals at said sensing point during image intervals when said amplitude excursions exceed a given threshold level.
29. An amplifier according to claim 28, wherein
said sensing impedance is coupled in series with said main current conduction path; and
said conveying means comprises feedback means coupled from said second terminal to said first terminal.
30. In a video signal processing system including an image display device responsive to video signals applied thereto, a driver amplifier for said display device comprising:
a first terminal for receiving video signals to be amplified, a second terminal coupled to an operating potential via an output load impedance and to an intensity control electrode of said image display for supplying amplified video signals thereto, and a third terminal coupled to an operating potential and with said second terminal defining a main video signal current conduction path of said video amplifier;
a sensing impedance coupled to said main current conduction path remote from said output impedance;
means for conveying to said sensing impedance a signal representative of the bias condition of the said image display device during image blanking intervals for developing at a sensing point coupled to said sensing impedance a voltage related to said bias condition; and
means for attenuating
amplitude excursions manifested by video signals at said sensing point during image intervals when said amplitude excursions exceed a given threshold level; wherein said sensing impedance is coupled in series with said main current conduction path;
said conveying means comprises feedback means coupled from said second terminal to said first terminal; and
said attenuating means comprises switching means coupled to said impedance means, said switching means being rendered conductive for attenuating said video signal amplitude excursions at said sensing point during image intervals.
31. An amplifier according to claim 30, wherein
said switching means comprises a diode.
32. In a video signal processing system including an image display device responsive to video signals applied thereto, a driver amplifier for said display device comprising;
A first terminal for receiving video signals to be amplified, a second terminal coupled to an operating potential via an output load impedance and to an intensity control electrode of said image display device for supplying amplified video signals thereto, and a third terminal coupled to an operating potential and with said second terminal defining a main video signal current conduction path of said video amplifier;
a sensing impedance coupled to said main current conduction path remote from said output impedance;
means for conveying to said sensing impedance a signal representative of the bias condition of said image display device during image blanking intervals, for developing at a sensing point coupled to said sensing impedance a voltage related to said bias condition; and
means for attenuating amplitude excursions manifested by video signals at said sensing point during image intervals when said amplitude excursions exceed a given threshold level; wherein
said video signal amplitude excursions exceeding said threshold level are within a range of normally expected video signal amplitude excursions; and
said attenuating means does not disrupt the display of video information by said display device in response to video signal provided via said driver amplifier.
Description:
This invention concerns a system for sensing and automatically controlling a characteristic of a signal processing network. In particular, this invention concerns a system for sensing and automatically controlling the black image current conducted by a video signal image reproducing device, wherein compensation is provided for potentially distruptive video signal components appearing at the sensing point during intervals when the control system is inactive.
Color television receivers sometimes employ an automatic kinescope bias (AKB) control system for automatically establishing proper black image representative current levels for each electron gun of a color kin
escope associated with the receiver. As a result of this operation, pictures reproduced by the kinescope are prevented from being adversely affected by variations of kinescope operating parameters (e.g., due to aging and temperature effects).
An AKB system typically operates during image blanking intervals, at which time each electron gun of the kinescope conducts a small black image representative blanking current in response to a reference voltage representative of black video signal information. This current is processed by the AKB system to generate a signal which is representative of the currents conducted during the blanking intervals, and which is used to maintain a desired black current level.
In one type of AKB system control circuits respond to a periodically derived pulse signal with a magnitude representative of the cathode black current level. The derived signal is processed by control circuits including clamping and sampling networks for developing a kinescope bias correction signal which increases or decreases in magnitude and is coupled to the kinescope for maintaining a correct black current level. The clamping network includes a clamping capacitor for establishing a reference condition for the signal information to be sampled. The reference condition is established by applying a reference voltage to the clamping capacitor which is coupled to the sampling network during the clamping interval. An AKB system of this type is described in U.S. Pat. No. 4,331,981 of R. P. Parker, for example.
In the automatic control system disclosed herein, a bias representative signal is derived at a sensing point during video signal blanking intervals. The sensing point exhibits voltage variations related to amplitude variations of the video signal during video signal image intervals when signal processing circuits of the control system are inactive.
It is herein recognized that the presence of large amplitude video signals at the sensing point can have a disruptive effect on the operation of the signal processing circuits of the control system, particularly when such circuits are constructed in the form of an integrated circuit. Accordingly, a control system disclosed herein includes means for attenuating large video signal amplitude components which can appear at the control system sensing point during video signal picture intervals when the signal processing circuits of the control system are inactive.
In the drawing:
FIG. 1 shows a portion of a color television receiver with an automatic kinescope bias control system including a sensing circuit according to the principles of the present invention; and
FIG. 2 illustrates signal waveforms associated with the operation of the system in FIG. 1.
In FIG. 1, television signal processing circuits 10 provide separated luminance (Y) and chrominance (C) components of a composite color television signal to a luminance-chrominance signal processing network 12. Processor 12 includes luminance and chrominance gain control circuits, DC level setting circuits (e.g, comprising keyed black level clamping circuits), color demodulators for developing r-y, g-y and b-y color difference signals, and matrix amplifiers for combining the latter signals with processed luminance signals to provide low level color image representative signals r, g and b. These signals are amplified and otherwise processed by circuits within video output signal processing networks 14a, 14b and 14c, respectively, which supply high level amplified color image signals R, G and B to respective cathode intensity control electrodes 16a, 16b and 16c of a color kinescope 15. Network 14a, 14b and 14c also perform functions related to the automatic kinescope bias (AKB) control function, as will be discussed. Kinescope 15 is of the self-converging in-line gun type with a commonly energized control grid 18 associated with each of the electron guns comprising cathode electrodes 16a, 16b and 16c.
Since output signal processors 14a, 14b and 14c are similar in this embodiment, the following discussion of the operation of processor 14a also applies to processors 14b and 14c.
Processor 14a includes a kinescope driver stage comprising an input transistor 20 configured as a common emitter amplifier which receives video signal R from processor 12 via an input resistor 21, and an output high voltage transistor 22 configured as a common base ampifier which together with transistor 20 forms a cascode video driver amplifier. High level video signal R, suitable for driving kinescope cathode 16a, is developed across a load resistor 24 in the collector output circuit of transistor 22. Direct current negative feedback for driver 20, 22 is provided by means of a resistor 25. The signal gain of cascode amplifier 20, 22 is primarily determined by the ratio of the value of feedback resistor 25 to the value of input resistor 21.
A sensing resistor 30 DC coupled in series with and between the collector-emitter paths of transistor 20, 22 serves to develop a voltage, at a relatively low voltage sensing node A, representing the level of kinescope cathode black current conducted during kinescope blanking intervals. A normally non-conductive Zener Diode 40 is coupled across sensing resistor 30. Resistor 30 and Zener Diode 40 operate in conjunction with the AKB system of the receiver, which will now be described.
A timing signal generator 40 containing combinational and sequential logic control circuits as well as level shifting circuits responds to periodic horizontal synchronizing rate signals (H) and to periodic vertical synchronizing rate signals (V), both derived from deflection circuits of the receiver for generating timing signals V B , V S , V C , V P and V G which control the operation of the AKB function during periodic AKB intervals. Each AKB interval begins shortly after the end of the vertical retrace interval within the vertical blanking interval, and encompasses several horizontal line intervals also within the vertical blanking interval and during which video signal image information is absent. These timing signals are illustrated by the waveforms in FIG. 2.
R
eferring to FIG. 2 for the moment, timing signal V B , used as a video blanking signal, comprises a positive pulse generated soon after the vertical retrace interval ends at time T 1 , as indicated by reference to signal waveform V. Blanking signal V B exists for the duration of the AKB interval and is applied to a blanking control input terminal of luminance-chrominance processor 12 for casing the r, g and b outputs of processor 12 to exhibit a black image representative DC reference level at the signal outputs of processor 12. Timing signal V G , used as a positive grid drive pulse, encompasses three horizontal line intervals within the vertical blanking interval. Timing signal V C is used to control the operation of a clamping circuit associated with the signal sampling function of the AKB system. Timing signal V S , used as a sampling control signal, occurs after signal V C and serves to time the operation of a sample and hold circuit which develops a DC bias control signal for controlling the kinescope cathode black current level. Signal V S encompasses a sampling interval the beginning of which is slightly delayed relative to the end of the clamping interval encompassed by signal V C , and the end of which substantially coincides with the end of the AKB interval. A negative-going auxiliary pulse V P coincides with the sampling interval. Signal timing delays T D indicated in FIG. 2 are on the order of 200 nanoseconds.
Referring again to FIG. 1, during the AKB interval positive pulse V G (e.g., on the order of +10 volts) biases grid 18 of the kinescope for causing the electron gun comprising cathode 16a and grid 18 to increase conduction. At times other than the AKB intervals, signal V G provides the normal, less positive, bias for grid 18. In response to positive grid pulse V G , a similarly phased, positive current pulse appears at cathode 16a during the grid pulse interval. The amplitude of the cathode output current pulse so developed is proportional to the level of cathode black current conduction (typically a few microamperes).
The induced positive cathode output pulse appears at the collector of transistor 22, and is coupled to the base input of transistor 20 via feedback resistor 25, causing the current conduction of transistor 20 to increase proportionally while the cathode pulse is present. The increased current conducted by transistor 20 causes a related voltage to be developed across sensing resistor 30. This voltage is in the form of a negative-going voltage change which appears at sensing node A and which is proportional in magnitude to the magnitude of the black current representative cathode output pulse. The magnitude of the voltage perturbation at node A is determined by the product of the value of resistor 30 times the magnitude of the perturbation current flowing through resistor 30. The operation of sensing resistor 30 in combination with kinescope driver 20, 22 is described in detail in copending U.S. patent application Ser. No. 394,422 of R. P. Parker, now U.S. Pat. No. 4,463,385 titled "Kinescope Black Level Current Sensing Apparatus", incorporated herein by reference. The voltage change at node A is coupled via a small resistor 31 to a node B at which a voltage change V 1 , essentially corresponding to the voltage change at node A, is developed. Node B is coupled to a bias control voltage processing network 50.
Network 50 performs signal clamping and sampling functions. The clamping function is performed during a clamping interval within each AKB interval by means of a feedback clamping network comprising an input AC coupling capacitor 51, an amplifier 52, and an electronic switch 56. The sampling function is performed during a sampling interval, following the clamping interval during each AKB interval, by means of a network comprising amplifier 52, an electronic switch 57, and an average responding charge storage capacitor 58.
A kinescope bias correction voltage is developed across capacitor 58 and is coupled via a translating circuit comprising a resistor network 60, 62, 64 to the kinescope driver via a bias control input at the base of transistor 20. The correction voltage developed across capacitor 58 serves to automatically maintain a desired correct level of kinescope black current conduction. The bias correction voltage developed across storage capacitor 58 is a function of both voltage change V 1 developed at node B during the clamping interval, and a voltage change V 2 developed at node B during the subsequent sampling interval, as will be discussed in greater detail subsequently in connection with the waveforms shown in FIG. 2.
During the clamping set-up reference interval, switch 56 is rendered conductive in response to clamping control signal V C . At this time switch 57 is non-conductive so that the charge on storage capacitor 58 remains unaffected during the clampling interval. As a consequence of the feedback action during the clamping interval, the negative terminal (-) of capacitor 51 is reference to (i.e., clamped to) a reference voltage V R which is a function of a fixed reference voltage V REF applied to an input of amplifier 52, for establishing an input reference bias condition at a signal input of amplifier 52 at a node C. At this time the voltage V 3 across input capacitor 51 is a function of the level of voltage change V 1 developed at node B, and the clamping reference voltage V R provided via the feedback action.
During the following sampling interval when
voltage channel V 2 is developed at node B, switch 56 is rendered non-conductive, and switch 57 is rendered conductive in response to sampling control signal V S . The magnitude of voltage change V 2 is indicative of the magnitude of the kinescope black current level, and is sampled by means of amplifier 52 (with respect to reference voltage V R ) to develop a corresponding voltage across storage capacitor 58. Network 50 can include circuits of the types described in U.S. Pat. No. 4,331,981 of R. P. Parker, and in a copending U.S. patent application of P. Filliman Ser. No. 437,827 titled "Signal Sampling Network with Reduced Offset Error". Amplifier 52 is preferably rendered non-conductive during picture intervals when the AKB clamping and sampling functions are not being performed. This can be accomplished by disabling the operating current source of amplifier 52 in response to a keying signal coincident with the picture intervals.
Zener diode 40 serves to attenuate large amplitude video signal components, and particularly video signal peaking components, which otherwise appear with significant magnitude at sensing node A during field scanning picture information intervals. In the absence of the attenuation provided by Zener Diode 40, large amplitude video signal appearing at sensing node A can ultimately disrupt the AKB signal processing function, particularly with respect to the development of clamping reference voltage V R , when the AKB signal processor including amplifier 52 is constructed in the form of an integrated circuit with an input at node C, as follows.
Sensing node A and node B exhibit a nominal DC voltage (V DC ) of approximately +8.8 volts for black video signal conditions during picture intervals, as well as during AKB intervals (except when voltage change V 2 is generated during AKB sampling intervals as will be discussed subsequently). At the end of the AKB clamping reference interval, voltage V 3 across clamp capacitor 51 is equal to V DC -V R , where V DC is the nominal black level voltage (+8.8 volts) and V R is the reference voltage (e.g., +6 volts) developed at the negative terminal of capacitor 51 during the clamping interval.
During the field scanning picture interval which begins at the end of the vertical blanking interval, video signals applied to kinescope driver 20, 22 can cause large voltage transitions to be developed at the collector output of driver transistor 22 and at the kinescope cathode. A large video input signal r (e.g., a 100 IRE peak white signal) can cause the collector output voltage of driver transistor 22 to decrease by about 130 volts. A heavily peaked video signal with accentuated white-going amplitude transitions can increase the effective video signal peak white level by 20%, causing the collector output voltage of driver transistor 22 to decrese by an additional 20%. The effective peak white level of the video signal can be increased by more than 20% in receivers which do not include circuits for automatically limiting the amount of peaking present in the video signal.
A version of such peak white amplitude transitions appears at AKB sense point A, and can cause a significant and potentially troublesome negative-going transient decrease in the voltage at sense point A. This transient voltage decrease can be as great as 7.28 volts (or even greater in receivers without peak limiting circuits) according to the expression ΔV A =R 30 /R 24 (ΔV K )
where
ΔV A corresponds to the transient voltage decrease at sensing point A;
R 30 and R 24 correspond to the values of resistors 30 and 24, respectively; and
ΔV K corresponds to the amount by which the kinescope cathode voltage decreases in response to large white-going video signal amplitude transitions including peaking effects (e.g., 130 volts×1.2).
The voltage at input node C of the AKB signal processor is given by V A -V 3 , where V A is the voltage at sense point A and V 3 is the voltage across capacitor 51. More specifically, the voltage at input node C is given by (V DC -ΔV A )-(V DC -V R )
where
V DC is the nominal black level voltage at sense point A (+8.8 volts);
ΔV A is the transient voltage at sense point A; and
V R is the clamping reference voltage developed on and stored at the negative terminal of capacitor 51 (+6.0 volts).
Thus in this instance l
arge white-going video signal amplitude transitions can cause a negative voltage of -1.28 volts to appear at input node C of the AKB signal processor.
This negative voltage at node C is large enough to forward bias the integrated circuit substrate-to-ground semiconductor junction at the input of the AKB signal processor. A diode D S represents the substrate-to-ground semiconductor junction, and is forward biased into conduction since the -1.28 volt negative voltage transient at node C exceeds the threshold conduction level (0.7 volts) of substrate diode D S . If this were to occur, the voltage at node C would be clamped to -0.7 volts and the negative terminal of clamp capacitor 51 would rapidly discharge to a distorted reference level which might impair the subsequent AKB clamping and sampling functions. This condition could be difficult to recover from during succeeding AKB operating intervals, and the distorted reference level could persist for a relatively long time, depending on the nature of the video signal picture information, its peaking content and duration. As a consequence, proper AKB operation could be distrupted such that an abnormally high kinescope black current level would result with an associated unwanted visible increase in picture brightness.
Zener diode 40 prevents the described objectionable effects caused by large amplitude video signals during the picture interval. Specifically, the action of diode 40 prevents clamping reference voltage V R from being disturbed from one AKB interval to another, by preventing picture interval video signal amplitude excursions of significant magnitude from being developed at AKB sensing point A, as follows.
The emitter voltage of driver transistor 22 is substantially constant (+10.5 volts), and is equal to the fixed base bias voltage of transistor 22 (+11.2 volts) minus the base-emitter junction voltage drop of transistor 22 (+0.7 volts). During AKB intervals, the collector voltage of transistor 20 and thereby the voltage at sense point A vary in response to the perturbation current conducted to the base of video signal amplifier transistor 20 via feedback resistor 25, as a function of the induced kinescope output current pulse developed as discussed previously. The voltage across sense resistor 30 changes with variations in the current conduction of transistor 20 during both AKB intervals and video information picture intervals.
Zener diode 40 is normally non-conductive, but conducts whenever the conduction of transistor 20 causes the voltage across sense resistor 30 to exceed the Zener threshold conduction voltage of diode 40. When Zener diode 40 conducts, the collector current of transistor 20 flows through Zener diode 40 rather than through sense resistor 30. At this time the voltage across resistor 30 is clamped to the fixed voltage developed across Conductive Zener diode 40, whereby the voltage across resistor 30 and the voltage at sense point A do not change. Accordingly, the amount by which the voltage at sense point A can decrease in response to a large amplitude white-going video signal is limited as a function of the voltage developed across diode 40 when conducting.
The lowest voltage capable of being developed at sense point A is equal to the substantially fixed emitter voltage of transistor 22 (+10.5 volts), minus the substantially fixed Zener voltage drop across diode 40. When diode 40 exhibits a +6.2 volt Zener voltage, the maximum voltage decrease at point A (i.e., the most negative-going transient voltage ΔV A ) is limited to +4.3 volts. In such case the voltage at input node C of the AKB signal processor exhibits a corresponding minimum voltage of +1.7 volts, whereby the input substrate to ground semiconductor junction represented by diode D S is prevented from becoming forward biased. Accordingly, reference voltage V R and the AKB signal processing function remain undisturbed in the presence of large peak white video signal amplitude transitions during picture intervals.
The video output signal developed at the output of driver transistor 22 and coupled to the kinescope advantageously is not disturbed when Zener diode 40 conducts during picture intervals. This results because the emitter current of driver transistor 22 does not change when diode 40 conducts. When diode 40 conducts, the signal current which would otherwise flow through resistor 30 flows instead through conductive diode 40.
Other embodiments of the disclosed invention can be developed. For example, an electronic switch can be coupled across resistor 30 and keyed such that the switch is conductive during picture intervals and non-conductive during AKB intervals.
Following is a more detail discussion of the clamping and sampling operation of network 50, made with reference to the waveforms of FIG. 2.
Auxiliary signal V p is applied to circuit node B in FIG. 1 via a diode 35 and a voltage translating impedance network comprising resistors 32 and 34. Signal V P exhibits a given positive DC level at all times except during the AKB sampling interval, for maintaining diode 35 conductive so that a DC bias voltage is developed at node B. When the positive DC component of signal V P is present, the junction of resistors 32 and 34 is clamped to a voltage equal to the positive DC component of signal V P , minus the voltage drop across diode 35. Signal V P manifests a negative-going, less positive fixed amplitude pulse component during the AKB sampling interval. Diode 35 is rendered non-conductive in response to negative pulse V P , whereby the junction of resistors 32 and 34 is unclamped. Resistor 31 causes insignificant attenuation of the voltage change (V 1 ) developed at node B since the value of resistor 31 is small relative to the values of resistors 32 and 34.
Prior to the clamping interval but during the AKB interval, the pre-existing nominal DC voltage (V DC ) appearing at node B charges the positive terminal of capacitor 51. During the clamping interval when grid drive pulse V G is developed, the voltage at node A decreases in response to pulse V G by an amount representative of the black current level. This causes the voltage at node B to decrease to a level substantially equal to V DC -V 1 . Also during the clamping interval, timing signal V C renders clamping switch 56 conductive, whereby via feedback action reference voltage V R is developed at the negative terminal of clamp capacitor 51 as discussed. During the clamping interval, voltage V 3 across capacitor 51 is a function of reference set-up voltage V R at the negative terminal of capacitor 51, and a voltage at the positive terminal of capacitor 51 corresponding to the difference between the described pre-existing nominal DC level (V DC ) at node B and voltage change V 1 developed at node B during the clamping interval. Thus voltage V 3 across capacitor 51 during the clamping reference interval is a function of the level of black current representative voltage change V 1 , which may vary. Voltage V 3 can be expressed as (V DC -V 1 )-V R .
During the immediately following sample interval, positive grid drive pulse V G is absent, causing the voltage at node B to increase positively to the pre-existing nominal DC level V DC that appeared prior to the clamping interval. Simultaneously, negative pulse V P appears, reverse biasing diode 35 and perturbing (i.e., momentarily changing) the normal voltage translating and coupling action of resistors 32, 34 such that the voltage at node B is reduced by an amount V 2 as indicated in FIG. 2. At the same time, clamping switch 56 is rendered non-conductive and switch 57 conducts in response to signal V S .
Thus during the sampling interval the voltage applied to the signal input of amplifier 52 is equal to the difference between the voltage at node B and voltage V 3 across input capacitor 51. The input voltage applied to amplifier 52 is a function of the magnitude of voltage change V 1 , which can vary with changes in the kinescope black current level.
The voltage on output storage capacitor 58 remains unchanged during the sampling interval when the magnitude of voltage change V 1 developed during the clamping interval equals the magnitude of voltage change V 2 developed during the sampling interval, indicating a correct kinescope black current level. This results because during the sampling interval, voltage change V 1 at node B increases in a positive direction (from the clamping set-up reference level) when the grid drive pulse is removed, and voltage change V 2 causes a simultaneous negative-going voltage perturbation at node B. When kinescope bias is correct, positive-going voltage change V 1 and negative-going voltage change V 2 exhibit equal magnitudes whereby these voltage changes mutually cancel during the sampling interval, leaving the voltage at node B unchanged.
When the magnitude of voltage change V 1 is less than the magnitude of voltage change V 2 , amplifier 52 proportionally charges storage capacitor 58 via switch 57 in a direction for increasing cathode black current conduction. Conversely, amplifier 52 proportionally discharges storage capacitor 58 via switch 57 for causing decreased cathode black current conduction when the magnitude of voltage change V 1 is greater than the magnitude of voltage change V 2 .
As more specifically shown by the waveforms of FIG. 2, the amplitude "A" of voltage change V 1 is assumed to be approximately three millivolts when the cathode black current level is correct, and varies over a range of a few millivolts (±Î”) as the cathode black current level increases and decreases relative to the correct level as the operating characteristics of the kinescope change. Thus the clamping interval set-up reference voltage across capacitor 51 varies with changes in the magnitude of voltage V 1 as the cathode black current level changes. Voltage change V 2 at node B exhibits an amplitude "A" of approximately three millivolts, which corresponds to amplitude "A" associated with voltage change V 1 , when the black current level is correct.
As indicated by waveform V COR in FIG. 2, corresponding to a condition of correct kinescope bias, the voltage at the signal input of amplifier 52 remains unchanged during the sampling interval when voltages V 1 and V 2 are both of amplitude "A". However, as indicated by waveform V H , the signal input voltage of amplifier 52 increases by an amount Δ when voltage change V 1 exhibits amplitude "A+Δ", corresponding to a high black current level. In this event output storage capacitor 58 is discharged so that the bias control voltage applied to the base of transistor 20 causes the collector voltage of transistor 22 to increase, whereby the cathode black current decreases toward the correct level.
Conversely, and as indicated by waveform V L , the signal input voltage of amplifier 52 decreases by an amount Δ during the sampling interval when voltage change V 1 exhibits amplitude "A-Δ", corresponding to a low black current level. In this case output storage capacitor 58 charges, causing the collector voltage of transistor 22 to decrease whereby the cathode black current increases toward the correct level. In either case, several sampling intervals may be required to achieve the correct black current level.
The described combined-pulse sampling technique employing voltage changes V 1 and V 2 is discussed in greater detail in a copending U.S. patent application Ser. No. 434,314 of R. P. Parker titled "Signal Processing Network For An Automatic Kinescope Bias Control System", incorporated herein by reference. This copending application also discloses additional information concerning the arrangement including auxiliary control signal V P , as well as disclosing a suitable arrangement for timing signal generator 40.
Color television receivers sometimes employ an automatic kinescope bias (AKB) control system for automatically establishing proper black image representative current levels for each electron gun of a color kin
escope associated with the receiver. As a result of this operation, pictures reproduced by the kinescope are prevented from being adversely affected by variations of kinescope operating parameters (e.g., due to aging and temperature effects). An AKB system typically operates during image blanking intervals, at which time each electron gun of the kinescope conducts a small black image representative blanking current in response to a reference voltage representative of black video signal information. This current is processed by the AKB system to generate a signal which is representative of the currents conducted during the blanking intervals, and which is used to maintain a desired black current level.
In one type of AKB system control circuits respond to a periodically derived pulse signal with a magnitude representative of the cathode black current level. The derived signal is processed by control circuits including clamping and sampling networks for developing a kinescope bias correction signal which increases or decreases in magnitude and is coupled to the kinescope for maintaining a correct black current level. The clamping network includes a clamping capacitor for establishing a reference condition for the signal information to be sampled. The reference condition is established by applying a reference voltage to the clamping capacitor which is coupled to the sampling network during the clamping interval. An AKB system of this type is described in U.S. Pat. No. 4,331,981 of R. P. Parker, for example.
In the automatic control system disclosed herein, a bias representative signal is derived at a sensing point during video signal blanking intervals. The sensing point exhibits voltage variations related to amplitude variations of the video signal during video signal image intervals when signal processing circuits of the control system are inactive.
It is herein recognized that the presence of large amplitude video signals at the sensing point can have a disruptive effect on the operation of the signal processing circuits of the control system, particularly when such circuits are constructed in the form of an integrated circuit. Accordingly, a control system disclosed herein includes means for attenuating large video signal amplitude components which can appear at the control system sensing point during video signal picture intervals when the signal processing circuits of the control system are inactive.
In the drawing:
FIG. 1 shows a portion of a color television receiver with an automatic kinescope bias control system including a sensing circuit according to the principles of the present invention; and
FIG. 2 illustrates signal waveforms associated with the operation of the system in FIG. 1.
In FIG. 1, television signal processing circuits 10 provide separated luminance (Y) and chrominance (C) components of a composite color tele
vision signal to a luminance-chrominance signal processing network 12. Processor 12 includes luminance and chrominance gain control circuits, DC level setting circuits (e.g, comprising keyed black level clamping circuits), color demodulators for developing r-y, g-y and b-y color difference signals, and matrix amplifiers for combining the latter signals with processed luminance signals to provide low level color image representative signals r, g and b. These signals are amplified and otherwise processed by circuits within video output signal processing networks 14a, 14b and 14c, respectively, which supply high level amplified color image signals R, G and B to respective cathode intensity control electrodes 16a, 16b and 16c of a color kinescope 15. Network 14a, 14b and 14c also perform functions related to the automatic kinescope bias (AKB) control function, as will be discussed. Kinescope 15 is of the self-converging in-line gun type with a commonly energized control grid 18 associated with each of the electron guns comprising cathode electrodes 16a, 16b and 16c. Since output signal processors 14a, 14b and 14c are similar in this embodiment, the following discussion of the operation of processor 14a also applies to processors 14b and 14c.
Processor 14a includes a kinescope driver stage comprising an input transistor 20 configured as a common emitter amplifier which receives video signal R from processor 12 via an input resistor 21, and an output high voltage transistor 22 configured as a common base ampifier which together with transistor 20 forms a cascode video driver amplifier. High level video signal R, suitable for driving kinescope cathode 16a, is developed across a load resistor 24 in the collector output circuit of transistor 22. Direct current negative feedback for driver 20, 22 is provided by means of a resistor 25. The signal gain of cascode amplifier 20, 22 is primarily determined by the ratio of the value of feedback resistor 25 to the value of input resistor 21.
A sensing resistor 30 DC coupled in series with and between the collector-emitter paths of transistor 20, 22 serves to develop a voltage, at a relatively low voltage sensing node A, representing the level of kinescope cathode black current conducted during kinescope blanking intervals. A normally non-conductive Zener Diode 40 is coupled across sensing resistor 30. Resistor 30 and Zener Diode 40 operate in conjunction with the AKB system of the receiver, which will now be described.
A timing signal generator 40 containing combinational and sequential logic control circuits as well as level shifting circuits responds to periodic horizontal synchronizing rate signals (H) and to periodic vertical synchronizing rate signals (V), both derived from deflection circuits of the receiver for generating timing signals V B , V S , V C , V P and V G which control the operation of the AKB function during periodic AKB intervals. Each AKB interval begins shortly after the end of the vertical retrace interval within the vertical blanking interval, and encompasses several horizontal line intervals also within the vertical blanking interval and during which video signal image information is absent. These timing signals are illustrated by the waveforms in FIG. 2.
R
eferring to FIG. 2 for the moment, timing signal V B , used as a video blanking signal, comprises a positive pulse generated soon after the vertical retrace interval ends at time T 1 , as indicated by reference to signal waveform V. Blanking signal V B exists for the duration of the AKB interval and is applied to a blanking control input terminal of luminance-chrominance processor 12 for casing the r, g and b outputs of processor 12 to exhibit a black image representative DC reference level at the signal outputs of processor 12. Timing signal V G , used as a positive grid drive pulse, encompasses three horizontal line intervals within the vertical blanking interval. Timing signal V C is used to control the operation of a clamping circuit associated with the signal sampling function of the AKB system. Timing signal V S , used as a sampling control signal, occurs after signal V C and serves to time the operation of a sample and hold circuit which develops a DC bias control signal for controlling the kinescope cathode black current level. Signal V S encompasses a sampling interval the beginning of which is slightly delayed relative to the end of the clamping interval encompassed by signal V C , and the end of which substantially coincides with the end of the AKB interval. A negative-going auxiliary pulse V P coincides with the sampling interval. Signal timing delays T D indicated in FIG. 2 are on the order of 200 nanoseconds. Referring again to FIG. 1, during the AKB interval positive pulse V G (e.g., on the order of +10 volts) biases grid 18 of the kinescope for causing the electron gun comprising cathode 16a and grid 18 to increase conduction. At times other than the AKB intervals, signal V G provides the normal, less positive, bias for grid 18. In response to positive grid pulse V G , a similarly phased, positive current pulse appears at cathode 16a during the grid pulse interval. The amplitude of the cathode output current pulse so developed is proportional to the level of cathode black current conduction (typically a few microamperes).
The induced positive cathode output pulse appears at the collector of transistor 22, and is coupled to the base input of transistor 20 via feedback resistor 25, causing the current conduction of transistor 20 to increase pr
oportionally while the cathode pulse is present. The increased current conducted by transistor 20 causes a related voltage to be developed across sensing resistor 30. This voltage is in the form of a negative-going voltage change which appears at sensing node A and which is proportional in magnitude to the magnitude of the black current representative cathode output pulse. The magnitude of the voltage perturbation at node A is determined by the product of the value of resistor 30 times the magnitude of the perturbation current flowing through resistor 30. The operation of sensing resistor 30 in combination with kinescope driver 20, 22 is described in detail in copending U.S. patent application Ser. No. 394,422 of R. P. Parker, now U.S. Pat. No. 4,463,385 titled "Kinescope Black Level Current Sensing Apparatus", incorporated herein by reference. The voltage change at node A is coupled via a small resistor 31 to a node B at which a voltage change V 1 , essentially corresponding to the voltage change at node A, is developed. Node B is coupled to a bias control voltage processing network 50. Network 50 performs signal clamping and sampling functions. The clamping function is performed during a clamping interval within each AKB interval by means of a feedback clamping network comprising an input AC coupling capacitor 51, an amplifier 52, and an electronic switch 56. The sampling function is performed during a sampling interval, following the clamping interval during each AKB interval, by means of a network comprising amplifier 52, an electronic switch 57, and an average responding charge storage capacitor 58.
A kinescope bias correction voltage is developed across capacitor 58 and is coupled via a translating circuit comprising a resistor network 60, 62, 64 to the kinescope driver via a bias control input at the base of transistor 20. The correction voltage developed across capacitor 58 serves to automatically maintain a desired correct level of kinescope black current conduction. The bias correction voltage developed across storage capacitor 58 is a function of both voltage change V 1 developed at node B during the clamping interval, and a voltage change V 2 developed at node B during the subsequent sampling interval, as will be discussed in greater detail subsequently in connection with the waveforms shown in FIG. 2.
During the clamping set-up reference interval, switch 56 is rendered conductive in response to clamping control signal V C . At this time switch 57 is non-conductive so that the charge on storage capacitor 58 remains unaffected during the clampling interval. As a consequence of the feedback action during the clamping interval, the negative terminal (-) of capacitor 51 is reference to (i.e., clamped to) a reference voltage V R which is a function of a fixed reference voltage V REF applied to an input of amplifier 52, for establishing an input reference bias condition at a signal input of amplifier 52 at a node C. At this time the voltage V 3 across input capacitor 51 is a function of the level of voltage change V 1 developed at node B, and the clamping reference voltage V R provided via the feedback action.
During the following sampling interval when
voltage channel V 2 is developed at node B, switch 56 is rendered non-conductive, and switch 57 is rendered conductive in response to sampling control signal V S . The magnitude of voltage change V 2 is indicative of the magnitude of the kinescope black current level, and is sampled by means of amplifier 52 (with respect to reference voltage V R ) to develop a corresponding voltage across storage capacitor 58. Network 50 can include circuits of the types described in U.S. Pat. No. 4,331,981 of R. P. Parker, and in a copending U.S. patent application of P. Filliman Ser. No. 437,827 titled "Signal Sampling Network with Reduced Offset Error". Amplifier 52 is preferably rendered non-conductive during picture intervals when the AKB clamping and sampling functions are not being performed. This can be accomplished by disabling the operating current source of amplifier 52 in response to a keying signal coincident with the picture intervals. Zener diode 40 serves to attenuate large amplitude video signal components, and particularly video signal peaking components, which otherwise appear with significant magnitude at sensing node A during field scanning picture information intervals. In the absence of the attenuation provided by Zener Diode 40, large amplitude video signal appearing at sensing node A can ultimately disrupt the AKB signal processing function, particularly with respect to the development of clamping reference voltage V R , when the AKB signal processor including amplifier 52 is constructed in the form of an integrated circuit with an input at node C, as follows.
Sensing node A and node B exhibit a nominal DC voltage (V DC ) of approximately +8.8 volts for black video signal conditions during picture intervals, as well as during AKB intervals (except when voltage change V 2 is generated during AKB sampling intervals as will be discussed subsequently). At the end of the AKB clamping reference interval, voltage V 3 across clamp capacitor 51 is equal to V DC -V R , where V DC is the nominal black level voltage (+8.8 volts) and V R is the reference voltage (e.g., +6 volts) developed at the negative terminal of capacitor 51 during the clamping interval.
During the field scanning picture interval which begins at the end of the vertical blanking interval, vide
o signals applied to kinescope driver 20, 22 can cause large voltage transitions to be developed at the collector output of driver transistor 22 and at the kinescope cathode. A large video input signal r (e.g., a 100 IRE peak white signal) can cause the collector output voltage of driver transistor 22 to decrease by about 130 volts. A heavily peaked video signal with accentuated white-going amplitude transitions can increase the effective video signal peak white level by 20%, causing the collector output voltage of driver transistor 22 to decrese by an additional 20%. The effective peak white level of the video signal can be increased by more than 20% in receivers which do not include circuits for automatically limiting the amount of peaking present in the video signal. A version of such peak white amplitude transitions appears at AKB sense point A, and can cause a significant and potentially troublesome negative-going transient decrease in the voltage at sense point A. This transient voltage decrease can be as great as 7.28 volts (or even greater in receivers without peak limiting circuits) according to the expression ΔV A =R 30 /R 24 (ΔV K )
where
ΔV A corresponds to the transient voltage decrease at sensing point A;
R 30 and R 24 correspond to the values of resistors 30 and 24, respectively; and
ΔV K corresponds to the amount by which the kinescope cathode voltage decreases in response to large white-going video signal amplitude transitions including peaking effects (e.g., 130 volts×1.2).
The voltage at input node C of the AKB signal processor is given by V A -V 3 , where V A is the voltage at sense point A and V 3 is the voltage across capacitor 51. More specifically, the voltage at input node C is given by (V DC -ΔV A )-(V DC -V R )
where
V DC is the nominal black level voltage at sense point A (+8.8 volts);
ΔV A is the transient voltage at sense point A; and
V R is the clamping reference voltage developed on and stored at the negative terminal of capacitor 51 (+6.0 volts).
Thus in this instance l
arge white-going video signal amplitude transitions can cause a negative voltage of -1.28 volts to appear at input node C of the AKB signal processor. This negative voltage at node C is large enough to forward bias the integrated circuit substrate-to-ground semiconductor junction at the input of the AKB signal processor. A diode D S represents the substrate-to-ground semiconductor junction, and is forward biased into conduction since the -1.28 volt negative voltage transient at node C exceeds the threshold conduction level (0.7 volts) of substrate diode D S . If this were to occur, the voltage at node C would be clamped to -0.7 volts and the negative terminal of clamp capacitor 51 would rapidly discharge to a distorted reference level which might impair the subsequent AKB clamping and sampling functions. This condition could be difficult to recover from during succeeding AKB operating intervals, and the distorted reference level could persist for a relatively long time, depending on the nature of the video signal picture information, its peaking content and duration. As a consequence, proper AKB operation could be distrupted such that an abnormally high kinescope black current level would result with an associated unwanted visible increase in picture brightness.
Zener diode 40 prevents the described objectionable effects caused by large amplitude video signals during the picture interval. Specifically, the action of diode 40 prevents clamping reference voltage V R from being disturbed from one AKB interval to another, by preventing picture interval video signal amplitude excursions of significant magnitude from being developed at AKB sensing point A, as follows.
The emitter voltage of driver transistor 22 is substantially constant (+10.5 volts), and is equal to the fixed base bias voltage of transistor 22 (+11.2 volts) minus the base-emitter junction voltage drop of transistor 22 (+0.7 volts). During AKB intervals, the collector voltage of transistor 20 and thereby the voltage at sense point A vary in response to the perturbation current conducted to the base of video signal amplifier transistor 20 via feedback resistor 25, as a function of the induced kinescope output current pulse developed as discussed previously. The voltage across sense resistor 30 changes with variations in the current conduction of transistor 20 during both AKB intervals and video information picture intervals.
Zener diode 40 is normally non-conductive, but conducts whenever the conduction of transistor 20 causes the voltage across sense resistor 30 to exceed the Zener threshold conduction voltage of diode 40. When Zener diode 40 conducts, the collector current of transistor 20 flows through Zener diode 40 rather than through sense resistor 30. At this time the voltage across resistor 30 is clamped to the fixed voltage developed across C
onductive Zener diode 40, whereby the voltage across resistor 30 and the voltage at sense point A do not change. Accordingly, the amount by which the voltage at sense point A can decrease in response to a large amplitude white-going video signal is limited as a function of the voltage developed across diode 40 when conducting. The lowest voltage capable of being developed at sense point A is equal to the substantially fixed emitter voltage of transistor 22 (+10.5 volts), minus the substantially fixed Zener voltage drop across diode 40. When diode 40 exhibits a +6.2 volt Zener voltage, the maximum voltage decrease at point A (i.e., the most negative-going transient voltage ΔV A ) is limited to +4.3 volts. In such case the voltage at input node C of the AKB signal processor exhibits a corresponding minimum voltage of +1.7 volts, whereby the input substrate to ground semiconductor junction represented by diode D S is prevented from becoming forward biased. Accordingly, reference voltage V R and the AKB signal processing function remain undisturbed in the presence of large peak white video signal amplitude transitions during picture intervals.
The video output signal developed at the output of driver transistor 22 and coupled to the kinescope advantageously is not disturbed when Zener diode 40 conducts during picture intervals. This results because the emitter current of driver transistor 22 does not change when diode 40 conducts. When diode 40 conducts, the signal current which would otherwise flow through resistor 30 flows instead through conductive diode 40.
Other embodiments of the disclosed invention can be developed. For example, an electronic switch can be coupled across resistor 30 and keyed such that the switch is conductive during picture intervals and non-conductive during AKB intervals.
Following is a more detail discussion of the clamping and sampling operation of network 50, made with reference to the waveforms of FIG. 2.
Auxiliary signal V p is applied to circuit node B in FIG. 1 via a diode 35 and a voltage translating impedance network comprising resistors 32 and 34. Signal V P exhibits a given positive DC level at all times except during the AKB sampling interval, for maintaining diode 35 conductive so that a DC bias voltage is developed at node B. When the positive DC component of signal V P is present, the junction of resistors 32 and 34 is clamped to a voltage equal to the positive DC component of signal V P , minus the voltage drop across diode 35. Signal V P manifests a negative-going, less positive fi
xed amplitude pulse component during the AKB sampling interval. Diode 35 is rendered non-conductive in response to negative pulse V P , whereby the junction of resistors 32 and 34 is unclamped. Resistor 31 causes insignificant attenuation of the voltage change (V 1 ) developed at node B since the value of resistor 31 is small relative to the values of resistors 32 and 34. Prior to the clamping interval but during the AKB interval, the pre-existing nominal DC voltage (V DC ) appearing at node B charges the positive terminal of capacitor 51. During the clamping interval when grid drive pulse V G is developed, the voltage at node A decreases in response to pulse V G by an amount representative of the black current level. This causes the voltage at node B to decrease to a level substantially equal to V DC -V 1 . Also during the clamping interval, timing signal V C renders clamping switch 56 conductive, whereby via feedback action reference voltage V R is developed at the negative terminal of clamp capacitor 51 as discussed. During the clamping interval, voltage V 3 across capacitor 51 is a function of reference set-up voltage V R at the negative terminal of capacitor 51, and a voltage at the positive terminal of capacitor 51 corresponding to the difference between the described pre-existing nominal DC level (V DC ) at node B and voltage change V 1 developed at node B during the clamping interval. Thus voltage V 3 across capacitor 51 during the clamping reference interval is a function of the level of black current representative voltage change V 1 , which may vary. Voltage V 3 can be expressed as (V DC -V 1 )-V R .
During the immediately following sample interval, positive grid drive pulse V G is absent, causing the voltage at node B to increase positively to the pre-existing nominal DC level V DC that appeared prior to the clamping interval. Simultaneously, negative pulse V P appears, reverse biasing diode 35 and perturbing (i.e., momentarily changing) the normal voltage translating and coupling action of resistors 32, 34 such that the voltage at node B is reduced by an amount V 2 as indicated in FIG. 2. At the same time, clamping switch 56 is rendered non-conductive and switch 57 conducts in response to signal V S .
Thus during the sampling interval the voltage applied to the signal input of amplifier 52 is equal to the difference between the voltage at node B and voltage V 3 across input capacitor 51. The input voltage applied to amplifier
52 is a function of the magnitude of voltage change V 1 , which can vary with changes in the kinescope black current level. The voltage on output storage capacitor 58 remains unchanged during the sampling interval when the magnitude of voltage change V 1 developed during the clamping interval equals the magnitude of voltage change V 2 developed during the sampling interval, indicating a correct kinescope black current level. This results because during the sampling interval, voltage change V 1 at node B increases in a positive direction (from the clamping set-up reference level) when the grid drive pulse is removed, and voltage change V 2 causes a simultaneous negative-going voltage perturbation at node B. When kinescope bias is correct, positive-going voltage change V 1 and negative-going voltage change V 2 exhibit equal magnitudes whereby these voltage changes mutually cancel during the sampling interval, leaving the voltage at node B unchanged.
When the magnitude of voltage change V 1 is less than the magnitude of voltage change V 2 , amplifier 52 proportionally charges storage capacitor 58 via switch 57 in a direction for increasing cathode black current conduction. Conversely, amplifier 52 proportionally discharges storage capacitor 58 via switch 57 for causing decreased cathode black current conduction when the magnitude of voltage change V 1 is greater than the magnitude of voltage change V 2 .
As more specifically shown by the waveforms of FIG. 2, the amplitude "A" of voltage change V 1 is assumed to be approximately three millivolts when the cathode black current level is correct, and varies over a range of a few millivolts (±Î”) as the cathode black current level increases and decreases relative to the correct level as the operating c
haracteristics of the kinescope change. Thus the clamping interval set-up reference voltage across capacitor 51 varies with changes in the magnitude of voltage V 1 as the cathode black current level changes. Voltage change V 2 at node B exhibits an amplitude "A" of approximately three millivolts, which corresponds to amplitude "A" associated with voltage change V 1 , when the black current level is correct. As indicated by waveform V COR in FIG. 2, corresponding to a condition of correct kinescope bias, the voltage at the signal input of amplifier 52 remains unchanged during the sampling interval when voltages V 1 and V 2 are both of amplitude "A". However, as indicated by waveform V H , the signal input voltage of amplifier 52 increases by an amount Δ when voltage change V 1 exhibits amplitude "A+Δ", corresponding to a high black current level. In this event output storage capacitor 58 is discharged so that the bias control voltage applied to the base of transistor 20 causes the collector voltage of transistor 22 to increase, whereby the cathode black current decreases toward the correct level.
Conversely, and as indicated by waveform V L , the signal input voltage of amplifier 52 decreases by an amount Δ during the sampling interval when voltage change V 1 exhibits amplitude "A-Δ", corresponding to a low black current level. In this case output storage capacitor 58 charges, causing the collector voltage of transistor 22 to decrease whereby the cathode black current increases toward the correct level. In either case, several sampling intervals may be required to achieve the correct black current level.
The described combined-pulse sampling technique employing voltage changes V 1 and V 2 is discussed in greater detail in a copending U.S. patent application Ser. No. 434,314 of R. P. Parker titled "Signal Processing Network For An Automatic Kinescope Bias Control System", incorporated herein by reference. This copending application also discloses additional information concerning the arrangement including auxiliary control signal V P , as well as disclosing a suitable arrangement for timing signal generator 40.
METZ 7285 MALLORCA COLOR CHASSIS 681G AMBIENT LIGHT RESPONSIVE CONTROL OF BRIGHTNESS, CONTRAST AND COLOR SATURATION
1. In a color television apparatus, a circuit for varying color display characteristics in accordance with variations in ambient light comprising: 2. In a color picture display system having a display device comprising: 3. The display system of claim 2 with kinescope means having a first set of electrodes and a second set of electrodes, 4. The display system of claim 2 with said light sensing means being responsive to the intensity of the ambient light and said parameter varying in accordance with the intensity of ambient light. 5. The display system of claim 4 with said modifying means increasing the gain of said luminance amplifying means at a greater rate than the gain of said chroma amplifying means as said ambient light intensity is increased. 6. A color television apparatus comprising: 7. In a color television receiver: 8. The receiver of claim 7 with said modifying means comprising a light dependent resistor means, 9. The receiver of claim 8 with second impedance means coupling said light dependent resistor means to said luminance gain means to control the gain of said luminance gain means. 10. The receiver of claim 9 with said second impedance means comprising a parallel combination of capacitance and resistance. 11. The receiver of claim 7 with said modifying means varying the gain of the luminance gain means at a greater rate than the gain of the chroma gain means as ambient light is varied. 12. The receiver of claim 7 with said modifying means being responsive to the intensity of ambient light and said parameter being varied as the intensity of the ambient light is varied. 13. The receiver of claim 7 with said modifying means attenuating the gain of said luminance amplifying means approximately fifty percent more than the gain of said chroma amplifying means, when the attenuation is measured in decibels, as said ambient light intensity is decreased. 14. In a color television receiver:
Description:
BACKGROUND OF THE INVENTION
The
present invention relates generally to a television receiver control
system and more particularly to a control system for maintaining
proper balance between room lighting conditions and the level of
picture tube excitation in a color television receiver. More
especially the present invention functions to increase contrast,
intensity and chroma signal strength when the room lighting level
increases to diminish these parameters when the level of room lighting
decreases.
Conventional television receivers, of course, have manually operable controls by means of which a viewer may set the level of contrast, intensity, and chroma signal strength to what he feels to be an optimum level for given room lighting conditions. Under changed room lighting conditions, the viewer will obtain the optimum viewing situation by changing these manual controls to a new preferred level.
It is also known in the prior art to automate this process for a black and white television receiver, for example, as taught in the U.S. Pat. No. 3,165,582 to Korda, issued Jan. 12, 1965, and the French patent 1,223,058 issued in June of 1960.
It is accordingly an object of the present invention to provide an automatic color saturation control for a color television receiver by providing separate, predetermined gains for the luminance and chroma for a given change in ambient light. In the disclosed preferred embodiment, the luminance signal is attenuated 3.3 dB and the chroma signal is attenuated 2.1 dB for a change in ambient light from 100 footcandles to 0.1 footcandles, measured at the display face.
SUMMARY OF THE INVENTION
The foregoing as well as numerous other objects and advantages of the present invention are achieved by providing a light sensitive element in a television receiver exposed to ambient light in the vicinity of the receiver for separately controlling brightness, contrast and chroma signal strength of the displayed picture in accordance with the level of ambient light. The circuit of a preferred embodiment of the present invention, in response to an increase of ambient light level, functions to increase the gain of the luminance amplifier in a relatively greater ratio than the increase in the gain of the chrominance amplifier whereas when the ambient light level decreases the respective gains of these two amplifiers are decreased, again, with the change in the luminance signal being in a greater proportion than the change in the chroma signal strength signal. By using the teaching of this invention, other gain relationships between the luminance components and chroma signal, for a given change in ambient light, may be automatically attained to achieve a desired result of luminance and color saturation.
BRIEF DESCRIPTION OF THE DRAWINGS
The aforementioned and other objects, features and advantages of the present invention will become more apparent from the following detailed description thereof when considered in conjunction with the drawings wherein:
FIG. 1 is a partial block diagram of a color television receiver employing the present invention;
FIG. 2 is a detailed schematic diagram of those portions of FIG. 1 embodying the present invention;
FIG. 3 illustrates chroma gain control characteristic curves for the circuit of FIG. 2; and
FIG. 4 is a graph showing changes in luminance and chroma signal strength according to changes in ambient light.
DESCRIPTION OF THE PREFERRED EMBODIMENT
Considering first FIG. 1 which
illustrates
generally in block diagram form a color television receiver embodying
the present invention, this receiver is seen to comprise a tuner and
radio frequency amplifier 11 for detecting and amplifying incoming
signals received on the antenna 13 and supplying those signals through
an appropriate heterodyning process to an intermediate frequency
amplifier 15. After detection in the detector 17, the luminance signals
are passed through a delay 19 which compensates for the delays
experienced by the chroma signal strength signals and then to the
luminance amplifier 21, which, of course, corresponds to the video
amplifier of a black and white receiver, to then be supplied to the
cathode ray tube 23. The luminance or video amplifier may also be
provided with gain control circuitry 25. An appropriate band pass
amplifier 27 may be employed to separate out the chroma signal strength
signals which are demodulated by the demodulator 29 in well known
fashion to provide the three color difference signals to grids in the
color cathode ray tube 23. While the present invention will be described
with respect to such color difference signals, it is equally
applicable to direct RGB color separation systems. An ambient light
level detector 31 such as a light dependent resistor of the cadmium
sulphide variety is physically located on the front of the television
receiver in such a position as to be exposed to the light levels in the
vicinity of the receiver so that its resistance varies inversely in
accordance with variations in the ambient light levels around the
receiver. These resistance variations are then employed to control the
gain of the luminance amplifier 21 by way of gain control 25 and to
control the gain of the chroma signal strength amplifier circuitry.
The entire color demodulation process is only generally depicted in the block diagram of FIG. 1 and is illustrated as a closed loop burst gain controlled chroma amplifier system with auxiliary chroma gain control introduced by way of the detector 33 from the ambient light level detector 31. A burst gain controlled chroma amplifier circuit is somewhat analogous to a black and white keyed AGC circuit and functions to set the gain level of the amplifier 27 in accordance with the color sync burst rather than the chroma signal level associated with a particular picture. While the present invention is being described with respect to this preferred type of gain control, it would, of course, be possible, in television circuits employing DC gain controls for chroma and/or contrast, to connect the ambient light tracking means to these direct current control circuits. The gain controlled chroma band pass amplifier, of course, supplies an output to a burst amplifier 35 which in turn drives an automatic phase control system 37 for synchronizing the 3.58 megacycle oscillator 39 the output of which is used in the color demodulation process.
C
onsidering
now FIG. 2 which illustrates schematically in detail those portions
of the receiver of FIG. 1 necessary for a complete understanding of
the present invention, the light dependent resistor 41 is mounted near
the front of the television receiver in such a position as to
adequately receive the ambient lighting conditions in the vicinity of
the receiver. The resistance of this device is inversely proportional
to the intensity of light incident thereon. If the room ambient light
experiences an increase in level, the resistance of light dependent
resistor 41 will decrease which decrease in turn lowers the voltage at
the base of transistor 43 which in turn lowers the voltage at the
emitter due to increased conduction through that transistor. This in
turn increases the gain of the chroma amplifier transistor stage 45.
More precisely the lowering the voltage at the emitter of transistor 43
raises a threshold in the automatic chroma control detector 33 so
that the chroma signal strength signal, and hence the color saturation
level, to the picture tube is increased. In the absence of a chroma
signal with its synchronizing burst, the gain of the chroma amplifier
is set at a maximum by the voltage divider comprising resistors 47 and
49. At this time there is no output from the automatic chroma control
detector to the base of transistor 51 and that transistor is
non-conducting.
When a color signal is received, the detector provides an output signal proportional to the color sync burst level which turns on the transistor 51 to control the gain of the chroma amplifier stage 45 so as to maintain the desired output level. The turn on level of transistor 51 represents a fairly well defined knee in the chroma gain control characteristic curves illustrated in FIG. 3. Operation beyond the knee or threshold of such a curve operates to maintain a nearly constant chroma output level while operation below the knee of the curve and its extension as the almost vertical dotted line represents the open loop characteristic wherein there is no automatic gain control to the chroma amplifier. Since transistor 51 is non-conducting below the knee of this curve, gain control is delayed until the output signal reaches this threshold point. Since variations in the potential at the emitter of transistor 43 cause corresponding variations in the potential at the base of transistor 51, it is clear that a variation in the resistance of the light dependent resistor 41 will, for example, cause the gain control characteristic curve to shift from that depicted by curve A to that depicted by curve B and that for a given burst level input as represented by the vertical dotted line, two different levels of chroma output which, in turn, cause two different levels of color saturation will be achieved by a change in the light intensity incident on the resistor 41.
To better understand the operation of detector 33, assume that the burst voltage induced across the top half of the secondary of transformer 34 is in phase with the 3.58 megacycle reference signal and that the burst voltage induced across the bottom half of the secondary of transformer 34 is 180° out of
phase with this reference signal. Assuming further that the diodes 36
and 38 have equal characteristics, that the resistors 40 and 42 are
equal, that the capacitors 44 and 46 are equal, and that the two
portions of the secondary winding on transformer 34 are equal when no
burst is being received, diodes 36 and 38 will conduct equally but
during opposite portions of a cycle. Diode 36 conducts during negative
excursions of the reference signal whereas diode 38 conducts during
positive portions of that reference wave form. Thus during the
negative portions of the reference wave form diode 36 conducts to
charge capacitor 44 so that its right hand plate is negative and its
left hand plate is positive. During the positive excursions, diode 38
conducts to charge capacitor 46 with its right hand plate positive and
its left hand plate negative. Under this assumed no burst input
condition the net charge on these capacitors yields a voltage on line
48 which is zero. If noise is introduced into the system, it will be
of equal amplitude but opposite phase across the two diodes and both
diodes will be affected to an equal extent resulting in no change in
the voltage on line 48. When during a color telecast a burst signal is
present, we may assume that the burst voltage induced across the two
portions of the secondary of transformer 34 are of equal amplitude to
the 3.58 megacycle reference signal. With this situation the diode 36
will not conduct since the burst voltage is equal in phase and
amplitude to the reference signal and its anode and cathode remain at
the same potential. The diode 38 will, however, conduct readily since
the burst and reference signals have an additive rather than a
cancelling effect on it resulting in the diode 38 conducting twice as
much as in the previous no burst example and resulting in the
capacitor 46 charging to about twice its previous voltage which
voltage is presented on line 48 as a control signal.
Suppose now that the burst signal amplitude is reduced to one half that of the foregoing example. With this new assumption the phase relationships remain as before but now diode 36 will conduct about one half its previous amount while diode 38 conducts about one and one half times its previous amount resulting in a voltage on line 48 which is about one half the previous voltage.
The voltage on line 48 which is approximately proportional to the burst voltage is applied to the base of transistor 51 which biases the base of the chroma amplifier transistor 45 thereby controlling the gain of that chroma amplifier stage.
A variation in threshold can be achieved by altering the conduction points of the diodes 36 and 38. This is accomplished by applying a bias voltage to the junction of these two diodes to alter their respective points of conduction thereby changing the output voltage on line 48. For example, if a positive 2-volt direct current bias is applied to the junction of the
two diodes, under a no burst input condition, diode 38 will conduct
sooner and turn off later than with no bias applied, while diode 36
will turn on later and off sooner than under the no bias condition.
This results in a control voltage on line 48 under the no burst
condition. In other words, a bias voltage applied to the junction of
the two diodes acts as an additional bias on the chroma amplifier
stage thereby affecting its gain.
The control of brightness (intensity) and contrast is achieved in the present invention by a second light dependent resistor 53 which is optically coupled to a light emitting diode 55. LIght emitting diode 55 and light dependent resistor 53 are encapsulated in a light impervious housing illustrated by the dotted line 57. As the room ambient light changes, the change in the resistance of light dependent resistor 41 causes a change in the current through light emitting diode 55. Variations in the current through the light emitting diode cause corresponding variations in the light emitted thereby which in turn cause variations in the resistance of the light dependent resistor 53. The luminance or video amplifier is here illustrated as a three transistor amplifier with the output of the first amplifier stage being across resistor 59. A diminution in the resistance of light dependent resistor 53 causes a lowering of this output impedance and thus a diminution in the gain of the luminance amplifier. In other words, if the light intensity in the room increases, the resistance of resistor 41 will decrease causing a decrease in the current through light emitting diode 55 and, therefore, a decrease in its light output level and this decreased light will cause an increase in the resistance of light dependent resistor 53 thus increasing the effective output load resistor for the transistor 61 thus increasing the gain of the video amplifier as desired.
Variable resistor 63 being effectively in series with the light dependent resistor 41 may be varied to compensate for differences in specific light dependent resistors so as to establish a desired level of picture brightness, contrast and color saturation for a given level of ambient light. Variable resistance 65 which is in parallel with the light dependent resistor 41 may be varied so as to effectively change the range of variation in brightness, contrast and color saturation for a specific range of variations in the ambient light conditions. The entire automatic control circuit of the present invention may be bypassed by closing the defeat switch 67.
Looking now at FIGS. 2 and
4, the relative attenuation of the chroma channel and luminance
channel will become apparent. Looking first at FIG. 4, the abscissa is
the measure of ambient illumination in foot candles on a log scale,
and the ordinate is the measure of attenuation of signal amplitude in
dB. At 100 footcandles there is 0 dB attenuation of luminance and
chroma signals and as the ambient illumination decreases to 0.1 foot
candles, it is seen that the chroma signal line 72 is down 2.1 dB
while the luminance signal line 72 is down 3.3 dB. This ratio has been
found to be a highly satisfactory ratio giving a very pleasing
picture at all ambient light levels between 0.1 footcandles and 100
footcandles of ambient light.
The manner in which this variation in luminance attenuation is achieved may be seen by looking at FIG. 2. As mentioned, the chroma channel signal is varied by the conduction level of transistor 43. As light dependent resistor 41 changes in resistance, the conduction level of transistor 43 will also change with the degree of change being determined by divider resistances 75 and 76. Further the luminance channel gain is determined by resistor 77 since it is this resistor which will control the signal level of light emitting diode 55 which in turn will control the gain to luminance transistor 61. It is these resistors which determine the relative amount of attenuation of gain in the chroma and luminance channels as the ambient light is changed. In this embodiment, resistance 75 is 5.6 k ohms, resistance 76 is 4.3 k ohms, resistance 77 is 3.9 k ohms, resistance 78 is 7.5 k ohms, the voltage applied to the upper terminal of resistance 78 is 35 volts, resistance 63 is 500 ohms, resistance 65 is 25 k ohms, resistance 69 is 4.7 k ohms, capacitance 71 is 47 microfarads, resistance 59 is 1 k ohm, resistance 59a is 6.8 k ohms, resistance 62a is 1 k ohms, resistance 64a is 100 ohms, resistance 64b is 6.8 k ohms. Light dependent resistor 41 is a Clariex CL-11360, photocoupler unit 57 is Magnavox Part Number 701482. Transistors 43, 61, 62, and 64 are 2N3962, 2N4916, MPSA20 and 25C685A, respectively. This invention has been incorporated in a Magnavox Company T979 color television chassis.
The effective load resistance for the transistor 61 under direct current conditions is the parallel combination of the resistor 59 and the series pair of resistors 53 and 69 whereas due to the presence of capacitor 71 this effective load resistance under alternating current conditions is the parallel combination of resistors 59 and 53. Thus the ratio of AC to DC gain for this video amplifier stage may be selected by proper selection of these parameters so as to maintain the black level of the picture essentially constant.
Thus while the present invention has been described with respect to a specific embodiment, numerous modifications will suggest themselves to those of ordinary skill in the art. Since the luminance and chroma gains are individually controlled for a given change in ambient light, the gain ratios between the luminance and chroma channels may be selected as desired to achieve a desired effect for a given change in ambient light. Also, while the present invention has been described in the environment of a television receiver, the invention could equally well be used in television monitors as well as many other types of display devices. Accordingly the scope of the present invention is to be measured only by that of the appended claims.
The
present invention relates generally to a television receiver control
system and more particularly to a control system for maintaining
proper balance between room lighting conditions and the level of
picture tube excitation in a color television receiver. More
especially the present invention functions to increase contrast,
intensity and chroma signal strength when the room lighting level
increases to diminish these parameters when the level of room lighting
decreases.Conventional television receivers, of course, have manually operable controls by means of which a viewer may set the level of contrast, intensity, and chroma signal strength to what he feels to be an optimum level for given room lighting conditions. Under changed room lighting conditions, the viewer will obtain the optimum viewing situation by changing these manual controls to a new preferred level.
It is also known in the prior art to automate this process for a black and white television receiver, for example, as taught in the U.S. Pat. No. 3,165,582 to Korda, issued Jan. 12, 1965, and the French patent 1,223,058 issued in June of 1960.
It is accordingly an object of the present invention to provide an automatic color saturation control for a color television receiver by providing separate, predetermined gains for the luminance and chroma for a given change in ambient light. In the disclosed preferred embodiment, the luminance signal is attenuated 3.3 dB and the chroma signal is attenuated 2.1 dB for a change in ambient light from 100 footcandles to 0.1 footcandles, measured at the display face.
SUMMARY OF THE INVENTION
The foregoing as well as numerous other objects and advantages of the present invention are achieved by providing a light sensitive element in a television receiver exposed to ambient light in the vicinity of the receiver for separately controlling brightness, contrast and chroma signal strength of the displayed picture in accordance with the level of ambient light. The circuit of a preferred embodiment of the present invention, in response to an increase of ambient light level, functions to increase the gain of the luminance amplifier in a relatively greater ratio than the increase in the gain of the chrominance amplifier whereas when the ambient light level decreases the respective gains of these two amplifiers are decreased, again, with the change in the luminance signal being in a greater proportion than the change in the chroma signal strength signal. By using the teaching of this invention, other gain relationships between the luminance components and chroma signal, for a given change in ambient light, may be automatically attained to achieve a desired result of luminance and color saturation.
BRIEF DESCRIPTION OF THE DRAWINGS
The aforementioned and other objects, features and advantages of the present invention will become more apparent from the following detailed description thereof when considered in conjunction with the drawings wherein:
FIG. 1 is a partial block diagram of a color television receiver employing the present invention;
FIG. 2 is a detailed schematic diagram of those portions of FIG. 1 embodying the present invention;
FIG. 3 illustrates chroma gain control characteristic curves for the circuit of FIG. 2; and
FIG. 4 is a graph showing changes in luminance and chroma signal strength according to changes in ambient light.
DESCRIPTION OF THE PREFERRED EMBODIMENT
Considering first FIG. 1 which
illustrates
generally in block diagram form a color television receiver embodying
the present invention, this receiver is seen to comprise a tuner and
radio frequency amplifier 11 for detecting and amplifying incoming
signals received on the antenna 13 and supplying those signals through
an appropriate heterodyning process to an intermediate frequency
amplifier 15. After detection in the detector 17, the luminance signals
are passed through a delay 19 which compensates for the delays
experienced by the chroma signal strength signals and then to the
luminance amplifier 21, which, of course, corresponds to the video
amplifier of a black and white receiver, to then be supplied to the
cathode ray tube 23. The luminance or video amplifier may also be
provided with gain control circuitry 25. An appropriate band pass
amplifier 27 may be employed to separate out the chroma signal strength
signals which are demodulated by the demodulator 29 in well known
fashion to provide the three color difference signals to grids in the
color cathode ray tube 23. While the present invention will be described
with respect to such color difference signals, it is equally
applicable to direct RGB color separation systems. An ambient light
level detector 31 such as a light dependent resistor of the cadmium
sulphide variety is physically located on the front of the television
receiver in such a position as to be exposed to the light levels in the
vicinity of the receiver so that its resistance varies inversely in
accordance with variations in the ambient light levels around the
receiver. These resistance variations are then employed to control the
gain of the luminance amplifier 21 by way of gain control 25 and to
control the gain of the chroma signal strength amplifier circuitry.The entire color demodulation process is only generally depicted in the block diagram of FIG. 1 and is illustrated as a closed loop burst gain controlled chroma amplifier system with auxiliary chroma gain control introduced by way of the detector 33 from the ambient light level detector 31. A burst gain controlled chroma amplifier circuit is somewhat analogous to a black and white keyed AGC circuit and functions to set the gain level of the amplifier 27 in accordance with the color sync burst rather than the chroma signal level associated with a particular picture. While the present invention is being described with respect to this preferred type of gain control, it would, of course, be possible, in television circuits employing DC gain controls for chroma and/or contrast, to connect the ambient light tracking means to these direct current control circuits. The gain controlled chroma band pass amplifier, of course, supplies an output to a burst amplifier 35 which in turn drives an automatic phase control system 37 for synchronizing the 3.58 megacycle oscillator 39 the output of which is used in the color demodulation process.
C
onsidering
now FIG. 2 which illustrates schematically in detail those portions
of the receiver of FIG. 1 necessary for a complete understanding of
the present invention, the light dependent resistor 41 is mounted near
the front of the television receiver in such a position as to
adequately receive the ambient lighting conditions in the vicinity of
the receiver. The resistance of this device is inversely proportional
to the intensity of light incident thereon. If the room ambient light
experiences an increase in level, the resistance of light dependent
resistor 41 will decrease which decrease in turn lowers the voltage at
the base of transistor 43 which in turn lowers the voltage at the
emitter due to increased conduction through that transistor. This in
turn increases the gain of the chroma amplifier transistor stage 45.
More precisely the lowering the voltage at the emitter of transistor 43
raises a threshold in the automatic chroma control detector 33 so
that the chroma signal strength signal, and hence the color saturation
level, to the picture tube is increased. In the absence of a chroma
signal with its synchronizing burst, the gain of the chroma amplifier
is set at a maximum by the voltage divider comprising resistors 47 and
49. At this time there is no output from the automatic chroma control
detector to the base of transistor 51 and that transistor is
non-conducting.When a color signal is received, the detector provides an output signal proportional to the color sync burst level which turns on the transistor 51 to control the gain of the chroma amplifier stage 45 so as to maintain the desired output level. The turn on level of transistor 51 represents a fairly well defined knee in the chroma gain control characteristic curves illustrated in FIG. 3. Operation beyond the knee or threshold of such a curve operates to maintain a nearly constant chroma output level while operation below the knee of the curve and its extension as the almost vertical dotted line represents the open loop characteristic wherein there is no automatic gain control to the chroma amplifier. Since transistor 51 is non-conducting below the knee of this curve, gain control is delayed until the output signal reaches this threshold point. Since variations in the potential at the emitter of transistor 43 cause corresponding variations in the potential at the base of transistor 51, it is clear that a variation in the resistance of the light dependent resistor 41 will, for example, cause the gain control characteristic curve to shift from that depicted by curve A to that depicted by curve B and that for a given burst level input as represented by the vertical dotted line, two different levels of chroma output which, in turn, cause two different levels of color saturation will be achieved by a change in the light intensity incident on the resistor 41.
To better understand the operation of detector 33, assume that the burst voltage induced across the top half of the secondary of transformer 34 is in phase with the 3.58 megacycle reference signal and that the burst voltage induced across the bo
ttom half of the secondary of transformer 34 is 180° out of
phase with this reference signal. Assuming further that the diodes 36
and 38 have equal characteristics, that the resistors 40 and 42 are
equal, that the capacitors 44 and 46 are equal, and that the two
portions of the secondary winding on transformer 34 are equal when no
burst is being received, diodes 36 and 38 will conduct equally but
during opposite portions of a cycle. Diode 36 conducts during negative
excursions of the reference signal whereas diode 38 conducts during
positive portions of that reference wave form. Thus during the
negative portions of the reference wave form diode 36 conducts to
charge capacitor 44 so that its right hand plate is negative and its
left hand plate is positive. During the positive excursions, diode 38
conducts to charge capacitor 46 with its right hand plate positive and
its left hand plate negative. Under this assumed no burst input
condition the net charge on these capacitors yields a voltage on line
48 which is zero. If noise is introduced into the system, it will be
of equal amplitude but opposite phase across the two diodes and both
diodes will be affected to an equal extent resulting in no change in
the voltage on line 48. When during a color telecast a burst signal is
present, we may assume that the burst voltage induced across the two
portions of the secondary of transformer 34 are of equal amplitude to
the 3.58 megacycle reference signal. With this situation the diode 36
will not conduct since the burst voltage is equal in phase and
amplitude to the reference signal and its anode and cathode remain at
the same potential. The diode 38 will, however, conduct readily since
the burst and reference signals have an additive rather than a
cancelling effect on it resulting in the diode 38 conducting twice as
much as in the previous no burst example and resulting in the
capacitor 46 charging to about twice its previous voltage which
voltage is presented on line 48 as a control signal.Suppose now that the burst signal amplitude is reduced to one half that of the foregoing example. With this new assumption the phase relationships remain as before but now diode 36 will conduct about one half its previous amount while diode 38 conducts about one and one half times its previous amount resulting in a voltage on line 48 which is about one half the previous voltage.
The voltage on line 48 which is approximately proportional to the burst voltage is applied to the base of transistor 51 which biases the base of the chroma amplifier transistor 45 thereby controlling the gain of that chroma amplifier stage.
A variation in threshold can be achieved by altering the conduction points of the diodes 36 and 38. This is accomplished by applying a bias voltage to the junction of these two diodes to alter their respective points of conduction thereby changing the output voltage on line 48. For example, if a positive 2-volt direct current bias is applied to the junc
tion of the
two diodes, under a no burst input condition, diode 38 will conduct
sooner and turn off later than with no bias applied, while diode 36
will turn on later and off sooner than under the no bias condition.
This results in a control voltage on line 48 under the no burst
condition. In other words, a bias voltage applied to the junction of
the two diodes acts as an additional bias on the chroma amplifier
stage thereby affecting its gain.The control of brightness (intensity) and contrast is achieved in the present invention by a second light dependent resistor 53 which is optically coupled to a light emitting diode 55. LIght emitting diode 55 and light dependent resistor 53 are encapsulated in a light impervious housing illustrated by the dotted line 57. As the room ambient light changes, the change in the resistance of light dependent resistor 41 causes a change in the current through light emitting diode 55. Variations in the current through the light emitting diode cause corresponding variations in the light emitted thereby which in turn cause variations in the resistance of the light dependent resistor 53. The luminance or video amplifier is here illustrated as a three transistor amplifier with the output of the first amplifier stage being across resistor 59. A diminution in the resistance of light dependent resistor 53 causes a lowering of this output impedance and thus a diminution in the gain of the luminance amplifier. In other words, if the light intensity in the room increases, the resistance of resistor 41 will decrease causing a decrease in the current through light emitting diode 55 and, therefore, a decrease in its light output level and this decreased light will cause an increase in the resistance of light dependent resistor 53 thus increasing the effective output load resistor for the transistor 61 thus increasing the gain of the video amplifier as desired.
Variable resistor 63 being effectively in series with the light dependent resistor 41 may be varied to compensate for differences in specific light dependent resistors so as to establish a desired level of picture brightness, contrast and color saturation for a given level of ambient light. Variable resistance 65 which is in parallel with the light dependent resistor 41 may be varied so as to effectively change the range of variation in brightness, contrast and color saturation for a specific range of variations in the ambient light conditions. The entire automatic control circuit of the present invention may be bypassed by closing the defeat switch 67.
Looking now at FIGS. 2 and
4, the relative attenuation of the chroma channel and luminance
channel will become apparent. Looking first at FIG. 4, the abscissa is
the measure of ambient illumination in foot candles on a log scale,
and the ordinate is the measure of attenuation of signal amplitude in
dB. At 100 footcandles there is 0 dB attenuation of luminance and
chroma signals and as the ambient illumination decreases to 0.1 foot
candles, it is seen that the chroma signal line 72 is down 2.1 dB
while the luminance signal line 72 is down 3.3 dB. This ratio has been
found to be a highly satisfactory ratio giving a very pleasing
picture at all ambient light levels between 0.1 footcandles and 100
footcandles of ambient light.The manner in which this variation in luminance attenuation is achieved may be seen by looking at FIG. 2. As mentioned, the chroma channel signal is varied by the conduction level of transistor 43. As light dependent resistor 41 changes in resistance, the conduction level of transistor 43 will also change with the degree of change being determined by divider resistances 75 and 76. Further the luminance channel gain is determined by resistor 77 since it is this resistor which will control the signal level of light emitting diode 55 which in turn will control the gain to luminance transistor 61. It is these resistors which determine the relative amount of attenuation of gain in the chroma and luminance channels as the ambient light is changed. In this embodiment, resistance 75 is 5.6 k ohms, resistance 76 is 4.3 k ohms, resistance 77 is 3.9 k ohms, resistance 78 is 7.5 k ohms, the voltage applied to the upper terminal of resistance 78 is 35 volts, resistance 63 is 500 ohms, resistance 65 is 25 k ohms, resistance 69 is 4.7 k ohms, capacitance 71 is 47 microfarads, resistance 59 is 1 k ohm, resistance 59a is 6.8 k ohms, resistance 62a is 1 k ohms, resistance 64a is 100 ohms, resistance 64b is 6.8 k ohms. Light dependent resistor 41 is a Clariex CL-11360, photocoupler unit 57 is Magnavox Part Number 701482. Transistors 43, 61, 62, and 64 are 2N3962, 2N4916, MPSA20 and 25C685A, respectively. This invention has been incorporated in a Magnavox Company T979 color television chassis.
The effective load resistance for the transistor 61 under direct current conditions is the parallel combination of the resistor 59 and the series pair of resistors 53 and 69 whereas due to the presence of capacitor 71 this effective load resistance under alternating current conditions is the parallel combination of resistors 59 and 53. Thus the ratio of AC to DC gain for this video amplifier stage may be selected by proper selection of these parameters so as to maintain the black level of the picture essentially constant.
Thus while the present invention has been described with respect to a specific embodiment, numerous modifications will suggest themselves to those of ordinary skill in the art. Since the luminance and chroma gains are individually controlled for a given change in ambient light, the gain ratios between the luminance and chroma channels may be selected as desired to achieve a desired effect for a given change in ambient light. Also, while the present invention has been described in the environment of a television receiver, the invention could equally well be used in television monitors as well as many other types of display devices. Accordingly the scope of the present invention is to be measured only by that of the appended claims.
In a color television receiver, first and second amplifiers are respectively included in the luminance and chrominance channels to permit control of contrast and saturation. The amplifiers have gain versus control voltage characteristics including linear portions extrapolated to cut off at predetermined voltages which may or may not be the same. A first potentiometer is coupled between a source of fixed voltage equal to the extrapolated cut off voltage of the first amplifier and a gain controlling voltage source. The gain controlling voltage may be produced by a circuit including an element responsive to ambient light. The wiper of the first potentiometer is coupled to the first amplifier to couple a voltage developed at a predetermined point of the first potentiometer to the first amplifier to control its gain. A second potentiometer is coupled between a source of voltage equal to the extrapolated cut off voltage of the second amplifier and the gain controlling voltage source to receive a portion of the gain controlling voltage in accordance with the ratio of the extrapolated cut off voltages of the first and second amplifiers. The wiper of the second potentiometer is coupled to the second amplifier to couple a voltage developed at a predetermined point of the second potentiometer to the second amplifier to control its gain. In this manner, the contrast of the receiver may be varied over a relatively wide range while saturation is maintained substantially constant.
1. In a color television signal processing system of the type including luminance and chrominance signal processing channels, apparatus comprising:
first and second amplifiers respectively included in said luminance and chrominance channels, said amplifiers having gain versus control voltage characteristics including linear portions extrapolated to cut-off at predetermined voltages which may or may not be the same voltage;
a gain controlling voltage source;
means for coupling said gain controlling voltage to said first amplifier to control its gain;
potentiometer means coupled between a fixed voltage substantially equal to the extrapolated cut-off voltage of said second amplifier and to said gain controlling voltage source to recieve a portion of said gain controlling voltage in accordance with the ratio of the extrapolated cut-off voltages of said first and second amplifiers; and
means for coupling a voltage developed at a predetermined point on said potentiometer means to said second amplifier to control its gain.
2. The apparatus recited in claim 1 wherein said means for coupling said gain controlling voltage to said first amp
lifier includes another
potentiometer coupled between a source of fixed voltage substantially
equal to the extrapolated cut-off voltage of said first amplifier and
said gain controlling voltage source.
3. In a color television signal processing system of the type
including luminance and chrominance signal processing channels,
apparatus comprising:first and second amplifiers respectively included in said luminance and chrominance channels, said amplifiers having gain control voltage characteristics including linear portions extrapolated to cut-off at substantially the same predetermined voltage;
a source of gain controlling voltage; and
means for coupling said gain controlling voltage to said first and second amplifiers.
4. Apparatus comprising:
first variable gain amplifying means for amplifying a first signal in response to a first DC control signal, said first amplifying means having a first gain versus DC control voltage characteristic including a linear region, said linear region having a gain substantially equal to 0 at a DC control voltage equal to VO ;
second variable gain amplifying means for amplifying a second signal in response to a second DC control signal, said second amplifying means having a second gain versus DC control voltage characteristic including a linear region, said linear region having a gain substantially equal to 0 at a DC control voltage equal to AVO, where A is a number greater than 0;
a first source of fixed voltage substantially equal to VO ;
a second source of fixed voltage substantially equal to AVO ;
means for developing a third DC control voltage v;
means for developing a portion Av of said third control voltage v;
first means for deriving said first control voltage including means for providing the difference between said third control voltage v and said fixed voltage VO and means for adding a predetermined portion of the difference between said third control voltage v and said fixed voltage VO to said DC control voltage v; and
second means for deriving said second control voltage including means for providing the difference between a portion Av of said third control voltage v and said fixed voltage AVO and means for adding a predetermined portion of the difference between said portion Av and said fixed voltage AVO to said DC control voltage v.
5. The apparatus recited in claim 4 wherein A is equal to 1. 6. The apparatus recited in claim 4 wherein said first amplifying means is included in a luminance channel of a televeision signal processing system and said second amplifying means is included in a chrominance channel of said television signal processing system. 7. The apparatus recited in claim 6 wherein means for developing said third control voltage includes means responsive to ambient light. 8. The apparatus recited in claim 4 wherein said first means includes first voltage divider means coupled bet
ween
said fixed voltage VO and said third DC control voltage v;
and wherein said second means includes second voltage divider means
coupled between said fixed voltage AVO and said portion Av.
9. The apparatus recited in claim
8 wherein said first voltage divider means includes a first
potentiometer, said first potentiometer having a wiper coupled to said
first amplifying means; and wherein said second voltage divider means
includes a second potentiometer, said second potentiometer having a
wiper coupled to said amplifying means.
10. The apparatus recited in claim 4 wherein said second gain
versus DC control voltage characteristic includes a region between said
voltage AVO and a voltage VB where the gain is greater than 0, said voltage VB
being substantially equal to the voltage at which said second
amplifying means has a gain substantially equal to 0; and wherein said
second source of fixed voltage includes means for coupling said voltage
VB to said second amplifying means.
11. The apparatus recited in claim 10 wherein said
second source of said voltage AVO includes a third source of fixed voltage VB ; potentiometer means coupled between said third source of fixed voltage VB
and said means for developing said third DC control voltage; and
means coupled to said potentiometer means for developing said voltage
AVO at a point along said potentiometer means; said
potentiometer means including a wiper coupled to said second amplifier
means, said wiper being adjustable to couple a DC voltage VFB and said third control voltage to said second amplifying means.
Description:
The
present invention pertains to gain controlling apparatus and
particularly to apparatus for controlling the gains of amplifiers
included in the luminance and chrominance channels of a television
signal processing system.
Recently, the maximum brightness available from television receivers has increased sufficiently so that a pleasing image may be reproduced under conditions of high ambient
light as well as under conditions of low ambient light. Apparatus is
known for automatically controlling the contrast and brightness
properties of a television receiver in response to ambient light to
provide a pleasing image over a range of ambient light conditions. Such
apparatus is described in U.S. Pat. Nos. 3,027,421, entitled "Circuit
Arrangements For Automatically Adjusting The Brightness And The
Contrast In A Television Receiver," issued to H. Heijligers on Mar.
27, 1962 and 3,025,345, entitled "Circuit Arrangement For Automatic
Readjustment Of The Background Brightness And The Contrast In A
Television Receiver," issued to R. Suhrmann on Mar. 13, 1962.
Apparatus is also known for automatically controlling the contrast and saturation properties of a color television receiver by controlling the gains of luminance and chrominance channel amplifiers, respectively, in response to ambient light. Such apparatus is described in U.S. Pat. Nos. 3,813,686 entitled "Ambient Light Responsive Control Of Brightness, Contrast And Color Saturation," issued to Eugene Peter Mierzwinski, on May 28, 1974 and 3,814,852 entitled "Ambient Light Responsive Control Of Brightness, Contrast and Color Saturation," issued to Eugene P. Mierzwinski on June 4, 1974.
Also of interest is apparatus for manually controlling the gains of luminance and chrominance channel amplifiers. Such apparatus is described in U.S. Pat. Nos. 3,374,310, entitled "Color Television Receiver with Simultaneous Brightness and Color Saturation Controls," issued to G.L. Beers on Mar. 19, 1968; 3,467,770, entitled "Dual Channel Automatic Control Circuit," issued to DuMonte O. Voigt on June 7, 1966; and 3,715,463, entitled "Tracking Control Circuits Using a Common Potentiometer," issued to Lester Tucker Matzek, on Feb. 6, 1973.
When the gain of luminance channel is adjusted to control the contrast of an image, either manually or automatically, in response to ambient light, it is desirable to simultaneously control the gain of the chrominance channel in such a manner that the ratio of the gains of the luminance and chrominance channels is substantially constant over a wide range of contrast control to maintain constant saturation. If the proper ratio between the amplitudes of the chrominance and luminance signals is not maintained incorrect color reproduction may result. For instance, if the amplitude of the luminance signals are increased without correspondingly increasing the amplitude of the chrominance signals, colors may become desaturated, i.e., they will appear washed out or pastel in shade. Furthermore, it may be desirable to provide controls for presetting the gains of the luminance and chrominance channels to compensate for tolerance variations in other portions of the television signal processing apparatus.
In accordance with the present invention, apparatus is provided which may be utilized in a color television receiver to control contrast over a relatively wide range while maintaining constant saturation. The apparatus includes first and second amplifiers having gain versus control voltage characteristics including linear portions extrapolated to cut off at predetermined voltages which may or may not be the same. Means couple a gain controlling voltage source to the first amplifier to control its gain. Potentiometer means are coupled between a source of fixed voltage substantially equal to the extrapolated cut off voltage of the second amplifier and the source of gain controlling voltage to receive a portion of said gain controlling voltage in accordance with the ratio of the extrapolated cut off voltages of the amplifiers. A voltage developed at a predetermined point along the potentiometer means is coupled to the second amplifier to control its gain.
In accordance with another feature of the present invention, the means for coupling said gain controlling voltage to said first amplifier includes another potentiometer coupled between a source of fixed voltage substantially equal to the extrapolated cut off voltage of said first amplifier and said gain controlling voltage source.
In accordance with still another feature of the present invention the gain controlling voltage source includes an element responsive to ambient light .
These and other aspects of the present invention may best be understood by references to the following detailed description and accompanying drawing in which:
FIG. 1 shows the general arrangement, partly in block diagram form and partly in schematic diagram form, of a color television receiver employing an embodiment of the present invention;
FIG. 1A shows, in schematic form, a modification to the embodiment shown in FIG. 1;
FIG. 2 shows graphical representation of gain versus control voltage characteristics of amplifiers utilized in the embodiment shown in FIG. 1;
FIG. 3 shows graphical representations of gain versus control voltage characteristics of amplifiers which may be utilized in the receiver shown in FIG. 1;
FIG. 4 shows, in schematic form, another embodiment of the present invention which may be utilized to control the amplifiers whose gain versus control voltage characteristics are shown in FIG. 3;
FIG. 5 shows, in schematic form, an amplifier which may be utilized in the receiver shown in FIG. 1; and
FIG. 6 shows, in schematic form, another amplifier which may be utilized in the receiver shown in FIG. 1.
Referring now
to
FIG. 1, the general arrangement of a color television receiver
employing the present invention includes a video signal processing unit
112 responsive to radio frequency (RF) television signals for
generating, by means of suitable intermediate frequency (IF) circuits
(not shown) and detection circuits (not shown), a composite video signal
comprising chrominance, luminance, sound and synchronizing signals.
The output of signal processing unit 112 is coupled to chrominance
channel 114, luminance channel 116, a channel 118 for processing the
synchronizing signals and a channel (not shown) for processing sound
signals.
Chrominance
processing channel 114 includes chrominance processing unit 120 which
serves to remove chrominance signals from the composite video signal
and otherwise process chrominance signals. Chrominance signal
processing unit 120 may include, for example, automatic color control
(ACC) circuits for adjusting the amplitude of the chrominance channels
in response to amplitude variations of a reference signals, such as a
color burst signal, included in the commposite video signal.
Chrominance signal processing circuits of the type described in the
U.S. Pat. No. 3,740,462, entitled "Automatic Chroma Gain Control
System," issued to L.A. Harwood, on June 19, 1973 and assigned to the
same assignee as the present invention are suitable for use as
chrominance processing unit 120.
The output of the chrominance signal processing unit 120 is coupled to chrominance amplifier 122 which serves to amplify chrominance signals in response to a DC signal vC generated by gain control network 142. As illustrated, chrominance amplifier 122 provides chrominance signals to a chroma demodulator 124. An amplifier suitable for use as chrominance amplifier 122 will subsequently be described with reference to FIG. 6.
Chroma demodulator 124 derives color difference signals representing, for example, R-Y, B-Y and G-Y information from the chrominance signals. Demodulator circuits of the general type illustrated by the chrominance amplifier CA 3067 integrated circuit manufactured by RCA Corporation are suitable for use as chrominance demodulator 124.
The color difference signals are applied to a video driver 126 where they are combined with the output signals -Y of luminance channel 116 to produce color signals of the appropriate polarity, representing for example, red (R), green (G) and blue (B) information. The color signals are coupled to kinescope 128.
Luminance channel 116 includes a first luminance signal processing unit 129 which relatively attenuates undesirable signals, such as chrominance or sound signals or both, present in luminance channel 116 and otherwise processes the luminance signals. The output of first luminance processing unit 129 is coupled to luminance amplifier 130 which serves to amplify the luminance signals in response to a DC control signal vL generated by gain control unit 142 to thereby determine the contrast of a reproduced image. An amplifier suitable for use as luminance amplifier 130 will subsequently be described with reference to FIG. 5. The output of luminance amplifier 130 is coupled to second luminance signal processing unit 132 which serves to further process luminance signals. A brightness control unit 131 is coupled to luminance signal processing unit 132 to control the DC content of the luminance signals. The output -Y of luminance processing unit 132 is coupled to kinescope driver 126.
Channel 118 includes a sync separator 134 which separates horizontal and vertical synchronizing pulses from the composite video signal. The synchronizing pulses are coupled to horizontal deflection circuit 136 and vertical deflection circuit 138.
Horizontal deflection circuit 136 and vertical deflection circuit 138
are coupled to kinescope 128 and to a high voltage unit 140 to
control the generation and deflection of one or more electron beams
generated by kinescope 128 in the conventional manner. Deflection
circuits 136 and 138 also generate horizontal and vertical blanking
signals which are coupled to luminance signal processing unit 132 to
inhibit its operation during the horizontal and vertical retrace
intervals.
Gain control unit 142 is coupled to luminance amplifier 130 and to chrominance amplifier 122 to control their gains. Gain control unit 142 includes a PNP transistor 152 arranged as an emitter-follower amplifier. The collector of transistor 152 is coupled to ground while its emitter is coupled through a series connection of a potentiometer 156 and fixed resistor 154 to a source of positive supply voltage VO. The wiper of potentiometer 156 is coupled to luminance amplifier 130. The series connection of a potentiometer 158 and a variable resistor 159 is coupled between the source of positive supply voltage VO and the emitter of transistor 152. The wiper of potentiometer 158 is coupled to chrominance amplifier 122.
The base of transistor 152 is coupled to the wiper of a potentiometer 146. One end of potentiometer 146 is coupled to the source of positive supply voltage VO through a fixed resistor 144. The other end of potentionmeter 146 is coupled to ground through a light dependent resistor (LDR) 148. LDR 148 is a resistance element whose impedance varies in inverse relationship with light which impinges on it. LDR 148 may comprise a simple cadmium sulfide type of light dependent element or other suitable light dependent device. LDR 148 is desirably mounted to receive ambient light in the vicinity of the screen of kinescope 128.
A single pole double-throw switch 150 has a pole coupled to the junction of potentiometer 146 and LDR 148. A resistor 151 is coupled between the wiper of potentiometer 146 and the other pole of switch 150. The arm of switch 150 is coupled to ground.
The general arrangement shown in FIG. 1 is suitable for use in a color television receiver of the type shown, for example, in RCA Color Television Service Data 1973 No. C -8 for a CTC-68 type receiver, published by RCA Corporation, Indianapolis, Indiana.
In operation, gain control circuit 142 maintains the ratio of the gain of chrominance amplifier 122 to the gain of amplifier 130 constant in order to maintain constant saturation while providing for contrast adjustment either manually by means of potentiometer 146 or automatically by means of LDR 148. If the gain of luminance were adjusted to control the contrast of an image without a corresponding change in the gain of chrominance amplifier 122, the amplitudes of luminance signals -Y and color difference signals R-Y, B-Y and G-Y
would not, in general, be in the correct ratio when combined by
divider 126 to provide the desired color.
When switch 140 is in the MANUAL position, the gains of chrominance amplifier 122 and luminance amplifier 130 are controlled by adjustment of the position of potentiometer 146. When switch 150 is in the AUTO position the gain of the chrominance amplifier 122 and luminance amplifier is automatically controlled by the response of LDR 148 to ambient light conditions. The voltage developed at the wiper of potentiometer 146 (base of transistor 152) when switch 150 is in the AUTO position is inversely related to the ambient light recieved by LDR 148. It is noted that the values of resistors 114, potentiometer 146, LDR 148 and resistor 151 are desirably selected such that the adjustment of the wiper arm of potentiometer 146 when switch 150 is in the MANUAL position does not substantially affect the voltage developed at the base of transister 152 when switch 150 is placed in the AUTO position.
The control voltage v developed at the wiper arm of potentiometer 146 is coupled through emitter-follower transistor 152 to the common junction of potentiometer 156 and variable resistor 159. A control voltage vL comprising v plus a predetermined portion of the difference VO -v developed across the series connection of fixed resistor 154 and potentiometer 156, depending on the setting of potentiometer 156, is coupled to luminance amplifier 130 to control its gain. Similarly, a control voltage vC comprising v plus a predetermined portion of the difference voltage VO -v developed across the series connection of potentiometer resistor 158 and variable resistor 159, depending on the setting of the wiper of potentiometer 158, is coupled to chrominance amplifier 122 to control its gain.
The gain of luminance amplifier 130 may be pre-set to a desired value by the factory adjustment of potentiometer 156. Similarly, variable resistor 159 is provided to allow factory pre-set of the gain of the chrominance amplifier 122. Potentiometer 158 is provided to allow customer control of saturation.
R
eferring to FIG. 2, the gain versus voltage characteristics of chroma amplifier 122 (gC) and luminance amplifier 130 (gL) are shown. The characteristic gC has a reversed S-shape including a linear portion 214. Extrapolated linear portion 214 of gC intersects the GAIN axis at GC and intersects the CONTROL VOLTAGE axis at VO. Similarly, the characteristics gL has a reverse S-shape characteristic including a linear portion 212. Extrapolated linear portion 214 of gL intersects the GAIN axis at GL and intersects the CONTROL VOLTAGE axis at VO.
From FIG. 2, the expression for linear portion 212 of gL is ##EQU1## The expression for linear portion 214 of gC is ##EQU2## From FIG. 1, the expression for vL is vL = v + (VO -v) K1 [3]
where K1 is determined by the voltage division of fixed resistor 154 and potentiometer 156 at the wiper of potentiometer 156. When the wiper of potentiometer 156 is at the emitter of transistor 152, K1 =0. The expression for vC is vC = v + (VO -v)K2 [4]
where K2 is determined by the voltage division of potentiometer 158 and fixed resistor 159 at the wiper of potentiometer 158. By combining equations [1] and [3], the equation for gL becomes ##EQU3## By combining equations [2] and [4], the equation for gC becomes ##EQU4## The ratio of gL to gC is thus ##EQU5## It is noted that this ratio is independent of DC control voltage v. Thus, although DC control voltage v may be varied either manually or in response to ambient light to control the contrast of an image reproduced by kinescope 128, the saturation remains constant.
With re
ference to FIG. 2, it is noted that although the linear portion 214 of gC has an extrapolated gain equal to 0 at a control voltage equal to VO, the non-linear portion of gC does not attain a gain equal to 0 until a control voltage equal to VB. That is, a control voltage of VO will not cut-off chrominance amplifier 122.
In FIG. 1A there is shown, in schematic form, a modification to the arrangement of gain control network 142 of FIG. 1 with provisions which allow a viewer to cut off chrominance amplifier 122 to produce a more pleasing image under conditions of poor color reception due, for example, to noise or interference. The modifications to gain control unit 142 shown in FIG. 1A include coupling potentiometer resistor 158 between a source of positive supply voltage VB, the value of VB being greater than the value of VO, and coupling a resistor 160 from a tap-off point 162 along potentiometer 158 to ground. The value of potentiometer 158 and resistor 160 and the location of tap 162 are selected so that voltage VO is developed at tap 162.
The arrangement shown in FIG. 1A allows for the adjustment of contrast while constant saturation is maintained and additionally allows a viewer, by adjusting the wiper of potentiometer 158 to voltage VB, to cut off chrominance amplifier 122.
Referring to FIG. 3 there are shown gain versus DC control voltage characteristics of chrominance and luminance amplifiers which do not have the same extrapolated linear cut off control voltage. The gain versus control voltage characteristic gL ' of the luminance amplifier has a reverse S-shape characteristic including a linear portion 312. Extrapolated linear portion 312 of gL ' intersects the GAIN axis at a gain GL ' and intersects the CONTROL VOLTAGE axis at a voltage VO '. The gain versus control voltage characteristic gC ' of the chrominance amplifier has a reverse S-shape characteristic having a linear portion 314. Extrapolated linear portion 314 of gC ' intersects the GAIN axis at a gain GC ' and intersects the CONTROL VOLTAGE axis at a voltage AVO ', where A is a number greater than zero.
From FIG. 3, the expression for linear portion 312 of gL ' is ##EQU6## where vL ' is the DC conrol voltage coupled to the luminance amplifier. The expression for linear portion 314 of gC ' is ##EQU7## where vC ' is the DC control voltage coupled to the chrominance amplifier.
A modified form of the control network 142 of FIG. 1 suitable for controlling the gain of a chrominance and a luminance amplifier having characteristics such as shown in FIG. 3 is shown in FIG. 4. Similar portions of FIGS. 1 and 4 are identified by reference numbers having the same last two significant digits and primed (') designations. The modified portions of FIG. 1 shown in FIG. 4 include the series connection resistors 460 and 462 coupled between the emitter of transistor 452 to ground. The values of resistors 460 and 462 are selected so that a portion Av' of the DC control voltage v' developed at the emitter of transistor 452 is developed at the junction of resistors 460 and 462. Furthermore, the series connection of potentiometer 458 and variable resistor 459 is coupled between the junction of resistor 460 and 462 and a source of positive supply voltage AVO '.
From FIG. 4, the expression for control voltage vL ' developed at the wiper of potentiometer 456 is vL ' = v' + (vO '-v')K1 ' [10]
where K1 ' is determined by the voltage division at the wiper of potentiometer 456. The expression for control voltage vC ' developed at the wiper of potentiometer 458 is VC ' = Av' + (AVO ' - Av')K 2 ' [11]
where K2 ' is determined by the voltage division at the wiper of potentiometer 458. By combining equations [8] and [10], ##EQU8## By combining equations [9] and [11], ##EQU9## The ratio of gL ' to gC ' is given by the expression ##EQU10## It is noted that this ratio is independent of DC control voltage v'. Therefore, gain control network 442 of FIG. 4 also allows for the adjustment of contrast while maintaining constant saturation.
It is noted that if A were made equal to 1, the arrangement gain control unit 442 would be suitable to control the gains of chrominance and luminance amplifiers having the characteristics shown in FIG. 2.
In FIG. 5, there is shown an amplifier suitable for use as luminance amplifier 130 of FIG. 1. The amplifier includes a differential amplifier comprising NPN transistors 532 and 534. The commonly coupled emitters of transistors 532 and 534 are coupled to the collector of an NPN transistor 528. The emitter of transistor 528 is coupled via a resistor 530 to ground. The collector of transistor 532 and the collector of transistor 534, via load resistor 536, is coupled to a bias voltage provided by bias supply 546, illustrated as a series connection of batteries. The bases of transistors 532 and 534 are respectively coupled to a lower bias voltage through resistors 533 and 535 respectively.
An input signal, such as, for example, the output signal provided by first luminance processing circuit 129 of FIG. 1 is coupled to the base of transistor 532 via terminal 542. The output signal of the amplifier is developed at the collector of transistor 534 and coupled to output terminal 544.
A DC control voltage, such as vL provided by gain control unit 142 of FIG. 1, is coupled to the base of an NPN transistor 514, arranged as an emitt
er-follower, via
terminal 512. The collector of transistor 514 is coupled to bias
supply 546. The emitter of transistor 514 is coupled to ground through
the series connection of resistor 516, a diode connected transistor
518 and resistor 520.
The anode of diode 520 is coupled to the base of an NPN transistor 538. The collector of transistor 538 is coupled to the collector of transistor 534 while its emitter is coupled to ground through resistor 540. Transistor 538, resistor 540, diode 518 and resistor 520 are arranged in a current mirror configuration.
The emitter of transistor 514 is coupled to the base of a PNP transistor 522. The emitter of transistor 522 is coupled to bias supply 546 while its collector is coupled to the base of transistor 528 and to ground through the series connection of a diode connected transistor 524 and resistor 526. Transistor 528, resistor 530, diode 524 and resistor 526 are arranged in a current mirror configuration
In operation, the DC control voltage coupled to terminal 512 is coupled in inverted fashion to the anode of diode 524 by transistor 522. As a result, current directly related to the voltage developed at the anode of diode 524 flows through diode 524 and resistor 526. Due to the operation of the current mirror arrangement of diode 524, resistor 526, transistor 528 and resistor 530, a similar current flows through the emitter circuit of transistor 528. The gain of the differential amplifier comprising transistors 532 and 534 is directly related to this current flowing in the emitter circuit of transistor 528, and therefore is inversely related to the DC control voltage at terminal 512. The gain versus DC control voltage characteristics of the differential is similar to gL shown in FIG. 2.
Further, a current is developed through the series connection of resistor 516, diode 518 and resistor 520 in direct relationship to the DC control coupled to terminal 512. A similar current is developed through resistor 540 due to the operation of the current mirror comprising diode 518, resistor 520, transistor 538 and resistor 540. This current is of the opposite sense to that provided by the current mirror arrangement of diode 524, resistor 526, transistor 528 and resistor 530 and is coupled to the collector of transistor 534 so that the DC voltage at output terminal 544 does not substantially vary with the DC control voltage.
In FIG. 6, there
is shown an amplifier suitable for use as chroma amplifier 120 of
FIG. 1. The amplifier shown in FIG. 6 is of the type described in U.S.
patent application Ser. No. 530,405 entitled "Controllable Gain
Signal Amplifier," fled by L.A. Harwood et al. on Dec. 6, 1974.
The amplifier comprises a differential amplifier including NPN transistors 624 and 625 having their bases coupled to terminal 603 via a resistor 626. Chrominance signals, provided by a source of chrominance signals such as chrominance processing unit 120 of FIG. 1, are coupled to terminal 603. The current conduction paths between the collectors and emitters of transistors 624 and 625 are respectively coupled to ground via resistors 628, 629 and 630.
A current splitter circuit comprising an NPN transistor 632 and a diode 634 is coupled to the collector of transistor 624. Diode 634 and the base-emitter junction of transistor 632 are poled in the same direction with respect to the flow of collector current in transistor 624. It desirable that conduction characteristics of transistor 632 and diode 635 be substantially matched. Similarly, the collector of transistor 625 is coupled to a second current splitter comprising a transistor 633 and a diode 635.
An output load circuit comprising series connected resistors 636 and 638 is coupled between the collector of transistor 632 and a source of operating voltage provided by bias supply 610. Amplified chrominance signals are provided at output terminal 640 for coupling, for example, to a chroma demodulator such as chroma demodulator 124 of FIG. 1. Similarly, series connected load resistors 637 and 639 are coupled between the collector of transistor 633 and bias supply 610. An output terminal 641 at the junction of resistors 637 ad 639 provides oppositely phased chrominance signals to those provided at terminal 640. The gain associated with the cascode combination of transistors 624 and 632 is controlled in response to a DC control voltage, such as, for example, vC provided by gain control unit 142 of FIG. 1, coupled to the base of an NPN transistor 646 via terminal 602. Direct control current is supplied from the emitter of transistor 646 to diode 634 and 635 via a series resistor 652. A signal by-pass circuit comprising a series resonant combination 654 of inductance and capacitance is coupled from the anode of diode 634 to ground. Resonant circuit 654 is tuned, for example, to 3.58 MHz to provide a low impedance path to ground for color subcarrier signals.
Bias voltages and currents are supplied to the amplifier arrangement by bias supply 610, illustrated as a series connection of batterys. A voltage B+ is coupled to the collector of transistor 646. A lower bias voltage is coupled to the load circuits of transistors 632 and 633. The bases of transistors 632 and 633 are coupled in common to a still lower bias voltage. The bases of transistors 624 and 625 are coupled to a still lower bias voltage via substantially equal in value resistors 658 and 659. A resistor 694 is coupled from the common junction of resistors 658 and 659 to ground.
I
n operation, a quiescent operating current is provided through resistor 630. In the absence of an input signal at terminal 603, this current will divide substantially equally between the similarly biased transistors 624 and 625. If the DC control voltage at terminal 602 is near ground potential, transistor 646 will be effectively cut off and no current will flow in resistor 652 and diodes 634 and 635. In that case, neglecting the normally small difference betweeen collector and emitter currents of NPN transistors, the collector currents of transistors 624 and 625 will flow, respectively, in transistors 632 and 633. The transistors 632 and 633 are operated in common base mode and form cascode signal amplifiers with respective transistors 624 and 625. With the DC control voltage near ground potential, one-half of the quiescent current from resistor 630 flows in each of the load circuits and maximum gain for chrominance signals supplied from terminal 603 is provided.
Transistor 646 will conduct when the DC control voltage approaches the bias voltage supplied to the bases of transistors 632 and 633 of the current splitters. By selection of the circuit parameters, diodes 634 and 635 may be arranged to operate in a range between cut off to the conduction of all of the quiescent operating current supplied via resistor 630, thereby cutting off transistors 632 and 633 to provide no output signals at terminals 640 and 641.
At a DC control voltage intermediate to that corresponding to cut off of transistors 632 and 633 on the one hand and cut off of diodes 634 and 635 on the other hand, the voltage gain of the illustrated amplifier will vary in a substantially linear manner with the DC control voltage.
It
is noted that although the characteristics shown in FIGS. 2 and 3
were reversed S-shaped characteristics, the characteristics could have
other shapes including linear portions. For example, the
characteristics could be substantially linear. Furthermore, with
reference to FIG. 3, although gC ' was shown as having a
linear portion that had a cut off control voltage lower than the cut
off control voltage of the linear portion of gL ', the cut off control voltage of the linear portion of gC ' could be greater than the cut off voltage for the linear region of gL
'. In addition, the gain control units and associate amplifiers could
be arranged to utilize voltages opposite in polarity to those shown.
These and other modifications are intended to be within the scope of
the invention.
Recently, the maximum brightness available from television receivers has increased sufficiently so that a pleasing image may be repro
duced under conditions of high ambient
light as well as under conditions of low ambient light. Apparatus is
known for automatically controlling the contrast and brightness
properties of a television receiver in response to ambient light to
provide a pleasing image over a range of ambient light conditions. Such
apparatus is described in U.S. Pat. Nos. 3,027,421, entitled "Circuit
Arrangements For Automatically Adjusting The Brightness And The
Contrast In A Television Receiver," issued to H. Heijligers on Mar.
27, 1962 and 3,025,345, entitled "Circuit Arrangement For Automatic
Readjustment Of The Background Brightness And The Contrast In A
Television Receiver," issued to R. Suhrmann on Mar. 13, 1962.Apparatus is also known for automatically controlling the contrast and saturation properties of a color television receiver by controlling the gains of luminance and chrominance channel amplifiers, respectively, in response to ambient light. Such apparatus is described in U.S. Pat. Nos. 3,813,686 entitled "Ambient Light Responsive Control Of Brightness, Contrast And Color Saturation," issued to Eugene Peter Mierzwinski, on May 28, 1974 and 3,814,852 entitled "Ambient Light Responsive Control Of Brightness, Contrast and Color Saturation," issued to Eugene P. Mierzwinski on June 4, 1974.
Also of interest is apparatus for manually controlling the gains of luminance and chrominance channel amplifiers. Such apparatus is described in U.S. Pat. Nos. 3,374,310, entitled "Color Television Receiver with Simultaneous Brightness and Color Saturation Controls," issued to G.L. Beers on Mar. 19, 1968; 3,467,770, entitled "Dual Channel Automatic Control Circuit," issued to DuMonte O. Voigt on June 7, 1966; and 3,715,463, entitled "Tracking Control Circuits Using a Common Potentiometer," issued to Lester Tucker Matzek, on Feb. 6, 1973.
When the gain of luminance channel is adjusted to control the contrast of an image, either manually or automatically, in response to ambient light, it is desirable to simultaneously control the gain of the chrominance channel in such a manner that the ratio of the gains of the luminance and chrominance channels is substantially constant over a wide range of contrast control to maintain constant saturation. If the proper ratio between the amplitudes of the chrominance and luminance signals is not maintained incorrect color reproduction may result. For instance, if the amplitude of the luminance signals are increased without correspondingly increasing the amplitude of the chrominance signals, colors may become desaturated, i.e., they will appear washed out or pastel in shade. Furthermore, it may be desirable to provide controls for presetting the gains of the luminance and chrominance channels to compensate for tolerance variations in other portions of the television signal processing apparatus.
In accordance with the present invention, apparatus is provided which may be utilized in a color television receiver to control contrast over a relatively wide range while maintaining constant saturation. The apparatus includes first and second amplifiers having gain versus control voltage characteristics including linear portions extrapolated to cut off at predetermined voltages which may or may not be the same. Means couple a gain controlling voltage source to the first amplifier to control its gain. Potentiometer means are coupled between a source of fixed voltage substantially equal to the extrapolated cut off voltage of the second amplifier and the source of gain controlling voltage to receive a portion of said gain controlling voltage in accordance with the ratio of the extrapolated cut off voltages of the amplifiers. A voltage developed at a predetermined point along the potentiometer means is coupled to the second amplifier to control its gain.
In accordance with another feature of the present invention, the means for coupling said gain controlling voltage to said first amplifier includes another potentiometer coupled between a source of fixed voltage substantially equal to the extrapolated cut off voltage of said first amplifier and said gain controlling voltage source.
In accordance with still another feature of the present invention the gain controlling voltage source includes an element responsive to ambient light .
These and other aspects of the present invention may best be understood by references to the following detailed description and accompanying drawing in which:
FIG. 1 shows the general arrangement, partly in block diagram form and partly in schematic diagram form, of a color television receiver employing an embodiment of the present invention;
FIG. 1A shows, in schematic form, a modification to the embodiment shown in FIG. 1;
FIG. 2 shows graphical representation of gain versus control voltage characteristics of amplifiers utilized in the embodiment shown in FIG. 1;
FIG. 3 shows graphical representations of gain versus control voltage characteristics of amplifiers which may be utilized in the receiver shown in FIG. 1;
FIG. 4 shows, in schematic form, another embodiment of the present invention which may be utilized to control the amplifiers whose gain versus control voltage characteristics are shown in FIG. 3;
FIG. 5 shows, in schematic form, an amplifier which may be utilized in the receiver shown in FIG. 1; and
FIG. 6 shows, in schematic form, another amplifier which may be utilized in the receiver shown in FIG. 1.
Referring now
to
FIG. 1, the general arrangement of a color television receiver
employing the present invention includes a video signal processing unit
112 responsive to radio frequency (RF) television signals for
generating, by means of suitable intermediate frequency (IF) circuits
(not shown) and detection circuits (not shown), a composite video signal
comprising chrominance, luminance, sound and synchronizing signals.
The output of signal processing unit 112 is coupled to chrominance
channel 114, luminance channel 116, a channel 118 for processing the
synchronizing signals and a channel (not shown) for processing sound
signals.Chrominance
processing channel 114 includes chrominance processing unit 120 which
serves to remove chrominance signals from the composite video signal
and otherwise process chrominance signals. Chrominance signal
processing unit 120 may include, for example, automatic color control
(ACC) circuits for adjusting the amplitude of the chrominance channels
in response to amplitude variations of a reference signals, such as a
color burst signal, included in the commposite video signal.
Chrominance signal processing circuits of the type described in the
U.S. Pat. No. 3,740,462, entitled "Automatic Chroma Gain Control
System," issued to L.A. Harwood, on June 19, 1973 and assigned to the
same assignee as the present invention are suitable for use as
chrominance processing unit 120.The output of the chrominance signal processing unit 120 is coupled to chrominance amplifier 122 which serves to amplify chrominance signals in response to a DC signal vC generated by gain control network 142. As illustrated, chrominance amplifier 122 provides chrominance signals to a chroma demodulator 124. An amplifier suitable for use as chrominance amplifier 122 will subsequently be described with reference to FIG. 6.
Chroma demodulator 124 derives color difference signals representing, for example, R-Y, B-Y and G-Y information from the chrominance signals. Demodulator circuits of the general type illustrated by the chrominance amplifier CA 3067 integrated circuit manufactured by RCA Corporation are suitable for use as chrominance demodulator 124.
The color difference signals are applied to a video driver 126 where they are combined with the output signals -Y of luminance channel 116 to produce color signals of the appropriate polarity, representing for example, red (R), green (G) and blue (B) information. The color signals are coupled to kinescope 128.
Luminance channel 116 includes a first luminance signal processing unit 129 which relatively attenuates undesirable signals, such as chrominance or sound signals or both, present in luminance channel 116 and otherwise processes the luminance signals. The output of first luminance processing unit 129 is coupled to luminance amplifier 130 which serves to amplify the luminance signals in response to a DC control signal vL generated by gain control unit 142 to thereby determine the contrast of a reproduced image. An amplifier suitable for use as luminance amplifier 130 will subsequently be described with reference to FIG. 5. The output of luminance amplifier 130 is coupled to second luminance signal processing unit 132 which serves to further process luminance signals. A brightness control unit 131 is coupled to luminance signal processing unit 132 to control the DC content of the luminance signals. The output -Y of luminance processing unit 132 is coupled to kinescope driver 126.
Channel 118 includes a sync separator 134 which separates horizontal and vertical synchronizing pulses from the composite video signal. The synchronizing pulses are coupled to horizontal deflection circuit 136 and vertical deflection cir
cuit 138.
Horizontal deflection circuit 136 and vertical deflection circuit 138
are coupled to kinescope 128 and to a high voltage unit 140 to
control the generation and deflection of one or more electron beams
generated by kinescope 128 in the conventional manner. Deflection
circuits 136 and 138 also generate horizontal and vertical blanking
signals which are coupled to luminance signal processing unit 132 to
inhibit its operation during the horizontal and vertical retrace
intervals.Gain control unit 142 is coupled to luminance amplifier 130 and to chrominance amplifier 122 to control their gains. Gain control unit 142 includes a PNP transistor 152 arranged as an emitter-follower amplifier. The collector of transistor 152 is coupled to ground while its emitter is coupled through a series connection of a potentiometer 156 and fixed resistor 154 to a source of positive supply voltage VO. The wiper of potentiometer 156 is coupled to luminance amplifier 130. The series connection of a potentiometer 158 and a variable resistor 159 is coupled between the source of positive supply voltage VO and the emitter of transistor 152. The wiper of potentiometer 158 is coupled to chrominance amplifier 122.
The base of transistor 152 is coupled to the wiper of a potentiometer 146. One end of potentiometer 146 is coupled to the source of positive supply voltage VO through a fixed resistor 144. The other end of potentionmeter 146 is coupled to ground through a light dependent resistor (LDR) 148. LDR 148 is a resistance element whose impedance varies in inverse relationship with light which impinges on it. LDR 148 may comprise a simple cadmium sulfide type of light dependent element or other suitable light dependent device. LDR 148 is desirably mounted to receive ambient light in the vicinity of the screen of kinescope 128.
A single pole double-throw switch 150 has a pole coupled to the junction of potentiometer 146 and LDR 148. A resistor 151 is coupled between the wiper of potentiometer 146 and the other pole of switch 150. The arm of switch 150 is coupled to ground.
The general arrangement shown in FIG. 1 is suitable for use in a color television receiver of the type shown, for example, in RCA Color Television Service Data 1973 No. C -8 for a CTC-68 type receiver, published by RCA Corporation, Indianapolis, Indiana.
In operation, gain control circuit 142 maintains the ratio of the gain of chrominance amplifier 122 to the gain of amplifier 130 constant in order to maintain constant saturation while providing for contrast adjustment either manually by means of potentiometer 146 or automatically by means of LDR 148. If the gain of luminance were adjusted to control the contrast of an image without a corresponding change in the gain of chrominance amplifier 122, the amplitudes of luminance signals -Y and color difference signals R-Y, B-Y and G-Y
would not, in general, be in the correct ratio when combined by
divider 126 to provide the desired color.When switch 140 is in the MANUAL position, the gains of chrominance amplifier 122 and luminance amplifier 130 are controlled by adjustment of the position of potentiometer 146. When switch 150 is in the AUTO position the gain of the chrominance amplifier 122 and luminance amplifier is automatically controlled by the response of LDR 148 to ambient light conditions. The voltage developed at the wiper of potentiometer 146 (base of transistor 152) when switch 150 is in the AUTO position is inversely related to the ambient light recieved by LDR 148. It is noted that the values of resistors 114, potentiometer 146, LDR 148 and resistor 151 are desirably selected such that the adjustment of the wiper arm of potentiometer 146 when switch 150 is in the MANUAL position does not substantially affect the voltage developed at the base of transister 152 when switch 150 is placed in the AUTO position.
The control voltage v developed at the wiper arm of potentiometer 146 is coupled through emitter-follower transistor 152 to the common junction of potentiometer 156 and variable resistor 159. A control voltage vL comprising v plus a predetermined portion of the difference VO -v developed across the series connection of fixed resistor 154 and potentiometer 156, depending on the setting of potentiometer 156, is coupled to luminance amplifier 130 to control its gain. Similarly, a control voltage vC comprising v plus a predetermined portion of the difference voltage VO -v developed across the series connection of potentiometer resistor 158 and variable resistor 159, depending on the setting of the wiper of potentiometer 158, is coupled to chrominance amplifier 122 to control its gain.
The gain of luminance amplifier 130 may be pre-set to a desired value by the factory adjustment of potentiometer 156. Similarly, variable resistor 159 is provided to allow factory pre-set of the gain of the chrominance amplifier 122. Potentiometer 158 is provided to allow customer control of saturation.
R
eferring to FIG. 2, the gain versus voltage characteristics of chroma amplifier 122 (gC) and luminance amplifier 130 (gL) are shown. The characteristic gC has a reversed S-shape including a linear portion 214. Extrapolated linear portion 214 of gC intersects the GAIN axis at GC and intersects the CONTROL VOLTAGE axis at VO. Similarly, the characteristics gL has a reverse S-shape characteristic including a linear portion 212. Extrapolated linear portion 214 of gL intersects the GAIN axis at GL and intersects the CONTROL VOLTAGE axis at VO.From FIG. 2, the expression for linear portion 212 of gL is ##EQU1## The expression for linear portion 214 of gC is ##EQU2## From FIG. 1, the expression for vL is vL = v + (VO -v) K1 [3]
where K1 is determined by the voltage division of fixed resistor 154 and potentiometer 156 at the wiper of potentiometer 156. When the wiper of potentiometer 156 is at the emitter of transistor 152, K1 =0. The expression for vC is vC = v + (VO -v)K2 [4]
where K2 is determined by the voltage division of potentiometer 158 and fixed resistor 159 at the wiper of potentiometer 158. By combining equations [1] and [3], the equation for gL becomes ##EQU3## By combining equations [2] and [4], the equation for gC becomes ##EQU4## The ratio of gL to gC is thus ##EQU5## It is noted that this ratio is independent of DC control voltage v. Thus, although DC control voltage v may be varied either manually or in response to ambient light to control the contrast of an image reproduced by kinescope 128, the saturation remains constant.
With re
ference to FIG. 2, it is noted that although the linear portion 214 of gC has an extrapolated gain equal to 0 at a control voltage equal to VO, the non-linear portion of gC does not attain a gain equal to 0 until a control voltage equal to VB. That is, a control voltage of VO will not cut-off chrominance amplifier 122.In FIG. 1A there is shown, in schematic form, a modification to the arrangement of gain control network 142 of FIG. 1 with provisions which allow a viewer to cut off chrominance amplifier 122 to produce a more pleasing image under conditions of poor color reception due, for example, to noise or interference. The modifications to gain control unit 142 shown in FIG. 1A include coupling potentiometer resistor 158 between a source of positive supply voltage VB, the value of VB being greater than the value of VO, and coupling a resistor 160 from a tap-off point 162 along potentiometer 158 to ground. The value of potentiometer 158 and resistor 160 and the location of tap 162 are selected so that voltage VO is developed at tap 162.
The arrangement shown in FIG. 1A allows for the adjustment of contrast while constant saturation is maintained and additionally allows a viewer, by adjusting the wiper of potentiometer 158 to voltage VB, to cut off chrominance amplifier 122.
Referring to FIG. 3 there are shown gain versus DC control voltage characteristics of chrominance and luminance amplifiers which do not have the same extrapolated linear cut off control voltage. The gain versus control voltage characteristic gL ' of the luminance amplifier has a reverse S-shape characteristic including a linear portion 312. Extrapolated linear portion 312 of gL ' intersects the GAIN axis at a gain GL ' and intersects the CONTROL VOLTAGE axis at a voltage VO '. The gain versus control voltage characteristic gC ' of the chrominance amplifier has a reverse S-shape characteristic having a linear portion 314. Extrapolated linear portion 314 of gC ' intersects the GAIN axis at a gain GC ' and intersects the CONTROL VOLTAGE axis at a voltage AVO ', where A is a number greater than zero.
From FIG. 3, the expression for linear portion 312 of gL ' is ##EQU6## where vL ' is the DC conrol voltage coupled to the luminance amplifier. The expression for linear portion 314 of gC ' is ##EQU7## where vC ' is the DC control voltage coupled to the chrominance amplifier.
A modified form of the control network 142 of FIG. 1 suitable for controlling the gain of a chrominance and a luminance amplifier having characteristics such as shown in FIG. 3 is shown in FIG. 4. Similar portions of FIGS. 1 and 4 are identified by reference numbers having the same last two significant digits and primed (') designations. The modified portions of FIG. 1 shown in FIG. 4 include the series connection resistors 460 and 462 coupled between the emitter of transistor 452 to ground. The values of resistors 460 and 462 are selected so that a portion Av' of the DC control voltage v' developed at the emitter of transistor 452 is developed at the junction of resistors 460 and 462. Furthermore, the series connection of potentiometer 458 and variable resistor 459 is coupled between the junction of resistor 460 and 462 and a source of positive supply voltage AVO '.
From FIG. 4, the expression for control voltage vL ' developed at the wiper of potentiometer 456 is vL ' = v' + (vO '-v')K1 ' [10]where K1 ' is determined by the voltage division at the wiper of potentiometer 456. The expression for control voltage vC ' developed at the wiper of potentiometer 458 is VC ' = Av' + (AVO ' - Av')K 2 ' [11]
where K2 ' is determined by the voltage division at the wiper of potentiometer 458. By combining equations [8] and [10], ##EQU8## By combining equations [9] and [11], ##EQU9## The ratio of gL ' to gC ' is given by the expression ##EQU10## It is noted that this ratio is independent of DC control voltage v'. Therefore, gain control network 442 of FIG. 4 also allows for the adjustment of contrast while maintaining constant saturation.
It is noted that if A were made equal to 1, the arrangement gain control unit 442 would be suitable to control the gains of chrominance and luminance amplifiers having the characteristics shown in FIG. 2.
In FIG. 5, there is shown an amplifier suitable for use as luminance amplifier 130 of FIG. 1. The amplifier includes a differential amplifier comprising NPN transistors 532 and 534. The commonly coupled emitters of transistors 532 and 534 are coupled to the collector of an NPN transistor 528. The emitter of transistor 528 is coupled via a resistor 530 to ground. The collector of transistor 532 and the collector of transistor 534, via load resistor 536, is coupled to a bias voltage provided by bias supply 546, illustrated as a series connection of batteries. The bases of transistors 532 and 534 are respectively coupled to a lower bias voltage through resistors 533 and 535 respectively.
An input signal, such as, for example, the output signal provided by first luminance processing circuit 129 of FIG. 1 is coupled to the base of transistor 532 via terminal 542. The output signal of the amplifier is developed at the collector of transistor 534 and coupled to output terminal 544.
A DC control voltage, such as vL provided by gain control unit 142 of FIG. 1, is coupled to the base of an NPN transistor 514, arranged as an emitt
er-follower, via
terminal 512. The collector of transistor 514 is coupled to bias
supply 546. The emitter of transistor 514 is coupled to ground through
the series connection of resistor 516, a diode connected transistor
518 and resistor 520.The anode of diode 520 is coupled to the base of an NPN transistor 538. The collector of transistor 538 is coupled to the collector of transistor 534 while its emitter is coupled to ground through resistor 540. Transistor 538, resistor 540, diode 518 and resistor 520 are arranged in a current mirror configuration.
The emitter of transistor 514 is coupled to the base of a PNP transistor 522. The emitter of transistor 522 is coupled to bias supply 546 while its collector is coupled to the base of transistor 528 and to ground through the series connection of a diode connected transistor 524 and resistor 526. Transistor 528, resistor 530, diode 524 and resistor 526 are arranged in a current mirror configuration
In operation, the DC control voltage coupled to terminal 512 is coupled in inverted fashion to the anode of diode 524 by transistor 522. As a result, current directly related to the voltage developed at the anode of diode 524 flows through diode 524 and resistor 526. Due to the operation of the current mirror arrangement of diode 524, resistor 526, transistor 528 and resistor 530, a similar current flows through the emitter circuit of transistor 528. The gain of the differential amplifier comprising transistors 532 and 534 is directly related to this current flowing in the emitter circuit of transistor 528, and therefore is inversely related to the DC control voltage at terminal 512. The gain versus DC control voltage characteristics of the differential is similar to gL shown in FIG. 2.
Further, a current is developed through the series connection of resistor 516, diode 518 and resistor 520 in direct relationship to the DC control coupled to terminal 512. A similar current is developed through resistor 540 due to the operation of the current mirror comprising diode 518, resistor 520, transistor 538 and resistor 540. This current is of the opposite sense to that provided by the current mirror arrangement of diode 524, resistor 526, transistor 528 and resistor 530 and is coupled to the collector of transistor 534 so that the DC voltage at output terminal 544 does not substantially vary with the DC control voltage.
In FIG. 6, ther
e
is shown an amplifier suitable for use as chroma amplifier 120 of
FIG. 1. The amplifier shown in FIG. 6 is of the type described in U.S.
patent application Ser. No. 530,405 entitled "Controllable Gain
Signal Amplifier," fled by L.A. Harwood et al. on Dec. 6, 1974.The amplifier comprises a differential amplifier including NPN transistors 624 and 625 having their bases coupled to terminal 603 via a resistor 626. Chrominance signals, provided by a source of chrominance signals such as chrominance processing unit 120 of FIG. 1, are coupled to terminal 603. The current conduction paths between the collectors and emitters of transistors 624 and 625 are respectively coupled to ground via resistors 628, 629 and 630.
A current splitter circuit comprising an NPN transistor 632 and a diode 634 is coupled to the collector of transistor 624. Diode 634 and the base-emitter junction of transistor 632 are poled in the same direction with respect to the flow of collector current in transistor 624. It desirable that conduction characteristics of transistor 632 and diode 635 be substantially matched. Similarly, the collector of transistor 625 is coupled to a second current splitter comprising a transistor 633 and a diode 635.
An output load circuit comprising series connected resistors 636 and 638 is coupled between the collector of transistor 632 and a source of operating voltage provided by bias supply 610. Amplified chrominance signals are provided at output terminal 640 for coupling, for example, to a chroma demodulator such as chroma demodulator 124 of FIG. 1. Similarly, series connected load resistors 637 and 639 are coupled between the collector of transistor 633 and bias supply 610. An output terminal 641 at the junction of resistors 637 ad 639 provides oppositely phased chrominance signals to those provided at terminal 640. The gain associated with the cascode combination of transistors 624 and 632 is controlled in response to a DC control voltage, such as, for example, vC provided by gain control unit 142 of FIG. 1, coupled to the base of an NPN transistor 646 via terminal 602. Direct control current is supplied from the emitter of transistor 646 to diode 634 and 635 via a series resistor 652. A signal by-pass circuit comprising a series resonant combination 654 of inductance and capacitance is coupled from the anode of diode 634 to ground. Resonant circuit 654 is tuned, for example, to 3.58 MHz to provide a low impedance path to ground for color subcarrier signals.
Bias voltages and currents are supplied to the amplifier arrangement by bias supply 610, illustrated as a series connection of batterys. A voltage B+ is coupled to the collector of transistor 646. A lower bias voltage is coupled to the load circuits of transistors 632 and 633. The bases of transistors 632 and 633 are coupled in common to a still lower bias voltage. The bases of transistors 624 and 625 are coupled to a still lower bias voltage via substantially equal in value resistors 658 and 659. A resistor 694 is coupled from the common junction of resistors 658 and 659 to ground.
I
n operation, a quiescent operating current is provided through resistor 630. In the absence of an input signal at terminal 603, this current will divide substantially equally between the similarly biased transistors 624 and 625. If the DC control voltage at terminal 602 is near ground potential, transistor 646 will be effectively cut off and no current will flow in resistor 652 and diodes 634 and 635. In that case, neglecting the normally small difference betweeen collector and emitter currents of NPN transistors, the collector currents of transistors 624 and 625 will flow, respectively, in transistors 632 and 633. The transistors 632 and 633 are operated in common base mode and form cascode signal amplifiers with respective transistors 624 and 625. With the DC control voltage near ground potential, one-half of the quiescent current from resistor 630 flows in each of the load circuits and maximum gain for chrominance signals supplied from terminal 603 is provided.
Transistor 646 will conduct when the DC control voltage approaches the bias voltage supplied to the bases of transistors 632 and 633 of the current splitters. By selection of the circuit parameters, diodes 634 and 635 may be arranged to operate in a range between cut off to the conduction of all of the quiescent operating current supplied via resistor 630, thereby cutting off transistors 632 and 633 to provide no output signals at terminals 640 and 641.
At a DC control voltage intermediate to that corresponding to cut off of transistors 632 and 633 on the one hand and cut off of diodes 634 and 635 on the other hand, the voltage gain of the illustrated amplifier will vary in a substantially linear manner with the DC control voltage.
It
is noted that although the characteristics shown in FIGS. 2 and 3
were reversed S-shaped characteristics, the characteristics could have
other shapes including linear portions. For example, the
characteristics could be substantially linear. Furthermore, with
reference to FIG. 3, although gC ' was shown as having a
linear portion that had a cut off control voltage lower than the cut
off control voltage of the linear portion of gL ', the cut off control voltage of the linear portion of gC ' could be greater than the cut off voltage for the linear region of gL
'. In addition, the gain control units and associate amplifiers could
be arranged to utilize voltages opposite in polarity to those shown.
These and other modifications are intended to be within the scope of
the invention.
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