The chassis is an awesome example of enegineering.
The chassis is fully modularized and has a technology like a high grade professional monitor.
The Beovision 7702 replaced the Beovision 7700 for the reason of the introduction of the new 77XX 30AX series chassis. This was in many ways similar to the final version of the previous 33XX type, to the point where most of the circuit modules were interchangeable, though there was one big change: electronic tuning.
The 77XX models included a microprocessor controlled “search and store” tuning system that offered a number of advantages over the bank of tuning knobs that the 33XX models used. 32 programmes could be stored, tuning was automatic and could be operated from either the set or the remote control. In the case where the channel number was known, this could be entered directly, making the tuning “instant”.
Teletext was a standard fitting for the 1984 season but it reverted to being an option for the rest of the production run. A single A/V socket (DIN A/V standard) was standard though a dual A/V interface could be specified, providing an extra DIN A/V socket (SCART in later versions), at extra cost.
BANG & OLUFSEN BEOVISION 7702 CHASSIS SERIES 77XX 30AX Horizontal deflection output circuit:
1. A horizontal deflection output circuit comprising:
a switching element;
a resonant capacitor connected in parallel with said switching element; and
a first series circuit connected in parallel with said switching element and including a horizontal deflection coil and a linearity correcting coil,
wherein the improvement comprises:
a second series circuit connected in parallel with said linearity correcting coil, said second series circuit comprising load means for damping resonance energy in said first series circuit and current control means for limiting the current flow through said load means to the first half of a horizontal scanning period and including a one-way switching element which turns on for a first half of said horizontal scanning period and turns off for the last half of the horizontal scanning period and for a fly-back pulse period, thereby limiting current flow through said load means to the first half of said horizontal scanning period.
2. A horizontal deflection output circuit according to claim 1, wherein said load means includes a resistor. 3. A horizontal deflection output circuit according to claim 2, wherein a capacitor is connected in parallel with said linearity correcting coil. 4. A horizontal deflection output circuit according to claim 2, wherein said one-way switching element is a diode. 5. A horizontal deflection output circuit according to claim 1, wherein said load means includes: a resistor; and current adjusting means for adjusting the current to flow through said resistor. 6. A horizontal deflection output circuit comprising:
a switching element;
a resonant capacitor connected in parallel with said switching element;
a series circuit connected in parallel with said switching element and including a horizontal deflection coil and a linearity correcting coil; and
a series circuit connected in parallel with said linearity correcting coil and including load means and a one-way switching element adapted to be turned on for the front half of a horizontal scanning period, said load means including a resistor and current adjusting means for adjusting the current flow through said resistor, said current adjusting means including a transistor connected in series with said resistor and bias voltage feeding means for feeding a bias voltage to the base of said transistor.
7. A horizontal deflection output circuit according to claim 6, wherein a capacitor is connected in parallel with said linearity correcting coil. 8. A horizontal deflection output circuit according to claim 6, wherein said one-way switching element is turned off at least for a fly-back pulse period. 9. A horizontal deflection output circuit according to claim 6, wherein said one-way switching element is a diode. 10. A horizontal deflection output circuit according to claim 6, wherein said bias voltage feeding means includes resistance voltage-dividing means for dividing the voltage between the two terminals of said linearity correcting coil. 11. A horizontal deflection output circuit according to claim 10, wherein a capacitor is connected in parallel with said linearity correcting coil. 12. A horizontal deflection output circuit according to claim 10, wherein said one-way switching element is turned off at least for a fly-back pulse period. 13. A horizontal deflection output circuit according to claim 10, wherein said one-way switching element is a diode. 14. A horizontal deflection output circuit according to claim 10, wherein said bias voltage feeding means includes a time constant circuit composed of a resistor and a capacitor. 15. A horizontal deflection output circuit according to claim 14, wherein a capacitor is connected in parallel with said linearity correcting coil. 16. A horizontal deflection output circuit according to claim 14, wherein said one-way switching element is a diode. 17. A horizontal deflection output circuit according to claim 14, wherein said one-way switching element is turned off at least for a fly-back pulse period. 18. A horizontal deflection output circuit comprising:
a switching element;
a damper diode connected in parallel with said switching element;
a resonant capacitor connected in parallel with said switching element;
a first series circuit connected in parallel with said switching element and including a horizontal deflection coil and a linearity correcting coil;
a second series circuit connected in parallel with said linearity correcting coil, said second series circuit comprising load means for damping resonance energy in said first series circuit and current control means for limiting the current flow through said load means to the first half of a horizontal scanning period and including a one-way switching element which turns on for the first half of said horizontal scanning period and turns off for the last half of said horizontal scanning period and a fly-back pulse period, thereby limiting current flow through said load means to said first half of said horizontal scanning period;
a choke coil connected with the cathode terminal of said damper diode; and
a d.c. current blocking capacitor connected in series with said horizontal deflection coil.
19. A horizontal deflection output circuit according to claim 18, wherein said choke coil is a fly-back transformer. 20. A horizontal deflection output circuit according to claim 19, wherein said load means includes a resistor. 21. A horizontal deflection output circuit according to claim 20, wherein a capacitor is connected in parallel with said linearity correcting coil. 22. A horizontal deflection output circuit according to claim 20, wherein said one-way switching element is a diode. 23. A horizontal deflection output circuit according to claim 19, wherein said load means includes: a resistor; and current adjusting means for adjusting the current to flow through said resistor. 24. A horizontal deflection output circuit comprising:
a switching element;
a damper diode connected in parallel with said switching element;
a resonant capacitor connected in parallel with said switching element;
a series circuit connected in parallel with said switching element and including a horizontal deflection coil and a linearity correcting coil;
a series circuit connected in parallel with said linearity correcting coil and including load means and a one-way switching element adapted to be turned on for the front half of a horizontal scanning period, said load means including a resistor and current adjusting means for adjusting the current flow through said resistor, said current adjusting means including a transistor connected in series with said resistor and bias voltage feeding means for feeding a bias voltage to the base of said transistor;
a choke coil in the form of a fly-back transformer connected with the cathode terminal of said damper diode; and
a d.c. current blocking capacitor connected in series with said horizontal deflection coil.
25. A horizontal deflection output circuit according to claim 24, wherein said one-way switching element is turned off at least for a fly-back pulse period. 26. A horizontal deflection output circuit according to claim 24, wherein a capacitor is connected in parallel with said linearity correcting coil. 27. A horizontal deflection output circuit according to claim 24, wherein said one-way switching element is a diode. 28. A horizontal deflection output circuit according to claim 24, wherein said bias voltage feeding means includes resistance voltage-dividing means for dividing the voltage between the two terminals of said linearity correcting coil. 29. A horizontal deflection output circuit according to claim 28, wherein said bias voltage feeding means includes a time constant circuit composed of a resistor and a capacitor. 30. A horizontal deflection output circuit according to claim 28, wherein said one-way switching element is turned off at least for a fly-back pulse period. 31. A horizontal deflection output circuit according to claim 28, wherein a capacitor is connected in parallel with said linearity correcting coil. 32. A horizontal deflection output circuit according to claim 28, wherein said one-way switching element is a diode.
The present invention relates to a horizontal deflection output circuit which is to be used with a high resolution display and which has a high horizontal deflection frequency and a high output.
In a conventional TV receiver, a horizontal deflection current having a saw-tooth waveform reaches saturation as it approaches its maximum, causing a problem in that the scanning rate of the electron beam is reduced at the extreme right-hand side, as viewed toward the frame of the display, so that the picture reproduced on the face plate is distorted.
The circuit for solving the above-specified problem to form a symmetrical picture is called a "linearity correcting circuit". In order to correct the linearity of the raster scanned on the face plate, the linearity correcting circuit of the prior art is equipped with a linearity correcting coil which is connected in series with a horizontal deflection coil. That linearity correcting coil is so magnetically biased by means of a permanent magnet that its magnetic saturation characteristics are set differently depending upon the direction of the horizontal deflection current. This horizontal deflection circuit is exemplified by Japanese Patent Laid-Open Nos. 40615/1982, 128949/1981, 124850/1980 and U.S. Pat. No. 3,962,603, as shown schematically in FIGS. 1A and 1B.
As shown in FIG. 1A, the horizontal deflection circuit is composed of an input terminal 1, an output transistor 2, a damper diode 3, a resonant capacitor 4, a horizontal deflection coil 5, a linearity correcting coil 6, an S-shaped correction capacitor 7, a choke coil 8, a supply terminal 9, and a permanent magnet 12 for setting the magnetic bias of the linearity correcting coil 6.
The permanent magnet 12 has its polarity arranged so as to apply a magnetic field in the same direction as that of the magnetic field established in the linearity correcting coil in case a horizontal deflection current IDY flows in the direction of arrow a to the horizontal deflection coil 5.
In case the horizontal deflection current IDY flows in the direction of the arrow a, therefore, the linearity correcting coil 6 is more liable to be magnetically saturated than when the horizontal deflection current IDY flows in the reverse direction.
As a result, the inductance of the linearity correcting coil 6 is least in the vicinity of the maximum of the horizontal deflection current so that this current increases.
Thus, the drop of the scanning rate of the electron beam at the right side of the display frame is corrected. In the display, however, the use of a linearity correcting coil will form longitudinal shading streaks at the left side of the display frame. Those streaks are formed as a result of the fact that a ringing current is established in the horizontal deflection current by the resonance of a resonant circuit which is composed of the inductance of the linearity coil 6 and a stray capacity 17, as shown in FIG. 1B.
In order to solve this problem, the horizontal deflection circuit of the prior art is equipped with a resistor 14 which is connected in parallel with the linearity correcting coil 6. By the provision of that resistor 14, the resonant circuit of the stray capacity and the linearity correcting coil has its Q (i.e., quality) factor dropped to reduce the amplitude of the ringing current.
As the horizontal deflection current has its frequency increased and its output raised in accordance with the fineness in the structure of the display, however, there arises another problem that the power loss at the ringing current preventing resistor is increased.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a horizontal deflection output circuit of high speed and output enabled to reduce such ringing of the horizontal deflection current as will raise a problem, when the horizontal linearity is to be corrected by a linearity correcting coil, without inviting an increase in the loss of the output circuit thereby to eliminate in a more advantageous way the longitudinal streaks which might otherwise be formed in a picture frame.
In order to achieve the above-specified object, the horizontal deflection output circuit according to the present invention has a series circuit connected in parallel with a linearity coil, the series circuit being composed of a resistor and a switching element. The switching element is so controlled that it may be turned on only for a predetermined time period including that for which ringing occurs in the horizontal deflection current.
BANG & OLUFSEN BEOVISION 7702 CHASSIS SERIES 77XX 30AX Horizontal deflection circuit with a start-up power supply
I
n a horizontal deflection circuit, a horizontal oscillator, energized by a supply voltage, develops a horizontal frequency switching signal. A deflection outputs stage is responsive to the switching signal and generates scanning current in a horizontal deflection winding. After commencement of oscillator operation, the voltage developed across a secondary winding of a flyback transformer is rectified and filtered and applied to the horizontal oscillator as the oscillator energizing supply voltage. A start-up supply for developing the oscillator supply voltage during an initial interval includes a source of voltage that is available for use prior to the commencement of oscillator operation, a capacitor, a charging circuit for charging the capacitor from the available voltage source, and a controllable switch coupled to the capacitor and to the oscillator. After the charging circuit has charged the capacitor to a predetermined threshold voltage level, the controllable switch is made conductive to apply the capacitor voltage to the oscillator to commence oscillator operation. The switch is arranged with the capacitor as a relaxation oscillator to begin discharging the capacitor by the load current drawn by the horizontal oscillator. Should the capacitor discharge to a lower threshold level before the flyback-derived supply voltage is developed, the relaxation oscillator changes states to disconnect the horizontal oscillator from the capacitor to initiate a capacitor recharging cycle.
1. An oscillator-derived power supply with start-up circuitry, comprising:
a supply terminal;
an oscillator being energized by the voltage developed at said supply terminal for producing an oscillator output signal;
a start-up voltage supply to energize said oscillator into commencing operation, said start-up voltage supply comprising:
a capacitor,
a source of DC input voltage available prior to commencement of oscillator operation,
means for charging said capacitor from said DC input voltage source, and
switching means interposed between said capacitor and said supply terminal for applying said capacitor voltage to said oscillator after said capacitor has charged to a first threshold level, to commence oscillator operation;
means responsive to said oscillator output signal for developing a steady-state voltage; and
means for applying said steady-state voltage to said supply terminal via said switching means to maintain oscillator energization during steady-state operation.
2. A supply according to claim 1 wherein the minimum load current required by said oscillator to commence operation exceeds in magnitude the current being provided to said capacitor by said charging means.
3. A supply according to claim 2 wherein said capacitor is being discharged to lower voltage by said oscillator after said switching means applies said capacitor voltage to said supply terminal and prior to steady-state oscillator operation.
4. A supply according to claim 3 wherein said steady-state voltage maintains said capacitor charged to a substantially constant voltage level during said steady-state operation.
5. A supply according to claim 4 wherein said DC input voltage is of greater magnitude than the magnitude of said substantially constant voltage level.
6. A supply according to claim 4 wherein said switching means serves to disconnect said capacitor from said supply terminal when said capacitor discharges to a second threshold level lower than said first threshold level to enable said capacitor to recharge.
7. A supply according to claim 6 wherein said steady-state voltage applying means comprises a diode blocking current flow from said charging means to said steady-state voltage developing means.
8. A supply according to any preceding claim wherein said oscillator comprises a deflection generator oscillator and wherein said oscillator output signal responsive means comprises a deflection generator output stage, a flyback transformer coupled to said output stage for developing a flyback pulse voltage across a transformer secondary winding, and rectifying and filtering means for developing said steady-state voltage from said flyback pulse voltage.
9. A deflection circuit-derived power supply with a start-up supply for the deflection circuit oscillator, comprising:
a horizontal oscillator energized by a supply voltage for developing a horizontal frequency switching signal after commencement of oscillator operation;
a horizontal deflection winding;
a deflection output stage responsive to said horizontal frequency switching signal for generating scanning current in said deflection winding;
a flyback transformer having a first winding coupled to said deflection output stage for developing a horizontal frequency alternating polarity output voltage across a plurality of secondary windings;
supply voltage producing means responsive to the horizontal frequency alternating polarity output voltage developed across one of said plurality of secondary windings for producing said supply voltage after commencement of horizontal oscillator operation; and
a start-up supply for developing said supply voltage during an initial interval to enable said horizontal oscillator to commence operation, said start-up supply comprising:
a source of voltage available prior to commencement of horizontal oscillator operation,
a capacitor,
means for charging said capacitor from said prior available voltage source, and
switching means coupled to said capacitor and to said horizontal oscillator for applying said capacitor voltage to said horizontal oscillator as said supply voltage to commence horizontal oscillator operation after said charging means has charged said capacitor to an upper threshold voltage level, said switching means arranged with said capacitor as a relaxation oscillator that begins discharging said capacitor by the load current drawn by said horizontal oscillator after said charging means has charged said capacitor to said upper threshold voltage level and begins recharging said capacitor from said charging means when said capacitor discharges to a lower threshold voltage level.
10. A supply according to claim 9 wherein said switching means comprises a first transistor interposed between said capacitor and said horizontal oscillator and a second transistor coupled to said capacitor and to a control electrode of said first transistor.
11. A supply according to claim 9 wherein said supply voltage producing means comprises means for rectifying and filtering said horizontal frequency alternating polarity output voltage and means for applying the output of said rectifying and filtering means to said capacitor to develop said supply voltage as a substantially constant voltage across said capacitor.
12. A supply according to claim 11 wherein said prior available voltage source comprises a source of DC input voltage of magnitude greater than said substantially constant voltage.
BANG & OLUFSEN BEOVISION 7702 CHASSIS SERIES 77XX 30AX CIRCUIT ARRANGEMENT IN A PICTURE DISPLAY DEVICE UTILIZING A STABILIZED SUPPLY VOLTAGE CIRCUIT:TDA2581 CONTROL CIRCUIT FOR SMPS/PHILIPS POWER PACK:
The TDA2581 is a monolithic integrated circuit for controlling switched-mode power supplies (SMPS) which are provided with the drive for the horizontal deflection stage.
The circuit features the following:
— Voltage controlled horizontal oscillator.
— Phase detector.
— Duty factor control for the positive-going transient of the output signal.
— Duty factor increases from zero to its normal operation value.
— Adjustable maximum duty factor.
- Over-voltage and over-current protection with automatic re-start after switch-off.
— Counting circuit for permanent switch-off when n~times over~current or over-voltage is sensed
-Protection for open-reference voltage.
- Protection for too low supply voltage.
Protection against loop faults.
Positive tracking of duty factor and feedback voltage when the feedback voltage is smaller than the
reference voltage minus 1,5 V.
BANG & OLUFSEN BEOVISION 7702 CHASSIS SERIES 77XX 30AX Line synch Switched Mode Power Supply with Line deflection output Transistor Drive Circuit:
A stabilized supply voltage circuit for a picture display device comprising a chopper wherein the switching signal has the line frequency and is duration-modulated. The coil of the chopper constitutes the primary winding of a transformer a secondary winding of which drives the line output transistor so that the switching transistor of the chopper also functions as a driver for the line output stage. The oscillator generating the switching signal may be the line oscillator. In a special embodiment the driver and line output transistor conduct simultaneously and in order to limit the base current of the line output transistor a coil shunted by a diode is incorporated in the drive line of the line output transistor. Other secondary windings of the transformer drive diodes which conduct simultaneously with the efficiency diode of the chopper so as to generate further stabilized supply voltages.
Description:
The invention relates to a circuit arrangement in a picture display device wherein the input direct voltage between two input terminals, which is obtained be rectifying the mains alternating voltage, is converted into a stabilized output direct voltage by means of a switching transistor and a coil and wherein the transistor is connected to a first input terminal and an efficiency diode is connected to the junction of the transistor and the coil. The switching transistor is driven by a pulsatory voltage of line frequency which pulses are duration-modulated in order to saturate the switching transistor during part of the period dependent on the direct voltage to be stabilized and to cut off this transistor during the remaining part of the period. The pulse duration modulation is effected by means of a comparison circuit which compares the direct voltage to be stabilized with a substantially constant voltage, the coil constituting the primary winding of a transformer.
Such a circuit arrangement is known from German "Auslegeschrift" 1.293.304. wherein a circuit arrangement is described which has for its object to convert an input direct voltage which is generated between two terminals into a different direct voltage. The circuit employs a switch connected to the first terminal of the input voltage and periodically opens and closes so that the input voltage is converted into a pulsatory voltage. This pulsatory voltage is then applied to a coil. A diode is arranged between the junction of the switch and the coil and the second terminal of the input voltage whilst a load and a charge capacitor in parallel thereto are arranged between the other end of the coil and the second terminal of the input voltage. The assembly operates in accordance with the known efficiency principle i.e., the current supplied to the load flows alternately through the switch and through the diode. The function of the switch is performed by a switching transistor which is driven by a periodical pulsatory voltage which saturates this transistor for a given part of the period. Such a configuration is known under different names in the literature; it will be referred to herein as a "chopper." A known advantage thereof, is that the switching transistor must be able to stand a high voltage or provide a great current but it need not dissipate a great power. The output voltage of the chopper is compared with a constant reference voltage. If the output voltage attempts to vary because the input voltage and/or the load varies, a voltage causing a duration modulation of the pulses is produced at the output of the comparison arrangement. As a result the quantity of the energy stored in the coil varies and the output voltage is maintained constant. In the German "Auslegeschrift" referred to it is therefore an object to provide a stabilized supply
voltage device.
In the circuit arrangement according to the mentioned German "Auslegeschrift" the frequency of the load variations or a harmonic thereof is chosen as the frequency for the switching voltage. Particularly when the load fed by the chopper is the line deflection circuit of a picture display device, wherein thus the impedance of the load varies in the rhythm of the line frequency, the frequency of the switching voltage is equal to or is a multiple of the line frequency.
It is to be noted that the chopper need not necessarily be formed as that in the mentioned German "Auslegeschrift." In fact, it is known from literature that the efficiency diode and the coil may be exchanged. It is alternatively possible for the coil to be provided at the first terminal of the input voltage whilst the switching transistor is arranged between the other end and the second terminal of the input voltage. The efficiency diode is then provided between the junction of said end and the switching transistor and the load. It may be recognized that for all these modifications a voltage is present across the connections of the coil which voltage has the same frequency and the same shape as the pulsatory switching voltage. The control voltage of a line deflection circuit is a pulsatory voltage which causes the line output transistor to be saturates and cut off alternately. The invention is based on the recognition that the voltage present across the connections of the coil is suitable to function as such a control voltage and that the coil constitutes the primary of a transformer. To this end the circuit arrangement according to the invention is characterized in that a secondary winding of the transformer drives the switching element which applies a line deflection current to line deflection coils and by which the voltage for the final anode of a picture display tube which forms part of the picture display device is generated, and that the ratio between the period during which the switching transistor is saturated and the entire period, i.e., the switching transistor duty cycle is between 0.3 and 0.7 during normal operation.
The invention is also based on the recognition that the duration modulation which is necessary to stabilize the supply voltage with the switching transistor does not exert influence on the driving of the line output transistor. This resides in the fact that in case of a longer or shorter cut-off period of the line output transistor the current flowing through the line deflection coils thereof is not influenced because of the efficiency diode current and transistor current are taken over or, in case of a special kind of transistor, the collector-emitter current is taken over by the base collector current and conversely. However, in that case the above-mentioned ratios of 0.3 : 0.7 should be taken into account since otherwise this take-over principle is jeopardized.
As will be further explained the use of the switching transistor as a driver for the line output transistor in an embodiment to be especially described hereinafter has the further advantage that the line output transistor automatically becomes non-conductive when this switching transistor is short circuited so that the deflection and the EHT for the display tube drop out and thus avoid damage thereof.
Due to the step according to the invention the switching transistor in the stabilized supply functions as a driver for the line deflection circuit. The circuit arrangement according to the invention may in addition be equipped with a very efficient safety circuit so that the reliability is considerably enhanced, which is described in the U.S. Pat. No. 3,629,686. The invention is
furthermore based on the recognition of the fact that the pulsatory voltage present across the connections of the coil is furthermore used and to this end the circuit arrangement according to the invention is characterized in that secondary windings of the transformer drive diodes which conduct simultaneously with the efficiency diode so as to generate further stabilized direct voltages, one end of said diodes being connected to ground.
In order that the invention may be readily carried into effect, a few embodiments thereof will now be described in detail by way of example with reference to the accompanying diagrammatic drawings in which:
FIG. 1 shows a principle circuit diagram wherein the chopper and the line deflection circuit are further shown but other circuits are not further shown.
FIGS. 2a, 2b and 2c show the variation as a function of time of two currents and of a voltage occurring in the circuit arrangement according to FIG. 1.
FIGS. 3a 3b, 3c and 3d show other embodiments of the chopper.
FIGS. 4a and 4b show modifications of part of the circuit arrangement of FIG. 1.
In FIG. 1 the reference numeral 1 denotes a rectifier circuit which converts the mains voltage supplied thereto into a non-stabilized direct voltage. The collector of a switching transistor 2 is connected to one of the two terminals between which this direct voltage is obtained, said transistor being of the npn-type in this embodiment and the base of which receives a pulsatory voltage which originates through a control stage 4 from a modulator 5 and causes transistor 2 to be saturated and cut off alternately. The voltage waveform 3 is produced at the emitter of transistor 2. In order to maintain the output voltage of the circuit arrangement constant, the duration of the pulses provided is varied in modulator 5. A pulse oscillator 6 supplies the pulsatory voltage to modulator 5 and is synchronized by a signal of line frequency which originates from the line oscillator 6' present in the picture display device. This line oscillator 6' is in turn directly synchronized in known manner by pulses 7' of line frequency which are present in the device and originate for example from a received television signal if the picture display device is a television receiver. Pulse oscillator 6 thus generates a pulsatory voltage the repetition frequency of which is the line frequency.
The emitter of switching transistor 2 is connected at one end to the cathode of an efficiency diode 7 whose other end is connected to the second input voltage terminal and at the other end to primary winding 8 of a transformer 9. Pulsatory voltage 3 which is produced at the cathode of efficiency diode 7 is clamped against the potential of said second terminal during the intervals when this diode conducts. During the other intervals the pulsatory voltage 3 assumes the value V i . A charge capacitor 10 and a load 11 are arranged between the other end of winding 8 and the second input voltage terminal. The elements 2,7,8,10 and 11 constitute a so-called chopper producing a direct voltage across charge capacitor 10, provided that capacitor 10 has a sufficiently great value for the line frequency and the current applied to load 11 flowing alternately through switching transistor 2 or through efficiency diode 7. The output voltage V o which is the direct voltage produced across charge capacitor 10 is applied to a comparison circuit 12 which compares the voltage V o with a reference voltage. Comparison circuit 12 generates a direct voltage which is applied to modulator 5 so that the duration of the effective period δ T of switching transistor 2 relative to the period T of pulses 3 varies as a function of the variations of output voltage V 0 . In fact, it is readily evident that output voltage V o is proportional to the ratio δ :
V o = V i . δ
Load 11 of the chopper consists in the consumption of parts of the picture display device which are fed by output voltage V 0 . In a practical embodiment of the circuit arrangement according to FIG. 1 wherein the mains alternating voltage has a nominal effective value of 220 V and the rectified voltage V i is approximately 270 V, output voltage V o for δ = 0.5 is approximately 135 V. This makes it also possible, for example, to feed a line deflection circuit as is shown in FIG. 1 wherein load 11 then represents different parts which are fed by the chopper. Since voltage V o is maintained constant due to pulse duration modulation, the supply voltage of this line deflection circuit remains constant with the favorable result that the line amplitude(= the width of the picture displayed on the screen of the picture display tube) likewise remains constant as well as the EHT required for the final anode of the picture display tube in the same circuit arrangement independent of the variations in the mains voltage and the load on the EHT generator (= variations in brightness).
However, variations in the line amplitude and the EHT may occur as a result of an insufficiently small internal impedance of the EHT generator. Compensation means are known for this purpose. A possibility within the scope of the present invention is to use comparison circuit 12 for this purpose. In fact, if the beam current passes through an element having a substantially quadratic characteristic, for example, a voltage-dependent resistor, then a variation for voltage V o may be obtained through comparison circuit 12 which variation is proportional to the root of the variation in the EHT which is a known condition for the line amplitude to remain constant.
In addition this facilitates smoothing of voltage V o since the repetition frequency of pulsatory voltage 3 is many times higher than that of the mains and a comparatively small value may be sufficient for charge capacitor 10. If charge capacitor 10 has a sufficiently high value for the line frequency, voltage V o is indeed a direct voltage so that a voltage having the same form as pulsatory voltage 3 is produced across the terminals of primary winding 8. Thus voltages which have the same shape as pulsatory voltage 3 but have a greater or smaller amplitude are produced across secondary windings 13, 14 of transformer 9 (FIG. 1 shows only 2 secondary windings but there may be more). The invention is based on the recognition that one end of each secondary winding is connected to earth while the other end thereof drives a diode, the winding sense of each winding and the direction of conductance of each diode being chosen to be such that these diodes conduct during the same period as does efficiency diode 7. After smoothing, stabilized supply voltages, for example, at terminal 15 are generated in this manner at the amplitudes and polarities required for the circuit arrangements present in the picture display device. In FIG. 1 the voltage generated at terminal 15 is, for example, positive relative to earth. It is to be noted that the load currents of the supply voltages obtained in this manner cause a reduction of the switching power which is economized by efficiency diode 7. The sum of all diode currents including that of diode 7 is in fact equal to the current which would flow through diode 7 if no secondary winding were wound on transformer 9 and if no simultaneous diode were used. This reduction may be considered an additional advantage of the circuit arrangement according to the invention, for a diode suitable for smaller powers may then be used. However, it will be evident that the overall secondary load must not exceed the primary load since otherwise there is the risk of efficiency diode 7 being blocked so that stabilization of the secondary supply voltages would be out of the question.
It is to be noted that a parabola voltage of line frequency as shown at 28 is produced across the charge capacitor 10 if this capacitor is given a smaller capacitance so that consequently the so-called S-correction is established.
In FIG. 1 charge capacitors are arranged between terminals 15 etc. and earth so as to ensure that the voltages on these points are stabilized direct voltages. If in addition the mean value of the voltage on one of these terminals has been made equal to the effective value of the alternating voltage which is required for heating the filament of the picture display tube present in the picture display device, this voltage is suitable for this heating. This is a further advantage of the invention since the cheap generation of a stabilized filament voltage for the picture display tube has always been a difficult problem in transistorized arrangements.
A further advantage of the picture display device according to the invention is that transformer 9 can function as a separation transformer so that the different secondary windings can be separated from the mains and their lower ends can be connected to ground of the picture display device. The latter step makes it possible to connect a different apparatus such as, for example, a magnetic recording and/or playback apparatus to the picture display device without earth connection problems occurring.
In FIG. 1 the reference numeral 14 denotes a secondary winding of transformer 9 which in accordance with the previously mentioned recognition of the invention can drive line output transistor 16 of the line deflection circuit 17. Line deflection circuit 17 which is shown in a simplified form in FIG. 1 includes inter alia line deflection coils 18 and an EHT transformer 19 a secondary winding 20 of which serves for generating the EHT required for the acceleration anode of the picture display tube. Line deflection circuit 17 is fed by the output voltage V o of the chopper which voltage is stabilized due to the pulse duration modulation with all previously mentioned advantages. Line deflection circuit 17 corresponds, for example, to similar arrangements which have been described in U.S. Pat. No. 3,504,224 issued Mar. 31, 1970 to J.J. Reichgelt et al., U.S. patent application Ser. No. 737,009 filed June 14, 1968 by W. H. Hetterscheid and U.S. application Ser. No. 26,497 filed April 8, 1970 by W. Hetterscheid et al. It will be evident that differently formed lined deflection circuits are alternatively possible.
It will now be shown that secondary winding 14 can indeed drive a line deflection circuit so that switching transistor 2 can function as a driver for the line deflection. FIGS. 2a and b show the variation as a function of time of the current i C which flows in the collector of transistor 16 and of the drive voltage v 14 across the terminals of secondary winding 14. During the flyback period (0, t 1 ) transistor 16 must be fully cut off because a high voltage peak is then produced at its collector; voltage v 14 must then be absolutely negative. During the scan period (t 1 , t 4 ) a sawtooth current i C flows through the collector electrode of transistor 16 which current is first negative and then changes its direction. As the circuit arrangement is not free from loss, the instant t 3 when current i C becomes zero lies, as is known, before the middle of the scan period. At the end t 4 of the scan period transistor 16 must be switched off again. However, since transistor 16 is saturated during the scan period and since this transistor must be suitable for high voltages and great powers so that its collector layer is thick, this transistor has a very great excess of charge carriers in both its base and collector layers. The removal of these charge carriers takes a period t s which is not negligible whereafter the transistor is indeed switched off. Thus the fraction δ T of the line period T at which v 14 is positive must end at the latest at the instant (t 4 - t s ) located after the commencement (t = 0) of the previous flyback.
The time δ T may be initiated at any instant t 2 which is located between the end t 1 of the flyback period and the instant t 3 when collector current i C reverses its direction. It is true that emitter current flows through transistor 16 at the instant t 2 , but collector current i C is not influenced thereby, at least not when the supply voltage (= V o ) for line deflection circuit 17 is high enough. All this has been described in the U.S. Pat. No. 3,504,224. The same applies to line deflection circuits wherein the collector base diode does not function as an efficiency diode as is the case in the described circuit 17, but wherein an efficiency diode is arranged between collector and emitter of the line output transistor. In such a case the negative part of the current i C of FIG. 2a represents the current flowing through the said efficiency diode.
After the instant t 3 voltage v 14 must be positive. In other words, the minimum duration of the period T when voltage v 14 must be positive is (t 4 - t s ) - t 3 whilst the maximum duration thereof is (t 4 - t s ) - t 1 . In a television system employing 625 lines per raster the line period t 4 is approximately 64 μus and the flyback period is approximately 12 μus. Without losses in the circuit arrangement instant t 3 would be located approximately 26 μus after the instant t 1 , and with losses a reasonable value is 22 μus which is 34 μus after the commencement of the period. If for safety's sake it is assumed that t s lasts approximately 10 μus, the extreme values of δ T are approximately 20 and 42 μus and consequently the values for δ are approximately 0.31 and 0.66 at a mean value which is equal to approximately 0.49. It was previously stated that a mean value of δ = 0.5 was suitable. Line deflection circuit 17 can therefore indeed be used in combination with the chopper in the manner described, and the relative variation of δ may be (0.66 - 0.31) : 0.49 = 71.5 percent. This is more than necessary to obviate the variations in the mains voltage or in the various loads and to establish the East-West modulation and ripple compensation to be described hereinafter. In fact, if it is assumed that the mains voltage varies between -15 and +10 percent of the nominal value of 220 V, while the 50 Hz ripple voltage which is superimposed on the input voltage V i has a peak-to-peak value of 40 V and V i is nominally 270 V, then the lowest occurring V i is:
0.85 × 270 V - 20 V = 210 V and the highest occurring V i is
1.1 × 270 V + 20 V = 320 V. For an output voltage V o of 135 V the ratio must thus vary between
δ = 135 : 210 = 0.64 and δ = 135 : 320 = 0.42.
A considerable problem presenting itself is that of the simultaneous or non-simultaneous drive of line output transistor 16 with switching transistor 2, it being understood that in case of simultaneous drive both transistors are simultaneously bottomed, that is during the period δ T. This depends on the winding sense of secondary winding 14 relative to that of primary winding 8. In FIG. 1 it has been assumed that the drive takes place simultaneously so that the voltage present across winding 14 has the shape shown in FIG. 2b. This voltage assumes the value n(V i - V o ) in the period δ T and the value -nVo in the period (1 - δ )T, wherein n is the ratio of the number of turns on windings 14 and 8 and wherein V o is maintained constant at nominal mains voltage V o = δ V inom . However, if as a result of an increase or a decrease of the mains voltage V i increases or decreases proportionally therewith, i.e., V i = V i nom + Δ V, the positive portion of V 14 becomes equal to n(V i nom - V o +Δ V) = n [(1 -δ)V i nom +ΔV] = n(0.5 V inom +ΔV) if δ = 0.5 for V i = V i nom. Relatively, this is a variation which is twice as great. For example, if V i nom = 270 V and V o = 135 V, a variation in the mains voltage of from -15 to +10 percent causes a variation of V i of from -40.5 V to +27 V which ranges from -30 to +20 percent of 135 V which is present across winding 8 during the period δ T. The result is that transistor 16 can always be bottomed over a large range of variation. If the signal of FIG. 2b would be applied through a resistor to the base of transistor 16, the base current thereof would have to undergo the same variation while the transistor would already be saturated in case of too low a voltage. In this case it is assumed that transformer 9 is ideal (without loss) and that coil 21 has a small inductance as is explained in the U.S. patent application Ser. No. 737,009 above mentioned. It is therefore found to be desirable to limit the base current of transistor 16.
This may be effected by providing a coil 22 having a large value inductance, approximately 100 μH, between winding 14 and the small coil 21. The variation of said base current i b is shown in FIG. 2c but not to the same scale as the collector current of FIG. 2a. During the conducting interval δ T current i b varies as a linear function of time having a final value of wherein L represents the inductance of coil 22. This not only provides the advantage that this final value is not immediately reached, but it can be shown that variation of this final value as a function of the mains voltage has been reduced, for there applies at nominal mains voltage that: If the mains voltage V i = V i nom +Δ V, then ##SPC1## because V i nom = 2 V o . Thus this variation is equal to that of the mains voltage and is not twice as great.
During switching off, t 2 , of transistor 16 coil 22 must exert no influence and coil 21 must exert influence which is achieved by arranging a diode 23 parallel to coil 22. Furthermore the control circuit of transistor 16 in this example comprises the two diodes 24 and 25 as described in U.S. application Ser. No. 26,497 above referred to, wherein one of these diodes, diode 25 in FIG. 1, must be shunted by a resistor.
The control circuit of transistor 16 may alternatively be formed as is shown in FIG. 4. In fact, it is known that coil 21 may be replaced by the parallel arrangement of a diode 21' and a resistor 21" by which the inverse current can be limited. To separate the path of the inverse current from that of the forward current the parallel arrangement of a the diode 29' and a resistor 29" must then be present. This leads to the circuit arrangement shown in the upper part of FIG. 4. This circuit arrangement may now be simplified if it is noted that diodes 25 and 21' on the one hand and diodes 23 and 29' on the other hand are series-arranged. The result is shown in the lower part of FIG. 4 which, as compared with the circuit arrangement of FIG. 1, employs one coil less and an additional resistor.
FIG. 3 shows possible modifications of the chopper. FIG. 3a shown in a simplified form the circuit arrangement according to FIG. 1 wherein the pulsatory voltage present across the connections of windings 8 has a peak-to-peak amplitude of V i - V o = 0.5 V i for δ = 0.5, As has been stated, the provision of coil 22 gives a relative variation for the base current of transistor 16 which is equal to that of the mains voltage. In the cases according to FIG. 3b, 3c and 3d the peak-to-peak amplitude of the voltage across winding 8 is equal to V i so that the provision of coil 22 results in a relative variation which is equal to half that of the mains voltage which is still more favorable than in the first case.
Transistors of the npn type are used in FIG. 3. If transistors of the pnp type are used, the relevant efficiency diodes must of course be reversed.
In this connection it is to be noted that it is possible to obtain an output voltage V o with the aid of the modifications according to FIGS. 3b, c and d, which voltage is higher than input voltage V i . These modifications may be used in countries such as, for example, the United of America or France where the nominal mains voltage is 117 or 110 V without having to modify the rest of the circuit arrangement.
The above-mentioned remark regarding the sum of the diode currents only applies, however, for the modifications shown in FIGS. 3a and d.
If line output transistor 16 is not simultaneously driven with switching transistor 2, efficiency diodes 7 conducts simultaneously with transistor 16 i.e., during the period which is denoted by δ T in FIGS. 1 and 2b. During that period the output voltage V o of the chopper is stabilized so that the base current of transistor 16 is stabilized without further difficulty. However, a considerable drawback occurs. In FIG. 1 the reference numeral 26 denotes a safety circuit the purpose of which is to safeguard switching transistor 2 when the current supplied to load 11 and/or line deflection circuit 17 becomes to high, which happens because the chopper stops. After a given period output voltage V o is built up again, but gradually which means that the ratio δ is initially small in the order of 0.1. All this is described in U.S. patent No. 3,629,686. The same phenomenon occurs when the display device is switched on. Since δ = 0.1 corresponds to approximately 6 μs when T = 64 μs, efficiency diode 7 conducts in that case for 64 - 6 = 58 μus so that transistor 16 is already switched on at the end of the scan or at a slightly greater ratio δ during the flyback. This would cause an inadmissibly high dissipation. For this reason the simultaneous drive is therefore to be preferred.
The line deflection circuit itself is also safeguarded: in fact, if something goes wrong in the supply, the driver voltage of the line deflection circuit drops out because the switching voltage across the terminals of primary winding 8 is no longer present so that the deflection stops. This particularly happens when switching transistor 2 starts to constitute a short-circuit between emitter and collector with the result that the supply voltage V o for the line deflection circuit in the case of FIG. 1 becomes higher, namely equal to V i . However, the line output transformer is now cut off and is therefore also safe as well as the picture display tube and other parts of the display device which are fed by terminal 15 or the like. However, this only applies to the circuit arrangement according to FIG. 1 or 3a.
Pulse oscillator 6 applies pulses of line frequency to modulator 5. It may be advantageous to have two line frequency generators as already described, to wit pulse oscillator 6 and line oscillator 6' which is present in the picture display device and which is directly synchronized in known manner by line synchronizing pulses 7'. In fact, in this case line oscillator 6' applies a signal of great amplitude and free from interference to pulse oscillator 6. However, it is alternatively possible to combine pulse oscillator 6 and line oscillator 6' in one single oscillator 6" (see FIG. 1) which results in an economy of components. It will be evident that line oscillator 6' and oscillator 6" may alternatively be synchronized indirectly, for example, by means of a phase discriminator. It is to be noted neither pulse oscillator 6, line oscillator 6' and oscillator 6" nor modulator 5 can be fed by the supply described since output voltage V o is still not present when the mains voltage is switched on. Said circuit arrangements must therefore be fed directly from the input terminals. If as described above these circuit arrangements are to be separated from the mains, a small separation transformer can be used whose primary winding is connected between the mains voltage terminals and whose secondary winding is connected to ground at one end and controls a rectifier at the other end.
Capacitor 27 is arranged parallel to efficiency diode 7 so as to reduce the dissipation in switching transistor 2. In fact, if transistor 2 is switched off by the pulsatory control voltage, its collector current decreases and its collector-emitter voltage increases simultaneously so that the dissipated power is not negligible before the collector current has becomes zero. If efficiency diode 7 is shunted by capacitor 27 the increase of the collector-emitter voltage is delayed i.e., this voltage does not assume high values until the collector current has already been reduced. It is true that in that case the dissipation in transistor 2 slightly increases when it is switched on by the pulsatory control voltage but on the other hand since the current flowing through diode 7 has decreased due to the presence of the secondary windings, its inverse current is also reduced when transistor 2 is switched on and hence its dissipation has become smaller. In addition it is advantageous to delay these switching-on and switching-off periods to a slight extent because the switching pulses then contain fewer Fourier components of high frequency which may cause interferences in the picture display device and which may give rise to visible interferences on the screen of the display tube. These interferences occupy a fixed position on the displayed image because the switching frequency is the line frequency which is less disturbing to the viewer. In a practical circuit wherein the line frequency is 15,625 Hz and wherein switching transistor 2 is an experimental type suitable for a maximum of 350 V collector-emitter voltage or 1 A collector current and wherein efficiency diode 7 is of the Philips type BA 148 the capacitance of capacitor 27 is approximately 680 pF whilst the load is 70 W on the primary and 20 W on the secondary side of transformer 9. The collector dissipation upon switching off is 0.3 W (2.5 times smaller than without capacitor 27) and 0.7 W upon switching on.
As is known the so-called pincushion distortion is produced in the picture display tubes having a substantially flat screen and large deflection angles which are currently used. This distortion is especially a problem in color television wherein a raster correction cannot be brought about by magnetic means. The correction of the so-called East-West pincushion distortion i.e., in the horizontal direction on the screen of the picture display tube can be established in an elegant manner with the aid of the circuit arrangement according to the invention. In fact, if the voltage generated by comparison circuit 12 and being applied to modulator 5 for duration-modulating pulsatory voltage 3 is modulated by a parabola voltage 28 of field frequency, pulsatory voltage 3 is also modulated thereby. If the power consumption of the line deflection circuit forms part of the load on the output voltage of the chopper, the signal applied to the line deflection coils is likewise modulated in the same manner. Conditions therefore are that the parabola voltage 28 of field frequency has a polarity such that the envelope of the sawtooth current of line frequency flowing through the line deflection coils has a maximum in the middle of the scan of the field period and that charge capacitor 10 has not too small an impedance for the field frequency. On the other hand the other supply voltages which are generated by the circuit arrangement according to the invention and which might be hampered by this component of field frequency must be smoothed satisfactorily.
A practical embodiment of the described example with the reference numerals given provides an output for the supply of approximately 85 percent at a total load of 90 W, the internal resistance for direct current loads being 1.5 ohms and for pulsatory currents being approximately 10 ohms. In case of a variation of ± 10 percent of the mains voltage, output voltage V o is stable within 0.4 V. Under the nominal circumstances the collector dissipation of switching transistor 2 is approximately 2.5 W.
Since the internal resistance of the supply is so small, it can be used advantageously, for example, at terminal 15 for supplying a class-B audio amplifier which forms part of the display device. Such an amplifier has the known advantages that its dissipation is directly proportional to the amplitude of the sound to be reproduced and that its output is higher than that of a class-A amplifier. On the other hand a class-A amplifier consumes a substantially constant power so that the internal resistance of the supply voltage source is of little importance. However, if this source is highly resistive, the supply voltage is modulated in the case of a class-B amplifier by the audio information when the sound intensity is great which may detrimentally influence other parts of the display device. This drawback is prevented by means of the supply according to the invention.
The 50 Hz ripple voltage which is superimposed on the rectified input voltage V i is compensated by comparison circuit 12 and modulator 5 since this ripple voltage may be considered to be a variation of input voltage V i . A further compensation is obtained by applying a portion of this ripple voltage with suitable polarity to comparison circuit 12. It is then sufficient to have a lower value for the smoothing capacitor which forms part of rectifier circuit 1 (see FIG. 3). The parabola voltage 28 of field frequency originating from the field time base is applied to the same circuit 12 so as to correct the East-West pincushion distortion.
BANG & OLUFSEN BEOVISION 7702 CHASSIS SERIES 77XX 30AX - VIDEO CHROMA PROCESSING WITH TDA3300 (MOTOROLA)
TDA3300 3301 TV COLOR PROCESSOR
This device will accept a PAL or NTSC composite video signal and output the
three color signals, needing only a simple driver amplifier to interface to the pic-
ture tube. The provision of high bandwidth on-screen display inputs makes it
suitable for text display, TV games, cameras, etc. The TDA3301 B has user con»
trol laws, and also a phase shift control which operates in PAL, as well as NTSC.
0 Automatic Black Level Setup
0 Beam Current Limiting
0 Uses Inexpensive 4.43 MHZ to 3.58 MHz Crystal
0 No Oscillator Adjustment Required
0 Three OSD Inputs Plus Fast Blanking Input
0 Four DC, High Impedance User Controls
0 lnterlaces with TDA33030B SECAM Adaptor
0 Single 12 V Supply
0 Low Dissipation, Typically 600 mW
The brilliance control operates by adding a pedestal to the output
signals. The amplitude of the pedestal is controlled by Pin 30.
During CRT beam current sampling a standard pedestal is
substituted, its value being equivalent tothe value given by V30 Nom
Brightness at black level with V30 Nom is given by the sum of three gun
currents at the sampling level, i.e. 3x20 |.1A with 100 k reference
resistors on Pins 16, 19, and 22.
During picture blanking the brilliance pedestal is zero; therefore, the
output voltage during blanking is always the minimum brilliance black
level (Note: Signal channels are also gain blanked).
Chrominance Decoder
The chrominance decoder section of the TDA3301 B
consists of the following blocks:
Phase-locked reference oscillator;
Phase-locked 90 degree servo loop;
U and V axis decoders
ACC detector and identification detector; .
Identification circuits and PAL bistable; .
Color difference filters and matrixes with fast blanking
Circuits.
The major design considerations apart from optimum
performance were:
o A minimum number of factory adjustments,
o A minimum number of external components,
0 Compatibility with SECAM adapter TDA3030B,
0 Low dissipation,
0 Use of a standard 4.433618 Mhz crystal rather
than a 2.0 fc crystal with a divider.
The crystal VCO is of the phase shift variety in which the
frequency is controlled by varying the phase of the feedback.
A great deal of care was taken to ensure that the oscillator loop
gain and the crystal loading impedance were held constant in
order to ensure that the circuit functions well with low grade
crystal (crystals having high magnitude spurious responses
can cause bad phase jitter). lt is also necessary to ensure that
the gain at third harmonic is low enough to ensure absence of
oscillation at this frequency.
It can be seen that the
necessary 1 45°C phase shift is obtained by variable addition
ol two currents I1 and I2 which are then fed into the load
resistance of the crystal tuned circuit R1. Feedback is taken
from the crystal load capacitance which gives a voltage of VF
lagging the crystal current by 90°.
The RC network in the T1 collector causes I1 to lag the
collector current of T1 by 45°.
For SECAM operation, the currents I1 and I2 are added
together in a fixed ratio giving a frequency close to nominal.
When decoding PAL there are two departures from normal
chroma reference regeneration practice:
a) The loop is locked to the burst entering from the PAL
delay line matrix U channel and hence there is no
alternating component. A small improvement in signal
noise ratio is gained but more important is that the loop
filter is not compromised by the 7.8 kHz component
normally required at this point for PAL identification
b) The H/2 switching of the oscillator phase is carried out
before the phase detector. This implies any error signal
from the phase detector is a signal at 7.8 kHz and not dc.
A commutator at the phase detector output also driven
from the PAL bistable coverts this ac signal to a dc prior
to the loop filter. The purpose ot this is that constant
offsets in the phase detector are converted by the
commutator to a signal at 7.8 kHz which is integrated to
zero and does not give a phase error.
When used for decoding NTSC the bistable is inhibited, and
slightly less accurate phasing is achieved; however, as a hue
control is used on NTSC this cannot be considered to be a
serious disadvantage.
90° Reference Generation
To generate the U axis reference a variable all-pass network
is utilized in a servo loop. The output of the all-pass network
is compared with the oscillator output with a phase detector of
which the output is filtered and corrects the operating point of
the variable all»pass network .
As with the reference loop the oscillator signal is taken after
the H/2 phase switch and a commutator inserted before the
filter so that constant phase detector errors are cancelled.
For SECAM operation the loop filter is grounded causing
near zero phase shift so that the two synchronous detectors
work in phase and not in quadralure.
The use of a 4.4 MHz oscillator and a servo loop to generate
the required 90° reference signal allows the use of a standard,
high volume, low cost crystal and gives an extremely accurate
90° which may be easily switched to 0° for decoding AM
SECAM generated by the TDA3030B adapter.
ACC and Identification Detectors
During burst gate time the output components of the U and
also the V demodulators are steered into PNP emitters. One
collector current of each PNP pair is mirrored and balanced
against its twin giving push-pull current sources for driving the
ACC and the identification filter capacitors.
The identification detector is given an internal offset by
making the NPN current mirror emitter resistors unequal. The
resistors are offset by 5% such that the identification detector
pulls up on its filter capacitor with zero signal.
Identification
See Figure 11 for definitions.
Monochrome I1 > I2
PAL ldent. OK I1 < lg
PAL ldent_ X l1 > I2
NTSC I3 > I2
Only for correctly identified PAL signal is the capacitor
voltage held low since I2 is then greater than I1.
For monochrome and incorrectly identified PAL signals l1>l2
hence voltage VC rises with each burst gate pulse.
When V,ef1 is exceeded by 0.7 V Latch 1 is made to conduct
which increases the rate of voltage rise on C. Maximum
current is limited by R1.
When Vref2 is exceeded by 0.7 V then Latch 2 is made to
conduct until C is completely discharged and the current drops
to a value insufficient to hold on Latch 2.
As Latch 2 turns on Latch 1 must turn off.
Latch 2 turning on gives extra trigger pulse to bistable to
correct identification.
The inhibit line on Latch 2 restricts its conduction to alternate
lines as controlled by the bistable. This function allows the
SECAM switching line to inhibit the bistable operation by firing
Latch 2 in the correct phase for SECAM. For NTSC, Latch 2
is fired by a current injected on Pin 6.
lf the voltage on C is greater than 1.4 V, then the saturation
is held down. Only for SECAM/NTSC with Latch 2 on, or
correctly identified PAL, can the saturation control be
anywhere but minimum.
NTSC Switch
NTSC operation is selected when current (I3) is injected into
Pin 6. On the TDA33O1 B this current must be derived
externally by connecting Pin 6 to +12 V via a 27 k resistor (as
on TDA33OOB). For normal PAL operation Pin 40 should be
connected to +12 V and Pin 6 to the filter capacitor.
4 Color Difference Matrixing, Color Killing,
and Chroma Blanking
During picture time the two demodulators feed simple RC
filters with emitter follower outputs. Color killing and blanking
is performed by lifting these outputs to a voltage above the
maximum value that the color difference signal could supply.
The color difference matrixing is performed by two
differential amplifiers, each with one side split to give the
correct values of the -(B-Y) and -(Ft-Y) signals. These are
added to give the (G-Y) signal.
The three color difference signals are then taken to the
virtual grounds of the video output stages together with
luminance signal.
Sandcastle Selection
The TDA3301B may be used with a two level sandcastle
and a separate frame pulse to Pin 28, or with only a three level
(super) sandcastle. In the latter case, a resistor of 1.0 MQ is
necessary from + 12 V to Pin 28 and a 70 pF capacitor from
Pin 28 to ground.
Timing Counter for Sample Control
In order to control beam current sampling at the beginning
of each frame scan, two edge triggered flip-flops are used.
The output K ofthe first flip-flop A is used to clock the second
tlip-flop B. Clocking of A by the burst gate is inhibited by a count
of A.B.
The count sequence can only be initiated by the trailing
edge of the frame pulse. ln order to provide control signals for:
Luma/Chroma blanking
Beam current sampling
On-screen display blanking
Brilliance control
The appropriate flip-flop outputs ar matrixed with sandcastle
and frame signals by an emitter-follower matrix.
Video Output Sections
Each video output stage consists of a feedback amplifier in A further drive current is used to control the DC operating
which the input signal is a current drive to the virtual earth from point; this is derived from the sample and hold stage which
the luminance, color difference and on-screen display stages. samples the beam current after frame flyback.
TDA1170 vertical deflection FRAME DEFLECTION INTEGRATED CIRCUIT
GENERAL DESCRIPTION f The TDA1170 and TDA1270 are monolithic integrated
circuits designed for use in TV vertical deflection systems. They are manufactured using
the Fairchild Planar* process.
Both devices are supplied in the 12-pin plastic power package with the heat sink fins bent
for insertion into the printed circuit board.
The TDA1170 is designed primarily for large and small screen black and white TV
receivers and industrial TV monitors. The TDA1270 is designed primarily for driving
complementary vertical deflection output stages in color TV receivers and industrial
monitors.
APPLICATION INFORMATION (TDA1170)
The vertical oscillator is directly synchronized by the sync pulses (positive or negative); therefore its free
running frequency must be lower than the sync frequency. The use of current feedback causes the yoke
current to be independent of yoke resistance variations due to thermal effects, Therefore no thermistor is
required in series with the yoke. The flyback generator applies a voltage, about twice the supply voltage, to
the yoke. This produces a short flyback time together with a high useful power to dissipated power
ratio.
1. A transformerless output vertical deflection circuit, comprising a vertical oscillator circuit for generating a vertical pulse train in response to vertical synchronizing pulses applied thereto, a sawtooth signal generator for generating a series of sawtooth signals, each cycle of said sawtooth signal including a pulse component, a vertical output circuit coupled to said sawtooth generator for amplifying said sawtooth signal including said pulse component and loading a vertical deflection coil, and stabilizing means connected between said vertical oscillator and said sawtooth signal generator for varying the width of the pulse component which is to be fed to said vertical output circuit in response to the average level of DC output voltage fed from the vertical output circuit. 2. A transformerless output vertical deflection circuit claimed in claim 1, wherein said stabilizing means comprises a control circuit means for receiving a series of pulses from the vertical oscillator and a feedback signal from the vertical output circuit and for varying the width of the pulse which is to be fed to the vertical output circuit in response to a DC control signal proportional to the width of the pulse component included in the vertical output signal and smoothing circuit means connected between said vertical output circuit and said stabalizing means for smoothing said feedback signal. 3. A transformerless output vertical deflection circuit claimed in claim 2, wherein said control circuit comprises a charging capacitor which is parallel to a transistor, said transistor being switched on in response to pulses fed from the vertical oscillator wherein said capacitor is charged by the voltage fed from said smoothing circuit, and discharged in response to conduction of the transistor, a differential amplifier circuit which receives the voltage on said capacitor and a fixed voltage, and a gating circuit for producing a pulse which has a width equal to the difference between the width of the pulse fed from the vertical oscillator circuit and the width of pulse fed from the differential amplifier circuit. 4. A transformerless output vertical deflection circuit claimed in claim 2, wherein said control circuit comprises a capacitor which is charged by a fixed power source and is discharged by means of a switching transistor operated by the pulses fed from the vertical oscillator circuit and a differential amplifier circuit receiving the voltage on the capacitor and the output of said smoothing circuit. 5. A transformable output vertical deflection circuit comprising a vertical oscillator for generating a vertical pulse train in response to vertical synchronizing pulses applied thereto, a sawtooth signal generator for generating a series of sawtooth signals each cycle of said sawtooth signal including a pulse component, a vertical output circuit for amplifying said sawtooth signal including said pulse component and loading a vertical deflection coil, and pulse stabilizing means coupled between the vertical oscillator circuit a
nd the sawtooth signal generator, said stabilizing means comprising a capacitor which is charged by a fixed power source and discharged by means of a discharging means operated in response to the vertical pulse fed from the vertical oscillator, a circuit means for generating a train of output pulses each starting at the time when the voltage appearing on the capacitor exceeds a predetermined value and terminating in synchronism with termination of the pulse fed from the vertical oscillator, and gating means for generating pulses having a width equal to the difference between the width of the pulse fed from the vertical oscillator and the width of the output pulse of the circuit means. 6. A transformerless output vertical deflection circuit, comprising a vertical oscillator circuit for generating a vertical pulse train in response to vertical synchronizing pulses applied thereto, a sawtooth signal generator for generating a series of sawtooth signals, each cycle of said sawtooth signal including a pulse component, a vertical output circuit coupled to said sawtooth generator for amplifying said sawtooth signal including said pulse component and loading a vertical deflection coil, and stabilizing means, comprising a control circuit connected between said vertical output circuit and said vertical oscillator circuit for varying the width of each pulse produced by the vertical oscillator circuit in response to a DC control signal having a value corresponding to the width of the pulse component applied to the vertical deflection coil of the vertical output circuit for controlling the pulse width of the output of said vertical oscillator circuit and thereby the pulse width of said pulse component.
The present invention relates to a vertical deflection circuit for use in a television receiver and, more particularly, to a vertical deflection circuit of a type wherein no vertical output transformer is employed. This type of vertical deflection circuit with no output transformer is generally referred to as an OTL (Output Transformerless) type vertical deflection circuit.
It is known that variation of the pulse width of the flyback pulse produced in a vertical output stage of the vertical deflection circuit is the cause in the raster on the television picture tube, of a white bar, flicker, jitter, line crowding and/or other raster disorders. In addition thereto, in the vertical deflection output circuit where the output stage is composed of a single-ended push-pull amplifier having a vertical output transistor, an excessive load is often imposed on the output transistor and, in an extreme case, the output transistor is destroyed.
BANG & OLUFSEN BEOVISION 7702 CHASSIS SERIES 77XX 30AX Television receiver including a teletext decoder circuit :
In a teletext decoder circuit the character generator supplies picture elements at a rate of nominally approximately 6 MHz under the control of display pulses occurring at the same rate. These display pulses are derived from reference clock pulses which occur at a rate which is not a rational multiple of 6 MHz. The character generator comprises a generator circuit which receives the reference clock pulses and selects, from each series of N reference clock pulses, as many pulses as correspond to the number of horizontal picture elements constituting a character, while the time interval of N reference clock pulses corresponds to the desired width of the characters to be displayed. The character generator supplies picture elements of distinct length, while the length of a picture element is dependent on the ordinal number of this picture element in the character.
1. A receiver for television signal s including a teletext decoder circuit for decoding teletext signals constituted by character codes which are transmitted in the television signal, and comprising:
a video input circuit receiving the television signal and converting it into a serial data flow;
an acquisition circuit for receiving the serial data flow supplied by the video input circuit and selecting that part therefrom which corresponds to the teletext page described by the viewer;
a character generator comprising:
a memory medium addressed by the character codes which together represent the teletext page desired by the user and which in response to each character code successively supply m2 series of m1 simultaneously occurring character picture element codes each indicating wether a corresponding picture element of the character must be displayed in the foreground colour or in the background colour;
a generator circuit receiving a series of reference clock pulses and deriving display clock pulses therefrom;
a converter circuit receiving each series of m1 simultaneously occurring character picture element codes as well as the display clock pulses for supplying the m1 character picture element codes of a series one after the other and at the display clock pulse rate;
a display control circuit receiving the serial character picture element codes and converting each into an R, a G and a B signal for the relevant picture element of the character to be displayed;
characterized in that
the generator circuit is adapted to partition the series of reference clock pulses applied thereto into groups of N reference clock pulses each, in which N reference clock pulse periods correspond to the desired width of a character to be displayed, and to select from each such group m1 clock pulse to function as display clock pulses;
the converter circuit is adapted to supply each character picture element code during a period which is dependent on the ordinal number of the character picture element code in the series of m1 character picture element codes.
2. A character generator for use in a receiver teletext claim 1, comprising:
a memory medium which is addressable by character codes and successively applies m2 series of m1 simultaneously occurring character picture element codes in response to a character code applied as an address thereto, each character picture element code indicating whether a corresponding picture element of the character must be displayed in the foreground colour or in the background colour;
a generator circuit receiving a series of reference clock pulses and deriving display clock pulses therefrom;
a converter circuit receiving each series of m1 simultaneously occurring character picture element codes and the display clock pulses for supplying the m1 character picture element codes of the series one after the other at the display clock pulse rate;
a display control circuit receiving the serial character picture element codes and converting each into an R, a G and a B signal for the relevant picture element of the character to be displayed; characterized in that
the generator circuit is adapted to partition the series of reference clock pulses applied thereto into groups of N reference clock pulses each, in which N reference clock pulse periods correspond to the desired width of a character to be displayed, and to select from each such group m1 clock pulses to function as display clock pulses;
the converter circuit is adapted to supply each character picture element code during a period which is dependent on the ordinal number of the character picture element code in the series of m1 character picture element codes.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention generally relates to receivers for television signals and more particularly to receivers including teletext decoders for use in a teletext transmission system.
2. Description of the Prior Art
As is generally known, in a teletext transmission system, a number of pages is transmitted from a transmitter to the receiver in a predetermined cyclic sequence. Such a page comprises a plurality of lines and each line comprises a plurality of alphanumerical characters. A character code is assigned to each of these characters and all character codes are transmitted in those (or a number of those) television lines which are not used for the transmission of video signals. These television lines are usually referred to as data lines.
Nowadays the teletext transmission system is based on the standard known as "World System Teletext", abbreviates WST. According to this standard each page has 24 lines and each line comprises 40 characters. Furthermore each data line comprises, inter alia, a line number (in a binary form) and the 40 character codes of the 40 characters of that line.
A receiver which is suitable for use in such a teletext transmission system includes a teletext decoder enabling a user to select a predetermined page for display on a screen. As is indicated in, for example, Reference 1, a teletext decoder comprises, inter alia, a video input circuit (VIP) which receives the received television signal and converts it into a serial data flow. This flow is subsequently applied to an acquisition circuit which selects those data which are required for building up the page desired by the user. The 40 character codes of each teletext line are stored in a page memory which at a given moment thus comprises all character codes of the desired page. These character codes are subsequently applied one after the other and line by line to a character generator which supplies such output signals that the said characters become visible when signals are applied to a display.
For the purpose of display each character is considered as a matrix of m 1 ×m 2 picture elements which are displayed row by row on the screen. Each picture element corresponds to a line section having a predetermined length (measured with respect to time); for example, qμsec. Since each line of a page comprises 40 characters and each character has a width of m 1 qμsec, each line has a length of 40 m 1 μsec. In practice a length of approximately 36 to 44 μsec appears to be a good choice. In the teletext decoder described in Reference 1 line length of 40 μsec and a character width of 1 μsec at m 1 =6 have been chosen.
The central part of the character generator is constituted by a memory which is sub-divided into a number of submemories, for example, one for each character. Each sub-memory then comprises m 1 ×m 2 memory locations each corresponding to a picture element and the contents of each memory location define whether the relevant picture element must be displayed in the so-called foreground colour or in the so-called background colour. The contents of such a code memory location will be referred to as character picture element code. This memory is each time addressed by a character code and a row code. The character code selects the sub-memory and the row code selects the row of m 1 memory elements whose contents are desired. The memory thus supplies groups of m simultaneously occurring character picture element codes which are applied to a converter circuit. This converter circuit usually includes a buffer circuit for temporarily storing the m 1 substantially presented character picture element codes. It is controlled by display clock pulses occurring at a given rate and being supplied by a generator circuit. It also supplies the m 1 character picture element codes, which are stored in the buffer circuit, one after the other and at a rate of the display clock pulses. The serial character picture element codes thus obtained are applied to a display control circuit converting each character picture element code into an R, a G and a B signal value for the relevant picture element, which signal values are applied to the display device (for example, display tube).
The frequency f d at which the display clock pulses occur directly determines the length of a picture element and hence the character width. In the above-mentioned case in which m 1 =6 and in which a character width of 1 μsec is chosen, this means that f d =6 MHz. A change in the rate of the display clock pulses involves a change in the length of a line of the page to be displayed (now 40 μsec). In practice a small deviation of, for example, not more than 5% appears to be acceptable. For generating the display clock pulses the generator circuit receives reference clock pulses. In the decoder circuit described in Reference 1 these reference clock pulses are also supplied at a rate of 6 MHz, more specifically by an oscillator specially provided for this purpose.
OBJECT AND SUMMARY OF THE INVENTION
A particular object of the invention is to provide a teletext decoder circuit which does not include a separate 6 MHz oscillator but in which for other reasons clock pulses, which are already present in the television receiver, can be used as reference clock pulses, which reference clock pulses generally do not occur at a rate which is a rational multiple of the rate at which the display clock pulses must occur.
According to the invention,
the generator circuit is adapted to partition the series of reference clock pulses applied thereto into groups of N reference clock pulses each, in which N clock pulse periods correspond to the desired width of a character to be displayed, and to select of each such group m 1 clockpulses to function as display clock pulses;
the converter circuit is adapted to supply each character picture element code during a period which is dependent on the ordinal number of the character picture element code in the series of m 1 character picture element codes.
The invention has resulted from research into teletext decoder circuits for use in the field of digital video signal processing in which a 13.5 MHz clock generator is provided for sampling the video signal. The 13.5 MHz clock pulses supplied by this clock generator are now used as reference clock pulses. The generator circuit partitions these reference clock pulses into groups of N clock pulses periods each. The width of such a group is equal to the desired character width. Since a character comprises rows of m 1 picture elements, m 1 reference clock pulses are selected from such a group which clock pulses are distributed over this group as regularly as possible. Since the mutual distance between the display clock pulses thus obtained is not constantly the same, further measures will have to be taken to prevent undesired gaps from occurring between successive picture elements when a character is displayed. Since the length of a picture element is determined by the period during which the converter circuit supplies a given character picture element code, this period has been rendered dependent on the ordinal number of the character picture element code in the series of m 1 character picture element codes.
REFERENCES
1. Computer-controlled teletext, J. R. Kinghorn; Electronic Components and Applications, Vol. 6, No. 1, 1984, pages 15-29.
2. Video and associated systems, Bipolar, MOS; Types MAB 8031 AH to TDA 1521: Philips' Data Handbook, Integrated circuits, Book ICO2a 1986, pages 374,375.
3. Bipolar IC's for video equipment; Philips' Data Handbook, Integrated Circuits Part 2, January 1983.
4. IC' for digital systems in radio, audio and video equipment, Philips' Data Handbook, Integrated Circuits Part 3, September 1982.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 shows the general structure of a television receiver including a teletext decoder circuit;
FIG. 2 shows different matrices of picture elements constituting a character;
FIG. 3 shows diagrammatically the general structure of a character generator;
FIG. 4 shows an embodiment of a converter circuit and a generator circuit for use in the character generator shown in FIG. 3, and
FIG. 5 shows some time diagrams to explain its operation;
FIG. 6 shows another embodiment of a converter circuit and a generator circuit for use in the character generator shown in FIG. 3, and
FIG. 7 shows some time diagrams to explain its operation;
FIG. 8 shows a modification of the converter circuit shown in FIG. 6, adapted to round the characters.
EXPLANATION OF THE INVENTION
General structure of a TV receiver
FIG. 1 shows diagrammatically the general structure of a colour television receiver. It has an antenna input 1 connected to an antenna 2 receiving a television signal modulated on a high-frequency carrier, which signal is processed in a plurality of processing circuits. More particularly, it is applied to a tuning circuit 23 (tuner or channel selector). This circuit receives a band selection voltage V B in order to enable the receiver to be tuned to a frequency within one of the frequency bands VHF1, VHF2, UHF, etc. The tuning circuit also receives a tuning voltage V T with which the receiver is tuned to the desired frequency within the selected frequency band.
This tuning circuit 3 supplies an oscillator signal having a frequency of f OSC on the one hand and an intermediate frequency video signal IF on the other hand. The latter signal is applied to an intermediate frequency amplification and demodulation circuit 4 supplying a baseband composite video signal CVBS. The Philips IC TDA 2540 described in Reference 3 can be used for this circuit 4.
The signal CVBS thus obtained is also applied to a colour decoder circuit 5. this circuit supplies the three primary colour signals R', G' and B' which in their turn are applied via an amplifier circuit 6 to a display device 7 in the form of a display tube for the display of broadcasts on a display screen 8. In the colour decoder circuit 5 colour saturation, contrast and brightness are influenced by means of control signals ANL. The circuit also receives an additional set of primary colour signals R, G and B and a switching signal BLK (blanking) with which the primary colour signals R', G' and B' can be replaced by the signals R, G and B of the additional set of primary colour signals. A Philips IC of the TDA 356X family described in Reference 3 can be used for this circuit 5.
The video signal CVBS is also applied to a teletext decoder circuit 9. This circuit comprises a video input circuit 91 which receives the video signal CVBS and converts it into a serial data flow. This flow is applied to a circuit 92 which will be referred to as teletext acquisition and control circuit (abbreviated TAC circuit). This circuit selects that part of the data applied thereto which corresponds to the teletext page desired by the viewer. The character codes defined by these data are stored in a memory 93 which is generally referred to as page memory and are applied from this memory to a character generator 94 supplying an R, a G and a B signal for each picture element of the screen 8. It is to be noted that this character generator 94 also supplies the switching signal BLK in this embodiment. As is shown in the Figure, the teletext acquisition and control circuit 92, the page memory 93 and the character generator 94 are controlled by a control circuit 95 which receives reference clock pulses with a frequency f o from a reference clock oscillator 10. The control circuit 95 has such a structure that it supplies the same reference clock pulses from its output 951 with a phase which may be slightly shifted with respect to the reference clock pulses supplied by the clock pulse oscillator 10 itself. The reference clock pulses occurring at this output 951 will be denoted by TR.
The Philips IC SAA 5030 may be used as video input circuits 91, the Philips IC SAA 5040 may be used as teletext acquisition and control circuit, a 1K8 RAM may be used as page memory, a modified version of the Philips IC SAA 5050 may be used as character generator 94 and a modified version of the Philips IC SAA 5020 may be used as control circuit 95, the obvious modification being a result of the fact that this IC is originally intended to receive reference clock pulses at a rate of 6 MHz for which 13.5 MHz has now been taken.
The acquisition and control circuit 92 is also connected to a bus system 11. A control circuit 12 in the form of a microcomputer, an interface circuit 13 and a non-volatile memory medium 14 are also connected to this system. The interface circuit 13 supplies the said band selection voltage V B , the tuning voltage V T and the control signals ANL for controlling the analog functions of contrast, brightness and colour saturation. It receives an oscillator signal at the frequency f' OSC which is derived by means of a frequency divider 15, a dividing factor of which is 256, from the oscillator signal at the frequency f OSC which is supplied by the tuning circuit 3. Tuning circuit 3, frequency divider 15 and interface circuit 13 combined constitute a frequency synthesis circuit. The Philips IC SAB 3035 known under the name of CITAC (Computer Interface for Tuning and Analog Control) and described in Reference 4 can be used as interface circuit 13. A specimen from the MAB 84XX family, manufactured by Philips, can be used as a microcomputer.
The memory medium 14 is used, for example, for storing tuning data of a plurality of preselected transmitter stations (or programs). When such tuning data are applied to the interface circuit 13 under the control of the microcomputer 12, this circuit supplies a given band selection voltage V B and a given tuning voltage V T so that the receiver is tuned to the desired transmitter.
For operating this television receiver an operating system is provided in the form of a remote control system comprising a hand-held apparatus 16 and a local receiver 17. This receiver 17 has an output which is connected to an input (usually the "interrupt" input) of the microcomputer 12. It may be constituted by the Philips IC TDB 2033 described in Reference 4 and is then intended for receiving infrared signals which are transmitted by the hand-held apparatus 16.
The hand-held apparatus 16 comprises an operating panel 161 with a plurality of figure keys denoted by the FIGS. 0 to 9 inclusive, a colour saturation key SAT, a brightness key BRI, a volume key VOL, and a teletext key TXT. These keys are coupled to a transmitter circuit 162 for which, for example, the Philips IC SAA 3004, which has extensively been described in Reference 4, can be used. When a key is depressed, a code which is specific of that key is generated by the transmitter circuit 162, which code is transferred via an infrared carrier to the local receiver 17, demodulated in this receiver and subsequently presented to the microcomputer 12. This microcomputer thus receiv
es operating instructions and activates, via the bus system 11, one of the circuits connected thereto. It is to be noted that an operating instruction may be a single instruction, that is to say, it is complete after depressing only one key. It may also be multiple, that is to say, it is not complete until two or more keys have been depressed. This situation occurs, for example, when the receiver is operating in the teletext mode. Operation of figure keys then only yields a complete operating instruction when, for example, three figure keys have been depressed. As is known, such a combination results in the page number of the desired teletext page.
The character generator
As already stated, a character is a matrix comprising m 2 rows of m 1 picture elements each. Each picture element corresponds to a line section of a predetermined length (measured with respect to time); for example, q/μsec. Such a matrix is indicated at A in FIG. 2 for m 1 =6 and m 2 =10. More particularly this is the matrix of a dummy character. The character for the letter A is indicated at B in the same FIG. 2. It is to be noted that the forty characters constituting a line of teletext page are contiguous to one another without any interspace. The sixth column of the matrix then ensures the required spacing between the successive letters and figures.
FIG. 3 shows diagrammatically the general structure of the character generator described in Reference 2 and adapted to supply a set of R, G and B signals for each picture element of the character. This character generator comprises a buffer 940 which receives the character codes from memory 93 (see FIG. 1). These character codes address a sub-memory in a memory medium 941, which sub-memory consists of m 1 ×m 2 memory elements each comprising a character picture element code. Each m 1 ×m 2 char
acter picture element code corresponds to a picture element of the character and defines, as already stated, whether the relevation picture element must be displayed in the so-called foreground colour or in the so-called background colour. Such a character picture element code has the logic value "0" or "1". A "0" means that the corresponding picture element must be displayed in the background colour (for example, white). The "1" means that the corresponding picture element must be displayed in the foreground colour (for example, black or blue). At C in FIG. 2 there is indicated, the contents of the sub-memory for the character shown at B in FIG. 2.
The addressed sub-memory is read now by row under the control of a character row signal LOSE. More particularly, all first rows are read of the sub-memories of the forty characters of a teletext line, subsequently all second rows are read, then all third rows are read and so forth until finally all tenth rows are read.
The six character element codes of a row will hereinafter be referred to as CH(1), CH(2), . . . CH(6). They are made available in parallel by the memory medium 941 and are applied to a converter circuit 942 operating as a parallel-series converter. In addition to the six character picture element codes it receives display clock pulses DCL and applies these six character picture element codes one by one at the rate of the display clock pulses to a display control circuit 943 which converts each character picture element code into a set of R, G, B signals.
The display clock pulses DCL and the character row signal LOSE are supplied in known manner (see Reference 2, page 391) by a generator circuit 944 which receives the reference clock pulses TR from the control circuit 95 (see FIG. 1), which reference clock pulses have a rate f 0 . In the character generator described in Reference 2, page 391, f 0 is 6 MHz and the display clock pulses DCL occur at the same rate. The converter circuit thus supplies the separate character picture element codes at a rate of 6 MHz. The picture elements shown at A and B therefore have a length of 1/6 μsec each and a character thus has a width of 1 μsec.
When the rate of the reference clock pulses increases, the rate of the display clock pulses also increases and the character width decreases. Without changing the character width the above-described character generator can also be used without any essential changes if the rate of the reference clock pulses is an integral multiple of 6 MHz. In that case the desired display clock pulses can e derived from the reference clock pulses by means of a divider circuit with an integral dividing number. However, there is a complication if f 0 is not a rational multiple of 6 MHz, for example, if f 0 =13.5 MHz and each character nevertheless must have a width of substantially 1 μsec. Two generator circuits and a plurality of converter circuits suitable for use in the character generator shown in FIG. 3 and withstanding the above-mentioned complication will be described hereinafter.
FIG. 4 shows an embodiment of the generator circuit 944 and the converter circuit 942. The reference clock pulses TR are assumed to occur at a rate of 13.5 MHz. To derive the desired display clock pulses from these reference clock pulses, the generator circuit 944 comprises a modulo-N-counter circuit 9441 which receives the 13.5 MHz reference clock pulses TR indicated at A in FIG. 5. The quantity N is chosen to be such that N clock pulse periods of the reference clock pulses substantially correspond to the desired character width of, for example, 1 μsec. This is the case for N=14, which yields a character width of 1.04 μsec.
An encoding network 9442 comprising two output lines 9443 and 9444 is connected to this modulo-N-counter circuit 9441. This encoding network 9442 each time supplies a display clock pulse in response to the first, the third, the sixth, the eighth, the eleventh and the thirteenth reference clock pulse in a group of fourteen reference clock pulses. More particularly the display clock pulse, which is obtained each time in response to the first reference clock pulse of a group, is applied to the output line 9443, whilst the other display clock pulses are applied to the output line 9444. Thus, the pulse series shown at B and C in FIG. 5 occur at these output lines 9443 and 9444, respectively.
The converter circuit 942 is constituted by a shift register circuit 9420 comprising six shift register elements each being suitable for storing a character picture element code CH(.) which is supplied by the memory medium 941 (see FIG. 3). This shift register circuit 9420 has a load pulse input 9421 and a shift pulse input 9422. The load pulse input 9421 is connected to the output line 9443 of the encoding network 9442 and thus receives the display clock pulses indicated at B in FIG. 5. The shift pulse input 9422 is connected to the output line 9444 of the encoding network 9442 and thus receives the display clock pulses indicated at C in FIG. 5.
This converter circuit operates as follows. Whenever a display clock pulse occurs at the load pulse input 9421, the six character picture element codes CH(.) are loaded into the shift register circuit 9420. The first character picture element code CH(1) thereby becomes immediately available at the output. The contents of the shift register el
ements are shifted one position in the direction of the output by each display clock pulse at the shift pulse input 9422.
Since the display clock pulses occur at mutually unequal distances, the time interval during which a character picture element code is available at the output of the shift register circuit is longer for the one character picture element code than for the other. This is shown in the time diagrams D of FIG. 5. More particularly the diagrams show for each character picture element code CH(.) during which reference clock pulse periods the code is available at the output of the shift register circuit. The result is that the picture elements from which the character is built up upon display also have unequal lengths as is indicated at D and E in FIG. 2.
The same character display is obtained by implementing the converter circuit 942 and the generator circuit 944 in the way shown in FIG. 6. The generator circuit 944 again comprises the modulo-N-counter circuit 9441 with N=14 which receives the 13.5 MHz reference clock pulses TR shown at A in FIG. 7. An encoding network 9445 is also connected to this counter circuit, which network now comprises six output lines 9446(.). This encoding network 9445 again supplies a display clock pulse in response to the first, the third, the sixth, the eighth, the eleventh and the thirteenth reference clock pulse of a group of fourteen reference clock pulses, which display clock pulses are applied to the respective output lines 9446(1), . . . , 9446(6). Thus, the pulse series indicated at B, C, D, E, F and G in FIG. 7 occur at these outputs.
The converter circuit 942 has six latches 9423(.) each adapted to store a character picture element code CH(.). The outputs of these latches are connected to inputs of respective AND gate circuits 9424(.). Their outputs are connected to inputs of an OR gate circuit 9425. The AND gate circuit is 9424(.) are controlled by the control signals S(1) to S(6), respectively, which are derived by means of a pulse widening circuit 9426 from the display clock pulses occurring at the output lines 9446(.) of the encoding network 9445 and which are also shown in FIG. 7. Such a control signal S(i) determines how long the character picture element code CH(i) is presented to the output of the OR gate circuit 9425 and hence determines the length of the different picture elements of the character on the display screen.
As is shown in FIG. 6, the pulse widening circuit 9426 may be constituted by a plurality of JK flip-flops 9426(.) which are connected to the output lines of the encoding network 944, in the manner shown in the Figure. It is to be noted that the function of the pulse widening circuit 9426 may also be included in the encoding network 9445. In that case this function may be realized in a different manner.
In the above-described embodiments of the converter circuit 942 and the generator circuit 944 the character generator supplies exactly contiguous picture elements on the display screen. This means that the one picture elements begins immediately after the previous picture element has ended. The result is that round and diagonal shapes become vague. It is therefore common practice to realize a rounding for such shapes. This rounding can be realized with the converter circuit shown in FIGS. 4 and 6
by ensuring that two consecutive picture elements partly overlap each other. This is realized in the converter circuit shown in FIG. 4 by means of a rounding circuit 9427 which receives the character picture element codes occurring at the output of the shift register circuit 9420. This rounding circuit 9427 comprises an OR gate 9427(1) and a D flip-flop 9427(2). The T input of this flip-flop receives the clock pulses shown at E in FIG. 5, which pulses are derived from the reference clock pulses TR by means of a delay circuit 9427(3). This circuit has a delay time t 0 for which a value in the time diagram indicated at E in FIG. 5 is chosen which corresponds to half a clock pulse period of the reference cock pulses. The character picture element codes supplied by the shift register circuit 9420 are now applied directly and via the D flip-flop 9427(2) to the OR gate which thereby supplies the six character picture element codes CH(.) in the time intervals as indicated at F in FIG. 5. The result of this measure for the display of the character with the letter A is shown at F in FIG. 2.
The same rounding effect can be realized by means of the converter circuit shown in FIG. 6, namely by providin
g it with a rounding circuit as well. This is shown in FIG. 8. In this FIG. 8 the elements corresponding to those in FIG. 6 h
ave the same reference numerals. The converter circuit 942 shown in FIG. 8 differs from the circuit shown in FIG. 6 in that the said rounding circuit denoted by the reference numeral 9428 is incorporated between the pulse widening circuit 9426 and the AND gate circuits 9424(.). More particularly this rounding circuit is a pluriform version of the rounding circuit 9427 shown in FIG. 4 and is constituted by six D flip-flops 9428(.) and six OR gates 9429(.). These OR gates receive the respective control signals S(1) to S(6) directly and via the D flip-flops. The T inputs of these D flip-flops again receive the version of the reference clock pulses delayed over half a reference clock pulse period by means of the delay circuit 94210. This rounding circuit thus supplies the control signals S'(.) shown in FIG. 7.
Philips Data Handbook, Electronic Components and Materials "Integrated Circuits: Part 3, Sep. 1982: ICs for Digital Systems in Radio, Audio, and Video Equipment: SAA5020 Series", pp. 1-10.
Philips Data Handbook, Electronic Components and Materials "Integrated Circuits: Book IC02a, 1986: Video and Associated Systems: Bipolar, MOS: Types MAB8031AH to TDA1521", pp. 374-375.
F. J. R. Kinghorn, "Computer Controlled Teletext"; Electronic Components and Applications; vol. 6, No. 1, 1984, pp. 15-29.
"World System Teletext Technical Specification", Revised Mar. 1985, pp. 1-10 and 38-41.
Philips Data Handbook, Electronic Components and Materials; "Integrated Circuits, Part 2: Jan. 1983: Bipolar ICs for Video Equipment: TDA2540, TDA2540Q"; pp. 1-8.
Philips Data Handbook, Electronic Components and Materials; "Integrated Circuits: Part 2: Jan. 1983: Bipolar ICs for Video Equipment: TDA 3562A"; pp. 1-16.
Philips Data Handbook, Electronic Components and Materials "Integrated Circuits: Part 3, Sep. 1982: IC's for Digital Systems in Radio, Audio, and Video Equipment: SAA3004"; pp. 1-10.
Philips Data Handbook, Electronic Components and Materials, "Integrated Circuits: Part 3, Sep. 1982: Ics for Digital Systems in Radio, Audio, and Video Equipment: SAB3035", pp. 1-4.
Philips Data Handbook, Electronic Components and Materials "Integrated Circuits: Part 3, Sep. 1982: ICs for Digital Systems in Radio, Audio and Video Equipment: TDB2033", pp. 1-9.
BANG & OLUFSEN BEOVISION 7702 CHASSIS SERIES 77XX 30AX Teletext / Videotext Error correction circuit using character probability :
An error correction circuit in a television receiver for receiving, for example, Teletext information, Viewdata information or information of comparable systems. The codes representing symbol information received by the receiver are classified into one out of two or more classes in dependence on the frequency of their occurrence, this classification being an indication of the extent to which it is probable that a received code is correctly received.
In FIG. 1, a picture text television receiver has a receiving section, audio and video amplifiers 4 and 9 and a picture tube 10, 11. A text decoder 21 receives symbol information which is stored in a store 25 for display. An error detector circuit 40 including a comparison circuit 43 and two parity circuits 41 and 42, and checks for parity between newly received and already stored symbol information. A reliability circuit 60 is also included.
1. An error correction circuit for a receiving device for receiving digitally transmitted symbol information, the transmission of this information being repeated one or more times, the receiving device having a decoding circuit for decoding the received information, an information store coupled to said decoding circuit for storing the information, a circuit for generating synchronizing signals and a video converter circuit coupled to said information store and said generating circuit for converting information and synchronizing signals into a composite video signal for application to a standard television receiver, a symbol address in the information store corresponding with a symbol location on a television picture screen, a symbol location being a portion of a text line which is displayed with a number of video lines greater than one, the error correction circuit being coupled to said decoding circuit and said information store and including means coupled between said decoding circuit and said information store for checking newly received symbol information against symbol information stored in the information store for the corresponding symbol location, a write-switch having one input coupled to said decoding circuit and an output coupled to said information store, and a write-setting circuit, coupled to another input of said write-switch, which determines whether the newly received information is written or not written into the information store, said write-setting circit having an input coupled to said checking means whereby the results of said checking are a factor in the setting of said write-switch by said write-setting circuit, characterized in that the error correction circuit further comprises a classification circuit coupled to the output of said decoding circuit for classifying a newly received and decoded symbol in one of at least two classes on the basis of the probability of occurrence of the newly received symbol, the input of the classification circuit being coupled to another input of the write-setting circuit. 2. An error correction circuit for a receiving device as claimed in claim 1, characterized in that the write-setting circuit includes a reliability circuit and the information store comprises an additional storage element for each symbol address in the information store for storing a reliability bit associated with that symbol address, inputs of the reliability circuit being coupled to the classification circuit and to the information store for accessing the additional storage elements, for determining, from the additional storage element corresponding with the symbol address position of newly received symbol information, a new reliability bit, an output of the reliability circuit being coupled back to the information store for writing this new reliability bit into the corresponding additional storage element when the reliability bit for this symbol address changes its value. 3. An error correction circuit for a receiving device as claimed in claim 2, characterized in that the checking means comprises a comparison circuit for bit-wise comparing a newly received and decoded symbol with a symbol read from an address of the information store, this address corresponding with the symbol location, a comparison output of the comparison circuit being coupled to a further input of the reliability circuit. 4. An error correction circuit for a receiving device as claimed in any one of the preceding claims, characterized in that the classification circuit comprises a parity circuit for classifying newly received symbols for respective particular symbol locations into one of two classes which correspond to an even and an odd parity respectively, of the newly received information, and for classifying symbol information already stored in the corresponding symbol addresses in the information store. 5. An error correction circuit for a receiving device as claimed in claim 2, characterized in that the reliability circuit comprises a reliability flipflop and a reliability read circuit for this flipflop, an output of which also constitutes the output of the reliability circuit. 6. An error correction circuit for a receiving device as claimed in claim 1, characterized in that the error correction circuit comprises a second classification circuit, coupled between said other classification circuit and said write-setting circuit and having inputs coupled to said information store, for classifying a symbol read from the information store. 7. An error correction circuit for a receiving device as claimed in claim 1 characterized in that the information store comprises, for each symbol address in the information store, at least one further storage element for storing the classification associated with the symbol for that symbol address.
You can see the complexity of the tellye even only from the wiring around it.
The 77XX models included a microprocessor controlled “search and store” tuning system that offered a number of advantages over the bank of tuning knobs that the 33XX models used. 32 programmes could be stored, tuning was automatic and could be operated from either the set or the remote control. In the case where the channel number was known, this could be entered directly, making the tuning “instant”.
Teletext was a standard fitting for the 1984 season but it reverted to being an option for the rest of the production run. A single A/V socket (DIN A/V standard) was standard though a dual A/V interface could be specified, providing an extra DIN A/V socket (SCART in later versions), at extra cost.
BANG & OLUFSEN BEOVISION 7702 CHASSIS SERIES 77XX 30AX Horizontal deflection output circuit:
A horizontal deflection output circuit, such as used in a TV receiver or a display device, includes a series circuit composed of a ringing preventing resistor and a one-way switching element connected in parallel with a linearity correcting coil. That one-way switching element is turned on at the beginning of a horizontal scanning period to feed a current to the ringing preventing resistor but is turned off in the vicinity of a fly-back period to block the flow of the current to the ringing preventing resistor. Thus, the power loss due to the current flowing through the ringing preventing resistor for the fly-back period can be reduced according to the present invention.
a switching element;
a resonant capacitor connected in parallel with said switching element; and
a first series circuit connected in parallel with said switching element and including a horizontal deflection coil and a linearity correcting coil,
wherein the improvement comprises:
a second series circuit connected in parallel with said linearity correcting coil, said second series circuit comprising load means for damping resonance energy in said first series circuit and current control means for limiting the current flow through said load means to the first half of a horizontal scanning period and including a one-way switching element which turns on for a first half of said horizontal scanning period and turns off for the last half of the horizontal scanning period and for a fly-back pulse period, thereby limiting current flow through said load means to the first half of said horizontal scanning period.
2. A horizontal deflection output circuit according to claim 1, wherein said load means includes a resistor. 3. A horizontal deflection output circuit according to claim 2, wherein a capacitor is connected in parallel with said linearity correcting coil. 4. A horizontal deflection output circuit according to claim 2, wherein said one-way switching element is a diode. 5. A horizontal deflection output circuit according to claim 1, wherein said load means includes: a resistor; and current adjusting means for adjusting the current to flow through said resistor. 6. A horizontal deflection output circuit comprising:
a switching element;
a resonant capacitor connected in parallel with said switching element;
a series circuit connected in parallel with said switching element and including a horizontal deflection coil and a linearity correcting coil; and
7. A horizontal deflection output circuit according to claim 6, wherein a capacitor is connected in parallel with said linearity correcting coil. 8. A horizontal deflection output circuit according to claim 6, wherein said one-way switching element is turned off at least for a fly-back pulse period. 9. A horizontal deflection output circuit according to claim 6, wherein said one-way switching element is a diode. 10. A horizontal deflection output circuit according to claim 6, wherein said bias voltage feeding means includes resistance voltage-dividing means for dividing the voltage between the two terminals of said linearity correcting coil. 11. A horizontal deflection output circuit according to claim 10, wherein a capacitor is connected in parallel with said linearity correcting coil. 12. A horizontal deflection output circuit according to claim 10, wherein said one-way switching element is turned off at least for a fly-back pulse period. 13. A horizontal deflection output circuit according to claim 10, wherein said one-way switching element is a diode. 14. A horizontal deflection output circuit according to claim 10, wherein said bias voltage feeding means includes a time constant circuit composed of a resistor and a capacitor. 15. A horizontal deflection output circuit according to claim 14, wherein a capacitor is connected in parallel with said linearity correcting coil. 16. A horizontal deflection output circuit according to claim 14, wherein said one-way switching element is a diode. 17. A horizontal deflection output circuit according to claim 14, wherein said one-way switching element is turned off at least for a fly-back pulse period. 18. A horizontal deflection output circuit comprising:
a switching element;
a damper diode connected in parallel with said switching element;
a resonant capacitor connected in parallel with said switching element;
a first series circuit connected in parallel with said switching element and including a horizontal deflection coil and a linearity correcting coil;
a second series circuit connected in parallel with said linearity correcting coil, said second series circuit comprising load means for damping resonance energy in said first series circuit and current control means for limiting the current flow through said load means to the first half of a horizontal scanning period and including a one-way switching element which turns on for the first half of said horizontal scanning period and turns off for the last half of said horizontal scanning period and a fly-back pulse period, thereby limiting current flow through said load means to said first half of said horizontal scanning period;
a choke coil connected with the cathode terminal of said damper diode; and
a d.c. current blocking capacitor connected in series with said horizontal deflection coil.
19. A horizontal deflection output circuit according to claim 18, wherein said choke coil is a fly-back transformer. 20. A horizontal deflection output circuit according to claim 19, wherein said load means includes a resistor. 21. A horizontal deflection output circuit according to claim 20, wherein a capacitor is connected in parallel with said linearity correcting coil. 22. A horizontal deflection output circuit according to claim 20, wherein said one-way switching element is a diode. 23. A horizontal deflection output circuit according to claim 19, wherein said load means includes: a resistor; and current adjusting means for adjusting the current to flow through said resistor. 24. A horizontal deflection output circuit comprising:
a switching element;
a damper diode connected in parallel with said switching element;
a resonant capacitor connected in parallel with said switching element;
a series circuit connected in parallel with said switching element and including a horizontal deflection coil and a linearity correcting coil;
a series circuit connected in parallel with said linearity correcting coil and including load means and a one-way switching element adapted to be turned on for the front half of a horizontal scanning period, said load means including a resistor and current adjusting means for adjusting the current flow through said resistor, said current adjusting means including a transistor connected in series with said resistor and bias voltage feeding means for feeding a bias voltage to the base of said transistor;
a choke coil in the form of a fly-back transformer connected with the cathode terminal of said damper diode; and
a d.c. current blocking capacitor connected in series with said horizontal deflection coil.
25. A horizontal deflection output circuit according to claim 24, wherein said one-way switching element is turned off at least for a fly-back pulse period. 26. A horizontal deflection output circuit according to claim 24, wherein a capacitor is connected in parallel with said linearity correcting coil. 27. A horizontal deflection output circuit according to claim 24, wherein said one-way switching element is a diode. 28. A horizontal deflection output circuit according to claim 24, wherein said bias voltage feeding means includes resistance voltage-dividing means for dividing the voltage between the two terminals of said linearity correcting coil. 29. A horizontal deflection output circuit according to claim 28, wherein said bias voltage feeding means includes a time constant circuit composed of a resistor and a capacitor. 30. A horizontal deflection output circuit according to claim 28, wherein said one-way switching element is turned off at least for a fly-back pulse period. 31. A horizontal deflection output circuit according to claim 28, wherein a capacitor is connected in parallel with said linearity correcting coil. 32. A horizontal deflection output circuit according to claim 28, wherein said one-way switching element is a diode.
Description:
BACKGROUND OF THE INVENTIONIn a conventional TV receiver, a horizontal deflection current having a saw-tooth waveform reaches saturation as it approaches its maximum, causing a problem in that the scanning rate of the electron beam is reduced at the extreme right-hand side, as viewed toward the frame of the display, so that the picture reproduced on the face plate is distorted.
The circuit for solving the above-specified problem to form a symmetrical picture is called a "linearity correcting circuit". In order to correct the linearity of the raster scanned on the face plate, the linearity correcting circuit of the prior art is equipped with a linearity correcting coil which is connected in series with a horizontal deflection coil. That linearity correcting coil is so magnetically biased by means of a permanent magnet that its magnetic saturation characteristics are set differently depending upon the direction of the horizontal deflection current. This horizontal deflection circuit is exemplified by Japanese Patent Laid-Open Nos. 40615/1982, 128949/1981, 124850/1980 and U.S. Pat. No. 3,962,603, as shown schematically in FIGS. 1A and 1B.
As shown in FIG. 1A, the horizontal deflection circuit is composed of an input terminal 1, an output transistor 2, a damper diode 3, a resonant capacitor 4, a horizontal deflection coil 5, a linearity correcting coil 6, an S-shaped correction capacitor 7, a choke coil 8, a supply terminal 9, and a permanent magnet 12 for setting the magnetic bias of the linearity correcting coil 6.
The permanent magnet 12 has its polarity arranged so as to apply a magnetic field in the same direction as that of the magnetic field established in the linearity correcting coil in case a horizontal deflection current IDY flows in the direction of arrow a to the horizontal deflection coil 5.
In case the horizontal deflection current IDY flows in the direction of the arrow a, therefore, the linearity correcting coil 6 is more liable to be magnetically saturated than when the horizontal deflection current IDY flows in the reverse direction.
As a result, the inductance of the linearity correcting coil 6 is least in the vicinity of the maximum of the horizontal deflection current so that this current increases.
Thus, the drop of the scanning rate of the electron beam at the right side of the display frame is corrected. In the display, however, the use of a linearity correcting coil will form longitudinal shading streaks at the left side of the display frame. Those streaks are formed as a result of the fact that a ringing current is established in the horizontal deflection current by the resonance of a resonant circuit which is composed of the inductance of the linearity coil 6 and a stray capacity 17, as shown in FIG. 1B.
As the horizontal deflection current has its frequency increased and its output raised in accordance with the fineness in the structure of the display, however, there arises another problem that the power loss at the ringing current preventing resistor is increased.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a horizontal deflection output circuit of high speed and output enabled to reduce such ringing of the horizontal deflection current as will raise a problem, when the horizontal linearity is to be corrected by a linearity correcting coil, without inviting an increase in the loss of the output circuit thereby to eliminate in a more advantageous way the longitudinal streaks which might otherwise be formed in a picture frame.
BANG & OLUFSEN BEOVISION 7702 CHASSIS SERIES 77XX 30AX Horizontal deflection circuit with a start-up power supply
I
n a horizontal deflection circuit, a horizontal oscillator, energized by a supply voltage, develops a horizontal frequency switching signal. A deflection outputs stage is responsive to the switching signal and generates scanning current in a horizontal deflection winding. After commencement of oscillator operation, the voltage developed across a secondary winding of a flyback transformer is rectified and filtered and applied to the horizontal oscillator as the oscillator energizing supply voltage. A start-up supply for developing the oscillator supply voltage during an initial interval includes a source of voltage that is available for use prior to the commencement of oscillator operation, a capacitor, a charging circuit for charging the capacitor from the available voltage source, and a controllable switch coupled to the capacitor and to the oscillator. After the charging circuit has charged the capacitor to a predetermined threshold voltage level, the controllable switch is made conductive to apply the capacitor voltage to the oscillator to commence oscillator operation. The switch is arranged with the capacitor as a relaxation oscillator to begin discharging the capacitor by the load current drawn by the horizontal oscillator. Should the capacitor discharge to a lower threshold level before the flyback-derived supply voltage is developed, the relaxation oscillator changes states to disconnect the horizontal oscillator from the capacitor to initiate a capacitor recharging cycle.1. An oscillator-derived power supply with start-up circuitry, comprising:
a supply terminal;
an oscillator being energized by the voltage developed at said supply terminal for producing an oscillator output signal;
a start-up voltage supply to energize said oscillator into commencing operation, said start-up voltage supply comprising:
a capacitor,
a source of DC input voltage available prior to commencement of oscillator operation,
means for charging said capacitor from said DC input voltage source, and
switching means interposed between said capacitor and said supply terminal for applying said capacitor voltage to said oscillator after said capacitor has charged to a first threshold level, to commence oscillator operation;
means responsive to said oscillator output signal for developing a steady-state voltage; and
means for applying said steady-state voltage to said supply terminal via said switching means to maintain oscillator energization during steady-state operation.
2. A supply according to claim 1 wherein the minimum load current required by said oscillator to commence operation exceeds in magnitude the current being provided to said capacitor by said charging means.
3. A supply according to claim 2 wherein said capacitor is being discharged to lower voltage by said oscillator after said switching means applies said capacitor voltage to said supply terminal and prior to steady-state oscillator operation.
4. A supply according to claim 3 wherein said steady-state voltage maintains said capacitor charged to a substantially constant voltage level during said steady-state operation.
5. A supply according to claim 4 wherein said DC input voltage is of greater magnitude than the magnitude of said substantially constant voltage level.
6. A supply according to claim 4 wherein said switching means serves to disconnect said capacitor from said supply terminal when said capacitor discharges to a second threshold level lower than said first threshold level to enable said capacitor to recharge.
7. A supply according to claim 6 wherein said steady-state voltage applying means comprises a diode blocking current flow from said charging means to said steady-state voltage developing means.
8. A supply according to any preceding claim wherein said oscillator comprises a deflection generator oscillator and wherein said oscillator output signal responsive means comprises a deflection generator output stage, a flyback transformer coupled to said output stage for developing a flyback pulse voltage across a transformer secondary winding, and rectifying and filtering means for developing said steady-state voltage from said flyback pulse voltage.
9. A deflection circuit-derived power supply with a start-up supply for the deflection circuit oscillator, comprising:
a horizontal oscillator energized by a supply voltage for developing a horizontal frequency switching signal after commencement of oscillator operation;
a horizontal deflection winding;
a deflection output stage responsive to said horizontal frequency switching signal for generating scanning current in said deflection winding;
a flyback transformer having a first winding coupled to said deflection output stage for developing a horizontal frequency alternating polarity output voltage across a plurality of secondary windings;
supply voltage producing means responsive to the horizontal frequency alternating polarity output voltage developed across one of said plurality of secondary windings for producing said supply voltage after commencement of horizontal oscillator operation; and
a start-up supply for developing said supply voltage during an initial interval to enable said horizontal oscillator to commence operation, said start-up supply comprising:
a source of voltage available prior to commencement of horizontal oscillator operation,
a capacitor,
means for charging said capacitor from said prior available voltage source, and
switching means coupled to said capacitor and to said horizontal oscillator for applying said capacitor voltage to said horizontal oscillator as said supply voltage to commence horizontal oscillator operation after said charging means has charged said capacitor to an upper threshold voltage level, said switching means arranged with said capacitor as a relaxation oscillator that begins discharging said capacitor by the load current drawn by said horizontal oscillator after said charging means has charged said capacitor to said upper threshold voltage level and begins recharging said capacitor from said charging means when said capacitor discharges to a lower threshold voltage level.
11. A supply according to claim 9 wherein said supply voltage producing means comprises means for rectifying and filtering said horizontal frequency alternating polarity output voltage and means for applying the output of said rectifying and filtering means to said capacitor to develop said supply voltage as a substantially constant voltage across said capacitor.
12. A supply according to claim 11 wherein said prior available voltage source comprises a source of DC input voltage of magnitude greater than said substantially constant voltage.
Description:
This invention relates to start-up supplies for horizontal deflection circuits.
In a television receiver, the supply voltages to power various television receiver circuits such as the vertical deflection circuit and the audio and video circuits are derived from rectified and filtered flyback pulses developed by the horizontal deflection circuit. After the horizontal oscillator in the deflection circuit has commenced operation, the supply voltage for the oscillator is also derived from rectified and filtered flyback pulse voltages.
When the television receiver is turned on, the flyback pulse voltages are absent. A start-up supply for the horizontal oscillator is therefore required in order to energize the oscillator and develop the flyback-derived power supply voltages for the television receiver. A voltage that is available to power the oscillator during the start-up interval after the television receiver is turned on is the DC input voltage obtained by rectifying and filtering the AC mains supply voltage.
Since the horizontal oscillator is designed to use a relatively low supply voltage, the DC input voltage during start-up may be applied to the oscillator through a dropping resistor. The value of the resistor is selected to be relatively large in order to minimize the dissipation in the resistor while at the same time providing the horizontal oscillator with at least the minimum amount of current required to initiate oscillator operation. After the flyback-derived supply voltage becomes available, the normal load current for the oscillator is provided from this supply excluding the load current still being provided by the dropping resistor. Thus, the dropping resistor dissipates a significant amount of power even during steady-state television receiver operation after the start-up interval has elapsed.
To eliminate power dissipation in the dropping resistor during steady-state operation, some start-up circuits include a transistor switch in series with the dropping resistor. When the steady-state flyback-derived supply voltage for the oscillator is developed, the switch becomes reverse biased, disconnecting the dropping resistor from the oscillator. A relatively expensive switch is required that is capable of withstanding the off-state voltage stress applied to it. This off-state voltage equals the difference between the DC input voltage and the oscillator supply voltage.
A feature of the invention is the design of an oscillator-derived power supply with start-up circuitry that dissipates relatively little power during steady-state operation after the oscillator has commenced operation. An oscillator energized by the voltage developed at a supply terminal produces an output signal that is used by a subsequent power supply stage to develop a steady-state voltage to energize the load circuit. The steady-state voltage is also applied to the oscillator to maintain it energized after commencement of oscillator operation. A start-up voltage supply to energize the oscillator into commencing operation comprises a capacitor, a source of energy that is available prior to the commencement of oscillator operation, a charging circuit for charging the capacitor from the energy source, and switching means interposed between the capacitor and the oscillator. The switching means applies the capacitor voltage to the oscillator after the capacitor has charged to a first threshold level, thereby commencing oscillator operation and the development of the steady-state voltage by the oscillator responsive power supply.
With such an arrangement, the charging current flowing to the capacitor may be selected to be of relatively low magnitude, much lower than even the minimum amount of load current required to energize the oscillator. Dissipation in the charging circuit is substantially reduced, even though the charging circuit may still be supplying current during steady-state operation after commencement of oscillator operation.
During the start-up interval, the oscillator draws more current from the capacitor than is being supplied by the charging circuit, resulting in the capacitor being discharged. Another feature of the invention is that should the capacitor discharge to a lower threshold level, indicating that the steady-state voltage supply is still unavailable for use, the switching means disconnects the capacitor from the oscillator, enabling the capacitor to recharge and reinitiate the start-up sequence.
FIG. 1 illustrates a horizontal deflection circuit with derived power supplies and with a start-up circuit for the deflection oscillator; and
FIG. 2 illustrates waveforms associated with the circuit of FIG. 1.
In FIG. 1, a source 20 of AC mains supply voltage is coupled to input terminals 23 and 24 of a full-wave bridge rectifier 27. Source 20 is coupled to input terminal 23 through an on/off switch 21 and a current limiting resistor 22. A filter capacitor 28 is coupled across output terminal 25 of bridge rectifier 27 and the current return or ground terminal 26. A filtered but unregulated DC input voltage Vin is developed at terminal 25 and applied to a regulator 29. Regulator 29 may be a conventional switching regulator, such as described in U.S. Pat. No. 4,147,964, D. W. Luz et al., entitled "COMPLEMENTARY LATCHING DISABLING CIRCUIT", using an SCR regulator switch operated at the horizontal deflection frequency of a television receiver to produce a regulated B+ voltage at a terminal 30. Feedback of the B+ voltage to the switching regulator is provided by a conductor line 74. A filter capacitor 31 is provided to filter out horizontal rate ripple voltage from terminal 30.
The B+ voltage developed at terminal 30 is applied through the primary winding 32a of a flyback transformer 32 to the collector of a horizontal output transistor 35 in a horizontal deflection output stage 34 of a horizontal deflection circuit 80. Horizontal deflection circuit 80 includes a horizontal oscillator 43, energized by a supply voltage Vcc developed at a supply terminal 45 and drawing a load current iL therefrom, a horizontal driver transistor 44 and horizontal output stage 34. Horizontal output stage 34 comprises horizontal output transistor 35, a damper diode 36, a retrace capacitor 38 and the series arrangement of a horizontal deflection winding 39 and an S-shaping or trace capacitor 40.
Horizontal oscillator 43, when energized by the voltage developed at supply terminal 45, produces a horizontal frequency, 1/TH, output switching signal 37 that is inverted by horizontal driver transistor 44 and applied to horizontal output transistor 35 through a driver transformer 42 to produce the switching action needed to generate horizontal scanning current in horizontal deflection winding 39. A waveshaping and filtering network 41 is coupled between the secondary winding 42b of driver transformer 42 and the base and emitter electrodes of output transistor 35.
Horizontal output transistor 35 is turned on early within the trace interval of each deflection cycle to conduct the horizontal scanning current after damper diode 36 is cut off and is turned off to initiate the horizontal retrace interval. During horizontal retrace, a retrace pulse voltage Vr is developed at the collector of horizontal output transistor 35 and applied to flyback transformer primary winding 32a to develop alternating polarity horizontal retrace pulse voltages across secondary windings 32b-32d.
The high voltage developed across winding 32b is applied to a high voltage circuit 33 to develop a DC ultor accelerating potential at a terminal U. The voltage across flyback transformer secondary winding 32c is rectified by a diode 46 during the horizontal trace interval and filtered by a capacitor 47 to develop a DC supply voltage V1 at a terminal 49. Supply voltage V1 energizes and provides current to such television receiver load circuits as the vertical deflection circuit and the audio circuit, designated in FIG. 1 generally as a resistor 48. The voltage across flyback transformer secondary winding 32d is rectified during the horizontal retrace interval by a diode 51 and applied to a supply terminal 53 through a current limiting resistor 52 to develop a DC supply voltage V2 across a filter capacitor 54. The DC supply voltage V2 energizes and provides current to such television receiver load circuits as the video driver circuit designated in FIG. 1 generally as a resistor 55.
The rectified and filtered voltage from flyback transformer winding 32d also supplies the collector voltage for horizontal driver transistor 44. The substantially DC voltage developed at the cathode of diode 51 at terminal 50 is applied through a resistor 57 and primary winding 42a of driver transformer 42 to the collector of driver transistor 44. A capacitor 56 provides horizontal rate filtering.
When the television receiver is turned on, after closure of on/off switch 21, the unregulated DC input voltage Vin is developed at terminal 25 and applied to switching regulator 29 to develop a voltage at B+ terminal 30. During the initial or start-up interval following closure of on/off switch 21, the flyback-derived supply voltages V1 and V2 are absent. To generate these voltages, switching action of horizontal output transistor 35 must be initiated by initiating or commencing the switching actions of horizontal oscillator 43 and driver transistor 44. Energization of these two elements, 43 and 44, must be obtained from voltage or energy sources that are available for use prior to commencement of operation of horizontal oscillator 43 and driver transistor 44.
The voltage used during start-up for providing collector supply voltage to driver transistor 44 is the voltage developed at B+ terminal 30 after closure of on/off switch 21. Terminal 30 is coupled to terminal 50 through a resistor 59 and a diode 60. Collector voltage for driver transistor 44 is obtained from B+ terminal 30 during start-up by way of resistor 59 and diode 60.
A start-up supply 90 is provided to initially develop supply voltage for horizontal oscillator 43 to energize the oscillator into commencing operation. Start-up supply 90 comprises a capacitor 63, a transistor switch 66 interposed between capacitor 63 and horizontal oscillator 43 at the supply terminal 45, a source of energy or voltage available prior to commencement of oscillator operation, namely the source of the DC input voltage Vin, and a charging resistor 61 that is used to charge capacitor 63 during the start-up interval from the DC input voltage terminal 25 by way of a resistor 62. Resistor 62 is a relatively low valued resistor used for a purpose hereinafter to be described.
Upon closureof on/off switch 21 and the development of a DC voltage Vin at terminal 25, a charging current ic begins to flow through resistor 61 and resistor 62 to terminal 73, the junction of capacitor 63 and the emitter of controllable transistor switch 66. Capacitor 63 is initially uncharged and the voltage Vc at terminal 73 is zero, maintaining transistor switch 66 in the off-state immediately after closure of on/off switch 21.
The base of transistor switch 66 is coupled to the collector of a transistor 67 through a resistor 72. A biasing network for transistors 66 and 67, comprising resistors 68-72, establishes at terminal 73 an upper threshold voltage level Va and a lower threshold voltage level Vb so as to enable transistors 66 and 67 to form with capacitor 63 a relaxation oscillator arrangement. When transistor 66 is cut off, resistor 70 is effectively in parallel with resistor 69, thereby establishing the upper threshold voltage level Va of FIG. 2; and when transistor 66 is in saturated conduction, resistor 70 is effectively in parallel with resistor 68, thereby establishing the lower threshold voltage level Vb.
As illustrated in FIG. 2 by the solid-line waveform of the voltage Vc, at a time t0, on/off switch 21 is closed and the charging current ic flowing from terminal 73 begins to charge capacitor 63. At time t1, capacitor 63 has charged to the upper threshold voltage level Va, turning on transistor 67 which turns on transistor switch 66 into saturated conduction. After transistor 66 becomes conductive, the voltage across capacitor 63 is applied to horizontal oscillator 43 at supply terminal 45 as a start-up supply voltage for the horizontal oscillator. Horizontal oscillator 43 commences operation and begins producing the horizontal rate switching signal 37 to initiate the switching action of horizontal driver transistor 44 and horizontal output transistor 35, thereby initiating the development of the horizontal retrace pulse voltage Vr and the horizontal retrace pulse voltages across flyback transformer secondary windings 32b-32d.
The load current iL being drawn by horizontal oscillator 43 durin
g the initial or start-up interval, after time t1 of FIG. 2, is of greater magnitude than the charging current ic flowing to terminal 73 from charging resistor 61. Thus, after time t1, horizontal oscillator 43 begins discharging capacitor 63 as illustrated in FIG. 2 by the decreasing voltage Vc after time t1. Even though the voltage Vc applied to horizontal oscillator 43 during the start-up interval after time t1 is decreasing, it is still sufficiently greater than the minimum voltage needed to maintain the oscillator operating. Thus, the horizontal rate switching signal is still being produced by horizontal oscillator 43 after time t1. By time t2 of FIG. 2, a sufficient period has elapsed so as to enable a substantial buildup of the flyback-derived supply voltage V1 at terminal 49. Supply voltage V1 is then applied to horizontal oscillator 43 by way of a diode 64 that has its cathode coupled to terminal 65, the junction of charging resistor 61 and resistor 62. Diode 64 blocks the flow of charging current to flyback supply terminal to prevent undue shunting of the current from oscillator 43 during start-up.
Near time t2, the flyback-derived supply voltage V1 has increased sufficiently so as to be able to generate a current i1 flowing out of supply terminal 49 that is greater than the load current iL being drawn by horizontal oscillator 43. Thus, after time t2, capacitor 63 ceases discharging and becomes charged shortly thereafter to a relatively constant voltage level Vcc0, as illustrated by the solid-line waveform of FIG. 2 after time t2.
The voltage Vcc0 maintains transistor switch 66 conducting and is applied via the transistor to horizontal oscillator 43 as the steady-state supply voltage. Thus, the steady-state supply voltage Vcc0 is obtained from the flyback-derived supply voltage V1. Because the flyback-derived supply voltage V1 also functions as a supply voltage for other television receiver loads, the voltage V1 is not necessarily of the ideal magnitude to energize horizontal oscillator 43. Typically, the voltage V1 is slightly greater in magnitude than is desirable for use by horizontal oscillator 43. Resistor 62 is therefore provided to generate a voltage drop to establish the correct lower voltage Vcc0 at supply terminal 45.
During steady-state operation, the load current iL for horizontal oscillator 43 comprises the sum of the current i1 obtained from flyback supply terminal 49 and the charging current ic obtained from charging resistor 61, if the biasing currents to transistors 66 and 67 are neglected. Thus, even during steady-state operation, the charging current ic flows through resistor 61.
To keep power dissipation in charging resistor 61 to a relatively small amount especially during steady-state operation, the magnitude of the charging current ic is kept at a relatively small value, illustratively at 5% or less of the steady-state load current of horizontal oscillator 43 and 10 times less than the minimum load current needed to maintain horizontal oscillator 43 operating at start-up. By providing a transistor 66 interposed between capacitor 63 and oscillator supply terminal 45, the current required to flow through the resistance that is coupled between the DC input voltage Vin and oscillator 43 may be kept relatively small to reduce steady-state dissipation. Sufficient start-up load current to horizontal oscillator 43 is available, nonetheless, due to the charge buildup on capacitor 63 and the subsequent discharge of the capacitor.
The values of the upper threshold voltage level Va and of the capacitance of capacitor 63 may be selected such that for almost every deflection circuit operating condition encountered, sufficient time is available after capacitor 63 begins to be discharged by the load current drawn by horizontal oscillator 43 to enable the flyback-derived supply voltage V1 to subsequently take over energization of the oscillator before the capacitor has discharged to a voltage less than the minimum required to maintain operation of the oscillator.
Another feature of the invention is to arrange transistor switch 66, transistor 67 and capacitor 63 as a relaxation oscillator. By providing a relaxation oscillator arrangement, start-up of horizontal deflection circuit 80 is ensured for practically all operating conditions encountered by horizontal deflection circuit 80. For example, a situation may be encountered during start-up where the DC input voltage Vin is extremely low and the loading on flyback transformer 32 is extremely high. In such an operating situation, a much longer interval after the initiation of start-up may be required to build up the flyback-derived supply voltage V1 to a satisfactory level. If capacitor 63 discharges to a level below the minimum necessary to maintain horizontal oscillator 43 in operation before the voltage V1 builds up to a satisfactory level, start-up of deflection circuit 80 is defeated.
To prevent such a situation from occurring, the relaxation oscillator arrangement of start-up supply 90 establishes a lower threshold voltage level Vb when transistor switch 66 is conductive. Should capacitor 63 discharge to the lower threshold voltage level Vb, as illustrated by FIG. 2 by the dashed-line waveform of the voltage Vc after time t2, indicating a failure of the flyback-derived supply voltage V1 to build up to a satisfactory level, transistor 67 is biased off, thereby turning off transistor switch 66. The value of the lower threshold voltage level Vb may be selected as greater than the minimum voltage needed to maintain oscillator 43 functioning.
With transistor switch 66 cut off at time t3, a start-up charging cycle for capacitor 63 is reinitiated. As illustrated in FIG. 2 by the dashed-line waveform, capacitor 63 recharges from time t3 to time t4, at which time the upper threshold voltage level Va is again reached at terminal 73 to turn on transistor switch 66 at time t4. The voltage across capacitor 63 is again applied to horizontal oscillator 43 to recommence oscillator operation and to continue the buildup of flyback-derived supply voltage V1 so that by time t5 the supply voltage V1 has increased sufficiently to take over supplying current to horizontal oscillator 43. Shortly after time t5, the steady-state supply voltage Vcc0 at supply terminal 45 is established.
The relaxation oscillator arrangement of start-up supply 90 can provide as many charge/discharge cycles for capacitor 63 as may be required in order to build up the flyback-derived supply voltage V1 to the levels needed to maintain steady-state deflection circuit operation.
In a television receiver, the supply voltages to power various television receiver circuits such as the vertical deflection circuit and the audio and video circuits are derived from rectified and filtered flyback pulses developed by the horizontal deflection circuit. After the horizontal oscillator in the deflection circuit has commenced operation, the supply voltage for the oscillator is also derived from rectified and filtered flyback pulse voltages.
When the television receiver is turned on, the flyback pulse voltages are absent. A start-up supply for the horizontal oscillator is therefore required in order to energize the oscillator and develop the flyback-derived power supply voltages for the television receiver. A voltage that is available to power the oscillator during the start-up interval after the television receiver is turned on is the DC input voltage obtained by rectifying and filtering the AC mains supply voltage.
To eliminate power dissipation in the dropping resistor during steady-state operation, some start-up circuits include a transistor switch in series with the dropping resistor. When the steady-state flyback-derived supply voltage for the oscillator is developed, the switch becomes reverse biased, disconnecting the dropping resistor from the oscillator. A relatively expensive switch is required that is capable of withstanding the off-state voltage stress applied to it. This off-state voltage equals the difference between the DC input voltage and the oscillator supply voltage.
A feature of the invention is the design of an oscillator-derived power supply with start-up circuitry that dissipates relatively little power during steady-state operation after the oscillator has commenced operation. An oscillator energized by the voltage developed at a supply terminal produces an output signal that is used by a subsequent power supply stage to develop a steady-state voltage to energize the load circuit. The steady-state voltage is also applied to the oscillator to maintain it energized after commencement of oscillator operation. A start-up voltage supply to energize the oscillator into commencing operation comprises a capacitor, a source of energy that is available prior to the commencement of oscillator operation, a charging circuit for charging the capacitor from the energy source, and switching means interposed between the capacitor and the oscillator. The switching means applies the capacitor voltage to the oscillator after the capacitor has charged to a first threshold level, thereby commencing oscillator operation and the development of the steady-state voltage by the oscillator responsive power supply.
With such an arrangement, the charging current flowing to the capacitor may be selected to be of relatively low magnitude, much lower than even the minimum amount of load current required to energize the oscillator. Dissipation in the charging circuit is substantially reduced, even though the charging circuit may still be supplying current during steady-state operation after commencement of oscillator operation.
During the start-up interval, the oscillator draws more current from the capacitor than is being supplied by the charging circuit, resulting in the capacitor being discharged. Another feature of the invention is that should the capacitor discharge to a lower threshold level, indicating that the steady-state voltage supply is still unavailable for use, the switching means disconnects the capacitor from the oscillator, enabling the capacitor to recharge and reinitiate the start-up sequence.
FIG. 1 illustrates a horizontal deflection circuit with derived power supplies and with a start-up circuit for the deflection oscillator; and
FIG. 2 illustrates waveforms associated with the circuit of FIG. 1.
In FIG. 1, a source 20 of AC mains supply voltage is coupled to input terminals 23 and 24 of a full-wave bridge rectifier 27. Source 20 is coupled to input terminal 23 through an on/off switch 21 and a current limiting resistor 22. A filter capacitor 28 is coupled across output terminal 25 of bridge rectifier 27 and the current return or ground terminal 26. A filtered but unregulated DC input voltage Vin is developed at terminal 25 and applied to a regulator 29. Regulator 29 may be a conventional switching regulator, such as described
in U.S. Pat. No. 4,147,964, D. W. Luz et al., entitled "COMPLEMENTARY LATCHING DISABLING CIRCUIT", using an SCR regulator switch operated at the horizontal deflection frequency of a television receiver to produce a regulated B+ voltage at a terminal 30. Feedback of the B+ voltage to the switching regulator is provided by a conductor line 74. A filter capacitor 31 is provided to filter out horizontal rate ripple voltage from terminal 30.The B+ voltage developed at terminal 30 is applied through the primary winding 32a of a flyback transformer 32 to the collector of a horizontal output transistor 35 in a horizontal deflection output stage 34 of a horizontal deflection circuit 80. Horizontal deflection circuit 80 includes a horizontal oscillator 43, energized by a supply voltage Vcc developed at a supply terminal 45 and drawing a load current iL therefrom, a horizontal driver transistor 44 and horizontal output stage 34. Horizontal output stage 34 comprises horizontal output transistor 35, a damper diode 36, a retrace capacitor 38 and the series arrangement of a horizontal deflection winding 39 and an S-shaping or trace capacitor 40.
Horizontal output transistor 35 is turned on early within the trace interval of each deflection cycle to conduct the horizontal scanning current after damper diode 36 is cut off and is turned off to initiate the horizontal retrace interval. During horizontal retrace, a retrace pulse voltage Vr is developed at the collector of horizontal output transistor 35 and applied to flyback transformer primary winding 32a to develop alternating polarity horizontal retrace pulse voltages across secondary windings 32b-32d.
The rectified and filtered voltage from flyback transformer winding 32d also supplies the collector voltage for horizontal driver transistor 44. The substantially DC voltage developed at the cathode of diode 51 at terminal 50 is applied through a resistor 57 and primary winding 42a of driver transformer 42 to the collector of driver transistor 44. A capacitor 56 provides horizontal rate filtering.
When the television receiver is turned on, after closure of on/off switch 21, the unregulated DC input voltage Vin is developed at terminal 25 and applied to switching regulator 29 to develop a voltage at B+ terminal 30. During the initial or start-up interval following closure of on/off switch 21, the flyback-derived supply voltages V1 and V2 are absent. To generate these voltages, switching action of horizontal output transistor 35 must be initiated by initiating or commencing the switching actions of horizontal oscillator 43 and driver transistor 44. Energization of these two elements, 43 and 44, must be obtained from voltage or energy sources that are available for use prior to commencement of operation of horizontal oscillator 43 and driver transistor 44.
The voltage used during start-up for providing collector supply voltage to driver transistor 44 is the voltage developed at B+ terminal 30 after closure of on/off switch 21. Terminal 30 is coupled to terminal 50 through a resistor 59 and a diode 60. Collector voltage for driver transistor 44 is obtained from B+ terminal 30 during start-up by way of resistor 59 and diode 60.
A start-up supply 90 is provided to initially develop supply voltage for horizontal oscillator 43 to energize the oscillator into commencing operation. Start-up supply 90 comprises a capacitor 63, a transistor switch 66 interposed between capacitor 63 and horizontal oscillator 43 at the supply terminal 45, a source of energy or voltage available prior to commencement of oscillator operation, namely the source of the DC input voltage Vin, and a charging resistor 61 that is used to charge capacitor 63 during the start-up interval from the DC input voltage terminal 25 by way of a resistor 62. Resistor 62 is a relatively low valued resistor used for a purpose hereinafter to be described.
Upon closure
of on/off switch 21 and the development of a DC voltage Vin at terminal 25, a charging current ic begins to flow through resistor 61 and resistor 62 to terminal 73, the junction of capacitor 63 and the emitter of controllable transistor switch 66. Capacitor 63 is initially uncharged and the voltage Vc at terminal 73 is zero, maintaining transistor switch 66 in the off-state immediately after closure of on/off switch 21.The base of transistor switch 66 is coupled to the collector of a transistor 67 through a resistor 72. A biasing network for transistors 66 and 67, comprising resistors 68-72, establishes at terminal 73 an upper threshold voltage level Va and a lower threshold voltage level Vb so as to enable transistors 66 and 67 to form with capacitor 63 a relaxation oscillator arrangement. When transistor 66 is cut off, resistor 70 is effectively in parallel with resistor 69, thereby establishing the upper threshold voltage level Va of FIG. 2; and when transistor 66 is in saturated conduction, resistor 70 is effectively in parallel with resistor 68, thereby establishing the lower threshold voltage level Vb.
As illustrated in FIG. 2 by the solid-line waveform of the voltage Vc, at a time t0, on/off switch 21 is closed and the charging current ic flowing from terminal 73 begins to charge capacitor 63. At time t1, capacitor 63 has charged to the upper threshold voltage level Va, turning on transistor 67 which turns on transistor switch 66 into saturated conduction. After transistor 66 becomes conductive, the voltage across capacitor 63 is applied to horizontal oscillator 43 at supply terminal 45 as a start-up supply voltage for the horizontal oscillator. Horizontal oscillator 43 commences operation and begins producing the horizontal rate switching signal 37 to initiate the switching action of horizontal driver transistor 44 and horizontal output transistor 35, thereby initiating the development of the horizontal retrace pulse voltage Vr and the horizontal retrace pulse voltages across flyback transformer secondary windings 32b-32d.
The load current iL being drawn by horizontal oscillator 43 durin
g the initial or start-up interval, after time t1 of FIG. 2, is of greater magnitude than the charging current ic flowing to terminal 73 from charging resistor 61. Thus, after time t1, horizontal oscillator 43 begins discharging capacitor 63 as illustrated in FIG. 2 by the decreasing voltage Vc after time t1. Even though the voltage Vc applied to horizontal oscillator 43 during the start-up interval after time t1 is decreasing, it is still sufficiently greater than the minimum voltage needed to maintain the oscillator operating. Thus, the horizontal rate switching signal is still being produced by horizontal oscillator 43 after time t1. By time t2 of FIG. 2, a sufficient period has elapsed so as to enable a substantial buildup of the flyback-derived supply voltage V1 at terminal 49. Supply voltage V1 is then applied to horizontal oscillator 43 by way of a diode 64 that has its cathode coupled to terminal 65, the junction of charging resistor 61 and resistor 62. Diode 64 blocks the flow of charging current to flyback supply terminal to prevent undue shunting of the current from oscillator 43 during start-up.Near time t2, the flyback-derived supply voltage V1 has increased sufficiently so as to be able to generate a current i1 flowing out of supply terminal 49 that is greater than the load current iL being drawn by horizontal oscillator 43. Thus, after time t2, capacitor 63 ceases discharging and becomes charged shortly thereafter to a relatively constant voltage level Vcc0, as illustrated by the solid-line waveform of FIG. 2 after time t2.
During steady-state operation, the load current iL for horizontal oscillator 43 comprises the sum of the current i1 obtained from flyback supply terminal 49 and the charging current ic obtained from charging resistor 61, if the biasing currents to transistors 66 and 67 are neglected. Thus, even during steady-state operation, the charging current ic flows through resistor 61.
The values of the upper threshold voltage level Va and of the capacitance of capacitor 63 may be selected such that for almost every deflection circuit operating condition encountered, sufficient time is available after capacitor 63 begins to be discharged by the load current drawn by horizontal oscillator 43 to enable the flyback-derived supply voltage V1 to subsequently take over energization of the oscillator before the capacitor has discharged to a voltage less than the minimum required to maintain operation of the oscillator.
To prevent such a situation from occurring, the relaxation oscillator arrangement of start-up supply 90 establishes a lower threshold voltage level Vb when transistor switch 66 is conductive. Should capacitor 63 discharge to the lower threshold voltage level Vb, as illustrated by FIG. 2 by the dashed-line waveform of the voltage Vc after time t2, indicating a failure of the flyback-derived supply voltage V1 to build up to a satisfactory level, transistor 67 is biased off, thereby turning off transistor switch 66. The value of the lower threshold voltage level Vb may be selected as greater than the minimum voltage needed to maintain oscillator 43 functioning.
With transistor switch 66 cut off at time t3, a start-up charging cycle for capacitor 63 is reinitiated. As illustrated in FIG. 2 by the dashed-line waveform, capacitor 63 recharges from time t3 to time t4, at which time the upper threshold voltage level Va is again reached at terminal 73 to turn on transistor switch 66 at time t4. The voltage across capacitor 63 is again applied to horizontal oscillator 43 to recommence oscillator operation and to continue the buildup of flyback-derived supply voltage V1 so that by time t5 the supply voltage V1 has increased sufficiently to take over supplying current to horizontal oscillator 43. Shortly after time t5, the steady-state supply voltage Vcc0 at supply terminal 45 is established.
The relaxation oscillator arrangement of start-up supply 90 can provide as many charge/discharge cycles for capacitor 63 as may be required in order to build up the flyback-derived supply voltage V1 to the levels needed to maintain steady-state deflection circuit operation.
BANG & OLUFSEN BEOVISION 7702 CHASSIS SERIES 77XX 30AX CIRCUIT ARRANGEMENT IN A PICTURE DISPLAY DEVICE UTILIZING A STABILIZED SUPPLY VOLTAGE CIRCUIT:TDA2581 CONTROL CIRCUIT FOR SMPS/PHILIPS POWER PACK:
The TDA2581 is a monolithic integrated circuit for controlling switched-mode power supplies (SMPS) which are provided with the drive for the horizontal deflection stage.
The circuit features the following:
— Voltage controlled horizontal oscillator.
— Phase detector.
— Duty factor control for the positive-going transient of the output signal.
— Duty factor increases from zero to its normal operation value.
— Adjustable maximum duty factor.
- Over-voltage and over-current protection with automatic re-start after switch-off.
— Counting circuit for permanent switch-off when n~times over~current or over-voltage is sensed
-Protection for open-reference voltage.
- Protection for too low supply voltage.
Protection against loop faults.
Positive tracking of duty factor and feedback voltage when the feedback voltage is smaller than the
reference voltage minus 1,5 V.
BANG & OLUFSEN BEOVISION 7702 CHASSIS SERIES 77XX 30AX Line synch Switched Mode Power Supply with Line deflection output Transistor Drive Circuit:
1. An electrical circuit arrangement for a picture display device operating at a given line scanning frequency, comprising a source of unidirectional voltage, an inductor, first switching transistor means for periodically energizing said inductor at said scanning frequency with current from said source, an electrical load circuit coupled to said inductor and having applied thereto a voltage as determined by the ratio of the ON and OFF periods of said transistor, means for maintaining the voltage across said load circuit at a given value comprising means for comparing the voltage of said load circuit with a reference voltage, means responsive to departures of the value of the load circuit voltage from the value of said reference voltage for varying the conduction ratio of the ON and OFF periods of said transistor thereby to stabilize said load circuit voltage at the given value, a line deflection coil system for said picture display device, means for energizing said line deflection coil system from said load voltage circuit means, means for periodically interrupting the energization of said line deflection coil comprising second switching means and means coupled to said inductor for deriving therefrom a switching current in synchronism with the energization periods of said transistor and applying said switching current to said switching means thereby to actuate the same, and means coupled to said switching means and to said load voltage circuit for producing a voltage for energizing said 2. A circuit as claimed in claim 1 wherein the duty cycle of said switching 3. A circuit as claimed in claim 1 further comprising an efficiency first 4. A circuit as claimed in claim 3 further comprising at least a second diode coupled to said deriving means and to ground, and being poled to 5. A circuit as claimed in claim 1 wherein said second switching means comprises a second transistor coupled to said deriving means to conduct simultaneously with said first transistor, and further comprising a coil coupled between said driving means and said second transistor and a third diode shunt coupled to said coil and being poled to conduct when said 6. A circuit as claimed in claim 1 further comprising a horizontal oscillator coupled to said first transistor, said oscillator being the 7. A circuit as claimed in claim 1 further comprising means coupled to said inductor for deriving filament voltage for said display device.
Description:
Such a circuit arrangement is known from German "Auslegeschrift" 1.293.304. wherein a circuit arrangement is described which has for its object to convert an input direct voltage which is generated between two terminals into a different direct voltage. The circuit employs a switch connected to the first terminal of the input voltage and periodically opens and closes so that the input voltage is converted into a pulsatory voltage. This pulsatory voltage is then applied to a coil. A diode is arranged between the junction of the switch and the coil and the second terminal of the input voltage whilst a load and a charge capacitor in parallel thereto are arranged between the other end of the coil and the second terminal of the input voltage. The assembly operates in accordance with the known efficiency principle i.e., the current supplied to the load flows alternately through the switch and through the diode. The function of the switch is performed by a switching transistor which is driven by a periodical pulsatory voltage which saturates this transistor for a given part of the period. Such a configuration is known under different names in the literature; it will be referred to herein as a "chopper." A known advantage thereof, is that the switching transistor must be able to stand a high voltage or provide a great current but it need not dissipate a great power. The output voltage of the chopper is compared with a constant reference voltage. If the output voltage attempts to vary because the input voltage and/or the load varies, a voltage causing a duration modulation of the pulses is produced at the output of the comparison arrangement. As a result the quantity of the energy stored in the coil varies and the output voltage is maintained constant. In the German "Auslegeschrift" referred to it is therefore an object to provide a stabilized supply
voltage device.
The invention is also based on the recognition that the duration modulation which is necessary to stabilize the supply voltage with the switching transistor does not exert influence on the driving of the line output transistor. This resides in the fact that in case of a longer or shorter cut-off period of the line output transistor the current flowing through the line deflection coils thereof is not influenced because of the efficiency diode current and transistor current are taken over or, in case of a special kind of transistor, the collector-emitter current is taken over by the base collector current and conversely. However, in that case the above-mentioned ratios of 0.3 : 0.7 should be taken into account since otherwise this take-over principle is jeopardized.
As will be further explained the use of the switching transistor as a driver for the line output transistor in an embodiment to be especially described hereinafter has the further advantage that the line output transistor automatically becomes non-conductive when this switching transistor is short circuited so that the deflection and the EHT for the display tube drop out and thus avoid damage thereof.
Due to the step according to the invention the switching transistor in the stabilized supply functions as a driver for the line deflection circuit. The circuit arrangement according to the invention may in addition be equipped with a very efficient safety circuit so that the reliability is considerably enhanced, which is described in the U.S. Pat. No. 3,629,686. The invention is
In order that the invention may be readily carried into effect, a few embodiments thereof will now be described in detail by way of example with reference to the accompanying diagrammatic drawings in which:
FIG. 1 shows a principle circuit diagram wherein the chopper and the line deflection circuit are further shown but other circuits are not further shown.
FIGS. 2a, 2b and 2c show the variation as a function of time of two currents and of a voltage occurring in the circuit arrangement according to FIG. 1.
FIGS. 3a 3b, 3c and 3d show other embodiments of the chopper.
FIGS. 4a and 4b show modifications of part of the circuit arrangement of FIG. 1.
The emitter of switching transistor 2 is connected at one end to the cathode of an efficiency diode 7 whose other end is connected to the second input voltage terminal and at the other end to primary winding 8 of a transformer 9. Pulsatory voltage 3 which is produced at the cathode of efficiency diode 7 is clamped against the potential of said second terminal during the intervals when this diode conducts. During the other intervals the pulsatory voltage 3 assumes the value V i . A charge capacitor 10 and a load 11 are arranged between the other end of winding 8 and the second input voltage terminal. The elements 2,7,8,10 and 11 constitute a so-called chopper producing a direct voltage across charge capacitor 10, provided that capacitor 10 has a sufficiently great value for the line frequency and the current applied to load 11 flowing alternately through switching transistor 2 or through efficiency diode 7. The output voltage V o which is the direct voltage produced across charge capacitor 10 is applied to a comparison circuit 12 which compares the voltage V o with a reference voltage. Comparison circuit 12 generates a direct voltage which is applied to modulator 5 so that the duration of the effective period δ T of switching transistor 2 relative to the period T of pulses 3 varies as a function of the variations of output voltage V 0 . In fact, it is readily evident that output voltage V o is proportional to the ratio δ :
V o = V i . δ
However, variations in the line amplitude and the EHT may occur as a result of an insufficiently small internal impedance of the EHT generator. Compensation means are known for this purpose. A possibility within the scope of the present invention is to use comparison circuit 12 for this purpose. In fact, if the beam current passes through an element having a substantially quadratic characteristic, for example, a voltage-dependent resistor, then a variation for voltage V o may be obtained through comparison circuit 12 which variation is proportional to the root of the variation in the EHT which is a known condition for the line amplitude to remain constant.In addition this facilitates smoothing of voltage V o since the repetition frequency of pulsatory voltage 3 is many times higher than that of the mains and a comparatively small value may be sufficient for charge capacitor 10. If charge capacitor 10 has a sufficiently high value for the line frequency, voltage V o is indeed a direct voltage so that a voltage having the same form as pulsatory voltage 3 is produced across the terminals of primary winding 8. Thus voltages which have the same shape as pulsatory voltage 3 but have a greater or smaller amplitude are produced across secondary windings 13, 14 of transformer 9 (FIG. 1 shows only 2 secondary windings but there may be more). The invention is based on the recognition that one end of each secondary winding is connected to earth while the other end thereof drives a diode, the winding sense of each winding and the direction of conductance of each diode being chosen to be such that these diodes conduct during the same period as does efficiency diode 7. After smoothing, stabilized supply voltages, for example, at terminal 15 are generated in this manner at the amplitudes and polarities required for the circuit arrangements present in the picture display device. In FIG. 1 the voltage generated at terminal 15 is, for example, positive relative to earth. It is to be noted that the load currents of the supply voltages obtained in this manner cause a reduction of the switching power which is economized by efficiency diode 7. The sum of all diode currents including that of diode 7 is in fact equal to the current which would flow through diode 7 if no secondary winding were wound on transformer 9 and if no simultaneous diode were used. This reduction may be considered an additional advantage of the circuit arrangement according to the invention, for a diode suitable for smaller powers may then be used. However, it will be evident that the overall secondary load must not exceed the primary load since otherwise there is the risk of efficiency diode 7 being blocked so that stabilization of the secondary supply voltages would be out of the question.
It is to be noted that a parabola voltage of line frequency as shown at 28 is produced across the charge capacitor 10 if this capacitor is given a smaller capacitance so that consequently the so-called S-correction is established.
In FIG. 1 charge capacitors are arranged between terminals 15 etc. and earth so as to ensure that the voltages on these points are stabilized direct voltages. If in addition the mean value of the voltage on one of these terminals has been made equal to the effective value of the alternating voltage which is required for heating the filament of the picture display tube present in the picture display device, this voltage is suitable for this heating. This is a further advantage of the invention since the cheap generation of a stabilized filament voltage for the picture display tube has always been a difficult problem in transistorized arrangements.
A further advantage of the picture display device according to the invention is that transformer 9 can function as a separation transformer so that the different secondary windings can be separated from the mains and their lower ends can be connected to ground of the picture display device. The latter step makes it possible to connect a different apparatus such as, for example, a magnetic recording and/or playback apparatus to the picture display device without earth connection problems occurring.
It will now be shown that secondary winding 14 can indeed drive a line deflection circuit so that switching transistor 2 can function as a driver for the line deflection. FIGS. 2a and b show the variation as a function of time of the current i C which flows in the collector of transistor 16 and of the drive voltage v 14 across the terminals of secondary winding 14. During the flyback period (0, t 1 ) transistor 16 must be fully cut off because a high voltage peak is then produced at its collector; voltage v 14 must then be absolutely negative. During the scan period (t 1 , t 4 ) a sawtooth current i C flows through the collector electrode of transistor 16 which current is first negative and then changes its direction. As the circuit arrangement is not free from loss, the instant t 3 when current i C becomes zero lies, as is known, before the middle of the scan period. At the end t 4 of the scan period transistor 16 must be switched off again. However, since transistor 16 is saturated during the scan period and since this transistor must be suitable for high voltages and great powers so that its collector layer is thick, this transistor has a very great excess of charge carriers in both its base and collector layers. The removal of these charge carriers takes a period t s which is not negligible whereafter the transistor is indeed switched off. Thus the fraction δ T of the line period T at which v 14 is positive must end at the latest at the instant (t 4 - t s ) located after the commencement (t = 0) of the previous flyback.
The time δ T may be initiated at any instant t 2 which is located between the end t 1 of the flyback period and the instant t 3 when collector current i C reverses its direction. It is true that emitter current flows through transistor 16 at the instant t 2 , but collector current i C is not influenced thereby, at least not when the supply voltage (= V o ) for line deflection circuit 17 is high enough. All this has been described in the U.S. Pat. No. 3,504,224. The same applies to line deflection circuits wherein the collector base diode does not function as an efficiency diode as is the case in the described circuit 17, but wherein an efficiency diode is arranged between collector and emitter of the line output transistor. In such a case the negative part of the current i C of FIG. 2a represents the current flowing through the said efficiency diode.
After the instant t 3 voltage v 14 must be positive. In other words, the minimum duration of the period T when voltage v 14 must be positive is (t 4 - t s ) - t 3 whilst the maximum duration thereof is (t 4 - t s ) - t 1 . In a television system employing 625 lines per raster the line period t 4 is approximately 64 μus and the flyback period is approximately 12 μus. Without losses in the circuit arrangement instant t 3 would be located approximately 26 μus after the instant t 1 , and with losses a reasonable value is 22 μus which is 34 μus after the commencement of the period. If for safety's sake it is assumed that t s lasts approximately 10 μus, the extreme values of δ T are approximately 20 and 42 μus and consequently the values for δ are approximately 0.31 and 0.66 at a mean value which is equal to approximately 0.49. It was previously stated that a mean value of δ = 0.5 was suitable. Line deflection circuit 17 can therefore indeed be used in combination with the chopper in the manner described, and the relative variation of δ may be (0.66 - 0.31) : 0.49 = 71.5 percent. This is more than necessary to obviate the variations in the mains voltage or in the various loads and to establish the East-West modulation and ripple compensation to be described hereinafter. In fact, if it is assumed that the mains voltage varies between -15 and +10 percent of the nominal value of 220 V, while the 50 Hz ripple voltage which is superimposed on the input voltage V i has a peak-to-peak value of 40 V and V i is nominally 270 V, then the lowest occurring V i is:
0.85 × 270 V - 20 V = 210 V and the highest occurring V i is
1.1 × 270 V + 20 V = 320 V. For an output voltage V o of 135 V the ratio must thus vary between
δ = 135 : 210 = 0.64 and δ = 135 : 320 = 0.42.
A considerable problem presenting itself is that of the simultaneous or non-simultaneous drive of line output transistor 16 with switching transistor 2, it being understood that in case of simultaneous drive both transistors are simultaneously bottomed, that is during the period δ T. This depends on the winding sense of secondary winding 14 relative to that of primary winding 8. In FIG. 1 it has been assumed that the drive takes place simultaneously so that the voltage present across winding 14 has the shape shown in FIG. 2b. This voltage assumes the value n(V i - V o ) in the period δ T and the value -nVo in the period (1 - δ )T, wherein n is the ratio of the number of turns on windings 14 and 8 and wherein V o is maintained constant at nominal mains voltage V o = δ V inom . However, if as a result of an increase or a decrease of the mains voltage V i increases or decreases proportionally therewith, i.e., V i = V i nom + Δ V, the positive portion of V 14 becomes equal to n(V i nom - V o +Δ V) = n [(1 -δ)V i nom +ΔV] = n(0.5 V inom +ΔV) if δ = 0.5 for V i = V i nom. Relatively, this is a variation which is twice as great. For example, if V i nom = 270 V and V o = 135 V, a variation in the mains voltage of from -15 to +10 percent causes a variation of V i of from -40.5 V to +27 V which ranges from -30 to +20 percent of 135 V which is present across winding 8 during the period δ T. The result is that transistor 16 can always be bottomed over a large range of variation. If the signal of FIG. 2b would be applied through a resistor to the ba
se of transistor 16, the base current thereof would have to undergo the same variation while the transistor would already be saturated in case of too low a voltage. In this case it is assumed that transformer 9 is ideal (without loss) and that coil 21 has a small inductance as is explained in the U.S. patent application Ser. No. 737,009 above mentioned. It is therefore found to be desirable to limit the base current of transistor 16.This may be effected by providing a coil 22 having a large value inductance, approximately 100 μH, between winding 14 and the small coil 21. The variation of said base current i b is shown in FIG. 2c but not to the same scale as the collector current of FIG. 2a. During the conducting interval δ T current i b varies as a linear function of time having a final value of wherein L represents the inductance of coil 22. This not only provides the advantage that this final value is not immediately reached, but it can be shown that variation of this final value as a function of the mains voltage has been reduced, for there applies at nominal mains voltage that: If the mains voltage V i = V i nom +Δ V, then ##SPC1## because V i nom = 2 V o . Thus this variation is equal to that of the mains voltage and is not twice as great.
During switching off, t 2 , of transistor 16 coil 22 must exert no influence and coil 21 must exert influence which is achieved by arranging a diode 23 parallel to coil 22. Furthermore the control circuit of transistor 16 in this example comprises the two diodes 24 and 25 as described in U.S. application Ser. No. 26,497 above referred to, wherein one of these diodes, diode 25 in FIG. 1, must be shunted by a resistor.The control circuit of transistor 16 may alternatively be formed as is shown in FIG. 4. In fact, it is known that coil 21 may be replaced by the parallel arrangement of a diode 21' and a resistor 21" by which the inverse current can be limited. To separate the path of the inverse current from that of the forward current the parallel arrangement of a the diode 29' and a resistor 29" must then be present. This leads to the circuit arrangement shown in the upper part of FIG. 4. This circuit arrangement may now be simplified if it is noted that diodes 25 and 21' on the one hand and diodes 23 and 29' on the other hand are series-arranged. The result is shown in the lower part of FIG. 4 which, as compared with the circuit arrangement of FIG. 1, employs one coil less and an additional resistor.
Transistors of the npn type are used in FIG. 3. If transistors of the pnp type are used, the relevant efficiency diodes must of course be reversed.
In this connection it is to be noted that it is possible to obtain an output voltage V o with the aid of the modifications according to FIGS. 3b, c and d, which voltage is higher than input voltage V i . These modifications may be used in countries such as, for example, the United of America or France where the nominal mains voltage is 117 or 110 V without having to modify the rest of the circuit arrangement.
The above-mentioned remark regarding the sum of the diode currents only applies, however, for the modifications shown in FIGS. 3a and d.
The line deflection circuit itself is also safeguarded: in fact, if something goes wrong in the supply, the driver voltage of the line deflection circuit drops out because the switching voltage across the terminals of primary winding 8 is no longer present so that the deflection stops. This particularly happens when switching transistor 2 starts to constitute a short-circuit between emitter and collector with the result that the supply voltage V o for the line deflection circuit in the case of FIG. 1 becomes higher, namely equal to V i . However, the line output transformer is now cut off and is therefore also safe as well as the picture display tube and other parts of the display device which are fed by terminal 15 or the like. However, this only applies to the circuit arrangement according to FIG. 1 or 3a.
Capacitor 27 is arranged parallel to efficiency diode 7 so as to reduce the dissipation in switching transistor 2. In fact, if transistor 2 is switched off by the pulsatory control voltage, its collector current decreases and its collector-emitter voltage increases simultaneously so that the dissipated power is not negligible before the collector current has becomes zero. If efficiency diode 7 is shunted by capacitor 27 the increase of the collector-emitter voltage is delayed i.e., this voltage does not assume high values until the collector current has already been reduced. It is true that in that case the dissipation in transistor 2 slightly increases when it is switched on by the pulsatory control voltage but on the other hand since the current flowing through diode 7 has decreased due to the presence of the secondary windings, its inverse current is also reduced when transistor 2 is switched on and hence its dissipation has become smaller. In addition it is advantageous to delay these switching-on and switching-off periods to a slight extent because the switching pulses then contain fewer Fourier components of high frequency which may cause interferences in the picture display device and which may give rise to visible interferences on the screen of the display tube. These interferences occupy a fixed position on the displayed image because the switching frequency is the line frequency which is less disturbing to the viewer. In a practical circuit wherein the line frequency is 15,625 Hz and wherein switching transistor 2 is an experimental type suitable for a maximum of 350 V collector-emitter voltage or 1 A collector current and wherein efficiency diode 7 is of the Philips type BA 148 the capacitance of capacitor 27 is approximately 680 pF whilst the load is 70 W on the primary and 20 W on the secondary side of transformer 9. The collector dissipation upon switching off is 0.3 W (2.5 times smaller than without capacitor 27) and 0.7 W upon switching on.
A practical embodiment of the described example with the reference numerals given provides an output for the supply of approximately 85 percent at a total load of 90 W, the internal resistance for direct current loads being 1.5 ohms and for pulsatory currents being approximately 10 ohms. In case of a variation of ± 10 percent of the mains voltage, output voltage V o is stable within 0.4 V. Under the nominal circumstances the collector dissipation of switching transistor 2 is approximately 2.5 W.
Since the internal resistance of the supply is so small, it can be used advantageously, for example, at terminal 15 for supplying a class-B audio amplifier which forms part of the display device. Such an amplifier has the known advantages that its dissipation is directly proportional to the amplitude of the sound to be reproduced and that its output is higher than that of a class-A amplifier. On the other hand a class-A amplifier consumes a substantially constant power so that the internal resistance of the supply voltage source is of little importance. However, if this source is highly resistive, the supply voltage is modulated in the case of a class-B amplifier by the audio information when the sound intensity is great which may detrimentally influence other parts of the display device. This drawback is prevented by means of the supply according to the invention.
The 50 Hz ripple voltage which is superimposed on the rectified input voltage V i is compensated by comparison circuit 12 and modulator 5 since this ripple voltage may be considered to be a variation of input voltage V i . A further compensation is obtained by applying a portion of this ripple voltage with suitable polarity to comparison circuit 12. It is then sufficient to have a lower value for the smoothing capacitor which forms part of rectifier circuit 1 (see FIG. 3). The parabola voltage 28 of field frequency originating from the field time base is applied to the same circuit 12 so as to correct the East-West pincushion distortion.
BANG & OLUFSEN BEOVISION 7702 CHASSIS SERIES 77XX 30AX - VIDEO CHROMA PROCESSING WITH TDA3300 (MOTOROLA)
TDA3300 3301 TV COLOR PROCESSOR
This device will accept a PAL or NTSC composite video signal and output the
three color signals, needing only a simple driver amplifier to interface to the pic-
ture tube. The provision of high bandwidth on-screen display inputs makes it
suitable for text display, TV games, cameras, etc. The TDA3301 B has user con»
trol laws, and also a phase shift control which operates in PAL, as well as NTSC.
0 Automatic Black Level Setup
0 Beam Current Limiting
0 Uses Inexpensive 4.43 MHZ to 3.58 MHz Crystal
0 No Oscillator Adjustment Required
0 Three OSD Inputs Plus Fast Blanking Input
0 Four DC, High Impedance User Controls
0 lnterlaces with TDA33030B SECAM Adaptor
0 Single 12 V Supply
0 Low Dissipation, Typically 600 mW
The brilliance control operates by adding a pedestal to the output
signals. The amplitude of the pedestal is controlled by Pin 30.
During CRT beam current sampling a standard pedestal is
substituted, its value being equivalent tothe value given by V30 Nom
Brightness at black level with V30 Nom is given by the sum of three gun
currents at the sampling level, i.e. 3x20 |.1A with 100 k reference
resistors on Pins 16, 19, and 22.
During picture blanking the brilliance pedestal is zero; therefore, the
output voltage during blanking is always the minimum brilliance black
level (Note: Signal channels are also gain blanked).
Chrominance Decoder
The chrominance decoder section of the TDA3301 B
consists of the following blocks:
Phase-locked reference oscillator;
Phase-locked 90 degree servo loop;
U and V axis decoders
ACC detector and identification detector; .
Identification circuits and PAL bistable; .
Color difference filters and matrixes with fast blanking
Circuits.
The major design considerations apart from optimum
performance were:
o A minimum number of factory adjustments,
o A minimum number of external components,
0 Compatibility with SECAM adapter TDA3030B,
0 Low dissipation,
0 Use of a standard 4.433618 Mhz crystal rather
than a 2.0 fc crystal with a divider.
The crystal VCO is of the phase shift variety in which the
frequency is controlled by varying the phase of the feedback.
A great deal of care was taken to ensure that the oscillator loop
gain and the crystal loading impedance were held constant in
order to ensure that the circuit functions well with low grade
crystal (crystals having high magnitude spurious responses
can cause bad phase jitter). lt is also necessary to ensure that
the gain at third harmonic is low enough to ensure absence of
oscillation at this frequency.
It can be seen that the
necessary 1 45°C phase shift is obtained by variable addition
ol two currents I1 and I2 which are then fed into the load
resistance of the crystal tuned circuit R1. Feedback is taken
from the crystal load capacitance which gives a voltage of VF
lagging the crystal current by 90°.
The RC network in the T1 collector causes I1 to lag the
collector current of T1 by 45°.
For SECAM operation, the currents I1 and I2 are added
together in a fixed ratio giving a frequency close to nominal.
When decoding PAL there are two departures from normal
chroma reference regeneration practice:
a) The loop is locked to the burst entering from the PAL
delay line matrix U channel and hence there is no
alternating component. A small improvement in signal
noise ratio is gained but more important is that the loop
filter is not compromised by the 7.8 kHz component
normally required at this point for PAL identification
b) The H/2 switching of the oscillator phase is carried out
before the phase detector. This implies any error signal
from the phase detector is a signal at 7.8 kHz and not dc.
A commutator at the phase detector output also driven
from the PAL bistable coverts this ac signal to a dc prior
to the loop filter. The purpose ot this is that constant
offsets in the phase detector are converted by the
commutator to a signal at 7.8 kHz which is integrated to
zero and does not give a phase error.
When used for decoding NTSC the bistable is inhibited, and
slightly less accurate phasing is achieved; however, as a hue
control is used on NTSC this cannot be considered to be a
serious disadvantage.
90° Reference Generation
To generate the U axis reference a variable all-pass network
is utilized in a servo loop. The output of the all-pass network
is compared with the oscillator output with a phase detector of
which the output is filtered and corrects the operating point of
the variable all»pass network .
As with the reference loop the oscillator signal is taken after
the H/2 phase switch and a commutator inserted before the
filter so that constant phase detector errors are cancelled.
For SECAM operation the loop filter is grounded causing
near zero phase shift so that the two synchronous detectors
work in phase and not in quadralure.
The use of a 4.4 MHz oscillator and a servo loop to generate
the required 90° reference signal allows the use of a standard,
high volume, low cost crystal and gives an extremely accurate
90° which may be easily switched to 0° for decoding AM
SECAM generated by the TDA3030B adapter.
ACC and Identification Detectors
During burst gate time the output components of the U and
also the V demodulators are steered into PNP emitters. One
collector current of each PNP pair is mirrored and balanced
against its twin giving push-pull current sources for driving the
ACC and the identification filter capacitors.
The identification detector is given an internal offset by
making the NPN current mirror emitter resistors unequal. The
resistors are offset by 5% such that the identification detector
pulls up on its filter capacitor with zero signal.
Identification
See Figure 11 for definitions.
Monochrome I1 > I2
PAL ldent. OK I1 < lg
PAL ldent_ X l1 > I2
NTSC I3 > I2
Only for correctly identified PAL signal is the capacitor
voltage held low since I2 is then greater than I1.
For monochrome and incorrectly identified PAL signals l1>l2
hence voltage VC rises with each burst gate pulse.
When V,ef1 is exceeded by 0.7 V Latch 1 is made to conduct
which increases the rate of voltage rise on C. Maximum
current is limited by R1.
When Vref2 is exceeded by 0.7 V then Latch 2 is made to
conduct until C is completely discharged and the current drops
to a value insufficient to hold on Latch 2.
As Latch 2 turns on Latch 1 must turn off.
Latch 2 turning on gives extra trigger pulse to bistable to
correct identification.
The inhibit line on Latch 2 restricts its conduction to alternate
lines as controlled by the bistable. This function allows the
SECAM switching line to inhibit the bistable operation by firing
Latch 2 in the correct phase for SECAM. For NTSC, Latch 2
is fired by a current injected on Pin 6.
lf the voltage on C is greater than 1.4 V, then the saturation
is held down. Only for SECAM/NTSC with Latch 2 on, or
correctly identified PAL, can the saturation control be
anywhere but minimum.
NTSC Switch
NTSC operation is selected when current (I3) is injected into
Pin 6. On the TDA33O1 B this current must be derived
externally by connecting Pin 6 to +12 V via a 27 k resistor (as
on TDA33OOB). For normal PAL operation Pin 40 should be
connected to +12 V and Pin 6 to the filter capacitor.
4 Color Difference Matrixing, Color Killing,
and Chroma Blanking
During picture time the two demodulators feed simple RC
filters with emitter follower outputs. Color killing and blanking
is performed by lifting these outputs to a voltage above the
maximum value that the color difference signal could supply.
The color difference matrixing is performed by two
differential amplifiers, each with one side split to give the
correct values of the -(B-Y) and -(Ft-Y) signals. These are
added to give the (G-Y) signal.
The three color difference signals are then taken to the
virtual grounds of the video output stages together with
luminance signal.
Sandcastle Selection
The TDA3301B may be used with a two level sandcastle
and a separate frame pulse to Pin 28, or with only a three level
(super) sandcastle. In the latter case, a resistor of 1.0 MQ is
necessary from + 12 V to Pin 28 and a 70 pF capacitor from
Pin 28 to ground.
In order to control beam current sampling at the beginning
of each frame scan, two edge triggered flip-flops are used.
The output K ofthe first flip-flop A is used to clock the second
tlip-flop B. Clocking of A by the burst gate is inhibited by a count
of A.B.
The count sequence can only be initiated by the trailing
edge of the frame pulse. ln order to provide control signals for:
Luma/Chroma blanking
Beam current sampling
On-screen display blanking
Brilliance control
The appropriate flip-flop outputs ar matrixed with sandcastle
and frame signals by an emitter-follower matrix.
Video Output Sections
Each video output stage consists of a feedback amplifier in A further drive current is used to control the DC operating
which the input signal is a current drive to the virtual earth from point; this is derived from the sample and hold stage which
the luminance, color difference and on-screen display stages. samples the beam current after frame flyback.
TDA1170 vertical deflection FRAME DEFLECTION INTEGRATED CIRCUIT
GENERAL DESCRIPTION f The TDA1170 and TDA1270 are monolithic integrated
circuits designed for use in TV vertical deflection systems. They are manufactured using
the Fairchild Planar* process.
Both devices are supplied in the 12-pin plastic power package with the heat sink fins bent
for insertion into the printed circuit board.
The TDA1170 is designed primarily for large and small screen black and white TV
receivers and industrial TV monitors. The TDA1270 is designed primarily for driving
complementary vertical deflection output stages in color TV receivers and industrial
monitors.
APPLICATION INFORMATION (TDA1170)
The vertical oscillator is directly synchronized by the sync pulses (positive or negative); therefore its free
running frequency must be lower than the sync frequency. The use of current feedback causes the yoke
current to be independent of yoke resistance variations due to thermal effects, Therefore no thermistor is
required in series with the yoke. The flyback generator applies a voltage, about twice the supply voltage, to
the yoke. This produces a short flyback time together with a high useful power to dissipated power
ratio.
1. A transformerless output vertical deflection circuit, comprising a vertical oscillator circuit for generating a vertical pulse train in response to vertical synchronizing pulses applied thereto, a sawtooth signal generator for generating a series of sawtooth signals, each cycle of said sawtooth signal including a pulse component, a vertical output circuit coupled to said sawtooth generator for amplifying said sawtooth signal including said pulse component and loading a vertical deflection coil, and stabilizing means connected between said vertical oscillator and said sawtooth signal generator for varying the width of the pulse component which is to be fed to said vertical output circuit in response to the average level of DC output voltage fed from the vertical output circuit. 2. A transformerless output vertical deflection circuit claimed in claim 1, wherein said stabilizing means comprises a control circuit means for receiving a series of pulses from the vertical oscillator and a feedback signal from the vertical output circuit and for varying the width of the pulse which is to be fed to the vertical output circuit in response to a DC control signal proportional to the width of the pulse component included in the vertical output signal and smoothing circuit means connected between said vertical output circuit and said stabalizing means for smoothing said feedback signal. 3. A transformerless output vertical deflection circuit claimed in claim 2, wherein said control circuit comprises a charging capacitor which is parallel to a transistor, said transistor being switched on in response to pulses fed from the vertical oscillator wherein said capacitor is charged by the voltage fed from said smoothing circuit, and discharged in response to conduction of the transistor, a differential amplifier circuit which receives the voltage on said capacitor and a fixed voltage, and a gating circuit for producing a pulse which has a width equal to the difference between the width of the pulse fed from the vertical oscillator circuit and the width of pulse fed from the differential amplifier circuit. 4. A transformerless output vertical deflection circuit claimed in claim 2, wherein said control circuit comprises a capacitor which is charged by a fixed power source and is discharged by means of a switching transistor operated by the pulses fed from the vertical oscillator circuit and a differential amplifier circuit receiving the voltage on the capacitor and the output of said smoothing circuit. 5. A transformable output vertical deflection circuit comprising a vertical oscillator for generating a vertical pulse train in response to vertical synchronizing pulses applied thereto, a sawtooth signal generator for generating a series of sawtooth signals each cycle of said sawtooth signal including a pulse component, a vertical output circuit for amplifying said sawtooth signal including said pulse component and loading a vertical deflection coil, and pulse stabilizing means coupled between the vertical oscillator circuit a
Description:
BACKGROUND OF THE INVENTIONThe present invention relates to a vertical deflection circuit for use in a television receiver and, more particularly, to a vertical deflection circuit of a type wherein no vertical output transformer is employed. This type of vertical deflection circuit with no output transformer is generally referred to as an OTL (Output Transformerless) type vertical deflection circuit.
It is known that variation of the pulse width of the flyback pulse produced in a vertical output stage of the vertical deflection circuit is the cause in the raster on the television picture tube, of a white bar, flicker, jitter, line crowding and/or other raster disorders. In addition thereto, in the vertical deflection output circuit where the output stage is composed of a single-ended push-pull amplifier having a vertical output transistor, an excessive load is often imposed on the output transistor and, in an extreme case, the output transistor is destroyed.
BANG & OLUFSEN BEOVISION 7702 CHASSIS SERIES 77XX 30AX Television receiver including a teletext decoder circuit :
In a teletext decoder circuit the character generator supplies picture elements at a rate of nominally approximately 6 MHz under the control of display pulses occurring at the same rate. These display pulses are derived from reference clock pulses which occur at a rate which is not a rational multiple of 6 MHz. The character generator comprises a generator circuit which receives the reference clock pulses and selects, from each series of N reference clock pulses, as many pulses as correspond to the number of horizontal picture elements constituting a character, while the time interval of N reference clock pulses corresponds to the desired width of the characters to be displayed. The character generator supplies picture elements of distinct length, while the length of a picture element is dependent on the ordinal number of this picture element in the character.
1. A receiver for television signal s including a teletext decoder circuit for decoding teletext signals constituted by character codes which are transmitted in the television signal, and comprising:
a video input circuit receiving the television signal and converting it into a serial data flow;
an acquisition circuit for receiving the serial data flow supplied by the video input circuit and selecting that part therefrom which corresponds to the teletext page described by the viewer;
a character generator comprising:
a memory medium addressed by the character codes which together represent the teletext page desired by the user and which in response to each character code successively supply m2 series of m1 simultaneously occurring character picture element codes each indicating wether a corresponding picture element of the character must be displayed in the foreground colour or in the background colour;
a generator circuit receiving a series of reference clock pulses and deriving display clock pulses therefrom;
a converter circuit receiving each series of m1 simultaneously occurring character picture element codes as well as the display clock pulses for supplying the m1 character picture element codes of a series one after the other and at the display clock pulse rate;
a display control circuit receiving the serial character picture element codes and converting each into an R, a G and a B signal for the relevant picture element of the character to be displayed;
characterized in that
the generator circuit is adapted to partition the series of reference clock pulses applied thereto into groups of N reference clock pulses each, in which N reference clock pulse periods correspond to the desired width of a character to be displayed, and to select from each such group m1 clock pulse to function as display clock pulses;
the converter circuit is adapted to supply each character picture element code during a period which is dependent on the ordinal number of the character picture element code in the series of m1 character picture element codes.
2. A character generator for use in a receiver teletext claim 1, comprising:
a memory medium which is addressable by character codes and successively applies m2 series of m1 simultaneously occurring character picture element codes in response to a character code applied as an address thereto, each character picture element code indicating whether a corresponding picture element of the character must be displayed in the foreground colour or in the background colour;
a generator circuit receiving a series of reference clock pulses and deriving display clock pulses therefrom;
a converter circuit receiving each series of m1 simultaneously occurring character picture element codes and the display clock pulses for supplying the m1 character picture element codes of the series one after the other at the display clock pulse rate;
a display control circuit receiving the serial character picture element codes and converting each into an R, a G and a B signal for the relevant picture element of the character to be displayed; characterized in that
the generator circuit is adapted to partition the series of reference clock pulses applied thereto into groups of N reference clock pulses each, in which N reference clock pulse periods correspond to the desired width of a character to be displayed, and to select from each such group m1 clock pulses to function as display clock pulses;
the converter circuit is adapted to supply each character picture element code during a period which is dependent on the ordinal number of the character picture element code in the series of m1 character picture element codes.
Description:
BACKGROUND OF THE INVENTION1. Field of the Invention
The invention generally relates to receivers for television signals and more particularly to receivers including teletext decoders for use in a teletext transmission system.
2. Description of the Prior Art
As is generally known, in a teletext transmission system, a number of pages is transmitted from a transmitter to the receiver in a predetermined cyclic sequence. Such a page comprises a plurality of lines and each line comprises a plurality of alphanumerical characters. A character code is assigned to each of these characters and all character codes are transmitted in those (or a number of those) television lines which are not used for the transmission of video signals. These television lines are usually referred to as data lines.
Nowadays the teletext transmission system is based on the standard known as "World System Teletext", abbreviates WST. According to this standard each page has 24 lines and each line comprises 40 characters. Furthermore each data line comprises, inter alia, a line number (in a binary form) and the 40 character codes of the 40 characters of that line.
A receiver which is suitable for use in such a teletext transmission system includes a teletext decoder enabling a user to select a predetermined page for display on a screen. As is indicated in, for example, Reference 1, a teletext decoder comprises, inter alia, a video input circuit (VIP) which receives the received television signal and converts it into a serial data flow. This flow is subsequently applied to an acquisition circuit which selects those data which are required for building up the page desired by the user. The 40 character codes of each teletext line are stored in a page memory which at a given moment thus comprises all character codes of the desired page. These character codes are subsequently applied one after the other and line by line to a character generator which supplies such output signals that the said characters become visible when signals are applied to a display.
For the purpose of display each character is considered as a matrix of m 1 ×m 2 picture elements which are displayed row by row on the screen. Each picture element corresponds to a line section having a predetermined length (measured with respect to time); for example, qμsec. Since each line of a page comprises 40 characters and each character has a width of m 1 qμsec, each line has a length of 40 m 1 μsec. In practice a length of approximately 36 to 44 μsec appears to be a good choice. In the teletext decoder described in Reference 1 line length of 40 μsec and a character width of 1 μsec at m 1 =6 have been chosen.
The central part of the character generator is constituted by a memory which is sub-divided into a number of submemories, for example, one for each character. Each sub-memory then comprises m 1 ×m 2 memory locations each corresponding to a picture element and the contents of each memory location define whether the relevant picture element must be displayed in the so-called foreground colour or in the so-called background colour. The contents of such a code memory location will be referred to as character picture element code. This memory is each time addressed by a character code and a row code. The character code selects the sub-memory and the row code selects the row of m 1 memory elements whose contents are desired. The memory thus supplies groups of m simultaneously occurring character picture element codes which are applied to a converter circuit. This converter circuit usually includes a buffer circuit for temporarily storing the m 1 substantially presented character picture element codes. It is controlled by display clock pulses occurring at a given rate and being supplied by a generator circuit. It also supplies the m 1 character picture element codes, which are stored in the buffer circuit, one after the other and at a rate of the display clock pulses. The serial character picture element codes thus obtained are applied to a display control circuit converting each character picture element code into an R, a G and a B signal value for the relevant picture element, which signal values are applied to the display device (for example, display tube).
OBJECT AND SUMMARY OF THE INVENTION
A particular object of the invention is to provide a teletext decoder circuit which does not include a separate 6 MHz oscillator but in which for other reasons clock pulses, which are already present in the television receiver, can be used as reference clock pulses, which reference clock pulses generally do not occur at a rate which is a rational multiple of the rate at which the display clock pulses must occur.
According to the invention,
the generator circuit is adapted to partition the series of reference clock pulses applied thereto into groups of N reference clock pulses each, in which N clock pulse periods correspond to the desired width of a character to be displayed, and to select of each such group m 1 clockpulses to function as display clock pulses;
the converter circuit is adapted to supply each character picture element code during a period which is dependent on the ordinal number of the character picture element code in the series of m 1 character picture element codes.
The invention has resulted from research into teletext decoder circuits for use in the field of digital video signal processing in which a 13.5 MHz clock generator is provided for sampling the video signal. The 13.5 MHz clock pulses supplied by this clock generator are now used as reference clock pulses. The generator circuit partitions these reference clock pulses into groups of N clock pulses periods each. The width of such a group is equal to the desired character width. Since a character comprises rows of m 1 picture elements, m 1 reference clock pulses are selected from such a group which clock pulses are distributed over this group as regularly as possible. Since the mutual distance between the display clock pulses thus obtained is not constantly the same, further measures will have to be taken to prevent undesired gaps from occurring between successive picture elements when a character is displayed. Since the length of a picture element is determined by the period during which the converter circuit supplies a given character picture element code, this period has been rendered dependent on the ordinal number of the character picture element code in the series of m 1 character picture element codes.
REFERENCES
1. Computer-controlled teletext, J. R. Kinghorn; Electronic Components and Applications, Vol. 6, No. 1, 1984, pages 15-29.
2. Video and associated systems, Bipolar, MOS; Types MAB 8031 AH to TDA 1521: Philips' Data Handbook, Integrated circuits, Book ICO2a 1986, pages 374,375.
3. Bipolar IC's for video equipment; Philips' Data Handbook, Integrated Circuits Part 2, January 1983.
4. IC' for digital systems in radio, audio and video equipment, Philips' Data Handbook, Integrated Circuits Part 3, September 1982.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 shows the general structure of a television receiver including a teletext decoder circuit;
FIG. 2 shows different matrices of picture elements constituting a character;
FIG. 3 shows diagrammatically the general structure of a character generator;
FIG. 4 shows an embodiment of a converter circuit and a generator circuit for use in the character generator shown in FIG. 3, and
FIG. 5 shows some time diagrams to explain its operation;
FIG. 6 shows another embodiment of a converter circuit and a generator circuit for use in the character generator shown in FIG. 3, and
FIG. 7 shows some time diagrams to explain its operation;
FIG. 8 shows a modification of the converter circuit shown in FIG. 6, adapted to round the characters.
EXPLANATION OF THE INVENTION
General structure of a TV receiver
FIG. 1 shows diagra
mmatically the general structure of a colour television receiver. It has an antenna input 1 connected to an antenna 2 receiving a television signal modulated on a high-frequency carrier, which signal is processed in a plurality of processing circuits. More particularly, it is applied to a tuning circuit 23 (tuner or channel selector). This circuit receives a band selection voltage V B in order to enable the receiver to be tuned to a frequency within one of the frequency bands VHF1, VHF2, UHF, etc. The tuning circuit also receives a tuning voltage V T with which the receiver is tuned to the desired frequency within the selected frequency band.This tuning circuit 3 supplies an oscillator signal having a frequency of f OSC on the one hand and an intermediate frequency video signal IF on the other hand. The latter signal is applied to an intermediate frequency amplification and demodulation circuit 4 supplying a baseband composite video signal CVBS. The Philips IC TDA 2540 described in Reference 3 can be used for this circuit 4.
The video signal CVBS is also applied to a teletext decoder circuit 9. This circuit comprises a video input circuit 91 which receives the video signal CVBS and converts it into a serial data flow. This flow is applied to a circuit 92 which will be referred to as teletext acquisition and control circuit (abbreviated TAC circuit). This circuit selects that part of the data applied thereto which corresponds to the teletext page desired by the viewer. The character codes defined by these data are stored in a memory 93 which is generally referred to as page memory and are applied from this memory to a character generator 94 supplying an R, a G and a B signal for each picture element of the screen 8. It is to be noted that this character generator 94 also supplies the switching signal BLK in this embodiment. As is shown in the Figure, the teletext acquisition and control circuit 92, the page memory 93 and the character generator 94 are controlled by a control circuit 95 which receives reference clock pulses with a frequency f o from a reference clock oscillator 10. The control circuit 95 has such a structure that it supplies the same reference clock pulses from its output 951 with a phase which may be slightly shifted with respect to the reference clock pulses supplied by the clock pulse oscillator 10 itself. The reference clock pulses occurring at this output 951 will be denoted by TR.
The Philips IC SAA 5030 may be used as video input circuits 91, the Philips IC SAA 5040 may be used as teletext acquisition and control circuit, a 1K8 RAM may be used as page memory, a modified version of the Philips IC SAA 5050 may be used as character generator 94 and a modified version of the Philips IC SAA 5020 may be used as control circuit 95, the obvious modification being a result of the fact that this IC is originally intended to receive reference clock pulses at a rate of 6 MHz for which 13.5 MHz has now been taken.
The memory medium 14 is used, for example, for storing tuning data of a plurality of preselected transmitter stations (or programs). When such tuning data are applied to the interface circuit 13 under the control of the microcomputer 12, this circuit supplies a given band selection voltage V B and a given tuning voltage V T so that the receiver is tuned to the desired transmitter.
For operating this television receiver an operating system is provided in the form of a remote control system comprising a hand-held apparatus 16 and a local receiver 17. This receiver 17 has an output which is connected to an input (usually the "interrupt" input) of the microcomputer 12. It may be constituted by the Philips IC TDB 2033 described in Reference 4 and is then intended for receiving infrared signals which are transmitted by the hand-held apparatus 16.
The hand-held apparatus 16 comprises an operating panel 161 with a plurality of figure keys denoted by the FIGS. 0 to 9 inclusive, a colour saturation key SAT, a brightness key BRI, a volume key VOL, and a teletext key TXT. These keys are coupled to a transmitter circuit 162 for which, for example, the Philips IC SAA 3004, which has extensively been described in Reference 4, can be used. When a key is depressed, a code which is specific of that key is generated by the transmitter circuit 162, which code is transferred via an infrared carrier to the local receiver 17, demodulated in this receiver and subsequently presented to the microcomputer 12. This microcomputer thus receiv
es operating instructions and activates, via the bus system 11, one of the circuits connected thereto. It is to be noted that an operating instruction may be a single instruction, that is to say, it is complete after depressing only one key. It may also be multiple, that is to say, it is not complete until two or more keys have been depressed. This situation occurs, for example, when the receiver is operating in the teletext mode. Operation of figure keys then only yields a complete operating instruction when, for example, three figure keys have been depressed. As is known, such a combination results in the page number of the desired teletext page.The character generator
As already stated, a character is a matrix comprising m 2 rows of m 1 picture elements each. Each picture element corresponds to a line section of a predetermined length (measured with respect to time); for example, q/μsec. Such a matrix is indicated at A in FIG. 2 for m 1 =6 and m 2 =10. More particularly this is the matrix of a dummy character. The character for the letter A is indicated at B in the same FIG. 2. It is to be noted that the forty characters constituting a line of teletext page are contiguous to one another without any interspace. The sixth column of the matrix then ensures the required spacing between the successive letters and figures.
FIG. 3 shows diagrammatically the general structure of the character generator described in Reference 2 and adapted to supply a set of R, G and B signals for each picture element of the character. This character generator comprises a buffer 940 which receives the character codes from memory 93 (see FIG. 1). These character codes address a sub-memory in a memory medium 941, which sub-memory consists of m 1 ×m 2 memory elements each comprising a character picture element code. Each m 1 ×m 2 char
acter picture element code corresponds to a picture element of the character and defines, as already stated, whether the relevation picture element must be displayed in the so-called foreground colour or in the so-called background colour. Such a character picture element code has the logic value "0" or "1". A "0" means that the corresponding picture element must be displayed in the background colour (for example, white). The "1" means that the corresponding picture element must be displayed in the foreground colour (for example, black or blue). At C in FIG. 2 there is indicated, the contents of the sub-memory for the character shown at B in FIG. 2.The addressed sub-memory is read now by row under the control of a character row signal LOSE. More particularly, all first rows are read of the sub-memories of the forty characters of a teletext line, subsequently all second rows are read, then all third rows are read and so forth until finally all tenth rows are read.
The six character element codes of a row will hereinafter be referred to as CH(1), CH(2), . . . CH(6). They are made available in parallel by the memory medium 941 and are applied to a converter circuit 942 operating as a parallel-series converter. In addition to the six character picture element codes it receives display clock pulses DCL and applies these six character picture element codes one by one at the rate of the display clock pulses to a display control circuit 943 which converts each character picture element code into a set of R, G, B signals.
The display clock pulses DCL and the character row signal LOSE are supplied in known manner (see Reference 2, page 391) by a generator circuit 944 which receives the reference clock pulses TR from the control circuit 95 (see FIG. 1), which reference clock pulses have a rate f 0 . In the character generator described in Reference 2, page 391, f 0 is 6 MHz and the display clock pulses DCL occur at the same rate. The converter circuit thus supplies the separate character picture element codes at a rate of 6 MHz. The picture elements shown at A and B therefore have a length of 1/6 μsec each and a character thus has a width of 1 μsec.When the rate of the reference clock pulses increases, the rate of the display clock pulses also increases and the character width decreases. Without changing the character width the above-described character generator can also be used without any essential changes if the rate of the reference clock pulses is an integral multiple of 6 MHz. In that case the desired display clock pulses can e derived from the reference clock pulses by means of a divider circuit with an integral dividing number. However, there is a complication if f 0 is not a rational multiple of 6 MHz, for example, if f 0 =13.5 MHz and each character nevertheless must have a width of substantially 1 μsec. Two generator circuits and a plurality of converter circuits suitable for use in the character generator shown in FIG. 3 and withstanding the above-mentioned complication will be described hereinafter.
FIG. 4 shows an embodiment of the generator circuit 944 and the converter circuit 942. The reference clock pulses TR are assumed to occur at a rate of 13.5 MHz. To derive the desired display clock pulses from these reference clock pulses, the generator circuit 944 comprises a modulo-N-counter circuit 9441 which receives the 13.5 MHz reference clock pulses TR indicated at A in FIG. 5. The quantity N is chosen to be such that N clock pulse periods of the reference clock pulses substantially correspond to the desired character width of, for example, 1 μsec. This is the case for N=14, which yields a character width of 1.04 μsec.
An encoding network 9442 comprising two output lines 9443 and 9444 is connected to this modulo-N-counter circuit 9441. This encoding network 9442 each time supplies a display clock pulse in response to the first, the third, the sixth, the eighth, the eleventh and the thirteenth reference clock pulse in a group of fourteen reference clock pulses. More particularly the display clock pulse, which is obtained each time in response to the first reference clock pulse of a group, is applied to the output line 9443, whilst the other display clock pulses are applied to the output line 9444. Thus, the pulse series shown at B and C in FIG. 5 occur at these output lines 9443 and 9444, respectively.
The converter circuit 942 is constituted by a shift register circuit 9420 comprising six shift register elements each being suitable for storing a character picture element code CH(.) which is supplied by the memory medium 941 (see FIG. 3). This shift register circuit 9420 has a load pulse input 9421 and a shift pulse input 9422. The load pulse input 9421 is connected to the output line 9443 of the encoding network 9442 and thus receives the display clock pulses indicated at B in FIG. 5. The shift pulse input 9422 is connected to the output line 9444 of the encoding network 9442 and thus receives the display clock pulses indicated at C in FIG. 5.
This converter circuit operates as follows. Whenever a display clock pulse occurs at the load pulse input 9421, the six character picture element codes CH(.) are loaded into the shift register circuit 9420. The first character picture element code CH(1) thereby becomes immediately available at the output. The contents of the shift register el
ements are shifted one position in the direction of the output by each display clock pulse at the shift pulse input 9422.Since the display clock pulses occur at mutually unequal distances, the time interval during which a character picture element code is available at the output of the shift register circuit is longer for the one character picture element code than for the other. This is shown in the time diagrams D of FIG. 5. More particularly the diagrams show for each character picture element code CH(.) during which reference clock pulse periods the code is available at the output of the shift register circuit. The result is that the picture elements from which the character is built up upon display also have unequal lengths as is indicated at D and E in FIG. 2.
The same character display is obtained by implementing the converter circuit 942 and the generator circuit 944 in the way shown in FIG. 6. The generator circuit 944 again comprises the modulo-N-counter circuit 9441 with N=14 which receives the 13.5 MHz reference clock pulses TR shown at A in FIG. 7. An encoding network 9445 is also connected to this counter circuit, which network now comprises six output lines 9446(.). This encoding network 9445 again supplies a display clock pulse in response to the first, the third, the sixth, the eighth, the eleventh and the thirteenth reference clock pulse of a group of fourteen reference clock pulses, which display clock pulses are applied to the respective output lines 9446(1), . . . , 9446(6). Thus, the pulse series indicated at B, C, D, E, F and G in FIG. 7 occur at these outputs.
The converter circuit 942 has six latches 9423(.) each adapted to store a character picture element code CH(.). The outputs of these latches are connected to inputs of respective AND gate circuits 9424(.). Their outputs are connected to inputs of an OR gate circuit 9425. The AND gate circuit is 9424(.) are controlled by the control signals S(1) to S(6), respectively, which are derived by means of a pulse widening circuit 9426 from the display clock pulses occurring at the output lines 9446(.) of the encoding network 9445 and which are also shown in FIG. 7. Such a control signal S(i) determines how long the character picture element code CH(i) is presented to the output of the OR gate circuit 9425 and hence determines the length of the different picture elements of the character on the display screen.
As is shown in FIG. 6, the pulse widening circuit 9426 may be constituted by a plurality of JK flip-flops 9426(.) which are connected to the output lines of the encoding network 944, in the manner shown in the Figure. It is to be noted that the function of the pulse widening circuit 9426 may also be included in the encoding network 9445. In that case this function may be realized in a different manner.In the above-described embodiments of the converter circuit 942 and the generator circuit 944 the character generator supplies exactly contiguous picture elements on the display screen. This means that the one picture elements begins immediately after the previous picture element has ended. The result is that round and diagonal shapes become vague. It is therefore common practice to realize a rounding for such shapes. This rounding can be realized with the converter circuit shown in FIGS. 4 and 6
by ensuring that two consecutive picture elements partly overlap each other. This is realized in the converter circuit shown in FIG. 4 by means of a rounding circuit 9427 which receives the character picture element codes occurring at the output of the shift register circuit 9420. This rounding circuit 9427 comprises an OR gate 9427(1) and a D flip-flop 9427(2). The T input of this flip-flop receives the clock pulses shown at E in FIG. 5, which pulses are derived from the reference clock pulses TR by means of a delay circuit 9427(3). This circuit has a delay time t 0 for which a value in the time diagram indicated at E in FIG. 5 is chosen which corresponds to half a clock pulse period of the reference cock pulses. The character picture element codes supplied by the shift register circuit 9420 are now applied directly and via the D flip-flop 9427(2) to the OR gate which thereby supplies the six character picture element codes CH(.) in the time intervals as indicated at F in FIG. 5. The result of this measure for the display of the character with the letter A is shown at F in FIG. 2.The same rounding effect can be realized by means of the converter circuit shown in FIG. 6, namely by providin
g it with a rounding circuit as well. This is shown in FIG. 8. In this FIG. 8 the elements corresponding to those in FIG. 6 h
ave the same reference numerals. The converter circuit 942 shown in FIG. 8 differs from the circuit shown in FIG. 6 in that the said rounding circuit denoted by the reference numeral 9428 is incorporated between the pulse widening circuit 9426 and the AND gate circuits 9424(.). More particularly this rounding circuit is a pluriform version of the rounding circuit 9427 shown in FIG. 4 and is constituted by six D flip-flops 9428(.) and six OR gates 9429(.). These OR gates receive the respective control signals S(1) to S(6) directly and via the D flip-flops. The T inputs of these D flip-flops again receive the version of the reference clock pulses delayed over half a reference clock pulse period by means of the delay circuit 94210. This rounding circuit thus supplies the control signals S'(.) shown in FIG. 7.
Other References:
Philips Data Handbook, Electronic Components and Materials "Integrated Circuits: Part 3, Sep. 1982: ICs for Digital Systems in Radio, Audio, and Video Equipment: SAA5030 Series", pp. 1-10. Philips Data Handbook, Electronic Components and Materials "Integrated Circuits: Part 3, Sep. 1982: ICs for Digital Systems in Radio, Audio, and Video Equipment: SAA5020 Series", pp. 1-10.
Philips Data Handbook, Electronic Components and Materials "Integrated Circuits: Book IC02a, 1986: Video and Associated Systems: Bipolar, MOS: Types MAB8031AH to TDA1521", pp. 374-375.
F. J. R. Kinghorn, "Computer Controlled Teletext"; Electronic Components and Applications; vol. 6, No. 1, 1984, pp. 15-29.
"World System Teletext Technical Specification", Revised Mar. 1985, pp. 1-10 and 38-41.
Philips Data Handbook, Electronic Components and Materials; "Integrated Circuits, Part 2: Jan. 1983: Bipolar ICs for Video Equipment: TDA2540, TDA2540Q"; pp. 1-8.
Philips Data Handbook, Electronic Components and Materials; "Integrated Circuits: Part 2: Jan. 1983: Bipolar ICs for Video Equipment: TDA 3562A"; pp. 1-16.
Philips Data Handbook, Electronic Components and Materials "Integrated Circuits: Part 3, Sep. 1982: IC's for Digital Systems in Radio, Audio, and Video Equipment: SAA3004"; pp. 1-10.
Philips Data Handbook, Electronic Components and Materials, "Integrated Circuits: Part 3, Sep. 1982: Ics for Digital Systems in Radio, Audio, and Video Equipment: SAB3035", pp. 1-4.
Philips Data Handbook, Electronic Components and Materials "Integrated Circuits: Part 3, Sep. 1982: ICs for Digital Systems in Radio, Audio and Video Equipment: TDB2033", pp. 1-9.
BANG & OLUFSEN BEOVISION 7702 CHASSIS SERIES 77XX 30AX Teletext / Videotext Error correction circuit using character probability :
An error correction circuit in a television receiver for receiving, for example, Teletext information, Viewdata information or information of comparable systems. The codes representing symbol information received by the receiver are classified into one out of two or more classes in dependence on the frequency of their occurrence, this classification being an indication of the extent to which it is probable that a received code is correctly received.
In FIG. 1, a picture text television receiver has a receiving section, audio and video amplifiers 4 and 9 and a picture tube 10, 11. A text decoder 21 receives symbol information which is stored in a store 25 for display. An error detector circuit 40 including a comparison circuit 43 and two parity circuits 41 and 42, and checks for parity between newly received and already stored symbol information. A reliability circuit 60 is also included.1. An error correction circuit for a receiving device for receiving digitally transmitted symbol information, the transmission of this information being repeated one or more times, the receiving device having a decoding circuit for decoding the received information, an information store coupled to said decoding circuit for storing the information, a circuit for generating synchronizing signals and a video converter circuit coupled to said information store and said generating circuit for converting information and synchronizing signals into a composite video signal for application to a standard television receiver, a symbol address in the information store corresponding with a symbol location on a television picture screen, a symbol location being a portion of a text line which is displayed with a number of video lines greater than one, the error correction circuit being coupled to said decoding circuit and said information store and including means coupled between said decoding circuit and said information store for checking newly received symbol information against symbol information stored in the information store for the corresponding symbol location, a write-switch having one input coupled to said decoding circuit and an output coupled to said information store, and a write-setting circuit, coupled to another input of said write-switch, which determines whether the newly received information is written or not written into the information store, said write-setting circit having an input coupled to said checking means whereby the results of said checking are a factor in the setting of said write-switch by said write-setting circuit, characterized in that the error correction circuit further comprises a classification circuit coupled to the output of said decoding circuit for classifying a newly received and decoded symbol in one of at least two classes on the basis of the probability of occurrence of the newly received symbol, the input of the classification circuit being coupled to another input of the write-setting circuit. 2. An error correction circuit for a receiving device as claimed in claim 1, characterized in that the write-setting circuit includes a reliability circuit and the information store comprises an additional storage element for each symbol address in the information store for storing a reliability bit associated with that symbol address, inputs of the reliability circuit being coupled to the classification circuit and to the information store for accessing the additional storage elements, for determining, from the additional storage element corresponding with the symbol address position of newly received symbol information, a new reliability bit, an output of the reliability circuit being coupled back to the information store for writing this new reliability bit into the corresponding additional storage element when the reliability bit for this symbol address changes its value. 3. An error correction circuit for a receiving device as claimed in claim 2, characterized in that the checking means comprises a comparison circuit for bit-wise comparing a newly received and decoded symbol with a symbol read from an address of the information store, this address corresponding with the symbol location, a comparison output of the comparison circuit being coupled to a further input of the reliability circuit. 4. An error correction circuit for a receiving device as claimed in any one of the preceding claims, characterized in that the classification circuit comprises a parity circuit for classifying newly received symbols for respective particular symbol locations into one of two classes which correspond to an even and an odd parity respectively, of the newly received information, and for classifying symbol information already stored in the corresponding symbol addresses in the information store. 5. An error correction circuit for a receiving device as claimed in claim 2, characterized in that the reliability circuit comprises a reliability flipflop and a reliability read circuit for this flipflop, an output of which also constitutes the output of the reliability circuit. 6. An error correction circuit for a receiving device as claimed in claim 1, characterized in that the error correction circuit comprises a second classification circuit, coupled between said other classification circuit and said write-setting circuit and having inputs coupled to said information store, for classifying a symbol read from the information store. 7. An error correction circuit for a receiving device as claimed in claim 1 characterized in that the information store comprises, for each symbol address in the information store, at least one further storage element for storing the classification associated with the symbol for that symbol address.
Description:
BACKGROUND OF THE INVENTION
The invention relates to an error correction circuit of a type suitable for a receiving device for receiving digitally transmitted symbol information (picture and/or text), the transmission of this information being repeated one or more times, the receiving device comprising a deconding circuit for decoding the received information, an information store for storing the information, a circuit for generating synchronizing signals and a video converter circuit for converting information and synchronizing signals for applying a composite video signal to a standard television receiver, a symbol address in the information store corresponding with a symbol location on a television picture screen, a symbol location being a portion of a text line which is displayed with a number of videolines greater than one, the error correction circuit comprising means for checking newly received symbol information against symbol information stored in the information store for the corresponding symbol location, together with a write-switch having a write-setting circuit which determines whether the newly received information is written or not written into the information store, the position of the switch being determined on the basis of the result of said checking.
Error correction circuits of the above type are used in auxiliary apparatus for the reception of Teletext transmissions or comparable transmissions, these auxiliary apparatus being connected to a standard television receiver either by applying video signals to a so-called video input, or by applying these video signals, modulated on a carrier, to an aerial input of the television set. There are already television receivers with a built-in Teletext receiver already including an error correction circuit of the above-mentioned type.
The present Teletext system as it is already used rather widely in the UK, is based on an 8-bit symbol teletext code having 7 information bits and 1 parity bit; this parity bit is chosen so that each 8-bit symbol in the code has a so-called "odd" parity, that is to say there is an odd number of ones in a symbol, and, consequently, also an odd number of zeros. A display on the television picture screen comprises a "page" consisting of a number of rows (e.g. 24) of symbols.
Only symbols with the "odd" parity are stored in the information store. Each symbol represents either an alpha-numeric or a graphics character for display on the picture screen, or a control symbol.
If, in a subsequent transmission cycle for the same symbol location of the same page, a faulty symbol is detected, then, assuming that only a single error occurs within a symbol, this faulty symbol will have an even parity, that is to say a "one" changed into a "zero", or vice versa, as the result of the error. In this case the information store is not written into and the old information is retained in the relevant symbol address.
As the probability is very great that this old information is correct, the parity check does not only furnish an error detection, but also an error correction, partly because of the fact that some knowledge has already been gained from the previous history. Of course, this does not hold for the first transmission cycle. Should an "even" parity be found in a 8-bit symbol in the first transmission cycle, a space ("blank") is generally recorded in the relevant symbol address and, consequently, displayed as a space. The easiest way to do this is by filling the entire information store with space symbols when a new Teletext page is requested, so that also in the first cycle no information need be written into the information store on receipt of a symbol having an "even" parity.
For a poor transmission condition an error probability of 0.01 is assumed, that is to say one symbol out of a hundred symbols is received incorrectly. In a complete page having 960 Teletext symbol locations, (i.e. up to 24 rows of up to 40 symbols per row) the displayed page then shows, after the first cycle, 9 to 10 erroneous spaces on average. In the present system substantially all these erroneous spaces are likely to have been corrected in the second cycle.
When the receiving conditions are better, this situation is already correspondingly more favourable in the first cycle. Even in the poorest receiving conditions, it appears that the number of double errors is so small that they may be neglected. Double errors therefore are hardly ever taken into consideration hereafter. It will be apparent that in this system each symbol has a certain degree of redundancy in the form of the parity bit, but this is off-set by the drawback that the 8-bit code, which has 256 (=2 8 ) combinations, is utilized for only 50% of this capacity, i.e. only for the 128 symbols having "odd" parity.
Although, for the U.K. itself, such a code has a sufficient capacity to contain all desired symbols for control, graphics elements, letters, figures, punctuation marks, etc. as required for Teletext and also, for example, for Viewdata, it is not possible to allot a specific symbol to all of the special characters occurring in various other languages.
Several European languages, in so far they are written in latin characters, have all sorts of "extra" characters, for example Umlaut letters, accent letters, etc. When all these extra characters are totalled, including Icelandic, Maltese and Turkish, then it appears that a total of approximately 220 symbols is required, namely the 128 known symbols plus further symbols for these "extra" characters.
Several solutions have been proposed to solve this, but so far none of these have been satisfactory as they are either very cumbersome or allow only one language within one page, so that it is impossible or very difficult e.g. to quote foreign names in a page of text.
Alternatively it has been proposed--and this is of course very obvious--to use the entire 8-bit code for symbols. As the redundancy in the code has now been reduced to zero, no correction can be effected in the second cycle. If two codes for one symbol location differ from one another in different transmission cycles, it is theoretically impossible to decide with certainty which one of the two codes is correct. An additional information store is required to enable a comparison between a newly received symbol in the third cycle and a symbol from the second and the first cycles, and to take the frequently used majority decision thereafter. This is possible, but three reading cycles are necessary before the number of errors is reduced to an acceptable level. As each transmission cycle of a completely full magazine (i.e. a plurality of pages) takes approximately 25 seconds, the correct text is not known until after approximately 75 seconds.
As the present system displays the text correctly after approximately 50 seconds already, such a solution would mean an increase in the so-called access time.
If a new parity bit were added to the 8-bit code, each symbol would require 8+1=9 bits so that it is no longer possible, as is done in the present system, to accommodate the symbols for one text line of 40 characters in one video line, whereas on the other hand the average transmission rate decreases if more video lines are needed for the information transmission. This solution is generally considered to be unacceptable, also because the compatibility with existing receivers would be fully lost.
Although any language to be displayed can be considered to contain redundancy both as regards text and graphics, so that a viewer may "overlook" many errors, in the sense that there is still an intelligible display, this does not offer a satisfactory solution.
SUMMARY OF THE INVENTION
It is the object of the invention to provide an error correction circuit of the type referred to for a receiving device for Teletext and comparable systems, which offers such a solution for the problem outlined above that also for an 8-bit code without a parity bit substantially all errors, if any, can be corrected in the second transmission cycle which is received.
According to the invention an error correction circuit of the type referred to is characterized in that it comprises at least one classification circuit for classifying a newly received and decoded symbol in one of at least two classes on the basis of the probability of occurrence of the newly received symbol, an output of the classification circuit being coupled to an input of the write-setting circuit.
The classification circuit utilizes the hitherto unrecognized fact that the "language" used for the Teletext system and for associated systems comprises a third form of redundancy, namely the frequency with which the different symbols occur in any random text.
From counts performed on longer texts in several languages, including texts that quote words or names from other languages, it is found that, on average, these texts did not contain more than approximately 5% "extra" symbols, in spite of the fact that the extra symbols constitute approximately 50% of the different code combinations. The remaining 95% are symbols from the original 50% of the different code combinations, that is to say control, graphics and text symbols which were already used in the existing system. For simplicity, these latter symbols are hereinafter denoted A-symbols, and the "extra" symbols are denoted B-symbols.
If now an A-symbol is received in the first cycle and a B-symbol in the second cycle, or vice versa, it is already possible to decide with a high degree of certainty which of the two is correct.
Let us assume that an identified A-symbol is transmitted from the transmitter end for the same symbol location in those first and second cycles, whereas the receiver receives an A-symbol in the first cycle and a B-symbol in the second cycle.
It can be seen that some form of A-symbol is obtained in the receiver when either a real A-symbol is properly received or a real B-symbol is erroneously received. Assuming there is an error probability of 0.01, the probability that the first-mentioned situation occurs is 0.95×0.99=0.9405 and the probability that the second situation occurs is 0.05×0.01=0.0005 so that the probability that an A-symbol is received totals 0.941. A B-symbol results from a real B-symbol (0.05×0.99=0.0495) or a faulty A-symbol (0.95×0.01=0.0095), adding up to a total probability of 0.059. Of course 0.941+0.059=1.000, based on the assumption that double errors do not occur, so that any A-symbol A x will never be received as another A-symbol A y from the same class. The probability that a received A-symbol is correct is 0.9405/0.941=0.9995. The probability that a received B-symbol is correct is 0.0495/0.059=0.839.
For the above mentioned case, it is correctly assumed that the A-symbol in the first cycle is correct, and that the B-symbol in the second cycle is incorrect.
Consequently, there is an A-symbol in the information store in both cycles. In the second cycle the B-symbol must not be stored, and the A-symbol obtained from the first cycle must be retained.
Should a B-symbol be received first, then a B-symbol is written into the information store, (the probability that this B-symbol is correct is still 84%) but it is not retained in the second cycle, and the A-symbol received in the second cycle must now be recorded in the information store.
At the end of the second cycle it is seen that in this manner the then remaining error is less than one in approximately 5 full pages, as applied to the Teletext system. Such a number of errors is so small that apparently they are not noticed by a viewer.
When an A-symbol is received in the first cycle and in the second cycle or a B-symbol is received in both cycles then there is no doubt, after symbol sequences A, B or B, A there is little doubt, but the symbol stored in the information store must be considered to be somewhat suspect. This also applies to each B-symbol recorded in the first cycle, which may lead to a further improvement when a decision is taken.
Another advantageous embodiment of an error correction circuit according to the invention is characterized in that the error correction circuit comprises a reliability circuit and the information store comprises an additional storage element for each symbol address in the information store for storing a reliability bit associated with that symbol address, inputs of the reliability circuit being coupled to the classification circuit and to a read circuit for the additional storage elements, for determining from the additional storage element corresponding with the symbol address of newly received symbol information a new reliability bit, this new reliability bit being written at least into the corresponding additional storage element when the reliability bit for this symbol address changes its value.
When the transmitter successively transmits an A-symbol for a certain symbol and location and symbols ABA are successively received, then the A-symbol may be recorded as being "non-suspect" after the first cycle, indicated by an R (reliable) hereinafter. An R' after the second (A), the brackets indicating that the information is retained (not written into the information store) indicates the assumed non-reliability of this retained (A)-symbol, and an A and an R in the third cycle indicates the reliability of the correctly received A-symbol. The A-symbol in the information store is now again assumed to be reliable for this symbol sequence.
In like manner, when the transmitter transmits a B for a certain symbol location, and the symbols B, A, B, B are successively received, symbols and reliability states B. R', A.R', B. R' and B.R are recorded.
All this depends on the decision logic opted for.
It is assumed here that the possibility of an error for the same symbol location in two consecutive cycles is also extremely small; when the transmitter transmits symbols A, A, A, A in successive cycles, the probability that the receiver would receive, for example, symbols A, B, B, A is assumed to be zero. From practical experiments it was seen that this form of a double error can be fully neglected.
This improvement makes it of course necessary for reliability state R or R' to be retained together with the related symbol in the information store and that it must be revised every cycle, if necessary. Each symbol address now has 9 bits instead of 8 in the Teletext receiver memory. This has hardly any consequences for the price as a standard RAM having a capacity of 1kx9 can be used.
As is apparent from the foregoing examples, it can be advantageous to make different decisions in the case a symbol sequence B-A is formed after the first cycle or after a further cycle.
A further advantageous embodiment of an error correction circuit is characterized in that the error correction circuit comprises a counting circuit for counting information transmission cycles following a new request for (always) a full picture of the requested symbol information, a counting output of this counting circuit being coupled at least to another input of the reliability circuit, this counting output being, for example, also coupled to a further input of the write-setting circuit.
As seen earlier in the history of data transmission and information processing equipment, the need was felt also for Teletext and comparable systems, to realise the extension with new symbols by doubling the number of symbols identified by an n-bit code, in such a way that the original symbols retain as far as possible their existing bit combustion.
This results inter alia in that transmission in a new, extended, code are also displayed reasonably well by existing receivers. A receiver for the original symbols only allots the correct symbol to approximately 95% or more of the symbol locations in the display. A limited compatability is therefore still possible, and even a full compatibility if a normal "English" text is transmitted.
In the example considered herein all the original symbols remain the same, and all the "extra" symbols have even parity.
This symbol set is now under discussion as an international standardization proposal.
It will be apparent that in the last-mentioned case no intricate classification circuit is required to decide for each symbol whether this symbol must be allocated to the A or to the B group.
A further advantageous embodiment of an error correction circuit according to the invention is therefore characterized in that the classification circuit comprises a parity circuit for classifying newly received symbols for respective particular symbol locations into one of two classes which correspond to an even and an odd parity, respectively, of the newly received information, and for classifying symbol information already stored in the corresponding symbol addresses in the information store.
This results, at first sight, in very strange circuit, as now a parity check is performed on a code which contains no parity bit at all.
It is, of course, alternatively possible to record the relevant classification of a symbol in the information store, but this requires at least a tenth bit for each symbol address and, for a classification in more than two groups, it requires even more. It is, however, more advantageous, when a newly received symbol for a particular symbol location is compared with the symbol already stored in the corresponding symbol address of the information store, to determine the classification of the symbol again when it is read from the address, as this requires less material and the advantage that a standard 1 Kx9 RAM can be used is retained.
A further advantageous embodiment is characterized in that the error correction circuit comprises a second classification circuit for classifying a symbol read from the information store.
In the most advantageous case, wherein all extra symbols are even parity codes, this means a second parity check circuit.
In the case that classification in two classes coincides with an even and an odd parity, respectively, of the symbols, it furthermore appears to be possible to enter the classification in the information store in such a way that the notation of the classification does not require an additional storage bit.
An embodiment of an error correction circuit according to the invention, which is advantageous for this case, is characterized in that the error correction circuit comprises a modification circuit which after having determined the "0" or "1" parity value of a newly received symbol means of the parity circuit replaces the content of a fixed bit position of the newly received symbol by this parity value.
Any random bit can be selected as the fixed bit position in the symbol, for example, the eight bit in the case of an 8-bit symbol, whereas a ninth bit is used as, for example, the reliability bit.
There are four distruct possibilities:
In this case only one 8-bit parity circuit is needed.
It is of course alternatively possible to realize the second classification circuit virtually by using the first classification circuit twice on a time-sharing basis, first as the first and then as the second classification circuit. This requires some additional control logic and some additional time, so that the provision of a second classification circuit will be preferred, especially in the case where a simple parity check is performed.
The above-mentioned solution with its possible extensions will furnish the best result if all these extensions are provided. This is at the same time the most expensive solution. Error correction circuits which do not have all the above-described extensions are cheaper and hardly less good.
DESCRIPTION OF THE DRAWINGS
One specific combination will now be discussed in greater detail by way of example with reference to the drawings. On the basis thereof, any other combination can be easily implemented by one skilled in the art.
In the drawings:
FIG. 1 shows a simplified block diagram of a television receiver comprising a Teletext receiving section including an error correction circuit according to the invention.
FIG. 2 shows a simplified time diagram in which a number of different error combinations is shown in an exaggerated burst of errors.
DESCRIPTION OF THE PREFERRED EMBODIMENT
The embodiment chosen for FIG. 1 is suitable for reception in accordance with the proposed new code and comprises two clasification circuits consisting of two parity circuits, a comparison circuit for the bit-wise comparison of two symbols, a reliability circuit comprising a reliability flipflop and, in addition, the elements already known for a television plus Teletext receiver.
FIG. 1 shows a television receiver by means of a simplified block diagram.
A receiving section 1 having an aerial input 2 comprises the high-frequency receiving section, the intermediate-frequency amplifier section, the detection and the synchronizing circuits of the receiver. An audio output 3 is coupled to one or more loudspeakers 5 via an audio amplifier 4. Via control switches 7 and 8 a video output 6 is coupled for normal television reception to a video amplifier 9 for a picture tube 10 comprising the picture screen 11. Via a control switch 13 a synchronizing output 12 is coupled during normal television reception to a time-base circuit 14 which supplies the deflection voltages for the picture tube 10 via an output 15.
However, the control switches 7, 8 and 13 are shown in the position for Teletext reception and display.
Via the switch 7 the video signal is applied to an input 20 of a Teletext decoder 21, a synchronizing input 22 of which is coupled to the synchronizing output 12 of the receiving section 1.
In the Teletext decoder 21, serially received Teletext symbols are successively entered in parallel into a buffer register 23 thereof. Depending on the action decided upon, the contents of the buffer register 23 can be transferred to a storage register 24 of an information store 25, and from the storage register 24, the consecutive symbol addresses each corresponding to a symbol location on the picture screen 11 are filled, until the entire information store 25 is filled with the symbol information which corresponds to the desired Teletext page.
This and also the further processing operations are fully in agreement with the existing Teletext system. Addressing, reading of the information store, etc. are therefore not further described.
An output 26 of the information store 25 is coupled to a video (Teletext) generator 27, an output 28 of which is connected to the video amplifier 9 via the switch 8. In addition, there is provided in known manner a signal generator 29 and a generator 30 for generating several timing signals required in the receiver, which are applied to several other elements via outputs 31 to 35, inclusive. Synchronizing signals which can be applied to the time-base circuit 14 via the switch 13 are produced at the output 32.
The decision whether the content of the buffer register 23 must be transferred or not transferred to the storage register 24 is taken by an error correction circuit, which would, in the known Teletext system, consist of a parity check circuit.
The error correction circuit according to the invention consists of an error detection circuit 40 and, in the specific embodiment being described, a reliability circuit 60. The error detection circuit 40 comprises a parity circuit 41 for the buffer register 23, a parity circuit 42 for the storage register 24, a comparison circuit 43 for comparing the contents of buffer and storage registers 23, 24 with one another, and a number of write switches 44-0 to 44-7 inclusive. In this example these write switches are represented as respective AND-gates each having two inputs and an output. An input 45-i of each of the write switches is always connected to a corresponding output 46-i of the buffer register 23, these outputs also being connected respectively to inputs 47-1 to 47-8 inclusive, of the parity circuit 41 and to inputs 48-0 to 48-7 inclusive, of the comparison circuit 43.
The other input 49-i of each of the write switches is connected to a common write command input 50 of the error detection circuit 40.
In addition, output 51-i of the storage register 24 are connected to respective inputs 52-1 to 52-8 inclusive, of the parity circuit 42 and to corresponding further inputs 53-i of the comparison circuit 43 and to outputs 54-i of the write switches 44-0 to 44-7.
An odd parity-output 55 ("1" for odd-parity) of the parity circuit 41, is connected to an input 52-9 of the additional parity circuit 42, which has an output 56 for even or odd parity at the inputs 52-1 to 52-9, inclusive.
A Signetics IC No. 54180 or No. 8262 may, for example, be used for the parity circuit 41. If the parity of the symbol in the buffer register 23 is odd or even, a "1" and "0", respectively, appears at the output 55.
A Signetics IC No. 8262 may also be used for the parity circuit 42. If the parity of the symbol in the storage register 24 is odd and a "1" has appeared at the output 55, then a "1" appears at the output 56 for the even parity of the parity circuit 42, that is to say both symbols had an odd parity. If both symbols have an even parity the input 52-9 receives a zero, so that the total number of ones is even again and the output 56 shows an "1" again. Should the parities of the buffer register 23 and the storge register 24 be unequal, then the output 56 shows "0".
Thus the output 56 (Even Parity) may be considered to be an output which indicates by means of the "1", that the investigated symbols have an equal parity (Equal Parity, EP).
The comparison circuit 43 has an output 57 which becomes a "1" as soon as all the bits of the compared symbols are mutually equal. The signal thus obtained will be denoted EB (Equal Bytes).
The reliability circuit 60 comprises a flipflop 61 having number of writing gates 62. A JK flipflop is chosen for the described example but this is not essential to the inventive idea. One half of a Signetics 54112 may, for example, be used as a JK flipflop. Descriptions, truth tables and time diagrams of the above-mentioned Signetics circuits are known from the Philips Signetics Data Handbook.
The reliability circit 60 satisfies the following equations:
CK R =CLK, obtained from the clock signal generator 29. J R =R/WR G +(R/W)'EP (I) K R =R/WR G +(R/W)'EB (II)
in which R G is the reliability status as stored in the memory 25,
The operation of the JK-flipflop can be explained as follows, reference also being made to the time diagram of FIG. 2.
Within successive periods of approximately 25 seconds the symbols for 960 symbol locations (i.e. a page of text) are repeatedly received. The solid line sections 100 represent the symbol processing of the symbol S x in consecutive cycles 0 to 7, inclusive, indicated as S x ,0 to S x ,7 inclusive. The broken line sections represent in a very concise manner the processing of S 0 to S x -1, inclusive, and S x +1 to S 959 , inclusive, one processing period comprising, for example, two cycles of the clock signal 101 of the clock signal generator 29 and one read/write cycle consisting of the portions R/W and (R/W)', read and write respectively, controlled by the signal 102, obtained from the output 31 of time signal generator 30. During the read portion 103 of cycle 102 the contents of a symbol address which correspond with the signal combination entered in the buffer register 23 for a given symbol location, is entered into the storage register 24. As each symbol address has a ninth bit for a reliability bit, a status value R G appears simultaneously at an output 63 of the information store 25. On the first rising clock edge 104 only the first terms of the equations I and II are operative, as R/W="1" and consequently (R/W)'="0". This means that at the instant 104 the flipflop 61, R assumes the value "1" when R G ="1" and the value "0" when R G ="0", as shown in the line sections 105. At the next clock edge 106 only the second terms are operative, and the flipflop 61 can now retain the previously adjusted value or assume the other value. This final value at the output 64 of the flipflop 61 is applied to an input 65 of the information store for writing a next R G in the ninth bit of the corresponding storage address.
The output 66 (R') of the flipflop 61, which is connected to thewrite command signal input 50 of the error detection circuit 50, further determines whether the contents of the buffer register 23 can be transferred to the storage register 24 during the write cycle 107 (see FIG. 2).
Finally, the lines 108, 109 of FIG. 2 represent two bit contents of the storage register and 110, 111 represent two bit contents of the buffer register. For clarity's sake the remaining bits have been omitted.
The signal EP is denoted by 112, and the signal EB by 113.
In this example the following set of decision rules has been realised in the circuit.
The states, indicated by an x, of J R and K R are irrelevant for the position of the flipflop. The equations I and II have been chosen thus that the required values "0" and "1" for J R and K R are produced.
FIG. 2 shows the states and EP, EB and R in the line sections 112, 113 and 105, respectively, by means of an example which shows an unprobable burst of received errors, such that each one of the decisions occurs at least once.
When the first cycle starts, the entire information store 25 is filled with space symbols. The space symbol is an A-symbol, denoted in FIG. 2 by A. It is assumed that the transmitter transmits a B-symbol and continues to do so. A faulty B-symbol has the same parity as A and is denoted by B'. On the basis of decision 1, EP=0, EB=0 and R G ="0" in the second half of the cycle a B' (erroneously received B with an even number of errors) is written into the storage register 24. The new R G remains "0" because J R =0, K R =x.
In the next cycle the buffer register 23 contains a correctly received B, which is transferred to the storage register 24 in accordance with decision 2.
The further cycles need no explanation. (B) indicates when there is no transfer to the store. The B already present in the relevant symbol address is not changed.
Throughout the example of the transmitter
transmitted: B B B B B B B B
received: B' B B' B B A B B
dislayed: B' B (B) B B (B) B B
The displayed error B' in the first cycle can of course not be avoided in this example, all following results are correct.
Any other possible received sequence can be followed in a similar manner.
Two of the decisions need some further explanation.
Decision 2 with EP="1" and EB="0", seems to indicate a multiple and, consequently, very rare error. As the information store 25 is initially filled with A's and the probability that an A will be received is high, this "error" will occur very frequently, especially in the first cycle.
Any double error occurring at a later instant will be treated likewise, in that very rare event.
Decision 6 deals with an equally rare event, but with R G ="1". It shortens the elimination of a multiple error, but will be rarely necessary. However, this decision 6 can be combined cheaply with decision 7.
In the embodiment explained on the basis of Table I the processing of EP in particular is simplified.
The following simple process can now, for example, be applied.
A newly received symbol is applied to the input of the parity circuit 41.
If the newly received symbol (n+1) is a symbol from the A group, then the parity circuit 41 indicates an odd parity that is to say a "1" at the output "odd parity".
This "1" is transferred to the eight bit of the buffer register 23.
By comparing a corresponding symbol (n) from the information store 25 with a modified symbol (n+1), EP can now be found by comparing the two eights bits of the buffer register 23 and the storage register 24. EB can be determined as previously to detect whether there is or there is not a difference between the two (modified) symbols.
In dependence on EP, EB and R, it is decided in a conventional manner whether the modified symbol will be written or not written into the information store 25. Thus the information store 25 comprises modified symbols only, so that in checking with the comparator 43, this check must be made against the also modified, newly received symbol.
During the display of the page, the parity circuit 41 is available for remodification, it only being necessary to invert the eighth bit if the eighth bit of the symbol to be displayed differs from the parity of this symbol, that is to say it is sufficient to replace the eighth bit of the storge register 24 by the parity now found..
A slight improvement can still be obtained by means of the additional decision (see at the bottom of the Table II). However, to enable the use of this additional decision, instead of decision 2 which can then only hold for the first cycle, a cycle counter must now be incorporated which forms with New Request="1" an additional condition for decision 2 and which, in all subsequent cycles with NR="0" results in decision 4 when EP=1, EB=0 and R G =0.
In view of what was described herefore such an extension can be easily realized by one normally skilled in the art of logic design.
In extremely rare cases this embodiment results in a further small improvement.
A simplified embodiment produces for all normal single errors an equally satisfactory result but it deals with the multiple errors in a less satisfactory way. However, the total result remains very satisfactory for the user.
The entire comparison circuit is omitted from this simplified embodiment. The decision table is now reduced to:
Again this embodiment can be easily realized by one normally skilled in the art, using what has been described herein.
The same applies if smll changes are desired in the decisions, and also when, for example, the circuit must be implemented in the form of one or more Large Scale Integrated circuits (LSI), or when it is realized wholly or partly by means of a micro-processor.
The invention relates to an error correction circuit of a type suitable for a receiving device for receiving digitally transmitted symbol information (picture and/or text), the transmission of this information being repeated one or more times, the receiving device comprising a deconding circuit for decoding the received information, an information store for storing the information, a circuit for generating synchronizing signals and a video converter circuit for converting information and synchronizing signals for applying a composite video signal to a standard television receiver, a symbol address in the information store corresponding with a symbol location on a television picture screen, a symbol location being a portion of a text line which is displayed with a number of videolines greater than one, the error correction circuit comprising means for checking newly received symbol information against symbol information stored in the information store for the corresponding symbol location, together with a write-switch having a write-setting circuit which determines whether the newly received information is written or not written into the information store, the position of the switch being determined on the basis of the result of said checking.Error correction circuits of the above type are used in auxiliary apparatus for the reception of Teletext transmissions or comparable transmissions, these auxiliary apparatus being connected to a standard television receiver either by applying video signals to a so-called video input, or by applying these video signals, modulated on a carrier, to an aerial input of the television set. There are already television receivers with a built-in Teletext receiver already including an error correction circuit of the above-mentioned type.
The present Teletext system as it is already used rather widely in the UK, is based on an 8-bit symbol teletext code having 7 information bits and 1 parity bit; this parity bit is chosen so that each 8-bit symbol in the code has a so-called "odd" parity, that is to say there is an odd number of ones in a symbol, and, consequently, also an odd number of zeros. A display on the television picture screen comprises a "page" consisting of a number of rows (e.g. 24) of symbols.
Only symbols with the "odd" parity are stored in the information store. Each symbol represents either an alpha-numeric or a graphics character for display on the picture screen, or a control symbol.
If, in a subsequent transmission cycle for the same symbol location of the same page, a faulty symbol is detected, then, assuming that only a single error occurs within a symbol, this faulty symbol will have an even parity, that is to say a "one" changed into a "zero", or vice versa, as the result of the error. In this case the information store is not written into and the old information is retained in the relevant symbol address.
As the probability is very great that this old information is correct, the parity check does not only furnish an error detection, but also an error correction, partly because of the fact that some knowledge has already been gained from the previous history. Of course, this does not hold for the first transmission cycle. Should an "even" parity be found in a 8-bit symbol in the first transmission cycle, a space ("blank") is generally recorded in the relevant symbol address and, consequently, displayed as a space. The easiest way to do this is by filling the entire information store with space symbols when a new Teletext page is requested, so that also in the first cycle no information need be written into the information store on receipt of a symbol having an "even" parity.
For a poor transmission condition an error probability of 0.01 is assumed, that is to say one symbol out of a hundred symbols is received incorrectly. In a complete page having 960 Teletext symbol locations, (i.e. up to 24 rows of up to 40 symbols per row) the displayed page then shows, after the first cycle, 9 to 10 erroneous spaces on average. In the present system substantially all these erroneous spaces are likely to have been corrected in the second cycle.
When the receiving conditions are better, this situation is already correspondingly more favourable in the first cycle. Even in the poorest receiving conditions, it appears that the number of double errors is so small that they may be neglected. Double errors therefore are hardly ever taken into consideration hereafter. It will be apparent that in this system each symbol has a certain degree of redundancy in the form of the parity bit, but this is off-set by the drawback that the 8-bit code, which has 256 (=2 8 ) combinations, is utilized for only 50% of this capacity, i.e. only for the 128 symbols having "odd" parity.
Although, for the U.K. itself, such a code has a sufficient capacity to contain all desired symbols for control, graphics elements, letters, figures, punctuation marks, etc. as required for Teletext and also, for example, for Viewdata, it is not possible to allot a specific symbol to all of the special characters occurring in various other languages.
Several European languages, in so far they are written in latin characters, have all sorts of "extra" characters, for example Umlaut letters, accent letters, etc. When all these extra characters are totalled, including Icelandic, Maltese and Turkish, then it appears that a total of approximately 220 symbols is required, namely the 128 known symbols plus further symbols for these "extra" characters.
Several solutions have been proposed to solve this, but so far none of these have been satisfactory as they are either very cumbersome or allow only one language within one page, so that it is impossible or very difficult e.g. to quote foreign names in a page of text.
Alternatively it has been proposed--and this is of course very obvious--to use the entire 8-bit code for symbols. As the redundancy in the code has now been reduced to zero, no correction can be effected in the second cycle. If two codes for one symbol location differ from one another in different transmission cycles, it is theoretically impossible to decide with certainty which one of the two codes is correct. An additional information store is required to enable a comparison between a newly received symbol in the third cycle and a symbol from the second and the first cycles, and to take the frequently used majority decision thereafter. This is possible, but three reading cycles are necessary before the number of errors is reduced to an acceptable level. As each transmission cycle of a completely full magazine (i.e. a plurality of pages) takes approximately 25 seconds, the correct text is not known until after approximately 75 seconds.
As the present system displays the text correctly after approximately 50 seconds already, such a solution would mean an increase in the so-called access time.
If a new parity bit were added to the 8-bit code, each symbol would require 8+1=9 bits so that it is no longer possible, as is done in the present system, to accommodate the symbols for one text line of 40 characters in one video line, whereas on the other hand the average transmission rate decreases if more video lines are needed for the information transmission. This solution is generally considered to be unacceptable, also because the compatibility with existing receivers would be fully lost.
Although any language to be displayed can be considered to contain redundancy both as regards text and graphics, so that a viewer may "overlook" many errors, in the sense that there is still an intelligible display, this does not offer a satisfactory solution.
SUMMARY OF THE INVENTION
According to the invention an error correction circuit of the type referred to is characterized in that it comprises at least one classification circuit for classifying a newly received and decoded symbol in one of at least two classes on the basis of the probability of occurrence of the newly received symbol, an output of the classification circuit being coupled to an input of the write-setting circuit.
The classification circuit utilizes the hitherto unrecognized fact that the "language" used for the Teletext system and for associated systems comprises a third form of redundancy, namely the frequency with which the different symbols occur in any random text.
From counts performed on longer texts in several languages, including texts that quote words or names from other languages, it is found that, on average, these texts did not contain more than approximately 5% "extra" symbols, in spite of the fact that the extra symbols constitute approximately 50% of the different code combinations. The remaining 95% are symbols from the original 50% of the different code combinations, that is to say control, graphics and text symbols which were already used in the existing system. For simplicity, these latter symbols are hereinafter denoted A-symbols, and the "extra" symbols are denoted B-symbols.
If now an A-symbol is received in the first cycle and a B-symbol in the second cycle, or vice versa, it is already possible to decide with a high degree of certainty which of the two is correct.
Let us assume that an identified A-symbol is transmitted from the transmitter end for the same symbol location in those first and second cycles, whereas the receiver receives an A-symbol in the first cycle and a B-symbol in the second cycle.
It can be seen that some form of A-symbol is obtained in the receiver when either a real A-symbol is properly received or a real B-symbol is erroneously received. Assuming there is an error probability of 0.01, the probability that the first-mentioned situation occurs is 0.95×0.99=0.9405 and the probability that the second situation occurs is 0.05×0.01=0.0005 so that the probability that an A-symbol is received totals 0.941. A B-symbol results from a real B-symbol (0.05×0.99=0.0495) or a faulty A-symbol (0.95×0.01=0.0095), adding up to a total probability of 0.059. Of course 0.941+0.059=1.000, based on the assumption that double errors do not occur, so that any A-symbol A x will never be received as another A-symbol A y from the same class. The probability that a received A-symbol is correct is 0.9405/0.941=0.9995. The probability that a received B-symbol is correct is 0.0495/0.059=0.839.
For the above mentioned case, it is correctly assumed that the A-symbol in the first cycle is correct, and that the B-symbol in the second cycle is incorrect.
Consequently, there is an A-symbol in the information store in both cycles. In the second cycle the B-symbol must not be stored, and the A-symbol obtained from the first cycle must be retained.
Should a B-symbol be received first, then a B-symbol is written into the information store, (the probability that this B-symbol is correct is still 84%) but it is not retained in the second cycle, and the A-symbol received in the second cycle must now be recorded in the information store.
At the end of the second cycle it is seen that in this manner the then remaining error is less than one in approximately 5 full pages, as applied to the Teletext system. Such a number of errors is so small that apparently they are not noticed by a viewer.
When an A-symbol is received in the first cycle and in the second cycle or a B-symbol is received in both cycles then there is no doubt, after symbol sequences A, B or B, A there is little doubt, but the symbol stored in the information store must be considered to be somewhat suspect. This also applies to each B-symbol recorded in the first cycle, which may lead to a further improvement when a decision is taken.
Another advantageous embodiment of an error correction circuit according to the invention is characterized in that the error correction circuit comprises a reliability circuit and the information store comprises an additional storage element for each symbol address in the information store for storing a reliability bit associated with that symbol address, inputs of the reliability circuit being coupled to the classification circuit and to a read circuit for the additional storage elements, for determining from the additional storage element corresponding with the symbol address of newly received symbol information a new reliability bit, this new reliability bit being written at least into the corresponding additional storage element when the reliability bit for this symbol address changes its value.
In like manner, when the transmitter transmits a B for a certain symbol location, and the symbols B, A, B, B are successively received, symbols and reliability states B. R', A.R', B. R' and B.R are recorded.
All this depends on the decision logic opted for.
It is assumed here that the possibility of an error for the same symbol location in two consecutive cycles is also extremely small; when the transmitter transmits symbols A, A, A, A in successive cycles, the probability that the receiver would receive, for example, symbols A, B, B, A is assumed to be zero. From practical experiments it was seen that this form of a double error can be fully neglected.
This improvement makes it of course necessary for reliability state R or R' to be retained together with the related symbol in the information store and that it must be revised every cycle, if necessary. Each symbol address now has 9 bits instead of 8 in the Teletext receiver memory. This has hardly any consequences for the price as a standard RAM having a capacity of 1kx9 can be used.
As is apparent from the foregoing examples, it can be advantageous to make different decisions in the case a symbol sequence B-A is formed after the first cycle or after a further cycle.
A further advantageous embodiment of an error correction circuit is characterized in that the error correction circuit comprises a counting circuit for counting information transmission cycles following a new request for (always) a full picture of the requested symbol information, a counting output of this counting circuit being coupled at least to another input of the reliability circuit, this counting output being, for example, also coupled to a further input of the write-setting circuit.
As seen earlier in the history of data transmission and information processing equipment, the need was felt also for Teletext and comparable systems, to realise the extension with new symbols by doubling the number of symbols identified by an n-bit code, in such a way that the original symbols retain as far as possible their existing bit combustion.
This results inter alia in that transmission in a new, extended, code are also displayed reasonably well by existing receivers. A receiver for the original symbols only allots the correct symbol to approximately 95% or more of the symbol locations in the display. A limited compatability is therefore still possible, and even a full compatibility if a normal "English" text is transmitted.
In the example considered herein all the original symbols remain the same, and all the "extra" symbols have even parity.
This symbol set is now under discussion as an international standardization proposal.
It will be apparent that in the last-mentioned case no intricate classification circuit is required to decide for each symbol whether this symbol must be allocated to the A or to the B group.
A further advantageous embodiment of an error correction circuit according to the invention is therefore characterized in that the classification circuit comprises a parity circuit for classifying newly received symbols for respective particular symbol locations into one of two classes which correspond to an even and an odd parity, respectively, of the newly received information, and for classifying symbol information already stored in the corresponding symbol addresses in the information store.
This results, at first sight, in very strange circuit, as now a parity check is performed on a code which contains no parity bit at all.
It is, of course, alternatively possible to record the relevant classification of a symbol in the information store, but this requires at least a tenth bit for each symbol address and, for a classification in more than two groups, it requires even more. It is, however, more advantageous, when a newly received symbol for a particular symbol location is compared with the symbol already stored in the corresponding symbol address of the information store, to determine the classification of the symbol again when it is read from the address, as this requires less material and the advantage that a standard 1 Kx9 RAM can be used is retained.
A further advantageous embodiment is characterized in that the error correction circuit comprises a second classification circuit for classifying a symbol read from the information store.
In the most advantageous case, wherein all extra symbols are even parity codes, this means a second parity check circuit.
In the case that classification in two classes coincides with an even and an odd parity, respectively, of the symbols, it furthermore appears to be possible to enter the classification in the information store in such a way that the notation of the classification does not require an additional storage bit.
An embodiment of an error correction circuit according to the invention, which is advantageous for this case, is characterized in that the error correction circuit comprises a modification circuit which after having determined the "0" or "1" parity value of a newly received symbol means of the parity circuit replaces the content of a fixed bit position of the newly received symbol by this parity value.
Any random bit can be selected as the fixed bit position in the symbol, for example, the eight bit in the case of an 8-bit symbol, whereas a ninth bit is used as, for example, the reliability bit.
There are four distruct possibilities:
| TABLE I |
| ______________________________________ |
| Modified Class Symbol (n+1) Parity symbol (n+1) Parity |
| ______________________________________ |
A xxxxxxx 1 1 xxxxxxx 1 1 A xxxxxxx 0 1 xxxxxxx 1 0 B xxxxxxx 1 0 xxxxxxx 0 1 B xxxxxxx 0 0 xxxxxxx 0 0 |
| ______________________________________ |
It is of course alternatively possible to realize the second classification circuit virtually by using the first classification circuit twice on a time-sharing basis, first as the first and then as the second classification circuit. This requires some additional control logic and some additional time, so that the provision of a second classification circuit will be preferred, especially in the case where a simple parity check is performed.
The above-mentioned solution with its possible extensions will furnish the best result if all these extensions are provided. This is at the same time the most expensive solution. Error correction circuits which do not have all the above-described extensions are cheaper and hardly less good.
DESCRIPTION OF THE DRAWINGS
One specific combination will now be discussed in greater detail by way of example with reference to the drawings. On the basis thereof, any other combination can be easily implemented by one skilled in the art.
In the drawings:
FIG. 1 shows a simplified block diagram of a television receiver comprising a Teletext receiving section including an error correction circuit according to the invention.
FIG. 2 shows a simplified time diagram in which a number of different error combinations is shown in an exaggerated burst of errors.
DESCRIPTION OF THE PREFERRED EMBODIMENT
The embodiment chosen for FIG. 1 is suitable for reception in accordance with the proposed new code and comprises two clasification circuits consisting of two parity circuits, a comparison circuit for the bit-wise comparison of two symbols, a reliability circuit comprising a reliability flipflop and, in addition, the elements already known for a television plus Teletext receiver.
FIG. 1 shows a television receiver by means of a simplified block diagram.
A receiving section 1 having an aerial input 2 comprises the high-frequency receiving section, the intermediate-frequency amplifier section, the detection and the synchronizing circuits of the receiver. An audio output 3 is coupled to one or more loudspeakers 5 via an audio amplifier 4. Via control switches 7 and 8 a video output 6 is coupled for normal television reception to a video amplifier 9 for a picture tube 10 comprising the picture screen 11. Via a control switch 13 a synchronizing output 12 is coupled during normal television reception to a time-base circuit 14 which supplies the deflection voltages for the picture tube 10 via an output 15.However, the control switches 7, 8 and 13 are shown in the position for Teletext reception and display.
Via the switch 7 the video signal is applied to an input 20 of a Teletext decoder 21, a synchronizing input 22 of which is coupled to the synchronizing output 12 of the receiving section 1.
In the Teletext decoder 21, serially received Teletext symbols are successively entered in parallel into a buffer register 23 thereof. Depending on the action decided upon, the contents of the buffer register 23 can be transferred to a storage register 24 of an information store 25, and from the storage register 24, the consecutive symbol addresses each corresponding to a symbol location on the picture screen 11 are filled, until the entire information store 25 is filled with the symbol information which corresponds to the desired Teletext page.
This and also the further processing operations are fully in agreement with the existing Teletext system. Addressing, reading of the information store, etc. are therefore not further described.
An output 26 of the information store 25 is coupled to a video (Teletext) generator 27, an output 28 of which is connected to the video amplifier 9 via the switch 8. In addition, there is provided in known manner a signal generator 29 and a generator 30 for generating several timing signals required in the receiver, which are applied to several other elements via outputs 31 to 35, inclusive. Synchronizing signals which can be applied to the time-base circuit 14 via the switch 13 are produced at the output 32.The error correction circuit according to the invention consists of an error detection circuit 40 and, in the specific embodiment being described, a reliability circuit 60. The error detection circuit 40 comprises a parity circuit 41 for the buffer register 23, a parity circuit 42 for the storage register 24, a comparison circuit 43 for comparing the contents of buffer and storage registers 23, 24 with one another, and a number of write switches 44-0 to 44-7 inclusive. In this example these write switches are represented as respective AND-gates each having two inputs and an output. An input 45-i of each of the write switches is always connected to a corresponding output 46-i of the buffer register 23, these outputs also being connected respectively to inputs 47-1 to 47-8 inclusive, of the parity circuit 41 and to inputs 48-0 to 48-7 inclusive, of the comparison circuit 43.
The other input 49-i of each of the write switches is connected to a common write command input 50 of the error detection circuit 40.
In addition, output 51-i of the storage register 24 are connected to respective inputs 52-1 to 52-8 inclusive, of the parity circuit 42 and to corresponding further inputs 53-i of the comparison circuit 43 and to outputs 54-i of the write switches 44-0 to 44-7.
An odd parity-output 55 ("1" for odd-parity) of the parity circuit 41, is connected to an input 52-9 of the additional parity circuit 42, which has an output 56 for even or odd parity at the inputs 52-1 to 52-9, inclusive.
A Signetics IC No. 54180 or No. 8262 may, for example, be used for the parity circuit 41. If the parity of the symbol in the buffer register 23 is odd or even, a "1" and "0", respectively, appears at the output 55.
A Signetics IC No. 8262 may also be used for the parity circuit 42. If the parity of the symbol in the storage register 24 is odd and a "1" has appeared at the output 55, then a "1" appears at the output 56 for the even parity of the parity circuit 42, that is to say both symbols had an odd parity. If both symbols have an even parity the input 52-9 receives a zero, so that the total number of ones is even again and the output 56 shows an "1" again. Should the parities of the buffer register 23 and the storge register 24 be unequal, then the output 56 shows "0".
Thus the output 56 (Even Parity) may be considered to be an output which indicates by means of the "1", that the investigated symbols have an equal parity (Equal Parity, EP).
The comparison circuit 43 has an output 57 which becomes a "1" as soon as all the bits of the compared symbols are mutually equal. The signal thus obtained will be denoted EB (Equal Bytes).
The reliability circuit 60 comprises a flipflop 61 having number of writing gates 62. A JK flipflop is chosen for the described example but this is not essential to the inventive idea. One half of a Signetics 54112 may, for example, be used as a JK flipflop. Descriptions, truth tables and time diagrams of the above-mentioned Signetics circuits are known from the Philips Signetics Data Handbook.
The reliability circit 60 satisfies the following equations:
CK R =CLK, obtained from the clock signal generator 29. J R =R/WR G +(R/W)'EP (I) K R =R/WR G +(R/W)'EB (II)
in which R G is the reliability status as stored in the memory 25,
The operation of the JK-flipflop can be explained as follows, reference also being made to the time diagram of FIG. 2.Within successive periods of approximately 25 seconds the symbols for 960 symbol locations (i.e. a page of text) are repeatedly received. The solid line sections 100 represent the symbol processing of the symbol S x in consecutive cycles 0 to 7, inclusive, indicated as S x ,0 to S x ,7 inclusive. The broken line sections represent in a very concise manner the processing of S 0 to S x -1, inclusive, and S x +1 to S 959 , inclusive, one processing period comprising, for example, two cycles of the clock signal 101 of the clock signal generator 29 and one read/write cycle consisting of the portions R/W and (R/W)', read and write respectively, controlled by the signal 102, obtained from the output 31 of time signal generator 30. During the read portion 103 of cycle 102 the contents of a symbol address which correspond with the signal combination entered in the buffer register 23 for a given symbol location, is entered into the storage register 24. As each symbol address has a ninth bit for a reliability bit, a status value R G appears simultaneously at an output 63 of the information store 25. On the first rising clock edge 104 only the first terms of the equations I and II are operative, as R/W="1" and consequently (R/W)'="0". This means that at the instant 104 the flipflop 61, R assumes the value "1" when R G ="1" and the value "0" when R G ="0", as shown in the line sections 105. At the next clock edge 106 only the second terms are operative, and the flipflop 61 can now retain the previously adjusted value or assume the other value. This final value at the output 64 of the flipflop 61 is applied to an input 65 of the information store for writing a next R G in the ninth bit of the corresponding storage address.
The output 66 (R') of the flipflop 61, which is connected to thewrite command signal input 50 of the error detection circuit 50, further determines whether the contents of the buffer register 23 can be transferred to the storage register 24 during the write cycle 107 (see FIG. 2).
Finally, the lines 108, 109 of FIG. 2 represent two bit contents of the storage register and 110, 111 represent two bit contents of the buffer register. For clarity's sake the remaining bits have been omitted.
The signal EP is denoted by 112, and the signal EB by 113.
In this example the following set of decision rules has been realised in the circuit.
| TABLE II |
| ______________________________________ |
| Decision Read Write SR EP EB R G 23➝24 Written S R K R |
| ______________________________________ |
1 0 0 0 1 0 0 x 2 1 0 0 1 1 1 x 3 1 1 0 1 1 1 x 5 1 1 1 0 1 x 1 6 1 0 1 0 0 x 0 7 0 0 1 0 0 x 0 (4) 1 0 0 1 0 0 x |
| ______________________________________ |
FIG. 2 shows the states and EP, EB and R in the line sections 112, 113 and 105, respectively, by means of an example which shows an unprobable burst of received errors, such that each one of the decisions occurs at least once.When the first cycle starts, the entire information store 25 is filled with space symbols. The space symbol is an A-symbol, denoted in FIG. 2 by A. It is assumed that the transmitter transmits a B-symbol and continues to do so. A faulty B-symbol has the same parity as A and is denoted by B'. On the basis of decision 1, EP=0, EB=0 and R G ="0" in the second half of the cycle a B' (erroneously received B with an even number of errors) is written into the storage register 24. The new R G remains "0" because J R =0, K R =x.
In the next cycle the buffer register 23 contains a correctly received B, which is transferred to the storage register 24 in accordance with decision 2.
The further cycles need no explanation. (B) indicates when there is no transfer to the store. The B already present in the relevant symbol address is not changed.
Throughout the example of the transmitter
transmitted: B B B B B B B B
received: B' B B' B B A B B
dislayed: B' B (B) B B (B) B B
The displayed error B' in the first cycle can of course not be avoided in this example, all following results are correct.
Any other possible received sequence can be followed in a similar manner.
Two of the decisions need some further explanation.
Decision 2 with EP="1" and EB="0", seems to indicate a multiple and, consequently, very rare error. As the information store 25 is initially filled with A's and the probability that an A will be received is high, this "error" will occur very frequently, especially in the first cycle.
Any double error occurring at a later instant will be treated likewise, in that very rare event.
Decision 6 deals with an equally rare event, but with R G ="1". It shortens the elimination of a multiple error, but will be rarely necessary. However, this decision 6 can be combined cheaply with decision 7.In the embodiment explained on the basis of Table I the processing of EP in particular is simplified.
The following simple process can now, for example, be applied.
A newly received symbol is applied to the input of the parity circuit 41.
If the newly received symbol (n+1) is a symbol from the A group, then the parity circuit 41 indicates an odd parity that is to say a "1" at the output "odd parity".
This "1" is transferred to the eight bit of the buffer register 23.
By comparing a corresponding symbol (n) from the information store 25 with a modified symbol (n+1), EP can now be found by comparing the two eights bits of the buffer register 23 and the storage register 24. EB can be determined as previously to detect whether there is or there is not a difference between the two (modified) symbols.
In dependence on EP, EB and R, it is decided in a conventional manner whether the modified symbol will be written or not written into the information store 25. Thus the information store 25 comprises modified symbols only, so that in checking with the comparator 43, this check must be made against the also modified, newly received symbol.
During the display of the page, the parity circuit 41 is available for remodification, it only being necessary to invert the eighth bit if the eighth bit of the symbol to be displayed differs from the parity of this symbol, that is to say it is sufficient to replace the eighth bit of the storge register 24 by the parity now found..
A slight improvement can still be obtained by means of the additional decision (see at the bottom of the Table II). However, to enable the use of this additional decision, instead of decision 2 which can then only hold for the first cycle, a cycle counter must now be incorporated which forms with New Request="1" an additional condition for decision 2 and which, in all subsequent cycles with NR="0" results in decision 4 when EP=1, EB=0 and R G =0.
In view of what was described herefore such an extension can be easily realized by one normally skilled in the art of logic design.
In extremely rare cases this embodiment results in a further small improvement.
A simplified embodiment produces for all normal single errors an equally satisfactory result but it deals with the multiple errors in a less satisfactory way. However, the total result remains very satisfactory for the user.
The entire comparison circuit is omitted from this simplified embodiment. The decision table is now reduced to:
| TABLE III |
| ______________________________________ |
| Read Write Written Decision EP R G 23-24 R G |
| ______________________________________ |
1A 1 0 1 1 2A 1 1 1 1 3A 0 0 1 0 4A 0 1 0 0 |
| ______________________________________ |
The same applies if smll changes are desired in the decisions, and also when, for example, the circuit must be implemented in the form of one or more Large Scale Integrated circuits (LSI), or when it is realized wholly or partly by means of a micro-processor.
You can see the complexity of the tellye even only from the wiring around it.
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