The Korting Chassis 9, which was introduced in 1979, was designed to drive several different types of tube - PIL in the 20in. size, and 20AX/30AX in the 22 and 26in. sizes. It was used in a range of models with serial numbers' 40,000, 41,000 and 59,000, e.g. the 22in. Model 59571 and the 26in. Model 59671. There's a main vertical panel into which a number of subpanels are plugged - the arrangement is shown in Fig. 1.
A self -oscillating chopper circuit (Siemens /Blaupunkt type) pro vides various regulated supplies, also mains isolation. See Fig. 2. The line output stage employs a BU208 transistor and an e.h.t. tripler. It requires a 150V h.t. supply with the 20AX tube, 155V with the 30AX - this is set with R623 on the chopper panel, at minimum brightness. Though they all look similar, different line output transformers are required with the different tube types.
The tripler also differs, due to the different focus voltage requirements of the 20AX and 30AX tubes.
A diode modulator is used for EW correction, driven by a BU125S transistor. The correction waveform is produced by an i.c., type TDA1082. See Fig. 4.
The field timebase consists of a TDA1170 followed by a three transistor driver/output stage. There's also an output stage flyback voltage dou bling circuit. See Fig. 3. Sync separation and line generation are carried out by a TDA2591 i.c. In later versions a different subpanel with a TDA2576A i.c. is used.
On the signals side there's a single i.c. (TDA2541) strip and a three chip (TDA2560/TDA2522/TDA2530) decoder. The RGB output stages are of the complemen- tary symmetry type (BF715/BF716 or BF869/BF870 transistors). There are two alternative sound modules. The basic one uses a TBA120U intercarrier sound chip followed by a TDA2611 audio chip that provides an output of 3-5W. For up-market models there's a board with TDA2790 and TDA2030 i.c.s delivering 15W and incorporating bass and treble controls.
In a set of this type, the no sound or picture symptom can be caused by many things. First check the 3.15AT 1 mains fuse Si601. If this is open -circuit, check the mains filter capacitors C601 and C603, the mains bridge rectifier G601 and the rectifier's protection capacitors C609-612.
If the mains input circuit is o.k., check R634 (1Mfl) and D632 (1N4007) in the chopper's start-up circuit. R634 can also be responsible for intermittent failure to operate.
It was subsequently reduced in value to 470kohm. Next check for dry -joints on the chopper transformer Tr601 and the chopper panel, then check the rectifier panel where the usual offenders are the 150/155V rectifier D651 (BY299) and its reservoir capacitor 0651 (47µF). They tend to go short-circuit. If everything is in order up to this point, it's necessary to pay closer attention to the chopper circuit. Check for voltage at the collector of the BU326A chopper transistor T622. If this if missing, check the continuity between pins 7 and 1 of the chopper transformer. If voltage is present, check the chopper circuit fuse Si621 (1.6A). If this is open -circuit, check the chopper transistor and the switch off thyristor Th621 (BR303) for being short-circuit. These two items must be replaced in pairs. If the power supply seems to be all right, move on to the line timebase. Check the 12V supply to pin 1 of the TDA2591. If missing, check the filter resistor R434 (120t1) for being open -circuit. If R434 is o.k. and the voltage at pin 1 of the i.c. is missing or low, suspect the i.c. With the TDA2576A the supply pin is 16 and the filter resistor R453 (56n, 1W). With both boards there should be 17.5V at pin 6 of the panel. Next check the line driver stage. There should be 150/ 155V at pins 9/10 of the line output subpanel. If there's no output from the driver, check the feed resistor R1005 (1.81cf1) for being open -circuit and its decoupler C1003 (0.047AF) for being short-circuit. If necessary check the transistor (T1001, type BD232) for being short-circuit or Leaky. Check for dry -joints at the pins of the line driver transformer U1001. On rare occasions you may find that the primary winding is open -circuit. The most likely cause of a dead line timebase is failure of the BU208 (T1002) line output transistor however. It usually goes short-circuit, and in this event R1008 (la) in its base circuit is likely to be open -circuit. If the line output transistor is all right, disconnect the lead from the line output transformer to the tripler. If the set then bursts into life either the tripler or the transformer is faulty. It's usually the tripler.
If the set is tripping, ensure that the line output stage h.t. voltage is correctly set (test point U4) for 150V or 155V depending on tube type. Adjust with R623. If R623 cannot be adjusted for the correct voltage, check transistor T621 (BC557) and zener diode D621 (BZX83C7.5) in the chopper control circuit. If the h.t. voltage is varying,
check the condition of R623's carbon track. Next check the line output transistor which could be short-circuit or leaky, and the EW modulator diodes D1001 (BY223) and D1002 (BYX71-600R). Finally check the line output transformer and tripler by dis- connection as previously described. Focus Faults The most likely cause of focus trouble is the control, which is mounted on the tripler. Less likely is the series resistor R1218 (imn) on the tube base panel (this resistor is not present in all models), the spark gap FU1, or corrosion on the focus pin. A faulty tripler is another possibility. The focus spark gap can also be responsible for intermittent focus variations. Collapsing Picture A collapsing picture with the sound cutting in and out as the picture collapses could be tripping, see above, or a faulty line output transistor. Line Timebase Faults For line collapse check the output transistor, the scan correction capacitor C1021 (1µF - check for being open - circuit or for dry -jointed leads), the scan coils, plugs and sockets, and for dry -joints on the linearity coil L1023. The linearity coil is the usual cause of line whstle - check by replacement.
For excessive width check whether the width control R396 is set correctly, then check D1002 in the diode modulator circuit and if necessary the line output transistor, both by replacement. If there's evidence of balloon- ing, suspect the tripler. For EW correction faults, check the modulator diodes D1001/2 and the driver transistor T371, then suspect the TDA1082 chip (IS371). If the line shift control has no effect, check the control itself and the resistor in series with its slider. With the TDA2591 these are R435 (47kf1) and R438 (180kfl) respectively. With the TDA2576A the control is R427 (100kti) and the series resistor R423 (100kfl). Field Collapse In the event of field collapse, first check that the 28V supply is reaching pin 2 of the TDA1170 i.c. If the voltage is very low, suspect the decoupling capacitor C310 or the chip. If there's no voltage, check back to the rectifier panel: D652 (BYW15200) could be open -circuit or C652 (220µF) short-circuit. If the supply is correct, check the following items: the field output transistors T304 and T305 (both BD537); the height control R321 (100.0), and R317 (6.8kft or 5-61d/ depending on model) which is in series with it; the scan coupling capacitor C361 (2,200µF); R951 (2.212) on the convergence board (20AX sets); finally, suspect the scan coils. Sync Troubles, For no sync at all, check the TDA2591/TDA2576A i.c.
For no field sync check the TDA1170, and C306 (0.01µF) for being short-circuit. Signal Faults If the sound is all right but there's a blank raster, check the TDA2541 i.f. i.c. In the event of tuning drift, check that the 50V supply from the line output stage is not varying. If it is, replace D1039 (BA157).
If the tuning voltage is varying, check R051 and R053 (both 2.2k0) and DO5 (ZTK33) by replacement. If the tuning voltage doesn't vary, suspect the tuner unit. In the event of the loss of one colour, check the appropriate first anode preset control for being open- circuit and the condition of its track, then check the relevant output transistors. If necessary check the voltages around the TDA2530 matrixing i.c. The TDA2522 demodulator i.c. is a less likely possibility. If the brightness level rises when the set has warmed up, check the TDA2560 chroma/luminance processing i.c. by substitution.
For no colour, first check the voltages around the TDA2522 demodulator/reference oscillator i.c. carefully. If necessary replace the i.c. Other causes we've had are the 8.8MHz crystal and dry -joints on the chroma delay line. The TDA2560 is a less likely possibility. If it's suspect after making voltage checks, replace it. We've had several cases of Venetian blinds. In this event check the setting of the amplitude control R755 and the condition of its track, then check that the phase coils L706/7 are set up correctly.
If still in trouble, check the chroma delay line by substitution. Sound, No Raster If sound is present but there's no raster, check the e.h.t. and first anode voltages.
Absence of e.h.t. points to the tripler while absence of first anode voltage is normally due to R1031 being open -circuit. It may be 560kfl or 2701d1 depending on model. If the c.r.t. heaters are out but the line timebase is operative, check R1208 (2.71/, 2W) on the tube base panel.
No Sound We'll deal with the basic sound module as we've not had much experience with the 15W one. In the event of no sound, check the following items: the loudspeaker for being open -circuit; the presence of the 28V supply at pin 12 of the sound module and the 12V supply at pin 7 - if 12V is not present at pin 11 of the TBA120U, check R504 (33a) for being open -circuit; the two chips; the coupling capacitor C531 (220µF).
For excessive width check whether the width control R396 is set correctly, then check D1002 in the diode modulator circuit and if necessary the line output transistor, both by replacement. If there's evidence of balloon- ing, suspect the tripler. For EW correction faults, check the modulator diodes D1001/2 and the driver transistor T371, then suspect the TDA1082 chip (IS371). If the line shift control has no effect, check the control itself and the resistor in series with its slider. With the TDA2591 these are R435 (47kf1) and R438 (180kfl) respectively. With the TDA2576A the control is R427 (100kti) and the series resistor R423 (100kfl). Field Collapse In the event of field collapse, first check that the 28V supply is reaching pin 2 of the TDA1170 i.c. If the voltage is very low, suspect the decoupling capacitor C310 or the chip. If there's no voltage, check back to the rectifier panel: D652 (BYW15200) could be open -circuit or C652 (220µF) short-circuit. If the supply is correct, check the following items: the field output transistors T304 and T305 (both BD537); the height control R321 (100.0), and R317 (6.8kft or 5-61d/ depending on model) which is in series with it; the scan coupling capacitor C361 (2,200µF); R951 (2.212) on the convergence board (20AX sets); finally, suspect the scan coils. Sync Troubles, For no sync at all, check the TDA2591/TDA2576A i.c.
For no field sync check the TDA1170, and C306 (0.01µF) for being short-circuit. Signal Faults If the sound is all right but there's a blank raster, check the TDA2541 i.f. i.c. In the event of tuning drift, check that the 50V supply from the line output stage is not varying. If it is, replace D1039 (BA157).
If the tuning voltage is varying, check R051 and R053 (both 2.2k0) and DO5 (ZTK33) by replacement. If the tuning voltage doesn't vary, suspect the tuner unit. In the event of the loss of one colour, check the appropriate first anode preset control for being open- circuit and the condition of its track, then check the relevant output transistors. If necessary check the voltages around the TDA2530 matrixing i.c. The TDA2522 demodulator i.c. is a less likely possibility. If the brightness level rises when the set has warmed up, check the TDA2560 chroma/luminance processing i.c. by substitution.
For no colour, first check the voltages around the TDA2522 demodulator/reference oscillator i.c. carefully. If necessary replace the i.c. Other causes we've had are the 8.8MHz crystal and dry -joints on the chroma delay line. The TDA2560 is a less likely possibility. If it's suspect after making voltage checks, replace it. We've had several cases of Venetian blinds. In this event check the setting of the amplitude control R755 and the condition of its track, then check that the phase coils L706/7 are set up correctly.
If still in trouble, check the chroma delay line by substitution. Sound, No Raster If sound is present but there's no raster, check the e.h.t. and first anode voltages.
Absence of e.h.t. points to the tripler while absence of first anode voltage is normally due to R1031 being open -circuit. It may be 560kfl or 2701d1 depending on model. If the c.r.t. heaters are out but the line timebase is operative, check R1208 (2.71/, 2W) on the tube base panel.
No Sound We'll deal with the basic sound module as we've not had much experience with the 15W one. In the event of no sound, check the following items: the loudspeaker for being open -circuit; the presence of the 28V supply at pin 12 of the sound module and the 12V supply at pin 7 - if 12V is not present at pin 11 of the TBA120U, check R504 (33a) for being open -circuit; the two chips; the coupling capacitor C531 (220µF).
KORTING MARATHON VTS FFS 22" 41531 CHASSIS 9 G-030AD1 Controlled power supply for a television receiver equipped with remote control:BLAUPUNKT SWITCH MODE POWER SUPPLY.Blaupunkt-Werke GmbH (Hildesheim, DT)
A single isolation transformer supplies both the remote control receiver and the television receiver. A pulse generator such as a blocking oscillator which energizes the primary winding of the isolation transformer has its pulse width controlled in response to the loading of the circuit of the secondary winding of the isolation transformer, as measured by the voltage across a resistor in the circuit of a primary winding. This measuring resistor is interposed between the emitter of the switching transistor of the blocking oscillator and the receiver chassis. A transistor switching circuit for cutting off the low voltage supply to the scanning circuit oscillators of the television receiver is responsive to the output of the remote control receiver, to a signal from an operating control of the television receiver, and to an indication of overcurrent in the picture tube, independently.
1. A power supply circuit for a television receiver equipped for remote control comprising, in combination:
an on-off switch for connecting and disconnecting the television receiver and its power supply circuit respectively to and from the electricity supply mains;
pulse generating means arranged for energization through said on-off switch;
an isolation transformer having its primary winding supplied with the output of said pulse generating means;
a power conversion circuit connected to the secondary winding of said isolation transformer for energization thereby, for supplying an operating voltage for the scanning circuits of the television receiver and for supplying a plurality of other voltages to said receiver, at least one of which other voltages is also supplied to said scanning circuits;
a remote control signal receiver for remote control of said television receiver and controlled switching means responsive to said remote control receiver for switching said television receiver between a stand-by condition and an operating condition, both said remote control receiver and said controlled switching means being connected to a secondary winding of said isolation transformer for energization thereby, said controlled switching means having a switching path for connecting and disconnecting said scanning circuits of said television receiver respectively to and from a source of said operating voltage in said power conversion circuit and
means for reducing energy transfer through said pulse generating means to said isolation transformer when said television receiver is in the stand-by condition.
2. A power supply circuit as defined in claim 1, in which said pulse generating means includes rectifying means energized through said on-off switch for supplying direct current for energization of said pulse generating means. 3. A power supply circuit as defined in claim 2, in which said energy transfer reducing means includes means for varying the width (duration) of pulses generated by said pulse generating means in response to the extent of loading of the secondary circuit of said isolating transformer as measured in the primary circuit of said transformer. 4. A power supply circuit as defined in claim 2, in which said pulse generating means includes a blocking oscillator and said energy transfer reducing means includes means for reducing the width (duration) of the pulses generated by said blocking oscillator. 5. A power supply circuit as defined in claim 4, in which said blocking oscillator includes a switching transistor (5) and a load measuring resistor (7) interposed in a connection between the emitter of said switching transistor and the receiver chassis, and in which said pulse width reducing means is responsive to the voltage drop across said load measuring resistor. 6. A power supply circuit as defined in claim 5, in which said pulse width reducing means includes a controllable resistance (10) in the circuit of said blocking oscillator controlled in response to the voltage drop across said load measuring resistor. 7. A power supply circuit as defined in claim 1, in which said operating voltage connected and disconnected to said scanning circuits by said controlled switching means is the low voltage supply voltage (U 3') of the line scan and picture scan oscillators of the television receiver and in which said controlled switching means is controlled so as to switch off said low voltage supply voltage to put the television receiver in the stand-by condition. 8. A power supply circuit as defined in claim 7, in which said controlled switching means includes a first switching transistor (15) at the collector of which there is applied a direct current supply voltage (U 3) energized through said isolating transformer and a second switching transistor (24) for controllably short-circuiting the base bias of said first switching transistor, whereby a stabilized low voltage (U 3') exists at the emitter of said first switching transistor (15) when a positive signal is supplied from an operating control of the television receiver or from said remote control receiver to the base of said second switching transistor (24). 9. A power supply circuit as defined in claim 7, in which said controlled switching means is responsive independently to an overcurrent condition in the picture tube for switching off said low voltage supply voltage (U 3') in response to said overcurrent condition.
Description:
The present invention relates to a power supply unit including a blocking oscillator for utilization with a television receiver provided with ultrasonic remote control, and more particularly to a television receiver the operating conditions of which are normal operation, a stand-by operation, and the turned-off condition, and a power supply unit therefor that includes an isolating transformer.
In recent times television receivers have frequently been provided with ultrasonic remote control devices for the purpose of offering easier control. As more and more television receivers are utilized in combination with additional equipment, it becomes increasingly necessary to connect the receivers only indirectly to the electric power mains (house wiring). In a known advantageous solution of this problem, a power supply unit includes an isolating transformer which is wired up with a blocking oscillator in the primary circuit. The blocking oscillator is supplied with a d-c voltage which is obtained by rectification of the supply voltage. Compared to the isolating transformers which are directly mains-operated, these so-called switch-mode power supply units have the advantage that they can be made in considerably smaller size, as they are operated at a significantly higher frequency, and the further advantage that they require less expensive means for rectification.
It is necessary to supply television receivers equipped with ultrasonic remote control with the possibility for a stand-by operation in which only the ultransonic receiver is supplied with power and, in some cases, also the heating current for the picture tube. Usually a separate power supply unit is provided for the ultrasonic receiver and the heating of the picture tube, a unit that includes an isolating transformer of its own, the primary winding of which is directly mains-fed. Upon transition from normal operation to stand-by operation, the power supply unit of the blocking osciallator is switched off, so that the television receiver receives only the relatively small quantity of energy required for the ultrasonic receiver and, in some cases, also for the heating of the picture tube.
Because of the required second isolating transformer, this known circuit has the disadvantages that it requires both greater space and greater expenditure.
It is the object of the present invention to develop a simplified power supply unit which does not have the above-mentioned disadvantages.
SUMMARY OF THE INVENTION
Briefly, the television receiver and the ultrasonic receiver are connected to the same isolating transformer; means for the switching from normal operation to stand-by operation and vice versa are placed in the secondary circuit of the isolating transformer, and means are arranged in the primary circuits of the isolating transformer for reducing the amount of energy made available for stand-by operation purposes.
The main advantages of the present invention are that no separate isolating transformer is required for supplying the current during the stand-by operation, and that, during the stand-by operation, it is nevertheless only the power required for this operation which is consumed.
An advantageous embodiment of the present invention obtains reduction of the energy quantum transmitted through the power supply during stand-by by reduction of the pulse width of the pulses generated by the blocking oscillator.
Another advantageous embodiment of the present invention utilizes measurement in the primary circuit of the isolating transformer of variation in load occurring in the secondary circuit as a control variable for determining the pulse width.
A further advantageous embodiment of the present invention obtains the control variable for the pulse width across a measuring resistor interposed in the connection of the emitter of the switching transistor of the blocking oscillator to the chassis.
Still another advantageous embodiment of the present invention provides that the voltage drop across the measuring resistor controls a controllable resistor.
The advantageous embodiments described above offer highly simple and advantageous possibilities for measuring the variation in load upon switching between normal and stand-by operation, as well as for the consequent control of the energy transmitted via the isolating transformer.
The possibility of a simple and inexpensive switching between normal and stand-by operation is achieved by effecting the switching between normal and stand-by operation by means of switching on or switching off, respectively, the low voltage supply of the line scan oscillator, and, especially, by a first switching transistor which short-circuits the base bias of a second switching transistor at the collector of which a direct current supply voltage is present and at the emitter of which a stabilized low voltage exists, when a positive signal is supplied from the operating control of the television receiver or from the remote control receiver to the base of the first switching transistor.
The circuit arrangements just mentioned offer the advantage that they may simultaneously be utilized as a protective circuit. This is achieved by a switching-off device for the low voltage which can also be triggered at any time by a signal built up by overcurrent in the picture tube.
BRIEF DESCRIPTION OF THE DRAWINGS
The invention is further described by way of illustrative example by reference to the annexed drawings in which:
FIG. 1 is a circuit diagram, partly in block form, of an embodiment of the invention;
FIG. 2 is a circuit diagram of one form of means for interrupting the power to the picture circuits in the stand-by condition in connection with the circuit of FIG. 1, and
FIG. 3 is a circuit diagram of one way of controlling the pulse width of the blocking oscillator 4 in response to the switching circuit 8 in the circuit of FIG. 1.
DESCRIPTION OF THE PREFERRED EMBODIMENT
An on-off power switch 2 of the television receiver is connected to the supply terminals 1, providing a primary operating control for the receiver. Consquently, the supply voltage is also present at the output of the operating control 2 when the television receiver is turned on thereby, and arrives at a rectifying stage 3 comprising means for rectifying and smoothing the supply current as well as for suppressing interference. A d-c voltage, feeding a blocking oscillator stage 4, is present at the output of the recifying stage 3. The main part of the blocking oscillator 4, symbolically represented in FIG. 1 by a fragmentary circuit diagram, is a switching transistor 5, in the load circuit of which the primary winding of an isolating tranformer 6 is placed. A measuring resistor 7 is connected between the emitter of the switching transistor 5 and the chassis, across which measuring resistor a voltage is taken and applied to a load-dependent control circuit 8. The voltage taken at the measuring resistor 7 is fed via a resistor 9 to the base of a transistor 10 which serves as a controllable load for the blocking oscillator 4. A resistor 11 and a capacitor 12, each of which is connected to chassis with its other terminal, are also connected to the base of the transistor 10. The emitter of transistor 10 is connected to chassis, while the collector of the transistor 10 is connected back to the blocking oscillator stage 4.
In the secondary circuit of the isolating transformer 6, a d-c voltage supply stage or power conversion circuit 13 is placed, substantially consisting of a rectifying circuit 14, which, in the example shown, is provided with six outputs at which the voltages U 1 to U 5 can be taken off with respect to the sixth output connected to the chassis. At the terminal U 3, there is, in addition, a branch feeding both the collector-to-emitter path of the transistor 15 and also, through a resistor 16, the collector-to-emitter path of the transistor 15a. The emitter of the transistor 15a is directly connected to the base of transistor 15. The emitter of the transistor 15 is connected to chassis via a series connection of a resistor 17, a potentiometer 18, and a further resistor 19. The tap of the potentiometer 18 is connected to the base of a further transistor 20. The transistor 20 is connected to chassis by means of its emitter via a Zener diode 21, the collector of the transistor 20 controlling the base of the transistor 15a. The emitter of the transistor 20 is connected to the emitter of the transistor 15 via a resistor 22. A terminal for tapping off the voltage U 3' is connected to the emitter of the transistor 15.
The base of the transistor 15a is connected to a switching stage 23 responsive to a remote control ultrasonic receiver by a conductor leading to the collector of a switching transistor 24 which is connected to chassis via its emitter. The base of the switching transistor 24 is connected to an input terminal 28 leading into the television receiver via two resistors 25, 26 and a capacitor 27 connected in series, that input terminal 28 passing on switching signals from the receiver to the switching transistor 24, as will be explained in more detail below.
The cathode of a diode 29, which is connected to chassis via its anode, is connected to the junction point of the resistor 26 and the capacitor 27. The junction point of the two resistors 25, 26 is connected to chassis via a capacitor 30. The base of the switching transistor 24 is connected to chassis via a resistor 31. Furthermore, that base electrode is also connected to a terminal 32 to which an electrical switching signal is applied which is either built up in response to an ultrasonic signal received by the remote control receiver 32' or is supplied from an operating control of the television receiver. At the terminal 32, the switching transistor 24 receives the signal containing the information whether the television receiver is to work in the normal operating condition, i.e. to receive and process the sound and video signals, or in the stand-by condition in which it is substantially only the ultrasonic receiver that is supplied with current.
When a positive signal arrives at the base of the switching transistor 24, the latter becomes conductive, and causes chassis potential to be present at the base of transistor 15a. The transistor 15 is thereby blocked, and there is no longer any voltage at the terminal U 3'. Since the voltage U 3' serves as an operating voltage for the line and picture scan oscillator, the deflecting stages of the receiver cannot work and no high voltage and other related supply voltages are generated at the line circuit transformer. In consequence, by means illustrated diagrammatically in FIG. 2, the electric circuits connected to the terminals U 1 to U 3 are interrupted. The voltages U 4 and U 5 serve for supplying the ultrasonic receiver, i.e. they are required for the stand-by operation.
In case no counteracting means should be provided for, the variation in load would cause a voltage rise in the secondary circuit of the isolating transformer 6, which effect is, of course, not desired. Therefore, a measuring resistor is connected in the primary circuit in the emitter line of the switching transistor 5 of the blocking oscillator 6, the variation in load in the secondary circuit appearing at the measuring resistor 7 as a current variation. The current change thus produced, causes a variation in the base bias of the transistor 10, the capacitor 12 having an integrating effect to avoid undesired effects due to interference pulses and abrupt load fluctuations.
The change of the working point of the transistor 10 causes a change in the pulse width in the blocking oscillator stage 4, as more fully shown in FIG. 3, so that the energy quantum transmitted via the isolating transformer 6 is such that the required voltages are present in the secondary circuit. It should also be mentioned that the load-dependent switch 8 and the circuit of FIG. 3 are represented only by way of illustration and that many circuit arrangements may be devised by straight-forward application of known principles for controlling the pulse width.
The circuit connected between the terminal 28 and the base of the switching transistor 24 serves as a part of a protective circuit for the picture tube. Any overcurrent is measured at the low-end resistor 31 of the high-voltage cascade in conventional techinque. The voltage thus produced is fed to the base of the switching transistor 24, and causes the television receiver to be switched over to stand-by operation, so that no damage can be done to the picture tube. Thus, the device performing the switching between normal operation and stand-by operation is advantageously and simultaneously utilized as a protective circuit. The circuit 23, as shown, provides for stabilizing the potential at the base of transistor 24 and for integrating such possibly occurring overload peaks as are not intended to triggering the protective circuit.
Using the circuit diagram according to FIG. 3 it is possible in a simple manner to control the pulse width of the blocking oscillator 4 in response to the switching circuit 8.
According to the circuit diagram of FIG. 2 the terminal U1 is connected to a line scan oscillator circuit 40, the terminal U2 to a picture scan oscillator circuit 41 and the terminal U3 to a circuit 42 for a sound output stage. The circuits 40, 41, 42 get their operating voltage from the terminal U3'. If the operating voltage U3' is zero, the circuits 40, 41, 42 are interrupted. In this case the voltages at the terminals U1, U2, U3 remain.
The described circuit of this invention for controlling the voltage in the secondary circuit of the isolating transformer 6 offers the advantage that it is exclusively arranged in the primary circuit, and, therefore, permits an uncomplicated design which is easy to realize. To control the pulse width by measuring the load fluctuations at the low-end resistor of the switching transistor 5, represents a very useful means for control since, thereby the transmitted energy can effectively and easily be controlled.
The blocking oscillator stage 4 shown in detail in FIG. 3 incorporates an externally triggered blocking oscillator arranged to be triggered through an oscillator operating preferably at the line scanning frequency, which is to say its wave form is not particularly critical and it should be provided with means to keep it in step with the line scanning frequency, as is known to be desirable. The transistors 51 and 52 of the triggered output stage of the blocking oscillator circuit could be regarded as constituting a differential amplifier the inputs of which are defined by the base connections of the respective transistors 51 and 52. The input voltage applied to the base connection of transistor 52 is the Zener voltage of the Zener diode 53, thus a constant reference voltage. The operating voltage for the transistors 51 and 52 and for the Zener diode 53 is obtained from the supply voltage UB, which is to say from the rectifier 3. The diode 67 protects the transistor 52, for example at the time of the apparatus being switched on, against damage from an excessively high emitter-base blocking voltage. The capacitor 65 prevents undesired oscillation of the circuit of transistors 51 and 52, which could give rise to undesired disturbances.
At the base of the transistor 51, there is present as input voltage for the circuit a composite voltage that is the sum of three voltages. These are, first, the line scan frequency trigger voltage coupled through the capacitor 63; second, a bias voltage dependent upon the loading of the blocking oscillator stage resulting from the load on the secondary of the transformer 6, but detected by the voltage across the resistor 7 and actually controlled by the load-sensitive control circuit 8, and, third, a regulating voltage applied at the terminal 71 of the resistor 70, which regulating voltage is proportional to the voltage of the secondary winding of the transformer 6 and can accordingly be provided by one or another of the output circuits of the rectifier 14 of FIG. 1 or by a separate winding of the transformer 6 and a separate rectifier element connected in circuit therewith. This regulating voltage and the control voltage provided by the control circuit 8 are applied to the resistor 61 which completes the circuit for both of these bias voltages and their combined effect constitutes the bias voltage for the transistor 51 which determines its working point.
The circuit of the transistors 51 and 52 operates as an overdriven differential amplifier. When the trigger voltage exceeds the threshold determined by the base voltage of the transistor 51, the circuit produces an approximately rectangular output voltage pulse of constant amplitude. Since the trigger voltage is recurrent, the result is a periodic succession of rectangular output voltage pulses, but the duration or pulse width of these pulses depends upon the loading and the output voltage of the stage. The output voltage of the circuit constituted by the transistors 51 and 52 comes from the emitter connection of the transistor 52 and is furnished to the switching transistor 5, preferably through a driver stage 54, such as a transformer or another transistor stage for better matching of the circuit impedances. Of course, the collector circuit of the transistor 5 includes the primary winding of the transformer 6 of FIG. 1.
The described power supply unit thus represents a well functioning component subject to but a small number of potential sources of error, due to the simple design, and permits considerable reduction of costs in comparison with circuits and equipment heretofore known.
TBA120S
TDA2611A 5 W audio power amplifier
The TDA2611A is a monolithic integrated circuit in a 9-lead single in-line (SIL) plastic package with a high supply voltage
audio amplifier. Special features are:
· possibility for increasing the input impedance
· single in-line (SIL) construction for easy mounting
· very suitable for application in mains-fed apparatus
· extremely low number of external components
· thermal protection
· well defined open loop gain circuitry with simple quiescent current setting and fixed integrated closed loop gain.
RATINGS
Limiting values in accordance with the Absolute Maximum System (IEC 134)
Supply voltage VP max. 35 V
Non-repetitive peak output current IOSM max. 3 A
Repetitive peak output current IORM max. 1,5 A
Total power dissipation see derating curves Fig. 2
Storage temperature Tstg -55 to + 150 °C
Operating ambient temperature Tamb -25 to + 150 °C
SAB3024 COMPUTER INTERFACE FOR TUNING AND CONTROL (CITAC)
GENERAL DESCRIPTION
The SAB3024 provides closed-loop digital tuning of TV receivers, with or without a.f.c., as required. lt
also controls up to 8 analogue functions, 4 general purpose I/O ports and 4 high-current outputs for
tuner band selection.
The IC is used in conjunction with a microcomputer from the MAB84OO family and is controlled via a two-wire, bidirectional I2 C bus.
Featu res
Combined analogue and digital circuitry minimizes the number of additional interfacing components
required
Frequency measurement with resolution of 50 KHz
Selectable prescaler divisor of 64 or 256
32 V tuning voltage amplifier
4 high-current outputs for direct band selection
8 static digital to analogue converters (DACSI for control of analogue functions
Four general purpose input/output (l/O) ports
Tuning with control of speed and direction
Tuning with or without a.f.c.
Single-pin, 4 MHZ on-chip oscillator
I2 C bus slave transceiver
FUNCTIONAL DESCRIPTION
The SAB3024 is a monolithic computer interface which provides tuning and control functions and
operates in conjunction with a microcomputer via an I2 C bus.
Tuning
This is performed using frequency-locked loop digital control. Data corresponding to the required tuner
frequency is stored in a 15-bit frequency buffer. The actual tuner frequency, divided by a factor of 256
(or by 64) by a prescaler, is applied via a gate to a 15-bit frequency counter. This input (FDIV) is
measured over a period controlled by a time reference counter and is compared with the contents of the frequency buffer. The result of the comparison is used to control the tuning voltage so that the tuner frequency equals the contents of the frequency buffer multiplied by 50 kHz within a programmable tuning window (TUW).
The system cycles over a period of 6,4 ms (or 2,56 ms), controlled by the time reference counter which is clocked by an on-chip 4 lVlHz reference oscillator. Regulation of the tuning voltage is performed by a charge pump frequency-locked loop system. The charge IT flowing into the tuning voltage amplifier is controlled by the tuning counter, 3-bit DAC and the charge pump circuit. The charge IT is linear with the frequency deviation Af in steps of 50.
CRT TV EHT VOLTAGE MULTIPLIER - KASKADE COCKCROFT-WALTON CASCADE CIRCUIT FOR VOLTAGE MULTIPLICATION:
A Cockcroft-Walton cascade circuit comprises an input voltage source and a pumping and storage circuit with a series array of capacitors with pumping and storage portions of the circuit being interconnected by silicon rectifiers, constructed and arranged so that at least the capacitor nearest the voltage source, and preferably one or more of the next adjacent capacitors in the series array, have lower tendency to internally discharge than the capacitors in the array more remote from the voltage source.
1. An improved voltage multiplying circuit comprising,
2. An improved voltage multiplying circuit in accordance with claim 1 wherein said first pumping capacitor is a self-healing impregnated capacitor which is impregnated with a high voltage impregnant.
3. An improved voltage multiplying circuit in accordance with claim 1 wherein said first pumping capacitor comprises a foil capacitor.
Description:
BACKGROUND OF THE INVENTION
The invention relates in general to Cockcroft-Walton cascade circuits for voltage multiplication and more particularly to such circuits with a pumping circuit and a storage circuit composed of capacitors connected in series, said pumping circuits and storage circuit being linked with one another by a rectifier circuit whose rectifiers are preferably silicon rectifiers, especially for a switching arrangement sensitive to internal discharges of capacitors, and more especially a switching arrangement containing transistors, and especially an image tube switching arrangement.
Voltage multiplication cascades composed of capacitors and rectifiers are used to produce high D.C. voltages from sinusoidal or pulsed alternating voltages. All known voltage multiplication cascades and voltage multipliers are designed to be capacitance-symmetrical, i.e., all capacitors used have the same capacitance. If U for example is the maximum value of an applied alternating voltage, the input capacitor connected directly to the alternating voltage source is charged to a D.C. voltage with a value U, while all other capacitors are charged to the value of 2U. Therefore, a total voltage can be obtained from the series-connected capacitors of a capacitor array.
In voltage multipliers, internal resistance is highly significant. In order to obtain high load currents on the D.C. side, the emphasis in the prior art has been on constructing voltage multipliers with internal resistances that are as low as possible.
Internal resistance of voltage multipliers can be reduced by increasing the capacitances of the individual capacitors by equal amounts. However, the critical significance of size of the assembly in the practical application of a voltage multiplier, limits the extent to which capacitance of the individual capacitors can be increased as a practical matter.
In television sets, especially color television sets, voltage multiplication cascades are required whose internal resistance is generally 400 to 500 kOhms. Thus far, it has been possible to achieve this low internal resistance with small dimensions only by using silicon diodes as rectifiers and metallized film capacitors as the capacitors.
When silicon rectifiers are used to achieve low internal resistance, their low forward resistance produces high peak currents and therefore leads to problems involving the pulse resistance of the capacitors. Metallized film capacitors are used because of space requirements, i.e., in order to ensure that the assembly will have the smallest possible dimensions, and also for cost reasons. These film capacitors have a self-healing effect, in which the damage caused to the capacitor by partial evaporation of the metal coating around the point of puncture (pinhole), which develops as a result of internal spark-overs, is cured again. This selfhealing effect is highly desirable as far as the capacitors themselves are concerned, but is not without its disadvantages as far as the other cirucit components are concerned, especially the silicon rectifiers, the image tubes, and the components which conduct the image tube voltage.
It is therefore an important object of the invention to improve voltage multiplication cascades of the type described above.
It is a further object of the invention to keep the size of the entire assembly small and the internal resistance low.
It is a further object of the invention to increase pulse resistance of the entire circuit.
It is a further object of the invention to avoid the above-described disadvantageous effects on adjacent elements.
It is a further object of the invention to achieve multiples of the foregoing objects and preferably all of them consistent with each other.
SUMMARY OF THE INVENTION
In accordance with the invention, the foregoing objects are met by making at least one of the capacitors in the pumping circuit, preferably including the one which is adjacent to the input voltage source, one which is less prone to internal discharges than any of the individual capacitors in the storage circuit.
The Cockcroft-Walton cascade circuit is not provided with identical capacitors. Instead, the individual capacitors are arranged according to their loads and designed in such a way that a higher pulse resistance is attained only in certain capacitors. It can be shown that the load produced by the voltage in all the capacitors in the multiplication circuit is approximately the same. But the pulse currents of the capacitors as well as their forward flow angles are different. In particular, the capacitors of the pumping circuit are subjected to very high loads in a pulsed mode. In the voltage multiplication cascade according to the invention, these capacitors are arranged so that they exhibit fewer internal discharges than the capacitors in the storage circuit.
The external dimensions of the entire assembly would be unacceptably large if one constructed the entire switching arrangement using such capacitors.
The voltage multiplication cascade according to the invention also makes it possible to construct a reliably operating
arrangement which has no tendency toward spark-overs, consistent with satisfactory internal resistance of the voltage multiplication cascade and small dimensions of the entire assembly. This avoids the above cited disadvantages with respect to the particularly sensitive components in the rest of the circuit and makes it possible to design voltage multiplication cascades with silicon rectifiers, which are characterized by long lifetimes. Hence, a voltage multiplication cascade has been developed particularly for image tube circuits in television sets, especially color television sets, and this cascade satisfies the highest requirements in addition to having an average lifetime which in every case is greater than that of the television set.
A further aspect of the invention is that at least one of the capacitors that are less prone to internal discharges is a capacitor which is impregnated with a high-voltage impregnating substance, especially a high-voltage oil such as polybutene or silicone oil, or mixtures thereof. In contrast to capacitors made of metallized film which have not been impregnated, this allows the discharge frequency due to internal discharges or spark-overs to be reduced by a factor of 10 to 100.
According to a further important aspect of the invention, at least one of the capacitors that are less prone to internal discharges is either a foil capacitor or a self-healing capacitor. In addition, the capacitor in the pumping circuit which is adjacent to the voltage source input can be a foil capacitor which has been impregnated in the manner described above, while the next capacitor in the pumping circuit is a self-healing capacitor impregnated in the same fashion.
Other objects, features and advantages of the invention will be apparent from the following detailed description of preferred embodiments, taken in connection with the accompanying drawing, the single FIGURE of which:
BRIEF DESCRIPTION OF THE DRAWING
is a schematic diagram of a circuit made according to a preferred embodiment of the invention.
DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS
The voltage multiplier comprises capacitors C1 to C5 and rectifiers D1 to D5 connected in a cascade. An alternating voltage source UE is connected to terminals 1 and 2, said voltage source supplying for example a pulsed alternating voltage. Capacitors C1 and C2 form the pumping circuit while capacitors C3, C4 and C5 form the storage circuit.
In the steady state, capacitor C1 is charged to the maximum value of the alternating voltage UE as are the other capacitors C2 to C5. The desired high D.C. voltage UA is picked off at terminals 3 and 4, said D.C. voltage being composed of the D.C. voltages from capacitors C3 to C5. Terminal 3 and terminal 2 are connected to one pole of the alternating voltage source UE feeding the circuit, which can be at ground potential. In the circuit described here, a D.C. voltage UA can be picked off whose voltage value is approximately 3 times the maximum value of the pulsed alternating voltage UE. By using more than five capacitors, a correspondingly higher D.C. voltage can be obtained.
The individual capacitors are discharged by disconnecting D.C. voltage UA. However, they are constantly being recharged by the electrical energy supplied by the alternating voltage source UE, so that the voltage multiplier can be continuously charged on the output side.
According to the invention, in this preferred embodiment, capacitor C1 and/or C2 in the pumping circuit are designed so that they have a lower tendency toward internal discharges than any of the individual capacitors C3, C4 and C5 in the storage circuit.
It is evident that those skilled in the art, once given the benefit of the foregoing disclosure, may now make numerous other uses and modifications of, and departures from the specific embodiments described herein without departing from the inventive concepts. Consequently, the invention is to be construed as embracing each and every novel feature and novel combination of features present in, or possessed by, the apparatus and techniques herein disclosed and limited solely by the scope and spirit of the appended claims.
Inventors:Petrick, Paul (Landshut, DT)
Schwedler, Hans-peter (Landshut, DT)
Holzer, Alfred (Schonbrunn, DT)
ERNST ROEDERSTEIN SPEZIALFABRIK
US Patent References:
3714528 ELECTRICAL CAPACITOR WITH FILM-PAPER DIELECTRIC 1973-01-30 Vail
3699410 SELF-HEALING ELECTRICAL CONDENSER 1972-10-17 Maylandt
3463992 ELECTRICAL CAPACITOR SYSTEMS HAVING LONG-TERM STORAGE CHARACTERISTICS 1969-08-26 Solberg
3457478 WOUND FILM CAPACITORS 1969-07-22 Lehrer
3363156 Capacitor with a polyolefin dielectric 1968-01-09 Cox
2213199 Voltage multiplier 1940-09-03 Bouwers et al.
KORTING MARATHON VTS FFS 22" 41531 CHASSIS G-030AD1 Channel selector having a plurality of tuning systems:
TBA120S
TDA2611A 5 W audio power amplifier
The TDA2611A is a monolithic integrated circuit in a 9-lead single in-line (SIL) plastic package with a high supply voltage
audio amplifier. Special features are:
· possibility for increasing the input impedance
· single in-line (SIL) construction for easy mounting
· very suitable for application in mains-fed apparatus
· extremely low number of external components
· thermal protection
· well defined open loop gain circuitry with simple quiescent current setting and fixed integrated closed loop gain.
RATINGS
Limiting values in accordance with the Absolute Maximum System (IEC 134)
Supply voltage VP max. 35 V
Non-repetitive peak output current IOSM max. 3 A
Repetitive peak output current IORM max. 1,5 A
Total power dissipation see derating curves Fig. 2
Storage temperature Tstg -55 to + 150 °C
Operating ambient temperature Tamb -25 to + 150 °C
SAB3024 COMPUTER INTERFACE FOR TUNING AND CONTROL (CITAC)
GENERAL DESCRIPTION
The SAB3024 provides closed-loop digital tuning of TV receivers, with or without a.f.c., as required. lt
also controls up to 8 analogue functions, 4 general purpose I/O ports and 4 high-current outputs for
tuner band selection.
The IC is used in conjunction with a microcomputer from the MAB84OO family and is controlled via a two-wire, bidirectional I2 C bus.
Featu res
Combined analogue and digital circuitry minimizes the number of additional interfacing components
required
Frequency measurement with resolution of 50 KHz
Selectable prescaler divisor of 64 or 256
32 V tuning voltage amplifier
4 high-current outputs for direct band selection
8 static digital to analogue converters (DACSI for control of analogue functions
Four general purpose input/output (l/O) ports
Tuning with control of speed and direction
Tuning with or without a.f.c.
Single-pin, 4 MHZ on-chip oscillator
I2 C bus slave transceiver
FUNCTIONAL DESCRIPTION
The SAB3024 is a monolithic computer interface which provides tuning and control functions and
operates in conjunction with a microcomputer via an I2 C bus.
Tuning
This is performed using frequency-locked loop digital control. Data corresponding to the required tuner
frequency is stored in a 15-bit frequency buffer. The actual tuner frequency, divided by a factor of 256
(or by 64) by a prescaler, is applied via a gate to a 15-bit frequency counter. This input (FDIV) is
measured over a period controlled by a time reference counter and is compared with the contents of the frequency buffer. The result of the comparison is used to control the tuning voltage so that the tuner frequency equals the contents of the frequency buffer multiplied by 50 kHz within a programmable tuning window (TUW).
The system cycles over a period of 6,4 ms (or 2,56 ms), controlled by the time reference counter which is clocked by an on-chip 4 lVlHz reference oscillator. Regulation of the tuning voltage is performed by a charge pump frequency-locked loop system. The charge IT flowing into the tuning voltage amplifier is controlled by the tuning counter, 3-bit DAC and the charge pump circuit. The charge IT is linear with the frequency deviation Af in steps of 50.
A Cockcroft-Walton cascade circuit comprises an input voltage source and a pumping and storage circuit with a series array of capacitors with pumping and storage portions of the circuit being interconnected by silicon rectifiers, constructed and arranged so that at least the capacitor nearest the voltage source, and preferably one or more of the next adjacent capacitors in the series array, have lower tendency to internally discharge than the capacitors in the array more remote from the voltage source.
1. An improved voltage multiplying circuit comprising,
2. An improved voltage multiplying circuit in accordance with claim 1 wherein said first pumping capacitor is a self-healing impregnated capacitor which is impregnated with a high voltage impregnant.
3. An improved voltage multiplying circuit in accordance with claim 1 wherein said first pumping capacitor comprises a foil capacitor.
Description:
BACKGROUND OF THE INVENTION
The invention relates in general to Cockcroft-Walton cascade circuits for voltage multiplication and more particularly to such circuits with a pumping circuit and a storage circuit composed of capacitors connected in series, said pumping circuits and storage circuit being linked with one another by a rectifier circuit whose rectifiers are preferably silicon rectifiers, especially for a switching arrangement sensitive to internal discharges of capacitors, and more especially a switching arrangement containing transistors, and especially an image tube switching arrangement.
Voltage multiplication cascades composed of capacitors and rectifiers are used to produce high D.C. voltages from sinusoidal or pulsed alternating voltages. All known voltage multiplication cascades and voltage multipliers are designed to be capacitance-symmetrical, i.e., all capacitors used have the same capacitance. If U for example is the maximum value of an applied alternating voltage, the input capacitor connected directly to the alternating voltage source is charged to a D.C. voltage with a value U, while all other capacitors are charged to the value of 2U. Therefore, a total voltage can be obtained from the series-connected capacitors of a capacitor array.
In voltage multipliers, internal resistance is highly significant. In order to obtain high load currents on the D.C. side, the emphasis in the prior art has been on constructing voltage multipliers with internal resistances that are as low as possible.
Internal resistance of voltage multipliers can be reduced by increasing the capacitances of the individual capacitors by equal amounts. However, the critical significance of size of the assembly in the practical application of a voltage multiplier, limits the extent to which capacitance of the individual capacitors can be increased as a practical matter.
In television sets, especially color television sets, voltage multiplication cascades are required whose internal resistance is generally 400 to 500 kOhms. Thus far, it has been possible to achieve this low internal resistance with small dimensions only by using silicon diodes as rectifiers and metallized film capacitors as the capacitors.
When silicon rectifiers are used to achieve low internal resistance, their low forward resistance produces high peak currents and therefore leads to problems involving the pulse resistance of the capacitors. Metallized film capacitors are used because of space requirements, i.e., in order to ensure that the assembly will have the smallest possible dimensions, and also for cost reasons. These film capacitors have a self-healing effect, in which the damage caused to the capacitor by partial evaporation of the metal coating around the point of puncture (pinhole), which develops as a result of internal spark-overs, is cured again. This selfhealing effect is highly desirable as far as the capacitors themselves are concerned, but is not without its disadvantages as far as the other cirucit components are concerned, especially the silicon rectifiers, the image tubes, and the components which conduct the image tube voltage.
It is therefore an important object of the invention to improve voltage multiplication cascades of the type described above.
It is a further object of the invention to keep the size of the entire assembly small and the internal resistance low.
It is a further object of the invention to increase pulse resistance of the entire circuit.
It is a further object of the invention to avoid the above-described disadvantageous effects on adjacent elements.
It is a further object of the invention to achieve multiples of the foregoing objects and preferably all of them consistent with each other.
SUMMARY OF THE INVENTION
In accordance with the invention, the foregoing objects are met by making at least one of the capacitors in the pumping circuit, preferably including the one which is adjacent to the input voltage source, one which is less prone to internal discharges than any of the individual capacitors in the storage circuit.
The Cockcroft-Walton cascade circuit is not provided with identical capacitors. Instead, the individual capacitors are arranged according to their loads and designed in such a way that a higher pulse resistance is attained only in certain capacitors. It can be shown that the load produced by the voltage in all the capacitors in the multiplication circuit is approximately the same. But the pulse currents of the capacitors as well as their forward flow angles are different. In particular, the capacitors of the pumping circuit are subjected to very high loads in a pulsed mode. In the voltage multiplication cascade according to the invention, these capacitors are arranged so that they exhibit fewer internal discharges than the capacitors in the storage circuit.
The external dimensions of the entire assembly would be unacceptably large if one constructed the entire switching arrangement using such capacitors.
The voltage multiplication cascade according to the invention also makes it possible to construct a reliably operating
arrangement which has no tendency toward spark-overs, consistent with satisfactory internal resistance of the voltage multiplication cascade and small dimensions of the entire assembly. This avoids the above cited disadvantages with respect to the particularly sensitive components in the rest of the circuit and makes it possible to design voltage multiplication cascades with silicon rectifiers, which are characterized by long lifetimes. Hence, a voltage multiplication cascade has been developed particularly for image tube circuits in television sets, especially color television sets, and this cascade satisfies the highest requirements in addition to having an average lifetime which in every case is greater than that of the television set.
A further aspect of the invention is that at least one of the capacitors that are less prone to internal discharges is a capacitor which is impregnated with a high-voltage impregnating substance, especially a high-voltage oil such as polybutene or silicone oil, or mixtures thereof. In contrast to capacitors made of metallized film which have not been impregnated, this allows the discharge frequency due to internal discharges or spark-overs to be reduced by a factor of 10 to 100.
According to a further important aspect of the invention, at least one of the capacitors that are less prone to internal discharges is either a foil capacitor or a self-healing capacitor. In addition, the capacitor in the pumping circuit which is adjacent to the voltage source input can be a foil capacitor which has been impregnated in the manner described above, while the next capacitor in the pumping circuit is a self-healing capacitor impregnated in the same fashion.
Other objects, features and advantages of the invention will be apparent from the following detailed description of preferred embodiments, taken in connection with the accompanying drawing, the single FIGURE of which:
BRIEF DESCRIPTION OF THE DRAWING
is a schematic diagram of a circuit made according to a preferred embodiment of the invention.
DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS
The voltage multiplier comprises capacitors C1 to C5 and rectifiers D1 to D5 connected in a cascade. An alternating voltage source UE is connected to terminals 1 and 2, said voltage source supplying for example a pulsed alternating voltage. Capacitors C1 and C2 form the pumping circuit while capacitors C3, C4 and C5 form the storage circuit.
In the steady state, capacitor C1 is charged to the maximum value of the alternating voltage UE as are the other capacitors C2 to C5. The desired high D.C. voltage UA is picked off at terminals 3 and 4, said D.C. voltage being composed of the D.C. voltages from capacitors C3 to C5. Terminal 3 and terminal 2 are connected to one pole of the alternating voltage source UE feeding the circuit, which can be at ground potential. In the circuit described here, a D.C. voltage UA can be picked off whose voltage value is approximately 3 times the maximum value of the pulsed alternating voltage UE. By using more than five capacitors, a correspondingly higher D.C. voltage can be obtained.
The individual capacitors are discharged by disconnecting D.C. voltage UA. However, they are constantly being recharged by the electrical energy supplied by the alternating voltage source UE, so that the voltage multiplier can be continuously charged on the output side.
According to the invention, in this preferred embodiment, capacitor C1 and/or C2 in the pumping circuit are designed so that they have a lower tendency toward internal discharges than any of the individual capacitors C3, C4 and C5 in the storage circuit.
It is evident that those skilled in the art, once given the benefit of the foregoing disclosure, may now make numerous other uses and modifications of, and departures from the specific embodiments described herein without departing from the inventive concepts. Consequently, the invention is to be construed as embracing each and every novel feature and novel combination of features present in, or possessed by, the apparatus and techniques herein disclosed and limited solely by the scope and spirit of the appended claims.
Inventors:Petrick, Paul (Landshut, DT)
Schwedler, Hans-peter (Landshut, DT)
Holzer, Alfred (Schonbrunn, DT)
ERNST ROEDERSTEIN SPEZIALFABRIK
US Patent References:
3714528 ELECTRICAL CAPACITOR WITH FILM-PAPER DIELECTRIC 1973-01-30 Vail
3699410 SELF-HEALING ELECTRICAL CONDENSER 1972-10-17 Maylandt
3463992 ELECTRICAL CAPACITOR SYSTEMS HAVING LONG-TERM STORAGE CHARACTERISTICS 1969-08-26 Solberg
3457478 WOUND FILM CAPACITORS 1969-07-22 Lehrer
3363156 Capacitor with a polyolefin dielectric 1968-01-09 Cox
2213199 Voltage multiplier 1940-09-03 Bouwers et al.
KORTING MARATHON VTS FFS 22" 41531 CHASSIS G-030AD1 Channel selector having a plurality of tuning systems:
A channel selector characterized in that a plurality of receivers capable of simultaneously performing a receiving operation have a main part of a phase-locked loop frequency synthesizer connected in common thereto, the frequency synthesizer having a programmable frequency divider, a phase comparator, a reference oscillator and a reference frequency divider. The frequency synthesizer is controlled so that a local oscillation frequency corresponding to a determined frequency close to a broadcast signal of a desired receiving channel is synthesized, and one of a plurality of search tuning systems searches and tunes the broadcast signal from the local oscillation frequency.
1. A channel selector for controlling the tuning frequency of a plurality of receivers capable of simultaneously performing receiving operations, each of said plurality of receivers having a portion of a phase-locked loop frequency synthesizer; wherein another portion of a phase-locked loop frequency synthesizer is commonly used by said portions of said synthesizers whereby each of said plurality of receivers has an equivalent complete phase-locked loop frequency synthesizer;
and wherein each of said plurality of receivers has its own low pass filter included in its equivalent phase-locked loop frequency synthesizer, and an output of a phase comparator is switched to an input terminal of one low pass filter from among said plurality of low pass filters by a 3-state switching circuit.
2. A channel selector according to claim 1, wherein said common portion of each of said equivalent phase-locked loop frequency synthesizers comprises a programmable frequency divider, a phase comparator, a reference oscillator and a reference frequency divider.
3. A channel selector according to claim 1, wherein said common portion of each of said equivalent phase-locked loop frequency synthesizers comprises a prescaler.
4. A channel selector according to claim 1, wherein said common portion of each of said equivalent phase-locked loop frequency synthesizers comprises a channel entry means and a code converter means.
5. A channel selector for controlling the tuning frequency of a plurality of receivers capable of simultaneously performing rec
eiving operations, each of said plurality of receivers having a portion of a phase-locked loop frequency synthesizer; wherein another portion of a phase-locked loop frequency synthesizer is commonly used by said portions of said synthesizers whereby each of said plurality of receivers has an equivalent complete phase-locked loop frequency synthesizer;
and wherein each of said equivalent phase-locked loop frequency synthesizers is controlled so that a local oscillation frequency corresponding to a predetermined frequency close to a broadcast signal of a desired receiving channel is synthesized, and one of a plurality of search tuning systems searches and tunes said broadcast signal from said local oscillation frequency whereby said broadcast signal of said desired receiving channel is tuned.
6. A channel selector for controlling the tuning frequency of a plurality of receivers capable of simultaneously performing receiving operations, each of said plurality of receivers having a portion of a phase-locked loop frequency synthesizer; wherein another portion of a phase-locked loop frequency synthesizer is commonly used by said portions of said synthesizers whereby each of said plurality of receivers has an equivalent complete phase-locked loop frequency synthesizer;
and wherein each of said phase-locked loop frequency synthesizers selects a desired receiving channel, and wherein a tuning voltage of said desired receiving channel is stored in a voltage memory means, and wherein said channel selector further comprises a tuning means provided for each of said plurality of receivers so that while receiving, said tuning means tunes in accordance with the output of said voltage memory means.
7. A channel selector according to claims 5 or 6, wherein said common portion of each of said equivalent phase-locked loop frequency synthesizers comprises a programmable frequency divider, a phase comparator, a reference oscillator and a reference frequency divider.
8. A channel selector according to claims 5 or 6, wherein said common portion of each of said equivalent phase-locked loop frequency synthesizers comprises a prescaler.
9. A channel selector according to claims 5 or 6, wherein said common portion of each of said equivalent phase-locked loop frequency synthesizers comprises a channel entry means and a code converter means.
This invention relates to a channel selector for use in television receivers, FM (frequency modulation) radio receivers, AM (amplitude modulation) radio receivers and so on.
TDA2576 SYNC COMBINATION WITH TRANSMITTER IDENTIFICATION
AND VERTICAL 625 DIVIDER SYSTEM
GENERAL DESCRIPTION
The TDA2576 B is a monolithic integrated circuit for use in colour television receivers with switched-
mode driven or self-regulating horizontal time-base circuits. It is designed in combination with the
TDA2581 to operate as a matched pair. When supplied with a composite video signal the TDA2576 B
delivers drive pulses for the TDA2581 and sync pulses for the vertical deflection. The circuit is
optimized for a horizontal and vertical frequency ratio of 625. It incorporates the following features:
Features
O Horizontal sync separator (including noise inverter) I
O Horizontal phase detector
0 Horizontal oscillator (31,25 kHz)
0 Sandcastle pulse generator
O Vertical sync pulse separator
O Very stable automatic vertical synchronization due to the 625 divider system, without delay after
channel change
I Three voltage level sensor on coincidence detector circuit output
I Video transmitter identification circuit for sound muting and search tuning systems
O Inhibit of vertical sync pulse when no video transmitter is detected
QUICK REFERENCE DATA
Supply voltage _
horizontal (pin 14) V14_13 typ. 12 V
vertical (pin 18) V13_13 typ. 12 V
Supply current (pin 14 + pin 18) V14+18 typ. 52 mA
Sync separator
input voltage level (peak-to-peak value) V2.131p.p) 0,07 to I V
slicing level typ. 50 % _
Output pulse E
horizontal (peak-to-peak value) V3_131p_p1 min. 10 V =
vertical sync (peak-to-peak value) V1_131p_p1 min. 10 V —
burst key (peak-to~peak value) V15_131p_p1 min. 10 V
Video transmitter identification circuit
Output voltage (pin 10)
sync pulse present V10_13 typ. 8 V
no sync pulse V1Q_13 max. 1 V
Phase locked loop
control sensitivity typ. 2000 Hz/;1s
holding range Af typ. 1 1000 Hz
catching range Af typ. : 900 Hz
Operating ambient temperature range Tamb -25 to + 65 °C
PACKAGE OUTLINE
18-lead DIL; plastic (SOT-102A).
FUNCTIONAL DESCRIPTION
The video input voltage to drive the sync separator must have negative-going sync, which can be
obtained from synchronous demodulators such as TDA2540, TDA2541 and TDA2670.
The slicing level of the sync separator is determined by the value of the resistor between pins 3 and 4.
A 5,6 kfl resistor provides a slicing level midway between the top sync level and the blanking level.
Thus the slicing level is independent of the amplitude of the sync pulse input at pin 2.
The nominal top sync level at pin 2 is 1,5 V, and the amplitude selective noise inverter is activated at
0,7 V. The horizontal phase detector has a steepness of 1,2 V/its and together with the 1800 Hz/V of
the horizontal oscillator provides a total control steepness of 2000 Hz/us.
A second horizontal phase detector provides a 5,5 its pulse which ensures symmetrical gating of the
horizontal synchronization. During catching the gating is automatically switched off. At the same time
the flywheel filter is switched to a short time constant. The value of this time constant can be deter~
mined externally via pin 11.
When the indirect vertical sync output is generated by the 625 divider system an anti-top flutter pulse
switches off the equalizing and vertical sync pulse operation of the phase detector. Thus top flutter
distortion of the control voltage due to vertical pulses can be anticipated. When the 625 divider system
is in the direct mode the anti~top flutter pulse is inhibited.
The free running output frequency of the horizontal oscillator is 31,25 kl-lz. The vertical frequency
output is obtained by dividing this double horizontal frequency by 625. The double horizontal
frequency is fed via a binary divider to provide the normal 15,625 kHz horizontal output at pin 8. The
trailing edge of this pulse is positioned 0,9 us after the end of the video sync pulse input at pin 2
(see Fig. 2).
The automatic vertical sync block contains the following:
0 625 divider
0 In/out-sync detector
I Direct/indirect sync switch
O Identification circuit
It is fed by a signal obtained by integration of the composite sync signal and an internally generated,
clipped video signal. The vertical sync pulse is sliced out of this integrated signal by an automatically
biased clipper. The videopart of the signal helps to build up a vertical sync pulse when heavy negative-
going reflections (mountains) distort the video signal. The in/out sync-detector considers a signal
out~of-sync when fifteen or more successive incoming vertical sync pulses are not in phase with a
reference signal from the 625 divider. Therefore a distorted vertical sync signal needs only one
out-of-fifteen pulses to be in phase to keep the system in sync. When the sixteenth successive out-of-
sync pulse is detected, the direct/indirect sync switch is activated to feed the vertical sync signal
directly out of the block at pin 2 (direct sync vertical output).
At the same time the 625 divider is reset by one of the sync pulses. After the reset pulse, if the 7th
sliced vertical sync pulse coincides with a 625 divider window, the sync output pulse is presented
again by the divider system and switch-over to indirect mode occurs.
In the direct mode, every 7th non-coinciding sliced vertical sync pulse will reset the counter. Thus a
non-standard video signal will result in continuous reset pulses and the direct/indirect switch will
remain in the direct position.
To avoid delay in vertical synchronization, caused by waiting time of the divider circuit after channel
change or an unsynchronized camera change in the studio, information is fed from the horizontal coin-
cidence detector to the automatic switch for the vertical sync pulse. The loss of horizontal synchroni-
zation sets the automatic switch to direct vertical sync. When horizontal coincidence is detected again
the setting of the automatic switch depends on whether a standard video signal is received or not. When
an external voltage between 2,5 V and 7,25 V is applied via pin 12 to the coincidence detector, the hor-
izontal phase detector is swsync. A voltage level on pin 12 > 8,25 V switches the horizontal phase detector to a short time constant,
without affecting the indirect/direct vertical sync system which remains operational.
The video transmitter identification circuit detects when a sync pulse occurs during the internal gating
pulse. This indicates the presence of a video transmitter and results in the capacitor connected to pin
10 being charged to 8 V. When no sync pulse is present the capacitor discharges to < 1 V. The voltage
at pin 10 is compared with an internal d.c. voltage. The identification output at pin 9 is active when
pin 10 is < 1,6 V (no video transmitter) and inactive (high impedance) when pin 10 is > 3,5 V.
The vertical sync output pulse at pin 1 is inhibited when no video transmitter is identified, which
prevents interference or noise affecting the frequency of the vertical output stage. This results in a vertical stable picture, plus vertical stable position information of tuning systems.
TDA2541 IF AMPLIFIER WITH DEMODULATOR AND AFC
DESCRIPTION
The TDA2540 and 2541 are IF amplifier and A.M.
demodulator circuits for colour and black and white
television receivers using PNP or NPN tuners. They
are intended for reception of negative or positive
modulation CCIR standard.
They incorporate the following functions : .Gain controlled amplifier .Synchronous demodulator .White spot inverter .Video preamplifier with noise protection .Switchable AFC .AGC with noise gating .Tuner AGC output (NPN tuner for 2540)-(PNP
tuner for 2541) .VCR switch for video output inhibition (VCR
play back).
.SUPPLYVOLTAGE : 12V TYP
.SUPPLYCURRENT : 50mATYP
.I.F. INPUT VOLTAGE SENSITIVITY AT
F = 38.9MHz : 85mVRMS TYP
.VIDEO OUTPUT VOLTAGE (white at 10% of
top synchro) : 2.7VPP TYP
.I.F. VOLTAGE GAIN CONTROL RANGE :
64dB TYP .SIGNAL TO NOISE RATIO AT VI = 10mV :
58dB TYP
.A.F.C. OUTPUT VOLTAGE SWING FOR
Df = 100kHz : 10V TYP
KORTING MARATHON VTS FFS 22" 41531 CHASSIS G-030AD1 TDA1170 vertical deflection FRAME DEFLECTION INTEGRATED CIRCUIT
GENERAL DESCRIPTION f The TDA1170 and TDA1270 are monolithic integrated
circuits designed for use in TV vertical deflection systems. They are manufactured using
the Fairchild Planar* process.
Both devices are supplied in the 12-pin plastic power package with the heat sink fins bent
for insertion into the printed circuit board.
The TDA1170 is designed primarily for large and small screen black and white TV
receivers and industrial TV monitors. The TDA1270 is designed primarily for driving
complementary vertical deflection output stages in color TV receivers and industrial
monitors.
APPLICATION INFORMATION (TDA1170)
The vertical oscillator is directly synchronized by the sync pulses (positive or negative); therefore its free
running frequency must be lower than the sync frequency. The use of current feedback causes the yoke
current to be independent of yoke resistance variations due to thermal effects, Therefore no thermistor is
required in series with the yoke. The flyback generator applies a voltage, about twice the supply voltage, to
the yoke. This produces a short flyback time together with a high useful power to dissipated power
ratio.
1. A transformerless output vertical deflection circuit, comprising a vertical oscillator circuit for generating a vertical pulse train in response to vertical synchronizing pulses applied thereto, a sawtooth signal generator for generating a series of sawtooth signals, each cycle of said sawtooth signal including a pulse component, a vertical output circuit coupled to said sawtooth generator for amplifying said sawtooth signal including said pulse component and loading a vertical deflection coil, and stabilizing means connected between said vertical oscillator and said sawtooth signal generator for varying the width of the pulse component which is to be fed to said vertical output circuit in response to the average level of DC output voltage fed from the vertical output circuit. 2. A transformerless output vertical deflection circuit claimed in claim 1, wherein said stabilizing means comprises a control circuit means for receiving a series of pulses from the vertical oscillator and a feedback signal from the vertical output circuit and for varying the width of the pulse which is to be fed to the vertical output circuit in response to a DC control signal proportional to the width of the pulse component included in the vertical output signal and smoothing circuit means connected between said vertical output circuit and said stabalizing means for smoothing said feedback signal. 3. A transformerless output vertical deflection circuit claimed in claim 2, wherein said control circuit comprises a charging capacitor which is parallel to a transistor, said transistor being switched on in response to pulses fed from the vertical oscillator wherein said capacitor is charged by the voltage fed from said smoothing circuit, and discharged in response to conduction of the transistor, a differential amplifier circuit which receives the voltage on said capacitor and a fixed voltage, and a gating circuit for producing a pulse which has a width equal to the difference between the width of the pulse fed from the vertical oscillator circuit and the width of pulse fed from the differential amplifier circuit. 4. A transformerless output vertical deflection circuit claimed in claim 2, wherein said control circuit comprises a capacitor which is charged by a fixed power source and is discharged by means of a switching transistor operated by the pulses fed from the vertical oscillator circuit and a differential amplifier circuit receiving the voltage on the capacitor and the output of said smoothing circuit. 5. A transformable output vertical deflection circuit comprising a vertical oscillator for generating a vertical pulse train in response to vertical synchronizing pulses applied thereto, a sawtooth signal generator for generating a series of sawtooth signals each cycle of said sawtooth signal including a pulse component, a vertical output circuit for amplifying said sawtooth signal including said pulse component and loading a vertical deflection coil, and pulse stabilizing means coupled between the vertical oscillator circuit a
nd the sawtooth signal generator, said stabilizing means comprising a capacitor which is charged by a fixed power source and discharged by means of a discharging means operated in response to the vertical pulse fed from the vertical oscillator, a circuit means for generating a train of output pulses each starting at the time when the voltage appearing on the capacitor exceeds a predetermined value and terminating in synchronism with termination of the pulse fed from the vertical oscillator, and gating means for generating pulses having a width equal to the difference between the width of the pulse fed from the vertical oscillator and the width of the output pulse of the circuit means. 6. A transformerless output vertical deflection circuit, comprising a vertical oscillator circuit for generating a vertical pulse train in response to vertical synchronizing pulses applied thereto, a sawtooth signal generator for generating a series of sawtooth signals, each cycle of said sawtooth signal including a pulse component, a vertical output circuit coupled to said sawtooth generator for amplifying said sawtooth signal including said pulse component and loading a vertical deflection coil, and stabilizing means, comprising a control circuit connected between said vertical output circuit and said vertical oscillator circuit for varying the width of each pulse produced by the vertical oscillator circuit in response to a DC control signal having a value corresponding to the width of the pulse component applied to the vertical deflection coil of the vertical output circuit for controlling the pulse width of the output of said vertical oscillator circuit and thereby the pulse width of said pulse component.
TDA2530 RGB MATRIX PREAMPLIFIER
The TDA2530 is an integrated RGB -matrix preamplifier for colour television receivers,
incorporating a matrix preamplifier for RGB cathode drive of the picture tube with
clamping circuits. The three channels have the same layout to ensure identical frequency
behaviour.
This integrated circuit has been designed to be driven from the TDA2522 Synchronous
demodulator and oscillator IC.
TDA2522 PAL TV CHROMA DEMODULATOR COMBINATION
FAIRCHILD LINEAR INTEGRATED CIRCUIT
GENERAL DESCRIPTION- The TDA2522 is a monolithic integrated circuit designed as
a synchronous demodulator for PAL color television receivers. It includes an 8,8 MHz
oscillator and divider to generate two 4.4 MHz reference signals and provides color difference outputs.
PACKAGE OUTLINE 9B
The TDA2522 is Intended to Interface directly with the TDA2560 with a minimum oF external components. The TDA2530 may be added if RGB drive is required. The TDA2522
is constructed using the Fairchild Planar* process.
TDA2560 LUMINANCE AND CHROMINANCE CONTROL COMBINATION
The TDA2560 is a monolithic integrated circuit for use in decoding systems of COLOR
television receivers. The circuit consists of a luminance and chrominance amplifier.
The luminance amplifier has a low input impedance so that matching of the luminance
delay line is very easy.
It also incorporates the following functions:
- d.c. contrast control;
- d.c. brightness control;
- black level clamp;
- blanking;
- additional video output with positive-going sync.
The chrominance amplifier comprises:
- gain controlled amplifier;
- chrominance gain control tracked with contrast control;
- separate d.c. saturation control:
- combined chroma and burst output, burst signal amplitude not affected by contrast and
saturation control;
- the delay line can be driven directly ‘by the IC.
APPLICATION INFORMATION (continued)
The function is quoted against the corresponding pin number
Balanced chrominance input signal (in conjunction with pin 2)
This is derived from the chrominance signal bandpass filter, designed to provide a
push-pull input. A signal amplitude of at least 4 mV peak-to-peak is required
between pins l and 2. The chrominance amplifier is stabilized by an external feedback
loop from the output (pin 6) to the input (pins I and 2). The required level at pins l
and 2 will be 3 V.
All figures for the chrominance signals are based on a colour bar signal with 75%
saturation: i.e. burst-to-chrominance ratio of input signal is 1 1 2.
Chrominance signal input (see pin 1)
A. C.C. input
A negative-going potential, starting at +l,2 V, gives a 40 dB range of a. c. c.
Maximum gain reduction is achieved at an input voltage of 500 mV.
Chrominance saturation control
A control range of +6 dB to >-14 dB is provided over a range of d. c. potential on
pin 4 from +2 to +4 V. The saturation control is a linear function of the control
voltage.
Negative supply (earth)
Chro minance signal output
For nominal settings of saturation and contrast controls (max. -6 dB for saturation,
and max. -3 dB for contrast) both the chroma' and burst are available at this pin, and
in the same ratio as at the input pins 1 and 2. The burst signal is not affected by the
saturation and contrast controls. The a.c. c. circuit of the TDA2522 will hold
constant the colour burst amplitude at the input of the TDA2522. As the PAL delay
line is situated here between the TDA256O and TDA2522 there may be some variation
of the nominal 1 V peak-to-peak burst output of the TDA2560, according to the
tolerances of the delay line. An external network is required from pin 6 of the
TDA256O to provide d. c. negative feedback in the chroma channel via pins I and 2.
Burst gating and clamping pulse input
A two-level pulse is required at this pin to be used for burst gate and black level
clamping. The black level clamp is activated when the pulse level is greater than
7 V. The timing of this interval should be such that no appreciable encroachment
occurs into the sync pulse on picture line periods during normal operation of the
receiver. The burst gate, which switches the gain of the chroma amplifier to
maximum, requires that the input pulse at pin 7 should be sufficiently wide, at least
8 ps, at the actuating level of 2,3 V.
+12 V power supply
Correct operation occurs within the range 10 to 14 V. All signal and control levels
have a linear dependency on supply voltage but, in any given receiver design, this
range may be restricted due to considerations of tracking between the power supply
variations and picture contrast and chroma levels.
Flyback blanking input waveform
This pin is used for blanking the luminance amplifier. When the input pulse exceeds
the +2, 5 Vlevel, the output signal is blanked to a level of about 0 V. When the input
exceeds a +6 V level, a fixed level of about 1, 5 V is inserted in the output. This
level can be used for clamping purposes.
Luminance sigal output
An emitter follower provides a low impedance output signal of 3 V black-to-white
amplitude at nominal contrast setting having a black level in the range 1 to 3 V. An
external emitter load resistor is not required.
The luminance amplitude available for nominal contrast may be modified according
to the resistor value from pin 13 to the +12 V supply. At an input bias current
114 of 0,25 mA during black level the amplifier is compensated so that no black
level shift more than 10 mV occurs at contrast control. When the input current
deviates from the quoted value the black level shift amounts to 100 mV/rnA.
Brightness control
The black level at the luminance output (pin 10) is identical to the control voltage
required at this pin, A range of black level from l to 3 V may be obtained.
Black level clamp capacitor
Luminance gain setting resistor
The gain of the luminance amplifier may be adjusted by selection of the resistor
value from pin 13 to +12 V. Nominal luminance output amplitude is then 3 V
black-to-white at pin 10 when this resistor is 2, 7.
TDA1082
East-West correction driver circuit
East-West correction driver circuit TDA1082:
GENERAL DESCRIPTION
The TDA1082 is a monolithic integrated circuit driving east-west correction of colour tubes in television receivers.
The circuit can be used for class-A and class-D operation and incorporates the following functions:
· differential input amplifier
· squaring stage
· differential output amplifier with driver stage
· protection stage with threshold
· switching off the correction during flyback
· voltage stabilizer
QUICK REFERENCE DATA
PACKAGE OUTLINE
16-lead DIL; plastic (SOT38); SOT38-1;
Supply voltage (pin 1) VP typ. 12 V
Current consumption IP typ. 17 mA
Total power dissipation Ptot max. 600 mW
Operating ambient temperature range Tamb 0 to + 70 °C
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -- - - - - - - - - - - - - - - - - - - - - - - - - - - - -
MAB8021
DESCRIPTION
The MAB8021 is a single-chip 8-bit microcomputer that is fabricated using the N-MOS silicon gate
process It contains a 1K ><: 8 program memory, a 64 x 8 data memory, 21 I/O lines, and an 8-bit
timer/event counter, in addition to on-board oscillator and clock circuits.
For systems that require
extra I/O capacity, the MAB8021 can be expanded using the 8243 or discrete logic.
This microcomputer is designed to bean efficient controller as well as an arithmetic computer. The
MAB802l has bit handling capability as well as facilities for both binary and BCD arithmetic. Efficient
use of program memory results from aw instruction set (see Table 4) consisting mostly of single byte
instructions and no instructions; over two bytes in length.
FEATURES
8~bit CPU, ROM, RAM,I/O in a single 28-lead package
1K x 8 ROM, 64 x 8 RAM,
Internal timer/event counter
Clock generated with single inductor or crystal
Single 5 V supply (range: + 4,5 V to + 6,5 V)
38 us cycle time; all instructions 1 or 2 cycles
lnstructions: MAB8048 subset
Zero-cross detection capability.
and wherein each of said plurality of receivers has its own low pass filter included in its equivalent phase-locked loop frequency synthesizer, and an output of a phase comparator is switched to an input terminal of one low pass filter from among said plurality of low pass filters by a 3-state switching circuit.
2. A channel selector according to claim 1, wherein said common portion of each of said equivalent phase-locked loop frequency synthesizers comprises a programmable frequency divider, a phase comparator, a reference oscillator and a reference frequency divider.
3. A channel selector according to claim 1, wherein said common portion of each of said equivalent phase-locked loop frequency synthesizers comprises a prescaler.
4. A channel selector according to claim 1, wherein said common portion of each of said equivalent phase-locked loop frequency synthesizers comprises a channel entry means and a code converter means.
5. A channel selector for controlling the tuning frequency of a plurality of receivers capable of simultaneously performing rec
eiving operations, each of said plurality of receivers having a portion of a phase-locked loop frequency synthesizer; wherein another portion of a phase-locked loop frequency synthesizer is commonly used by said portions of said synthesizers whereby each of said plurality of receivers has an equivalent complete phase-locked loop frequency synthesizer;
and wherein each of said equivalent phase-locked loop frequency synthesizers is controlled so that a local oscillation frequency corresponding to a predetermined frequency close to a broadcast signal of a desired receiving channel is synthesized, and one of a plurality of search tuning systems searches and tunes said broadcast signal from said local oscillation frequency whereby said broadcast signal of said desired receiving channel is tuned.
6. A channel selector for controlling the tuning frequency of a plurality of receivers capable of simultaneously performing receiving operations, each of said plurality of receivers having a portion of a phase-locked loop frequency synthesizer; wherein another portion of a phase-locked loop frequency synthesizer is commonly used by said portions of said synthesizers whereby each of said plurality of receivers has an equivalent complete phase-locked loop frequency synthesizer;
and wherein each of said phase-locked loop frequency synthesizers selects a desired receiving channel, and wherein a tuning voltage of said desired receiving channel is stored in a voltage memory means, and wherein said channel selector further comprises a tuning means provided for each of said plurality of receivers so that while receiving, said tuning means tunes in accordance with the output of said voltage memory means.
7. A channel selector according to claims 5 or 6, wherein said common portion of each of said equivalent phase-locked loop frequency synthesizers comprises a programmable frequency divider, a phase comparator, a reference oscillator and a reference frequency divider.
8. A channel selector according to claims 5 or 6, wherein said common portion of each of said equivalent phase-locked loop frequency synthesizers comprises a prescaler.
9. A channel selector according to claims 5 or 6, wherein said common portion of each of said equivalent phase-locked loop frequency synthesizers comprises a channel entry means and a code converter means.
Description:
BACKGROUND OF THE INVENTIONThis invention relates to a channel selector for use in television receivers, FM (frequency modulation) radio receivers, AM (amplitude modulation) radio receivers and so on.
TDA2576 SYNC COMBINATION WITH TRANSMITTER IDENTIFICATION
AND VERTICAL 625 DIVIDER SYSTEM
GENERAL DESCRIPTION
The TDA2576 B is a monolithic integrated circuit for use in colour television receivers with switched-
mode driven or self-regulating horizontal time-base circuits. It is designed in combination with the
TDA2581 to operate as a matched pair. When supplied with a composite video signal the TDA2576 B
delivers drive pulses for the TDA2581 and sync pulses for the vertical deflection. The circuit is
optimized for a horizontal and vertical frequency ratio of 625. It incorporates the following features:
Features
O Horizontal sync separator (including noise inverter) I
O Horizontal phase detector
0 Horizontal oscillator (31,25 kHz)
0 Sandcastle pulse generator
O Vertical sync pulse separator
O Very stable automatic vertical synchronization due to the 625 divider system, without delay after
channel change
I Three voltage level sensor on coincidence detector circuit output
I Video transmitter identification circuit for sound muting and search tuning systems
O Inhibit of vertical sync pulse when no video transmitter is detected
QUICK REFERENCE DATA
Supply voltage _
horizontal (pin 14) V14_13 typ. 12 V
vertical (pin 18) V13_13 typ. 12 V
Supply current (pin 14 + pin 18) V14+18 typ. 52 mA
Sync separator
input voltage level (peak-to-peak value) V2.131p.p) 0,07 to I V
slicing level typ. 50 % _
Output pulse E
horizontal (peak-to-peak value) V3_131p_p1 min. 10 V =
vertical sync (peak-to-peak value) V1_131p_p1 min. 10 V —
burst key (peak-to~peak value) V15_131p_p1 min. 10 V
Video transmitter identification circuit
Output voltage (pin 10)
sync pulse present V10_13 typ. 8 V
no sync pulse V1Q_13 max. 1 V
Phase locked loop
control sensitivity typ. 2000 Hz/;1s
holding range Af typ. 1 1000 Hz
catching range Af typ. : 900 Hz
Operating ambient temperature range Tamb -25 to + 65 °C
PACKAGE OUTLINE
18-lead DIL; plastic (SOT-102A).
FUNCTIONAL DESCRIPTION
The video input voltage to drive the sync separator must have negative-going sync, which can be
obtained from synchronous demodulators such as TDA2540, TDA2541 and TDA2670.
The slicing level of the sync separator is determined by the value of the resistor between pins 3 and 4.
A 5,6 kfl resistor provides a slicing level midway between the top sync level and the blanking level.
Thus the slicing level is independent of the amplitude of the sync pulse input at pin 2.
The nominal top sync level at pin 2 is 1,5 V, and the amplitude selective noise inverter is activated at
0,7 V. The horizontal phase detector has a steepness of 1,2 V/its and together with the 1800 Hz/V of
the horizontal oscillator provides a total control steepness of 2000 Hz/us.
A second horizontal phase detector provides a 5,5 its pulse which ensures symmetrical gating of the
horizontal synchronization. During catching the gating is automatically switched off. At the same time
the flywheel filter is switched to a short time constant. The value of this time constant can be deter~
mined externally via pin 11.
When the indirect vertical sync output is generated by the 625 divider system an anti-top flutter pulse
switches off the equalizing and vertical sync pulse operation of the phase detector. Thus top flutter
distortion of the control voltage due to vertical pulses can be anticipated. When the 625 divider system
is in the direct mode the anti~top flutter pulse is inhibited.
The free running output frequency of the horizontal oscillator is 31,25 kl-lz. The vertical frequency
output is obtained by dividing this double horizontal frequency by 625. The double horizontal
frequency is fed via a binary divider to provide the normal 15,625 kHz horizontal output at pin 8. The
trailing edge of this pulse is positioned 0,9 us after the end of the video sync pulse input at pin 2
(see Fig. 2).
The automatic vertical sync block contains the following:
0 625 divider
0 In/out-sync detector
I Direct/indirect sync switch
O Identification circuit
It is fed by a signal obtained by integration of the composite sync signal and an internally generated,
clipped video signal. The vertical sync pulse is sliced out of this integrated signal by an automatically
biased clipper. The videopart of the signal helps to build up a vertical sync pulse when heavy negative-
going reflections (mountains) distort the video signal. The in/out sync-detector considers a signal
out~of-sync when fifteen or more successive incoming vertical sync pulses are not in phase with a
reference signal from the 625 divider. Therefore a distorted vertical sync signal needs only one
out-of-fifteen pulses to be in phase to keep the system in sync. When the sixteenth successive out-of-
sync pulse is detected, the direct/indirect sync switch is activated to feed the vertical sync signal
directly out of the block at pin 2 (direct sync vertical output).
At the same time the 625 divider is reset by one of the sync pulses. After the reset pulse, if the 7th
sliced vertical sync pulse coincides with a 625 divider window, the sync output pulse is presented
again by the divider system and switch-over to indirect mode occurs.
In the direct mode, every 7th non-coinciding sliced vertical sync pulse will reset the counter. Thus a
non-standard video signal will result in continuous reset pulses and the direct/indirect switch will
remain in the direct position.
To avoid delay in vertical synchronization, caused by waiting time of the divider circuit after channel
change or an unsynchronized camera change in the studio, information is fed from the horizontal coin-
cidence detector to the automatic switch for the vertical sync pulse. The loss of horizontal synchroni-
zation sets the automatic switch to direct vertical sync. When horizontal coincidence is detected again
the setting of the automatic switch depends on whether a standard video signal is received or not. When
an external voltage between 2,5 V and 7,25 V is applied via pin 12 to the coincidence detector, the hor-
izontal phase detector is swsync. A voltage level on pin 12 > 8,25 V switches the horizontal phase detector to a short time constant,
without affecting the indirect/direct vertical sync system which remains operational.
The video transmitter identification circuit detects when a sync pulse occurs during the internal gating
pulse. This indicates the presence of a video transmitter and results in the capacitor connected to pin
10 being charged to 8 V. When no sync pulse is present the capacitor discharges to < 1 V. The voltage
at pin 10 is compared with an internal d.c. voltage. The identification output at pin 9 is active when
pin 10 is < 1,6 V (no video transmitter) and inactive (high impedance) when pin 10 is > 3,5 V.
The vertical sync output pulse at pin 1 is inhibited when no video transmitter is identified, which
prevents interference or noise affecting the frequency of the vertical output stage. This results in a vertical stable picture, plus vertical stable position information of tuning systems.
TDA2541 IF AMPLIFIER WITH DEMODULATOR AND AFC
DESCRIPTION
The TDA2540 and 2541 are IF amplifier and A.M.
demodulator circuits for colour and black and white
television receivers using PNP or NPN tuners. They
are intended for reception of negative or positive
modulation CCIR standard.
They incorporate the following functions : .Gain controlled amplifier .Synchronous demodulator .White spot inverter .Video preamplifier with noise protection .Switchable AFC .AGC with noise gating .Tuner AGC output (NPN tuner for 2540)-(PNP
tuner for 2541) .VCR switch for video output inhibition (VCR
play back).
.SUPPLYVOLTAGE : 12V TYP
.SUPPLYCURRENT : 50mATYP
.I.F. INPUT VOLTAGE SENSITIVITY AT
F = 38.9MHz : 85mVRMS TYP
.VIDEO OUTPUT VOLTAGE (white at 10% of
top synchro) : 2.7VPP TYP
.I.F. VOLTAGE GAIN CONTROL RANGE :
64dB TYP .SIGNAL TO NOISE RATIO AT VI = 10mV :
58dB TYP
.A.F.C. OUTPUT VOLTAGE SWING FOR
Df = 100kHz : 10V TYP
KORTING MARATHON VTS FFS 22" 41531 CHASSIS G-030AD1 TDA1170 vertical deflection FRAME DEFLECTION INTEGRATED CIRCUIT
GENERAL DESCRIPTION f The TDA1170 and TDA1270 are monolithic integrated
circuits designed for use in TV vertical deflection systems. They are manufactured using
the Fairchild Planar* process.
Both devices are supplied in the 12-pin plastic power package with the heat sink fins bent
for insertion into the printed circuit board.
The TDA1170 is designed primarily for large and small screen black and white TV
receivers and industrial TV monitors. The TDA1270 is designed primarily for driving
complementary vertical deflection output stages in color TV receivers and industrial
monitors.
APPLICATION INFORMATION (TDA1170)
The vertical oscillator is directly synchronized by the sync pulses (positive or negative); therefore its free
running frequency must be lower than the sync frequency. The use of current feedback causes the yoke
current to be independent of yoke resistance variations due to thermal effects, Therefore no thermistor is
required in series with the yoke. The flyback generator applies a voltage, about twice the supply voltage, to
the yoke. This produces a short flyback time together with a high useful power to dissipated power
ratio.
1. A transformerless output vertical deflection circuit, comprising a vertical oscillator circuit for generating a vertical pulse train in response to vertical synchronizing pulses applied thereto, a sawtooth signal generator for generating a series of sawtooth signals, each cycle of said sawtooth signal including a pulse component, a vertical output circuit coupled to said sawtooth generator for amplifying said sawtooth signal including said pulse component and loading a vertical deflection coil, and stabilizing means connected between said vertical oscillator and said sawtooth signal generator for varying the width of the pulse component which is to be fed to said vertical output circuit in response to the average level of DC output voltage fed from the vertical output circuit. 2. A transformerless output vertical deflection circuit claimed in claim 1, wherein said stabilizing means comprises a control circuit means for receiving a series of pulses from the vertical oscillator and a feedback signal from the vertical output circuit and for varying the width of the pulse which is to be fed to the vertical output circuit in response to a DC control signal proportional to the width of the pulse component included in the vertical output signal and smoothing circuit means connected between said vertical output circuit and said stabalizing means for smoothing said feedback signal. 3. A transformerless output vertical deflection circuit claimed in claim 2, wherein said control circuit comprises a charging capacitor which is parallel to a transistor, said transistor being switched on in response to pulses fed from the vertical oscillator wherein said capacitor is charged by the voltage fed from said smoothing circuit, and discharged in response to conduction of the transistor, a differential amplifier circuit which receives the voltage on said capacitor and a fixed voltage, and a gating circuit for producing a pulse which has a width equal to the difference between the width of the pulse fed from the vertical oscillator circuit and the width of pulse fed from the differential amplifier circuit. 4. A transformerless output vertical deflection circuit claimed in claim 2, wherein said control circuit comprises a capacitor which is charged by a fixed power source and is discharged by means of a switching transistor operated by the pulses fed from the vertical oscillator circuit and a differential amplifier circuit receiving the voltage on the capacitor and the output of said smoothing circuit. 5. A transformable output vertical deflection circuit comprising a vertical oscillator for generating a vertical pulse train in response to vertical synchronizing pulses applied thereto, a sawtooth signal generator for generating a series of sawtooth signals each cycle of said sawtooth signal including a pulse component, a vertical output circuit for amplifying said sawtooth signal including said pulse component and loading a vertical deflection coil, and pulse stabilizing means coupled between the vertical oscillator circuit a
nd the sawtooth signal generator, said stabilizing means comprising a capacitor which is charged by a fixed power source and discharged by means of a discharging means operated in response to the vertical pulse fed from the vertical oscillator, a circuit means for generating a train of output pulses each starting at the time when the voltage appearing on the capacitor exceeds a predetermined value and terminating in synchronism with termination of the pulse fed from the vertical oscillator, and gating means for generating pulses having a width equal to the difference between the width of the pulse fed from the vertical oscillator and the width of the output pulse of the circuit means. 6. A transformerless output vertical deflection circuit, comprising a vertical oscillator circuit for generating a vertical pulse train in response to vertical synchronizing pulses applied thereto, a sawtooth signal generator for generating a series of sawtooth signals, each cycle of said sawtooth signal including a pulse component, a vertical output circuit coupled to said sawtooth generator for amplifying said sawtooth signal including said pulse component and loading a vertical deflection coil, and stabilizing means, comprising a control circuit connected between said vertical output circuit and said vertical oscillator circuit for varying the width of each pulse produced by the vertical oscillator circuit in response to a DC control signal having a value corresponding to the width of the pulse component applied to the vertical deflection coil of the vertical output circuit for controlling the pulse width of the output of said vertical oscillator circuit and thereby the pulse width of said pulse component.
Description:
BACKGROUND OF THE INVENTION
The present invention relates to a vertical deflection circuit for use in a television receiver and, more particularly, to a vertical deflection circuit of a type wherein no vertical output transformer is employed. This type of vertical deflection circuit with no output transformer is generally referred to as an OTL (Output Transformerless) type vertical deflection circuit.
It is known that variation of the pulse width of the flyback pulse produced in a vertical output stage of the vertical deflection circuit is the cause in the raster on the television picture tube, of a white bar, flicker, jitter, line crowding and/or other raster disorders. In addition thereto, in the vertical deflection output circuit where the output stage is composed of a single-ended push-pull amplifier having a vertical output transistor, an excessive load is often imposed on the output transistor and, in an extreme case, the output transistor is destroyed.
The TDA2530 is an integrated RGB -matrix preamplifier for colour television receivers,
incorporating a matrix preamplifier for RGB cathode drive of the picture tube with
clamping circuits. The three channels have the same layout to ensure identical frequency
behaviour.
This integrated circuit has been designed to be driven from the TDA2522 Synchronous
demodulator and oscillator IC.
TDA2522 PAL TV CHROMA DEMODULATOR COMBINATION
FAIRCHILD LINEAR INTEGRATED CIRCUIT
GENERAL DESCRIPTION- The TDA2522 is a monolithic integrated circuit designed as
a synchronous demodulator for PAL color television receivers. It includes an 8,8 MHz
oscillator and divider to generate two 4.4 MHz reference signals and provides color difference outputs.
PACKAGE OUTLINE 9B
The TDA2522 is Intended to Interface directly with the TDA2560 with a minimum oF external components. The TDA2530 may be added if RGB drive is required. The TDA2522
is constructed using the Fairchild Planar* process.
TDA2560 LUMINANCE AND CHROMINANCE CONTROL COMBINATION
The TDA2560 is a monolithic integrated circuit for use in decoding systems of COLOR
television receivers. The circuit consists of a luminance and chrominance amplifier.
The luminance amplifier has a low input impedance so that matching of the luminance
delay line is very easy.
It also incorporates the following functions:
- d.c. contrast control;
- d.c. brightness control;
- black level clamp;
- blanking;
- additional video output with positive-going sync.
The chrominance amplifier comprises:
- gain controlled amplifier;
- chrominance gain control tracked with contrast control;
- separate d.c. saturation control:
- combined chroma and burst output, burst signal amplitude not affected by contrast and
saturation control;
- the delay line can be driven directly ‘by the IC.
APPLICATION INFORMATION (continued)
The function is quoted against the corresponding pin number
Balanced chrominance input signal (in conjunction with pin 2)
This is derived from the chrominance signal bandpass filter, designed to provide a
push-pull input. A signal amplitude of at least 4 mV peak-to-peak is required
between pins l and 2. The chrominance amplifier is stabilized by an external feedback
loop from the output (pin 6) to the input (pins I and 2). The required level at pins l
and 2 will be 3 V.
All figures for the chrominance signals are based on a colour bar signal with 75%
saturation: i.e. burst-to-chrominance ratio of input signal is 1 1 2.
Chrominance signal input (see pin 1)
A. C.C. input
A negative-going potential, starting at +l,2 V, gives a 40 dB range of a. c. c.
Maximum gain reduction is achieved at an input voltage of 500 mV.
Chrominance saturation control
A control range of +6 dB to >-14 dB is provided over a range of d. c. potential on
pin 4 from +2 to +4 V. The saturation control is a linear function of the control
voltage.
Negative supply (earth)
Chro minance signal output
For nominal settings of saturation and contrast controls (max. -6 dB for saturation,
and max. -3 dB for contrast) both the chroma' and burst are available at this pin, and
in the same ratio as at the input pins 1 and 2. The burst signal is not affected by the
saturation and contrast controls. The a.c. c. circuit of the TDA2522 will hold
constant the colour burst amplitude at the input of the TDA2522. As the PAL delay
line is situated here between the TDA256O and TDA2522 there may be some variation
of the nominal 1 V peak-to-peak burst output of the TDA2560, according to the
tolerances of the delay line. An external network is required from pin 6 of the
TDA256O to provide d. c. negative feedback in the chroma channel via pins I and 2.
Burst gating and clamping pulse input
A two-level pulse is required at this pin to be used for burst gate and black level
clamping. The black level clamp is activated when the pulse level is greater than
7 V. The timing of this interval should be such that no appreciable encroachment
occurs into the sync pulse on picture line periods during normal operation of the
receiver. The burst gate, which switches the gain of the chroma amplifier to
maximum, requires that the input pulse at pin 7 should be sufficiently wide, at least
8 ps, at the actuating level of 2,3 V.
Correct operation occurs within the range 10 to 14 V. All signal and control levels
have a linear dependency on supply voltage but, in any given receiver design, this
range may be restricted due to considerations of tracking between the power supply
variations and picture contrast and chroma levels.
Flyback blanking input waveform
This pin is used for blanking the luminance amplifier. When the input pulse exceeds
the +2, 5 Vlevel, the output signal is blanked to a level of about 0 V. When the input
exceeds a +6 V level, a fixed level of about 1, 5 V is inserted in the output. This
level can be used for clamping purposes.
Luminance sigal output
An emitter follower provides a low impedance output signal of 3 V black-to-white
amplitude at nominal contrast setting having a black level in the range 1 to 3 V. An
external emitter load resistor is not required.
The luminance amplitude available for nominal contrast may be modified according
to the resistor value from pin 13 to the +12 V supply. At an input bias current
114 of 0,25 mA during black level the amplifier is compensated so that no black
level shift more than 10 mV occurs at contrast control. When the input current
deviates from the quoted value the black level shift amounts to 100 mV/rnA.
Brightness control
The black level at the luminance output (pin 10) is identical to the control voltage
required at this pin, A range of black level from l to 3 V may be obtained.
Black level clamp capacitor
Luminance gain setting resistor
The gain of the luminance amplifier may be adjusted by selection of the resistor
value from pin 13 to +12 V. Nominal luminance output amplitude is then 3 V
black-to-white at pin 10 when this resistor is 2, 7.
TDA1082
East-West correction driver circuit
East-West correction driver circuit TDA1082:
GENERAL DESCRIPTION
The TDA1082 is a monolithic integrated circuit driving east-west correction of colour tubes in television receivers.
The circuit can be used for class-A and class-D operation and incorporates the following functions:
· differential input amplifier
· squaring stage
· differential output amplifier with driver stage
· protection stage with threshold
· switching off the correction during flyback
· voltage stabilizer
QUICK REFERENCE DATA
PACKAGE OUTLINE
16-lead DIL; plastic (SOT38); SOT38-1;
Supply voltage (pin 1) VP typ. 12 V
Current consumption IP typ. 17 mA
Total power dissipation Ptot max. 600 mW
Operating ambient temperature range Tamb 0 to + 70 °C
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MAB8021
DESCRIPTION
The MAB8021 is a single-chip 8-bit microcomputer that is fabricated using the N-MOS silicon gate
process It contains a 1K ><: 8 program memory, a 64 x 8 data memory, 21 I/O lines, and an 8-bit
timer/event counter, in addition to on-board oscillator and clock circuits.
For systems that require
extra I/O capacity, the MAB8021 can be expanded using the 8243 or discrete logic.
This microcomputer is designed to bean efficient controller as well as an arithmetic computer. The
MAB802l has bit handling capability as well as facilities for both binary and BCD arithmetic. Efficient
use of program memory results from aw instruction set (see Table 4) consisting mostly of single byte
instructions and no instructions; over two bytes in length.
FEATURES
8~bit CPU, ROM, RAM,I/O in a single 28-lead package
1K x 8 ROM, 64 x 8 RAM,
Internal timer/event counter
Clock generated with single inductor or crystal
Single 5 V supply (range: + 4,5 V to + 6,5 V)
38 us cycle time; all instructions 1 or 2 cycles
lnstructions: MAB8048 subset
Zero-cross detection capability.
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