AUTOVOX TVC2609 SPAZIO 99TC CHASSIS 121 INTERNAL VIEW

 

AUTOVOX TVC2609 SPAZIO 99TC CHASSIS 121 Power Supply CONSTANT-VOLTAGE CONVERTER EMPLOYING THYRISTOR:


A constant voltage converter having a rectifier for rectifying AC power and with a thyristor connected between the rectifier and a filter for selectively passing therethrough a rectified output to an output terminal. There is a wave generator connected to the output of the rectifier for producing a first signal and an intergrator circuit connected to the output of the wave generator for producing an integral output in response to this first signal. In addition there is a detector circuit for detecting a fluctuation of the rectified output power and for producing second signal. A comparison circuit is connected between the intergrator circuit and the detector circuit for producing third signal in accordance with the comparison. A trigger circuit is connected between the comparison circuit and the control gate of the thyristor for supplying a phase control signal to the thyristor to thereby obtain a constant voltage output regardless of the fluctuation of the rectified output.

1. A constant voltage converter comprising an input of a power supply means, an output terminal, filter means, rectifier means connected to said input for rectifying a.c. power and for supplying output thereof to said output terminal, thyristor means connected between said rectifier means and said filter means for selectively passing therethrough a rectified output to the output terminal by way of said filter means, saw-tooth wave generator means connected between the output of said rectifier means and at least one integrator circuit means for producing an integral output in response to a saw-tooth wave produced, a first transistor in said saw-tooth wave generator, the input of said integrator circuit means being connected to a collector of said first transistor, detector circuit means connected to said output terminal for detecting a fluctuation of the rectified output power and for producing an output signal, said detector circuit means having a second transistor, pulse generator circuit means connected between said saw-tooth wave generator means and said detector circuit means for producing a trigger pulse to said thyristor through a trigger means, a third transistor in said pulse circuit generator means, the base of said third transistor being connected to the output of said integrator circuit means, the emitter thereof being connected to the emitter of said second transistor in said detector circuit means, and the collector thereof being connected to the gate of the thyristor means so as to supply a phase control signal thereto, thereby obtaining a constant voltage output regardless of the fluctuation of the rectified output.

Description:

This invention relates to constant-voltage converters and more particularly to a constant-voltage converter employing a thyristor.

Conventional constant-voltage converters of the type employing a thyristor are arranged to phase shift and full-wave-rectify an input a.c. power applied thereto and to maintain the output voltages constant by regulating the firing angle of the thyristor in comparison of the output voltages with the phase-shifted and rectified input a.c. power. When, however, these converters are connected to a common a.c. source having a relatively high internal impedance, the waveform of the phase-shifted and rectified a.c. input power is distorted thereby causing undesired operations of the converters.

It is therefore an object of the present invention to provide a constant-voltage converter which correctly operates notwithstanding the distortion of the input a.c. voltage.

Another object of the invention is to provide a constant-voltage converter which effectively suppress an undesired rush current.

Another object of the invention is to provide a constant-voltage converter having an improved feed-back circuit of a substantially constant loop gain .

In the drawings:

FIG. 1 is a schematic view of a converter according to the present invention;

FIG. 2 is a diagram showing a circuit arrangement of the converter of FIG. 1;

FIG. 3 is a diagram showing various waveforms of signals appearing in the circuit of FIG. 2;

FIG. 4 is a diagram showing various waveforms appearing in the circuit of FIG. 2 when an a.c. power is supplied to the circuit;

FIG. 5 is a diagram showing another circuit arrangement of the converter of FIG. 1;

FIG. 6 is a diagram showing waveforms of signals appearing in the circuit of FIG. 5; and

FIG. 7 is a diagram showing further another circuit arrangement of generator the of FIG. 1.

Referring now to FIG. 1, a constant-voltage converter 10 according to the present invention comprises a rectifier 11 having two input terminals 12 and 13 through which an a.c. power is supplied. The rectifier 11 is preferably a full-wave rectifier although a half-wave rectifier may be employed. An output 14 of the rectifier 11 is connected through a line 15 to an anode of a thyristor 16. The thyristor 16 passes therethrough the rectified a.c. power in only one direction from its anode to cathode when triggered by a trigger pulse through its gate. The cathode of the thyristor 16 is connected through a line 17 to an input of a smoothing filter 18. The smoothing filter 18 smoothes the power from the thyristor 16. An output of the smoothing filter 18 is connected through a line 19 to an output terminal 20. The output 14 of the rectifier 11 is also connected through a line 21 to a saw-tooth wave generator 22 which generates a saw-tooth wave signal having the same repetition period as the rectified input a.c. power. An output of the saw-tooth wave generator 22 is connected through a line 23 to one input of a trigger pulse generator 24. The other input of the trigger pulse generator 24 is connected through a line 25 to the line 19. An output of the trigger pulse generator 24 is connected through a line 26 to the gate of the thyristor 16. The trigger pulse generator 24 produces a trigger pulse on its output when the voltage of the saw-tooth wave signal reaches a level which is varied in response to the output voltage on the terminal 20. The trigger pulse generator 24 may be variously arranged and in this case arranged to comprise rectangular generator 27 having one input connected through the line 23 to the saw-tooth wave generator 22 and the other input connected through a line 28 to an output voltage detector 29. The detector 29 produces a reference signal representing the output voltage on the terminal 20. The pulse generator 27 is adapted to produces a rectangular pulse when the saw-tooth wave signal to the one input reaches a level which defined is in accordance with the reference signal. An output of the rectangular pulse generator 27 is connected through a line 30 to an input of a trigger circuit 31. The trigger circuit 31 is adapted to convert the rectangular pulse into a spike pulse. An output of the trigger circuit 31 is connected through the line 26 to the gate of the thyristor 16.

FIG. 2 illustrates a preferred circuit arrangement of the converter shown in FIG. 1 which comprises a rectifier 11 of a full-wave rectifier consisting of rectifiers 40, 41, 42 and 43. Inputs of the rectifier are connected to terminals 12 and 13 through which an a.c. power is applied. The output 14 of the rectifier 11 is connected through a line 15 to an anode of a thyristor 16. A cathode of the thyristor 16 is connected through a line 17 to a smoothing filter 18 which includes a capacitor C4 having one terminal connected to the line 17 and the other terminal grounded. The output of the smoothing filter 18 is connected through a line 19 to an output terminal 20.

The saw-tooth wave generator 22 includes a resistor R ₁ having one terminal connected to the line 21 and the terminal connected through a junction J ₁ to one terminal of a resistor R ₂ . The other terminal of the resistor R ₂ is grounded. The junction J ₁ is connected through a coupling capacitor C ₁ to a base of a transistor T ₁ of PNP type. An emitter of the transistor T ₁ is connected through a resistor R ₃ to the line 21. A resistor R ₄ is provided between the emitter and the base of the transistor T ₁ so as to apply a bias potential to the base. A collector of the transistor T ₁ is grounded through a parallel connection of a resistor R ₅ and capacitor C ₂ . To the emitter is connected a capacitor C ₃ which is in turn grounded and passes therethrough only a.c. signals to the ground.

The rectangular pulse generator 27 comprises a transistor T ₂ of PNP type having a base connected through a resistor R ₆ to the collector of the transistor T ₁ . An emitter of the transistor T ₂ is connected through a resistor R ₇ to the emitter of the transistor T ₁ . A collector of the transistor T ₂ is grounded through a resistor R ₈ and connected through the line 30 to one terminal of a capacitor C ₄ of the trigger circuit 31. The other terminal of the capacitor C ₄ is connected through a line 26 to the gate of the thyristor 16.

The output voltage detector 29 includes a transistor T ₃ of NPN type having an emitter grounded through a zener diode ZD. A collector of the transistor T ₃ is connected through a line 28 to the emitter of the transistor T ₂ and, on the other hand, connected through a capacitor C ₅ to the grounded. A base of the transistor T ₃ is connected to a tap of an adjustable resistor R ₉ connected through a resistor R ₁₀ and a line 25 to the line 19 and connected, in turn, to the ground through a resistor R ₁₁ .

When, in operation, an a.c. electric power is applied through the input terminals 12 and 13 of the rectifier 11, a full-wave rectified power as shown in FIG. 3 (a) appears on the output 14. The rectified power is applied through the line 15 to the anode of the thyristor 16. The thyristor 16 passes therethrough the rectified power while its firing angle is regulated by the trigger signal applied to the gate. The rectified power passed through the thyristor 16 is applied through the line 17 to the smoothing filter 18. The smoothing filter smoothes the power by removing the ripple component in the power. The smoothed power appears on the line 19 which is to be supplied to a load through the output terminal 20. The smoothed power on the line 19 is, on the other hand, delivered through the line 25 to the resistor R ₁₀ of the output voltage detector 29. The resistor R ₁₀ constitutes a voltage divider in cooperation with the resistors R ₉ and R ₁₁ . The output of the voltage divider is applied through the tap of the resistor R ₉ to the base of the transistor T ₃ . When the potential of the base of the transistor T ₃ exceeds the zener voltage of the zener diode ZD, a base current flows through the transistor T ₃ so as to render the transistor T ₃ conductive. The potential of the collector of the transistor T ₃ then varies in accordance with the voltage of the smoothed output power on the line 19. The potential variation at the collector of the transistor T ₃ is then applied through the line 28 to the trigger pulse generator 27 and utilized to regulate the triggering timing of the thyristor 16.

The full-wave rectified power is, on the other hand, applied through the line 21 to the saw-tooth wave generator 22. Since the resistors R ₁ and R ₂ consistute a voltage divider to reduce the voltage of the full-wave rectified power to a potential at the junction J ₁ , a charging current to the capacitor C ₁ flows from the emitter to the base of the transistor T ₁ whereby the transistor T ₁ repeats ON-OFF operation in accordance with the voltage of the rectified power. If the transistor T ₁ is conductive when the voltage of the full-wave rectified power is lower than a threshold voltage v ₁ as shown in FIG. 3(a), then the potential at the collector of the transistor T ₁ is varied as shown in FIG. 3 (b) due to the charge and discharge of the capacitor C ₂ . The variation of the potential at the collector of the transistor T ₁ is supplied through the line 23 to the resistor R ₆ of the trigger pulse generator 27.

As long as the voltage of the smoothed power on the line 19 equals to the rated output voltage, the transistor T ₂ is adapted to become conductive when the voltage of the saw-tooth wave signal falls below a threshold value v ₃ shown in FIG. 3(b). Therefore, a potential at the collector of the transistor T ₂ varies as shown in FIG. 3(c). The potential variation, that is, a pulse signal at the collector of the transistor T ₂ is supplied through the line 30 to the capacitor C ₄ of the trigger circuit trigger 31. The trigger circuit 31 converts the pulse signal into a spike pulse or a trigger pulse shown in FIG. 3(d) which is then applied through the line 25 to the gate of the thyristor 16. Upon receiving the spike pulse, the thyristor 16 becomes conductive until the voltage of the rectified power on the line 15 falls below the cut-off voltage of the thyristor 16.

When the voltage of the smoothed power on the line 19 exceeds the rated output voltage, the collector current of the transistor T ₃ increases with the result that the current flowing through the resistor R ₇ increases. The threshold voltage of the transistor T ₂ therefore reduces to a voltage v ₂ as shown in FIG. 3(b). At this instant, leading edge of the pulse signal delays as shown by dot-and-dash lines in FIG. 3(c), so that each trigger pulse delays as shown by dot-and-dash line in FIG. 3(d). When on the contrary, the voltage of the smoothed signal on the line 19 lowers below the rated output voltage, the collector current of the transistor T ₃ decreases whereby the threshold voltage rises to a voltage v ₄ in FIG. 3(b). Each leading edge of the signal pulse now leads as shown by dotted line in FIG. 3(d). Being apparent from the above description, the appearance timing of each trigger pulse is regulated in accordance with the voltage of the smoothed power on the line 19 so that the voltage of the output voltage at the terminal 20 is held substantially constant.

Referring now to FIG. 4, start operation of the converter 10 is discussed hereinbelow in conjunction with FIG. 2. When an a.c. voltage is applied to the input terminals 12 and 13, the capacitor C ₃ begins to be charged by the voltage on the line 15, and the capacitor C ₅ also begins to be charged through the resistors R ₃ and R ₇ . It is important that the time constant of power supply circuit constituted by the resistor R ₃ and the capacitor C ₃ is selected to be much larger than that of the time constant of another power supply circuit constituted by the resistor R ₇ and the capacitor C ₅ . Thus, the emitter potential of the transistor T ₁ is built up more quickly than that of the transistor T ₂ . Upon completion of the charging of the capacitor C ₃ , the saw-tooth wave generator 22 begins to generate saw-tooth wave signal as shown in FIG. 4(b). Since the capacitor C ₅ is, on the other hand, slowly charged, the emitter voltage of the transistor T ₂ slowly rises as shown in FIG. 4(c), so that, the threshold voltage of the transistor T ₂ gradually rises as shown by a dotted line in FIG. 4 (b). Accordingly, the trigger pulses is produced on the gate of the thyristor 16 as shown in FIG. 4(d), whereby the firing angle of the thyristor 16 is gradually reduced as shown in FIG. 4(a) which illustrates the voltage at the output terminal 14 of the rectifier 11. The output voltage on the output terminal 20 therefore gradually rise up as shown in FIG. 4(e). It is to be understood that since the output voltage of the converter 10 starts to gradually rise up as shown in FIG. 4(e), an undesired rush current is effectively suppressed.

FIG. 5 illustrates another form of the converter 10 which is arranged identically to the circuit arrangement of FIG. 1 except that an integrator 50 is interposed between the output of the saw-tooth wave generator 22 and the input of the trigger pulse generator 27. The integrator 50 includes a resistor R ₁₂ having one terminal connected to the output of the saw-tooth wave generator 22 and the other terminal connected to the input of the rectangular pulse generator 27, and a capacitor C ₇ having one terminal connected to the other terminal of the resistor R ₁₂ and the other terminal grounded.

In operation, the saw-tooth wave generator 22 produces on its ouput a saw-tooth wave signal having decreasing exponential wave form portion as shown in FIG. 6 (a), although the saw-tooth wave signal ideally is illustrated in FIG. 3. This saw-tooth wave signal is converted by the integrator 50 into another form of saw-tooth wave having a increasing exponential wave form portion as shown in FIG. 6(b).

It should be noted that the saw-tooth wave signal of FIG. 6(a) has a smaller inclination near 180°. Hence, when the integrator 50 is omitted and the saw-tooth wave signal as shown in FIG. 6(a) is applied to the trigger pulse generator 27, the rate of change of the output voltage of the converter 10 become larger at a firing angle near to 180°. On the other hand, it is apparent from FIG. 6(c) that the rate of change the output voltage of the thyristor 16 with respect to the firing angle become large at a firing angle near to 180°. Therefore, the loop gain of the trigger pulse generator 24 increases when the firing angle of the thyristor 16 is near to 180°. It is apparent through a similar discussion that the loop gain of the trigger pulse generator 24 decreases when the firing angle is near to 90°. Such non-uniformity of the loop gain of the trigger pulse generator invites a difficulty of the regulation of the output voltage of the converter. It is to be noted that the saw-tooth wave signal shown in FIG. 6(b) has a large inclination at an angle near 180°. Therefore, when the saw-tooth wave signal of FIG. 6(b) is applied to the trigger pulse generator 24, the loop gain of the trigger pulse generator 24 is held substantially constant, whereby the output voltage of the converter is effectively held constant.

It is to be understood that the integrator 50 may be substituted for by a miller integrator and a bootstrap integrator. Furthermore, a plurality of integrator may be employed, if desired.

FIG. 7 illustrates another circuit arrangement of the converter according to the present invention, which is arranged identically to the circuit of FIG. 2 except for the trigger circuit 31 and the smoothing circuit 18.

The trigger circuit 31 of FIG. 7 comprises a transformer TR with primary and secondary coils. One terminal of the primary coil is connected to the resistor R ₇ of the pulse generator 27. The other terminal of the primary coil is connected to a collector of a transistor T ₄ of NPN type. The secondary coil has terminals respectively connected to the gate and cathode of the thyristor 16. An emitter of the transistor T ₄ is grounded through a resistor R ₁₃ . A base of the transistor T ₄ is grounded through a resistor R ₁₄ and connected through a capacitor C ₈ to the collector of the transistor T ₂ of the pulse generator 27.

The smoothing filter 18 of FIG. 7 comprises a choke coil CH connected to the lines 17 and 19, and to capacitors C ₉ and C ₁₀ which are in turn grounded. The circuit of FIG. 7 operates in the same manner as the circuit of FIG. 2.

Obviously many modifications and variations of the present invention are possible in the light of the above teachings. It is therefore to be understood that within the scope of the appended claims the invention may be practiced otherwise than as specifically described.


AUTOVOX TVC2609 SPAZIO 99TC CHASSIS 121 CHASSIS 101 UNITS:

IF VIDEO DEMOD + AMPL + SOUND IF unit (Motorola TBA120C) (Motorola CA270BE) VIF STAGE

- CHROMINANCE unit (PHILIPS TBA570 + TBA540 + TAA630S)

- LUMINANCE + SYNCHRONIZATION unit (TBA920)

- Color difference amplifier + Luminance amplifier stage unit

- Line deflection output unit. (Texas Instruments BU208A)

- Frame deflection output unit. ( 2 x Motorola BD142-4 )

- E/W Correction output unit. (RCA BD182)


The Luminance and the chrominance are amplified and performed in separate way until the CRT MATRIX (CRT DE MATRIXING)



TBA920 line oscillator combination


DESCRIPTION
The line oscillator combination TBA920 is a monolithic
integrated circuit intended for the horizontal deflection of the black and white
and colour TV sets
picture tube.

FEATURES:
SYNC-PULSE SEPARATION
OPTIONAL NOISE INVERSION
GENERATION OF A LINE FREQUENCY VOL-
TAGE BY MEANS OF AN OSCILLATOR
PHASE COMPARISON BETWEEN SYNC-
PULSE AND THE OSCILLATOR WAVEFORM
PHASE COMPARISON BETWEEN THE OS-
CILLATOR WAVEFORM AND THE MIDDLE OF
THE LINE FLY-BACK PULSE
AUTOMATIC SWITCHING OF THE VARIABLE
TRANSCONDUCTANCE AND THE VARIABLE
TIME CONSTANT TO ACHIEVE NOISE SUP-
PRESSION AND, BY SWITCHING OFF, POS-
SIBILITY OF TAPE-VIDEO-REGISTERED RE-
PRODUCTION
SHAPING AND AMPLIFICATION OF THE OS-
CILLATOR WAVEFORM TO OBTAIN PULSES
FOR THE CONTROL OF DRIVING STAGES IN
HORIZONTAL, DEFLECTION CIRCUITS
USING EITHER TRANSISTORS OR THYRISTORS,
 THE TBA920 SYNC/TIMEBASE IC It has been quite common for some time for sync separation to be carried out in an i.c. but until 1971 this was as far as i.c.s had gone in television receiver timebase circuitry. With the recent introduction of the delta featured 110°  colour series however i.c.s have gone a step farther since this chassis uses a TBA920 as sync separator and line generator. A block diagram of this PHILIPS /Mullard  i.c. is shown in Fig. 1.
The video signal at about 2-7V peak -peak is fed to the sync separator section at pin 8, the composite sync waveform appearing at pin 7.
The noise gate switches off the sync separator when a positive -going input pulse is fed in at pin 9, an external noise limiter circuit being required .
The line sync pulses are shaped by R1 /C1 /C2/R2 and fed in to the oscillator phase detector section at pin 6.
The line oscillator waveform is fed internally to the oscillator phase detector circuit which produces at pin 12 a d.c. potential which is used to lock the line oscillator to the sync pulse frequency, the control potential being fed in at pin 15. The oscillator itself is a CR type whose waveform is produced by the charge and discharge of the external capacitor (C7) connected to pin 14. The oscillator frequency is set basically by C7 and R6 and can be varied by the control potential appearing at pin 15 from pin 12 and the external line hold control. Internally the line oscillator feeds a triangular waveform to the oscillator and flyback phase detector sections and the pulse width control section. The coincidence detector section is used to set the time constant of the oscillator phase detector circuit. It is fed internally with sync pulses from the sync separator section, and with line flyback pulses via pin 5. When the flyback pulses are out of phase with the sync pulses the impedance looking into pin 11 is high (21(Q). When the pulses are coincident the impedance falls to about 150Q and the oscillator phase detector circuit is then slow acting. The effect of this is to give fast pull -in when the pulses are out of sync and good noise immunity when they are in sync. The coincidence detector is controlled by the voltage on pin 10. When the sync and flyback pulses are in sync C3 is charged: when they are out of sync C3 discharges via R3. VTR use has been taken into consideration here. With a video recorder it is necessary to be able to follow the sync pulse phase variations that occur as a result of wow and flutter in the tape transport system, while noise is much less of a problem. For use with a VTR therefore the network on pin 10 can simply be left out so that the oscillator phase detector circuit is always fast acting. A second control loop is used to adjust the timing of the pulse output obtained from pin 2 to take into account the delay in the line output stage. The fly back phase detector compares the frequency of the flyback pulses fed in at pin 5 with the oscillator signal which has already been synchronised to the sync pulse frequency.
Any phase difference results in an output from pin 4 which is integrated and fed into the pulse width control section at pin 3. The potential at pin 3 sets the width of the output pulse obtained at pin 2: with a high positive voltage (via R11 and R12) at pin 3 a 1:1 mark -space ratio out- put pulse (32/us on, 32/us off) will be produced while a low potential at pin 3 (negative output at pin 4) will give a 16us output pulse at  the same frequency. The action of this control loop continues until the fly- back pulses are in phase with a fixed point on the oscillator waveform: the flyback pulses are then in phase with the sync pulses and delays in the line output stage are compensated. The output obtained at pin 2 is of low impedance and is suitable for driving valves, transistors or thyristors: R9 is necessary to provide current limiting.

BU208(A)

Silicon NPN
npn transistors,pnp transistors,transistors
Category: NPN Transistor, Transistor
MHz: <1 MHz
Amps: 5A
Volts: 1500V
HIGH VOLTAGE CAPABILITY
JEDEC TO-3 METAL CASE.

DESCRIPTION
The BU208A, BU508A and BU508AFI are
manufactured using Multiepitaxial Mesa
technology for cost-effective high performance
and use a Hollow Emitter structure to enhance
switching speeds.

APPLICATIONS:
* HORIZONTAL DEFLECTION FOR COLOUR TV With 110° or even 90° degree of deflection angle.

ABSOLUTE MAXIMUM RATINGS
Symbol Parameter Value Unit
VCES Collector-Emit ter Voltage (VBE = 0) 1500 V
VCEO Collector-Emit ter Voltage (IB = 0) 700 V
VEBO Emitter-Base Voltage (IC = 0) 10 V
IC Collector Current 8 A
ICM Collector Peak Current (tp < 5 ms) 15 A
TO - 3 TO - 218 ISOWATT218
Ptot Total Dissipation at Tc = 25 oC 150 125 50 W
Tstg Storage Temperature -65 to 175 -65 to 150 -65 to 150 oC
Tj Max. Operating Junction Temperature 175 150 150 °C

A vertical deflection circuit for use in a television receiver, comprising a control circuit for stabilizing the width of a pulse either in a vertical oscillator circuit or between a vertical oscillator circuit and vertical output circuit to thereby stabilize the width of a pulse component included in the vertical deflection output signal.

AUTOVOX TVC2609 SPAZIO 99TC CHASSIS 121 TDA1170 vertical deflection FRAME DEFLECTION INTEGRATED CIRCUIT

GENERAL DESCRIPTION f The TDA1170 and TDA1270 are monolithic integrated
circuits designed for use in TV vertical deflection systems. They are manufactured using
the Fairchild Planar* process.
Both devices are supplied in the 12-pin plastic power package with the heat sink fins bent
for insertion into the printed circuit board.
The TDA1170 is designed primarily for large and small screen black and white TV
receivers and industrial TV monitors. The TDA1270 is designed primarily for driving
complementary vertical deflection output stages in color TV receivers and industrial
monitors.
APPLICATION INFORMATION (TDA1170)
The vertical oscillator is directly synchronized by the sync pulses (positive or negative); therefore its free
running frequency must be lower than the sync frequency. The use of current feedback causes the yoke
current to be independent of yoke resistance variations due to thermal effects, Therefore no thermistor is
required in series with the yoke. The flyback generator applies a voltage, about twice the supply voltage, to
the yoke. This produces a short flyback time together with a high useful power to dissipated power
ratio.

1. A transformerless output vertical deflection circuit, comprising a vertical oscillator circuit for generating a vertical pulse train in response to vertical synchronizing pulses applied thereto, a sawtooth signal generator for generating a series of sawtooth signals, each cycle of said sawtooth signal including a pulse component, a vertical output circuit coupled to said sawtooth generator for amplifying said sawtooth signal including said pulse component and loading a vertical deflection coil, and stabilizing means connected between said vertical oscillator and said sawtooth signal generator for varying the width of the pulse component which is to be fed to said vertical output circuit in response to the average level of DC output voltage fed from the vertical output circuit. 2. A transformerless output vertical deflection circuit claimed in claim 1, wherein said stabilizing means comprises a control circuit means for receiving a series of pulses from the vertical oscillator and a feedback signal from the vertical output circuit and for varying the width of the pulse which is to be fed to the vertical output circuit in response to a DC control signal proportional to the width of the pulse component included in the vertical output signal and smoothing circuit means connected between said vertical output circuit and said stabalizing means for smoothing said feedback signal. 3. A transformerless output vertical deflection circuit claimed in claim 2, wherein said control circuit comprises a charging capacitor which is parallel to a transistor, said transistor being switched on in response to pulses fed from the vertical oscillator wherein said capacitor is charged by the voltage fed from said smoothing circuit, and discharged in response to conduction of the transistor, a differential amplifier circuit which receives the voltage on said capacitor and a fixed voltage, and a gating circuit for producing a pulse which has a width equal to the difference between the width of the pulse fed from the vertical oscillator circuit and the width of pulse fed from the differential amplifier circuit. 4. A transformerless output vertical deflection circuit claimed in claim 2, wherein said control circuit comprises a capacitor which is charged by a fixed power source and is discharged by means of a switching transistor operated by the pulses fed from the vertical oscillator circuit and a differential amplifier circuit receiving the voltage on the capacitor and the output of said smoothing circuit. 5. A transformable output vertical deflection circuit comprising a vertical oscillator for generating a vertical pulse train in response to vertical synchronizing pulses applied thereto, a sawtooth signal generator for generating a series of sawtooth signals each cycle of said sawtooth signal including a pulse component, a vertical output circuit for amplifying said sawtooth signal including said pulse component and loading a vertical deflection coil, and pulse stabilizing means coupled between the vertical oscillator circuit and the sawtooth signal generator, said stabilizing means comprising a capacitor which is charged by a fixed power source and discharged by means of a discharging means operated in response to the vertical pulse fed from the vertical oscillator, a circuit means for generating a train of output pulses each starting at the time when the voltage appearing on the capacitor exceeds a predetermined value and terminating in synchronism with termination of the pulse fed from the vertical oscillator, and gating means for generating pulses having a width equal to the difference between the width of the pulse fed from the vertical oscillator and the width of the output pulse of the circuit means. 6. A transformerless output vertical deflection circuit, comprising a vertical oscillator circuit for generating a vertical pulse train in response to vertical synchronizing pulses applied thereto, a sawtooth signal generator for generating a series of sawtooth signals, each cycle of said sawtooth signal including a pulse component, a vertical output circuit coupled to said sawtooth generator for amplifying said sawtooth signal including said pulse component and loading a vertical deflection coil, and stabilizing means, comprising a control circuit connected between said vertical output circuit and said vertical oscillator circuit for varying the width of each pulse produced by the vertical oscillator circuit in response to a DC control signal having a value corresponding to the width of the pulse component applied to the vertical deflection coil of the vertical output circuit for controlling the pulse width of the output of said vertical oscillator circuit and thereby the pulse width of said pulse component.

Description:

BACKGROUND OF THE INVENTION

The present invention relates to a vertical deflection circuit for use in a television receiver and, more particularly, to a vertical deflection circuit of a type wherein no vertical output transformer is employed. This type of vertical deflection circuit with no output transformer is generally referred to as an OTL (Output Transformerless) type vertical deflection circuit.

It is known that variation of the pulse width of the flyback pulse produced in a vertical output stage of the vertical deflection circuit is the cause in the raster on the television picture tube, of a white bar, flicker, jitter, line crowding and/or other raster disorders. In addition thereto, in the vertical deflection output circuit where the output stage is composed of a single-ended push-pull amplifier having a vertical output transistor, an excessive load is often imposed on the output transistor and, in an extreme case, the output transistor is destroyed.

AUTOVOX TVC2609 SPAZIO 99TC CHASSIS 121 Amplifier suitable for use as a color kinescope driver:

A color kinescope matrix amplifier has a first input coupled through a capacitor to a source of color difference signals. Another input is coupled to a source of luminance signals. The matrix amplifier includes a cascode output stage direct current coupled to a cathode of a kinescope. A portion of a direct voltage developed at the cascode output amplifier is coupled to one input of a comparator circuit. The other input of the comparator circuit is coupled to a temperature compensated direct voltage reference source. The comparator is rendered operative during horizontal retrace intervals to provide a current to either charge or discharge the input capacitor in accordance with the difference between the voltage at the output of the cascode output amplifier and the reference voltage to compensate for voltage variations at the output of the cascode amplifier due to power supply variations and the like. To compensate for droop caused by the discharge of the input capacitor during the scanning interval, one input of a differential amplifier is included between the input capacitor and the input of the cascode output stage. Negative signal feedback is provided from the output stage to the other input of the differential amplifier via a capacitor arranged to be charged during the horizontal retrace interval. The two capacitors discharge at substantially the same rates during the scanning interval. By virtue of the common mode operation of the differential amplifier droop effects are minimized.


1. In a television receiver including an image reproducing device, a source of chrominance signals, a source of luminance signals and a source of horizontal blanking pulses, said horizontal blanking pulses occurring during the time interval during which said image reproducing device is horizontally retraced, the apparatus comprising:

amplifying means for combining said chrominance signals and said luminance signals, said amplifying means including first and second input terminals and an output terminal, said output terminal being direct current coupled to said image reproducing device, said second input terminal being direct current coupled to said source of said luminance signals;

first capacitive means for coupling said chrominance signals to said first input terminal;

comparator means having first and second input terminals for comparing voltages applied thereto, said comparator means being normally inoperative;

a relatively low level stabilized reference voltage source coupled to said first input terminal of said comparator means;

means coupled to said second input terminal of said comparator means for providing a direct voltage proportional to the direct voltage developed at said output terminal;

means for selectively rendering said comparator operative in response to said horizontal blanking pulses; and

current converting means coupled to said comparator and to said first capacitive means for charging and discharging said capacitive means to a direct voltage level in relation to the difference in voltage between said first and second input terminals of said comparator means so as to counteract the changes of the voltage developed at said output terminal.

2. The apparatus recited in claim 1 wherein said amplifying means includes:

a differential amplifier having first and second input terminals and an output terminal, said first input terminal being coupled to said first input terminal of said amplifying means, said output terminal of said differential amplifier being coupled to said output terminal of said amplifying means;

second capacitive means coupled to said second input terminal of said differential amplifier; and

means for selectively charging said second capacitive means during said horizontal retrace interval, said first and second capacitive means being selected to have substantially equal discharging rates during the time intervals between said horizontal retrace intervals.

3. The apparatus recited in claim 2 wherein said second capacitive means is coupled between said output terminal of said amplifying means and said second input terminal of said differential amplifier. 4. The apparatus recited in claim 3 wherein said amplifying means includes a cascode amplifier coupled between the output of said differential amplifier and said output terminal of said amplifying means. 5. The apparatus recited in claim 3 wherein said amplifying means includes first and second transistors, the emitter of said first transistor being direct current coupled to the collector of said second transistor, the base of said first transistor being coupled to said first input terminal of said amplifying means, the base of said second transistor being coupled to said second input terminal of said amplifying means, the emitter of said first transistor being coupled to said first input terminal of said differential amplifier. 6. The apparatus recited in claim 3 wherein said means for selectively charging said second capacitive means includes means for clamping the second input terminal of said differential amplifier to a predetermined voltage during said horizontal retrace interval. 7. The apparatus recited in claim 3 wherein means are provided for adjusting the portion of the voltage developed at said output terminal of said amplifying means which is coupled to said second capacitive means. 8. The apparatus recited in claim 1 wherein said means coupled to said second input terminal of said comparator means for providing a direct voltage proportional to the direct voltage developed at said output terminal of said amplifying means includes means for adjusting the voltage coupled to said second input terminal of said comparator means. 9. The apparatus recited in claim 1 wherein said comparator means includes:

a differential amplifier having two input terminals and two output terminals, one of said input terminals being coupled to said reference voltage source, the other of said input terminals being coupled to said output terminal of said amplifier means; and

a current mirror circuit having an input and an output, one of said output terminals of said differential amplifier being coupled to said input terminal of said current mirror circuit, the other of said output terminals of said differential amplifier being coupled to the output of said current mirror circuit and to said first capacitor means.

10. The apparatus recited in claim 1 wherein said voltage reference source is temperature compensated. 11. In a television receiver including a color kinescope leaving a plurality of electron beam forming apparatus, a source of luminance signals, a source of a plurality of color difference signals, and a source of horizontal blanking pulses, said horizontal blanking pulses corresponding to the time interval during which said electron beams are horizontally retraced, the apparatus comprising:

a plurality of amplifiers, each of said amplifiers including

amplifying means for combining one of said plurality of color difference signals with said luminance signals, said amplifying means including first and second input terminals and an output terminal, said output terminal being direct current coupled to a respective one of said plurality of electron beam forming apparatus, said second input terminal being direct current coupled to said source of said luminance signals, capacitive means for coupling said one of said plurality of color difference signals to said first input terminal,

comparator means having first and second input terminals for comparing voltages applied thereto, said comparator means being normally inoperative,

means coupled to said second input terminal of said comparator means for providing a direct voltage proportional to the direct voltage developed at said output terminal,

means for selectively rendering said comparator operative in response to said horizontal blanking pulses, and

current converting means coupled to said comparator and to said capacitive means for charging and discharging said capacitive means to a direct voltage level in relation to the difference in voltage between said first and second input terminals of said comparator means so as to counteract the changes of the voltage developed at said output terminal; and a relatively low level stabilized reference

voltage source coupled to said first input terminals of each of said plurality of comparator means.

Description:

The present invention is directed to the field of amplifiers and is particularly directed to the field of amplifier arrangements utilized to drive color image reproducing devices such as kinescopes.

The electron guns of a color kinescope are typically driven by separate amplifier stages. Variations of the operating conditions of an amplifier stage, such as variations of the stage's supply voltage, tend to produce variations in the brightness of a reproduced image. Furthermore, because each of the stages tends to operate at different power dissipation levels the operating conditions of the stages vary with respect to each other and hence color imbalances may occur.

Athough supply voltage regulators and high level clamping circuits have been employed in conjunction with kinescope amplifier stages to inhibit the aformentioned problems, it is desirable to provide kinescope driver amplifier arrangements which maintain their operating point stability with variations in operating conditions such as power supply variations without the need of supply voltage regulators or high level clamping circuits.

Furthermore, it is desirable, because of the trend toward miniaturization in electronic art, that at least a portion of the kinescope amplifier driver should be able to be constructed in integrated circuit form.

It is also desirable to provide kinescope driver amplifier arrangements which include independent controls for adjusting the DC level and the AC amplitude of the signals coupled to the kinescope. This is particularly desirable where "precision-in-line" kinescopes or the like, in which the electron guns have common control electrodes, are employed since, in these types of kinescopes, it is difficult to independently adjust the operating conditions associated with the respective guns because of the commonality of control electrodes.

Furthermore, it is desirable that a kinescope driver amplifier which is to be utilized with a precision-in-line type of kinescope provide a relatively wide bandwidth without the requirement of high frequency peaking coils. Peaking coils tend to be bulky. In addition, undesirable voltages may be developed across a peaking coil due to the large magnetic fields which may be produced by the yokes associated with a precision-in-line kinescope. These undesirable voltages may produce disconcerting brightness and/or hue changes.

In accordance with the present invention, one input terminal of amplifying means is coupled to a source of chrominance signals through capacitive means. A second input of the amplifying means is direct current coupled to a source of luminance signals. The output terminal of the amplifying means is direct current coupled to a color image reproducing device such as a precision-in-line kinescope of the like. The amplifying means includes means for combining the luminance and chrominance signals to provide the image reproducing device with color signals. The amplifying means also includes comparator means for comparing the voltage developed at the output terminal to a reference voltage to generate a current to control the charging of the capacitive means in a manner so as to counter-act the changes of the voltage developed at the output due, for example, to changes in the power supply voltage. The comparator means is arranged to be normally inoperative and is selectively rendered operative during the horizontal retrace interval.

In accordance with another aspect of the present invention, the amplifying means includes a differential amplifier having first and second input terminals and an output terminal. The output terminal of the differential amplifier is coupled to the output terminal of the amplifying means. The first input terminal of the differential amplifier is coupled to the input terminal of the amplifying means. The second input terminal of the differential amplifying means is coupled to a second capacitive means. Means are provided for selectively charging the second capacitive means during the horizontal retrace interval. The first and second capacitive means are selected to have substantially equal discharging rates so as to compensate for any decrease in the DC content (i.e., droop) at the output terminal of the amplifying means during the scanning interval.

In accordance with still another feature of the present invention, the second capacitive means is coupled to the output terminal of the amplifying means in a manner so as to allow adjustment of the AC gain of the amplifying means. The DC conditions of the output of the amplifying means may be controlled by controlling the portion of the voltage developed at the output terminal coupled to the comparator means.

The present invention may best be understood by reference to the following detailed description and accompanying drawing which shows, partially in block diagram form and partially in schematic form, the general arrangement of a color television receiver employing a kinescope driver amplifier arrangement constructed in accordance with the present invention .

The color television receiver includes a video signal processing unit 141 responsive to radio frequency (RF) signals, received by an antenna, for receiving in a known manner, a composite video signal comprising chrominance, luminance, sound and synchronizing signal components.

The output of video processing unit 141 is coupled to a chrominance channel 142 including a chrominance processing unit 143 and a color demodulator 144. Chrominance processing unit 143 separates chrominance signals from the composite video signal. Color demodulator 144 derives signals of the appropriate polarity representing, for example, R-Y, G-Y and B-Y color difference signal information from the chrominance signals. The TAA630 integrated circuit or similar circuit is suitable for use as color demodulator 144.

The output of video processing unit 141 is also coupled to a luminance channel 145 including a luminance processing unit 146 which amplifies and processes luminance components of the composite signal to form an output signal of the appropriate polarity representing luminance, Y, information. A brightness control unit 147 to control the DC content of luminance signal Y and a contrast control unit 148 to control the amplitude of luminance signal Y are coupled to processing unit 146.

The composite video signal is also coupled to a sync separator 149 which, in turn, is coupled to a horizontal deflection unit 151 and a vertical deflection unit 152. Horizontal deflection unit 151 is also coupled to a high voltage unit 154 which generates operating voltages for kinescope 153. Outputs from horizontal deflection unit 151 and vertical deflection unit 152 are coupled to luminance processing unit 146 to inhibit or blank luminance signal Y during the horizontal and vertical retrace intervals. Similarly, an output from horizontal deflection unit 151 may be coupled to chroma processing unit 143 or color demodulator 144 to inhibit the color difference signals during the horizontal retrace interval. Furthermore, first and second signals including positive going pulses, the pulses of each signal being coincident with the horizontal retrace or blanking interval, are coupled to matrix unit 100 to control its operation, as will appear below, via conductors 159 and 167, respectively.

The R-Y output signal and luminance signal Y are coupled to a matrix unit 100 where they are combined to form a color signal representing red (R) information. Similarly, the B-Y and G-Y color difference signals are respectively coupled to matrix-driver units 150 and 157, similar to the combination of matrix unit 100 and kinescope driver 199, where they are matrixed with luminance signal Y to produce color signals representing blue (B) and green (G) information. Since the matrix units for the various color difference signals are similar, only matrix unit 100 will be described in detail.

Matrix unit 100, enclosed within dotted line 160, is suitable for construction as an integrated circuit. The R-Y color difference signal is coupled through a capacitor 110 to the base of an NPN transistor 101 which is arranged as a common collector amplifier for color difference signals. Transistor 101, NPN transistor 102, resistors 178 and 184 form a summing circuit 161 for the color difference signal and luminance signal Y, the latter being direct current coupled to the base of transistor 102. The combined output of circuit 161, taken at the collector of transistor 102, is coupled to the base of an NPN transistor 105. Transistor 105 and an NPN transistor 106 form a differential amplifier 162 to which bias current is supplied from a current source including a suitably biased transistor 182. The output of differential amplifier 162, taken at the collector of transistor 105, is coupled through a level shifter, shown as the series connection of a zener diode 163, and a diode 165 to a kinescope 199. Bias current is provided for zener diode 163 and diode 165 through a resistor 183, which serves as the load resistor of transistor 105, and resistors 176 and 177.

Kinescope driver 199 comprises a cascode amplifier 164 including NPN transistors 120 and 119. The output of matrix unit 100 is coupled to the base of transistor 119 while a positive supply voltage (e.g. +12 volts) is coupled to the base of transistor 120. The output of kinescope driver 199, taken at the collector of transistor 120 is direct current coupled through a resistor 179 to the red (R) cathode of kinescope 153. The collector of transistor 120 is coupled to a source of supply voltage B+ through a load resistor 165. Supply voltage B+ is a relatively high voltage, typically, in the order of 200 to 300 vdc.

The collector of transistor 120 is also coupled to a series combination of a resistor 166 and a black level setting potentiometer 167, the latter being returned to ground. A direct voltage proportional to that at the collector of transistor 120 is developed at the wiper arm of potentiometer 167 and is coupled to one input of a voltage comparator circuit 168. Comparator 168 comprises NPN transistors 103 and 104 coupled as a differential amplifier. A second input of comparator 168, at the base of transistor 103, is coupled to a temperature compensated voltage reference (TCVR) unit 169. Voltage reference unit 169, which may, for example, be similar to that employed in the CA3085 integrated circuit manufactured by RCA Corporation, supplies a regulated reference voltage of approximately 1.6 vdc.

Voltage reference unit 169 is also coupled to the matrix portions of units 150 and 157 via conductor 155 so that a common reference voltage is coupled to the respective comparators of units 100, 150 and 157. It is noted that matrix unit 100 and the matrix portions of units 150 and 153 may be constructed as a single integrated circuit.

A current source including an NPN transistor 170 is coupled to the jointly connected emitters of transistors 103 and 104. The first horizontal blanking pulse signal generated by horizontal deflection unit 151 is coupled to the base of transistor 170 via conductor 159.

The output of differential amplifier 168 provided at the collector of NPN transistor 103 is converted to a bidirectional current by means of a current mirror circuit 180 comprising a diode-connected PNP transistor 172 and a PNP transistor 173. The collector of transistor 173 is coupled to the collector of transistor 104 and to the base of transistor 101.

The junction of resistors 166 and 167 is coupled to a signal feedback circuit comprising a series connection of a potentiometer 174 and a resistor 175. Feedback voltage developed at the wiper arm of potentiometer 174 is coupled through a capacitor 120 to the base of transistor 106 (i.e., one input of differential amplifier 162). The base of transistor 106 is returned to ground through resistor 181 and the collector-emitter junction of a transistor 108. The base of transistor 108 is coupled to horizontal deflection unit 151 to receive the first horizontal blanking pulse signal via conductor 159. An NPN transistor 107, the emitter of which is coupled to the base of transistor 106, is arranged together with resistor 181 and the collector-emitter junction of transistor 108 as an emitter follower. The base of transistor 107 is coupled to horizontal deflection unit 151 to receive the second horizontal blanking pulse signal via conductor 167. It is noted that this signal may also be generated within the IC device.

Kinescope 153 may be a precision-in-line kinescope such as the RCA type 15VADTCO1. As is described in U.S. Pat. No. 3,817,397, issued May 21, 1974, there is no provision for separate adjustment of red, green and blue gun screen and grid potentials and only the cathodes of the three guns of such a kinescope are available for separate adjustment of the cut off point of the guns. As will become apparent in the following description, matrix unit 100 and kinescope driver 199 are particularly suited to a kinescope of the precision-in-line type but it should be appreciated that they may be utilized for other types of kinescopes such as delta-gun, shadow mask or other slotted mask types.

In operation, the signal supplied to the base of transistor 107 during the scanning interval by horizontal deflection unit 151 is of sufficiently low amplitude (e.g., less than +4vdc) in relationship to the voltage at its emitter (controlled by the charge on capacitor 120 as will be explained) that it is non-conductive. Because of relatively low voltage applied to the bases of transistors 108 and 170 during the scanning interval, transistors 108, 170, 103 and 104 are also non-conductive and do not affect the operation of matrix circuit 100 during the scanning interval.

The signal -(R-Y), representing red color difference information, and the signal Y, representing luminance information, are coupled to amplifier 161 where they are combined in the emitter circuit of transistor 101 to form a signal -R, representing red information. The signal -R is further amplified and inverted twice by differential amplifier 162 and cascode amplifier 164 for application to kinescope 153.

It is noted that resistors 183, 176 and 177 should be selected so that zener diode 163 is biased well into its reverse breakdown region to inhibit noise.

The portion of the output signal of cascode amplifier 164 developed at the wiper arm of potentiometer 174, is capacitively fed back to one input of differential amplifier 162. This negative feedback arrangement, in conjunction with the use of cascode amplifier 199, provides for a relatively wide bandwidth, thereby eliminating the need for peaking coils or the like to improve high frequency response. The AC gain (or drive) of the matrix unit-kinescope driver arrangement may be adjusted by adjustment of the wiper arm of potentiometer 174 (normally a service or factory adjustment).

During the horizontal retrace interval, a relatively high voltage (e.g., approximately +6 vdc plus the base to emitter voltage of transistor 107 when transistor 107 is rendered conductive) is applied to the base of transistor 107 from horizontal deflection unit 151. Horizontal deflection unit 151 also applies a relatively high voltage to the bases of transistors 108 and 170. As a result transistors 107, 108, 170, 103 and 104 are rendered conductive and the base of transistor 106 is clamped to a voltage substantially equal to the voltage at the base of transistor 107 less the base emitter voltage of transistor 107 (e.g., +6 vdc). The voltage to which the base of transistor 106 is clamped is sufficiently lower than that at the base of transistor 105 so that transistor 106 will be rendered non-conductive and transistor 105 will be rendered fully conductive. Under these conditions, the voltage developed at the collector of transistor 120 will rise toward B+ to a voltage determined by the conduction of transistors 119 and 120 and the voltage division action of resistors 165, 166 and the impedance of potentiometer 167 in parallel combination with the series combination of potentiometer 174 and resistor 175.

While the base of transistor 106 is clamped to the voltage applied to the base of transistor 107 less the voltage developed between the base and emitter of transistor 107, the AC feedback provided by capacitor 120 is effectively disconnected and capacitor 120 is provided with a charging path including resistor 166 and a portion of potentiometer 174 by which it is rapidly charged to a voltage determined by the voltage at the emitter of transistor 107 and DC voltage developed at the collector of transistor 120.

The voltage developed at the wiper arm of potentiometer 167 is coupled to the base of transistor 104 and, during each horizontal retrace interval, is compared to the voltage developed at the base of transistor 103 by TCVR 169. A difference in voltage is converted by virtue of the current mirror configuration of transistors 172 and 173 into an error current at the junction of the collectors of transistors 104 and 173. The error current acts, depending on the relative levels at the bases of transistors 103 and 104, to charge or discharge capacitor 110.

Potentiometer 167 initially is adjusted to provide a voltage at the collector of transistor 120 sufficient to cut off the red gun of kinescope 153 when a black image signal is present. Therefore, it is desirable to select the values of resistors 165 and 166 and potentiometer 167 to ensure that the full range of black level control at the red cathode of kinescope 153 is available.

Matrix circuit 100 is arranged so that capacitor 110 will be charged or discharged in a manner to compensate for any change in B+. For example, if B+ decreases, the voltage developed at the base of transistor 104 will decrease relative to the stable reference voltage developed at the base of transistor 103. Therefore, the collector current of transistor 103 and the substantially equal currents flowing through the emitter-collector circuits of transistors 172 and 173 will increase, causing capacitor 110 to be charged. As a result, the voltage at the base of transistor 101 will increase, the voltage at the base of transistor 105 will increase, the voltage at the collector of transistor 105 will decrease and the voltage at the collector of transistor 120 will increase.

It is noted that transistor 173 and transistor 104 operate in what may be termed a push-pull fashion in that the change in current flowing between the emitter and collector of transistor 173 is inversely related to the change in current flowing between the collector and the emitter of transistor 104. Thus, if the current flowing through the emitter-collector of transistor 104 increases, the current through the collector-emitter of transistor 173 decreases, so that capacitor 110 is discharged by the excess of current flowing through transistor 104 rather than being charged by current from transistor 173.

Thus, the feedback arrangement including TCVR 169 of matrix unit 100 adjusts the charge on capacitor 110 to compensate for, and therefore substantially eliminate, the effect on the direct voltage applied to the kinescope cathodes of variations in B+. Furthermore, it is noted that variations in other portions of the matrix amplifier driver arrangement (such as variations caused by temperature or component tolerance changes) affecting the DC conditions at the collector of transistor 120 will be compensated for by the arrangement in a similar manner.

The charge stored on capacitor 110 during the horizontal retrace interval serves to control the bias on cascode amplifier 164 during the succeeding scanning interval. It is noted that the charge on capacitor 110 is not affected by the color difference signals or luminance signals during the horizontal retrace interval, since these signals are arranged to be constant during the horizontal retrace interval.

After the horizontal retrace interval, transistors 103, 104, 170, 172, 173, 107 and 108 are rendered nonconductive (as previously described) and capacitors 110 and 120 begin to discharge. While capacitor 110 controls the bias voltage at the base of transistor 105, capacitor 120 controls the bias voltage at the base of transistor 106. Capacitors 110 and 120 and their associated discharging circuitry preferably are selected so that capacitors 110 and 120 discharge at substantially equal rates. The similar changes in voltage are applied to opposite sides of differential amplifier 162. The common mode rejection characteristics of differential amplifier 162 will prevent the discharging of capacitor 110 to be reflected in the DC conditions at the collector of transistor 120. This "droop" compensation feature provided by capacitor 120 in junction with differential amplifier 162 is desirable, since in its absence, capacitor 110 would have to be a relatively large value to prevent droop. This is especially undesirable if it is desired to construct matrix unit 100 as an integrated circuit because large currents, not compatible with integrated circuit technology, would be required to charge and discharge capacitor 110.

Typical values for the arrangement are shown on the accompanying drawing.

It should be noted that although the present invention has been described in terms of a particular configuration shown in the diagram, modifications may be made which are contemplated to be within the scope of the invention. For instance, cascode driver 199 may be placed with other driver stages well known in the art. Furthermore, the current mirror configuration comprising transistors 172 and 173 may be modified in accordance with other known current mirror configurations.

Rapid tuning circuit for high frequency receivers:AUTOVOX TVC2609 SPAZIO 99TC CHASSIS 121 DIGITAL FREQUENCY SYNTHESIZER:

SM564 + SAB3209 + TMS3894 + SO437

THE TUNING SEARCH AND STORE FUNCTION WAS PERFORMED ONLY VIA REMOTE.

1. An electronic system for tuning a receiver to a selected television channel comprising:
a. a voltage controlled oscillator;
b. a voltage signal generator for sweeping and holding the frequency of said oscillator;
c. a harmonic comb frequency generator for generating a first plurality of signals at 24 MHz frequency intervals, and a second plurality of signals at 6 MHz frequency intervals, said first plurality of signals being generated in response to a channel selection signal, said second plurality of signals being generated in response to a first actuating signal;
d. a mixing circuit for heterodyning the output signal of said oscillator with the output signal of said harmonic comb frequency generator;
e. a tuned amplifier connected to said mixing circuit for transmitting beat frequency signals of a predetermined frequency in the output signal of said mixing circuit;
f. an envelope detector connected to said tuned amplifier for converting said beat frequency signals to pulses, said envelope detector providing said first actuating signal to said harmonic comb frequency generator in response to a first beat frequency signal;
g. counting circuits connected to said envelope detector for counting said beat frequency signal pulses;
h. memory circuits for storing an entry number related to said selected television channel;
i. compare circuits for comparing said beat frequency pulse count in said counting circuits with said entry number in said memory circuits and for applying a second actuating signal to said voltage signal generator for stopping frequency sweeping of said oscillator when a preestablished relationship between said entry number and said pulse count exists; and
j. a discriminator continuously coupled between said tuned amplifier and said signal generator and cooperative therewith for stabilizing said oscillator frequency.

Description:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to the electronic tuning of a signal-receiving unit to a selected frequency and more particularly to apparatus for the automatic tuning of a television receiver to the selected channel.
2. Description of the Prior Art
The tuning system of television receiver units, according to the prior art, provides for a received broadcast signal and an output signal from a local oscillator to be applied to a heterodyne conversion transducer. The output signal of the conversion transducer is applied to an automatic frequency control conduit, including a discriminator, which in turn controls the local oscillator. The output signal of the transducer is also applied to intermediate frequency apparatus tuned to a difference or beat frequency between the received signal and the local oscillator frequency. The discriminator characteristics are chosen so that the local oscillator signal is maintained at a frequency to provide optimum performance of the intermediate frequency apparatus and subsequent demodulation apparatus of the television receiver. There is a local oscillator frequency which provides for the demodulation of each television channel.
It is known in the prior art to provide mechanical apparatus for providing a course frequency adjustment for the local oscillator. The AFC circuit provides the vernier control of the local oscillator frequency. It would be desirable to replace the mechanical apparatus with electronic apparatus to reduce maintenance problems associated with mechanical apparatus.
In the prior art, the received broadcast signal is used in conjunction with the local oscillator frequency in an automatic frequency tuning circuit. Originally, the received broadcast signal was utilized in order to minimize changes in the frequency of the output signal of the local oscillator. However, an internal reference frequency can be employed in the AFC circuit without compromising the channel reception by the television receiver.

It is a desirable feature of a television tuning system to provide that the entry of a channel number in the television receiver results in the entered channel being demodulated and the audio/visual information being available. It is also a desirable feature of a television system to tune electronically to a desired channel, decreasing the maintenance problems as well as expediting production of the channel information after entry of the selected channel designation in the system.
It is therefore an object of the present invention to provide an improved system for tuning to a preselected frequency.
It is another object of the present invention to provide an improved television receiver.
It is yet another object of the present invention to provide an electronic system for tuning to a selected television channel.
It is a particular object of the present invention to provide an electronic automatic frequency tuning circuit for tuning to a preselected frequency in which a local oscillation signal and a reference generator signal are combined to stabilize the oscillator signal frequency.
It is another particular object of the present invention to provide an electronic automatic frequency tuning circuit including a local oscillator capable of electronically sweeping the frequency of the oscillator through a frequency region.
It is yet another particular object of the present invention to provide a means for halting the frequency of a local oscillator signal frequency at a selected value.
It is a still more particular object of the present invention to identify a selected television channel by counting the number of beat frequency signals resulting from a combining of a variable local oscillator and a set of harmonic frequency signals.
It is a still further object of the present invention to provide an electronic automatic frequency tuning circuit with a reference signal generator producing a comb of harmonic frequency signals, the beat frequency signals occurring between varying local oscillator signal and the generator signals identifying a preselected local oscillator signal, and the combined signals of the local oscillator signal and a selected harmonic frequency of the reference generator used to stabilize the local oscillator signal.
It is a further object of the present invention to provide an electronic automatic frequency tuning circuit capable of tuning to every available commercial television channel.

SUMMARY OF THE INVENTION
The aforementioned and other objects are accomplished, according to the present invention, by an automatic frequency tuning circuit including a local oscillator with a controllable frequency output signal, apparatus for continuously varying the frequency of the oscillator output signal, and apparatus for combining the local oscillator output signal with a signal from a reference signal generator. The combined signals are used to identify a selected frequency of the local oscillator and suspend the changing of the frequency of the local oscillator signal. The combined signals are also used in conjunction with a discriminator circuit to stabilize the frequency of the local oscillator signal once the selected frequency is attained.
Upon entry of a channel designation into control apparatus of the automatic frequency tuning circuit, the channel designation causes the binary encoded channel designation to be entered in storage circuits and a related initial value to be entered in counting circuits of control apparatus. After entry of the initial values in the counting circuits, the local oscillator output signal frequency is continuously increased from a predetermined initial frequency. The signal from the reference generator, comprised of a comb of 6 MHz harmonic frequency signal components, is applied, along the output signal of the local oscillator to a heterodyne conversion transducer. The 1 MHz beat frequency signals from the transducer are transmitted by a tuned circuit and are counted by the counting circuits of the control apparatus. Television channels, excluding channel 5 and channel 6, have frequencies 1 MHz removed from appropriate 6 MHz harmonic frequencies. The local oscillator will provide the appropriate local oscillator frequency when the related number of counts has been identified by the control apparatus.
Thereafter, the output of the tuned circuit, applied to the discriminator, stabilizes the frequency of the local oscillator signal to provide optimum performance of the receiver apparatus.
Channel 5 and channel 6 can be tuned by separate apparatus.
A television receiver is provided comprising a variable frequency local oscillator and frequency synthesizer control means for controlling the frequency of the variable frequency local oscillator in accordance with the setting of variable divider means for effecting channel or frequency tuning of said receiver, the frequency synthesis control means comprising first divider means operable on the output of the variable frequency local oscillator, the first divider means being set to one of a plurality of division ratios under the control of fine tuning means associated therewith, variable divider means operable on the output of the first divider means, and phase/frequency comparator means for comparing the output of the variable divider means with a reference frequency and for affording a control signal to the variable frequency local oscillator for controlling its frequency.
1. A frequency synthesis control system for communications equipment including a variable frequency oscillator the frequency of which is changed to effect channel or frequency tuning of said equipment, the control system comprising,
first divider means for dividing the output of the variable frequency oscillator by a first division ratio or a second division ratio under the control of a fine tune control signal applied to said first divider means, the output of said first di

vider means being a first divided signal,
variable frequency divider means for dividing said first divided signal, the division ratio of which is selected in accordance with a required channel or frequency of said equipment, the output of said variable divider means being a second divided signal,
reference frequency generator means for generating a reference frequency signal, and
comparator means for comparing the second divided signal and the reference frequency signal and for producing a control signal which is fed to the variable frequency oscillator for controlling its frequency,
fine tuning means being provided for applying the fine tuning control signal to the first divider means and for applying a further fine tuning control signal to the variable frequency divider means whereby the division ratios of both divider means are changed for effecting fine tuning of the variable frequency oscillator.

2. A system as claimed in claim 1, in which the variable frequency divider means includes first programmable divider means, memory means being provided for selecting a division ratio of the first programmable divider means that corresponds to a required channel or frequency of said equipment. 3. A system as claimed in claim 2, in which the memory means takes the form of a read only memory. 4. A system as claimed in claim 2, in which the variable frequency divider means includes a further programmable divider means operable in conjunction with the first programmable divider means and to which the further fine tuning control signal from the fine tuning means is applied for controlling its operation. 5. A system as claimed in claim 4, in which the further programmable divider means takes the form of multi-bit shift delay means. 6. A system as claimed in claim 4, in which the further programmable divider means takes the form of multi-bit counter means. 7. A system as claimed in claim 1, in which the comparator means takes the form of a phase/frequency comparator. 8. A system as claimed in claim 7,

in which the variable frequency oscillator is voltage controlled, the phase/frequency comparator providing a control voltage to the variable frequency oscillator for controlling its frequency. 9. A system as claimed in claim 8, in which the voltage controlled variable frequency oscillator includes at least one varactor diode to which the control voltage is applied. 10. A system as claimed in claim 1, in which the first divider means includes prescaler divider means for dividing the output of the variable frequency oscillator and dual modulus divider means for dividing the output of the prescaler divider means to produce the first divided signal. 11.

A system as claimed in claim 7, in which the fine tuning means includes counter means being responsive to the output of the further programmable divider means for providing a fine tuning control signal to the first divider means for changing the division ratio of said first divider means. 12. A system as claimed in claim 11, in which the counter means comprises a fixed counter operable under the control of a control signal applied to it and a variable counter operable under the control of a control signal applied to it, the fixed counter and the variable counter being connected effectively in series. 13. A system as claimed in claim 12, in which the output of the variable counter is applied to the first divider means via synchronising latch means operable in conjunction with the output of the first divider means. 14. A system as claimed in claim 13, wherein the frequency of said variable frequency oscillator is changed to effect channel tuning of said equipment, the system further comprising channel counter means operable in conjunction with the memory means for selecting a division ratio of the first programmable divider means in accordance with a required channel of said equipment. 15. A system as claimed in claim 14, comprising channel select means connected to the channel counter means for selecting the required channel. 16. A system as claimed in claim 15, in which the channel select means takes the form of a digital switch. 17. A system as claimed in claim 15, comprising fine counter means for providing the control signal to the variable counter. 18. A system as claimed in claim 15, in which the channel select means and the fine counter means operate in conjunction with the timing control means under the control of a `tune` signal applied thereto. 19. A system as claimed in claim 18, in which the tuning control means derives an input thereto from the reference frequency generator means. 20. A system as claimed in claim 19, in which the channel counter means is provided with control means for changing the counting rate of the channel counter means. 21. A system as claimed in claim 20, in which the control means is effective for providing a coarse/fine control. 22. A system as claimed in claim 17, in which the fine counter means takes the form of an up/down counter which is provided with control inputs for causing the counter means to count up or count down. 23. A system as claimed in claim 17, comprising further memory means for storing information relating to the count positions of the channel counter means and the fine counter means corresponding to a required channel. 24. A system as claimed in claim 23, in which the further memory means is of non-volatile form. 25. A system as claimed in claim 24, in which the further memory means takes the form of a metal-nitride-oxide-semiconductor (MNOS) memory. 26. A system as claimed in claim 24, in which the further memory means takes the form of a complementary metal-oxide-semiconductor (CMOS) memory. 27. A system as claimed in claim 23, further comprising program select means operable in conjunction with the further memory means for causing the channel counter means and the fine counter means to be set in accordance with a preselected channel. 28.

A system as claimed in claim 27, in which the program select means enables one of a plurality of programs, each corresponding to a preselected channel to be selected, the further memory means being arranged to store information relating to the count positions of the channel counter means and the fine counter means for the preselected channels corresponding to the plurality of programs. 29. A system as claimed in claim 27, in which the program select means comprises a program address counter for causing the information stored in the further memory means relating to the count positions of the channel counter means to be applied to the channel counter means, and for causing the information stored in the further memory means relating to the counter positions of the fine counter means to be applied to the fine counter means. 30. A system as claimed in claim 29, in which the program select means comprises a touch tuning arangement for effecting program selection. 31. A system as claimed in claim 30, in which the touch tuning arrangement comprises a pair of touch plates for each of the programs to be selected, and latch means associated with each pair of touch plates which is caused to be operated when the pair of touch plates with which it is associated are activated, each of the latch means being effective for causing a common voltage to be applied to the program address counter to cause the information relating to a preselected channel and corresponding to a required program, stored in the further memory means to be applied to the channel counter means and the fine counter means respectively. 32. A system as claimed in claim 31, in which the touch tuning arrangement comprises indicator means for indicating which program has been selected.

Description:

This invention relates to communications equipment and although applicable to both receivers and transmitters is especially applicable to television receivers. The present invention relates more specifically to a frequency synthesis control system for use in such equipment to effect channel or frequency tuning thereof.
Frequency tuning, more often referred to as channel selection in present day television receivers, can be achieved manually and/or by preset push button, touch controls etc. The stabilisation of the frequency tuning is normally achieved by means of an automatic frequency control (AFC) system in which a comparison is made between an intermediate frequency with a reference tuned circuit and an error signal derived which is used to change the frequency of the local oscillator. Receivers incorporating such an AFC system suffer from the disadvantages that the accuracy is dependent upon the initial setting up of the reference tuned circuit which anyway tends to change with time; the operation of the AFC loop depends upon the incoming signal strength so that below a threshold level the loop will not operate; there is the possibility of the loop being captured by an adjacent strong signal when attempting to hold a weak signal; and it is necessary to remove the AFC when tuning to a different frequency.
The present invention avoids the necessity of using an AFC system by utilising a digital synthesis technique for tuning the local oscillator of a television receiver. In this way very accurate tuning without any setting up is obtained; there is no dependence on signal strength; capture by strong adjacent channels is impossible; and an indication of frequency channel tuning is automatically obtained.

According to the present invention there is provided a frequency synthesis control system for communications equipment including a variable frequency oscillator the frequency of which is changed to effect channel or frequency tuning of said equipment the control system comprising,
First divider means operable on the output of the variable frequency oscillator and settable to a first division ratio or a second division ratio under the control of a fine tune control signal applied to it to afford a first divided signal,
Variable frequency divider means operable on the first divided signal, the division ratio of which is selected in accordance with a required channel or frequency of said equipment to afford a second divided signal,
Reference frequency generator means for affording a reference frequency signal, and
comparator means for comparing the second divided signal and the reference frequency signal and for affording a control signal to the variable frequency oscillator for controlling its frequency,
fine tuning means being provided for applying the fine tuning control signal to the first divider means and for applying a further fine tuning control signal to the variable frequency divider means whereby the division ratio of both divider means are changed for effecting fine tuning of the variable frequency oscillator.
In carrying out the invention it may be arranged that the variable frequency divider means includes first programmable divider means, and memory means preferably in the form of a read only memory for selecting a division ratio of the first programmable divider means that corresponds to a required channel or frequency of said equipment, the variable frequency divider means conveniently including a further programmable divider means operable in conjunction with the first programmable divider means and to which the further fine tuning control signal from the fine tuning means is applied for controlling its operation.
In one arrangement according to the invention the further programmable divider means may take the form of multi-bit shift delay means, and in another arrangement the further programmable divider means may take the form of multi-bit counter means.
Conveniently, the comparator means may take the form of a phase-frequency comparator, and the variable frequency oscillator may be voltage controlled, the phase-frequency comparator affording a control voltage to the variable frequency oscillator for controlling its frequency. The voltage controlled variable frequency oscillator may conveniently include at least one varactor diode to which the control voltage is applied.
Advantageously it may be arranged that the first divider means includes prescaler divider means operable on the output of the variable frequency oscillator and dual modulus divider operable on the output of the prescaler divider means for affording the first divided signal.
In a preferred system according to the invention it may be arranged that the fine tuning means includes counter means operable on the output of the further programmable divider means for affording a fine tuning control signal to the first divider means for changing its division ratio, the counter means conveniently comprising a fixed counter operable under the control of a control signal applied to it and a variable counter operable under the control of a control signal applied to it, the fixed counter and the variable counter being connected effectively in series.
Conveniently the output of the variable counter may be applied to the first divider means via synchronising latch means operable in conjunction with the output of the first divider means.
In an especially preferred system according to the present invention for communications equipment including a variable frequency oscillator the frequency of which is changed to effect channel tuning of said equipment, it will be arranged that the system further comprises channel counter means operable in conjunction with the memory means for selecting a division ratio of the first programmable divider means in accordance with a required channel of said equipment.

In such a system channel select means may be provided connected to the channel counter means for selecting the required channel, the channel select means conveniently taking the form of a digital switch.
In carrying out the especially preferred system according to the invention fine counter means will be provided for affording the control signal to the variable counter, and conveniently the channel select means and the fine counter means may operate in conjunction with timing control means under the control of a `tune` signal applied thereto.
Conveniently the timing control means derives an input thereto from the reference frequency generator means.
Conveniently the channel counter means may be provided with control means for changing the counting rate of the channel counter means, the control means being effective for providing a coarse/fine control.

Advantageously the fine counter means may take the form of an up/down counter which is provided with control inputs for causing the counter means to count up or count down, and further memory means may be provided for storing information relating to the count positions of the channel counter means and the fine counter means corresponding to a required channel.
The further memory means is preferably of non-volatile form and conveniently in the form of a metal-nitride-oxide semiconductor (MNOS) memory or a complementary metal-oxide semiconductor (CMOS) memory.
Conveniently program select means may be provided operable in conjunction with the further memory means for causing the channel counter means and the fine counter means to be set in accordance with a preselected channel, the program select means enabling one of a plurality of programs, each corresponding to a preselected channel to be selected, the further memory means being arranged to store information relating to the count positions of the channel counter means and the fine counter means for the preselected channels corresponding to the plurality of programs.

It may be arranged that the program select means comprises a program address counter operable in the further memory means for causing the information stored therein relating to the count positions of the channel counter means and the fine counter means corresponding to a selected program to be applied to the channel counter means and the fine counter means respectively.
It may also be arranged that the program select means comprises a touch tuning arrangement for effecting program selection, the touch tuning arrangement conveniently comprising a pair of touch plates for each of the programs to be selected, and latch means associated with each pair of touch plates which is caused to be operated when the pair of touch plates with which it is associated are activated, each of the latch means being effective for causing a common voltage to be applied to the program address counter to cause the information relating to a preselected channel and corresponding to a required program stored in the further memory means to be applied to the channel counter means and the fine counter means respectively, and conveniently further comprising indicator means for indicating which program has been selected.
It is especially envisaged that a system in accordance with the present invention be used in a television receiver and accordingly in accordance with an aspect of the invention there is provided a television receiver comprising a variable frequency oscillator the frequency of which is changed to effect channel or frequency tuning of said receiver and a frequency synthesis control system in accordance with the present invention.

It is also especially envisaged that a system in accordance with the present system be used in a radio receiver, and accordingly in accordance with a further aspect of the invention there is provided a radio receiver comprising a variable frequency oscillator the frequency of which is changed to effect channel or frequency tuning of said receiver and a frequency synthesis control system in accordance with the present invention.
An exemplary embodiment of the invention will now be described, reference being made to the accompanying drawings, in which;
FIG. 1, is a block schematic diagram of a digital synthesis frequency control system for use in a television receiver according to the present invention;
FIG. 2, is a block schematic diagram of a touch tuning arrangement for use in the digital synthesis frequency control system of FIG. 1;
FIG. 3, is a block schematic diagram of a practical implementation of the digital synthesis frequency control system of FIG. 1;
FIG. 4, is a block schematic diagram of the fine tuning circuit of FIG. 2 in greater detail; and,
FIG. 5-8 are frequency diagrams illustrating the operation of the fine tuning circuit of FIG. 4.
The frequency control system to be described for use in a television receiver makes use of a digital synthesis principle in which a voltage controlled oscillator (VCO), normally in the form of a varactor diode tuned oscillator, is provided as the local oscillator of the television receiver, the frequency of the VCO, after frequency division, being compared with a reference frequency derived from a crystal controlled oscillator again via frequency division, an error signal being derived which is dependent upon the difference between the two compared frequencies, the error signal being applied to the VCO for controlling its frequency. The system acts as a closed feedback loop and the frequency of the VCO is changed so as to maintain the two compared frequencies the same. By changing the division ratio of the frequency divider acting on the output of the VCO, or possibly on the reference oscillator, the frequency of the VCO can be changed to effect frequency tuning i.e. channel selection of the television receiver with which it is associated.
In FIG. 1 of the drawings, there is shown a frequency control system of this form applied to a television receiver. Only part of the television receiver proper is shown, these parts being a tuner 20 fed from an aerial 21, and a voltage controlled local oscillator 22 the frequency of which is controlled by means of a varactor diode arrangement shown schematically at 23, the output of the tuner 20 being fed to a band-pass filter 24 and thence to an I.F. (intermediate frequency) amplifier 25 and a video detector 26 which affords the usual video output 27.
Frequency selection and control of the oscillator 22 and thus channel selection of the tuner 20 is achieved by feeding an output 28 from the oscillator 22 to a variable divider 29, the division ratio of which is variable over a predetermined range in dependence upon a control input 30 applied thereto. The output from the variable divider 29 is applied as one input to a frequency detector 31 which derives a second input from a reference oscillator 32 which operates under the control of a crystal 33 via a fixed divider 34. The output from the frequency detector 31 is applied to an error voltage amplifier 35 the output from which is applied to the varactor diode arrangement 23 of the oscillator 22. The arrangement operates as a closed feedback loop, the frequency of the oscillator 22 being set dependent upon the division ratio of the variable divider 29. The division ratio of the variable divider 29 may be set to correspond to each of the required channels by applying suitable tuning code information to the control input 30 thereof via tuning code input 36.
In this arrangement, the frequency stability is dependent entirely on the stability of the crystal oscillator 33 and the arrangement is advantageous over the known forms of AFC system in that:

(a) Very accurate tuning without any setting up is obtained. Once the frequency or channel code has been set into the variable divider, the accuracy is only dependent upon the accuracy of the oscillator crystal. The requirements of accuracy do not impose very heavily on crystal design and the crystal should not be as expensive as the normal colour crystal used in present day television receivers.
(b) The frequency control is totally independent of signal strength. This is because no input signal is required for the system to operate. The local oscillator is set to the required frequency without the assistance of the incoming signal.

(c) Capture by strong adjacent channels is impossible. This is because the frequency control is entirely independent of the incoming signal. (d) Channel identification is easily obtained. The channel code is unique and an indication of the station being received is easily established from the variable divider. In a preferred arrangement the code may be in decimal form and the station selected by selecting its own number. The code can be individually hand wired and then connected through an existing touch pad or push button system or a simple two-digit decimal switch can be used for each channel giving access to all stations.
(e) Considerable simplification of the television touch tuning system is achieved. In a conventional television touch tuning system, each touch pad is provided with a latch which acts as a memory to operate two sets of switches. One set of switches provides power to light a channel indicator lamp and to provide power to the VHF and UHF tuners. A second set of switches which have to operate at higher voltages pass the accurate voltages required for tuning the VFO varactor diode. This second set of switches whilst having to have the capability of handling typically 33 volts have also to have low `ON` voltage and a very low temperature drift characteristic if the frequency accuracy is to be maintained. By using the frequency control system of the present invention this second set of switches may be completely dispensed with so that the touch tuning system may be simplified to that shown in FIG. 2 of the drawings.
In the arrangement of FIG. 2, six pairs of touch plates 40 are shown, each pair corresponding to a required channel. Each pair of touch plates 40 is effective, when caused to be operated by the close proximity of say a finger to them, for causing a supply voltage V₁ to be applied to a corresponding one of six latches 42. Each of the latches 42, when operated, is arranged to cause a corresponding one of six switches 43 to be closed to connect a second supply voltage V₂ to a corresponding one of six indicator lamps 44 and to a corresponding output 45 which is applied to the channel select system as will be described hereinafter in connection with the embodiment of FIG. 3. In a typical arrangement sixteen touch-plates 40 may be provided for selecting any one of sixteen corresponding outputs 45.
Turning now to the embodiment of FIG. 3, this depicts a frequency control system based on that described with reference to FIG. 1 of the drawings but which has been modified to make it suitable for use in a so-called European type television receiver. In the following table there is set out the channel frequency and local oscillator (L.O.) frequency for the various channels that are currently in use in Europe.

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Channel No. Channel Frequency L. O. Frequency

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2(K2) 48.25 87.15 3(K3) 55.25 94.15 4(K4) 62.25 101.15 5(K5) 175.25 214.15 6(K6) 182.25 221.15 . . . . . . . . . 11(K11) 217.25 256.15 12(K12) 224.25 263.15 21 471.25 510.15 22 479.25 518.15 . . . . . . 50 703.25 742.15 . . . . . . 67 839.25 878.15 68 847.25 886.15 69 855.25 894.15 70(A) 53.75 92.65 71(B) 62.25 101.15 72(C) 82.25 121.15 73(D) 175.25 214.15 74(E) 183.75 222.65 75(F) 192.25 231.15 76(G) 201.25 240.15 77(H) 210.25 249.15 78(J) 217.25 256.15 79(L) 224.25 263.15

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Of these channels 2 to 4 constitute VHF Band I channels; channels 5 to 12 constitute VHF Band III channels; channels 21 to 69 constitute the UHF channels and channels 70 to 79 constitute the Italian VHF channels.

From the above it is evident that the channel separation in the UHF Band is 8MHz and that in the VHF Bands is 7MHz and also that the UHF channels and the VHF odd channels have odd integers in MHz whereas the VHF even channels have even integers in MHz. The VCO or L.O. frequency is equal to the sum of the channel frequency and the I.F. frequency of 38.9MHz.
The object of the frequency control system to be described with reference to FIG. 3 is to generate the required VCO frequencies of the television receiver to a very great accuracy so that the receiver can satisfactorily receive all the channels.
Considering now the block diagram shown in FIG. 3 of the drawings, this consists of a combined VHF/UHF VCO 50 which affords respective VHF and UHF outputs via outputs 51 to a fixed divider 52 having a division ratio of ÷ 64. Selection of one or other of the outputs 51 is effected under the control of two control inputs 53 applied to the VCO 50 and operation of the divider 52 on one or other of the outputs 51 is controlled by one of the control inputs 53 which is applied to it. The output from the fixed divider 52 is applied to a further divider 54, the division ratio of which may be set to ÷ 15 or ÷ 16 under the control of a control input 55 applied to it from a fine tuning circuit 56, the operation of which will be considered in detail with reference to FIG. 4 of the accompanying drawings. The output from the ÷ 15/16 divider 54 is applied to the fine tuning circuit 56 and to a variable frequency divider 57, typically in the form of a down counter, the division ratio N of which is controlled by means of a read only memory (ROM) 58 which also generates the control inputs 53 to the VCO 50. The output from the variable divider 57 is applied, via the fine tuning circuit 56 as will be explained later, as one input to a phase/frequency comparator 59 a second input to which is derived from a crystal oscillator 60 via a further fixed divider 61. The output from the phase/frequency comparator 59 is applied to an active filter 62 which integrates, smooths and amplifiers it to afford a control input to the VCO 50.

The read only memory (ROM) 58 is arranged to store information regarding the division ratio required of the variable divider 57 for each of the 68 possible channels. Selection between the channels in the ROM 58 is effected by an address decode circuit 63 under the control of a channel counter/buffer 64 which is itself controlled from either manual input controls 65 which include a `TUNE` button 66, `FINE UP` button 67, a `FINE DOWN` button 68, a digital switch 69 and an optional coarse/fine button 70, or from channel tuning information stored in a random access memory (RAM) which is preferably of non-volatile form, e.g. CMOS form. Similarly operation of the fine tuning circuit 56 is effected by a `fine` counter 72 which is itself controlled from either the manual input controls 65 or from fine tuning information stored in the RAM 71. The RAM 71 is arranged to store information relating to the settings of the channel counter/buffer 64 and the `Fine` counter 72 for each of sixteen selectable programs which may be selected by means of a program address counter 73 to which address inputs 74 are applied from, for example, a touch tuning arrangement (not shown) as hereinbefore described with reference to FIG. 2 of the accompanying drawings, or from a remote control unit (not shown) of conventional form which may typically afford 5-bit binary coded outputs or may be of the serial impulse type which delivers step and reset outputs. The `fine` counter 72, the channel counter/buffer 64 and the RAM 71 are each fed with timing information derived from a timing control 61' which is fed from the fixed divider 61.
Operation of the circuit arrangement of FIG. 3 may best be understood by considering some typical operating sequences. Let it be assumed that program number one of sixteen possible programs is selected by means of a touch control unit or a remote control which applies the appropriate input to the program address counter 73. Let is also be assumed that, say, channel 50 is required to be selected. The number 50 is therefore set into the digital switch 69 and the `TUNE` button 66 is pressed which causes the channel counter/buffer 64 to be actuated until it reaches a condition corresponding to channel 50. The setting of the channel counter/buffer is then fed into the RAM 71 to a position allocated to program one in which it is stored and is also applied to the address decode circuit 63 which causes the read only memory 58 to set the division ratio N of the variable divider 57 to the division ratio that corresponds to channel 50 as would previously have been stored therein. It may also be arranged that the setting of the channel counter/buffer 64 be displayed on a channel display unit (not shown). The closed feedback loop of the frequency control system then operates until the frequency of the VCO 50 is set to that corresponding to channel 50, thereby causing the television receiver to be set to the required channel. If, after having been so set, it is found that some fine tuning is necessary the `FINE UP` or `FINE DOWN` buttons are pressed which causes the `FINE` counter 7 to be actuated which in turn acts on the fine tuning circuit 56 to slightly change the frequency of two VCO 50 until the required fine tuning is obtained. The setting of the `FINE` counter 72 is then also stored in the RAM 71 when the FINE UP/DOWN buttons are released. Subsequent selection of program one without operation of the `TUNE` button 68 will automatically cause the television receiver to be set to channel 50 in accordance with the information stored in the RAM 71.

The above described arrangement is satisfactory if the channel numbers of the available television transmitters in an area are known but often this is not the case in which event the arrangement may be modified by arranging that the `FINE UP` and `FINE DOWN` buttons operate as `UP` and `DOWN` buttons on both the `FINE` counter 72 and the channel counter/buffer 64 and by arranging that the `TUNE` button is changed to a CHANNEL TUNE/FINE button. Optionally the coarse/fine button 70 may be provided which is quiescently in its `COARSE` position but may be pressed into the `FINE` position or vice versa. In this event, the CHANNEL TUNE/FINE button would be set to `CHANNEL TUNE` and the `UP` or `DOWN` button would be selected which would cause the channel counter/buffer to step `upwards` or `downwards` sequentially through each of its settings, each of these corresponding to a particular channel. When a required channel is obtained the `UP` or `DOWN` button is released and the CHANNEL TUNE/FINE button is set to `FINE` and the `UP` and `DOWN` button used to effect fine tuning as before. Again, the settings of the channel counter/buffer 64 and the `FINE` counter 72 are stored in the RAM 71 at a position allocated to the selected program number and subsequent selection of that program numbers will cause the television receiver to be returned to the pre-selected channel.
The coarse/fine button 70 may be used to initially cause the channels to be scanned sequentially at a fast rate and when in the vicinity of the channel required, cause the chanels to be scanned at a slow rate to enable the required channel to be more easily selected.
A detailed description of how frequency tuning or channel selection is effected will now be given, reference being made to FIG. 4 of the accompanying drawings, in association with the frequency diagrams of FIGS. 5 to 8. FIG. 4 depicts parts of the arrangement of FIG. 3, the various parts of which have been accorded the same reference numerals, and also the fine tuning circuit of FIG. 3 in greater detail.
As has been hereinbefore described with reference to FIG. 3, the outputs 51 from the VCO 50 in FIG. 4 are applied to a fixed divider 52 having a division ratio of ÷ 64, the output of which is applied to a ÷ 15/16 divider 54, which is normally arranged to have a division ratio of ÷ 16 but which may be set to have a division ratio of ÷ 15 by means of the control signal 55 applied to it from the fine tuning circuit 56. It is convenient to refer to this divider as D1. The output of the divider 54 is fed to the programmable variable divider 57 having a division ratio of N, which may conveniently be referred to as D2, an output 0 which is applied to the fine tuning circuit 56.

The output 0 from the programmable variable divider 57, which is afforded when the divider 57 has carried out its count of N, is applied to a 3-stage programmable shift delay 75 (which may also take the form of a two bit counter) which may conveniently be referred to as D3, and which has the capability of adding a maximum of three extra counts to the division ratio N of the variable divider 57 (D2), the number of extra counts being determined by a control input 76 applied to the shift delay 75 from the fine counter 7 (FIG. 3). When the programmable shift delay 75 starts counting, it affords an output 0' to the programmable variable divider 57 which inhibits the input applied to it from the ÷15/16 divider 54. This inhibit is maintained until the shift delay 75 has completed its count at which the inhibit signal afforded over output 0' is removed and the programmable divider 57 affords an output 0" which is applied to the phase/frequency comparator 59 in which it is compared with a reference frequency f_ref derived from the crystal controlled oscillator 60 via the fixed divider 61, the output of the comparator 59 being applied, via the active filter 62, to the VCO 50 to control its frequency.
By judicious selection of the various division ratios of the arrangement and by selecting the frequency of the crystal oscillator 60, it may be arranged that for each count of the variable divider 57 (D2) which corresponds to each output of the ÷ 15/16 divider 54 (D1), the frequency of the VCO 50 will change by 2MHz, this being achieved with the ÷ 15/16 divider being set to the division ratio of ÷ 16.
In this way selection of the VHF odd channels and UHF channels may be selected since for each of these channels, the whole number part of the VCO frequency is a even multiple of MHz. However, for VHF even channels, the whole number part of the VCO frequency is an odd multiple of MHz and means must be designed into the circuit to enable the VHF even channels to be selected. In addition it is nearly always required that a manual fine tuning capability be provided to allow for non-precise channel frequencies to be catered for. The VHF even channel selection and manual fine tuning is effected in the arrangement of FIG. 4 by making use of the fact that every count of the variable divider 57, which is effected by an output from the ÷ 15/16 divider 54 when set to a division ratio of ÷ 16 corresponds to a change in VCO frequency of 2MHz. If now, in N counts of the variable divider 57 the division ratio of the ÷ 15/16 divider 54 is set once to ÷ 15 instead of ÷ 16 then it can be shown that the VCO frequency will increase by 125KHz. Similarly, if the division ratio of the ÷ 15/16 divider 54 is set to ÷ 15, eight times in N counts, then the VCO frequency will be increased by 1MHz and if the division ratio is set to ÷ 15 times in N counts, then the VCO frequency will be increased by 1.875MHz.

It is thus arranged that in order to select VHF even channels, the division ratio of the ÷ 15/16 divider 54 is set to ÷ 15 eight times in every N counts of the variable divider 57, thereby enabling the odd multiple VCO frequencies to be selected. In order to provide a fine tuning facility it is arranged that the division ratio of the ÷ 15/16 divider 54 is set to ÷ 15 a further fifteen times in each sequence of N counts of the variable divider 57, thus affording a frequency change of 1.875 MHz, the additional counts of ÷ 15 being reduced sequentially from fifteen to zero in say 1/8 second time intervals, in order to obtain the required fine frequency change.
This is achieved in the arrangement of FIG. 4, by providing a preset ÷ 8 counter 77 which may be referred to as D4 and a 4-bit down counter 78 which may be referred to as D5 both of which are enabled by an output from the shift delay 75 and both of which are clocked by the output from the ÷ 15/16 divider 54. The ÷ 8 counter 77 is operated in accordance with VHF/UHF and ODD/EVEN control signals 79 applied to it from the channel counter/buffer 64 (FIG. 3) so that when VHF even channels are selected, the = 8 counter 77 and the 4-bit down counter 78 are connected in series, the ÷ 8 counter 77 counting first and when UHF and odd VHF channels are selected the ÷ 8 counter 77 is effectively by-passed so that only the 4-bit down counter 78 counts. The count of the 4-bit down counter may be set by means of a control input 80 applied to it from the fine counter 72 (FIG. 3) and its output is applied via a synchronising latch 81 to the control input 55 of the ÷ 15/16 divider 54 to control its division ratio.

The precise operation of the circuit arrangement of FIG. 4 may best be explained by considering a number of examples in which the VCO 50 is required to be set in accordance with a required channel number.
The frequency f_vco of the VCO 50 can be calculated from the equation: f_vco = 64. f_ref [16(N + x -A) + A.15 ] (1)

where, for UHF and odd VHF channels ##EQU1## and for even VHF channels ##EQU2## and where x = Division count of shift delay D₃. This could be any number between 0 and 3 both inclusive. A = Total division count of D₄ and D₅. This could be any number between 15 and 0, both inclusive, for UHF and odd VHF channels, any number between 23 and 8, both inclusive for even VHF channels. f_ref = 1.953 KHz
Equation 1 has been derived from the fact that D₁ initially divides by 15 A times during the total division count of D₂ and D₃ which equals (N + x), and that D₁ divides by 16 the rest of the times, (N + x - A). For a fixed value of N and x, as A changes, so does f_vco. The increment Δf_vco, which is the fine tuning step, can be calculated from equation 1 as follows: Δf_vco = 64 f_ref. = 125 KHz.
The ROM 58 (FIG. 3) has BCD coded inputs for channel numbers. Its binary outputs operate the programmable variable divider, 58, to provide the required division ratio, N.
Method of UHF and odd VHF Channel Selection
Let it be assumed that channel 50 is required to be selected, this lying in the UHF band and requiring a VCO frequency of 742.15 MHz. The requirements of operation are as follows:
1. When `TUNE` 68 (FIG. 3) is operated after setting the channel number in the digital switch 69 (FIG. 3), the frequency should be very close to 742.15MHz.
2. When fine tune UP 67 or DOWN 68 (FIG. 3) is operated, the fine tuning range should be ± 4MHz around the centre frequency of 742.15MHz in steps of 125KHz at a rate of say 1/8 sec per step.
The value of N can be calculated from equation 2 as follows; N = (742/2) -1 = 370
"tune" operation
When `TUNE` 68 (FIG. 3) is operated after setting `50` in the digital switch 69 (FIG. 3) the functions of the different stages of the system are as follows:
1. D₂ divides by N = 370
2. D₃ provides an additional count of 2. Thus x = 2
3. (1) D₅ is preset to down count from 15
(11) D₄ is ineffective
(111) total count of D₄ and D₅ i.e. A = 15.
Substituting the values of N, x and A in Equation 1 we obtain the value of f_vco given below, f_vco = 742.125 MHz (6)
This is indicated in position `a` in the frequency diagram of FIG. 5. This frequency is in fact 25KHz offset from the required frequency of 742.15 MHz but is acceptable.
Fine `UP` Tuning
Now, if any fine tuning is necessary to optimise the picture on the T.V. screen, the fine tuning `UP` control 67 (FIG. 3) is pressed. If the `UP` control remains pressed, the functions of the various stages involved now are as follows:
1. The presetting data input to D₅ changes from 15 to 0 at the rate of 8 steps per second. This changes `A` in equation 1 correspondingly. Accordingly, this means that f_vco is increasing by a step of 125KHz at the rate of 8 steps per second. When A goes to `0`, f_vco from Equation 1 becomes, f_vco = 744 MHz
This is indicated in position `b` in FIG. 5.
2. When the tuning frequency reaches `b` in FIG. 6:
(a) D₃ is increased by 1, thus x = 3.
(b) D₅ is preset to downcount from 15. Thus A = 15.
(c) Fine tuning continues as explained in paragraph 1 above, giving the end frequency of vco for A = 0 as; f_vco = 746MHz
This is indicated in position `c` in FIG. 5.
3. When the tuning frequency reaches `c` in FIG. 5:
(a) D₃ is set to zero, thus x = 0
(b) D₅ is preset to down count from 15, hence, A = 15.
(c) f_vco from Equation 1 now becomes as; f_vco = 738.125 MHz - `d` in FIG. 5,
(d) Fine tuning continues as before, making f_vco for A =0, as; f_vco = 740 MHz
This is indicated in position `e` in FIG. 5.
4. When the tuning frequency reaches `e` in FIG. 5:
(a) D₃ is set to 1, thus x = 1
(b) A = 15
(c) Fine tuning continues as before till the tuning frequency reaches position f in FIG. 5 for f_vco = 742MHz and A = 0.
From position `f` the fine tuning continues and the tuning frequency moves to position `b` and so on.

The moment the UP control is released, the fine tuning stops, D₃ stays at the value of x at that time, and D₅ stays at the value of A at that time. These values of x and A are stored in the RAM 71

(FIG. 3).
Fine `DOWN` Tuning
If the DOWN control 68 (FIG. 3) is pressed after TUNE operation for optimising the picture on the T.V. screen, the functions of the various stages involved, as long as the DOWN control remains pressed, are as follows:
1. D₃ is set to 1, thus, x = 1 and D₅ is preset to 0, thus A = 0. f_vco from Equation 1 now becomes as, f_vco = 742MHz
This is indicated in position `f` in FIG. 6.
2. When the tuning frequency reaches `f` in FIG. 6:

(a) The presetting data input to D₅ increases from 0 to 15 at the rate of 8 steps per second, increasing the value of A from 0 to 15 at the same rate. This means that f_vco is decreasing by a step of 125 KHz at the rate of 8 steps per second. The end value of f_vco for A = 15 can be calculated from equation 1, as, f_vco = 740.125MHz
(b) When this end is reached,
D₄ is set to 0, thus x = 0 and D₅ is preset to count up from 0, thus A = 0
f_vco from Equation 1 can now be written as, f_vco = 740 MHz
This is indicated in position `e` in FIG. 6.
3. Fine tuning continues as before as A increases from 0 to 15.
For x = 0 and A = 15, f_vco = 738.125 MHz. This is indicated in position `d` in FIG. 6.
4. (a) When the tuning frequency reaches position `d` (FIG. 6):
D₄ is set to 3, thus x = 3 and D₅ is preset to count up from 0, thus A = 0, hence, f_vco = 746 MHz
This is indicated in position `c` in FIG. 6.
(b) Fine tuning continues as before as A increases from 0 to 15. The tuning frequency reaches position `b` in FIG. 7, D₄ is set to 3, thus x = 2 and D₅ is preset to count up from 0, thus A = 0.
(c) From position `b` fine tuning continues and reaches position `a` at which time D₄ is set to 1, thus x = 1 and D₅ is preset to count up from 0, thus, A = 0. The fine `DOWN` tuning is then repeated.
As in the case of `UP` fine control, the moment the DOWN control is released, the fine tuning stops, D₃ stays at the value of x at that time, and D₅ stays at the value of A at that time. These values of x and A are stored in the RAM 71 (FIG. 3).
Method of Frequency Tuning for even VHF Channels
In order to explain the method of frequency tuning for even VHF channels, let us take channel `6` as an example. The corresponding VCO frequency is 221.15MHz. The value of N can be calculated from equation 3 as follows: N = 221 - 1/2 = 110
tune Operation
When `TUNE` 68 (FIG. 3) is operated after setting `6` in the digital switch 69, (FIG. 3), the functions of the different stages of the system are as follows:
1. D₂ divides by N = 110
2. d₃ provides an additional count of 2. Thus x = 2.
3. (1) D₅ is preset to down count from 15. (11) D₄ is preset to down count from 8. (111) Total count of D₄ and D₅ i.e. A = 23.
Substituting the value of N, x and A in Equation 1, we obtain the value of f_vco : f_vco = 221.125MHz
This frequency is offset by 25KHz from the required frequency of 221.15MHz but is acceptable.
The operation of the `Fine UP` tuning and `Fine DOWN` tuning is similar to that described above for UHF and odd VHF channel selection except that in both cases counter D₄ is set to count down from 8.
This results in a `Fine UP` frequency diagram as shown in FIG. 7 and a `Fine DOWN` frequency diagram as shown in FIG. 8.
It is especially envisaged that the digital synthesis frequency control system of FIG. 3 be implemented in integrated circuit form in which case it is envisaged that the following integrated circuit packages be used:
IC₁ - A bipolar, 14 pin dual-in-line (DIL) package incorporating the ÷ 64 divider 52.
IC₂ - A bipolar, 14 pin DIL package incorporating the - 15/16 divider 54, the phase/frequency comparator 59, part of the fixed divider 61 and the crystal oscillator 60.
IC₃ - A MOS, 16 pin DIL package incorporating the programmable variable divider 57, the ROM 58 and fine tuning circuit 56, part of the fixed divider 61.
IC₄ - A MNOS, 24 pin DIL package incorporating the RAM 71, the program address counter 73, the fine counter 72 and the channel counter/buffer 64.
IC₅ (optional) incorporating the active filter 62, and band supply switching circuit for the tuner.

In the arrangement of FIG. 3, in order to facilitate programming of the ROM 58 and the RAM 71 with the minimum number of interconnecting lines, conventional multiplexing techniques may be used and additionally the RAM 71 may be arranged to operate in accordance with a read/erase/write cycle which is generated whenever a change in program number is detected or when the `TUNE` or FINE UP/DOWN controls are operated.
Conveniently also, it may be arranged that a `MUTE` output be generated which operates when a channel is changed to block the T.V. sound for a period say, of 200mS.
Although described as being applied to television receivers, the frequency synthesis tuning system described may have application in other forms of communications equipment such as radio receivers, radio transmitters, transmitter/receivers etc., and although `channel` tuning has been extensively considered, in other applications, simple frequency tuning may be used.

An electronically controllable tuning device includes a voltage controlled oscillator adapted to have an oscillation frequency controlled by a control voltage and simultaneously generate a fundamental wave of a predetermined frequency, a programmable frequency divider for dividing the fundamental wave frequency at a frequency division ratio corresponding to the control of a channel selection means and a phase locked loop adapted to compare the fundamental wave phase with the phase of the output of the programmable divider to generate a comparison output and feeding the comparison output back to the voltage controlled oscillator to control the output frequency of the voltage controlled oscillator. The tuning device further includes means for supplying as a local oscillation signal to an intermediate frequency generating mixer one of higher harmonic wave components of the fundamental wave.

A digital phase control circuit which includes a controllable oscillator, a programmable divider coupled to the oscillator, a reference frequency source, a phase discriminator coupled to the outputs of the programmable divider and reference frequency source and means coupling the output of the phase discriminator to a control input of the oscillator. In addition to these components, an auxiliary circuit is provided which has its input coupled to the output of the phase discriminator and first and second outputs coupled to the reference frequency source and the programmable divider. The auxiliary circuit generates a first signal at the input of the reference frequency source when the phase difference between the signals at the outputs of the programmable divider and the reference frequency source is in one direction and a second signal at the second input of the programmable divider when the phase difference is in the opposite direction.

1. In a digital phase control circuit including a controllable oscillator having a control input; a programmable first divider having first and second inputs, said first input being coupled to the output of said oscillator; a reference frequency source comprising a second divider having an input; a phase discriminator having first and second inputs coupled to the outputs of said programmable first divider and said second divider respectively, said phase discriminator further having output means; and means coupling the output means of said phase discriminator to the control input of said controllable oscillator, the frequency of said oscillator being controlled in a direction determined by the direction of the phase deviation between the signals applied to the first and second inputs of said phase discriminator and compared therein; the improvement comprising:
an auxiliary circuit having input means coupled to the output means of said phase discriminator, a first output coupled to the input of said second divider comprising said reference frequency source and a second output coupled to the second input of said programmable first divider, said auxiliary circuit generating a first synchronizing signal at the input of said second divider when the phase difference between the signals at the ou

tputs of said programmable first divider and said second divider is in one direction and generating a second synchronizing signal at the second input of said programmable first divider when the phase difference between the signals at the outputs of said programmable first divider and said second divider is in the opposite direction thereby setting either said programmable first divider or said second divider, respectively, to a predetermined initial phase position, the divider set to said predetermined initial phase position being maintained in said position until the other divider reaches its predetermined initial phase position.

2. The phase control circuit defined by claim 1 wherein said auxiliary circuit comprises a clock pulse generator for generating a signal at a predetermined interval after generation of a signal at the output of said phase discriminator, an auxiliary circuit output signal being generated at the input of said second divider or at the input of said programmable first divider only if the signal at the output of said phase discriminator is generated for an interval longer than said predetermined interval. 3. The phase control circuit defined by claim 2 wherein the output of said phase discriminator and the output of said auxiliary circuit each comprise a plurality of sequential pulses having a leading edge and a trailing edge, the leading edges of the pulses at the output of said auxiliary circuit occurring later than the leading edges of the corresponding pulses at the output of said phase discriminator, and the trailing edges of the corresponding pulses at both the output of the auxiliary circuit and the output of the phase discriminator coinciding. 4. The phase control circuit defined by claim 2 wherein said clock pulse generator receives counting pulses at a constant frequency, means are provided for releasing said clock pulse generator to count said counting pulses from its predetermined initial position when a signal is generated at the output of said phase discriminator and means are provided for coupling the signal at the output of said clock pulse generator to a disable input thereof to stop said counter. 5. A phase control circuit as defined by claim 4 wherein the output means of said phase discriminator comprises a first output at which pulses appear when the frequency of said oscillator is increasing and a second output at which pulses appear when the frequency of said oscillator is decreasing, and wherein said auxiliary circuit further includes a first gating circuit having first and second inputs coupled to the first and second outputs of said phase discriminator and an output coupled to a reset terminal of said clock pulse generator, second and third gating circuits for coupling the output of said clock pulse generator to the input of said second divider and to the second input of said programmable first divider, respectively, and fourth and fifth gating circuits coupling the first and second outputs of said

phase discriminator to the inputs of said second and third gating circuits.

Description:

BACKGROUND OF THE INVENTION
This invention relates to digital phase control circuits and, in particular, to a phase control circuit which has improved transient response during its readjustment mode.
Digital phase control circuits are known which include a controllable oscillator, a programmable divider, a reference frequency source, a phase discriminator and a lowpass filter or integrating circuit. The output signal of the controllable oscillator is fed to one input of the phase discriminator via the programmable divider and the other input of the phase discriminator receives a signal from the reference frequency source. The low-pass filter circuit derives a control signal from the output of the phase discriminator so as to control the controllable oscillator.
The signals at the output of the phase discriminator have rectangular pulses. The average d.c. voltage of the rectangular pulses is obtained by means of the series-connected filter circuit which provides a setting voltage for the controllable oscillator. The circuit regulates itself in such a way that, in the steady-state, the signals applied to the phase discriminator coincide in frequency and phase.
In order to prevent excessive overshoot of the controllable oscillator, a minimum time constant is required in the filter circuit which may be designed, for example, as an active integrator. This results in a relatively long time constant for the entire system which can be detrimental in many cases. A long time constant may also increase the tendency toward resonance of the entire circuit.
It is an object of the present invention to provide a phase control circuit which is substantially improved with respect to its transient response during readjustment.
SUMMARY OF THE INVENTION
The present invention comprises a digital phase control circuit which includes a controllable oscillator, a programmable divider coupled to the oscillator, a reference frequency source, a phase discriminator coupled to the outputs of the programmable divider and reference frequency source and means coupling the output of the phase discriminator to a control input of the oscillator. In addition to these components, an auxiliary circuit is provided which has its input coupled to the output of the phase discriminator and first and second outputs coupled to the reference frequency source and the programmable divider. The auxiliary circuit generates a first signal at the input of the reference frequency source when the phase difference between the signals at the outputs of the programmable divider and the reference frequency source are in one direction and a second signal at the second input of the programmable divider when the phase difference is in the opposite direction.

Thus, in the present invention, an auxiliary circuit is provided in addition to the components of the prior art phase control circuit. This auxiliary circuit acts selectively on the programmable divider or the reference frequency source to reset the programmable divider or the reference frequency source, respectively, to a predetermined initial phase position at specific points in time. This initiates a comparison which begins at the predetermined initial phase position of the circuit. The comparison process beginning with the return of the predetermined initial position of the programmable divider or of the reference frequency source is repeated continuously. The invention operates such that, during every comparison cycle, a genuine phase or frequency comparison is effected between the two signals present at the phase discriminator. Each time at the start of the comparison cycle, the phase difference is defined as "zero." Therefore, the phase of frequency deviation present at the end of the comparison cycle between the two signals present at the phase discriminator is an exact measure of the phase deviation.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 shows a phase control circuit in accordance with the present invention.
FIGS. 2 and 3 show the output signals of a prior art phase control circuit for both directions of adjustment.
FIG. 4 is a pulse diagram of the signals in a phase control circuit including the features of the present invention for one direction of adjustment.
FIG. 5 shows signals corresponding to FIG. 4 for the other direction of adjustment.
FIG. 6 is a waveform diagram comparing the operation of the circuit with and without the auxiliary circuit of FIG. 1.
FIG. 7 shows an embodiment of the auxiliary circuit of FIG. 1.
FIG. 8 shows a television tuner constructed in accordance with the invention.
DESCRIPTION OF THE PREFERRED EMBODIMENTS
FIG. 1 is a block diagram showing a phase adjustment circuit which includes a voltage controllable oscillator 1 (VCO), a programmable divider 2, a reference source 4, a phase discriminator 3, a coupling circuit 6 and a lowpass filter and amplifier circuit 5. These components are combined in a known manner to form a control loop. The programmable divider can be set to a selected dividing ratio which determines the initial frequency of the controllable oscillator 1. The programmable divider may also have fixed predividers (not shown) connected between it and the oscillator 1. The reference frequency source 4 includes a quartz oscillator 4a and a series-connected frequency divider 4b having, for example, a fixed dividing ratio. The output signal of the divider 4b is fed to the phase discriminator 3 to provide a reference signal.
Before describing auxiliary circuit 7 of FIG. 1, the operation of the prior art phase control circuit will be explained with the aid of FIGS. 2 and 3; that is, the circuit shown in FIG. 1 without the auxiliary circuit 7 will be described.
The output signal of the programmable divider 2 is shown at the top of FIG. 2. After each passage through the programmable divider 2, a negative pulse 8 appears at the output of this divider and is fed to the phase discriminator 3. In the second line of FIG. 2, the reference signal is shown which is fed to the other input of the phase discriminator 3.
The phase discriminator 3 has an output 9 at which control pulses appear when the oscillator 1 is adjusted in the upward direction; that is, toward a higher frequency, and an output 10 at which pulses appear for an adjustment in the downward or lower frequency direction. The signals at outputs 9 and 10 are illustrated in the third and fourth lines of FIG. 2. The last line shows a so-called "tristate signal" which is obtained at the output of coupling circuit 6 and which is fed to the lowpass filter 5. The diagram shown in FIG. 2 is based on a so-called Type 4 phase discriminator which is described at page 19 of the book by Horst Geschwinde "Einfuhrung in die PLL-Technik" (Introduction to the PLL Technique), published by Vieweg. Each of the outputs 9 and 10 of the phase discriminator 3 has an associated output in a bistable circuit comprising the phase discriminator. In the illustrated case, the phase discrimin

ator 3 is designed so that the bistable circuits respond to the negative-going edge of the pulse 8 coming from the programmed divider 2. If there is a phase difference between the signals applied to the phase discriminator 3, pulses appear either at the "upward" output 9 or at the "downward" output 10, depending on the direction of the deviation. The bistable circuit associated with the "upward" output can be set by the edges 11 of the reference signal and reset by the pulses 8 coming from tne programmable divider 2. Conversely, the bistable circuit in the phase discriminator associated with the "downward" output can be set exactly oppositely by the pulses 8 coming from the programmable divider 2 and reset by the edges 11 of the reference signal.
FIG. 2 shows the signals for the case where at time t ₀ the dividing ratio of the programmable divider 2 is switched to a higher value. Consequently, the frequency of the oscillator 1 is adjusted toward higher frequencies, which can be seen in FIG. 2 in that the pulses 8 at the output of the programmable divider jump toward a lower frequency after a new dividing ratio has been set into the programmable divider and thereafter are brought closer together by the adjustment process. Thus, at an interval indicated by the bracket 12, the frequency of the pulses coincides with the frequency of the reference signals but there still exists a phase deviation between the signals. This deviation can be overcome by temporarily increasing the frequency of the signal of oscillator 1 beyond the desired value. For that reason, the pulses at the "upward" output 9 continue to be generated. The prior art circuit thus exhibits an overshoot which is required by the system.
FIG. 3 is a pulse diagram in which the dividing ratio of the programmable divider 2 of FIG. 1 is set to a lower value at time t ₀ . The time at which coincidence with respect to frequency exists for the signals being compared in the phase discriminator is identified by a bracket 13. The operation of the prior art system under these conditions is analagous to the previously described operation under the conditions of FIG. 2.
The auxiliary circuit 7 of FIG. 1 resets the programmable divider 2 or the reference frequency source 4, to its initial position at specific points in time. The auxiliary circuit 7 is controlled by the signals at outputs 9 and 10 of the phase discriminator 3.
FIGS. 4 and 5 show how the auxiliary circuit of FIG. 1 controls the programmable divider 2 and the reference frequency source 4. FIG. 4 illustrates the operation of the circuit including auxiliary circuit 7 for a change in frequency corresponding to FIG. 2 wherein the oscillator frequency increases; that is, changes in the upward direction. It is assumed that the circuit has the same components as the circuits on which FIGS. 2 and 3 are based but that it includes in addition the auxiliary circuit 7.
The synchronizing signal A shown in the last line of FIG. 4 is generated by the auxiliary circuit 7. The synchronizing signal A includes pulses 14 and 17 which are fed to the reset input R of the reference frequency source. At time t ₀ , a new dividing ratio is fed into the programmable divider 2 and at time t ₁ the oscillator begins to increase its frequency so that the pulses 8 come closer together again. At time t ₁ , the pulse 15 is initiated at the "upward" output 9 of the phase discriminator since the edge 11 of the reference signal appears earlier than the next pulse 8 from the programmable divider. The pulse 14 of the synchronizing signal A is derived from the pulse 15.
Pulse 14 is used initially to reset the divider 4b of the reference frequency source 4 which does not generate reference signal pulses as long as pulse 14 is present. At time t ₂ , the pulse 15 and the output pulse 14 derived from pulse 15 are terminated. Thus, at time t ₂ , the divider of the frequency source 4 is restarted from its basic position.
The frequency divider 4b may be a twelve bit divider consisting, for example, of two type CD4520 integrated circuits manufactured by RCA. This known divider is set to its basic position by a logical reset signal.
After a period T ₁ of the reference signal, at time t ₃ , a new control pulse 16 starts at the output 9 of the phase discriminator 3 since the edge 11 again appears earlier than the next pulse 8 from the programmable divider. A synchronizing pulse 17 is again generated which sets back the divider 4b of the reference frequency source 4 and stops it.
The adjustment is effected in the above-described manner until at time t ₄ the signals being compared in the phase discriminator 3 coincide with respect to frequency and phase. As can be seen from a comparison of FIG. 4 with FIG. 2, this state is attained much faster than in the circuit without the auxiliary circuit 7. The control pulse terminated each time at the end of the comparison cycle provides a precise indication of the frequency deviation of the two signals applied to the phase discriminator, which is not the case in FIGS. 2 and 3.
Upon a change in the frequency of the oscillator in the opposite direction (downward), a synchronizing signal B is generated in the auxiliary circuit 7, as shown in FIG. 5, from the signal at "downward" output 10 of phase discriminator 3. With this synchronizing signal, the programmable divider 2 is controlled rather than the reference source 4 as shown in FIG. 4.
At time t ₀ , as in FIG. 3, the dividing ratio of the programmable divider is reduced to correspond to the reduction in frequency of the oscillator 1. This initially effects an increase in the output frequency of the controllable oscillator. The synchronizing signal B is derived from the pulses 18 and 19 at the "downward" output 10 of the discriminator 3. This signal is fed to the load input L of the programmable divider 2. At time t ₁ a pulse 8 from the programmable divider starts the pulse 18 at the output 10. The programmable divider is set by the synchronizing pulse 20 derived from pulse 18 and is kept in the initial position until time t ₂ . At time t ₂ , the edge 11 of the reference signal terminates the pulse 18. At the same time, the programmable divider begins to operate again. At t ₃ , the pulse 19 at the output 10 is started because the next pulse 8 appears earlier than the next negative-going edge 11 of the reference signal. The synchronizing pulse 21 derived from pulse 19 again sets the programmable divider 2 and holds it in its initial position. At time t ₄ the programmable divider 2 is released again and

the process continues.
The programmable divider 2 is a known component. For example, four type 74 LS169 integrated circuits manufactured by National Semiconductor may be used in series as a fourteen bit presettable down counter.
As is evident from the explanation of FIGS. 4 and 5, the reference frequency source 4 is controlled by the auxiliary circuit in one direction and the programmable divider 2, located between the oscillator 1 and the discriminator 3, in the other direction. The influenced circuit is controlled in accordance with the signals appearing at the output of the discriminator 3, which correspond to the phase or frequency error, so that at the beginning of each comparison cycle the phase error is assumed to be zero. In this way, adjustment of the circuit beyond the desired value is avoided. Thus, the described phase control circuit, including the auxiliary circuit 7, has very short transient periods.
FIGS. 4 and 5 show that the rising edge of the synchronizing signals A and B are shifted by the time τ with respect to the associated output signal of discriminator 3. By providing a predetermined delay period τ, the auxiliary circuit 7 is made effective for only a certain minimum width of the pulses of the output signal from discriminator 3. If the pulses at outputs 9 and 10 of the discriminator 3 fall below this minimum width, no synchronizing signals A or B are generated any longer. The circuit then operates in the customary manner, as described in connection with FIGS. 2 and 3. The delay period is advantageously selected to be greater than one period of the frequency of the reference oscillator so that the auxiliary circuit will not respond to the non-transient state.
If such a delay period is provided, the control circuit will be brought into a state, by means of the auxiliary circuit 7 provided to avoid overshooting, in which the signals present at the phase discriminator coincide with respect to frequency as well as phase. Then the auxiliary circuit 7 is no longer effective.
FIG. 6 shows the result obtained with the auxiliary circuit 7 by illustrating the control signal for oscillator 1. The top portion of FIG. 6 shows the signal obtained when an auxiliary circuit was used which operates in the manner described above under conditions of increasing frequency. The signal at the bottom of FIG. 6 was obtained when the same circuit was used without auxiliary circuit 7. It can be seen that the auxiliary circuit 7 resulted in a significant improvement in the transient behavior.
FIG. 7 shows an embodiment of the auxiliary circuit 7 of FIG. 1. The auxiliary circuit includes a counter 22 and logic gates 23 to 27, the counter generating the fixed delay period λ. A typical counter which may be used for this purpose is the type CD4520 manufactured by RCA. The signals at the outputs 9 and 10 of the phase discriminator 3 are fed through an AND gate 23 to the reset input of the counter 22. The clock pulse input of the counter 22 receives, via an input terminal 30, counting pulses at a frequency of, for example, 1 MHz. If no pulse arrives from the outputs 9 and 10 of the phase discriminator, the reset input receives a reset signal and the clock pulses at the clock pulse input of the counter 22 are ineffective. The output Q _n of the n ^th stage of the counter 22 is connected with a disable input D of the counter. That is, if the counter state Q _n is reached, the counter stops itself. The synchronizing signals A and B are also derived from output Q _n via gates 25 and 27. A signal is fed via inverters 24 and 26, to the gates 25 and 27 which act as gating circuits so as to indicate which one of the two gates 25 and 27 is to be enabled for the signal coming from output Q _n . Gates 25 and 27 therefore control whether the programmable divider 2 or the reference frequency source 4 of FIG. 1 receives a synchronizing signal.
With reference to FIGS. 4 and

5, the circuit in FIG. 7 operates as follows: The pulse 15 in FIG. 4 is present at the input 9 and enables gate 27 via inverter 26 to provide a synchronizing signal. However, no pulse appears at output 29 because the output Q _n of the counter 22 does not furnish a signal. Pulse 15 cancels the reset signal of counter 22 and counting pulses from input 30 are counted into the counter. After a delay period λ a signal jump appears at the output Q _n , in accordance with the clock pulse frequency and the number of stages in the counter, which stops the counter 22 through the disable input. The change of signals at the output Q _n also changes the logic state at the upper input of gate 27 so that the pulse 14 of FIG. 4 is formed. As soon as pulse 15 in FIG. 4 is completed, the AND condition for gate 27 is no longer met so that the pulse 14 is terminated simultaneously with pulse 15. The termination of pulse 15 causes the counter 22 to be reset to its starting position and held in that position.
When there is a pulse at input 10 of the circuit of FIG. 7, the circuit operates in a corresponding manner with the difference that gate 25 is enabled instead of gate 27. In this case, the synchronizing signal B is formed at output 28 and used to control the programmable divider 2. By selecting the frequency of the counting clock pulse at the input 30 it is possible to preselect the delay period λ.
It is also possible to obtain the delay period λ by means of circuit elements which operate in a different manner. For example, the delay of a plurality of series-connected gates (e.g., inverters) can be utilized.
FIG. 8 shows the complete circuit diagram of a tuner embodying the features of the present invention. At the top left of FIG. 1, block 31 is a tuner including the VCO 1. The signal from the VCO 1 travels through a predivider 32 included in the tuner to the programmable divider 2. At the beginning of a dividing cycle, the programmable divider is set to the preprogrammed value via a "load" input L and is then pulsed until it reaches the value zero. When it reaches the value zero, the load input receives a new charging pulse via a gate 33 with which the starting position of the programmable divider 2 is reset. The charging pulse of the programmable divider is fed to the input 35 of a phase discriminator 3 which is shown in dashed lines in FIG. 8. The other input 34 of the phase discriminator 3 receives a signal from the reference divider 4. The phase discriminator 3 which operates in a known manner, includes a plurality of gates.
At the lower right of FIG. 8, the coupling circuit 6 is shown. The auxiliary circuit 7 which has already been described in connection with FIG. 7 is shown in outline in FIG. 8. The synchronizing signal A is fed to the reset input of the reference divider 4 and the synchronizing signal B is fed to gate 33.
The auxiliary circuit 7 is also connected to a lock indicator which includes a counter 36, an AND gate 37 and an inverter 38. The counter 36 is set back with each synchronizing signal A and B via a reset input. Clock pulses at a relatively low frequency are fed to the clock pulse input of the counter 36 via an AND gate 37. These clock pulses are obtained from the output of the reference divider 4. From an output Q _p , a lock signal is derived. This lock signal appears only if no synchronizing signal appears for a relatively long period of time. The supply of clock pulses through gate 37 is blocked as soon as the lock signal appears because of the feedback of the lock signal via an inverter 38. The lock signal remains in effect until a new synchronizing signal is formed.
The lower left of FIG. 8 shows the filter circuit 5 which includes an operational amplifier 39.
It will be understood that the above description of the present invention is susceptible to various modifications, changes

and adaptations, and the same are intended to be comprehended within the meaning and range of equivalents of the appended claims.