The chassis PHILCO TX10 (CHASSIS THORN TX10) is realized on 2 boards divided by Power part and signal part.
The THORN TX10 is designed to drive 20, 22 and 26in. tubes of the 30AX type and the similar thin neck RCA S4 type.
There's but one "tolerance" control to match the chassis to the scan yoke. As with the TX9, simplicity is the keynote of the design and the basic chassis can be used with a variety of screen sizes and consumer options - the same chassis can be removed from a basic 22in. set and without any modification fitted into a 26in. remote controlled set with teletext and tone controls.
This versatility is a characteristic of the chassis, with its ability to operate with a simple or sophisticated remote control system and sweep tuning, drive an external loudspeaker, provide headphone or hi-fi outputs, incorporate bass and treble controls and accept video inputs.
The latter facility embraces many things - teletext, viewdata, TV games inputs, signals from a camera and use as a data display, for example as a VDU with a home computer.
To these ends a video/audio input/output socket is fitted and the video bandwidth is no less than 10MHz.
This is far beyond the 5.5MHz required for present TV transmissions, giving really crisp data displays. In fact we suspect that in the smaller screen sizes at least the c.r.t. phosphor "dot" size and the 625 -line standard are the limiting factors determining the resolution.
The power consumption has been kept low - 70W at zero beam current.
This is 28W more than the THORN TX9, an extra 20W being required for 110° scanning plus 8W for peripheral circuitry. While the signal stages and the field timebase are for the most part similar to those used in the TX9, the power supply and line timebase are totally different and the RGB output stages are of the class AB type. Apart from the i.f. daughter board, the chassis is to all intents and purposes a single board design.
The board is in two separate sections (signals and power supply/timebases) in the final chassis assembly, but is cut into two only at a late stage of production.
The two sections of the board are then mounted in a hinged steel frame, which results in a slim chassis with easy access for servicing. The metal chassis is isolated from the mains, facilitating the externnections previously mentioned, all the mains -live circuitry being protected by red plastic covers.
Signal Processing:
There is some complication in the TX10's front end due to the provision of sockets for sweep tuning and remote control. Otherwise the varicap tuner plus i.f. preamplifier/SAWF/ PHILIPS TDA2540 i.f. amplifier/demodulator i.c. arrangement follows the pattern set by the TX9. The sound department is also the same, with a single TDA1035T i.c. The loudspeaker is an 81 type however. Let's hope that the isolated chassis doesn't result in too many liberties being taken with the external speaker wires or we'll need to stock up on these!The single -chip decoder used is the PHILIPS TDA3560, as in later production versions of the THORN TX9 (earlier production used the quite different NEC uPC1365C). The PHILIPS TDA3560 does not need an external chroma delay line driver stage and operates with an 8.8MHz crystal. As a result of the latter feature, U and V reference signals with the correct phases for demodulation are obtained automatically and no adjustments in this part of the circuit are required. The most important point about the
PHILIPS TDA3560 however is its ability to accept and handle external video input signals. A blanking input is provided, along with the RGB input pins, so that any size or shape of black hole can be inserted in the picture and filled with characters or graphics from an external source. Alternatively the data can be superimposed on the picture, the blanking input then giving a crisper result than would be obtained by simply mixing the data and video signals within the chip. This arrangement also offers versatility in data or graphics presentation, for example the ability to surround characters with white or black edges. The RGB output stages are also worth mentioning. They are mounted on the c.r.t. base panel to reduce stray capacitance, and consist of three three -transistor configurations - a cascode pair plus an emitter -follower to improve the h.f. performance. The result is a bandwidth of 10MHz with a low current consumption.
Timebases:
The field timebase is similar to the THORN TX9, in that most of the circuitry is within a single i.c., a TDA1044 this time instead of a SGS TDA1170S, but there's an external output stage to provide the additional deflection power required for 110° deflection. The output stage (see Fig. 1) looks rather basic, and at first sight quite impractical since the bases of the output transistors are strapped together - you'd expect crossover distortion from this arrangement! The key to this however is R777, which feeds the scan coils directly from the chip during the part of the field scan (about the centre) when both output transistors (TR772/3) are non- conductive. A further external transistor (TR771) boosts the supply to the output stage during the flyback period., This works as follows. During the forward scan D771 is conductive and the positive plate of C781 is at 26V. When the flyback occurs, the flyback booster circuit in IC771 feeds a positive -going pulse to the base of the emitter - follower TR771 which switches on. The 26V developed across R786 increases the voltage on both plates of C781 by the same amount, the positive plate rising to 52V. D771 cuts off, and the supply to the external (TR772/3) and internal (within IC771) output stages is thus doubled. C775 and the network R778/C776 are included to prevent instability. The line processor i.c. is a PHILIPS TDA2576. In addition to the expected sync separator, flywheel line sync and line generator circuits, this i.c. produces the sandcastle pulse required for the decoder i.c. and incorporates a clever teletext blanking circuit. The line oscillator runs at twice the normal speed, so that division of the clock frequency (31.250kHz) by 625, plus a triggering input from the field sync, enables a precisely timed teletext blanking pulse to be generated by counting to lines 21/334. This happens only in the presence, recognised by the chip, of a full -specification broadcast field sync pulse train - so you won't loose the top of your tennis game or camera picture. The teletext blanking waveform emerging from pin 1 of the chip is added to the sandcastle pulse fed to the decoder. The TX10's line output stage is simplicity itself. Shorn of the responsibility for generating the e.h.t. and most of the other supplies (the chopper circuit provides the e.h.t.), there's simply a BU208B output transistor, a small transformer, a flyback tuning capacitor, scan -correction capacitor, the scan coils and very little else. The line output transformer in fact consists of a small choke, with a secondary winding that provides 60V and -60V pulses. Since harmonic tuning of the line output transformer is no longer necessary (this is required only when there's an e.h.t. overwinding to complicate matters), the usual EW diode modulator circuit can be dispensed with. Instead, as in the 4000 chassis circuit described last month, an EW modulator transistor is connected in series with the line output transistor - between its emitter and chassis. The EW modulator transistor is a Darlington type (BD677) whose base bias is controlled by the width potentiometer. Whenever the line scan and the e.h.t. are provided by different stages, there's the risk of danger to the c.r.t. screen should the line scan fail. To prevent this, the c.r.t.'s first anode supply is obtained from a rectifier which is fed from the junction of the scan coils and the scan -correction capacitor.Power Supply Circuit: (CHASSIS THORN TX10)
In many ways, power supply circuit design has come round full circle with the TX10. With the power supply providing the e.h.t., an isolated chassis and a very simple line output stage, the basic arrangement is just like that used in the 1938 EMI TV ! The control operations in the TX10 are provided by a PHILIPS TDA2582 chip - the only chips in the EMI set occurred if you dropped the chassis on the rectifier valve and smashed it .. . The incoming mains supply is fed to a bridge rectifier (D701) which charges its reservoir capacitor C708 to some 320V. This is applied to the collector of the TFK BU208B chopper transistor TR701 (see Fig. 2). A small mains transformer (T702) provides a start-up supply, the supply for the chopper driver transistor, and energy for the remote control receiver (if fitted). The PHILIPS TDA2582 contains a 15.625kHz oscillator which is synchronised to the line oscillator. The output from this passes via a pulse -width modulator stage within the i.c. to the chopper driver which switches the chopper transistor on and off.The pulse -width modulator varies the mark -space ratio of the chopper transistor's drive waveform, i.e. the on and off times of the chopper, thus regulating the supplies obtained from the chopper transformer T705. These include the e.h.t. and a 150V line for the line output stage. Feedback from the 150V line to the PHILIPS TDA2582 controls the action of the pulse -width modulator, i.e. the regulation. The i.c. also contains slow - start and comprehensive protection circuitry - the latter monitors the chopper current (the ripple flowing via T703), the h.t. and e.h.t. voltages (the latter indirectly) and the beam current. Apart from the first anode and start-up supplies, the chopper transformer T705 provides all the supply lines in the TX10 - the e.h.t. comes from a diode -split secondary. When the chopper transistor switches off, a "line flyback" pulse is produced. The e.h.t. and the 205V (for the RGB output stages) supplies are obtained by "flyback" rectification, the other supplies being produced by rectifying the "scan" part of the waveform in the chopper transformer in order to achieve good regulation. One of the secondary windings on the chopper transformer provides the drive to the line output transistor. The operation of the chopper itself is new and worth going into in greater detail. Apart from the chopper transistor TR701 and transformer T705, the components involved are diodes D702/3/4, capacitors C711/2 and coil L702. When TR701 is switched on, current flows via L702 and the primary winding of T705. When TR701 is switched off, the magnetic fields established around the two windings collapse. C712 tunes the primary winding of T705 to provide the "flyback" pulse. At the end of the half cycle of oscillation, D704 conducts, damping the circuit. The action is that of an efficiency diode, C711 being charged by the linear decay of current. C711 is also charged during the chopper transistor's off period by the energy decay in L702, D703 being on during the whole of the chopper transistor's off period. When TR701 switches on again, D704 and D703 switch off (unless the mains voltage is low, when D704 will remain on briefly). D704 will also be conductive during the slow - start period, before C711 has fully charged. D704 switches off when the charge across C711 is such that its cathode is positive with respect to its anode when TR701 switches on. Now the charge developed across C711 is proportional to the chopper transistor's on/off time, increasing when thetransistor is on for a longer time. The result of this is that D702 conducts, feeding the surplus energy in C711 back into the supply to improve the efficiency of the circuit. . This all adds up to a very efficient power supply, with an unusually large number of energy stores - C708, C711, L702, T705 and the reservoir capacitors associated with T705's secondary windings. Mains isolation is provided by no fewer than four transformers (T702/3/4/5) plus the network R701/C701, all of which have to comply with BEAB requirements.
Such is the standard of excellence amongst current TV receiver designs that it's difficult to make any really significant comparisons between the THORN TX 10 and its competitors. The picture quality is excellent - but then so is that with all current commercial designs. Like the THORN TX9, the e.h.t. regulation, or more strictly the picture size/brightness performance, is very good - but so is everyone else's!The cabinet and much of the stand is of plastic material - as again are most contemporary sets. THIS model did not incorporate teletext or viewdata, which was a pity since this would have brought out some of the best features of the design.
On test card an excellent display was obtained, with good geometry and the teletext truly blanked. Sound was satisfactory from the necessarily small loudspeaker. For a cost-efficient (that's what we call it nowadays!) design, the performance is very acceptable and comparable with anything the opposition (even the expensive Danish and oriental opposition) can offer. The chassis layout is delightfully clean and easy to get at - none of those myriads of plug-in modules that continental setmakers seem to like. Ah, you may say, but mightn't this make field servicing more awkward, since chunks of circuitry can't be substituted? Not really, since the straightforward circuitry employed means that fault-finding should prove to be relatively simple. The engineering elegance of a neat layout lies in the simplified production procedures.
PHILCO TX927 COLOR "ANTRANCITE" CHASSIS TX10 (CHASSIS THORN TX10) AMBIENT LIGHT RESPONSIVE CONTROL OF BRIGHTNESS, CONTRAST AND COLOR SATURATION Gain control arrangement useful in a television signal processing systemIn a color television receiver, first and second amplifiers are respectively included in the luminance and chrominance channels to permit control of contrast and saturation. The amplifiers have gain versus control voltage characteristics including linear portions extrapolated to cut off at predetermined voltages which may or may not be the same. A first potentiometer is coupled between a source of fixed voltage equal to the extrapolated cut off voltage of the first amplifier and a gain controlling voltage source. The gain controlling voltage may be produced by a circuit including an element responsive to ambient light. The wiper of the first potentiometer is coupled to the first amplifier to couple a voltage developed at a predetermined point of the first potentiometer to the first amplifier to control its gain. A second potentiometer is coupled between a source of voltage equal to the extrapolated cut off voltage of the second amplifier and the gain controlling voltage source to receive a portion of the gain controlling voltage in accordance with the ratio of the extrapolated cut off voltages of the first and second amplifiers. The wiper of the second potentiometer is coupled to the second amplifier to couple a voltage developed at a predetermined point of the second potentiometer to the second amplifier to control its gain. In this manner, the contrast of the receiver may be varied over a relatively wide range while saturation is maintained substantially constant.
1. In a color television signal processing system of the type including luminance and chrominance signal processing channels, apparatus comprising:
first and second amplifiers respectively included in said luminance and chrominance channels, said amplifiers having gain versus control voltage characteristics including linear portions extrapolated to cut-off at predetermined voltages which may or may not be the same voltage;
a gain controlling voltage source;
means for coupling said gain controlling voltage to said first amplifier to control its gain;
potentiometer means coupled between a fixed voltage substantially equal to the extrapolated cut-off voltage of said second amplifier and to said gain controlling voltage source to recieve a portion of said gain controlling voltage in accordance with the ratio of the extrapolated cut-off voltages of said first and second amplifiers; and
means for coupling a voltage developed at a predetermined point on said potentiometer means to said second amplifier to control its gain.
2. The apparatus recited in claim 1 wherein said means for coupling said gain controlling voltage to said first amplifier includes another potentiometer coupled between a source of fixed voltage substantially equal to the extrapolated cut-off voltage of said first amplifier and said gain controlling voltage source. 3. In a color television signal processing system of the type including luminance and chrominance signal processing channels, apparatus comprising:
first and second amplifiers respectively included in said luminance and chrominance channels, said amplifiers having gain control voltage characteristics including linear portions extrapolated to cut-off at substantially the same predetermined voltage;
a source of gain controlling voltage; and
means for coupling said gain controlling voltage to said first and second amplifiers.
4. Apparatus comprising:
first variable gain amplifying means for amplifying a first signal in response to a first DC control signal, said first amplifying means having a first gain versus DC control voltage characteristic including a linear region, said linear region having a gain substantially equal to 0 at a DC control voltage equal to VO ;
second variable gain amplifying means for amplifying a second signal in response to a second DC control signal, said second amplifying means having a second gain versus DC control voltage characteristic including a linear region, said linear region having a gain substantially equal to 0 at a DC control voltage equal to AVO, where A is a number greater than 0;
a first source of fixed voltage substantially equal to VO ;
a second source of fixed voltage substantially equal to AVO ;
means for developing a third DC control voltage v;
means for developing a portion Av of said third control voltage v;
first means for deriving said first control voltage including means for providing the difference between said third control voltage v and said fixed voltage VO and means for adding a predetermined portion of the difference between said third control voltage v and said fixed voltage VO to said DC control voltage v; and
second means for deriving said second control voltage including means for providing the difference between a portion Av of said third control voltage v and said fixed voltage AVO and means for adding a predetermined portion of the difference between said portion Av and said fixed voltage AVO to said DC control voltage v.
5. The apparatus recited in claim 4 wherein A is equal to 1. 6. The apparatus recited in claim 4 wherein said first amplifying means is included in a luminance channel of a televeision signal processing system and said second amplifying means is included in a chrominance channel of said television signal processing system. 7. The apparatus recited in claim 6 wherein means for developing said third control voltage includes means responsive to ambient light. 8. The apparatus recited in claim 4 wherein said first means includes first voltage divider means coupled between said fixed voltage VO and said third DC control voltage v; and wherein said second means includes second voltage divider means coupled between said fixed voltage AVO and said portion Av. 9. The apparatus recited in claim 8 wherein said first voltage divider means includes a first potentiometer, said first potentiometer having a wiper coupled to said first amplifying means; and wherein said second voltage divider means includes a second potentiometer, said second potentiometer having a wiper coupled to said amplifying means. 10. The apparatus recited in claim 4 wherein said second gain versus DC control voltage characteristic includes a region between said voltage AVO and a voltage VB where the gain is greater than 0, said voltage VB being substantially equal to the voltage at which said second amplifying means has a gain substantially equal to 0; and wherein said second source of fixed voltage includes means for coupling said voltage VB to said second amplifying means. 11. The apparatus recited in claim 10 wherein said second source of said voltage AVO includes a third source of fixed voltage VB ; potentiometer means coupled between said third source of fixed voltage VB and said means for developing said third DC control voltage; and means coupled to said potentiometer means for developing said voltage AVO at a point along said potentiometer means; said potentiometer means including a wiper coupled to said second amplifier means, said wiper being adjustable to couple a DC voltage VFB and said third control voltage to said second amplifying means.
The present invention pertains to gain controlling apparatus and particularly to apparatus for controlling the gains of amplifiers included in the luminance and chrominance channels of a television signal processing system.
Recently, the maximum brightness available from television receivers has increased sufficiently so that a pleasing image may be reproduced under conditions of high ambient light as well as under conditions of low ambient light. Apparatus is known for automatically controlling the contrast and brightness properties of a television receiver in response to ambient light to provide a pleasing image over a range of ambient light conditions. Such apparatus is described in U.S. Pat. Nos. 3,027,421, entitled "Circuit Arrangements For Automatically Adjusting The Brightness And The Contrast In A Television Receiver," issued to H. Heijligers on Mar. 27, 1962 and 3,025,345, entitled "Circuit Arrangement For Automatic Readjustment Of The Background Brightness And The Contrast In A Television Receiver," issued to R. Suhrmann on Mar. 13, 1962.
Apparatus is also known for automatically controlling the contrast and saturation properties of a color television receiver by controlling the gains of luminance and chrominance channel amplifiers, respectively, in response to ambient light. Such apparatus is described in U.S. Pat. Nos. 3,813,686 entitled "Ambient Light Responsive Control Of Brightness, Contrast And Color Saturation," issued to Eugene Peter Mierzwinski, on May 28, 1974 and 3,814,852 entitled "Ambient Light Responsive Control Of Brightness, Contrast and Color Saturation," issued to Eugene P. Mierzwinski on June 4, 1974.
Also of interest is apparatus for manually controlling the gains of luminance and chrominance channel amplifiers. Such apparatus is described in U.S. Pat. Nos. 3,374,310, entitled "Color Television Receiver with Simultaneous Brightness and Color Saturation Controls," issued to G.L. Beers on Mar. 19, 1968; 3,467,770, entitled "Dual Channel Automatic Control Circuit," issued to DuMonte O. Voigt on June 7, 1966; and 3,715,463, entitled "Tracking Control Circuits Using a Common Potentiometer," issued to Lester Tucker Matzek, on Feb. 6, 1973.
When the gain of luminance channel is adjusted to control the contrast of an image, either manually or automatically, in response to ambient light, it is desirable to simultaneously control the gain of the chrominance channel in such a manner that the ratio of the gains of the luminance and chrominance channels is substantially constant over a wide range of contrast control to maintain constant saturation. If the proper ratio between the amplitudes of the chrominance and luminance signals is not maintained incorrect color reproduction may result. For instance, if the amplitude of the luminance signals are increased without correspondingly increasing the amplitude of the chrominance signals, colors may become desaturated, i.e., they will appear washed out or pastel in shade. Furthermore, it may be desirable to provide controls for presetting the gains of the luminance and chrominance channels to compensate for tolerance variations in other portions of the television signal processing apparatus.
In accordance with the present invention, apparatus is provided which may be utilized in a color television receiver to control contrast over a relatively wide range while maintaining constant saturation. The apparatus includes first and second amplifiers having gain versus control voltage characteristics including linear portions extrapolated to cut off at predetermined voltages which may or may not be the same. Means couple a gain controlling voltage source to the first amplifier to control its gain. Potentiometer means are coupled between a source of fixed voltage substantially equal to the extrapolated cut off voltage of the second amplifier and the source of gain controlling voltage to receive a portion of said gain controlling voltage in accordance with the ratio of the extrapolated cut off voltages of the amplifiers. A voltage developed at a predetermined point along the potentiometer means is coupled to the second amplifier to control its gain.
In accordance with another feature of the present invention, the means for coupling said gain controlling voltage to said first amplifier includes another potentiometer coupled between a source of fixed voltage substantially equal to the extrapolated cut off voltage of said first amplifier and said gain controlling voltage source.
In accordance with still another feature of the present invention the gain controlling voltage source includes an element responsive to ambient light .
These and other aspects of the present invention may best be understood by references to the following detailed description and accompanying drawing in which:
FIG. 1 shows the general arrangement, partly in block diagram form and partly in schematic diagram form, of a color television receiver employing an embodiment of the present invention;
FIG. 1A shows, in schematic form, a modification to the embodiment shown in FIG. 1;
FIG. 2 shows graphical representation of gain versus control voltage characteristics of amplifiers utilized in the embodiment shown in FIG. 1;
FIG. 3 shows graphical representations of gain versus control voltage characteristics of amplifiers which may be utilized in the receiver shown in FIG. 1;
FIG. 4 shows, in schematic form, another embodiment of the present invention which may be utilized to control the amplifiers whose gain versus control voltage characteristics are shown in FIG. 3;
FIG. 5 shows, in schematic form, an amplifier which may be utilized in the receiver shown in FIG. 1; and
FIG. 6 shows, in schematic form, another amplifier which may be utilized in the receiver shown in FIG. 1.
Referring now
to FIG. 1, the general arrangement of a color television receiver employing the present invention includes a video signal processing unit 112 responsive to radio frequency (RF) television signals for generating, by means of suitable intermediate frequency (IF) circuits (not shown) and detection circuits (not shown), a composite video signal comprising chrominance, luminance, sound and synchronizing signals. The output of signal processing unit 112 is coupled to chrominance channel 114, luminance channel 116, a channel 118 for processing the synchronizing signals and a channel (not shown) for processing sound signals.
Chrominance processing channel 114 includes chrominance processing unit 120 which serves to remove chrominance signals from the composite video signal and otherwise process chrominance signals. Chrominance signal processing unit 120 may include, for example, automatic color control (ACC) circuits for adjusting the amplitude of the chrominance channels in response to amplitude variations of a reference signals, such as a color burst signal, included in the commposite video signal. Chrominance signal processing circuits of the type described in the U.S. Pat. No. 3,740,462, entitled "Automatic Chroma Gain Control System," issued to L.A. Harwood, on June 19, 1973 and assigned to the same assignee as the present invention are suitable for use as chrominance processing unit 120.
The output of the chrominance signal processing unit 120 is coupled to chrominance amplifier 122 which serves to amplify chrominance signals in response to a DC signal vC generated by gain control network 142. As illustrated, chrominance amplifier 122 provides chrominance signals to a chroma demodulator 124. An amplifier suitable for use as chrominance amplifier 122 will subsequently be described with reference to FIG. 6.
Chroma demodulator 124 derives color difference signals representing, for example, R-Y, B-Y and G-Y information from the chrominance signals. Demodulator circuits of the general type illustrated by the chrominance amplifier CA 3067 integrated circuit manufactured by RCA Corporation are suitable for use as chrominance demodulator 124.
The color difference signals are applied to a video driver 126 where they are combined with the output signals -Y of luminance channel 116 to produce color signals of the appropriate polarity, representing for example, red (R), green (G) and blue (B) information. The color signals are coupled to kinescope 128.
Luminance channel 116 includes a first luminance signal processing unit 129 which relatively attenuates undesirable signals, such as chrominance or sound signals or both, present in luminance channel 116 and otherwise processes the luminance signals. The output of first luminance processing unit 129 is coupled to luminance amplifier 130 which serves to amplify the luminance signals in response to a DC control signal vL generated by gain control unit 142 to thereby determine the contrast of a reproduced image. An amplifier suitable for use as luminance amplifier 130 will subsequently be described with reference to FIG. 5. The output of luminance amplifier 130 is coupled to second luminance signal processing unit 132 which serves to further process luminance signals. A brightness control unit 131 is coupled to luminance signal processing unit 132 to control the DC content of the luminance signals. The output -Y of luminance processing unit 132 is coupled to kinescope driver 126.
Channel 118 includes a sync separator 134 which separates horizontal and vertical synchronizing pulses from the composite video signal. The synchronizing pulses are coupled to horizontal deflection circuit 136 and vertical deflection circuit 138. Horizontal deflection circuit 136 and vertical deflection circuit 138 are coupled to kinescope 128 and to a high voltage unit 140 to control the generation and deflection of one or more electron beams generated by kinescope 128 in the conventional manner. Deflection circuits 136 and 138 also generate horizontal and vertical blanking signals which are coupled to luminance signal processing unit 132 to inhibit its operation during the horizontal and vertical retrace intervals.
Gain control unit 142 is coupled to luminance amplifier 130 and to chrominance amplifier 122 to control their gains. Gain control unit 142 includes a PNP transistor 152 arranged as an emitter-follower amplifier. The collector of transistor 152 is coupled to ground while its emitter is coupled through a series connection of a potentiometer 156 and fixed resistor 154 to a source of positive supply voltage VO. The wiper of potentiometer 156 is coupled to luminance amplifier 130. The series connection of a potentiometer 158 and a variable resistor 159 is coupled between the source of positive supply voltage VO and the emitter of transistor 152. The wiper of potentiometer 158 is coupled to chrominance amplifier 122.
The base of transistor 152 is coupled to the wiper of a potentiometer 146. One end of potentiometer 146 is coupled to the source of positive supply voltage VO through a fixed resistor 144. The other end of potentionmeter 146 is coupled to ground through a light dependent resistor (LDR) 148. LDR 148 is a resistance element whose impedance varies in inverse relationship with light which impinges on it. LDR 148 may comprise a simple cadmium sulfide type of light dependent element or other suitable light dependent device. LDR 148 is desirably mounted to receive ambient light in the vicinity of the screen of kinescope 128.
A single pole double-throw switch 150 has a pole coupled to the junction of potentiometer 146 and LDR 148. A resistor 151 is coupled between the wiper of potentiometer 146 and the other pole of switch 150. The arm of switch 150 is coupled to ground.
The general arrangement shown in FIG. 1 is suitable for use in a color television receiver of the type shown, for example, in RCA Color Television Service Data 1973 No. C -8 for a CTC-68 type receiver, published by RCA Corporation, Indianapolis, Indiana.
In operation, gain control circuit 142 maintains the ratio of the gain of chrominance amplifier 122 to the gain of amplifier 130 constant in order to maintain constant saturation while providing for contrast adjustment either manually by means of potentiometer 146 or automatically by means of LDR 148. If the gain of luminance were adjusted to control the contrast of an image without a corresponding change in the gain of chrominance amplifier 122, the amplitudes of luminance signals -Y and color difference signals R-Y, B-Y and G-Y would not, in general, be in the correct ratio when combined by divider 126 to provide the desired color.
When switch 140 is in the MANUAL position, the gains of chrominance amplifier 122 and luminance amplifier 130 are controlled by adjustment of the position of potentiometer 146. When switch 150 is in the AUTO position the gain of the chrominance amplifier 122 and luminance amplifier is automatically controlled by the response of LDR 148 to ambient light conditions. The voltage developed at the wiper of potentiometer 146 (base of transistor 152) when switch 150 is in the AUTO position is inversely related to the ambient light recieved by LDR 148. It is noted that the values of resistors 114, potentiometer 146, LDR 148 and resistor 151 are desirably selected such that the adjustment of the wiper arm of potentiometer 146 when switch 150 is in the MANUAL position does not substantially affect the voltage developed at the base of transister 152 when switch 150 is placed in the AUTO position.
The control voltage v developed at the wiper arm of potentiometer 146 is coupled through emitter-follower transistor 152 to the common junction of potentiometer 156 and variable resistor 159. A control voltage vL comprising v plus a predetermined portion of the difference VO -v developed across the series connection of fixed resistor 154 and potentiometer 156, depending on the setting of potentiometer 156, is coupled to luminance amplifier 130 to control its gain. Similarly, a control voltage vC comprising v plus a predetermined portion of the difference voltage VO -v developed across the series connection of potentiometer resistor 158 and variable resistor 159, depending on the setting of the wiper of potentiometer 158, is coupled to chrominance amplifier 122 to control its gain.
The gain of luminance amplifier 130 may be pre-set to a desired value by the factory adjustment of potentiometer 156. Similarly, variable resistor 159 is provided to allow factory pre-set of the gain of the chrominance amplifier 122. Potentiometer 158 is provided to allow customer control of saturation.
R
eferring to FIG. 2, the gain versus voltage characteristics of chroma amplifier 122 (gC) and luminance amplifier 130 (gL) are shown. The characteristic gC has a reversed S-shape including a linear portion 214. Extrapolated linear portion 214 of gC intersects the GAIN axis at GC and intersects the CONTROL VOLTAGE axis at VO. Similarly, the characteristics gL has a reverse S-shape characteristic including a linear portion 212. Extrapolated linear portion 214 of gL intersects the GAIN axis at GL and intersects the CONTROL VOLTAGE axis at VO.
From FIG. 2, the expression for linear portion 212 of gL is ##EQU1## The expression for linear portion 214 of gC is ##EQU2## From FIG. 1, the expression for vL is vL = v + (VO -v) K1 [3]
where K1 is determined by the voltage division of fixed resistor 154 and potentiometer 156 at the wiper of potentiometer 156. When the wiper of potentiometer 156 is at the emitter of transistor 152, K1 =0. The expression for vC is vC = v + (VO -v)K2 [4]
where K2 is determined by the voltage division of potentiometer 158 and fixed resistor 159 at the wiper of potentiometer 158. By combining equations [1] and [3], the equation for gL becomes ##EQU3## By combining equations [2] and [4], the equation for gC becomes ##EQU4## The ratio of gL to gC is thus ##EQU5## It is noted that this ratio is independent of DC control voltage v. Thus, although DC control voltage v may be varied either manually or in response to ambient light to control the contrast of an image reproduced by kinescope 128, the saturation remains constant.
With re
ference to FIG. 2, it is noted that although the linear portion 214 of gC has an extrapolated gain equal to 0 at a control voltage equal to VO, the non-linear portion of gC does not attain a gain equal to 0 until a control voltage equal to VB. That is, a control voltage of VO will not cut-off chrominance amplifier 122.
In FIG. 1A there is shown, in schematic form, a modification to the arrangement of gain control network 142 of FIG. 1 with provisions which allow a viewer to cut off chrominance amplifier 122 to produce a more pleasing image under conditions of poor color reception due, for example, to noise or interference. The modifications to gain control unit 142 shown in FIG. 1A include coupling potentiometer resistor 158 between a source of positive supply voltage VB, the value of VB being greater than the value of VO, and coupling a resistor 160 from a tap-off point 162 along potentiometer 158 to ground. The value of potentiometer 158 and resistor 160 and the location of tap 162 are selected so that voltage VO is developed at tap 162.
The arrangement shown in FIG. 1A allows for the adjustment of contrast while constant saturation is maintained and additionally allows a viewer, by adjusting the wiper of potentiometer 158 to voltage VB, to cut off chrominance amplifier 122.
Referring to FIG. 3 there are shown gain versus DC control voltage characteristics of chrominance and luminance amplifiers which do not have the same extrapolated linear cut off control voltage. The gain versus control voltage characteristic gL ' of the luminance amplifier has a reverse S-shape characteristic including a linear portion 312. Extrapolated linear portion 312 of gL ' intersects the GAIN axis at a gain GL ' and intersects the CONTROL VOLTAGE axis at a voltage VO '. The gain versus control voltage characteristic gC ' of the chrominance amplifier has a reverse S-shape characteristic having a linear portion 314. Extrapolated linear portion 314 of gC ' intersects the GAIN axis at a gain GC ' and intersects the CONTROL VOLTAGE axis at a voltage AVO ', where A is a number greater than zero.
From FIG. 3, the expression for linear portion 312 of gL ' is ##EQU6## where vL ' is the DC conrol voltage coupled to the luminance amplifier. The expression for linear portion 314 of gC ' is ##EQU7## where vC ' is the DC control voltage coupled to the chrominance amplifier.
A modified form of the control network 142 of FIG. 1 suitable for controlling the gain of a chrominance and a luminance amplifier having characteristics such as shown in FIG. 3 is shown in FIG. 4. Similar portions of FIGS. 1 and 4 are identified by reference numbers having the same last two significant digits and primed (') designations. The modified portions of FIG. 1 shown in FIG. 4 include the series connection resistors 460 and 462 coupled between the emitter of transistor 452 to ground. The values of resistors 460 and 462 are selected so that a portion Av' of the DC control voltage v' developed at the emitter of transistor 452 is developed at the junction of resistors 460 and 462. Furthermore, the series connection of potentiometer 458 and variable resistor 459 is coupled between the junction of resistor 460 and 462 and a source of positive supply voltage AVO '.
From FIG. 4, the expression for control voltage vL ' developed at the wiper of potentiometer 456 is vL ' = v' + (vO '-v')K1 ' [10]
where K1 ' is determined by the voltage division at the wiper of potentiometer 456. The expression for control voltage vC ' developed at the wiper of potentiometer 458 is VC ' = Av' + (AVO ' - Av')K 2 ' [11]
where K2 ' is determined by the voltage division at the wiper of potentiometer 458. By combining equations [8] and [10], ##EQU8## By combining equations [9] and [11], ##EQU9## The ratio of gL ' to gC ' is given by the expression ##EQU10## It is noted that this ratio is independent of DC control voltage v'. Therefore, gain control network 442 of FIG. 4 also allows for the adjustment of contrast while maintaining constant saturation.
It is noted that if A were made equal to 1, the arrangement gain control unit 442 would be suitable to control the gains of chrominance and luminance amplifiers having the characteristics shown in FIG. 2.
In FIG. 5, there is shown an amplifier suitable for use as luminance amplifier 130 of FIG. 1. The amplifier includes a differential amplifier comprising NPN transistors 532 and 534. The commonly coupled emitters of transistors 532 and 534 are coupled to the collector of an NPN transistor 528. The emitter of transistor 528 is coupled via a resistor 530 to ground. The collector of transistor 532 and the collector of transistor 534, via load resistor 536, is coupled to a bias voltage provided by bias supply 546, illustrated as a series connection of batteries. The bases of transistors 532 and 534 are respectively coupled to a lower bias voltage through resistors 533 and 535 respectively.
An input signal, such as, for example, the output signal provided by first luminance processing circuit 129 of FIG. 1 is coupled to the base of transistor 532 via terminal 542. The output signal of the amplifier is developed at the collector of transistor 534 and coupled to output terminal 544.
A DC control voltage, such as vL provided by gain control unit 142 of FIG. 1, is coupled to the base of an NPN transistor 514, arranged as an emitter-follower, via terminal 512. The collector of transistor 514 is coupled to bias supply 546. The emitter of transistor 514 is coupled to ground through the series connection of resistor 516, a diode connected transistor 518 and resistor 520.
The anode of diode 520 is coupled to the base of an NPN transistor 538. The collector of transistor 538 is coupled to the collector of transistor 534 while its emitter is coupled to ground through resistor 540. Transistor 538, resistor 540, diode 518 and resistor 520 are arranged in a current mirror configuration.
The emitter of transistor 514 is coupled to the base of a PNP transistor 522. The emitter of transistor 522 is coupled to bias supply 546 while its collector is coupled to the base of transistor 528 and to ground through the series connection of a diode connected transistor 524 and resistor 526. Transistor 528, resistor 530, diode 524 and resistor 526 are arranged in a current mirror configuration
In operation, the DC control voltage coupled to terminal 512 is coupled in inverted fashion to the anode of diode 524 by transistor 522. As a result, current directly related to the voltage developed at the anode of diode 524 flows through diode 524 and resistor 526. Due to the operation of the current mirror arrangement of diode 524, resistor 526, transistor 528 and resistor 530, a similar current flows through the emitter circuit of transistor 528. The gain of the differential amplifier comprising transistors 532 and 534 is directly related to this current flowing in the emitter circuit of transistor 528, and therefore is inversely related to the DC control voltage at terminal 512. The gain versus DC control voltage characteristics of the differential is similar to gL shown in FIG. 2.
Further, a current is developed through the series connection of resistor 516, diode 518 and resistor 520 in direct relationship to the DC control coupled to terminal 512. A similar current is developed through resistor 540 due to the operation of the current mirror comprising diode 518, resistor 520, transistor 538 and resistor 540. This current is of the opposite sense to that provided by the current mirror arrangement of diode 524, resistor 526, transistor 528 and resistor 530 and is coupled to the collector of transistor 534 so that the DC voltage at output terminal 544 does not substantially vary with the DC control voltage.
In FIG. 6, there is shown an amplifier suitable for use as chroma amplifier 120 of FIG. 1. The amplifier shown in FIG. 6 is of the type described in U.S. patent application Ser. No. 530,405 entitled "Controllable Gain Signal Amplifier," fled by L.A. Harwood et al. on Dec. 6, 1974.
The amplifier comprises a differential amplifier including NPN transistors 624 and 625 having their bases coupled to terminal 603 via a resistor 626. Chrominance signals, provided by a source of chrominance signals such as chrominance processing unit 120 of FIG. 1, are coupled to terminal 603. The current conduction paths between the collectors and emitters of transistors 624 and 625 are respectively coupled to ground via resistors 628, 629 and 630.
A current splitter circuit comprising an NPN transistor 632 and a diode 634 is coupled to the collector of transistor 624. Diode 634 and the base-emitter junction of transistor 632 are poled in the same direction with respect to the flow of collector current in transistor 624. It desirable that conduction characteristics of transistor 632 and diode 635 be substantially matched. Similarly, the collector of transistor 625 is coupled to a second current splitter comprising a transistor 633 and a diode 635.
An output load circuit comprising series connected resistors 636 and 638 is coupled between the collector of transistor 632 and a source of operating voltage provided by bias supply 610. Amplified chrominance signals are provided at output terminal 640 for coupling, for example, to a chroma demodulator such as chroma demodulator 124 of FIG. 1. Similarly, series connected load resistors 637 and 639 are coupled between the collector of transistor 633 and bias supply 610. An output terminal 641 at the junction of resistors 637 ad 639 provides oppositely phased chrominance signals to those provided at terminal 640. The gain associated with the cascode combination of transistors 624 and 632 is controlled in response to a DC control voltage, such as, for example, vC provided by gain control unit 142 of FIG. 1, coupled to the base of an NPN transistor 646 via terminal 602. Direct control current is supplied from the emitter of transistor 646 to diode 634 and 635 via a series resistor 652. A signal by-pass circuit comprising a series resonant combination 654 of inductance and capacitance is coupled from the anode of diode 634 to ground. Resonant circuit 654 is tuned, for example, to 3.58 MHz to provide a low impedance path to ground for color subcarrier signals.
Bias voltages and currents are supplied to the amplifier arrangement by bias supply 610, illustrated as a series connection of batterys. A voltage B+ is coupled to the collector of transistor 646. A lower bias voltage is coupled to the load circuits of transistors 632 and 633. The bases of transistors 632 and 633 are coupled in common to a still lower bias voltage. The bases of transistors 624 and 625 are coupled to a still lower bias voltage via substantially equal in value resistors 658 and 659. A resistor 694 is coupled from the common junction of resistors 658 and 659 to ground.
In operation, a quiescent operating current is provided through resistor 630. In the absence of an input signal at terminal 603, this current will divide substantially equally between the similarly biased transistors 624 and 625. If the DC control voltage at terminal 602 is near ground potential, transistor 646 will be effectively cut off and no current will flow in resistor 652 and diodes 634 and 635. In that case, neglecting the normally small difference betweeen collector and emitter currents of NPN transistors, the collector currents of transistors 624 and 625 will flow, respectively, in transistors 632 and 633. The transistors 632 and 633 are operated in common base mode and form cascode signal amplifiers with respective transistors 624 and 625. With the DC control voltage near ground potential, one-half of the quiescent current from resistor 630 flows in each of the load circuits and maximum gain for chrominance signals supplied from terminal 603 is provided.
Transistor 646 will conduct when the DC control voltage approaches the bias voltage supplied to the bases of transistors 632 and 633 of the current splitters. By selection of the circuit parameters, diodes 634 and 635 may be arranged to operate in a range between cut off to the conduction of all of the quiescent operating current supplied via resistor 630, thereby cutting off transistors 632 and 633 to provide no output signals at terminals 640 and 641.
At a DC control voltage intermediate to that corresponding to cut off of transistors 632 and 633 on the one hand and cut off of diodes 634 and 635 on the other hand, the voltage gain of the illustrated amplifier will vary in a substantially linear manner with the DC control voltage.
It is noted that although the characteristics shown in FIGS. 2 and 3 were reversed S-shaped characteristics, the characteristics could have other shapes including linear portions. For example, the characteristics could be substantially linear. Furthermore, with reference to FIG. 3, although gC ' was shown as having a linear portion that had a cut off control voltage lower than the cut off control voltage of the linear portion of gL ', the cut off control voltage of the linear portion of gC ' could be greater than the cut off voltage for the linear region of gL '. In addition, the gain control units and associate amplifiers could be arranged to utilize voltages opposite in polarity to those shown. These and other modifications are intended to be within the scope of the invention.
PHILCO TX927 COLOR "ANTRANCITE" CHASSIS TX 10 (CHASSIS THORN TX10) TDA1170 vertical deflection FRAME DEFLECTION INTEGRATED CIRCUIT
GENERAL DESCRIPTION f The TDA1170 and TDA1270 are monolithic integrated
circuits designed for use in TV vertical deflection systems. They are manufactured using
the Fairchild Planar* process.
Both devices are supplied in the 12-pin plastic power package with the heat sink fins bent
for insertion into the printed circuit board.
The TDA1170 is designed primarily for large and small screen black and white TV
receivers and industrial TV monitors. The TDA1270 is designed primarily for driving
complementary vertical deflection output stages in color TV receivers and industrial
monitors.
APPLICATION INFORMATION (TDA1170)
The vertical oscillator is directly synchronized by the sync pulses (positive or negative); therefore its free
running frequency must be lower than the sync frequency. The use of current feedback causes the yoke
current to be independent of yoke resistance variations due to thermal effects, Therefore no thermistor is
required in series with the yoke. The flyback generator applies a voltage, about twice the supply voltage, to
the yoke. This produces a short flyback time together with a high useful power to dissipated power
ratio.
1. A transformerless output vertical deflection circuit, comprising a vertical oscillator circuit for generating a vertical pulse train in response to vertical synchronizing pulses applied thereto, a sawtooth signal generator for generating a series of sawtooth signals, each cycle of said sawtooth signal including a pulse component, a vertical output circuit coupled to said sawtooth generator for amplifying said sawtooth signal including said pulse component and loading a vertical deflection coil, and stabilizing means connected between said vertical oscillator and said sawtooth signal generator for varying the width of the pulse component which is to be fed to said vertical output circuit in response to the average level of DC output voltage fed from the vertical output circuit. 2. A transformerless output vertical deflection circuit claimed in claim 1, wherein said stabilizing means comprises a control circuit means for receiving a series of pulses from the vertical oscillator and a feedback signal from the vertical output circuit and for varying the width of the pulse which is to be fed to the vertical output circuit in response to a DC control signal proportional to the width of the pulse component included in the vertical output signal and smoothing circuit means connected between said vertical output circuit and said stabalizing means for smoothing said feedback signal. 3. A transformerless output vertical deflection circuit claimed in claim 2, wherein said control circuit comprises a charging capacitor which is parallel to a transistor, said transistor being switched on in response to pulses fed from the vertical oscillator wherein said capacitor is charged by the voltage fed from said smoothing circuit, and discharged in response to conduction of the transistor, a differential amplifier circuit which receives the voltage on said capacitor and a fixed voltage, and a gating circuit for producing a pulse which has a width equal to the difference between the width of the pulse fed from the vertical oscillator circuit and the width of pulse fed from the differential amplifier circuit. 4. A transformerless output vertical deflection circuit claimed in claim 2, wherein said control circuit comprises a capacitor which is charged by a fixed power source and is discharged by means of a switching transistor operated by the pulses fed from the vertical oscillator circuit and a differential amplifier circuit receiving the voltage on the capacitor and the output of said smoothing circuit. 5. A transformable output vertical deflection circuit comprising a vertical oscillator for generating a vertical pulse train in response to vertical synchronizing pulses applied thereto, a sawtooth signal generator for generating a series of sawtooth signals each cycle of said sawtooth signal including a pulse component, a vertical output circuit for amplifying said sawtooth signal including said pulse component and loading a vertical deflection coil, and pulse stabilizing means coupled between the vertical oscillator circuit a
nd the sawtooth signal generator, said stabilizing means comprising a capacitor which is charged by a fixed power source and discharged by means of a discharging means operated in response to the vertical pulse fed from the vertical oscillator, a circuit means for generating a train of output pulses each starting at the time when the voltage appearing on the capacitor exceeds a predetermined value and terminating in synchronism with termination of the pulse fed from the vertical oscillator, and gating means for generating pulses having a width equal to the difference between the width of the pulse fed from the vertical oscillator and the width of the output pulse of the circuit means. 6. A transformerless output vertical deflection circuit, comprising a vertical oscillator circuit for generating a vertical pulse train in response to vertical synchronizing pulses applied thereto, a sawtooth signal generator for generating a series of sawtooth signals, each cycle of said sawtooth signal including a pulse component, a vertical output circuit coupled to said sawtooth generator for amplifying said sawtooth signal including said pulse component and loading a vertical deflection coil, and stabilizing means, comprising a control circuit connected between said vertical output circuit and said vertical oscillator circuit for varying the width of each pulse produced by the vertical oscillator circuit in response to a DC control signal having a value corresponding to the width of the pulse component applied to the vertical deflection coil of the vertical output circuit for controlling the pulse width of the output of said vertical oscillator circuit and thereby the pulse width of said pulse component.
TDA2576 SYNC COMBINATION WITH TRANSMITTER IDENTIFICATION (CHASSIS THORN TX10)
AND VERTICAL 625 DIVIDER SYSTEM
GENERAL DESCRIPTION
The TDA2576 B is a monolithic integrated circuit for use in colour television receivers with switched-
mode driven or self-regulating horizontal time-base circuits. It is designed in combination with the
TDA2581 to operate as a matched pair. When supplied with a composite video signal the TDA2576 B
delivers drive pulses for the TDA2581 and sync pulses for the vertical deflection. The circuit is
optimized for a horizontal and vertical frequency ratio of 625. It incorporates the following features:
Features
O Horizontal sync separator (including noise inverter) I
O Horizontal phase detector
0 Horizontal oscillator (31,25 kHz)
0 Sandcastle pulse generator
O Vertical sync pulse separator
O Very stable automatic vertical synchronization due to the 625 divider system, without delay after
channel change
I Three voltage level sensor on coincidence detector circuit output
I Video transmitter identification circuit for sound muting and search tuning systems
O Inhibit of vertical sync pulse when no video transmitter is detected
QUICK REFERENCE DATA
Supply voltage _
horizontal (pin 14) V14_13 typ. 12 V
vertical (pin 18) V13_13 typ. 12 V
Supply current (pin 14 + pin 18) V14+18 typ. 52 mA
Sync separator
input voltage level (peak-to-peak value) V2.131p.p) 0,07 to I V
slicing level typ. 50 % _
Output pulse E
horizontal (peak-to-peak value) V3_131p_p1 min. 10 V =
vertical sync (peak-to-peak value) V1_131p_p1 min. 10 V —
burst key (peak-to~peak value) V15_131p_p1 min. 10 V
Video transmitter identification circuit
Output voltage (pin 10)
sync pulse present V10_13 typ. 8 V
no sync pulse V1Q_13 max. 1 V
Phase locked loop
control sensitivity typ. 2000 Hz/;1s
holding range Af typ. 1 1000 Hz
catching range Af typ. : 900 Hz
Operating ambient temperature range Tamb -25 to + 65 °C
PACKAGE OUTLINE
18-lead DIL; plastic (SOT-102A).
FUNCTIONAL DESCRIPTION
The video input voltage to drive the sync separator must have negative-going sync, which can be
obtained from synchronous demodulators such as TDA2540, TDA2541 and TDA2670.
The slicing level of the sync separator is determined by the value of the resistor between pins 3 and 4.
A 5,6 kfl resistor provides a slicing level midway between the top sync level and the blanking level.
Thus the slicing level is independent of the amplitude of the sync pulse input at pin 2.
The nominal top sync level at pin 2 is 1,5 V, and the amplitude selective noise inverter is activated at
0,7 V. The horizontal phase detector has a steepness of 1,2 V/its and together with the 1800 Hz/V of
the horizontal oscillator provides a total control steepness of 2000 Hz/us.
A second horizontal phase detector provides a 5,5 its pulse which ensures symmetrical gating of the
horizontal synchronization. During catching the gating is automatically switched off. At the same time
the flywheel filter is switched to a short time constant. The value of this time constant can be deter~
mined externally via pin 11.
When the indirect vertical sync output is generated by the 625 divider system an anti-top flutter pulse
switches off the equalizing and vertical sync pulse operation of the phase detector. Thus top flutter
distortion of the control voltage due to vertical pulses can be anticipated. When the 625 divider system
is in the direct mode the anti~top flutter pulse is inhibited.
The free running output frequency of the horizontal oscillator is 31,25 kl-lz. The vertical frequency
output is obtained by dividing this double horizontal frequency by 625. The double horizontal
frequency is fed via a binary divider to provide the normal 15,625 kHz horizontal output at pin 8. The
trailing edge of this pulse is positioned 0,9 us after the end of the video sync pulse input at pin 2
(see Fig. 2).
The automatic vertical sync block contains the following:
0 625 divider
0 In/out-sync detector
I Direct/indirect sync switch
O Identification circuit
It is fed by a signal obtained by integration of the composite sync signal and an internally generated,
clipped video signal. The vertical sync pulse is sliced out of this integrated signal by an automatically
biased clipper. The videopart of the signal helps to build up a vertical sync pulse when heavy negative-
going reflections (mountains) distort the video signal. The in/out sync-detector considers a signal
out~of-sync when fifteen or more successive incoming vertical sync pulses are not in phase with a
reference signal from the 625 divider. Therefore a distorted vertical sync signal needs only one
out-of-fifteen pulses to be in phase to keep the system in sync. When the sixteenth successive out-of-
sync pulse is detected, the direct/indirect sync switch is activated to feed the vertical sync signal
directly out of the block at pin 2 (direct sync vertical output).
At the same time the 625 divider is reset by one of the sync pulses. After the reset pulse, if the 7th
sliced vertical sync pulse coincides with a 625 divider window, the sync output pulse is presented
again by the divider system and switch-over to indirect mode occurs.
In the direct mode, every 7th non-coinciding sliced vertical sync pulse will reset the counter. Thus a
non-standard video signal will result in continuous reset pulses and the direct/indirect switch will
remain in the direct position.
To avoid delay in vertical synchronization, caused by waiting time of the divider circuit after channel
change or an unsynchronized camera change in the studio, information is fed from the horizontal coin-
cidence detector to the automatic switch for the vertical sync pulse. The loss of horizontal synchroni-
zation sets the automatic switch to direct vertical sync. When horizontal coincidence is detected again
the setting of the automatic switch depends on whether a standard video signal is received or not. When
an external voltage between 2,5 V and 7,25 V is applied via pin 12 to the coincidence detector, the hor-
izontal phase detector is swsync. A voltage level on pin 12 > 8,25 V switches the horizontal phase detector to a short time constant,
without affecting the indirect/direct vertical sync system which remains operational.
The video transmitter identification circuit detects when a sync pulse occurs during the internal gating
pulse. This indicates the presence of a video transmitter and results in the capacitor connected to pin
10 being charged to 8 V. When no sync pulse is present the capacitor discharges to < 1 V. The voltage
at pin 10 is compared with an internal d.c. voltage. The identification output at pin 9 is active when
pin 10 is < 1,6 V (no video transmitter) and inactive (high impedance) when pin 10 is > 3,5 V.
The vertical sync output pulse at pin 1 is inhibited when no video transmitter is identified, which
prevents interference or noise affecting the frequency of the vertical output stage. This results in a vertical stable picture, plus vertical stable position information of tuning systems.
TDA2541 IF AMPLIFIER WITH DEMODULATOR AND AFC
DESCRIPTION
The TDA2540 and 2541 are IF amplifier and A.M.
demodulator circuits for colour and black and white
television receivers using PNP or NPN tuners. They
are intended for reception of negative or positive
modulation CCIR standard.
They incorporate the following functions : .Gain controlled amplifier .Synchronous demodulator .White spot inverter .Video preamplifier with noise protection .Switchable AFC .AGC with noise gating .Tuner AGC output (NPN tuner for 2540)-(PNP
tuner for 2541) .VCR switch for video output inhibition (VCR
play back).
.SUPPLYVOLTAGE : 12V TYP
.SUPPLYCURRENT : 50mATYP
.I.F. INPUT VOLTAGE SENSITIVITY AT
F = 38.9MHz : 85mVRMS TYP
.VIDEO OUTPUT VOLTAGE (white at 10% of
top synchro) : 2.7VPP TYP
.I.F. VOLTAGE GAIN CONTROL RANGE :
64dB TYP .SIGNAL TO NOISE RATIO AT VI = 10mV :
58dB TYP
.A.F.C. OUTPUT VOLTAGE SWING FOR
Df = 100kHz : 10V TYP.
PHILCO TX927 COLOR "ANTRANCITE" CHASSIS TX 10 Horizontal deflection output circuit:
1. A horizontal deflection output circuit comprising:
a switching element;
a resonant capacitor connected in parallel with said switching element; and
a first series circuit connected in parallel with said switching element and including a horizontal deflection coil and a linearity correcting coil,
wherein the improvement comprises:
a second series circuit connected in parallel with said linearity correcting coil, said second series circuit comprising load means for damping resonance energy in said first series circuit and current control means for limiting the current flow through said load means to the first half of a horizontal scanning period and including a one-way switching element which turns on for a first half of said horizontal scanning period and turns off for the last half of the horizontal scanning period and for a fly-back pulse period, thereby limiting current flow through said load means to the first half of said horizontal scanning period.
2. A horizontal deflection output circuit according to claim 1, wherein said load means includes a resistor. 3. A horizontal deflection output circuit according to claim 2, wherein a capacitor is connected in parallel with said linearity correcting coil. 4. A horizontal deflection output circuit according to claim 2, wherein said one-way switching element is a diode. 5. A horizontal deflection output circuit according to claim 1, wherein said load means includes: a resistor; and current adjusting means for adjusting the current to flow through said resistor. 6. A horizontal deflection output circuit comprising:
a switching element;
a resonant capacitor connected in parallel with said switching element;
a series circuit connected in parallel with said switching element and including a horizontal deflection coil and a linearity correcting coil; and
a series circuit connected in parallel with said linearity correcting coil and including load means and a one-way switching element adapted to be turned on for the front half of a horizontal scanning period, said load means including a resistor and current adjusting means for adjusting the current flow through said resistor, said current adjusting means including a transistor connected in series with said resistor and bias voltage feeding means for feeding a bias voltage to the base of said transistor.
7. A horizontal deflection output circuit according to claim 6, wherein a capacitor is connected in parallel with said linearity correcting coil. 8. A horizontal deflection output circuit according to claim 6, wherein said one-way switching element is turned off at least for a fly-back pulse period. 9. A horizontal deflection output circuit according to claim 6, wherein said one-way switching element is a diode. 10. A horizontal deflection output circuit according to claim 6, wherein said bias voltage feeding means includes resistance voltage-dividing means for dividing the voltage between the two terminals of said linearity correcting coil. 11. A horizontal deflection output circuit according to claim 10, wherein a capacitor is connected in parallel with said linearity correcting coil. 12. A horizontal deflection output circuit according to claim 10, wherein said one-way switching element is turned off at least for a fly-back pulse period. 13. A horizontal deflection output circuit according to claim 10, wherein said one-way switching element is a diode. 14. A horizontal deflection output circuit according to claim 10, wherein said bias voltage feeding means includes a time constant circuit composed of a resistor and a capacitor. 15. A horizontal deflection output circuit according to claim 14, wherein a capacitor is connected in parallel with said linearity correcting coil. 16. A horizontal deflection output circuit according to claim 14, wherein said one-way switching element is a diode. 17. A horizontal deflection output circuit according to claim 14, wherein said one-way switching element is turned off at least for a fly-back pulse period. 18. A horizontal deflection output circuit comprising:
a switching element;
a damper diode connected in parallel with said switching element;
a resonant capacitor connected in parallel with said switching element;
a first series circuit connected in parallel with said switching element and including a horizontal deflection coil and a linearity correcting coil;
a second series circuit connected in parallel with said linearity correcting coil, said second series circuit comprising load means for damping resonance energy in said first series circuit and current control means for limiting the current flow through said load means to the first half of a horizontal scanning period and including a one-way switching element which turns on for the first half of said horizontal scanning period and turns off for the last half of said horizontal scanning period and a fly-back pulse period, thereby limiting current flow through said load means to said first half of said horizontal scanning period;
a choke coil connected with the cathode terminal of said damper diode; and
a d.c. current blocking capacitor connected in series with said horizontal deflection coil.
19. A horizontal deflection output circuit according to claim 18, wherein said choke coil is a fly-back transformer. 20. A horizontal deflection output circuit according to claim 19, wherein said load means includes a resistor. 21. A horizontal deflection output circuit according to claim 20, wherein a capacitor is connected in parallel with said linearity correcting coil. 22. A horizontal deflection output circuit according to claim 20, wherein said one-way switching element is a diode. 23. A horizontal deflection output circuit according to claim 19, wherein said load means includes: a resistor; and current adjusting means for adjusting the current to flow through said resistor. 24. A horizontal deflection output circuit comprising:
a switching element;
a damper diode connected in parallel with said switching element;
a resonant capacitor connected in parallel with said switching element;
a series circuit connected in parallel with said switching element and including a horizontal deflection coil and a linearity correcting coil;
a series circuit connected in parallel with said linearity correcting coil and including load means and a one-way switching element adapted to be turned on for the front half of a horizontal scanning period, said load means including a resistor and current adjusting means for adjusting the current flow through said resistor, said current adjusting means including a transistor connected in series with said resistor and bias voltage feeding means for feeding a bias voltage to the base of said transistor;
a choke coil in the form of a fly-back transformer connected with the cathode terminal of said damper diode; and
a d.c. current blocking capacitor connected in series with said horizontal deflection coil.
25. A horizontal deflection output circuit according to claim 24, wherein said one-way switching element is turned off at least for a fly-back pulse period. 26. A horizontal deflection output circuit according to claim 24, wherein a capacitor is connected in parallel with said linearity correcting coil. 27. A horizontal deflection output circuit according to claim 24, wherein said one-way switching element is a diode. 28. A horizontal deflection output circuit according to claim 24, wherein said bias voltage feeding means includes resistance voltage-dividing means for dividing the voltage between the two terminals of said linearity correcting coil. 29. A horizontal deflection output circuit according to claim 28, wherein said bias voltage feeding means includes a time constant circuit composed of a resistor and a capacitor. 30. A horizontal deflection output circuit according to claim 28, wherein said one-way switching element is turned off at least for a fly-back pulse period. 31. A horizontal deflection output circuit according to claim 28, wherein a capacitor is connected in parallel with said linearity correcting coil. 32. A horizontal deflection output circuit according to claim 28, wherein said one-way switching element is a diode.
The present invention relates to a horizontal deflection output circuit which is to be used with a high resolution display and which has a high horizontal deflection frequency and a high output.
In a conventional TV receiver, a horizontal deflection current having a saw-tooth waveform reaches saturation as it approaches its maximum, causing a problem in that the scanning rate of the electron beam is reduced at the extreme right-hand side, as viewed toward the frame of the display, so that the picture reproduced on the face plate is distorted.
The circuit for solving the above-specified problem to form a symmetrical picture is called a "linearity correcting circuit". In order to correct the linearity of the raster scanned on the face plate, the linearity correcting circuit of the prior art is equipped with a linearity correcting coil which is connected in series with a horizontal deflection coil. That linearity correcting coil is so magnetically biased by means of a permanent magnet that its magnetic saturation characteristics are set differently depending upon the direction of the horizontal deflection current. This horizontal deflection circuit is exemplified by Japanese Patent Laid-Open Nos. 40615/1982, 128949/1981, 124850/1980 and U.S. Pat. No. 3,962,603, as shown schematically in FIGS. 1A and 1B.
As shown in FIG. 1A, the horizontal deflection circuit is composed of an input terminal 1, an output transistor 2, a damper diode 3, a resonant capacitor 4, a horizontal deflection coil 5, a linearity correcting coil 6, an S-shaped correction capacitor 7, a choke coil 8, a supply terminal 9, and a permanent magnet 12 for setting the magnetic bias of the linearity correcting coil 6.
The permanent magnet 12 has its polarity arranged so as to apply a magnetic field in the same direction as that of the magnetic field established in the linearity correcting coil in case a horizontal deflection current IDY flows in the direction of arrow a to the horizontal deflection coil 5.
In case the horizontal deflection current IDY flows in the direction of the arrow a, therefore, the linearity correcting coil 6 is more liable to be magnetically saturated than when the horizontal deflection current IDY flows in the reverse direction.
As a result, the inductance of the linearity correcting coil 6 is least in the vicinity of the maximum of the horizontal deflection current so that this current increases.
Thus, the drop of the scanning rate of the electron beam at the right side of the display frame is corrected. In the display, however, the use of a linearity correcting coil will form longitudinal shading streaks at the left side of the display frame. Those streaks are formed as a result of the fact that a ringing current is established in the horizontal deflection current by the resonance of a resonant circuit which is composed of the inductance of the linearity coil 6 and a stray capacity 17, as shown in FIG. 1B.
In order to solve this problem, the horizontal deflection circuit of the prior art is equipped with a resistor 14 which is connected in parallel with the linearity correcting coil 6. By the provision of that resistor 14, the resonant circuit of the stray capacity and the linearity correcting coil has its Q (i.e., quality) factor dropped to reduce the amplitude of the ringing current.
As the horizontal deflection current has its frequency increased and its output raised in accordance with the fineness in the structure of the display, however, there arises another problem that the power loss at the ringing current preventing resistor is increased.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a horizontal deflection output circuit of high speed and output enabled to reduce such ringing of the horizontal deflection current as will raise a problem, when the horizontal linearity is to be corrected by a linearity correcting coil, without inviting an increase in the loss of the output circuit thereby to eliminate in a more advantageous way the longitudinal streaks which might otherwise be formed in a picture frame.
In order to achieve the above-specified object, the horizontal deflection output circuit according to the present invention has a series circuit connected in parallel with a linearity coil, the series circuit being composed of a resistor and a switching element. The switching element is so controlled that it may be turned on only for a predetermined time period including that for which ringing occurs in the horizontal deflection current.
1. In a color television signal processing system of the type including luminance and chrominance signal processing channels, apparatus comprising:
first and second amplifiers respectively included in said luminance and chrominance channels, said amplifiers having gain versus control voltage characteristics including linear portions extrapolated to cut-off at predetermined voltages which may or may not be the same voltage;
a gain controlling voltage source;
means for coupling said gain controlling voltage to said first amplifier to control its gain;
potentiometer means coupled between a fixed voltage substantially equal to the extrapolated cut-off voltage of said second amplifier and to said gain controlling voltage source to recieve a portion of said gain controlling voltage in accordance with the ratio of the extrapolated cut-off voltages of said first and second amplifiers; and
2. The apparatus recited in claim 1 wherein said means for coupling said gain controlling voltage to said first amplifier includes another potentiometer coupled between a source of fixed voltage substantially equal to the extrapolated cut-off voltage of said first amplifier and said gain controlling voltage source. 3. In a color television signal processing system of the type including luminance and chrominance signal processing channels, apparatus comprising:
first and second amplifiers respectively included in said luminance and chrominance channels, said amplifiers having gain control voltage characteristics including linear portions extrapolated to cut-off at substantially the same predetermined voltage;
a source of gain controlling voltage; and
means for coupling said gain controlling voltage to said first and second amplifiers.
4. Apparatus comprising:
first variable gain amplifying means for amplifying a first signal in response to a first DC control signal, said first amplifying means having a first gain versus DC control voltage characteristic including a linear region, said linear region having a gain substantially equal to 0 at a DC control voltage equal to VO ;
second variable gain amplifying means for amplifying a second signal in response to a second DC control signal, said second amplifying means having a second gain versus DC control voltage characteristic including a linear region, said linear region having a gain substantially equal to 0 at a DC control voltage equal to AVO, where A is a number greater than 0;
a first source of fixed voltage substantially equal to VO ;
a second source of fixed voltage substantially equal to AVO ;
means for developing a third DC control voltage v;
means for developing a portion Av of said third control voltage v;
first means for deriving said first control voltage including means for providing the difference between said third control voltage v and said fixed voltage VO and means for adding a predetermined portion of the difference between said third control voltage v and said fixed voltage VO to said DC control voltage v; and
second means for deriving said second control voltage including means for providing the difference between a portion Av of said third control voltage v and said fixed voltage AVO and means for adding a predetermined portion of the difference between said portion Av and said fixed voltage AVO to said DC control voltage v.
5. The apparatus recited in claim 4 wherein A is equal to 1. 6. The apparatus recited in claim 4 wherein said first amplifying means is included in a luminance channel of a televeision signal processing system and said second amplifying means is included in a chrominance channel of said television signal processing system. 7. The apparatus recited in claim 6 wherein means for developing said third control voltage includes means responsive to ambient light. 8. The apparatus recited in claim 4 wherein said first means includes first voltage divider means coupled between said fixed voltage VO and said third DC control voltage v; and wherein said second means includes second voltage divider means coupled between said fixed voltage AVO and said portion Av. 9. The apparatus recited in claim 8 wherein said first voltage divider means includes a first potentiometer, said first potentiometer having a wiper coupled to said first amplifying means; and wherein said second voltage divider means includes a second potentiometer, said second potentiometer having a wiper coupled to said amplifying means. 10. The apparatus recited in claim 4 wherein said second gain versus DC control voltage characteristic includes a region between said voltage AVO and a voltage VB where the gain is greater than 0, said voltage VB being substantially equal to the voltage at which said second amplifying means has a gain substantially equal to 0; and wherein said second source of fixed voltage includes means for coupling said voltage VB to said second amplifying means. 11. The apparatus recited in claim 10 wherein said second source of said voltage AVO includes a third source of fixed voltage VB ; potentiometer means coupled between said third source of fixed voltage VB and said means for developing said third DC control voltage; and means coupled to said potentiometer means for developing said voltage AVO at a point along said potentiometer means; said potentiometer means including a wiper coupled to said second amplifier means, said wiper being adjustable to couple a DC voltage VFB and said third control voltage to said second amplifying means.
Description:
Recently, the maximum brightness available from television receivers has increased sufficiently so that a pleasing image may be reproduced under conditions of high ambient light as well as under conditions of low ambient light. Apparatus is known for automatically controlling the contrast and brightness properties of a television receiver in response to ambient light to provide a pleasing image over a range of ambient light conditions. Such apparatus is described in U.S. Pat. Nos. 3,027,421, entitled "Circuit Arrangements For Automatically Adjusting The Brightness And The Contrast In A Television Receiver," issued to H. Heijligers on Mar. 27, 1962 and 3,025,345, entitled "Circuit Arrangement For Automatic Readjustment Of The Background Brightness And The Contrast In A Television Receiver," issued to R. Suhrmann on Mar. 13, 1962.
Apparatus is also known for automatically controlling the contrast and saturation properties of a color television receiver by controlling the gains of luminance and chrominance channel amplifiers, respectively, in response to ambient light. Such apparatus is described in U.S. Pat. Nos. 3,813,686 entitled "Ambient Light Responsive Control Of Brightness, Contrast And Color Saturation," issued to Eugene Peter Mierzwinski, on May 28, 1974 and 3,814,852 entitled "Ambient Light Responsive Control Of Brightness, Contrast and Color Saturation," issued to Eugene P. Mierzwinski on June 4, 1974.
Also of interest is apparatus for manually controlling the gains of luminance and chrominance channel amplifiers. Such apparatus is described in U.S. Pat. Nos. 3,374,310, entitled "Color Television Receiver with Simultaneous Brightness and Color Saturation Controls," issued to G.L. Beers on Mar. 19, 1968; 3,467,770, entitled "Dual Channel Automatic Control Circuit," issued to DuMonte O. Voigt on June 7, 1966; and 3,715,463, entitled "Tracking Control Circuits Using a Common Potentiometer," issued to Lester Tucker Matzek, on Feb. 6, 1973.
When the gain of luminance channel is adjusted to control the contrast of an image, either manually or automatically, in response to ambient light, it is desirable to simultaneously control the gain of the chrominance channel in such a manner that the ratio of the gains of the luminance and chrominance channels is substantially constant over a wide range of contrast control to maintain constant saturation. If the proper ratio between the amplitudes of the chrominance and luminance signals is not maintained incorrect color reproduction may result. For instance, if the amplitude of the luminance signals are increased without correspondingly increasing the amplitude of the chrominance signals, colors may become desaturated, i.e., they will appear washed out or pastel in shade. Furthermore, it may be desirable to provide controls for presetting the gains of the luminance and chrominance channels to compensate for tolerance variations in other portions of the television signal processing apparatus.
In accordance with the present invention, apparatus is provided which may be utilized in a color television receiver to control contrast over a relatively wide range while maintaining constant saturation. The apparatus includes first and second amplifiers having gain versus control voltage characteristics including linear portions extrapolated to cut off at predetermined voltages which may or may not be the same. Means couple a gain controlling voltage source to the first amplifier to control its gain. Potentiometer means are coupled between a source of fixed voltage substantially equal to the extrapolated cut off voltage of the second amplifier and the source of gain controlling voltage to receive a portion of said gain controlling voltage in accordance with the ratio of the extrapolated cut off voltages of the amplifiers. A voltage developed at a predetermined point along the potentiometer means is coupled to the second amplifier to control its gain.
In accordance with another feature of the present invention, the means for coupling said gain controlling voltage to said first amplifier includes another potentiometer coupled between a source of fixed voltage substantially equal to the extrapolated cut off voltage of said first amplifier and said gain controlling voltage source.
In accordance with still another feature of the present invention the gain controlling voltage source includes an element responsive to ambient light .
These and other aspects of the present invention may best be understood by references to the following detailed description and accompanying drawing in which:
FIG. 1 shows the general arrangement, partly in block diagram form and partly in schematic diagram form, of a color television receiver employing an embodiment of the present invention;
FIG. 1A shows, in schematic form, a modification to the embodiment shown in FIG. 1;
FIG. 2 shows graphical representation of gain versus control voltage characteristics of amplifiers utilized in the embodiment shown in FIG. 1;
FIG. 3 shows graphical representations of gain versus control voltage characteristics of amplifiers which may be utilized in the receiver shown in FIG. 1;
FIG. 4 shows, in schematic form, another embodiment of the present invention which may be utilized to control the amplifiers whose gain versus control voltage characteristics are shown in FIG. 3;
FIG. 5 shows, in schematic form, an amplifier which may be utilized in the receiver shown in FIG. 1; and
FIG. 6 shows, in schematic form, another amplifier which may be utilized in the receiver shown in FIG. 1.
Referring now
to FIG. 1, the general arrangement of a color television receiver employing the present invention includes a video signal processing unit 112 responsive to radio frequency (RF) television signals for generating, by means of suitable intermediate frequency (IF) circuits (not shown) and detection circuits (not shown), a composite video signal comprising chrominance, luminance, sound and synchronizing signals. The output of signal processing unit 112 is coupled to chrominance channel 114, luminance channel 116, a channel 118 for processing the synchronizing signals and a channel (not shown) for processing sound signals. Chrominance processing channel 114 includes chrominance processing unit 120 which serves to remove chrominance signals from the composite video signal and otherwise process chrominance signals. Chrominance signal processing unit 120 may include, for example, automatic color control (ACC) circuits for adjusting the amplitude of the chrominance channels in response to amplitude variations of a reference signals, such as a color burst signal, included in the commposite video signal. Chrominance signal processing circuits of the type described in the U.S. Pat. No. 3,740,462, entitled "Automatic Chroma Gain Control System," issued to L.A. Harwood, on June 19, 1973 and assigned to the same assignee as the present invention are suitable for use as chrominance processing unit 120.
The output of the chrominance signal processing unit 120 is coupled to chrominance amplifier 122 which serves to amplify chrominance signals in response to a DC signal vC generated by gain control network 142. As illustrated, chrominance amplifier 122 provides chrominance signals to a chroma demodulator 124. An amplifier suitable for use as chrominance amplifier 122 will subsequently be described with reference to FIG. 6.
Chroma demodulator 124 derives color difference signals representing, for example, R-Y, B-Y and G-Y information from the chrominance signals. Demodulator circuits of the general type illustrated by the chrominance amplifier CA 3067 integrated circuit manufactured by RCA Corporation are suitable for use as chrominance demodulator 124.
The color difference signals are applied to a video driver 126 where they are combined with the output signals -Y of luminance channel 116 to produce color signals of the appropriate polarity, representing for example, red (R), green (G) and blue (B) information. The color signals are coupled to kinescope 128.
Luminance channel 116 includes a first luminance signal processing unit 129 which relatively attenuates undesirable signals, such as chrominance or sound signals or both, present in luminance channel 116 and otherwise processes the luminance signals. The output of first luminance processing unit 129 is coupled to luminance amplifier 130 which serves to amplify the luminance signals in response to a DC control signal vL generated by gain control unit 142 to thereby determine the contrast of a reproduced image. An amplifier suitable for use as luminance amplifier 130 will subsequently be described with reference to FIG. 5. The output of luminance amplifier 130 is coupled to second luminance signal processing unit 132 which serves to further process luminance signals. A brightness control unit 131 is coupled to luminance signal processing unit 132 to control the DC content of the luminance signals. The output -Y of luminance processing unit 132 is coupled to kinescope driver 126.
The base of transistor 152 is coupled to the wiper of a potentiometer 146. One end of potentiometer 146 is coupled to the source of positive supply voltage VO through a fixed resistor 144. The other end of potentionmeter 146 is coupled to ground through a light dependent resistor (LDR) 148. LDR 148 is a resistance element whose impedance varies in inverse relationship with light which impinges on it. LDR 148 may comprise a simple cadmium sulfide type of light dependent element or other suitable light dependent device. LDR 148 is desirably mounted to receive ambient light in the vicinity of the screen of kinescope 128.
A single pole double-throw switch 150 has a pole coupled to the junction of potentiometer 146 and LDR 148. A resistor 151 is coupled between the wiper of potentiometer 146 and the other pole of switch 150. The arm of switch 150 is coupled to ground.
The general arrangement shown in FIG. 1 is suitable for use in a color television receiver of the type shown, for example, in RCA Color Television Service Data 1973 No. C -8 for a CTC-68 type receiver, published by RCA Corporation, Indianapolis, Indiana.
When switch 140 is in the MANUAL position, the gains of chrominance amplifier 122 and luminance amplifier 130 are controlled by adjustment of the position of potentiometer 146. When switch 150 is in the AUTO position the gain of the chrominance amplifier 122 and luminance amplifier is automatically controlled by the response of LDR 148 to ambient light conditions. The voltage developed at the wiper of potentiometer 146 (base of transistor 152) when switch 150 is in the AUTO position is inversely related to the ambient light recieved by LDR 148. It is noted that the values of resistors 114, potentiometer 146, LDR 148 and resistor 151 are desirably selected such that the adjustment of the wiper arm of potentiometer 146 when switch 150 is in the MANUAL position does not substantially affect the voltage developed at the base of transister 152 when switch 150 is placed in the AUTO position.
The control voltage v developed at the wiper arm of potentiometer 146 is coupled through emitter-follower transistor 152 to the common junction of potentiometer 156 and variable resistor 159. A control voltage vL comprising v plus a predetermined portion of the difference VO -v developed across the series connection of fixed resistor 154 and potentiometer 156, depending on the setting of potentiometer 156, is coupled to luminance amplifier 130 to control its gain. Similarly, a control voltage vC comprising v plus a predetermined portion of the difference voltage VO -v developed across the series connection of potentiometer resistor 158 and variable resistor 159, depending on the setting of the wiper of potentiometer 158, is coupled to chrominance amplifier 122 to control its gain.
The gain of luminance amplifier 130 may be pre-set to a desired value by the factory adjustment of potentiometer 156. Similarly, variable resistor 159 is provided to allow factory pre-set of the gain of the chrominance amplifier 122. Potentiometer 158 is provided to allow customer control of saturation.
R
eferring to FIG. 2, the gain versus voltage characteristics of chroma amplifier 122 (gC) and luminance amplifier 130 (gL) are shown. The characteristic gC has a reversed S-shape including a linear portion 214. Extrapolated linear portion 214 of gC intersects the GAIN axis at GC and intersects the CONTROL VOLTAGE axis at VO. Similarly, the characteristics gL has a reverse S-shape characteristic including a linear portion 212. Extrapolated linear portion 214 of gL intersects the GAIN axis at GL and intersects the CONTROL VOLTAGE axis at VO. From FIG. 2, the expression for linear portion 212 of gL is ##EQU1## The expression for linear portion 214 of gC is ##EQU2## From FIG. 1, the expression for vL is vL = v + (VO -v) K1 [3]
where K1 is determined by the voltage division of fixed resistor 154 and potentiometer 156 at the wiper of potentiometer 156. When the wiper of potentiometer 156 is at the emitter of transistor 152, K1 =0. The expression for vC is vC = v + (VO -v)K2 [4]
where K2 is determined by the voltage division of potentiometer 158 and fixed resistor 159 at the wiper of potentiometer 158. By combining equations [1] and [3], the equation for gL becomes ##EQU3## By combining equations [2] and [4], the equation for gC becomes ##EQU4## The ratio of gL to gC is thus ##EQU5## It is noted that this ratio is independent of DC control voltage v. Thus, although DC control voltage v may be varied either manually or in response to ambient light to control the contrast of an image reproduced by kinescope 128, the saturation remains constant.
With re
ference to FIG. 2, it is noted that although the linear portion 214 of gC has an extrapolated gain equal to 0 at a control voltage equal to VO, the non-linear portion of gC does not attain a gain equal to 0 until a control voltage equal to VB. That is, a control voltage of VO will not cut-off chrominance amplifier 122. In FIG. 1A there is shown, in schematic form, a modification to the arrangement of gain control network 142 of FIG. 1 with provisions which allow a viewer to cut off chrominance amplifier 122 to produce a more pleasing image under conditions of poor color reception due, for example, to noise or interference. The modifications to gain control unit 142 shown in FIG. 1A include coupling potentiometer resistor 158 between a source of positive supply voltage VB, the value of VB being greater than the value of VO, and coupling a resistor 160 from a tap-off point 162 along potentiometer 158 to ground. The value of potentiometer 158 and resistor 160 and the location of tap 162 are selected so that voltage VO is developed at tap 162.
The arrangement shown in FIG. 1A allows for the adjustment of contrast while constant saturation is maintained and additionally allows a viewer, by adjusting the wiper of potentiometer 158 to voltage VB, to cut off chrominance amplifier 122.
A modified form of the control network 142 of FIG. 1 suitable for controlling the gain of a chrominance and a luminance amplifier having characteristics such as shown in FIG. 3 is shown in FIG. 4. Similar portions of FIGS. 1 and 4 are identified by reference numbers having the same last two significant digits and primed (') designations. The modified portions of FIG. 1 shown in FIG. 4 include the series connection resistors 460 and 462 coupled between the emitter of transistor 452 to ground. The values of resistors 460 and 462 are selected so that a portion Av' of the DC control voltage v' developed at the emitter of transistor 452 is developed at the junction of resistors 460 and 462. Furthermore, the series connection of potentiometer 458 and variable resistor 459 is coupled between the junction of resistor 460 and 462 and a source of positive supply voltage AVO '.
From FIG. 4, the expression for control voltage vL ' developed at the wiper of potentiometer 456 is vL ' = v' + (vO '-v')K1 ' [10]where K1 ' is determined by the voltage division at the wiper of potentiometer 456. The expression for control voltage vC ' developed at the wiper of potentiometer 458 is VC ' = Av' + (AVO ' - Av')K 2 ' [11]
where K2 ' is determined by the voltage division at the wiper of potentiometer 458. By combining equations [8] and [10], ##EQU8## By combining equations [9] and [11], ##EQU9## The ratio of gL ' to gC ' is given by the expression ##EQU10## It is noted that this ratio is independent of DC control voltage v'. Therefore, gain control network 442 of FIG. 4 also allows for the adjustment of contrast while maintaining constant saturation.
It is noted that if A were made equal to 1, the arrangement gain control unit 442 would be suitable to control the gains of chrominance and luminance amplifiers having the characteristics shown in FIG. 2.
In FIG. 5, there is shown an amplifier suitable for use as luminance amplifier 130 of FIG. 1. The amplifier includes a differential amplifier comprising NPN transistors 532 and 534. The commonly coupled emitters of transistors 532 and 534 are coupled to the collector of an NPN transistor 528. The emitter of transistor 528 is coupled via a resistor 530 to ground. The collector of transistor 532 and the collector of transistor 534, via load resistor 536, is coupled to a bias voltage provided by bias supply 546, illustrated as a series connection of batteries. The bases of transistors 532 and 534 are respectively coupled to a lower bias voltage through resistors 533 and 535 respectively.
An input signal, such as, for example, the output signal provided by first luminance processing circuit 129 of FIG. 1 is coupled to the base of transistor 532 via terminal 542. The output signal of the amplifier is developed at the collector of transistor 534 and coupled to output terminal 544.
A DC control voltage, such as vL provided by gain control unit 142 of FIG. 1, is coupled to the base of an NPN transistor 514, arranged as an emitter-follower, via terminal 512. The collector of transistor 514 is coupled to bias supply 546. The emitter of transistor 514 is coupled to ground through the series connection of resistor 516, a diode connected transistor 518 and resistor 520.
The anode of diode 520 is coupled to the base of an NPN transistor 538. The collector of transistor 538 is coupled to the collector of transistor 534 while its emitter is coupled to ground through resistor 540. Transistor 538, resistor 540, diode 518 and resistor 520 are arranged in a current mirror configuration.
The emitter of transistor 514 is coupled to the base of a PNP transistor 522. The emitter of transistor 522 is coupled to bias supply 546 while its collector is coupled to the base of transistor 528 and to ground through the series connection of a diode connected transistor 524 and resistor 526. Transistor 528, resistor 530, diode 524 and resistor 526 are arranged in a current mirror configuration
In operation, the DC control voltage coupled to terminal 512 is coupled in inverted fashion to the anode of diode 524 by transistor 522. As a result, current directly related to the voltage developed at the anode of diode 524 flows through diode 524 and resistor 526. Due to the operation of the current mirror arrangement of diode 524, resistor 526, transistor 528 and resistor 530, a similar current flows through the emitter circuit of transistor 528. The gain of the differential amplifier comprising transistors 532 and 534 is directly related to this current flowing in the emitter circuit of transistor 528, and therefore is inversely related to the DC control voltage at terminal 512. The gain versus DC control voltage characteristics of the differential is similar to gL shown in FIG. 2.
Further, a current is developed through the series connection of resistor 516, diode 518 and resistor 520 in direct relationship to the DC control coupled to terminal 512. A similar current is developed through resistor 540 due to the operation of the current mirror comprising diode 518, resistor 520, transistor 538 and resistor 540. This current is of the opposite sense to that provided by the current mirror arrangement of diode 524, resistor 526, transistor 528 and resistor 530 and is coupled to the collector of transistor 534 so that the DC voltage at output terminal 544 does not substantially vary with the DC control voltage.
In FIG. 6, ther
e is shown an amplifier suitable for use as chroma amplifier 120 of FIG. 1. The amplifier shown in FIG. 6 is of the type described in U.S. patent application Ser. No. 530,405 entitled "Controllable Gain Signal Amplifier," fled by L.A. Harwood et al. on Dec. 6, 1974. The amplifier comprises a differential amplifier including NPN transistors 624 and 625 having their bases coupled to terminal 603 via a resistor 626. Chrominance signals, provided by a source of chrominance signals such as chrominance processing unit 120 of FIG. 1, are coupled to terminal 603. The current conduction paths between the collectors and emitters of transistors 624 and 625 are respectively coupled to ground via resistors 628, 629 and 630.
A current splitter circuit comprising an NPN transistor 632 and a diode 634 is coupled to the collector of transistor 624. Diode 634 and the base-emitter junction of transistor 632 are poled in the same direction with respect to the flow of collector current in transistor 624. It desirable that conduction characteristics of transistor 632 and diode 635 be substantially matched. Similarly, the collector of transistor 625 is coupled to a second current splitter comprising a transistor 633 and a diode 635.
An output load circuit comprising series connected resistors 636 and 638 is coupled between the collector of transistor 632 and a source of operating voltage provided by bias supply 610. Amplified chrominance signals are provided at output terminal 640 for coupling, for example, to a chroma demodulator such as chroma demodulator 124 of FIG. 1. Similarly, series connected load resistors 637 and 639 are coupled between the collector of transistor 633 and bias supply 610. An output terminal 641 at the junction of resistors 637 ad 639 provides oppositely phased chrominance signals to those provided at terminal 640. The gain associated with the cascode combination of transistors 624 and 632 is controlled in response to a DC control voltage, such as, for example, vC provided by gain control unit 142 of FIG. 1, coupled to the base of an NPN transistor 646 via terminal 602. Direct control current is supplied from the emitter of transistor 646 to diode 634 and 635 via a series resistor 652. A signal by-pass circuit comprising a series resonant combination 654 of inductance and capacitance is coupled from the anode of diode 634 to ground. Resonant circuit 654 is tuned, for example, to 3.58 MHz to provide a low impedance path to ground for color subcarrier signals.
In operation, a quiescent operating current is provided through resistor 630. In the absence of an input signal at terminal 603, this current will divide substantially equally between the similarly biased transistors 624 and 625. If the DC control voltage at terminal 602 is near ground potential, transistor 646 will be effectively cut off and no current will flow in resistor 652 and diodes 634 and 635. In that case, neglecting the normally small difference betweeen collector and emitter currents of NPN transistors, the collector currents of transistors 624 and 625 will flow, respectively, in transistors 632 and 633. The transistors 632 and 633 are operated in common base mode and form cascode signal amplifiers with respective transistors 624 and 625. With the DC control voltage near ground potential, one-half of the quiescent current from resistor 630 flows in each of the load circuits and maximum gain for chrominance signals supplied from terminal 603 is provided.
Transistor 646 will conduct when the DC control voltage approaches the bias voltage supplied to the bases of transistors 632 and 633 of the current splitters. By selection of the circuit parameters, diodes 634 and 635 may be arranged to operate in a range between cut off to the conduction of all of the quiescent operating current supplied via resistor 630, thereby cutting off transistors 632 and 633 to provide no output signals at terminals 640 and 641.
At a DC control voltage intermediate to that corresponding to cut off of transistors 632 and 633 on the one hand and cut off of diodes 634 and 635 on the other hand, the voltage gain of the illustrated amplifier will vary in a substantially linear manner with the DC control voltage.
It is noted that although the characteristics shown in FIGS. 2 and 3 were reversed S-shaped characteristics, the characteristics could have other shapes including linear portions. For example, the characteristics could be substantially linear. Furthermore, with reference to FIG. 3, although gC ' was shown as having a linear portion that had a cut off control voltage lower than the cut off control voltage of the linear portion of gL ', the cut off control voltage of the linear portion of gC ' could be greater than the cut off voltage for the linear region of gL '. In addition, the gain control units and associate amplifiers could be arranged to utilize voltages opposite in polarity to those shown. These and other modifications are intended to be within the scope of the invention. PHILCO TX927 COLOR "ANTRANCITE" CHASSIS TX 10 (CHASSIS THORN TX10) TDA1170 vertical deflection FRAME DEFLECTION INTEGRATED CIRCUIT
circuits designed for use in TV vertical deflection systems. They are manufactured using
the Fairchild Planar* process.
Both devices are supplied in the 12-pin plastic power package with the heat sink fins bent
for insertion into the printed circuit board.
The TDA1170 is designed primarily for large and small screen black and white TV
receivers and industrial TV monitors. The TDA1270 is designed primarily for driving
complementary vertical deflection output stages in color TV receivers and industrial
monitors.
APPLICATION INFORMATION (TDA1170)
The vertical oscillator is directly synchronized by the sync pulses (positive or negative); therefore its free
running frequency must be lower than the sync frequency. The use of current feedback causes the yoke
current to be independent of yoke resistance variations due to thermal effects, Therefore no thermistor is
required in series with the yoke. The flyback generator applies a voltage, about twice the supply voltage, to
the yoke. This produces a short flyback time together with a high useful power to dissipated power
ratio.
1. A transformerless output vertical deflection circuit, comprising a vertical oscillator circuit for generating a vertical pulse train in response to vertical synchronizing pulses applied thereto, a sawtooth signal generator for generating a series of sawtooth signals, each cycle of said sawtooth signal including a pulse component, a vertical output circuit coupled to said sawtooth generator for amplifying said sawtooth signal including said pulse component and loading a vertical deflection coil, and stabilizing means connected between said vertical oscillator and said sawtooth signal generator for varying the width of the pulse component which is to be fed to said vertical output circuit in response to the average level of DC output voltage fed from the vertical output circuit. 2. A transformerless output vertical deflection circuit claimed in claim 1, wherein said stabilizing means comprises a control circuit means for receiving a series of pulses from the vertical oscillator and a feedback signal from the vertical output circuit and for varying the width of the pulse which is to be fed to the vertical output circuit in response to a DC control signal proportional to the width of the pulse component included in the vertical output signal and smoothing circuit means connected between said vertical output circuit and said stabalizing means for smoothing said feedback signal. 3. A transformerless output vertical deflection circuit claimed in claim 2, wherein said control circuit comprises a charging capacitor which is parallel to a transistor, said transistor being switched on in response to pulses fed from the vertical oscillator wherein said capacitor is charged by the voltage fed from said smoothing circuit, and discharged in response to conduction of the transistor, a differential amplifier circuit which receives the voltage on said capacitor and a fixed voltage, and a gating circuit for producing a pulse which has a width equal to the difference between the width of the pulse fed from the vertical oscillator circuit and the width of pulse fed from the differential amplifier circuit. 4. A transformerless output vertical deflection circuit claimed in claim 2, wherein said control circuit comprises a capacitor which is charged by a fixed power source and is discharged by means of a switching transistor operated by the pulses fed from the vertical oscillator circuit and a differential amplifier circuit receiving the voltage on the capacitor and the output of said smoothing circuit. 5. A transformable output vertical deflection circuit comprising a vertical oscillator for generating a vertical pulse train in response to vertical synchronizing pulses applied thereto, a sawtooth signal generator for generating a series of sawtooth signals each cycle of said sawtooth signal including a pulse component, a vertical output circuit for amplifying said sawtooth signal including said pulse component and loading a vertical deflection coil, and pulse stabilizing means coupled between the vertical oscillator circuit a
Description:
BACKGROUND OF THE INVENTION
The present invention relates to a vertical deflection circuit for use in a television receiver and, more particularly, to a vertical deflection circuit of a type wherein no vertical output transformer is employed. This type of vertical deflection circuit with no output transformer is generally referred to as an OTL (Output Transformerless) type vertical deflection circuit.
It is known that variation of the pulse width of the flyback pulse produced in a vertical output stage of the vertical deflection circuit is the cause in the raster on the television picture tube, of a white bar, flicker, jitter, line crowding and/or other raster disorders. In addition thereto, in the vertical deflection output circuit where the output stage is composed of a single-ended push-pull amplifier having a vertical output transistor, an excessive load is often imposed on the output transistor and, in an extreme case, the output transistor is destroyed.
TDA2576 SYNC COMBINATION WITH TRANSMITTER IDENTIFICATION (CHASSIS THORN TX10)
AND VERTICAL 625 DIVIDER SYSTEM
GENERAL DESCRIPTION
The TDA2576 B is a monolithic integrated circuit for use in colour television receivers with switched-
mode driven or self-regulating horizontal time-base circuits. It is designed in combination with the
TDA2581 to operate as a matched pair. When supplied with a composite video signal the TDA2576 B
delivers drive pulses for the TDA2581 and sync pulses for the vertical deflection. The circuit is
optimized for a horizontal and vertical frequency ratio of 625. It incorporates the following features:
O Horizontal sync separator (including noise inverter) I
O Horizontal phase detector
0 Horizontal oscillator (31,25 kHz)
0 Sandcastle pulse generator
O Vertical sync pulse separator
O Very stable automatic vertical synchronization due to the 625 divider system, without delay after
channel change
I Three voltage level sensor on coincidence detector circuit output
I Video transmitter identification circuit for sound muting and search tuning systems
O Inhibit of vertical sync pulse when no video transmitter is detected
QUICK REFERENCE DATA
Supply voltage _
horizontal (pin 14) V14_13 typ. 12 V
vertical (pin 18) V13_13 typ. 12 V
Supply current (pin 14 + pin 18) V14+18 typ. 52 mA
Sync separator
input voltage level (peak-to-peak value) V2.131p.p) 0,07 to I V
slicing level typ. 50 % _
Output pulse E
horizontal (peak-to-peak value) V3_131p_p1 min. 10 V =
vertical sync (peak-to-peak value) V1_131p_p1 min. 10 V —
burst key (peak-to~peak value) V15_131p_p1 min. 10 V
Video transmitter identification circuit
Output voltage (pin 10)
sync pulse present V10_13 typ. 8 V
no sync pulse V1Q_13 max. 1 V
Phase locked loop
control sensitivity typ. 2000 Hz/;1s
holding range Af typ. 1 1000 Hz
catching range Af typ. : 900 Hz
Operating ambient temperature range Tamb -25 to + 65 °C
PACKAGE OUTLINE
18-lead DIL; plastic (SOT-102A).
FUNCTIONAL DESCRIPTION
The video input voltage to drive the sync separator must have negative-going sync, which can be
obtained from synchronous demodulators such as TDA2540, TDA2541 and TDA2670.
The slicing level of the sync separator is determined by the value of the resistor between pins 3 and 4.
A 5,6 kfl resistor provides a slicing level midway between the top sync level and the blanking level.
Thus the slicing level is independent of the amplitude of the sync pulse input at pin 2.
The nominal top sync level at pin 2 is 1,5 V, and the amplitude selective noise inverter is activated at
0,7 V. The horizontal phase detector has a steepness of 1,2 V/its and together with the 1800 Hz/V of
the horizontal oscillator provides a total control steepness of 2000 Hz/us.
A second horizontal phase detector provides a 5,5 its pulse which ensures symmetrical gating of the
horizontal synchronization. During catching the gating is automatically switched off. At the same time
the flywheel filter is switched to a short time constant. The value of this time constant can be deter~
mined externally via pin 11.
When the indirect vertical sync output is generated by the 625 divider system an anti-top flutter pulse
switches off the equalizing and vertical sync pulse operation of the phase detector. Thus top flutter
distortion of the control voltage due to vertical pulses can be anticipated. When the 625 divider system
is in the direct mode the anti~top flutter pulse is inhibited.
The free running output frequency of the horizontal oscillator is 31,25 kl-lz. The vertical frequency
output is obtained by dividing this double horizontal frequency by 625. The double horizontal
frequency is fed via a binary divider to provide the normal 15,625 kHz horizontal output at pin 8. The
trailing edge of this pulse is positioned 0,9 us after the end of the video sync pulse input at pin 2
(see Fig. 2).
0 625 divider
0 In/out-sync detector
I Direct/indirect sync switch
O Identification circuit
It is fed by a signal obtained by integration of the composite sync signal and an internally generated,
clipped video signal. The vertical sync pulse is sliced out of this integrated signal by an automatically
biased clipper. The videopart of the signal helps to build up a vertical sync pulse when heavy negative-
going reflections (mountains) distort the video signal. The in/out sync-detector considers a signal
out~of-sync when fifteen or more successive incoming vertical sync pulses are not in phase with a
reference signal from the 625 divider. Therefore a distorted vertical sync signal needs only one
out-of-fifteen pulses to be in phase to keep the system in sync. When the sixteenth successive out-of-
sync pulse is detected, the direct/indirect sync switch is activated to feed the vertical sync signal
directly out of the block at pin 2 (direct sync vertical output).
At the same time the 625 divider is reset by one of the sync pulses. After the reset pulse, if the 7th
sliced vertical sync pulse coincides with a 625 divider window, the sync output pulse is presented
again by the divider system and switch-over to indirect mode occurs.
In the direct mode, every 7th non-coinciding sliced vertical sync pulse will reset the counter. Thus a
non-standard video signal will result in continuous reset pulses and the direct/indirect switch will
remain in the direct position.
To avoid delay in vertical synchronization, caused by waiting time of the divider circuit after channel
change or an unsynchronized camera change in the studio, information is fed from the horizontal coin-
cidence detector to the automatic switch for the vertical sync pulse. The loss of horizontal synchroni-
zation sets the automatic switch to direct vertical sync. When horizontal coincidence is detected again
the setting of the automatic switch depends on whether a standard video signal is received or not. When
an external voltage between 2,5 V and 7,25 V is applied via pin 12 to the coincidence detector, the hor-
izontal phase detector is swsync. A voltage level on pin 12 > 8,25 V switches the horizontal phase detector to a short time constant,
without affecting the indirect/direct vertical sync system which remains operational.
The video transmitter identification circuit detects when a sync pulse occurs during the internal gating
pulse. This indicates the presence of a video transmitter and results in the capacitor connected to pin
10 being charged to 8 V. When no sync pulse is present the capacitor discharges to < 1 V. The voltage
at pin 10 is compared with an internal d.c. voltage. The identification output at pin 9 is active when
pin 10 is < 1,6 V (no video transmitter) and inactive (high impedance) when pin 10 is > 3,5 V.
The vertical sync output pulse at pin 1 is inhibited when no video transmitter is identified, which
prevents interference or noise affecting the frequency of the vertical output stage. This results in a vertical stable picture, plus vertical stable position information of tuning systems.
TDA2541 IF AMPLIFIER WITH DEMODULATOR AND AFC
DESCRIPTION
The TDA2540 and 2541 are IF amplifier and A.M.
demodulator circuits for colour and black and white
television receivers using PNP or NPN tuners. They
are intended for reception of negative or positive
modulation CCIR standard.
They incorporate the following functions : .Gain controlled amplifier .Synchronous demodulator .White spot inverter .Video preamplifier with noise protection .Switchable AFC .AGC with noise gating .Tuner AGC output (NPN tuner for 2540)-(PNP
tuner for 2541) .VCR switch for video output inhibition (VCR
play back).
.SUPPLYVOLTAGE : 12V TYP
.I.F. INPUT VOLTAGE SENSITIVITY AT
F = 38.9MHz : 85mVRMS TYP
.VIDEO OUTPUT VOLTAGE (white at 10% of
top synchro) : 2.7VPP TYP
.I.F. VOLTAGE GAIN CONTROL RANGE :
64dB TYP .SIGNAL TO NOISE RATIO AT VI = 10mV :
58dB TYP
.A.F.C. OUTPUT VOLTAGE SWING FOR
Df = 100kHz : 10V TYP.
PHILCO TX927 COLOR "ANTRANCITE" CHASSIS TX 10 Horizontal deflection output circuit:
A horizontal deflection output circuit, such as used in a TV receiver or a display device, includes a series circuit composed of a ringing preventing resistor and a one-way switching element connected in parallel with a linearity correcting coil. That one-way switching element is turned on at the beginning of a horizontal scanning period to feed a current to the ringing preventing resistor but is turned off in the vicinity of a fly-back period to block the flow of the current to the ringing preventing resistor. Thus, the power loss due to the current flowing through the ringing preventing resistor for the fly-back period can be reduced according to the present invention.
a switching element;
a resonant capacitor connected in parallel with said switching element; and
a first series circuit connected in parallel with said switching element and including a horizontal deflection coil and a linearity correcting coil,
wherein the improvement comprises:
a second series circuit connected in parallel with said linearity correcting coil, said second series circuit comprising load means for damping resonance energy in said first series circuit and current control means for limiting the current flow through said load means to the first half of a horizontal scanning period and including a one-way switching element which turns on for a first half of said horizontal scanning period and turns off for the last half of the horizontal scanning period and for a fly-back pulse period, thereby limiting current flow through said load means to the first half of said horizontal scanning period.
2. A horizontal deflection output circuit according to claim 1, wherein said load means includes a resistor. 3. A horizontal deflection output circuit according to claim 2, wherein a capacitor is connected in parallel with said linearity correcting coil. 4. A horizontal deflection output circuit according to claim 2, wherein said one-way switching element is a diode. 5. A horizontal deflection output circuit according to claim 1, wherein said load means includes: a resistor; and current adjusting means for adjusting the current to flow through said resistor. 6. A horizontal deflection output circuit comprising:
a switching element;
a resonant capacitor connected in parallel with said switching element;
a series circuit connected in parallel with said switching element and including a horizontal deflection coil and a linearity correcting coil; and
7. A horizontal deflection output circuit according to claim 6, wherein a capacitor is connected in parallel with said linearity correcting coil. 8. A horizontal deflection output circuit according to claim 6, wherein said one-way switching element is turned off at least for a fly-back pulse period. 9. A horizontal deflection output circuit according to claim 6, wherein said one-way switching element is a diode. 10. A horizontal deflection output circuit according to claim 6, wherein said bias voltage feeding means includes resistance voltage-dividing means for dividing the voltage between the two terminals of said linearity correcting coil. 11. A horizontal deflection output circuit according to claim 10, wherein a capacitor is connected in parallel with said linearity correcting coil. 12. A horizontal deflection output circuit according to claim 10, wherein said one-way switching element is turned off at least for a fly-back pulse period. 13. A horizontal deflection output circuit according to claim 10, wherein said one-way switching element is a diode. 14. A horizontal deflection output circuit according to claim 10, wherein said bias voltage feeding means includes a time constant circuit composed of a resistor and a capacitor. 15. A horizontal deflection output circuit according to claim 14, wherein a capacitor is connected in parallel with said linearity correcting coil. 16. A horizontal deflection output circuit according to claim 14, wherein said one-way switching element is a diode. 17. A horizontal deflection output circuit according to claim 14, wherein said one-way switching element is turned off at least for a fly-back pulse period. 18. A horizontal deflection output circuit comprising:
a switching element;
a damper diode connected in parallel with said switching element;
a resonant capacitor connected in parallel with said switching element;
a first series circuit connected in parallel with said switching element and including a horizontal deflection coil and a linearity correcting coil;
a choke coil connected with the cathode terminal of said damper diode; and
a d.c. current blocking capacitor connected in series with said horizontal deflection coil.
19. A horizontal deflection output circuit according to claim 18, wherein said choke coil is a fly-back transformer. 20. A horizontal deflection output circuit according to claim 19, wherein said load means includes a resistor. 21. A horizontal deflection output circuit according to claim 20, wherein a capacitor is connected in parallel with said linearity correcting coil. 22. A horizontal deflection output circuit according to claim 20, wherein said one-way switching element is a diode. 23. A horizontal deflection output circuit according to claim 19, wherein said load means includes: a resistor; and current adjusting means for adjusting the current to flow through said resistor. 24. A horizontal deflection output circuit comprising:
a switching element;
a damper diode connected in parallel with said switching element;
a resonant capacitor connected in parallel with said switching element;
a series circuit connected in parallel with said switching element and including a horizontal deflection coil and a linearity correcting coil;
a series circuit connected in parallel with said linearity correcting coil and including load means and a one-way switching element adapted to be turned on for the front half of a horizontal scanning period, said load means including a resistor and current adjusting means for adjusting the current flow through said resistor, said current adjusting means including a transistor connected in series with said resistor and bias voltage feeding means for feeding a bias voltage to the base of said transistor;
a choke coil in the form of a fly-back transformer connected with the cathode terminal of said damper diode; and
a d.c. current blocking capacitor connected in series with said horizontal deflection coil.
25. A horizontal deflection output circuit according to claim 24, wherein said one-way switching element is turned off at least for a fly-back pulse period. 26. A horizontal deflection output circuit according to claim 24, wherein a capacitor is connected in parallel with said linearity correcting coil. 27. A horizontal deflection output circuit according to claim 24, wherein said one-way switching element is a diode. 28. A horizontal deflection output circuit according to claim 24, wherein said bias voltage feeding means includes resistance voltage-dividing means for dividing the voltage between the two terminals of said linearity correcting coil. 29. A horizontal deflection output circuit according to claim 28, wherein said bias voltage feeding means includes a time constant circuit composed of a resistor and a capacitor. 30. A horizontal deflection output circuit according to claim 28, wherein said one-way switching element is turned off at least for a fly-back pulse period. 31. A horizontal deflection output circuit according to claim 28, wherein a capacitor is connected in parallel with said linearity correcting coil. 32. A horizontal deflection output circuit according to claim 28, wherein said one-way switching element is a diode.
Description:
BACKGROUND OF THE INVENTIONIn a conventional TV receiver, a horizontal deflection current having a saw-tooth waveform reaches saturation as it approaches its maximum, causing a problem in that the scanning rate of the electron beam is reduced at the extreme right-hand side, as viewed toward the frame of the display, so that the picture reproduced on the face plate is distorted.
The circuit for solving the above-specified problem to form a symmetrical picture is called a "linearity correcting circuit". In order to correct the linearity of the raster scanned on the face plate, the linearity correcting circuit of the prior art is equipped with a linearity correcting coil which is connected in series with a horizontal deflection coil. That linearity correcting coil is so magnetically biased by means of a permanent magnet that its magnetic saturation characteristics are set differently depending upon the direction of the horizontal deflection current. This horizontal deflection circuit is exemplified by Japanese Patent Laid-Open Nos. 40615/1982, 128949/1981, 124850/1980 and U.S. Pat. No. 3,962,603, as shown schematically in FIGS. 1A and 1B.
As shown in FIG. 1A, the horizontal deflection circuit is composed of an input terminal 1, an output transistor 2, a damper diode 3, a resonant capacitor 4, a horizontal deflection coil 5, a linearity correcting coil 6, an S-shaped correction capacitor 7, a choke coil 8, a supply terminal 9, and a permanent magnet 12 for setting the magnetic bias of the linearity correcting coil 6.
The permanent magnet 12 has its polarity arranged so as to apply a magnetic field in the same direction as that of the magnetic field established in the linearity correcting coil in case a horizontal deflection current IDY flows in the direction of arrow a to the horizontal deflection coil 5.
In case the horizontal deflection current IDY flows in the direction of the arrow a, therefore, the linearity correcting coil 6 is more liable to be magnetically saturated than when the horizontal deflection current IDY flows in the reverse direction.
As a result, the inductance of the linearity correcting coil 6 is least in the vicinity of the maximum of the horizontal deflection current so that this current increases.
Thus, the drop of the scanning rate of the electron beam at the right side of the display frame is corrected. In the display, however, the use of a linearity correcting coil will form longitudinal shading streaks at the left side of the display frame. Those streaks are formed as a result of the fact that a ringing current is established in the horizontal deflection current by the resonance of a resonant circuit which is composed of the inductance of the linearity coil 6 and a stray capacity 17, as shown in FIG. 1B.
As the horizontal deflection current has its frequency increased and its output raised in accordance with the fineness in the structure of the display, however, there arises another problem that the power loss at the ringing current preventing resistor is increased. SUMMARY OF THE INVENTION
PHILCO TX927 COLOR "ANTRANCITE" CHASSIS TX10 (CHASSIS THORN TX10) Horizontal deflection circuit with a start-up power supply
I
n a horizontal deflection circuit, a horizontal oscillator, energized by a supply voltage, develops a horizontal frequency switching signal. A deflection outputs stage is responsive to the switching signal and generates scanning current in a horizontal deflection winding. After commencement of oscillator operation, the voltage developed across a secondary winding of a flyback transformer is rectified and filtered and applied to the horizontal oscillator as the oscillator energizing supply voltage. A start-up supply for developing the oscillator supply voltage during an initial interval includes a source of voltage that is available for use prior to the commencement of oscillator operation, a capacitor, a charging circuit for charging the capacitor from the available voltage source, and a controllable switch coupled to the capacitor and to the oscillator. After the charging circuit has charged the capacitor to a predetermined threshold voltage level, the controllable switch is made conductive to apply the capacitor voltage to the oscillator to commence oscillator operation. The switch is arranged with the capacitor as a relaxation oscillator to begin discharging the capacitor by the load current drawn by the horizontal oscillator. Should the capacitor discharge to a lower threshold level before the flyback-derived supply voltage is developed, the relaxation oscillator changes states to disconnect the horizontal oscillator from the capacitor to initiate a capacitor recharging cycle.
1. An oscillator-derived power supply with start-up circuitry, comprising:
a supply terminal;
an oscillator being energized by the voltage developed at said supply terminal for producing an oscillator output signal;
a start-up voltage supply to energize said oscillator into commencing operation, said start-up voltage supply comprising:
a capacitor,
a source of DC input voltage available prior to commencement of oscillator operation,
means for charging said capacitor from said DC input voltage source, and
switching means interposed between said capacitor and said supply terminal for applying said capacitor voltage to said oscillator after said capacitor has charged to a first threshold level, to commence oscillator operation;
means responsive to said oscillator output signal for developing a steady-state voltage; and
means for applying said steady-state voltage to said supply terminal via said switching means to maintain oscillator energization during steady-state operation.
2. A supply according to claim 1 wherein the minimum load current required by said oscillator to commence operation exceeds in magnitude the current being provided to said capacitor by said charging means. 3. A supply according to claim 2 wherein said capacitor is being discharged to lower voltage by said oscillator after said switching means applies said capacitor voltage to said supply terminal and prior to steady-state oscillator operation. 4. A supply according to claim 3 wherein said steady-state voltage maintains said capacitor charged to a substantially constant voltage level during said steady-state operation. 5. A supply according to claim 4 wherein said DC input voltage is of greater magnitude than the magnitude of said substantially constant voltage level. 6. A supply according to claim 4 wherein said switching means serves to disconnect said capacitor from said supply terminal when said capacitor discharges to a second threshold level lower than said first threshold level to enable said capacitor to recharge. 7. A supply according to claim 6 wherein said steady-state voltage applying means comprises a diode blocking current flow from said charging means to said steady-state voltage developing means. 8. A supply according to any preceding claim wherein said oscillator comprises a deflection generator oscillator and wherein said oscillator output signal responsive means comprises a deflection generator output stage, a flyback transformer coupled to said output stage for developing a flyback pulse voltage across a transformer secondary winding, and rectifying and filtering means for developing said steady-state voltage from said flyback pulse voltage. 9. A deflection circuit-derived power supply with a start-up supply for the deflection circuit oscillator, comprising:
a horizontal oscillator energized by a supply voltage for developing a horizontal frequency switching signal after commencement of oscillator operation;
a horizontal deflection winding;
a deflection output stage responsive to said horizontal frequency switching signal for generating scanning current in said deflection winding;
a flyback transformer having a first winding coupled to said deflection output stage for developing a horizontal frequency alternating polarity output voltage across a plurality of secondary windings;
supply voltage producing means responsive to the horizontal frequency alternating polarity output voltage developed across one of said plurality of secondary windings for producing said supply voltage after commencement of horizontal oscillator operation; and
a start-up supply for developing said supply voltage during an initial interval to enable said horizontal oscillator to commence operation, said start-up supply comprising:
a source of voltage available prior to commencement of horizontal oscillator operation,
a capacitor,
means for charging said capacitor from said prior available voltage source, and
switching means coupled to said capacitor and to said horizontal oscillator for applying said capacitor voltage to said horizontal oscillator as said supply voltage to commence horizontal oscillator operation after said charging means has charged said capacitor to an upper threshold voltage level, said switching means arranged with said capacitor as a relaxation oscillator that begins discharging said capacitor by the load current drawn by said horizontal oscillator after said charging means has charged said capacitor to said upper threshold voltage level and begins recharging said capacitor from said charging means when said capacitor discharges to a lower threshold voltage level.
10. A supply according to claim 9 wherein said switching means comprises a first transistor interposed between said capacitor and said horizontal oscillator and a second transistor coupled to said capacitor and to a control electrode of said first transistor. 11. A supply according to claim 9 wherein said supply voltage producing means comprises means for rectifying and filtering said horizontal frequency alternating polarity output voltage and means for applying the output of said rectifying and filtering means to said capacitor to develop said supply voltage as a substantially constant voltage across said capacitor. 12. A supply according to claim 11 wherein said prior available voltage source comprises a source of DC input voltage of magnitude greater than said substantially constant voltage.
PHILCO TX927 COLOR "ANTRANCITE" CHASSIS TX10 (CHASSIS THORN TX10) CIRCUIT ARRANGEMENT IN A PICTURE DISPLAY DEVICE UTILIZING A STABILIZED SUPPLY VOLTAGE CIRCUIT:TDA2581 CONTROL CIRCUIT FOR SMPS/PHILIPS POWER PACK:
The TDA2581 is a monolithic integrated circuit for controlling switched-mode power supplies (SMPS) which are provided with the drive for the horizontal deflection stage.
The circuit features the following:
— Voltage controlled horizontal oscillator.
— Phase detector.
— Duty factor control for the positive-going transient of the output signal.
— Duty factor increases from zero to its normal operation value.
— Adjustable maximum duty factor.
- Over-voltage and over-current protection with automatic re-start after switch-off.
— Counting circuit for permanent switch-off when n~times over~current or over-voltage is sensed
-Protection for open-reference voltage.
- Protection for too low supply voltage.
Protection against loop faults.
Positive tracking of duty factor and feedback voltage when the feedback voltage is smaller than the
reference voltage minus 1,5 V.
A stabilized supply voltage circuit for a picture display device comprising a chopper wherein the switching signal has the line frequency and is duration-modulated. The coil of the chopper constitutes the primary winding of a transformer a secondary winding of which drives the line output transistor so that the switching transistor of the chopper also functions as a driver for the line output stage. The oscillator generating the switching signal may be the line oscillator. In a special embodiment the driver and line output transistor conduct simultaneously and in order to limit the base current of the line output transistor a coil shunted by a diode is incorporated in the drive line of the line output transistor. Other secondary windings of the transformer drive diodes which conduct simultaneously with the efficiency diode of the chopper so as to generate further stabilized supply voltages.
Description:
The invention relates to a circuit arrangement in a picture display device wherein the input direct voltage between two input terminals, which is obtained be rectifying the mains alternating voltage, is converted into a stabilized output direct voltage by means of a switching transistor and a coil and wherein the transistor is connected to a first input terminal and an efficiency diode is connected to the junction of the transistor and the coil. The switching transistor is driven by a pulsatory voltage of line frequency which pulses are duration-modulated in order to saturate the switching transistor during part of the period dependent on the direct voltage to be stabilized and to cut off this transistor during the remaining part of the period. The pulse duration modulation is effected by means of a comparison circuit which compares the direct voltage to be stabilized with a substantially constant voltage, the coil constituting the primary winding of a transformer.
Such a circuit arrangement is known from German "Auslegeschrift" 1.293.304. wherein a circuit arrangement is described which has for its object to convert an input direct voltage which is generated between two terminals into a different direct voltage. The circuit employs a switch connected to the first terminal of the input voltage and periodically opens and closes so that the input voltage is converted into a pulsatory voltage. This pulsatory voltage is then applied to a coil. A diode is arranged between the junction of the switch and the coil and the second terminal of the input voltage whilst a load and a charge capacitor in parallel thereto are arranged between the other end of the coil and the second terminal of the input voltage. The assembly operates in accordance with the known efficiency principle i.e., the current supplied to the load flows alternately through the switch and through the diode. The function of the switch is performed by a switching transistor which is driven by a periodical pulsatory voltage which saturates this transistor for a given part of the period. Such a configuration is known under different names in the literature; it will be referred to herein as a "chopper." A known advantage thereof, is that the switching transistor must be able to stand a high voltage or provide a great current but it need not dissipate a great power. The output voltage of the chopper is compared with a constant reference voltage. If the output voltage attempts to vary because the input voltage and/or the load varies, a voltage causing a duration modulation of the pulses is produced at the output of the comparison arrangement. As a result the quantity of the energy stored in the coil varies and the output voltage is maintained constant. In the German "Auslegeschrift" referred to it is therefore an object to provide a stabilized supply
voltage device.
In the circuit arrangement according to the mentioned German "Auslegeschrift" the frequency of the load variations or a harmonic thereof is chosen as the frequency for the switching voltage. Particularly when the load fed by the chopper is the line deflection circuit of a picture display device, wherein thus the impedance of the load varies in the rhythm of the line frequency, the frequency of the switching voltage is equal to or is a multiple of the line frequency.
It is to be noted that the chopper need not necessarily be formed as that in the mentioned German "Auslegeschrift." In fact, it is known from literature that the efficiency diode and the coil may be exchanged. It is alternatively possible for the coil to be provided at the first terminal of the input voltage whilst the switching transistor is arranged between the other end and the second terminal of the input voltage. The efficiency diode is then provided between the junction of said end and the switching transistor and the load. It may be recognized that for all these modifications a voltage is present across the connections of the coil which voltage has the same frequency and the same shape as the pulsatory switching voltage. The control voltage of a line deflection circuit is a pulsatory voltage which causes the line output transistor to be saturates and cut off alternately. The invention is based on the recognition that the voltage present across the connections of the coil is suitable to function as such a control voltage and that the coil constitutes the primary of a transformer. To this end the circuit arrangement according to the invention is characterized in that a secondary winding of the transformer drives the switching element which applies a line deflection current to line deflection coils and by which the voltage for the final anode of a picture display tube which forms part of the picture display device is generated, and that the ratio between the period during which the switching transistor is saturated and the entire period, i.e., the switching transistor duty cycle is between 0.3 and 0.7 during normal operation.
The invention is also based on the recognition that the duration modulation which is necessary to stabilize the supply voltage with the switching transistor does not exert influence on the driving of the line output transistor. This resides in the fact that in case of a longer or shorter cut-off period of the line output transistor the current flowing through the line deflection coils thereof is not influenced because of the efficiency diode current and transistor current are taken over or, in case of a special kind of transistor, the collector-emitter current is taken over by the base collector current and conversely. However, in that case the above-mentioned ratios of 0.3 : 0.7 should be taken into account since otherwise this take-over principle is jeopardized.
As will be further explained the use of the switching transistor as a driver for the line output transistor in an embodiment to be especially described hereinafter has the further advantage that the line output transistor automatically becomes non-conductive when this switching transistor is short circuited so that the deflection and the EHT for the display tube drop out and thus avoid damage thereof.
Due to the step according to the invention the switching transistor in the stabilized supply functions as a driver for the line deflection circuit. The circuit arrangement according to the invention may in addition be equipped with a very efficient safety circuit so that the reliability is considerably enhanced, which is described in the U.S. Pat. No. 3,629,686. The invention is
furthermore based on the recognition of the fact that the pulsatory voltage present across the connections of the coil is furthermore used and to this end the circuit arrangement according to the invention is characterized in that secondary windings of the transformer drive diodes which conduct simultaneously with the efficiency diode so as to generate further stabilized direct voltages, one end of said diodes being connected to ground.
In order that the invention may be readily carried into effect, a few embodiments thereof will now be described in detail by way of example with reference to the accompanying diagrammatic drawings in which:
FIG. 1 shows a principle circuit diagram wherein the chopper and the line deflection circuit are further shown but other circuits are not further shown.
FIGS. 2a, 2b and 2c show the variation as a function of time of two currents and of a voltage occurring in the circuit arrangement according to FIG. 1.
FIGS. 3a 3b, 3c and 3d show other embodiments of the chopper.
FIGS. 4a and 4b show modifications of part of the circuit arrangement of FIG. 1.
In FIG. 1 the reference numeral 1 denotes a rectifier circuit which converts the mains voltage supplied thereto into a non-stabilized direct voltage. The collector of a switching transistor 2 is connected to one of the two terminals between which this direct voltage is obtained, said transistor being of the npn-type in this embodiment and the base of which receives a pulsatory voltage which originates through a control stage 4 from a modulator 5 and causes transistor 2 to be saturated and cut off alternately. The voltage waveform 3 is produced at the emitter of transistor 2. In order to maintain the output voltage of the circuit arrangement constant, the duration of the pulses provided is varied in modulator 5. A pulse oscillator 6 supplies the pulsatory voltage to modulator 5 and is synchronized by a signal of line frequency which originates from the line oscillator 6' present in the picture display device. This line oscillator 6' is in turn directly synchronized in known manner by pulses 7' of line frequency which are present in the device and originate for example from a received television signal if the picture display device is a television receiver. Pulse oscillator 6 thus generates a pulsatory voltage the repetition frequency of which is the line frequency.
The emitter of switching transistor 2 is connected at one end to the cathode of an efficiency diode 7 whose other end is connected to the second input voltage terminal and at the other end to primary winding 8 of a transformer 9. Pulsatory voltage 3 which is produced at the cathode of efficiency diode 7 is clamped against the potential of said second terminal during the intervals when this diode conducts. During the other intervals the pulsatory voltage 3 assumes the value V i . A charge capacitor 10 and a load 11 are arranged between the other end of winding 8 and the second input voltage terminal. The elements 2,7,8,10 and 11 constitute a so-called chopper producing a direct voltage across charge capacitor 10, provided that capacitor 10 has a sufficiently great value for the line frequency and the current applied to load 11 flowing alternately through switching transistor 2 or through efficiency diode 7. The output voltage V o which is the direct voltage produced across charge capacitor 10 is applied to a comparison circuit 12 which compares the voltage V o with a reference voltage. Comparison circuit 12 generates a direct voltage which is applied to modulator 5 so that the duration of the effective period δ T of switching transistor 2 relative to the period T of pulses 3 varies as a function of the variations of output voltage V 0 . In fact, it is readily evident that output voltage V o is proportional to the ratio δ :
V o = V i . δ
Load 11 of the chopper consists in the consumption of parts of the picture display device which are fed by output voltage V 0 . In a practical embodiment of the circuit arrangement according to FIG. 1 wherein the mains alternating voltage has a nominal effective value of 220 V and the rectified voltage V i is approximately 270 V, output voltage V o for δ = 0.5 is approximately 135 V. This makes it also possible, for example, to feed a line deflection circuit as is shown in FIG. 1 wherein load 11 then represents different parts which are fed by the chopper. Since voltage V o is maintained constant due to pulse duration modulation, the supply voltage of this line deflection circuit remains constant with the favorable result that the line amplitude(= the width of the picture displayed on the screen of the picture display tube) likewise remains constant as well as the EHT required for the final anode of the picture display tube in the same circuit arrangement independent of the variations in the mains voltage and the load on the EHT generator (= variations in brightness).
However, variations in the line amplitude and the EHT may occur as a result of an insufficiently small internal impedance of the EHT generator. Compensation means are known for this purpose. A possibility within the scope of the present invention is to use comparison circuit 12 for this purpose. In fact, if the beam current passes through an element having a substantially quadratic characteristic, for example, a voltage-dependent resistor, then a variation for voltage V o may be obtained through comparison circuit 12 which variation is proportional to the root of the variation in the EHT which is a known condition for the line amplitude to remain constant.
In addition this facilitates smoothing of voltage V o since the repetition frequency of pulsatory voltage 3 is many times higher than that of the mains and a comparatively small value may be sufficient for charge capacitor 10. If charge capacitor 10 has a sufficiently high value for the line frequency, voltage V o is indeed a direct voltage so that a voltage having the same form as pulsatory voltage 3 is produced across the terminals of primary winding 8. Thus voltages which have the same shape as pulsatory voltage 3 but have a greater or smaller amplitude are produced across secondary windings 13, 14 of transformer 9 (FIG. 1 shows only 2 secondary windings but there may be more). The invention is based on the recognition that one end of each secondary winding is connected to earth while the other end thereof drives a diode, the winding sense of each winding and the direction of conductance of each diode being chosen to be such that these diodes conduct during the same period as does efficiency diode 7. After smoothing, stabilized supply voltages, for example, at terminal 15 are generated in this manner at the amplitudes and polarities required for the circuit arrangements present in the picture display device. In FIG. 1 the voltage generated at terminal 15 is, for example, positive relative to earth. It is to be noted that the load currents of the supply voltages obtained in this manner cause a reduction of the switching power which is economized by efficiency diode 7. The sum of all diode currents including that of diode 7 is in fact equal to the current which would flow through diode 7 if no secondary winding were wound on transformer 9 and if no simultaneous diode were used. This reduction may be considered an additional advantage of the circuit arrangement according to the invention, for a diode suitable for smaller powers may then be used. However, it will be evident that the overall secondary load must not exceed the primary load since otherwise there is the risk of efficiency diode 7 being blocked so that stabilization of the secondary supply voltages would be out of the question.
It is to be noted that a parabola voltage of line frequency as shown at 28 is produced across the charge capacitor 10 if this capacitor is given a smaller capacitance so that consequently the so-called S-correction is established.
In FIG. 1 charge capacitors are arranged between terminals 15 etc. and earth so as to ensure that the voltages on these points are stabilized direct voltages. If in addition the mean value of the voltage on one of these terminals has been made equal to the effective value of the alternating voltage which is required for heating the filament of the picture display tube present in the picture display device, this voltage is suitable for this heating. This is a further advantage of the invention since the cheap generation of a stabilized filament voltage for the picture display tube has always been a difficult problem in transistorized arrangements.
A further advantage of the picture display device according to the invention is that transformer 9 can function as a separation transformer so that the different secondary windings can be separated from the mains and their lower ends can be connected to ground of the picture display device. The latter step makes it possible to connect a different apparatus such as, for example, a magnetic recording and/or playback apparatus to the picture display device without earth connection problems occurring.
In FIG. 1 the reference numeral 14 denotes a secondary winding of transformer 9 which in accordance with the previously mentioned recognition of the invention can drive line output transistor 16 of the line deflection circuit 17. Line deflection circuit 17 which is shown in a simplified form in FIG. 1 includes inter alia line deflection coils 18 and an EHT transformer 19 a secondary winding 20 of which serves for generating the EHT required for the acceleration anode of the picture display tube. Line deflection circuit 17 is fed by the output voltage V o of the chopper which voltage is stabilized due to the pulse duration modulation with all previously mentioned advantages. Line deflection circuit 17 corresponds, for example, to similar arrangements which have been described in U.S. Pat. No. 3,504,224 issued Mar. 31, 1970 to J.J. Reichgelt et al., U.S. patent application Ser. No. 737,009 filed June 14, 1968 by W. H. Hetterscheid and U.S. application Ser. No. 26,497 filed April 8, 1970 by W. Hetterscheid et al. It will be evident that differently formed lined deflection circuits are alternatively possible.
It will now be shown that secondary winding 14 can indeed drive a line deflection circuit so that switching transistor 2 can function as a driver for the line deflection. FIGS. 2a and b show the variation as a function of time of the current i C which flows in the collector of transistor 16 and of the drive voltage v 14 across the terminals of secondary winding 14. During the flyback period (0, t 1 ) transistor 16 must be fully cut off because a high voltage peak is then produced at its collector; voltage v 14 must then be absolutely negative. During the scan period (t 1 , t 4 ) a sawtooth current i C flows through the collector electrode of transistor 16 which current is first negative and then changes its direction. As the circuit arrangement is not free from loss, the instant t 3 when current i C becomes zero lies, as is known, before the middle of the scan period. At the end t 4 of the scan period transistor 16 must be switched off again. However, since transistor 16 is saturated during the scan period and since this transistor must be suitable for high voltages and great powers so that its collector layer is thick, this transistor has a very great excess of charge carriers in both its base and collector layers. The removal of these charge carriers takes a period t s which is not negligible whereafter the transistor is indeed switched off. Thus the fraction δ T of the line period T at which v 14 is positive must end at the latest at the instant (t 4 - t s ) located after the commencement (t = 0) of the previous flyback.
The time δ T may be initiated at any instant t 2 which is located between the end t 1 of the flyback period and the instant t 3 when collector current i C reverses its direction. It is true that emitter current flows through transistor 16 at the instant t 2 , but collector current i C is not influenced thereby, at least not when the supply voltage (= V o ) for line deflection circuit 17 is high enough. All this has been described in the U.S. Pat. No. 3,504,224. The same applies to line deflection circuits wherein the collector base diode does not function as an efficiency diode as is the case in the described circuit 17, but wherein an efficiency diode is arranged between collector and emitter of the line output transistor. In such a case the negative part of the current i C of FIG. 2a represents the current flowing through the said efficiency diode.
After the instant t 3 voltage v 14 must be positive. In other words, the minimum duration of the period T when voltage v 14 must be positive is (t 4 - t s ) - t 3 whilst the maximum duration thereof is (t 4 - t s ) - t 1 . In a television system employing 625 lines per raster the line period t 4 is approximately 64 μus and the flyback period is approximately 12 μus. Without losses in the circuit arrangement instant t 3 would be located approximately 26 μus after the instant t 1 , and with losses a reasonable value is 22 μus which is 34 μus after the commencement of the period. If for safety's sake it is assumed that t s lasts approximately 10 μus, the extreme values of δ T are approximately 20 and 42 μus and consequently the values for δ are approximately 0.31 and 0.66 at a mean value which is equal to approximately 0.49. It was previously stated that a mean value of δ = 0.5 was suitable. Line deflection circuit 17 can therefore indeed be used in combination with the chopper in the manner described, and the relative variation of δ may be (0.66 - 0.31) : 0.49 = 71.5 percent. This is more than necessary to obviate the variations in the mains voltage or in the various loads and to establish the East-West modulation and ripple compensation to be described hereinafter. In fact, if it is assumed that the mains voltage varies between -15 and +10 percent of the nominal value of 220 V, while the 50 Hz ripple voltage which is superimposed on the input voltage V i has a peak-to-peak value of 40 V and V i is nominally 270 V, then the lowest occurring V i is:
0.85 × 270 V - 20 V = 210 V and the highest occurring V i is
1.1 × 270 V + 20 V = 320 V. For an output voltage V o of 135 V the ratio must thus vary between
δ = 135 : 210 = 0.64 and δ = 135 : 320 = 0.42.
A considerable problem presenting itself is that of the simultaneous or non-simultaneous drive of line output transistor 16 with switching transistor 2, it being understood that in case of simultaneous drive both transistors are simultaneously bottomed, that is during the period δ T. This depends on the winding sense of secondary winding 14 relative to that of primary winding 8. In FIG. 1 it has been assumed that the drive takes place simultaneously so that the voltage present across winding 14 has the shape shown in FIG. 2b. This voltage assumes the value n(V i - V o ) in the period δ T and the value -nVo in the period (1 - δ )T, wherein n is the ratio of the number of turns on windings 14 and 8 and wherein V o is maintained constant at nominal mains voltage V o = δ V inom . However, if as a result of an increase or a decrease of the mains voltage V i increases or decreases proportionally therewith, i.e., V i = V i nom + Δ V, the positive portion of V 14 becomes equal to n(V i nom - V o +Δ V) = n [(1 -δ)V i nom +ΔV] = n(0.5 V inom +ΔV) if δ = 0.5 for V i = V i nom. Relatively, this is a variation which is twice as great. For example, if V i nom = 270 V and V o = 135 V, a variation in the mains voltage of from -15 to +10 percent causes a variation of V i of from -40.5 V to +27 V which ranges from -30 to +20 percent of 135 V which is present across winding 8 during the period δ T. The result is that transistor 16 can always be bottomed over a large range of variation. If the signal of FIG. 2b would be applied through a resistor to the base of transistor 16, the base current thereof would have to undergo the same variation while the transistor would already be saturated in case of too low a voltage. In this case it is assumed that transformer 9 is ideal (without loss) and that coil 21 has a small inductance as is explained in the U.S. patent application Ser. No. 737,009 above mentioned. It is therefore found to be desirable to limit the base current of transistor 16.
This may be effected by providing a coil 22 having a large value inductance, approximately 100 μH, between winding 14 and the small coil 21. The variation of said base current i b is shown in FIG. 2c but not to the same scale as the collector current of FIG. 2a. During the conducting interval δ T current i b varies as a linear function of time having a final value of wherein L represents the inductance of coil 22. This not only provides the advantage that this final value is not immediately reached, but it can be shown that variation of this final value as a function of the mains voltage has been reduced, for there applies at nominal mains voltage that: If the mains voltage V i = V i nom +Δ V, then ##SPC1## because V i nom = 2 V o . Thus this variation is equal to that of the mains voltage and is not twice as great.
During switching off, t 2 , of transistor 16 coil 22 must exert no influence and coil 21 must exert influence which is achieved by arranging a diode 23 parallel to coil 22. Furthermore the control circuit of transistor 16 in this example comprises the two diodes 24 and 25 as described in U.S. application Ser. No. 26,497 above referred to, wherein one of these diodes, diode 25 in FIG. 1, must be shunted by a resistor.
The control circuit of transistor 16 may alternatively be formed as is shown in FIG. 4. In fact, it is known that coil 21 may be replaced by the parallel arrangement of a diode 21' and a resistor 21" by which the inverse current can be limited. To separate the path of the inverse current from that of the forward current the parallel arrangement of a the diode 29' and a resistor 29" must then be present. This leads to the circuit arrangement shown in the upper part of FIG. 4. This circuit arrangement may now be simplified if it is noted that diodes 25 and 21' on the one hand and diodes 23 and 29' on the other hand are series-arranged. The result is shown in the lower part of FIG. 4 which, as compared with the circuit arrangement of FIG. 1, employs one coil less and an additional resistor.
FIG. 3 shows possible modifications of the chopper. FIG. 3a shown in a simplified form the circuit arrangement according to FIG. 1 wherein the pulsatory voltage present across the connections of windings 8 has a peak-to-peak amplitude of V i - V o = 0.5 V i for δ = 0.5, As has been stated, the provision of coil 22 gives a relative variation for the base current of transistor 16 which is equal to that of the mains voltage. In the cases according to FIG. 3b, 3c and 3d the peak-to-peak amplitude of the voltage across winding 8 is equal to V i so that the provision of coil 22 results in a relative variation which is equal to half that of the mains voltage which is still more favorable than in the first case.
Transistors of the npn type are used in FIG. 3. If transistors of the pnp type are used, the relevant efficiency diodes must of course be reversed.
In this connection it is to be noted that it is possible to obtain an output voltage V o with the aid of the modifications according to FIGS. 3b, c and d, which voltage is higher than input voltage V i . These modifications may be used in countries such as, for example, the United of America or France where the nominal mains voltage is 117 or 110 V without having to modify the rest of the circuit arrangement.
The above-mentioned remark regarding the sum of the diode currents only applies, however, for the modifications shown in FIGS. 3a and d.
If line output transistor 16 is not simultaneously driven with switching transistor 2, efficiency diodes 7 conducts simultaneously with transistor 16 i.e., during the period which is denoted by δ T in FIGS. 1 and 2b. During that period the output voltage V o of the chopper is stabilized so that the base current of transistor 16 is stabilized without further difficulty. However, a considerable drawback occurs. In FIG. 1 the reference numeral 26 denotes a safety circuit the purpose of which is to safeguard switching transistor 2 when the current supplied to load 11 and/or line deflection circuit 17 becomes to high, which happens because the chopper stops. After a given period output voltage V o is built up again, but gradually which means that the ratio δ is initially small in the order of 0.1. All this is described in U.S. patent No. 3,629,686. The same phenomenon occurs when the display device is switched on. Since δ = 0.1 corresponds to approximately 6 μs when T = 64 μs, efficiency diode 7 conducts in that case for 64 - 6 = 58 μus so that transistor 16 is already switched on at the end of the scan or at a slightly greater ratio δ during the flyback. This would cause an inadmissibly high dissipation. For this reason the simultaneous drive is therefore to be preferred.
The line deflection circuit itself is also safeguarded: in fact, if something goes wrong in the supply, the driver voltage of the line deflection circuit drops out because the switching voltage across the terminals of primary winding 8 is no longer present so that the deflection stops. This particularly happens when switching transistor 2 starts to constitute a short-circuit between emitter and collector with the result that the supply voltage V o for the line deflection circuit in the case of FIG. 1 becomes higher, namely equal to V i . However, the line output transformer is now cut off and is therefore also safe as well as the picture display tube and other parts of the display device which are fed by terminal 15 or the like. However, this only applies to the circuit arrangement according to FIG. 1 or 3a.
Pulse oscillator 6 applies pulses of line frequency to modulator 5. It may be advantageous to have two line frequency generators as already described, to wit pulse oscillator 6 and line oscillator 6' which is present in the picture display device and which is directly synchronized in known manner by line synchronizing pulses 7'. In fact, in this case line oscillator 6' applies a signal of great amplitude and free from interference to pulse oscillator 6. However, it is alternatively possible to combine pulse oscillator 6 and line oscillator 6' in one single oscillator 6" (see FIG. 1) which results in an economy of components. It will be evident that line oscillator 6' and oscillator 6" may alternatively be synchronized indirectly, for example, by means of a phase discriminator. It is to be noted neither pulse oscillator 6, line oscillator 6' and oscillator 6" nor modulator 5 can be fed by the supply described since output voltage V o is still not present when the mains voltage is switched on. Said circuit arrangements must therefore be fed directly from the input terminals. If as described above these circuit arrangements are to be separated from the mains, a small separation transformer can be used whose primary winding is connected between the mains voltage terminals and whose secondary winding is connected to ground at one end and controls a rectifier at the other end.
Capacitor 27 is arranged parallel to efficiency diode 7 so as to reduce the dissipation in switching transistor 2. In fact, if transistor 2 is switched off by the pulsatory control voltage, its collector current decreases and its collector-emitter voltage increases simultaneously so that the dissipated power is not negligible before the collector current has becomes zero. If efficiency diode 7 is shunted by capacitor 27 the increase of the collector-emitter voltage is delayed i.e., this voltage does not assume high values until the collector current has already been reduced. It is true that in that case the dissipation in transistor 2 slightly increases when it is switched on by the pulsatory control voltage but on the other hand since the current flowing through diode 7 has decreased due to the presence of the secondary windings, its inverse current is also reduced when transistor 2 is switched on and hence its dissipation has become smaller. In addition it is advantageous to delay these switching-on and switching-off periods to a slight extent because the switching pulses then contain fewer Fourier components of high frequency which may cause interferences in the picture display device and which may give rise to visible interferences on the screen of the display tube. These interferences occupy a fixed position on the displayed image because the switching frequency is the line frequency which is less disturbing to the viewer. In a practical circuit wherein the line frequency is 15,625 Hz and wherein switching transistor 2 is an experimental type suitable for a maximum of 350 V collector-emitter voltage or 1 A collector current and wherein efficiency diode 7 is of the Philips type BA 148 the capacitance of capacitor 27 is approximately 680 pF whilst the load is 70 W on the primary and 20 W on the secondary side of transformer 9. The collector dissipation upon switching off is 0.3 W (2.5 times smaller than without capacitor 27) and 0.7 W upon switching on.
As is known the so-called pincushion distortion is produced in the picture display tubes having a substantially flat screen and large deflection angles which are currently used. This distortion is especially a problem in color television wherein a raster correction cannot be brought about by magnetic means. The correction of the so-called East-West pincushion distortion i.e., in the horizontal direction on the screen of the picture display tube can be established in an elegant manner with the aid of the circuit arrangement according to the invention. In fact, if the voltage generated by comparison circuit 12 and being applied to modulator 5 for duration-modulating pulsatory voltage 3 is modulated by a parabola voltage 28 of field frequency, pulsatory voltage 3 is also modulated thereby. If the power consumption of the line deflection circuit forms part of the load on the output voltage of the chopper, the signal applied to the line deflection coils is likewise modulated in the same manner. Conditions therefore are that the parabola voltage 28 of field frequency has a polarity such that the envelope of the sawtooth current of line frequency flowing through the line deflection coils has a maximum in the middle of the scan of the field period and that charge capacitor 10 has not too small an impedance for the field frequency. On the other hand the other supply voltages which are generated by the circuit arrangement according to the invention and which might be hampered by this component of field frequency must be smoothed satisfactorily.
A practical embodiment of the described example with the reference numerals given provides an output for the supply of approximately 85 percent at a total load of 90 W, the internal resistance for direct current loads being 1.5 ohms and for pulsatory currents being approximately 10 ohms. In case of a variation of ± 10 percent of the mains voltage, output voltage V o is stable within 0.4 V. Under the nominal circumstances the collector dissipation of switching transistor 2 is approximately 2.5 W.
Since the internal resistance of the supply is so small, it can be used advantageously, for example, at terminal 15 for supplying a class-B audio amplifier which forms part of the display device. Such an amplifier has the known advantages that its dissipation is directly proportional to the amplitude of the sound to be reproduced and that its output is higher than that of a class-A amplifier. On the other hand a class-A amplifier consumes a substantially constant power so that the internal resistance of the supply voltage source is of little importance. However, if this source is highly resistive, the supply voltage is modulated in the case of a class-B amplifier by the audio information when the sound intensity is great which may detrimentally influence other parts of the display device. This drawback is prevented by means of the supply according to the invention.
The 50 Hz ripple voltage which is superimposed on the rectified input voltage V i is compensated by comparison circuit 12 and modulator 5 since this ripple voltage may be considered to be a variation of input voltage V i . A further compensation is obtained by applying a portion of this ripple voltage with suitable polarity to comparison circuit 12. It is then sufficient to have a lower value for the smoothing capacitor which forms part of rectifier circuit 1 (see FIG. 3). The parabola voltage 28 of field frequency originating from the field time base is applied to the same circuit 12 so as to correct the East-West pincushion distortion.
PAL decoder tda3560A
The PHILIPS TDA3560A
is a decoder for the PAL colour television standard. It combines all functions required for the identification
and demodulation of PAL signals. Furthermore it contains a luminance amplifier, an RGB-matrix and amplifier. These
amplifiers supply output signals up to 5 V peak-to-peak (picture information) enabling direct drive of the discrete output
stages. The circuit also contains separate inputs for data insertion, analogue as well as digital, which can be used for
text display systems (e.g. (Teletext/broadcast antiope), channel number display, etc. Additional to the TDA3560, the
circuit includes the following features:
· The peak white limiter is only active during the time that the 9,3 V level at the output is exceeded. The start of the
limiting function is delayed by one line period. This avoids peak white limiting by test patterns which have abrupt
transitions from colour to white signals.
· The brightness control is obtained by inserting a variable pulse in the luminance channel. Therefore the ratio of
brightness variation and signal amplitude at the three outputs will be identical and independent of the difference in gain
of the three channels. Thus discolouring due to adjustment of contrast and brightness is avoided.
· Improved suppression of the internal RGB signals when the device is switched to external signals, and vice versa.
· Non-synchronized external RGB signals do not disturb the black level of the internal signals.
· Improved suppression of the residual 4,4 MHz signal in the RGB output stages.
· Cascoded stages in the demodulators and burst phase detector minimize the radiation of the colour demodulator
inputs.
· High current capability of the RGB outputs and the chrominance output.
APPLICATION INFORMATION
The function is described against the corresponding pin
number.
1. + 12 V power supply
The circuit gives good operation in a supply voltage range
between 8 and 13,2 V provided that the supply voltage for
the controls is equal to the supply voltage for the
TDA3561A. All signal and control levels have a linear
dependency on the supply voltage. The current taken by
the device at 12 V is typically 85 mA. It is linearly
dependent on the supply voltage.
2. Control voltage for identification
This pin requires a detection capacitor of about 330 nF for
correct operation. The voltages available under various
signal conditions are given in the specification.
3. Chrominance input
The chroma signal must be a.c.-coupled to the input.
Its amplitude must be between 55 mV and 1100 mV
peak-to-peak (25 mV to 500 mV peak-to-peak burst
signal). All figures for the chroma signals are based on a
colour bar signal with 75% saturation, that is the
burst-to-chroma ratio of the input signal is 1 : 2,25.
4. Reference voltage A.C.C. detector
This pin must be decoupled by a capacitor of about 330
nF. The voltage at this pin is 4,9 V.
5. Control voltage A.C.C.
The A.C.C. is obtained by synchronous detection of the
burst signal followed by a peak detector. A good noise
immunity is obtained in this way and an increase of the
colour for weak input signals is prevented. The
recommended capacitor value at this pin is 2,2 mF.
6. Saturation control
The saturation control range is in excess of 50 dB.
The control voltage range is 2 to 4 V. Saturation control is
a linear function of the control voltage.
When the colour killer is active, the saturation control
voltage is reduced to a low level if the resistance of the
external saturation control network is sufficiently high.
Then the chroma amplifier supplies no signal to the
demodulator. Colour switch-on can be delayed by proper
choice of the time constant for the saturation control
setting circuit.
When the saturation control pin is connected to the power
supply the colour killer circuit is overruled so that the colour
signal is visible on the screen. In this way it is possible to
adjust the oscillator frequency without using a frequency
counter (see also pins 25 and 26).
7. Contrast control
The contrast control range is 20 dB for a control voltage
change from + 2 to + 4 V. Contrast control is a linear
function of the control voltage. The output signal is
suppressed when the control voltage is 1 V or less. If one
or more output signals surpasses the level of 9 V the peak
white limiter circuit becomes active and reduces the output
signals via the contrast control by discharging C2 via an
internal current sink.
8. Sandcastle and field blanking input
The output signals are blanked if the amplitude of the input
pulse is between 2 and 6,5 V. The burst gate and clamping
circuits are activated if the input pulse exceeds a level of
7,5 V.
The higher part of the sandcastle pulse should start just
after the sync pulse to prevent clamping of video signal on
the sync pulse. The width should be about 4 ms for proper
A.C.C. operation.
9. Video-data switching
The insertion circuit is activated by means of this input by
an input pulse between 1 V and 2 V. In that condition, the
internal RGB signals are switched off and the inserted
signals are supplied to the output amplifiers. If only normal
operation is wanted this pin should be connected to the
negative supply. The switching times are very short
(< 20 ns) to avoid coloured edges of the inserted signals
on the screen.
10. Luminance signal input
The input signal should have a peak-to-peak amplitude of
0,45 V (peak white to sync) to obtain a black-white output
signal to 5 V at nominal contrast. It must be a.c.-coupled to
the input by a capacitor of about 22 nF. The signal is
clamped at the input to an internal reference voltage.
A 1 kW luminance delay line can be applied because the
luminance input impedance is made very high.
Consequently the charging and discharging currents of the
coupling capacitor are very small and do not influence the
signal level at the input noticeably. Additionally the
coupling capacitor value may be small.
PHILCO TX927 COLOR "ANTRANCITE" CHASSIS TX10 (CHASSIS THORN TX10) Video signal processing circuit for a color television receiver PHILIPS TDA3560: In a video signal processing circuit for a color television receiver, a brightness setting, which is operative for external color signals as well as for internal color signals and which does not produce a color shift, can be obtained by combining with the luminance signal (Y) a
level shift signal (H) the amplitude of which is adjustable by the
brightness setting and by employing in each color channel two clamping
circuits, the first one of which clamps a first reference level (RL1)
in the external color signal (ER, EG, EB) onto a combination of the
level shift signal and the internal color signal (R, G, B) and the
second clamping circuit clamps a second reference leve (RL2)
which occurs in the sum signal of the internal and the external color
signal when the level shift signal has zero value, onto the cutoff level
of the relevant electron gun of a picture display tube.
1. A video signal processing circuit for a color television receiver having inputs for a luminance signal, for color difference signals and for external color signals, comprising respective matrix circuits for combining the respective color difference signals with the luminance signal to form respective color signals, respective first clamping circuits for clamping the respective external color signals onto the respective color signals, respective combining circuits for combining the respective clamped external color signals with the respective color signals, respective second clamping circuits for clamping the outputs of the respective combining circuits onto a predetermined level, and a brightness setting circuit, characterized in that the first clamping circuits act on a first reference level in said respective external color signals occurring in a first group of periods and the second clamping circuits act on a second reference level occurring in a second group of periods which differ from the periods of the first group, while the brightness setting circuit is an amplitude setting circuit for a level shift signal, which is combined with the luminance signal prior to processing the color difference signals, with which the relative position of the second reference level with respect to the remaining portion of the luminance signal is adjustable.
2. A video signal processing circuit as claimed in claim 1, characterized in that the respective first and second clamping circuits are operative alternately and every other line flyback period.
PHILCO TX927 COLOR "ANTRANCITE" CHASSIS TX10 (CHASSIS THORN TX10) Digital phase locked loop tuning system / PLL FREQUENCY SYNTHESIZER:(ITT SAA1274 SAA1275 SAA1276)
A phase locked loop circuit for use in an automatic frequency synthesizing system. The system includes a programmer circuit which is responsive to a channel number input signal and generates a first digital control signal which is representative of the selected channel number and a second digital control signal which is representative of a predetermined group of channel numbers. A programmable divider is controlled by the programming circuit and generates a digital output signal which causes the phase locked loop circuit to generate a desired system output frequency corresponding to the selected channel number input signal. The phase locked loop circuit includes automatic fine tuning and manual fine tuning features.
1. A digital phase locked loop tuning system responsive to a local oscillator signal for producing a frequency synthesized digital output signal which is utilized to control the frequency of the local oscillator, the local oscillator having a plurality of frequencies associated therewith corresponding, respectively, to a plurality of selectable channels, each of the channels being allocated to one of at least two channel groups with each channel in a particular channel group being separated from an adjacent channel in the particular channel group by a predetermined frequency spacing of the local oscillator, comprising:
programming means responsive to an input signal representing a selected channel number of a particular channel group for generating a first digital control signal having a value corresponding to the selected channel number and for generating a second digital control signal representative of said particular channel group, said second digital control signal being a constant predetermined value for all of said channel numbers that are within said group; and
programmable divider means coupled to said programming means being responsive to said first, second digital control signals and the local oscillator signal, in a local oscillator mode, for generating the digital output signal which is representative of a desired frequency corresponding to said selected channel number, said programmable divider means including means for dividing the local oscillator signal by first and second factors, said first factor being related to the frequency separation between local oscillator signals by an integral number, the local oscillator signal being divided by said first factor during a first interval for a first number of periods of the output signal and being divided by said second factor for a second number of periods of the output signal, said first number of periods being related to the number of the channel selected, said second number being related to the channel group within which the selected channel lies.
2. Phase locked loop system according to claim 1, wherein said programming means including means coupled to said programming means for receiving an MFT signal and being responsive to said MFT signal for altering said first and second digital control signals, and said programmable divider means being responsive to said altered digital control signals for generating an altered system output frequency. 3. Phase locked loop system according to claim 2, wherein said programming means includes first terminal means coupled to said programming means for receiving an AFT control signal, and first logic means responsive to the input signal and the AFT control signal for generating the first digital control signal. 4. Phase locked loop system according to claim 3, wherein said programming means includes second logic means coupled to said first logic means and responsive to the AFT control signal for generating the second digital control signal. 5. Phase locked loop system according to claim 4, wherein said second logic means includes group decoder means coupled to said first logic means. 6. Phase locked loop circuit means according to claim 5, wherein said second logic means includes memory means coupled to said group decoder means and to said first terminal means. 7. Phase locked loop system according to claim 6, wherein said second logic means includes second terminal means for receiving an MFT signal, and up/down counter latch means coupled to said memory means and to said second terminal means for altering said first and second digital control signals in response to said MFT signal. 8. Phase locked loop system according to claim 7, wherein said second logic means includes adder means coupled to said up/down counter latch means to said memory means. 9. Phase locked loop system according to claim 3, wherein said first logic means includes channel number generator means coupled to said first terminal means and responsive to said input signal. 10. Phase locked loop system according to claim 9, wherein said channel number generator means includes first and second data selector means coupled to said first terminal means, and adder means coupled to said second data selector means and to said up/down counter latch means. 11. Phase locked loop system according to claim 1, wherein said means for dividing the local oscillator signal includes programmable counter means for generating a modulus control output signal, and variable modulus prescaler divider means coupled to and responsive to said programmable counter means, said variable modulus prescaler divider means dividing the local oscillator signal by said first and second factors. 12. Phase locked loop system according to claim 11, wherein said programmable counter means includes third data selector means coupled to receive said first and second digital control signals and said modulus control signal. 13. Phase locked loop system according to claim 12, wherein said programmable counter means includes a programmable counter coupled to said third data selector means and to said variable modulus prescaler divider means. 14. Phase locked loop system according to claim 13, wherein said programmable counter means includes look ahead circuit means coupled to said programmable counter, and divide by two circuit means coupled to said look ahead circuit means for generating said modulus control output signal. 15. Phase locked loop tuning system according to claim 1 including digital automatic fine tuning (AFT) means wherein:
said programmable divider means includes switching means responsive to an AFT control signal to inhibit the local oscillator signal to said programmable divider means and to provide an input signal thereto of a different frequency than the local oscillator signal; and
said programming means including logic means responsive to said AFT control signal for altering said first and second digital control signals to predetermined values to cause the phase locked loop tuning system to be operable in an automatic fine tuning mode.
16. Phase locked loop tuning system of claim 15 wherein said programmable divider means includes:
programmable counter means for generating first and second modulus control signals; and
dual modulus prescaler means responsive to said first modulus control signal for dividing the local oscillator signal in said local oscillator mode and said input signal of a different frequency in said automatic fine tuning mode by said first factor which is equal to the integer six and being responsive to said second modulus control signal for dividing said local oscillator signal and said input signal of a different frequency by said second factor which is equal to the integer five respectively.
17. Phase locked loop tuning system of claim 16 wherein said signal of a different frequency is an intermediate frequency signal provided by the tuning system and supplied to said switching means.
18. In a phase locked loop tuning system for receiving a channel number input signal and a local oscillator signal having groups of selectable frequencies wherein the frequency spacing between each adjacent local oscillator frequency within a single group is uniform, the improvement comprising programmable divider means for generating a digital output signal representative of a desired tuning system output frequency including variable modulus prescaler divider means having a prescaler division ratio being equal to P = S/Y' for dividing the local oscillator frequency by said prescaler division ratio during a first interval for a first number of periods of the digital output signal and for dividing the local oscillator frequency by a second prescaler division ratio during a second interval for a second number of periods, said second ratio being related to said first ratio, where S is the frequency spacing between each adjacent local oscillator frequency within a single group (i), Yi =Di -Xi S, where Di is said desired tuning system output frequency within said selected group; Xi =Di /S rounded off to the nearest integer; Y' is chosen such that Yi /Y' is an integer and S/Y' is an integer and Y' is the smallest value of all values of Yi. 19. In a receiver including a tuning apparatus for providing a plurality of local oscillator signals each corresponding to a respective one of a plurality of selectable channels, each of the channels being allocated to one of at least two channel groups wherein each channel is separated from an adjacent channel in the respective channel group by a predetermined frequency spacing, a phase locked loop tuning system for producing a frequency synthesized output signal for controlling the frequency of the local oscillator, comprising:
variable modulus divider means for selectively dividing the frequency of the local oscillator signal by first and second factors in response to a modulus control signal to provide an output signal, said first factor being related to the frequency separation between local oscillator signals by an integral number; and
programmable means for generating said modulus control signal to cause said variable modulus divider means to divide by said first factor during a first interval for a first number of periods of said output signal and to divide by said second factor during a second interval for a second number of periods of said output signal, said first number of periods being related to the number of the channel selected, said second number of periods being related to the channel group corresponding to the selected channel.
20. The phase locked loop tuning system of claim 19 wherein said programmable means includes:
programming means responsive to a selected channel input signal for producing first and second digital output signals, said first digital output signal being related to the selected channel number plus one of two constant values which are determined in accordance within which channel group the selected channel input signal lies, said second digital signal being a constant value for all selected channels within a channel group; and
programmable divider means responsive to said first and second digital output signals from said programming means for providing said variable modulus control signal and the frequency synthesized output signal.
21. The phase locked loop tuning system of claim 20 wherein said programming means includes automatic fine tuning (AFT) means responsive to a AFT control signal being applied thereto when the receiver is placed in an AFT mode wherein:
said variable modulus divider means is caused to receive a input signal different from the local oscillator signal;
said programming means being responsive to the AFT control signal for altering said first and second digital signals such that the receiver is finely tuned to the frequency of the received signal applied to the receiver.
22. The phase locked loop tuning system of claim 21 wherein said programming means includes means for receiving a manual fine tuning (MFT) signal for altering said first and second digital output signals, and said programmable divider means being responsive to said altered digital control signals for generating an altered output signal. 23. The phase locked loop tuning system of claim 19 wherein the one of said first and second factors is an even number and the other is an odd number. 24. The phase locked loop tuning system of claim 23 wherein said first factor is the integer six and said second factor is the integer five.
This invention relates to digital tuning systems, and more particularly, to a simplified digital phase locked loop (PLL) tuning system incorporating unique digital automatic fine tuning and manual fine tuning schemes.
Since the appearance of varactor tuners for television, many tuning address schemes have evolved for controlling them. PLL techniques have maintained a performance advantage but have suffered a cost disadvantage due to complexity, the high frequencies involved, the need for automatic fine tuning and in some localities, the need for a manual fine tuning arrangement. With the advances that have taken place in semiconductor technology in the last several years, the high operating frequencies no longer present a significant problem.
Prior art PLL systems for use in television tuners have not yet been able to incorporate an automatic fine tuning feature, nor have they been able to incorporate a manual fine tuning system which would enable the PLL tuning system to be intentionally offset in predetermined increments. Television sets normally have an automatic fine tuning (AFT) feature, but this is normally incorporated as a separate circuit which is not directly incorporated into the television tuner.
An additional disadvantage of prior art PLL systems which are designed for use in a television tuner environment is that they are highly complex and relatively expensive. In order to convert the channel number input into the proper digital control signals for the PLL, a relatively large ROM having a capacity on the order of 82 words by 12 bits was required. The best prior art PLL tuning systems require two high speed programmable counters which greatly increase the system complexity. This together with the large ROM which the system required, greatly decreased the cost effectiveness of the system so that commercial manufacturers were able to use these prior art PLL systems only in their most expensive commercial television receivers.
Therefore, it is a feature of this invention to provide a digital PLL tuning system which incorporates design techniques that vastly simplify the complexity of the PLL while at the same time allowing the system to meet the latest needs of a television tuning system or any other PLL tuning system which is addressed by a channel number.
It is another feature of this invention to provide a digital PLL tuning system that has the ability to automatically tune nonprecise station frequencies and the ability to be manually fine tuned.
It is yet another feature of the present invention to provide a digital PLL tuning system having only a single high speed programmable counter and requiring a ROM capacity of only 5 words by 9 bits.
It is still another feature of this invention to provide a digital PLL tuning system which performs the automatic fine tuning feature by utilizing the PLL tuning system as a digital discriminator.
It is yet another feature of this invention to provide a digital PLL tuning system incorporating a manual fine tuning (MFT) arrangement which is capable of intentionally offsetting the local oscillator frequency of a TV tuner in one megahertz steps or of offsetting TV IF frequency in steps of 125 kilohertz.
SUMMARY OF THE INVENTION
The preferred embodiment of the present invention includes a phase locked loop circuit means for an automatic frequency synthesizing system. The phase locked loop circuit means includes programming means which is responsive to an input signal representing a selected channel number for generating a first digital control signal representative of the selected channel number and for generating a second digital control signal representative of a predetermined group of channel numbers. A programmable divider means is coupled to the first and second digital control signals and generates a digital output signal representative of a desired system output frequency corresponding to the selected channel number.
The phase locked loop circuit means further includes an automatic fine tuning feature for fine tuning the phase locked loop output frequency to the exact frequency of the received signal. The system further includes a manual fine tuning provision which allows the phase locked loop operating frequency to be intentionally offset in predetermined increments.
I
n a horizontal deflection circuit, a horizontal oscillator, energized by a supply voltage, develops a horizontal frequency switching signal. A deflection outputs stage is responsive to the switching signal and generates scanning current in a horizontal deflection winding. After commencement of oscillator operation, the voltage developed across a secondary winding of a flyback transformer is rectified and filtered and applied to the horizontal oscillator as the oscillator energizing supply voltage. A start-up supply for developing the oscillator supply voltage during an initial interval includes a source of voltage that is available for use prior to the commencement of oscillator operation, a capacitor, a charging circuit for charging the capacitor from the available voltage source, and a controllable switch coupled to the capacitor and to the oscillator. After the charging circuit has charged the capacitor to a predetermined threshold voltage level, the controllable switch is made conductive to apply the capacitor voltage to the oscillator to commence oscillator operation. The switch is arranged with the capacitor as a relaxation oscillator to begin discharging the capacitor by the load current drawn by the horizontal oscillator. Should the capacitor discharge to a lower threshold level before the flyback-derived supply voltage is developed, the relaxation oscillator changes states to disconnect the horizontal oscillator from the capacitor to initiate a capacitor recharging cycle.1. An oscillator-derived power supply with start-up circuitry, comprising:
a supply terminal;
an oscillator being energized by the voltage developed at said supply terminal for producing an oscillator output signal;
a start-up voltage supply to energize said oscillator into commencing operation, said start-up voltage supply comprising:
a capacitor,
a source of DC input voltage available prior to commencement of oscillator operation,
means for charging said capacitor from said DC input voltage source, and
switching means interposed between said capacitor and said supply terminal for applying said capacitor voltage to said oscillator after said capacitor has charged to a first threshold level, to commence oscillator operation;
means responsive to said oscillator output signal for developing a steady-state voltage; and
means for applying said steady-state voltage to said supply terminal via said switching means to maintain oscillator energization during steady-state operation.
a horizontal oscillator energized by a supply voltage for developing a horizontal frequency switching signal after commencement of oscillator operation;
a horizontal deflection winding;
a deflection output stage responsive to said horizontal frequency switching signal for generating scanning current in said deflection winding;
a flyback transformer having a first winding coupled to said deflection output stage for developing a horizontal frequency alternating polarity output voltage across a plurality of secondary windings;
supply voltage producing means responsive to the horizontal frequency alternating polarity output voltage developed across one of said plurality of secondary windings for producing said supply voltage after commencement of horizontal oscillator operation; and
a start-up supply for developing said supply voltage during an initial interval to enable said horizontal oscillator to commence operation, said start-up supply comprising:
a source of voltage available prior to commencement of horizontal oscillator operation,
a capacitor,
means for charging said capacitor from said prior available voltage source, and
switching means coupled to said capacitor and to said horizontal oscillator for applying said capacitor voltage to said horizontal oscillator as said supply voltage to commence horizontal oscillator operation after said charging means has charged said capacitor to an upper threshold voltage level, said switching means arranged with said capacitor as a relaxation oscillator that begins discharging said capacitor by the load current drawn by said horizontal oscillator after said charging means has charged said capacitor to said upper threshold voltage level and begins recharging said capacitor from said charging means when said capacitor discharges to a lower threshold voltage level.
Description:
This invention relates to start-up supplies for horizontal deflection circuits.
In a television receiver, the supply voltages to power various television receiver circuits such as the vertical deflection circuit and the audio and video circuits are derived from rectified and filtered flyback pulses developed by the horizontal deflection circuit. After the horizontal oscillator in the deflection circuit has commenced operation, the supply voltage for the oscillator is also derived from rectified and filtered flyback pulse voltages.
When the television receiver is turned on, the flyback pulse voltages are absent. A start-up supply for the horizontal oscillator is therefore required in order to energize the oscillator and develop the flyback-derived power supply voltages for the television receiver. A voltage that is available to power the oscillator during the start-up interval after the television receiver is turned on is the DC input voltage obtained by rectifying and filtering the AC mains supply voltage.
Since the horizontal oscillator is designed to use a relatively low supply voltage, the DC input voltage during start-up may be applied to the oscillator through a dropping resistor. The value of the resistor is selected to be relatively large in order to minimize the dissipation in the resistor while at the same time providing the horizontal oscillator with at least the minimum amount of current required to initiate oscillator operation. After the flyback-derived supply voltage becomes available, the normal load current for the oscillator is provided from this supply excluding the load current still being provided by the dropping resistor. Thus, the dropping resistor dissipates a significant amount of power even during steady-state television receiver operation after the start-up interval has elapsed.
To eliminate power dissipation in the dropping resistor during steady-state operation, some start-up circuits include a transistor switch in series with the dropping resistor. When the steady-state flyback-derived supply voltage for the oscillator is developed, the switch becomes reverse biased, disconnecting the dropping resistor from the oscillator. A relatively expensive switch is required that is capable of withstanding the off-state voltage stress applied to it. This off-state voltage equals the difference between the DC input voltage and the oscillator supply voltage.
A feature of the invention is the design of an oscillator-derived power supply with start-up circuitry that dissipates relatively little power during steady-state operation after the oscillator has commenced operation. An oscillator energized by the voltage developed at a supply terminal produces an output signal that is used by a subsequent power supply stage to develop a steady-state voltage to energize the load circuit. The steady-state voltage is also applied to the oscillator to maintain it energized after commencement of oscillator operation. A start-up voltage supply to energize the oscillator into commencing operation comprises a capacitor, a source of energy that is available prior to the commencement of oscillator operation, a charging circuit for charging the capacitor from the energy source, and switching means interposed between the capacitor and the oscillator. The switching means applies the capacitor voltage to the oscillator after the capacitor has charged to a first threshold level, thereby commencing oscillator operation and the development of the steady-state voltage by the oscillator responsive power supply.
With such an arrangement, the charging current flowing to the capacitor may be selected to be of relatively low magnitude, much lower than even the minimum amount of load current required to energize the oscillator. Dissipation in the charging circuit is substantially reduced, even though the charging circuit may still be supplying current during steady-state operation after commencement of oscillator operation.
During the start-up interval, the oscillator draws more current from the capacitor than is being supplied by the charging circuit, resulting in the capacitor being discharged. Another feature of the invention is that should the capacitor discharge to a lower threshold level, indicating that the steady-state voltage supply is still unavailable for use, the switching means disconnects the capacitor from the oscillator, enabling the capacitor to recharge and reinitiate the start-up sequence.
FIG. 1 illustrates a horizontal deflection circuit with derived power supplies and with a start-up circuit for the deflection oscillator; and
FIG. 2 illustrates waveforms associated with the circuit of FIG. 1.
In FIG. 1, a source 20 of AC mains supply voltage is coupled to input terminals 23 and 24 of a full-wave bridge rectifier 27. Source 20 is coupled to input terminal 23 through an on/off switch 21 and a current limiting resistor 22. A filter capacitor 28 is coupled across output terminal 25 of bridge rectifier 27 and the current return or ground terminal 26. A filtered but unregulated DC input voltage Vin is developed at terminal 25 and applied to a regulator 29. Regulator 29 may be a conventional switching regulator, such as described in U.S. Pat. No. 4,147,964, D. W. Luz et al., entitled "COMPLEMENTARY LATCHING DISABLING CIRCUIT", using an SCR regulator switch operated at the horizontal deflection frequency of a television receiver to produce a regulated B+ voltage at a terminal 30. Feedback of the B+ voltage to the switching regulator is provided by a conductor line 74. A filter capacitor 31 is provided to filter out horizontal rate ripple voltage from terminal 30.
The B+ voltage developed at terminal 30 is applied through the primary winding 32a of a flyback transformer 32 to the collector of a horizontal output transistor 35 in a horizontal deflection output stage 34 of a horizontal deflection circuit 80. Horizontal deflection circuit 80 includes a horizontal oscillator 43, energized by a supply voltage Vcc developed at a supply terminal 45 and drawing a load current iL therefrom, a horizontal driver transistor 44 and horizontal output stage 34. Horizontal output stage 34 comprises horizontal output transistor 35, a damper diode 36, a retrace capacitor 38 and the series arrangement of a horizontal deflection winding 39 and an S-shaping or trace capacitor 40.
Horizontal oscillator 43, when energized by the voltage developed at supply terminal 45, produces a horizontal frequency, 1/TH, output switching signal 37 that is inverted by horizontal driver transistor 44 and applied to horizontal output transistor 35 through a driver transformer 42 to produce the switching action needed to generate horizontal scanning current in horizontal deflection winding 39. A waveshaping and filtering network 41 is coupled between the secondary winding 42b of driver transformer 42 and the base and emitter electrodes of output transistor 35.
Horizontal output transistor 35 is turned on early within the trace interval of each deflection cycle to conduct the horizontal scanning current after damper diode 36 is cut off and is turned off to initiate the horizontal retrace interval. During horizontal retrace, a retrace pulse voltage Vr is developed at the collector of horizontal output transistor 35 and applied to flyback transformer primary winding 32a to develop alternating polarity horizontal retrace pulse voltages across secondary windings 32b-32d.
The high voltage developed across winding 32b is applied to a high voltage circuit 33 to develop a DC ultor accelerating potential at a terminal U. The voltage across flyback transformer secondary winding 32c is rectified by a diode 46 during the horizontal trace interval and filtered by a capacitor 47 to develop a DC supply voltage V1 at a terminal 49. Supply voltage V1 energizes and provides current to such television receiver load circuits as the vertical deflection circuit and the audio circuit, designated in FIG. 1 generally as a resistor 48. The voltage across flyback transformer secondary winding 32d is rectified during the horizontal retrace interval by a diode 51 and applied to a supply terminal 53 through a current limiting resistor 52 to develop a DC supply voltage V2 across a filter capacitor 54. The DC supply voltage V2 energizes and provides current to such television receiver load circuits as the video driver circuit designated in FIG. 1 generally as a resistor 55.
The rectified and filtered voltage from flyback transformer winding 32d also supplies the collector voltage for horizontal driver transistor 44. The substantially DC voltage developed at the cathode of diode 51 at terminal 50 is applied through a resistor 57 and primary winding 42a of driver transformer 42 to the collector of driver transistor 44. A capacitor 56 provides horizontal rate filtering.
When the television receiver is turned on, after closure of on/off switch 21, the unregulated DC input voltage Vin is developed at terminal 25 and applied to switching regulator 29 to develop a voltage at B+ terminal 30. During the initial or start-up interval following closure of on/off switch 21, the flyback-derived supply voltages V1 and V2 are absent. To generate these voltages, switching action of horizontal output transistor 35 must be initiated by initiating or commencing the switching actions of horizontal oscillator 43 and driver transistor 44. Energization of these two elements, 43 and 44, must be obtained from voltage or energy sources that are available for use prior to commencement of operation of horizontal oscillator 43 and driver transistor 44.
The voltage used during start-up for providing collector supply voltage to driver transistor 44 is the voltage developed at B+ terminal 30 after closure of on/off switch 21. Terminal 30 is coupled to terminal 50 through a resistor 59 and a diode 60. Collector voltage for driver transistor 44 is obtained from B+ terminal 30 during start-up by way of resistor 59 and diode 60.
A start-up supply 90 is provided to initially develop supply voltage for horizontal oscillator 43 to energize the oscillator into commencing operation. Start-up supply 90 comprises a capacitor 63, a transistor switch 66 interposed between capacitor 63 and horizontal oscillator 43 at the supply terminal 45, a source of energy or voltage available prior to commencement of oscillator operation, namely the source of the DC input voltage Vin, and a charging resistor 61 that is used to charge capacitor 63 during the start-up interval from the DC input voltage terminal 25 by way of a resistor 62. Resistor 62 is a relatively low valued resistor used for a purpose hereinafter to be described.
Upon closureof on/off switch 21 and the development of a DC voltage Vin at terminal 25, a charging current ic begins to flow through resistor 61 and resistor 62 to terminal 73, the junction of capacitor 63 and the emitter of controllable transistor switch 66. Capacitor 63 is initially uncharged and the voltage Vc at terminal 73 is zero, maintaining transistor switch 66 in the off-state immediately after closure of on/off switch 21.
The base of transistor switch 66 is coupled to the collector of a transistor 67 through a resistor 72. A biasing network for transistors 66 and 67, comprising resistors 68-72, establishes at terminal 73 an upper threshold voltage level Va and a lower threshold voltage level Vb so as to enable transistors 66 and 67 to form with capacitor 63 a relaxation oscillator arrangement. When transistor 66 is cut off, resistor 70 is effectively in parallel with resistor 69, thereby establishing the upper threshold voltage level Va of FIG. 2; and when transistor 66 is in saturated conduction, resistor 70 is effectively in parallel with resistor 68, thereby establishing the lower threshold voltage level Vb.
As illustrated in FIG. 2 by the solid-line waveform of the voltage Vc, at a time t0, on/off switch 21 is closed and the charging current ic flowing from terminal 73 begins to charge capacitor 63. At time t1, capacitor 63 has charged to the upper threshold voltage level Va, turning on transistor 67 which turns on transistor switch 66 into saturated conduction. After transistor 66 becomes conductive, the voltage across capacitor 63 is applied to horizontal oscillator 43 at supply terminal 45 as a start-up supply voltage for the horizontal oscillator. Horizontal oscillator 43 commences operation and begins producing the horizontal rate switching signal 37 to initiate the switching action of horizontal driver transistor 44 and horizontal output transistor 35, thereby initiating the development of the horizontal retrace pulse voltage Vr and the horizontal retrace pulse voltages across flyback transformer secondary windings 32b-32d.
The load current iL being drawn by horizontal oscillator 43 durin
g the initial or start-up interval, after time t1 of FIG. 2, is of greater magnitude than the charging current ic flowing to terminal 73 from charging resistor 61. Thus, after time t1, horizontal oscillator 43 begins discharging capacitor 63 as illustrated in FIG. 2 by the decreasing voltage Vc after time t1. Even though the voltage Vc applied to horizontal oscillator 43 during the start-up interval after time t1 is decreasing, it is still sufficiently greater than the minimum voltage needed to maintain the oscillator operating. Thus, the horizontal rate switching signal is still being produced by horizontal oscillator 43 after time t1. By time t2 of FIG. 2, a sufficient period has elapsed so as to enable a substantial buildup of the flyback-derived supply voltage V1 at terminal 49. Supply voltage V1 is then applied to horizontal oscillator 43 by way of a diode 64 that has its cathode coupled to terminal 65, the junction of charging resistor 61 and resistor 62. Diode 64 blocks the flow of charging current to flyback supply terminal to prevent undue shunting of the current from oscillator 43 during start-up.
Near time t2, the flyback-derived supply voltage V1 has increased sufficiently so as to be able to generate a current i1 flowing out of supply terminal 49 that is greater than the load current iL being drawn by horizontal oscillator 43. Thus, after time t2, capacitor 63 ceases discharging and becomes charged shortly thereafter to a relatively constant voltage level Vcc0, as illustrated by the solid-line waveform of FIG. 2 after time t2.
The voltage Vcc0 maintains transistor switch 66 conducting and is applied via the transistor to horizontal oscillator 43 as the steady-state supply voltage. Thus, the steady-state supply voltage Vcc0 is obtained from the flyback-derived supply voltage V1. Because the flyback-derived supply voltage V1 also functions as a supply voltage for other television receiver loads, the voltage V1 is not necessarily of the ideal magnitude to energize horizontal oscillator 43. Typically, the voltage V1 is slightly greater in magnitude than is desirable for use by horizontal oscillator 43. Resistor 62 is therefore provided to generate a voltage drop to establish the correct lower voltage Vcc0 at supply terminal 45.
During steady-state operation, the load current iL for horizontal oscillator 43 comprises the sum of the current i1 obtained from flyback supply terminal 49 and the charging current ic obtained from charging resistor 61, if the biasing currents to transistors 66 and 67 are neglected. Thus, even during steady-state operation, the charging current ic flows through resistor 61.
To keep power dissipation in charging resistor 61 to a relatively small amount especially during steady-state operation, the magnitude of the charging current ic is kept at a relatively small value, illustratively at 5% or less of the steady-state load current of horizontal oscillator 43 and 10 times less than the minimum load current needed to maintain horizontal oscillator 43 operating at start-up. By providing a transistor 66 interposed between capacitor 63 and oscillator supply terminal 45, the current required to flow through the resistance that is coupled between the DC input voltage Vin and oscillator 43 may be kept relatively small to reduce steady-state dissipation. Sufficient start-up load current to horizontal oscillator 43 is available, nonetheless, due to the charge buildup on capacitor 63 and the subsequent discharge of the capacitor.
The values of the upper threshold voltage level Va and of the capacitance of capacitor 63 may be selected such that for almost every deflection circuit operating condition encountered, sufficient time is available after capacitor 63 begins to be discharged by the load current drawn by horizontal oscillator 43 to enable the flyback-derived supply voltage V1 to subsequently take over energization of the oscillator before the capacitor has discharged to a voltage less than the minimum required to maintain operation of the oscillator.
Another feature of the invention is to arrange transistor switch 66, transistor 67 and capacitor 63 as a relaxation oscillator. By providing a relaxation oscillator arrangement, start-up of horizontal deflection circuit 80 is ensured for practically all operating conditions encountered by horizontal deflection circuit 80. For example, a situation may be encountered during start-up where the DC input voltage Vin is extremely low and the loading on flyback transformer 32 is extremely high. In such an operating situation, a much longer interval after the initiation of start-up may be required to build up the flyback-derived supply voltage V1 to a satisfactory level. If capacitor 63 discharges to a level below the minimum necessary to maintain horizontal oscillator 43 in operation before the voltage V1 builds up to a satisfactory level, start-up of deflection circuit 80 is defeated.
To prevent such a situation from occurring, the relaxation oscillator arrangement of start-up supply 90 establishes a lower threshold voltage level Vb when transistor switch 66 is conductive. Should capacitor 63 discharge to the lower threshold voltage level Vb, as illustrated by FIG. 2 by the dashed-line waveform of the voltage Vc after time t2, indicating a failure of the flyback-derived supply voltage V1 to build up to a satisfactory level, transistor 67 is biased off, thereby turning off transistor switch 66. The value of the lower threshold voltage level Vb may be selected as greater than the minimum voltage needed to maintain oscillator 43 functioning.
With transistor switch 66 cut off at time t3, a start-up charging cycle for capacitor 63 is reinitiated. As illustrated in FIG. 2 by the dashed-line waveform, capacitor 63 recharges from time t3 to time t4, at which time the upper threshold voltage level Va is again reached at terminal 73 to turn on transistor switch 66 at time t4. The voltage across capacitor 63 is again applied to horizontal oscillator 43 to recommence oscillator operation and to continue the buildup of flyback-derived supply voltage V1 so that by time t5 the supply voltage V1 has increased sufficiently to take over supplying current to horizontal oscillator 43. Shortly after time t5, the steady-state supply voltage Vcc0 at supply terminal 45 is established.
The relaxation oscillator arrangement of start-up supply 90 can provide as many charge/discharge cycles for capacitor 63 as may be required in order to build up the flyback-derived supply voltage V1 to the levels needed to maintain steady-state deflection circuit operation.
In a television receiver, the supply voltages to power various television receiver circuits such as the vertical deflection circuit and the audio and video circuits are derived from rectified and filtered flyback pulses developed by the horizontal deflection circuit. After the horizontal oscillator in the deflection circuit has commenced operation, the supply voltage for the oscillator is also derived from rectified and filtered flyback pulse voltages.
When the television receiver is turned on, the flyback pulse voltages are absent. A start-up supply for the horizontal oscillator is therefore required in order to energize the oscillator and develop the flyback-derived power supply voltages for the television receiver. A voltage that is available to power the oscillator during the start-up interval after the television receiver is turned on is the DC input voltage obtained by rectifying and filtering the AC mains supply voltage.
To eliminate power dissipation in the dropping resistor during steady-state operation, some start-up circuits include a transistor switch in series with the dropping resistor. When the steady-state flyback-derived supply voltage for the oscillator is developed, the switch becomes reverse biased, disconnecting the dropping resistor from the oscillator. A relatively expensive switch is required that is capable of withstanding the off-state voltage stress applied to it. This off-state voltage equals the difference between the DC input voltage and the oscillator supply voltage.
With such an arrangement, the charging current flowing to the capacitor may be selected to be of relatively low magnitude, much lower than even the minimum amount of load current required to energize the oscillator. Dissipation in the charging circuit is substantially reduced, even though the charging circuit may still be supplying current during steady-state operation after commencement of oscillator operation.
During the start-up interval, the oscillator draws more current from the capacitor than is being supplied by the charging circuit, resulting in the capacitor being discharged. Another feature of the invention is that should the capacitor discharge to a lower threshold level, indicating that the steady-state voltage supply is still unavailable for use, the switching means disconnects the capacitor from the oscillator, enabling the capacitor to recharge and reinitiate the start-up sequence.
FIG. 1 illustrates a horizontal deflection circuit with derived power supplies and with a start-up circuit for the deflection oscillator; and
FIG. 2 illustrates waveforms associated with the circuit of FIG. 1.
In FIG. 1, a source 20 of AC mains supply voltage is coupled to input terminals 23 and 24 of a full-wave bridge rectifier 27. Source 20 is coupled to input terminal 23 through an on/off switch 21 and a current limiting resistor 22. A filter capacitor 28 is coupled across output terminal 25 of bridge rectifier 27 and the current return or ground terminal 26. A filtered but unregulated DC input voltage Vin is developed at terminal 25 and applied to a regulator 29. Regulator 29 may be a conventional switching regulator, such as described
in U.S. Pat. No. 4,147,964, D. W. Luz et al., entitled "COMPLEMENTARY LATCHING DISABLING CIRCUIT", using an SCR regulator switch operated at the horizontal deflection frequency of a television receiver to produce a regulated B+ voltage at a terminal 30. Feedback of the B+ voltage to the switching regulator is provided by a conductor line 74. A filter capacitor 31 is provided to filter out horizontal rate ripple voltage from terminal 30. The B+ voltage developed at terminal 30 is applied through the primary winding 32a of a flyback transformer 32 to the collector of a horizontal output transistor 35 in a horizontal deflection output stage 34 of a horizontal deflection circuit 80. Horizontal deflection circuit 80 includes a horizontal oscillator 43, energized by a supply voltage Vcc developed at a supply terminal 45 and drawing a load current iL therefrom, a horizontal driver transistor 44 and horizontal output stage 34. Horizontal output stage 34 comprises horizontal output transistor 35, a damper diode 36, a retrace capacitor 38 and the series arrangement of a horizontal deflection winding 39 and an S-shaping or trace capacitor 40.
Horizontal output transistor 35 is turned on early within the trace interval of each deflection cycle to conduct the horizontal scanning current after damper diode 36 is cut off and is turned off to initiate the horizontal retrace interval. During horizontal retrace, a retrace pulse voltage Vr is developed at the collector of horizontal output transistor 35 and applied to flyback transformer primary winding 32a to develop alternating polarity horizontal retrace pulse voltages across secondary windings 32b-32d.
The rectified and filtered voltage from flyback transformer winding 32d also supplies the collector voltage for horizontal driver transistor 44. The substantially DC voltage developed at the cathode of diode 51 at terminal 50 is applied through a resistor 57 and primary winding 42a of driver transformer 42 to the collector of driver transistor 44. A capacitor 56 provides horizontal rate filtering.
When the television receiver is turned on, after closure of on/off switch 21, the unregulated DC input voltage Vin is developed at terminal 25 and applied to switching regulator 29 to develop a voltage at B+ terminal 30. During the initial or start-up interval following closure of on/off switch 21, the flyback-derived supply voltages V1 and V2 are absent. To generate these voltages, switching action of horizontal output transistor 35 must be initiated by initiating or commencing the switching actions of horizontal oscillator 43 and driver transistor 44. Energization of these two elements, 43 and 44, must be obtained from voltage or energy sources that are available for use prior to commencement of operation of horizontal oscillator 43 and driver transistor 44.
The voltage used during start-up for providing collector supply voltage to driver transistor 44 is the voltage developed at B+ terminal 30 after closure of on/off switch 21. Terminal 30 is coupled to terminal 50 through a resistor 59 and a diode 60. Collector voltage for driver transistor 44 is obtained from B+ terminal 30 during start-up by way of resistor 59 and diode 60.
A start-up supply 90 is provided to initially develop supply voltage for horizontal oscillator 43 to energize the oscillator into commencing operation. Start-up supply 90 comprises a capacitor 63, a transistor switch 66 interposed between capacitor 63 and horizontal oscillator 43 at the supply terminal 45, a source of energy or voltage available prior to commencement of oscillator operation, namely the source of the DC input voltage Vin, and a charging resistor 61 that is used to charge capacitor 63 during the start-up interval from the DC input voltage terminal 25 by way of a resistor 62. Resistor 62 is a relatively low valued resistor used for a purpose hereinafter to be described.
Upon closure
of on/off switch 21 and the development of a DC voltage Vin at terminal 25, a charging current ic begins to flow through resistor 61 and resistor 62 to terminal 73, the junction of capacitor 63 and the emitter of controllable transistor switch 66. Capacitor 63 is initially uncharged and the voltage Vc at terminal 73 is zero, maintaining transistor switch 66 in the off-state immediately after closure of on/off switch 21. The base of transistor switch 66 is coupled to the collector of a transistor 67 through a resistor 72. A biasing network for transistors 66 and 67, comprising resistors 68-72, establishes at terminal 73 an upper threshold voltage level Va and a lower threshold voltage level Vb so as to enable transistors 66 and 67 to form with capacitor 63 a relaxation oscillator arrangement. When transistor 66 is cut off, resistor 70 is effectively in parallel with resistor 69, thereby establishing the upper threshold voltage level Va of FIG. 2; and when transistor 66 is in saturated conduction, resistor 70 is effectively in parallel with resistor 68, thereby establishing the lower threshold voltage level Vb.
As illustrated in FIG. 2 by the solid-line waveform of the voltage Vc, at a time t0, on/off switch 21 is closed and the charging current ic flowing from terminal 73 begins to charge capacitor 63. At time t1, capacitor 63 has charged to the upper threshold voltage level Va, turning on transistor 67 which turns on transistor switch 66 into saturated conduction. After transistor 66 becomes conductive, the voltage across capacitor 63 is applied to horizontal oscillator 43 at supply terminal 45 as a start-up supply voltage for the horizontal oscillator. Horizontal oscillator 43 commences operation and begins producing the horizontal rate switching signal 37 to initiate the switching action of horizontal driver transistor 44 and horizontal output transistor 35, thereby initiating the development of the horizontal retrace pulse voltage Vr and the horizontal retrace pulse voltages across flyback transformer secondary windings 32b-32d.
The load current iL being drawn by horizontal oscillator 43 durin
g the initial or start-up interval, after time t1 of FIG. 2, is of greater magnitude than the charging current ic flowing to terminal 73 from charging resistor 61. Thus, after time t1, horizontal oscillator 43 begins discharging capacitor 63 as illustrated in FIG. 2 by the decreasing voltage Vc after time t1. Even though the voltage Vc applied to horizontal oscillator 43 during the start-up interval after time t1 is decreasing, it is still sufficiently greater than the minimum voltage needed to maintain the oscillator operating. Thus, the horizontal rate switching signal is still being produced by horizontal oscillator 43 after time t1. By time t2 of FIG. 2, a sufficient period has elapsed so as to enable a substantial buildup of the flyback-derived supply voltage V1 at terminal 49. Supply voltage V1 is then applied to horizontal oscillator 43 by way of a diode 64 that has its cathode coupled to terminal 65, the junction of charging resistor 61 and resistor 62. Diode 64 blocks the flow of charging current to flyback supply terminal to prevent undue shunting of the current from oscillator 43 during start-up. Near time t2, the flyback-derived supply voltage V1 has increased sufficiently so as to be able to generate a current i1 flowing out of supply terminal 49 that is greater than the load current iL being drawn by horizontal oscillator 43. Thus, after time t2, capacitor 63 ceases discharging and becomes charged shortly thereafter to a relatively constant voltage level Vcc0, as illustrated by the solid-line waveform of FIG. 2 after time t2.
During steady-state operation, the load current iL for horizontal oscillator 43 comprises the sum of the current i1 obtained from flyback supply terminal 49 and the charging current ic obtained from charging resistor 61, if the biasing currents to transistors 66 and 67 are neglected. Thus, even during steady-state operation, the charging current ic flows through resistor 61.
The values of the upper threshold voltage level Va and of the capacitance of capacitor 63 may be selected such that for almost every deflection circuit operating condition encountered, sufficient time is available after capacitor 63 begins to be discharged by the load current drawn by horizontal oscillator 43 to enable the flyback-derived supply voltage V1 to subsequently take over energization of the oscillator before the capacitor has discharged to a voltage less than the minimum required to maintain operation of the oscillator.
To prevent such a situation from occurring, the relaxation oscillator arrangement of start-up supply 90 establishes a lower threshold voltage level Vb when transistor switch 66 is conductive. Should capacitor 63 discharge to the lower threshold voltage level Vb, as illustrated by FIG. 2 by the dashed-line waveform of the voltage Vc after time t2, indicating a failure of the flyback-derived supply voltage V1 to build up to a satisfactory level, transistor 67 is biased off, thereby turning off transistor switch 66. The value of the lower threshold voltage level Vb may be selected as greater than the minimum voltage needed to maintain oscillator 43 functioning.
The relaxation oscillator arrangement of start-up supply 90 can provide as many charge/discharge cycles for capacitor 63 as may be required in order to build up the flyback-derived supply voltage V1 to the levels needed to maintain steady-state deflection circuit operation.
PHILCO TX927 COLOR "ANTRANCITE" CHASSIS TX10 (CHASSIS THORN TX10) CIRCUIT ARRANGEMENT IN A PICTURE DISPLAY DEVICE UTILIZING A STABILIZED SUPPLY VOLTAGE CIRCUIT:TDA2581 CONTROL CIRCUIT FOR SMPS/PHILIPS POWER PACK:
The TDA2581 is a monolithic integrated circuit for controlling switched-mode power supplies (SMPS) which are provided with the drive for the horizontal deflection stage.
The circuit features the following:
— Voltage controlled horizontal oscillator.
— Phase detector.
— Duty factor control for the positive-going transient of the output signal.
— Duty factor increases from zero to its normal operation value.
— Adjustable maximum duty factor.
- Over-voltage and over-current protection with automatic re-start after switch-off.
— Counting circuit for permanent switch-off when n~times over~current or over-voltage is sensed
-Protection for open-reference voltage.
- Protection for too low supply voltage.
Protection against loop faults.
Positive tracking of duty factor and feedback voltage when the feedback voltage is smaller than the
reference voltage minus 1,5 V.
PHILCO TX927 COLOR "ANTRANCITE" CHASSIS TX10 (CHASSIS THORN TX10) Line synch Switched Mode Power Supply with Line deflection output Transistor Drive Circuit:
1. An electrical circuit arrangement for a picture display device operating at a given line scanning frequency, comprising a source of unidirectional voltage, an inductor, first switching transistor means for periodically energizing said inductor at said scanning frequency with current from said source, an electrical load circuit coupled to said inductor and having applied thereto a voltage as determined by the ratio of the ON and OFF periods of said transistor, means for maintaining the voltage across said load circuit at a given value comprising means for comparing the voltage of said load circuit with a reference voltage, means responsive to departures of the value of the load circuit voltage from the value of said reference voltage for varying the conduction ratio of the ON and OFF periods of said transistor thereby to stabilize said load circuit voltage at the given value, a line deflection coil system for said picture display device, means for energizing said line deflection coil system from said load voltage circuit means, means for periodically interrupting the energization of said line deflection coil comprising second switching means and means coupled to said inductor for deriving therefrom a switching current in synchronism with the energization periods of said transistor and applying said switching current to said switching means thereby to actuate the same, and means coupled to said switching means and to said load voltage circuit for producing a voltage for energizing said 2. A circuit as claimed in claim 1 wherein the duty cycle of said switching 3. A circuit as claimed in claim 1 further comprising an efficiency first 4. A circuit as claimed in claim 3 further comprising at least a second diode coupled to said deriving means and to ground, and being poled to 5. A circuit as claimed in claim 1 wherein said second switching means comprises a second transistor coupled to said deriving means to conduct simultaneously with said first transistor, and further comprising a coil coupled between said driving means and said second transistor and a third diode shunt coupled to said coil and being poled to conduct when said 6. A circuit as claimed in claim 1 further comprising a horizontal oscillator coupled to said first transistor, said oscillator being the 7. A circuit as claimed in claim 1 further comprising means coupled to said inductor for deriving filament voltage for said display device.
Description:
Such a circuit arrangement is known from German "Auslegeschrift" 1.293.304. wherein a circuit arrangement is described which has for its object to convert an input direct voltage which is generated between two terminals into a different direct voltage. The circuit employs a switch connected to the first terminal of the input voltage and periodically opens and closes so that the input voltage is converted into a pulsatory voltage. This pulsatory voltage is then applied to a coil. A diode is arranged between the junction of the switch and the coil and the second terminal of the input voltage whilst a load and a charge capacitor in parallel thereto are arranged between the other end of the coil and the second terminal of the input voltage. The assembly operates in accordance with the known efficiency principle i.e., the current supplied to the load flows alternately through the switch and through the diode. The function of the switch is performed by a switching transistor which is driven by a periodical pulsatory voltage which saturates this transistor for a given part of the period. Such a configuration is known under different names in the literature; it will be referred to herein as a "chopper." A known advantage thereof, is that the switching transistor must be able to stand a high voltage or provide a great current but it need not dissipate a great power. The output voltage of the chopper is compared with a constant reference voltage. If the output voltage attempts to vary because the input voltage and/or the load varies, a voltage causing a duration modulation of the pulses is produced at the output of the comparison arrangement. As a result the quantity of the energy stored in the coil varies and the output voltage is maintained constant. In the German "Auslegeschrift" referred to it is therefore an object to provide a stabilized supply
voltage device.
As will be further explained the use of the switching transistor as a driver for the line output transistor in an embodiment to be especially described hereinafter has the further advantage that the line output transistor automatically becomes non-conductive when this switching transistor is short circuited so that the deflection and the EHT for the display tube drop out and thus avoid damage thereof.
Due to the step according to the invention the switching transistor in the stabilized supply functions as a driver for the line deflection circuit. The circuit arrangement according to the invention may in addition be equipped with a very efficient safety circuit so that the reliability is considerably enhanced, which is described in the U.S. Pat. No. 3,629,686. The invention is
In order that the invention may be readily carried into effect, a few embodiments thereof will now be described in detail by way of example with reference to the accompanying diagrammatic drawings in which:
FIG. 1 shows a principle circuit diagram wherein the chopper and the line deflection circuit are further shown but other circuits are not further shown.
FIGS. 2a, 2b and 2c show the variation as a function of time of two currents and of a voltage occurring in the circuit arrangement according to FIG. 1.
FIGS. 3a 3b, 3c and 3d show other embodiments of the chopper.
FIGS. 4a and 4b show modifications of part of the circuit arrangement of FIG. 1.
In FIG. 1 the reference numeral 1 denotes a rectifier circuit which converts the mains voltage supplied thereto into a non-stabilized direct voltage. The collector of a switching transistor 2 is connected to one of the two terminals between which this direct voltage is obtained, said transistor being of the npn-type in this embodiment and the base of which receives a pulsatory voltage which originates through a control stage 4 from a modulator 5 and causes transistor 2 to be saturated and cut off alternately. The voltage waveform 3 is produced at the emitter of transistor 2. In order to maintain the output voltage of the circuit arrangement constant, the duration of the pulses provided is varied in modulator 5. A pulse oscillator 6 supplies the pulsatory voltage to modulator 5 and is synchronized by a signal of line frequency which originates from the line oscillator 6' present in the picture display device. This line oscillator 6' is in turn directly synchronized in known manner by pulses 7' of line frequency which are present in the device and originate for example from a received television signal if the picture display device is a television receiver. Pulse oscillator 6 thus generates a pulsatory voltage the repetition frequency of which is the line frequency.
The emitter of switching transistor 2 is connected at one end to the cathode of an efficiency diode 7 whose other end is connected to the second input voltage terminal and at the other end to primary winding 8 of a transformer 9. Pulsatory voltage 3 which is produced at the cathode of efficiency diode 7 is clamped against the potential of said second terminal during the intervals when this diode conducts. During the other intervals the pulsatory voltage 3 assumes the value V i . A charge capacitor 10 and a load 11 are arranged between the other end of winding 8 and the second input voltage terminal. The elements 2,7,8,10 and 11 constitute a so-called chopper producing a direct voltage across charge capacitor 10, provided that capacitor 10 has a sufficiently great value for the line frequency and the current applied to load 11 flowing alternately through switching transistor 2 or through efficiency diode 7. The output voltage V o which is the direct voltage produced across charge capacitor 10 is applied to a comparison circuit 12 which compares the voltage V o with a reference voltage. Comparison circuit 12 generates a direct voltage which is applied to modulator 5 so that the duration of the effective period δ T of switching transistor 2 relative to the period T of pulses 3 varies as a function of the variations of output voltage V 0 . In fact, it is readily evident that output voltage V o is proportional to the ratio δ :
V o = V i . δ
However, variations in the line amplitude and the EHT may occur as a result of an insufficiently small internal impedance of the EHT generator. Compensation means are known for this purpose. A possibility within the scope of the present invention is to use comparison circuit 12 for this purpose. In fact, if the beam current passes through an element having a substantially quadratic characteristic, for example, a voltage-dependent resistor, then a variation for voltage V o may be obtained through comparison circuit 12 which variation is proportional to the root of the variation in the EHT which is a known condition for the line amplitude to remain constant.In addition this facilitates smoothing of voltage V o since the repetition frequency of pulsatory voltage 3 is many times higher than that of the mains and a comparatively small value may be sufficient for charge capacitor 10. If charge capacitor 10 has a sufficiently high value for the line frequency, voltage V o is indeed a direct voltage so that a voltage having the same form as pulsatory voltage 3 is produced across the terminals of primary winding 8. Thus voltages which have the same shape as pulsatory voltage 3 but have a greater or smaller amplitude are produced across secondary windings 13, 14 of transformer 9 (FIG. 1 shows only 2 secondary windings but there may be more). The invention is based on the recognition that one end of each secondary winding is connected to earth while the other end thereof drives a diode, the winding sense of each winding and the direction of conductance of each diode being chosen to be such that these diodes conduct during the same period as does efficiency diode 7. After smoothing, stabilized supply voltages, for example, at terminal 15 are generated in this manner at the amplitudes and polarities required for the circuit arrangements present in the picture display device. In FIG. 1 the voltage generated at terminal 15 is, for example, positive relative to earth. It is to be noted that the load currents of the supply voltages obtained in this manner cause a reduction of the switching power which is economized by efficiency diode 7. The sum of all diode currents including that of diode 7 is in fact equal to the current which would flow through diode 7 if no secondary winding were wound on transformer 9 and if no simultaneous diode were used. This reduction may be considered an additional advantage of the circuit arrangement according to the invention, for a diode suitable for smaller powers may then be used. However, it will be evident that the overall secondary load must not exceed the primary load since otherwise there is the risk of efficiency diode 7 being blocked so that stabilization of the secondary supply voltages would be out of the question.
It is to be noted that a parabola voltage of line frequency as shown at 28 is produced across the charge capacitor 10 if this capacitor is given a smaller capacitance so that consequently the so-called S-correction is established.
In FIG. 1 charge capacitors are arranged between terminals 15 etc. and earth so as to ensure that the voltages on these points are stabilized direct voltages. If in addition the mean value of the voltage on one of these terminals has been made equal to the effective value of the alternating voltage which is required for heating the filament of the picture display tube present in the picture display device, this voltage is suitable for this heating. This is a further advantage of the invention since the cheap generation of a stabilized filament voltage for the picture display tube has always been a difficult problem in transistorized arrangements.
It will now be shown that secondary winding 14 can indeed drive a line deflection circuit so that switching transistor 2 can function as a driver for the line deflection. FIGS. 2a and b show the variation as a function of time of the current i C which flows in the collector of transistor 16 and of the drive voltage v 14 across the terminals of secondary winding 14. During the flyback period (0, t 1 ) transistor 16 must be fully cut off because a high voltage peak is then produced at its collector; voltage v 14 must then be absolutely negative. During the scan period (t 1 , t 4 ) a sawtooth current i C flows through the collector electrode of transistor 16 which current is first negative and then changes its direction. As the circuit arrangement is not free from loss, the instant t 3 when current i C becomes zero lies, as is known, before the middle of the scan period. At the end t 4 of the scan period transistor 16 must be switched off again. However, since transistor 16 is saturated during the scan period and since this transistor must be suitable for high voltages and great powers so that its collector layer is thick, this transistor has a very great excess of charge carriers in both its base and collector layers. The removal of these charge carriers takes a period t s which is not negligible whereafter the transistor is indeed switched off. Thus the fraction δ T of the line period T at which v 14 is positive must end at the latest at the instant (t 4 - t s ) located after the commencement (t = 0) of the previous flyback.
The time δ T may be initiated at any instant t 2 which is located between the end t 1 of the flyback period and the instant t 3 when collector current i C reverses its direction. It is true that emitter current flows through transistor 16 at the instant t 2 , but collector current i C is not influenced thereby, at least not when the supply voltage (= V o ) for line deflection circuit 17 is high enough. All this has been described in the U.S. Pat. No. 3,504,224. The same applies to line deflection circuits wherein the collector base diode does not function as an efficiency diode as is the case in the described circuit 17, but wherein an efficiency diode is arranged between collector and emitter of the line output transistor. In such a case the negative part of the current i C of FIG. 2a represents the current flowing through the said efficiency diode.
After the instant t 3 voltage v 14 must be positive. In other words, the minimum duration of the period T when voltage v 14 must be positive is (t 4 - t s ) - t 3 whilst the maximum duration thereof is (t 4 - t s ) - t 1 . In a television system employing 625 lines per raster the line period t 4 is approximately 64 μus and the flyback period is approximately 12 μus. Without losses in the circuit arrangement instant t 3 would be located approximately 26 μus after the instant t 1 , and with losses a reasonable value is 22 μus which is 34 μus after the commencement of the period. If for safety's sake it is assumed that t s lasts approximately 10 μus, the extreme values of δ T are approximately 20 and 42 μus and consequently the values for δ are approximately 0.31 and 0.66 at a mean value which is equal to approximately 0.49. It was previously stated that a mean value of δ = 0.5 was suitable. Line deflection circuit 17 can therefore indeed be used in combination with the chopper in the manner described, and the relative variation of δ may be (0.66 - 0.31) : 0.49 = 71.5 percent. This is more than necessary to obviate the variations in the mains voltage or in the various loads and to establish the East-West modulation and ripple compensation to be described hereinafter. In fact, if it is assumed that the mains voltage varies between -15 and +10 percent of the nominal value of 220 V, while the 50 Hz ripple voltage which is superimposed on the input voltage V i has a peak-to-peak value of 40 V and V i is nominally 270 V, then the lowest occurring V i is:
0.85 × 270 V - 20 V = 210 V and the highest occurring V i is
1.1 × 270 V + 20 V = 320 V. For an output voltage V o of 135 V the ratio must thus vary between
δ = 135 : 210 = 0.64 and δ = 135 : 320 = 0.42.
A considerable problem presenting itself is that of the simultaneous or non-simultaneous drive of line output transistor 16 with switching transistor 2, it being understood that in case of simultaneous drive both transistors are simultaneously bottomed, that is during the period δ T. This depends on the winding sense of secondary winding 14 relative to that of primary winding 8. In FIG. 1 it has been assumed that the drive takes place simultaneously so that the voltage present across winding 14 has the shape shown in FIG. 2b. This voltage assumes the value n(V i - V o ) in the period δ T and the value -nVo in the period (1 - δ )T, wherein n is the ratio of the number of turns on windings 14 and 8 and wherein V o is maintained constant at nominal mains voltage V o = δ V inom . However, if as a result of an increase or a decrease of the mains voltage V i increases or decreases proportionally therewith, i.e., V i = V i nom + Δ V, the positive portion of V 14 becomes equal to n(V i nom - V o +Δ V) = n [(1 -δ)V i nom +ΔV] = n(0.5 V inom +ΔV) if δ = 0.5 for V i = V i nom. Relatively, this is a variation which is twice as great. For example, if V i nom = 270 V and V o = 135 V, a variation in the mains voltage of from -15 to +10 percent causes a variation of V i of from -40.5 V to +27 V which ranges from -30 to +20 percent of 135 V which is present across winding 8 during the period δ T. The result is that transistor 16 can always be bottomed over a large range of variation. If the signal of FIG. 2b would be applied through a resistor to the base of transistor 16, the base current thereof would have to undergo the same variation while the transistor would already be saturated in case of too low a voltage. In this case it is assumed that transformer 9 is ideal (without loss) and that coil 21 has a small inductance as is explained in the U.S. patent application Ser. No. 737,009 above mentioned. It is therefore found to be desirable to limit the base current of transistor 16.
This may be effected by providing a coil 22 having a large value inductance, approximately 100 μH, between winding 14 and the small coil 21. The variation of said base current i b is shown in FIG. 2c but not to the same scale as the collector current of FIG. 2a. During the conducting interval δ T current i b varies as a linear function of time having a final value of wherein L represents the inductance of coil 22. This not only provides the advantage that this final value is not immediately reached, but it can be shown that variation of this final value as a function of the mains voltage has been reduced, for there applies at nominal mains voltage that: If the mains voltage V i = V i nom +Δ V, then ##SPC1## because V i nom = 2 V o . Thus this variation is equal to that of the mains voltage and is not twice as great.
During switching off, t 2 , of transistor 16 coil 22 must exert no influence and coil 21 must exert influence which is achieved by arranging a diode 23 parallel to coil 22. Furthermore the control circuit of transistor 16 in this example comprises the two diodes 24 and 25 as described in U.S. application Ser. No. 26,497 above referred to, wherein one of these diodes, diode 25 in FIG. 1, must be shunted by a resistor.
The control circuit of transistor 16 may alternatively be formed as is shown in FIG. 4. In fact, it is known that coil 21 may be replaced by the parallel arrangement of a diode 21' and a resistor 21" by which the inverse current can be limited. To separate the path of the inverse current from that of the forward current the parallel arrangement of a the diode 29' and a resistor 29" must then be present. This leads to the circuit arrangement shown in the upper part of FIG. 4. This circuit arrangement may now be simplified if it is noted that diodes 25 and 21' on the one hand and diodes 23 and 29' on the other hand are series-arranged. The result is shown in the lower part of FIG. 4 which, as compared with the circuit arrangement of FIG. 1, employs one coil less and an additional resistor.
Transistors of the npn type are used in FIG. 3. If transistors of the pnp type are used, the relevant efficiency diodes must of course be reversed.In this connection it is to be noted that it is possible to obtain an output voltage V o with the aid of the modifications according to FIGS. 3b, c and d, which voltage is higher than input voltage V i . These modifications may be used in countries such as, for example, the United of America or France where the nominal mains voltage is 117 or 110 V without having to modify the rest of the circuit arrangement.
The above-mentioned remark regarding the sum of the diode currents only applies, however, for the modifications shown in FIGS. 3a and d.
If line output transistor 16 is not simultaneously driven with switching transistor 2, efficiency diodes 7 conducts simultaneously with transistor 16 i.e., during the period which is denoted by δ T in FIGS. 1 and 2b. During that period the output voltage V o of the chopper is stabilized so that the base current of transistor 16 is stabilized without further difficulty. However, a considerable drawback occurs. In FIG. 1 the reference numeral 26 denotes a safety circuit the purpose of which is to safeguard switching transistor 2 when the current supplied to load 11 and/or line deflection circuit 17 becomes to high, which happens because the chopper stops. After a given period output voltage V o is built up again, but gradually which means that the ratio δ is initially small in the order of 0.1. All this is described in U.S. patent No. 3,629,686. The same phenomenon occurs when the display device is switched on. Since δ = 0.1 corresponds to approximately 6 μs when T = 64 μs, efficiency diode 7 conducts in that case for 64 - 6 = 58 μus so that transistor 16 is already switched on at the end of the scan or at a slightly greater ratio δ during the flyback. This would cause an inadmissibly high dissipation. For this reason the simultaneous drive is therefore to be preferred.
Pulse oscillator 6 applies pulses of line frequency to modulator 5. It may be advantageous to have two line frequency generators as already described, to wit pulse oscillator 6 and line oscillator 6' which is present in the picture display device and which is directly synchronized in known manner by line synchronizing pulses 7'. In fact, in this case line oscillator 6' applies a signal of great amplitude and free from interference to pulse oscillator 6. However, it is alternatively possible to combine pulse oscillator 6 and line oscillator 6' in one single oscillator 6" (see FIG. 1) which results in an economy of components. It will be evident that line oscillator 6' and oscillator 6" may alternatively be synchronized indirectly, for example, by means of a phase discriminator. It is to be noted neither pulse oscillator 6, line oscillator 6' and oscillator 6" nor modulator 5 can be fed by the supply described since output voltage V o is still not present when the mains voltage is switched on. Said circuit arrangements must therefore be fed directly from the input terminals. If as described above these circuit arrangements are to be separated from the mains, a small separation transformer can be used whose primary winding is connected between the mains voltage terminals and whose secondary winding is connected to ground at one end and controls a rectifier at the other end.
Capacitor 27 is arranged parallel to efficiency diode 7 so as to reduce the dissipation in switching transistor 2. In fact, if transistor 2 is switched off by the pulsatory control voltage, its collector current decreases and its collector-emitter voltage increases simultaneously so that the dissipated power is not negligible before the collector current has becomes zero. If efficiency diode 7 is shunted by capacitor 27 the increase of the collector-emitter voltage is delayed i.e., this voltage does not assume high values until the collector current has already been reduced. It is true that in that case the dissipation in transistor 2 slightly increases when it is switched on by the pulsatory control voltage but on the other hand since the current flowing through diode 7 has decreased due to the presence of the secondary windings, its inverse current is also reduced when transistor 2 is switched on and hence its dissipation has become smaller. In addition it is advantageous to delay these switching-on and switching-off periods to a slight extent because the switching pulses then contain fewer Fourier components of high frequency which may cause interferences in the picture display device and which may give rise to visible interferences on the screen of the display tube. These interferences occupy a fixed position on the displayed image because the switching frequency is the line frequency which is less disturbing to the viewer. In a practical circuit wherein the line frequency is 15,625 Hz and wherein switching transistor 2 is an experimental type suitable for a maximum of 350 V collector-emitter voltage or 1 A collector current and wherein efficiency diode 7 is of the Philips type BA 148 the capacitance of capacitor 27 is approximately 680 pF whilst the load is 70 W on the primary and 20 W on the secondary side of transformer 9. The collector dissipation upon switching off is 0.3 W (2.5 times smaller than without capacitor 27) and 0.7 W upon switching on.
A practical embodiment of the described example with the reference numerals given provides an output for the supply of approximately 85 percent at a total load of 90 W, the internal resistance for direct current loads being 1.5 ohms and for pulsatory currents being approximately 10 ohms. In case of a variation of ± 10 percent of the mains voltage, output voltage V o is stable within 0.4 V. Under the nominal circumstances the collector dissipation of switching transistor 2 is approximately 2.5 W.
Since the internal resistance of the supply is so small, it can be used advantageously, for example, at terminal 15 for supplying a class-B audio amplifier which forms part of the display device. Such an amplifier has the known advantages that its dissipation is directly proportional to the amplitude of the sound to be reproduced and that its output is higher than that of a class-A amplifier. On the other hand a class-A amplifier consumes a substantially constant power so that the internal resistance of the supply voltage source is of little importance. However, if this source is highly resistive, the supply voltage is modulated in the case of a class-B amplifier by the audio information when the sound intensity is great which may detrimentally influence other parts of the display device. This drawback is prevented by means of the supply according to the invention.
The 50 Hz ripple voltage which is superimposed on the rectified input voltage V i is compensated by comparison circuit 12 and modulator 5 since this ripple voltage may be considered to be a variation of input voltage V i . A further compensation is obtained by applying a portion of this ripple voltage with suitable polarity to comparison circuit 12. It is then sufficient to have a lower value for the smoothing capacitor which forms part of rectifier circuit 1 (see FIG. 3). The parabola voltage 28 of field frequency originating from the field time base is applied to the same circuit 12 so as to correct the East-West pincushion distortion.
PAL decoder tda3560A
The PHILIPS TDA3560A
is a decoder for the PAL colour television standard. It combines all functions required for the identification
and demodulation of PAL signals. Furthermore it contains a luminance amplifier, an RGB-matrix and amplifier. These
amplifiers supply output signals up to 5 V peak-to-peak (picture information) enabling direct drive of the discrete output
stages. The circuit also contains separate inputs for data insertion, analogue as well as digital, which can be used for
text display systems (e.g. (Teletext/broadcast antiope), channel number display, etc. Additional to the TDA3560, the
circuit includes the following features:
· The peak white limiter is only active during the time that the 9,3 V level at the output is exceeded. The start of the
limiting function is delayed by one line period. This avoids peak white limiting by test patterns which have abrupt
transitions from colour to white signals.
· The brightness control is obtained by inserting a variable pulse in the luminance channel. Therefore the ratio of
brightness variation and signal amplitude at the three outputs will be identical and independent of the difference in gain
of the three channels. Thus discolouring due to adjustment of contrast and brightness is avoided.
· Improved suppression of the internal RGB signals when the device is switched to external signals, and vice versa.
· Non-synchronized external RGB signals do not disturb the black level of the internal signals.
· Improved suppression of the residual 4,4 MHz signal in the RGB output stages.
· Cascoded stages in the demodulators and burst phase detector minimize the radiation of the colour demodulator
inputs.
· High current capability of the RGB outputs and the chrominance output.
APPLICATION INFORMATION
The function is described against the corresponding pin
number.
1. + 12 V power supply
The circuit gives good operation in a supply voltage range
between 8 and 13,2 V provided that the supply voltage for
the controls is equal to the supply voltage for the
TDA3561A. All signal and control levels have a linear
dependency on the supply voltage. The current taken by
the device at 12 V is typically 85 mA. It is linearly
dependent on the supply voltage.
2. Control voltage for identification
This pin requires a detection capacitor of about 330 nF for
correct operation. The voltages available under various
signal conditions are given in the specification.
3. Chrominance input
The chroma signal must be a.c.-coupled to the input.
Its amplitude must be between 55 mV and 1100 mV
peak-to-peak (25 mV to 500 mV peak-to-peak burst
signal). All figures for the chroma signals are based on a
colour bar signal with 75% saturation, that is the
burst-to-chroma ratio of the input signal is 1 : 2,25.
4. Reference voltage A.C.C. detector
This pin must be decoupled by a capacitor of about 330
nF. The voltage at this pin is 4,9 V.
5. Control voltage A.C.C.
The A.C.C. is obtained by synchronous detection of the
burst signal followed by a peak detector. A good noise
immunity is obtained in this way and an increase of the
colour for weak input signals is prevented. The
recommended capacitor value at this pin is 2,2 mF.
6. Saturation control
The saturation control range is in excess of 50 dB.
The control voltage range is 2 to 4 V. Saturation control is
a linear function of the control voltage.
When the colour killer is active, the saturation control
voltage is reduced to a low level if the resistance of the
external saturation control network is sufficiently high.
Then the chroma amplifier supplies no signal to the
demodulator. Colour switch-on can be delayed by proper
choice of the time constant for the saturation control
setting circuit.
When the saturation control pin is connected to the power
supply the colour killer circuit is overruled so that the colour
signal is visible on the screen. In this way it is possible to
adjust the oscillator frequency without using a frequency
counter (see also pins 25 and 26).
7. Contrast control
The contrast control range is 20 dB for a control voltage
change from + 2 to + 4 V. Contrast control is a linear
function of the control voltage. The output signal is
suppressed when the control voltage is 1 V or less. If one
or more output signals surpasses the level of 9 V the peak
white limiter circuit becomes active and reduces the output
signals via the contrast control by discharging C2 via an
internal current sink.
8. Sandcastle and field blanking input
The output signals are blanked if the amplitude of the input
pulse is between 2 and 6,5 V. The burst gate and clamping
circuits are activated if the input pulse exceeds a level of
7,5 V.
The higher part of the sandcastle pulse should start just
after the sync pulse to prevent clamping of video signal on
the sync pulse. The width should be about 4 ms for proper
A.C.C. operation.
9. Video-data switching
The insertion circuit is activated by means of this input by
an input pulse between 1 V and 2 V. In that condition, the
internal RGB signals are switched off and the inserted
signals are supplied to the output amplifiers. If only normal
operation is wanted this pin should be connected to the
negative supply. The switching times are very short
(< 20 ns) to avoid coloured edges of the inserted signals
on the screen.
10. Luminance signal input
The input signal should have a peak-to-peak amplitude of
0,45 V (peak white to sync) to obtain a black-white output
signal to 5 V at nominal contrast. It must be a.c.-coupled to
the input by a capacitor of about 22 nF. The signal is
clamped at the input to an internal reference voltage.
A 1 kW luminance delay line can be applied because the
luminance input impedance is made very high.
Consequently the charging and discharging currents of the
coupling capacitor are very small and do not influence the
signal level at the input noticeably. Additionally the
coupling capacitor value may be small.
PHILCO TX927 COLOR "ANTRANCITE" CHASSIS TX10 (CHASSIS THORN TX10) Video signal processing circuit for a color television receiver PHILIPS TDA3560: In a video signal processing circuit for a color television receiver, a brightness setting, which is operative for external color signals as well as for internal color signals and which does not produce a color shift, can be obt
ained by combining with the luminance signal (Y) a
level shift signal (H) the amplitude of which is adjustable by the
brightness setting and by employing in each color channel two clamping
circuits, the first one of which clamps a first reference level (RL1)
in the external color signal (ER, EG, EB) onto a combination of the
level shift signal and the internal color signal (R, G, B) and the
second clamping circuit clamps a second reference leve (RL2)
which occurs in the sum signal of the internal and the external color
signal when the level shift signal has zero value, onto the cutoff level
of the relevant electron gun of a picture display tube.1. A video signal processing circuit for a color television receiver having inputs for a luminance signal, for color difference signals and for external color signals, comprising respective matrix circuits for combining the respective color difference signals with the luminance signal to form respective color signals, respective first clamping circuits for clamping the respective external color signals onto the respective color signals, respective combining circuits for combining the respective clamped external color signals with the respective color signals, respective second clamping circuits for clamping the outputs of the respective combining circuits onto a predetermined level, and a brightness setting circuit, characterized in that the first clamping circuits act on a first reference level in said respective external color signals occurring in a first group of periods and the second clamping circuits act on a second reference level occurring in a second group of periods which differ from the periods of the first group, while the brightness setting circuit is an amplitude setting circuit for a level shift signal, which is combined with the luminance signal prior to processing the color difference signals, with which the relative position of the second reference level with respect to the remaining portion of the luminance signal is adjustable.
2. A video signal processing circuit as claimed in claim 1, characterized in that the respective first and second clamping circuits are operative alternately and every other line flyback period.
Description:
BACKGROUND OF THE INVENTION
The invention relates to a video signal processing circuit for a color television receiver having inputs for a luminance signal, for color difference signals, and for external color signals, comprising a matrix circuitfor
combining a color difference signal with the luminance signal to form a
color signal, a first clamping circuit for clamping an external color
signal onto the corresponding color signal, a combining circuit for
combining a clamped external color signal with the corresponding color
signal, a second clamping circuit acting on an output signal of the
combining circuit and a brightness setting circuit.
A video signal processing circuit of the type defined above is described in Philip Data Handbook for Integrated Circuits, Part 2, May, 1980 as IC TDA3560. The brightness setting, which is common for internal and external video signals, is obtained by means of a common direct current level setting of the second clamping circuits. The settings of the three electron guns of a picture display tube coupled to the outputs of the video signal processing circuit are changed to an equal extent by this direct current level setting as a result whereof, due to the mutual differences in the efficiency of the phosphors of the picture display tube, a color shift may occur at a brightness adjustment. It is an object of the invention to prevent this.
SUMMARY OF THE INVENTION
According to the invention, a video signal processing circuit of the type defined in the preamble is therefore characterized in that the first clamping circuit acts on a first reference level occurring in a first group of periods and the second clamping circuit acts on a second reference level occurring in a second group of periods which differ from the periods of the first group, while the brightness setting circuit is an amplitude setting circuit for a level shift signal with which the relative position of the second reference level with respect to the remaining portion of the luminance signal is adjustable.
Owing to the measure in accordance with the invention, the common setting of the brightness for internal video signals is maintained and a color shift is prevented from occurring at a brightness setting.
DESCRIPTION OF THE DRAWINGS
An embodiment of the invention will now be further described by way of example with reference to the accompanying drawings.
In the drawings:
FIG. 1 illustrates, by means of a block schematic circuit diagram, a video signal processing circuit in accordance with the invention; and
FIG. 2 shows some waveforms such as they may occur in the circuit shown in FIG. 1.
DESCRIPTION OF THE PREFERRED EMBODIMENT
In
FIG. 1, an external red color signal ER' is applied to an input 1, a
red color difference signal (R-Y) to an input 3, an external green color
signal EG' to an input 5, a luminance signal Y to an input 7, a green
color difference signal (G-Y) to an input 9, an external blue color
signal EB' to an input 11, a blue color difference signal (B-Y) to an
input 13 and a synchronizing signal S to an input 15.
The luminance signal at the input 7 is shown in FIG. 2 as a waveform 207. In the line flyback periods this luminance signal has a black level Z which, for simplicity, is assumed to occur in all cases during the whole line flyback period but which may, of course, alternatively occur during only a portion of that line flyback period.
The luminance signal Y is applied to an input 17 of a combining circuit 19. To a further input 21 thereof, a level shift signal H is applied which, via an amplitude setting circuit 23, is obtained from an output 25 of a pulse generator 27, to an input 29 of which the synchronizing signal S is applied.
The level shift signal H is shown in FIG. 2 as a waveform 221 which in this case has a zero amplitude every other line flyback period and at other times an amplitude which depends on the setting of the amplitude setting circuit 23.
The respective color
difference signals (R-Y), (G-Y) and (B-Y) at the respective inputs 3, 9
and 13, are applied to inputs 31, 33 and 35, respectively, of matrix
circuits 37, 39 and 41, respectively, to respective inputs 43, 45 and 47
of which the combination Y+H of the luminance signal (Y) and the level
shift signal (H) is applied, and from respective outputs 49, 51 and 53,
the red (R) and green (G) and blue (B) color signals are obtained. FIG. 2
shows the red color signal of said color signals as a waveform 249.
The respective external color signals ER', EG' and EB' at the respective inputs 1, 5 and 11 are applied to respective inputs 61, 63 and 65 of respective combining circuits 67, 69 and 71 via respective capacitors 55, 57 and 59. Further inputs 73, 75 and 77, respectively, of the combining circuits 67, 69 and 71, respectively, are connected to the outputs 49, 51 and 53, respectively, of the matrix circuits 37, 39 and 41, respectively, and receive the red, green and blue color signals, respectively.
Arranged between the inputs 61 and 73, 63 and 75, and 65 and 77, respectively, there are first clamping circuits 79, 81 and 83, respectively, which, under the control of a pulse signal K1 coming from an output 84 of the pulse generator 27, clamps a first reference level RL1 in the respective external color signals ER', EG' and EB' onto the respective color signals R, G and B, as a result of which the respective clamped external color signals ER, EG and EB at the respective inputs 61, 63 and 65 of the combining circuits 67, 69 and 71 are produced, the signal level ER at the input 61 of the combining circuit 67 being shown in FIG. 2 as the waveform 261. The pulse signal K1 is shown in FIG. 2 as the waveform 284.
At respective outputs 85, 87 and 89 of the combining circuits 67, 69 and 71, respectively, there are now produced signals which are the sums of the respective clamped external color signals ER, EG and EB and the respective color signals R, G and B. Via respective capacitors 91, 93 and 95, said sum signals (ER+R), (EG+G) and (EB+B), respectively, are applied to respective inputs 97, 99 and 100 of respective video output amplifiers 102, 104 and 106, respective outputs 108, 110 and 112 of which being connected to respective cathodes of a picture display tube 114.
Second clamping circuits 116, 118 and 120, respectively, which are rendered operative by a pulse signal K2 coming from an output 122 of the pulse generator 27 and whereby a second reference level RL2 in the signals at the respective inputs 97, 99 and 100 is adjusted to a fixed potential, zero potential here, are connected to the respective inputs 97, 99 and 100 of the respective video output amplifiers 102, 104 and 106. This is shown in FIG. 2 by means of the waveform297 for the signal (ER+R) at the input 97 of the
video output amplifier 102. For the sake of clearness, the luminance
signal (Y) and the red color difference signal (R-Y) are assumed to have
zero values.
The picture display tube 114 has a deflection circuit 124 which is controlled by signals coming from outputs 126 and 128, respectively, of the pulse generator 27.
On the basis of FIG. 2, it will now be demonstrated that the brightness of the color signals as well as of the external color signals is adjustable by means of the amplitude setting circuit 23, more specifically in such a ratio, occurring at the picture display tube 114, that no color shift is produced.
If a luminance signal Y and a color difference signal (R-Y) are produced and the external color signal ER' has zero value, the signal at the output 49 of the matrix circuit 37 has the waveform 249 and likewise the signal at the input 97 of the video output amplifier 108, as during the occurrence of the signal K2 (waveform 222), the second clamping circuit 116 has adjusted the second reference level RL2 to zero, which corresponds to the cutoff level of the relevant cathode of the picture display tube 114. Outside the periods in which signal is clamped to the second reference level RL2, the black level, shown in the waveform 249 by means of a dashed line, of the color signal at the input 97 of the video amplifier is determined by the amplitude of the level shift signal H, which, in response to the video output amplifier gain factors which are adapted to the efficiencies of the phosphors of the picture display tube, are applied in the relevant signal paths to the cathodes of the picture display tube 114 to said cathodes in such an amplitude ratio that no color shift can be produced.
If there is an external color signal but no luminance and color difference signals (Y=O, R-Y=O, G-Y=O, B-Y=O), then a signal is produced at the input 97 of the video output amplifier 102 which has the waveform 297 and which, during the occurrence of the second reference level RL2, is clamped onto zero by the second clamping circuit 116 by means of the clamping pulses K2 and which consequently corresponds to the cutoff level of the relevant cathode of the picture display tube 114. During the occurrence of the first reference level RL1 in the signal ER', the first clamping circuit 79 clamps the signal ER (waveform 261) at the input 61 of the combining circit 61 onto the output signal of the matrix circuit 37 during the occurrence of the clamping pulses K1 (waveform 284). Now this output signal has the waveform 221, as R-Y and Y have zero values. From the waveform 297, it now appears that the signal ER+R, which in this case is equal to ER+H, has, outside the periods in which the second reference level RL2 occurs in the waveform 297, a black level which is indicated by means of a dashed line and is determined by the amplitude of the level shift signal H. Also now this amplitude is applied in the proper ratio to the cathodes of the picture display tube 114 by the video output amplifier gain factors which are adapted to the efficiencies of the phosphors of the picture display tube 114, so that no color shift can be produced.
It will be obvious that it is not imperative that the clamping pulses K1 and K2 be produced alternately and every other line flyback period. If so desired, the clamping pulses K1 may, for example, occur in a number of line trace periods of the field trace which are located outside the visible picture plane, and the clamping pulses K2 may occur in the line flyback periods. The clamping pulses K2 must be produced in the period in which the level shift signal causes the second reference level RL2 and the clamping pulses K1 outside said periods and in the periods the first level reference level RL1 occurs.
In the above-described embodiment the clamping circuits are provided in the form of short-circuiting switches which are arranged subsequent to capacitors which have for their function to block direct current signals. It will be obvious, that, if so desired, clamping circuits in the form of control circuits may alternatively be used and that in that event, if so desired, blocking the direct current component by a capacitor may be omitted.
If so desired, instead of an adder circuit 19, an insertion circuit may be employed by means of which, in the appropriate periods of the luminance signal, when the signal K2 is produced the reference level Z then present, is replaced by a new level which is influencable by the brightness setting .
The invention relates to a video signal processing circuit for a color television receiver having inputs for a luminance signal, for color difference signals, and for external color signals, comprising a matrix circuit
for
combining a color difference signal with the luminance signal to form a
color signal, a first clamping circuit for clamping an external color
signal onto the corresponding color signal, a combining circuit for
combining a clamped external color signal with the corresponding color
signal, a second clamping circuit acting on an output signal of the
combining circuit and a brightness setting circuit. A video signal processing circuit of the type defined above is described in Philip Data Handbook for Integrated Circuits, Part 2, May, 1980 as IC TDA3560. The brightness setting, which is common for internal and external video signals, is obtained by means of a common direct current level setting of the second clamping circuits. The settings of the three electron guns of a picture display tube coupled to the outputs of the video signal processing circuit are changed to an equal extent by this direct current level setting as a result whereof, due to the mutual differences in the efficiency of the phosphors of the picture display tube, a color shift may occur at a brightness adjustment. It is an object of the invention to prevent this.
SUMMARY OF THE INVENTION
According to the invention, a video signal processing circuit of the type defined in the preamble is therefore characterized in that the first clamping circuit acts on a first reference level occurring in a first group of periods and the second clamping circuit acts on a second reference level occurring in a second group of periods which differ from the periods of the first group, while the brightness setting circuit is an amplitude setting circuit for a level shift signal with which the relative position of the second reference level with respect to the remaining portion of the luminance signal is adjustable.
Owing to the measure in accordance with the invention, the common setting of the brightness for internal video signals is maintained and a color shift is prevented from occurring at a brightness setting.
DESCRIPTION OF THE DRAWINGS
An embodiment of the invention will now be further described by way of example with reference to the accompanying drawings.
In the drawings:
FIG. 1 illustrates, by means of a block schematic circuit diagram, a video signal processing circuit in accordance with the invention; and
FIG. 2 shows some waveforms such as they may occur in the circuit shown in FIG. 1.
DESCRIPTION OF THE PREFERRED EMBODIMENT
In
FIG. 1, an external red color signal ER' is applied to an input 1, a
red color difference signal (R-Y) to an input 3, an external green color
signal EG' to an input 5, a luminance signal Y to an input 7, a green
color difference signal (G-Y) to an input 9, an external blue color
signal EB' to an input 11, a blue color difference signal (B-Y) to an
input 13 and a synchronizing signal S to an input 15. The luminance signal at the input 7 is shown in FIG. 2 as a waveform 207. In the line flyback periods this luminance signal has a black level Z which, for simplicity, is assumed to occur in all cases during the whole line flyback period but which may, of course, alternatively occur during only a portion of that line flyback period.
The luminance signal Y is applied to an input 17 of a combining circuit 19. To a further input 21 thereof, a level shift signal H is applied which, via an amplitude setting circuit 23, is obtained from an output 25 of a pulse generator 27, to an input 29 of which the synchronizing signal S is applied.
The level shift signal H is shown in FIG. 2 as a waveform 221 which in this case has a zero amplitude every other line flyback period and at other times an amplitude which depends on the setting of the amplitude setting circuit 23.
The respective color
difference signals (R-Y), (G-Y) and (B-Y) at the respective inputs 3, 9
and 13, are applied to inputs 31, 33 and 35, respectively, of matrix
circuits 37, 39 and 41, respectively, to respective inputs 43, 45 and 47
of which the combination Y+H of the luminance signal (Y) and the level
shift signal (H) is applied, and from respective outputs 49, 51 and 53,
the red (R) and green (G) and blue (B) color signals are obtained. FIG. 2
shows the red color signal of said color signals as a waveform 249. The respective external color signals ER', EG' and EB' at the respective inputs 1, 5 and 11 are applied to respective inputs 61, 63 and 65 of respective combining circuits 67, 69 and 71 via respective capacitors 55, 57 and 59. Further inputs 73, 75 and 77, respectively, of the combining circuits 67, 69 and 71, respectively, are connected to the outputs 49, 51 and 53, respectively, of the matrix circuits 37, 39 and 41, respectively, and receive the red, green and blue color signals, respectively.
Arranged between the inputs 61 and 73, 63 and 75, and 65 and 77, respectively, there are first clamping circuits 79, 81 and 83, respectively, which, under the control of a pulse signal K1 coming from an output 84 of the pulse generator 27, clamps a first reference level RL1 in the respective external color signals ER', EG' and EB' onto the respective color signals R, G and B, as a result of which the respective clamped external color signals ER, EG and EB at the respective inputs 61, 63 and 65 of the combining circuits 67, 69 and 71 are produced, the signal level ER at the input 61 of the combining circuit 67 being shown in FIG. 2 as the waveform 261. The pulse signal K1 is shown in FIG. 2 as the waveform 284.
At respective outputs 85, 87 and 89 of the combining circuits 67, 69 and 71, respectively, there are now produced signals which are the sums of the respective clamped external color signals ER, EG and EB and the respective color signals R, G and B. Via respective capacitors 91, 93 and 95, said sum signals (ER+R), (EG+G) and (EB+B), respectively, are applied to respective inputs 97, 99 and 100 of respective video output amplifiers 102, 104 and 106, respective outputs 108, 110 and 112 of which being connected to respective cathodes of a picture display tube 114.
Second clamping circuits 116, 118 and 120, respectively, which are rendered operative by a pulse signal K2 coming from an output 122 of the pulse generator 27 and whereby a second reference level RL2 in the signals at the respective inputs 97, 99 and 100 is adjusted to a fixed potential, zero potential here, are connected to the respective inputs 97, 99 and 100 of the respective video output amplifiers 102, 104 and 106. This is shown in FIG. 2 by means of the waveform
297 for the signal (ER+R) at the input 97 of the
video output amplifier 102. For the sake of clearness, the luminance
signal (Y) and the red color difference signal (R-Y) are assumed to have
zero values. The picture display tube 114 has a deflection circuit 124 which is controlled by signals coming from outputs 126 and 128, respectively, of the pulse generator 27.
On the basis of FIG. 2, it will now be demonstrated that the brightness of the color signals as well as of the external color signals is adjustable by means of the amplitude setting circuit 23, more specifically in such a ratio, occurring at the picture display tube 114, that no color shift is produced.
If a luminance signal Y and a color difference signal (R-Y) are produced and the external color signal ER' has zero value, the signal at the output 49 of the matrix circuit 37 has the waveform 249 and likewise the signal at the input 97 of the video output amplifier 108, as during the occurrence of the signal K2 (waveform 222), the second clamping circuit 116 has adjusted the second reference level RL2 to zero, which corresponds to the cutoff level of the relevant cathode of the picture display tube 114. Outside the periods in which signal is clamped to the second reference level RL2, the black level, shown in the waveform 249 by means of a dashed line, of the color signal at the input 97 of the video amplifier is determined by the amplitude of the level shift signal H, which, in response to the video output amplifier gain factors which are adapted to the efficiencies of the phosphors of the picture display tube, are applied in the relevant signal paths to the cathodes of the picture display tube 114 to said cathodes in such an amplitude ratio that no color shift can be produced.
If there is an external color signal but no luminance and color difference signals (Y=O, R-Y=O, G-Y=O, B-Y=O), then a signal is produced at the input 97 of the video output amplifier 102 which has the waveform 297 and which, during the occurrence of the second reference level RL2, is clamped onto zero by the second clamping circuit 116 by means of the clamping pulses K2 and which consequently corresponds to the cutoff level of the relevant cathode of the picture display tube 114. During the occurrence of the first reference level RL1 in the signal ER', the first clamping circuit 79 clamps the signal ER (waveform 261) at the input 61 of the combining circit 61 onto the output signal of the matrix circuit 37 during the occurrence of the clamping pulses K1 (waveform 284). Now this output signal has the waveform 221, as R-Y and Y have zero values. From the waveform 297, it now appears that the signal ER+R, which in this case is equal to ER+H, has, outside the periods in which the second reference level RL2 occurs in the waveform 297, a black level which is indicated by means of a dashed line and is determined by the amplitude of the level shift signal H. Also now this amplitude is applied in the proper ratio to the cathodes of the picture display tube 114 by the video output amplifier gain factors which are adapted to the efficiencies of the phosphors of the picture display tube 114, so that no color shift can be produced.
It will be obvious that it is not imperative that the clamping pulses K1 and K2 be produced alternately and every other line flyback period. If so desired, the clamping pulses K1 may, for example, occur in a number of line trace periods of the field trace which are located outside the visible picture plane, and the clamping pulses K2 may occur in the line flyback periods. The clamping pulses K2 must be produced in the period in which the level shift signal causes the second reference level RL2 and the clamping pulses K1 outside said periods and in the periods the first level reference level RL1 occurs.
In the above-described embodiment the clamping circuits are provided in the form of short-circuiting switches which are arranged subsequent to capacitors which have for their function to block direct current signals. It will be obvious, that, if so desired, clamping circuits in the form of control circuits may alternatively be used and that in that event, if so desired, blocking the direct current component by a capacitor may be omitted.
If so desired, instead of an adder circuit 19, an insertion circuit may be employed by means of which, in the appropriate periods of the luminance signal, when the signal K2 is produced the reference level Z then present, is replaced by a new level which is influencable by the brightness setting .
PHILCO TX927 COLOR "ANTRANCITE" CHASSIS TX10 (CHASSIS THORN TX10) Digital phase locked loop tuning system / PLL FREQUENCY SYNTHESIZER:(ITT SAA1274 SAA1275 SAA1276)
1. A digital phase locked loop tuning system responsive to a local oscillator signal for producing a frequency synthesized digital output signal which is utilized to control the frequency of the local oscillator, the local oscillator having a plurality of frequencies associated therewith corresponding, respectively, to a plurality of selectable channels, each of the channels being allocated to one of at least two channel groups with each channel in a particular channel group being separated from an adjacent channel in the particular channel group by a predetermined frequency spacing of the local oscillator, comprising:
programming means responsive to an input signal representing a selected channel number of a particular channel group for generating a first digital control signal having a value corresponding to the selected channel number and for generating a second digital control signal representative of said particular channel group, said second digital control signal being a constant predetermined value for all of said channel numbers that are within said group; and
programmable divider means coupled to said programming means being responsive to said first, second digital control signals and the local oscillator signal, in a local oscillator mode, for generating the digital output signal which is representative of a desired frequency corresponding to said selected channel number, said programmable divider means including means for dividing the local oscillator signal by first and second factors, said first factor being related to the frequency separation between local oscillator signals by an integral number, the local oscillator signal being divided by said first factor during a first interval for a first number of periods of the output signal and being divided by said second factor for a second number of periods of the output signal, said first number of periods being related to the number of the channel selected, said second number being related to the channel group within which the selected channel lies.
2. Phase locked loop system according to claim 1, wherein said programming means including means coupled to said programming means for receiving an MFT signal and being responsive to said MFT signal for altering said first and second digital control signals, and said programmable divider means being responsive to said altered digital control signals for generating an altered system output frequency. 3. Phase locked loop system according to claim 2, wherein said programming means includes first terminal means coupled to said programming means for receiving an AFT control signal, and first logic means responsive to the input signal and the AFT control signal for generating the first digital control signal. 4. Phase locked loop system according to claim 3, wherein said programming means includes second logic means coupled to said first logic means and responsive to the AFT control signal for generating the second digital control signal. 5. Phase locked loop system according to claim 4, wherein said second logic means includes group decoder means coupled to said first logic means. 6. Phase locked loop circuit means according to claim 5, wherein said second logic means includes memory means coupled to said group decoder means and to said first terminal means. 7. Phase locked loop system according to claim 6, wherein said second logic means includes second terminal means for receiving an MFT signal, and up/down counter latch means coupled to said memory means and to said second terminal means for altering said first and second digital control signals in response to said MFT signal. 8. Phase locked loop system according to claim 7, wherein said second logic means includes adder means coupled to said up/down counter latch means to said memory means. 9. Phase locked loop system according to claim 3, wherein said first logic means includes channel number generator means coupled to said first terminal means and responsive to said input signal. 10. Phase locked loop system according to claim 9, wherein said channel number generator means includes first and second data selector means coupled to said first terminal means, and adder means coupled to said second data selector means and to said up/down counter latch means. 11. Phase locked loop system according to claim 1, wherein said means for dividing the local oscillator signal includes programmable counter means for generating a modulus control output signal, and variable modulus prescaler divider means coupled to and responsive to said programmable counter means, said variable modulus prescaler divider means dividing the local oscillator signal by said first and second factors. 12. Phase locked loop system according to claim 11, wherein said programmable counter means includes third data selector means coupled to receive said first and second digital control signals and said modulus control signal. 13. Phase locked loop system according to claim 12, wherein said programmable counter means includes a programmable counter coupled to said third data selector means and to said variable modulus prescaler divider means. 14. Phase locked loop system according to claim 13, wherein said programmable counter means includes look ahead circuit means coupled to said programmable counter, and divide by two circuit means coupled to said look ahead circuit means for generating said modulus control output signal. 15. Phase locked loop tuning system according to claim 1 including digital automatic fine tuning (AFT) means wherein:
said programmable divider means includes switching means responsive to an AFT control signal to inhibit the local oscillator signal to said programmable divider means and to provide an input signal thereto of a different frequency than the local oscillator signal; and
said programming means including logic means responsive to said AFT control signal for altering said first and second digital control signals to predetermined values to cause the phase locked loop tuning system to be operable in an automatic fine tuning mode.
16. Phase locked loop tuning system of claim 15 wherein said programmable divider means includes:
programmable counter means for generating first and second modulus control signals; and
dual modulus prescaler means responsive to said first modulus control signal for dividing the local oscillator signal in said local oscillator mode and said input signal of a different frequency in said automatic fine tuning mode by said first factor which is equal to the integer six and being responsive to said second modulus control signal for dividing said local oscillator signal and said input signal of a different frequency by said second factor which is equal to the integer five respectively.
17. Phase locked loop tuning system of claim 16 wherein said signal of a different frequency is an intermediate frequency signal provided by the tuning system and supplied to said switching means.
variable modulus divider means for selectively dividing the frequency of the local oscillator signal by first and second factors in response to a modulus control signal to provide an output signal, said first factor being related to the frequency separation between local oscillator signals by an integral number; and
programmable means for generating said modulus control signal to cause said variable modulus divider means to divide by said first factor during a first interval for a first number of periods of said output signal and to divide by said second factor during a second interval for a second number of periods of said output signal, said first number of periods being related to the number of the channel selected, said second number of periods being related to the channel group corresponding to the selected channel.
20. The phase locked loop tuning system of claim 19 wherein said programmable means includes:
programming means responsive to a selected channel input signal for producing first and second digital output signals, said first digital output signal being related to the selected channel number plus one of two constant values which are determined in accordance within which channel group the selected channel input signal lies, said second digital signal being a constant value for all selected channels within a channel group; and
programmable divider means responsive to said first and second digital output signals from said programming means for providing said variable modulus control signal and the frequency synthesized output signal.
21. The phase locked loop tuning system of claim 20 wherein said programming means includes automatic fine tuning (AFT) means responsive to a AFT control signal being applied thereto when the receiver is placed in an AFT mode wherein:
said variable modulus divider means is caused to receive a input signal different from the local oscillator signal;
said programming means being responsive to the AFT control signal for altering said first and second digital signals such that the receiver is finely tuned to the frequency of the received signal applied to the receiver.
22. The phase locked loop tuning system of claim 21 wherein said programming means includes means for receiving a manual fine tuning (MFT) signal for altering said first and second digital output signals, and said programmable divider means being responsive to said altered digital control signals for generating an altered output signal. 23. The phase locked loop tuning system of claim 19 wherein the one of said first and second factors is an even number and the other is an odd number. 24. The phase locked loop tuning system of claim 23 wherein said first factor is the integer six and said second factor is the integer five.
Description:
BACKGROUND OF THE INVENTIONThis invention relates to digital tuning systems, and more particularly, to a simplified digital phase locked loop (PLL) tuning system incorporating unique digital automatic fine tuning and manual fine tuning schemes.
Since the appearance of varactor tuners for television, many tuning address schemes have evolved for controlling them. PLL techniques have maintained a performance advantage but have suffered a cost disadvantage due to complexity, the high frequencies involved, the need for automatic fine tuning and in some localities, the need for a manual fine tuning arrangement. With the advances that have taken place in semiconductor technology in the last several years, the high operating frequencies no longer present a significant problem.
Prior art PLL systems for use in television tuners have not yet been able to incorporate an automatic fine tuning feature, nor have they been able to incorporate a manual fine tuning system which would enable the PLL tuning system to be intentionally offset in predetermined increments. Television sets normally have an automatic fine tuning (AFT) feature, but this is normally incorporated as a separate circuit which is not directly incorporated into the television tuner.
Therefore, it is a feature of this invention to provide a digital PLL tuning system which incorporates design techniques that vastly simplify the complexity of the PLL while at the same time allowing the system to meet the latest needs of a television tuning system or any other PLL tuning system which is addressed by a channel number.
It is another feature of this invention to provide a digital PLL tuning system that has the ability to automatically tune nonprecise station frequencies and the ability to be manually fine tuned.
It is yet another feature of the present invention to provide a digital PLL tuning system having only a single high speed programmable counter and requiring a ROM capacity of only 5 words by 9 bits.
It is still another feature of this invention to provide a digital PLL tuning system which performs the automatic fine tuning feature by utilizing the PLL tuning system as a digital discriminator.
It is yet another feature of this invention to provide a digital PLL tuning system incorporating a manual fine tuning (MFT) arrangement which is capable of intentionally offsetting the local oscillator frequency of a TV tuner in one megahertz steps or of offsetting TV IF frequency in steps of 125 kilohertz.
SUMMARY OF THE INVENTION
The preferred embodiment of the present invention includes a phase locked loop circuit means for an automatic frequency synthesizing system. The phase locked loop circuit means includes programming means which is responsive to an input signal representing a selected channel number for generating a first digital control signal representative of the selected channel number and for generating a second digital control signal representative of a predetermined group of channel numbers. A programmable divider means is coupled to the first and second digital control signals and generates a digital output signal representative of a desired system output frequency corresponding to the selected channel number.
The phase locked loop circuit means further includes an automatic fine tuning feature for fine tuning the phase locked loop output frequency to the exact frequency of the received signal. The system further includes a manual fine tuning provision which allows the phase locked loop operating frequency to be intentionally offset in predetermined increments.
CHASSIS TX10 SERVICE / REPAIRING SERVICE NOTES:
tx10 1515h remote panel no chan 3, mc14493p
tx10 baird 8233 tuning amnesia d345.
tx10 black horizontal lines, c776(100nf).
tx10 bottom blanking tr771(ztx450k),r786(100r).
tx10 bottom cramp- c782 (150nf)& ic771.
tx10 bottom lines tda3654
tx10 bright one side, c726(22uf).
tx10 channel 1 memory lost d345(aa143) .
tx10 channel change random tripping. r810 (150k) .
tx10 channel int changing. focus control arcing.
tx10 channel selection . c930 , c931.
tx10 cold bar graph d1441
tx10 cold field bounce tda1044 c777 (2200uf)
tx10 cold field bounce, c35 1uf in agc feed to sl1432 if preamplifier chip.
tx10 cold field bounce,ic741(tda2576).
tx10 color cast 12v reg ic621, tda3560. c616/7/8 (100nf)
tx10 color cast,r664,c616,c617,c618(100nf),ic601(tda3560).
tx10 color flickering. r627.
tx10 dead c732 10uf, 63v+resolder loptx earth pin
tx10 dead c732(10uf63v)exploded=pins t721.
tx10 dead choptr d704,c711,c712 chpotx pins.
tx10 dead choptr t705,d731.
tx10 dead choptr(tipl791a) t705,d731 r724(1k2) ,d704, c711, c712
tx10 dead d702 byx55-600
tx10 dead da12.
tx10 dead fuse+chopper , loptx pin 10 joints.
tx10 dead fuse, choptr+r724 1k2
tx10 dead lo ht r813(121k)
tx10 dead loptr d743 by588 some d743 are bt188b or by226.
tx10 dead r722 (220r)
tx10 dead r724 1k2, choptr tr721.
tx10 dead resolder t701 chopper tx pins.
tx10 dead t721 d831 .
tx10 dead thyristor da12 , dr03 , thyristor du04 , tu07.
tx10 dead tr801(bc547),r813(121k),t721,t702,r724,c711(2u2f).
tx10 dim/dark/no pic tda2654.
tx10 dim/no pic, tda3654 field
tx10 eht ok no raster green led d657 on crt base pcb,
tx10 ew bent sides rv851/852 , r864(8k2).
tx10 excess brill c726(22uf) r728(10k), c732
tx10 faint snd whistle c1104 1uf on panel pc1536 missing c1104
tx10 field bottom blank tr771 , r786 .
tx10 field bounce c35(1uf)
tx10 field collapse . c775 , sp6 ceramic.
tx10 field collapse c777(100uf)
tx10 field cramping c782 c773 c781 (100uf 35v)
tx10 field flag waving, c755 from 22n to 10n.
tx10 field poor interlace in centre of screen. replace capacitor c776 .
tx10 field roll r813(121k) .
tx10 flyback c776,r774 (620r), d771,r786 (470r) .
tx10 flyback lines c776(100nf),r774(620k),r786(470r),d771(in4007).
tx10 flyback lines r834(1m8),c726(22uf) r786(470r).
tx10 green screen 22k r664
tx10 horizontal lines across screen. c776 (100nf)
tx10 hum bar – replace capacitor c708 (22ouf 385v).
tx10 int bar graph cold,d1441.
tx10 int channel change rv721 focus pot.
tx10 int dead 12v regulator ic621.
tx10 int rolling/tripping arcing fb721.
tx10 int tripping,sqegging tr701,r704(27r).
tx10 int trips d801(6v2zen),d832,crt base earths,loptx pins.
tx10 int/no remote ir preamp.
tx10 interlace poor in centre of screen. c776 .
tx10 led lit all time ic1443 or c6(2u2f).
tx10 leds on bass/treble/balance permantly. ic1443.
tx10 looks like a low crt-replace 12v reg ic621.
tx10 line cramp striations, rgb leads to close to loptx.
tx10 line lin rv831,rv851,d831(by188).
tx10 line ringing,tripping d831.
tx10 line shift r613(10r) .
tx10 line speed faults first check r744 (30k) r802 (5k6)
tx10 line tearing-t721
tx10 line whistle d831,d743.
tx10 lines across pic,focus unit was arcing. tda2576a ic741
tx10 low brilliance – replace d657 led & r832 (150k) .
tx10 low brilliance,c606,rv601,c604,l604,ic601 crt base (white),r832(150k).
tx10 low height ,c775(5p6f),c781(100uf),tr771(ztx450k).
tx10 low hum varys with pic , video op trans on crt base pcb.
tx10 low snd ic561(tda1236),c582(6n8f).
tx10 low width , rv851
tx10 low width/tripping. d831(by188b/by226) .
tx10 loptr d743(by588/by226/bt188b) d831 by188b
tx10 loptr,choptr, r724(1k2).
tx10 memory d345 ,b341.c367(560pf).
tx10 middle line twinning, c776(100nf),c783(240pf).
tx10 mk2 field collapse tda3652( or tda3654 with 6k8 across r771)
tx10 no blue text . color decoder ic tda3560.
tx10 no brill d702 byx55-600 not by228.
tx10 no line op ic621.
tx10 no line sync ic741(tda2576a),ic1003(saa5030),r601(1k5).
tx10 no manual ctrl ,remote ok,tr258.
tx10 no pic d657 tr654/tr655.tr656
tx10 no pic d702
tx10 no pic l831,d702,c759,d738,d735,c758(33uf).
tx10 no pic no line d702(byw95c).
tx10 no pic snd ok, heater feed , pcb cracks
tx10 no pic snd ok. c759,d738, d735,c758(33uf)
tx10 no red no red text tda3560 .
tx10 no remote start tr410 bc237b) .
tx10 no signal/snd mute c22(330pf).
tx10 no snd. r243 r1243(4r7) .
tx10 no text sync saa5020.
tx10 no text.r1131(47k) ic1033(saa5030) due to focus control flash over.
tx10 norm snd alters,d101.
tx10 odd tuning controls sl430 chip ic105 on the remote control panel
tx10 only mixed text,pl31,has an extra grey flying . disconnect pin x
tx10 pc1500/1550 warm trip,d831 by188b.
tx10 pc1560 warm trips,r813 121k,bc547 tr801 12vreg zener d802
tx10 pic blanked across, c726(22uf).
tx10 pic fades , crt heater pins, loptx pins.
tx10 poor line sync c742(220uf), c745(100uf) c749 (4n7) tr345(bc237)
tx10 poor pic, lo a1’s, crt socket fault
tx10 poor sync. ic tda2576a.
tx10 poor video pbtr113 (bc237),d117 .
tx10 ramdom remote pl16/1.
tx10 random tripping r810(150k).
tx10 raster white c655(470uf) .
tx10 remote lo ,leds,d1,d2,d3.
tx10 remote no snd,no text, s402 switch stuck.
tx10 rolling hot r773(330k).
tx10 rolling hot. r773 330k
tx10 rolling tda2576a
tx10 side jitter on video pb tr113(bc237),d117,tr345(bc237).
tx10 slow snd,ic561(tda1236).
tx10 sound buzz ic621 (lm340t) l531,pl9.
tx10 sound buzz stereo- resolder/check panel earths.
tx10 sound crackling with volume turned down ic621 (lm340t) 12v reg.
tx10 sound distorted- replace c570 (100n) & c571(100n) .
tx10 sound lhs buzz – replace c1450 (10uf).
tx10 sound lo ic561 (tda1236) , c582 (6n8)
tx10 sound mute , c22 (330pf)
tx10 sound poor,c536(6n8),c544(22n), 12v reg ic621.
tx10 snow no signal ,c22(330pf)
tx10 snow, sl1430
tx10 spot burn- r834(1m8).
tx10 stby c137(470nf) c406(c106)
tx10 stby only remote tr410(bc237).
tx10 stby releases delete c406 or c106.
tx10 stby remote, tr410(bc236b).
tx10 stby. r724(1k2)
tx10 stereo whistle c103.
tx10 striations rhs c727(470uf).
tx10 sweep tuning ic344 (mc1449-9pb)
tx10 sweep tuning not stopping led flashes ic344 mc1449-9pb
tx10 sync poor ic33 (saa5030) ic1033
tx10 t/text mixed ok but no full text ensure pl31 grey lead is off .
tx10 text lines , scan coil shorts,tr771(ztx450k).
tx10 picture top cramping -c781 (100uf) & c773(100uf).
tx10 tripping focus pot,tr831(bu508a),ic771,t721(loptx),d831.
tx10 tripping t721.
tx10 trips on hi brill, c655(470uf)leaky.
tx10 trips tda3652( or tda3654 with 6k8 across r771)
tx10 trips tr831 (bu208a), r613(10) d801 (6.2v zenor) , r810 (150k) .
tx10 tuner drift, varicap tuner unit.
tx10 tuner sweeping at switch on, d356(itt44).
tx10 tuning drift on loud snd. il01 (lm341) 12v reg.
tx10 vertical lines wavy,int rolls r813(121k).
tx10 vol/color varies, loptx pin 1.
tx10 warm narrows/trips. d831(by226) d743
tx10 warm tripping d831(by188b),fb721,d702 leaky,r810(150k),r813(121k).
tx10 weak line sync c749(4n7f).
tx10 whistle d743 beads, glue on.
tx10 white spots, loud screeching ,hairline crack from earth point on the crt. base pcb
tx10 wide black line across pic,tda2576a
tx10 baird 8233 tuning amnesia d345.
tx10 black horizontal lines, c776(100nf).
tx10 bottom blanking tr771(ztx450k),r786(100r).
tx10 bottom cramp- c782 (150nf)& ic771.
tx10 bottom lines tda3654
tx10 bright one side, c726(22uf).
tx10 channel 1 memory lost d345(aa143) .
tx10 channel change random tripping. r810 (150k) .
tx10 channel int changing. focus control arcing.
tx10 channel selection . c930 , c931.
tx10 cold bar graph d1441
tx10 cold field bounce tda1044 c777 (2200uf)
tx10 cold field bounce, c35 1uf in agc feed to sl1432 if preamplifier chip.
tx10 cold field bounce,ic741(tda2576).
tx10 color cast 12v reg ic621, tda3560. c616/7/8 (100nf)
tx10 color cast,r664,c616,c617,c618(100nf),ic601(tda3560).
tx10 color flickering. r627.
tx10 dead c732 10uf, 63v+resolder loptx earth pin
tx10 dead c732(10uf63v)exploded=pins t721.
tx10 dead choptr d704,c711,c712 chpotx pins.
tx10 dead choptr t705,d731.
tx10 dead choptr(tipl791a) t705,d731 r724(1k2) ,d704, c711, c712
tx10 dead d702 byx55-600
tx10 dead da12.
tx10 dead fuse+chopper , loptx pin 10 joints.
tx10 dead fuse, choptr+r724 1k2
tx10 dead lo ht r813(121k)
tx10 dead loptr d743 by588 some d743 are bt188b or by226.
tx10 dead r722 (220r)
tx10 dead r724 1k2, choptr tr721.
tx10 dead resolder t701 chopper tx pins.
tx10 dead t721 d831 .
tx10 dead thyristor da12 , dr03 , thyristor du04 , tu07.
tx10 dead tr801(bc547),r813(121k),t721,t702,r724,c711(2u2f).
tx10 dim/dark/no pic tda2654.
tx10 dim/no pic, tda3654 field
tx10 eht ok no raster green led d657 on crt base pcb,
tx10 ew bent sides rv851/852 , r864(8k2).
tx10 excess brill c726(22uf) r728(10k), c732
tx10 faint snd whistle c1104 1uf on panel pc1536 missing c1104
tx10 field bottom blank tr771 , r786 .
tx10 field bounce c35(1uf)
tx10 field collapse . c775 , sp6 ceramic.
tx10 field collapse c777(100uf)
tx10 field cramping c782 c773 c781 (100uf 35v)
tx10 field flag waving, c755 from 22n to 10n.
tx10 field poor interlace in centre of screen. replace capacitor c776 .
tx10 field roll r813(121k) .
tx10 flyback c776,r774 (620r), d771,r786 (470r) .
tx10 flyback lines c776(100nf),r774(620k),r786(470r),d771(in4007).
tx10 flyback lines r834(1m8),c726(22uf) r786(470r).
tx10 green screen 22k r664
tx10 horizontal lines across screen. c776 (100nf)
tx10 hum bar – replace capacitor c708 (22ouf 385v).
tx10 int bar graph cold,d1441.
tx10 int channel change rv721 focus pot.
tx10 int dead 12v regulator ic621.
tx10 int rolling/tripping arcing fb721.
tx10 int tripping,sqegging tr701,r704(27r).
tx10 int trips d801(6v2zen),d832,crt base earths,loptx pins.
tx10 int/no remote ir preamp.
tx10 interlace poor in centre of screen. c776 .
tx10 led lit all time ic1443 or c6(2u2f).
tx10 leds on bass/treble/balance permantly. ic1443.
tx10 looks like a low crt-replace 12v reg ic621.
tx10 line cramp striations, rgb leads to close to loptx.
tx10 line lin rv831,rv851,d831(by188).
tx10 line ringing,tripping d831.
tx10 line shift r613(10r) .
tx10 line speed faults first check r744 (30k) r802 (5k6)
tx10 line tearing-t721
tx10 line whistle d831,d743.
tx10 lines across pic,focus unit was arcing. tda2576a ic741
tx10 low brilliance – replace d657 led & r832 (150k) .
tx10 low brilliance,c606,rv601,c604,l604,ic601 crt base (white),r832(150k).
tx10 low height ,c775(5p6f),c781(100uf),tr771(ztx450k).
tx10 low hum varys with pic , video op trans on crt base pcb.
tx10 low snd ic561(tda1236),c582(6n8f).
tx10 low width , rv851
tx10 low width/tripping. d831(by188b/by226) .
tx10 loptr d743(by588/by226/bt188b) d831 by188b
tx10 loptr,choptr, r724(1k2).
tx10 memory d345 ,b341.c367(560pf).
tx10 middle line twinning, c776(100nf),c783(240pf).
tx10 mk2 field collapse tda3652( or tda3654 with 6k8 across r771)
tx10 no blue text . color decoder ic tda3560.
tx10 no brill d702 byx55-600 not by228.
tx10 no line op ic621.
tx10 no line sync ic741(tda2576a),ic1003(saa5030),r601(1k5).
tx10 no manual ctrl ,remote ok,tr258.
tx10 no pic d657 tr654/tr655.tr656
tx10 no pic d702
tx10 no pic l831,d702,c759,d738,d735,c758(33uf).
tx10 no pic no line d702(byw95c).
tx10 no pic snd ok, heater feed , pcb cracks
tx10 no pic snd ok. c759,d738, d735,c758(33uf)
tx10 no red no red text tda3560 .
tx10 no remote start tr410 bc237b) .
tx10 no signal/snd mute c22(330pf).
tx10 no snd. r243 r1243(4r7) .
tx10 no text sync saa5020.
tx10 no text.r1131(47k) ic1033(saa5030) due to focus control flash over.
tx10 norm snd alters,d101.
tx10 odd tuning controls sl430 chip ic105 on the remote control panel
tx10 only mixed text,pl31,has an extra grey flying . disconnect pin x
tx10 pc1500/1550 warm trip,d831 by188b.
tx10 pc1560 warm trips,r813 121k,bc547 tr801 12vreg zener d802
tx10 pic blanked across, c726(22uf).
tx10 pic fades , crt heater pins, loptx pins.
tx10 poor line sync c742(220uf), c745(100uf) c749 (4n7) tr345(bc237)
tx10 poor pic, lo a1’s, crt socket fault
tx10 poor sync. ic tda2576a.
tx10 poor video pbtr113 (bc237),d117 .
tx10 ramdom remote pl16/1.
tx10 random tripping r810(150k).
tx10 raster white c655(470uf) .
tx10 remote lo ,leds,d1,d2,d3.
tx10 remote no snd,no text, s402 switch stuck.
tx10 rolling hot r773(330k).
tx10 rolling hot. r773 330k
tx10 rolling tda2576a
tx10 side jitter on video pb tr113(bc237),d117,tr345(bc237).
tx10 slow snd,ic561(tda1236).
tx10 sound buzz ic621 (lm340t) l531,pl9.
tx10 sound buzz stereo- resolder/check panel earths.
tx10 sound crackling with volume turned down ic621 (lm340t) 12v reg.
tx10 sound distorted- replace c570 (100n) & c571(100n) .
tx10 sound lhs buzz – replace c1450 (10uf).
tx10 sound lo ic561 (tda1236) , c582 (6n8)
tx10 sound mute , c22 (330pf)
tx10 sound poor,c536(6n8),c544(22n), 12v reg ic621.
tx10 snow no signal ,c22(330pf)
tx10 snow, sl1430
tx10 spot burn- r834(1m8).
tx10 stby c137(470nf) c406(c106)
tx10 stby only remote tr410(bc237).
tx10 stby releases delete c406 or c106.
tx10 stby remote, tr410(bc236b).
tx10 stby. r724(1k2)
tx10 stereo whistle c103.
tx10 striations rhs c727(470uf).
tx10 sweep tuning ic344 (mc1449-9pb)
tx10 sweep tuning not stopping led flashes ic344 mc1449-9pb
tx10 sync poor ic33 (saa5030) ic1033
tx10 t/text mixed ok but no full text ensure pl31 grey lead is off .
tx10 text lines , scan coil shorts,tr771(ztx450k).
tx10 picture top cramping -c781 (100uf) & c773(100uf).
tx10 tripping focus pot,tr831(bu508a),ic771,t721(loptx),d831.
tx10 tripping t721.
tx10 trips on hi brill, c655(470uf)leaky.
tx10 trips tda3652( or tda3654 with 6k8 across r771)
tx10 trips tr831 (bu208a), r613(10) d801 (6.2v zenor) , r810 (150k) .
tx10 tuner drift, varicap tuner unit.
tx10 tuner sweeping at switch on, d356(itt44).
tx10 tuning drift on loud snd. il01 (lm341) 12v reg.
tx10 vertical lines wavy,int rolls r813(121k).
tx10 vol/color varies, loptx pin 1.
tx10 warm narrows/trips. d831(by226) d743
tx10 warm tripping d831(by188b),fb721,d702 leaky,r810(150k),r813(121k).
tx10 weak line sync c749(4n7f).
tx10 whistle d743 beads, glue on.
tx10 white spots, loud screeching ,hairline crack from earth point on the crt. base pcb
tx10 wide black line across pic,tda2576a
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