The PHILIPS CHASSIS TVC11 is an amazing and awesome engineering example.
The chassis is a complex and a big combination of multi boards with many discretes and ASIC's.
On the left side the small signal boards with all IF / Video / luminance / chrominance / remote controls.
On the right side all large signal boards with synchronized power supply and line deflection and EHT and frame deflection and synchronization unit.
Left side in the cabinet upside the audio stages and power amplifier.
On bottom of the aforementioned the tuning drawbar.
The chassis is capable of multistandard and multi sound with stereo and spatial stereo feature.
ICS USED:
TDA1038
TCA660B Contrast/Saturation and Brightness Control Circuit
TDA2541 IF VIDEO
LM324 AMP OP
TDA1026 SYNCHRO
TDA2581 SUPPLY
TBA120T SOUND IF
TCA640 Chrominance Amplifier for SECAM or PAL/SECAM Decoders
TCA650 Chrominance Demodulator for Secam or PAL/Secam Decoders
TCA740 D.c. Treble Amd Bass Stereo Control Circuit (1980)
TCA730 15V 35mA D.C. volume and balance stereo control circuit
Dual-standard (PAL/SECAM) color TV receiver includes circuitry for automatically controlling the receiver's operating mode in accordance with recognition of the SECAM or PAL format of the received signals. A first sample-and-hold circuit monitors the output of an FM detector responsive to the received signals during blanking "backporch" portions of alternate line intervals, while a second sample-and-hold circuit monitors the output of said FM detector during blanking "backporch" portions of the intervening line intervals. Comparison of the outputs of the two sample-and-hold circuits achieves the desired format recognition. To avoid false recognition, sampling interval beginning is delayed relative to beginning of SECAM lead-in oscillations or PAL swinging bursts, while sampling interval termination substantially coincides with end of blanking interval.
In the SECAM color television system, R-Y and B-Y color-difference signals frequency modulate respective subcarriers (with respective resting frequencies of 4.40625 MHz. and 4.250 MHz.) which are provided alternately on a line-by-line basis in the active line intervals of the transmitted SECAM signal. An economical approach to processing such signals in a SECAM receiver, which is also attractive for use in dual-standard (SECAM/PAL) receivers, is to convert the SECAM signal into a signal similar to a PAL signal (i.e., a "quasi-PAL" signal) for further processing by standard PAL signal decoding techniques. The system for effecting such conversion is desirably of the general type described in U.K. Pat. No. 1,358,551, wherein the respective SECAM subcarriers are demodulated sequentially by a single FM detector, and the resultant color-difference signals amplitude modulate in appropriate sequence respective phases of a subcarrier derived from the PAL crystal oscillator of the PAL decoder apparatus. U.S. Pat. No. 4,232,268, for example, discloses an arrangement for line-by-line switching of the center frequency tuning of an FM detector which readily permits the aforementioned sequential demodulation of the respective SECAM subcarriers by a single FM detector.
In such use of a single FM detector for sequential demodulation of the respective SECAM subcarriers, an identification system is required for identification and correction of an incorrect mode of line-by-line switching of the detector's center frequency tuning. One source of information for such identification purposes is found in the lead-in bursts of oscillations which precede the image portion of each active line interval (with a lead-in burst at the R-Y resting frequency preceding the image portion of an active line interval that conveys R-Y image information, and with a lead-in burst at the B-Y resting frequency preceding the image portion of an active line interval that conveys B-Y image information).
In the identification system disclosed in U.S. Pat. No. 4,240,102-Groeneweg, a flip-flop develops half line rate control waves for use in switching the center frequency tuning of the detector employed for demodulating received SECAM signals. When the phasing of the flip-flop output is correct, the detector is provided with center frequency tuning (4.40625 MHz.) appropriate to demodulation of the R-Y modulated subcarrier during the image portion of an R-Y line interval of the SECAM signal, and tuning (4.250 MHz.) appropriate for demodulation of the B-Y modulated subcarrier during the image portion of a B-Y line interval of the SECAM signal. Through the supplemental association of line rate pulses in the tuning control, however, the timing of the changes in detector center frequency tuning is so controlled that during the lead-in bursts preceding the image portions of both of such R-Y and B-Y line intervals, the detector center frequency tuning is always the same (e.g., tuned for a center frequency corresponding to the R-Y subcarrier resting frequency).
In the identification system of the aforesaid Groeneweg patent, the output of a detector subject to center frequency tuning control of the above-described type is applied to a pair of sample-and -hold circuits. Using respective half line rate control waves of mutually opposite phase derived from the flip-flop, and common, line rate, burst interval gating pulses, for control of the sampling times of the respective sample-and-hold circuits, one sample-and-hold circuit effects sampling of the filtered detector output during the lead-in burst occurrence of alternate line intervals, while the other sample-and-hold circuit effects a sampling of the filtered detector output during the lead-in burst occurrence of the intervening line intervals. Comparison of the outputs of the two sample-and-hold circuits in a voltage comparator yields an output indicative of the correctness or incorrectness of the phasing of the flip-flop circuit. When the output is indicative of incorrect flip-flop phasing, the flip-flop is shut down, and then allowed to restart, whereupon a new comparison is effected, with such a process repeated until correct flip-flop phasing is achieved.
As disclosed in the aforesaid Groeneweg patent for instances of use of the above-described identification system in a dual-standard SECAM/PAL color TV receiver, information suitable for automatically controlling the operating mode of the dual-standard receiver can also be derived by comparison of the outputs of the respective sample-and-hold circuits. When SECAM signals are being received under conditions of correct phasing for the flip-flop, there will be a significant difference of a predetermined sense between the outputs of the respective sample-and-hold circuits. In the arrangement of the aforesaid Groeneweg patent, the receiver is switched into a SECAM operating mode (with the quasi-PAL output of the SECAM-PAL transcoder fed to the receiver's PAL decoder apparatus) only when such a relationship between the sample-and-hold circuit outputs is obtained. In all other instances (i.e., when the outputs are substantially equal, or when a difference of the opposite sense is obtained), the receiver is maintained in a PAL operating mode (with the PAL decoder receiving its input from a signal path bypassing the SECAM-PAL transcoder).
Since the frequency of the PAL burst remains the same in successive line intervals, one would expect the outputs of two sample-and-hold circuits to be the same during reception of a PAL signal, whereby false switching to a SECAM operating mode could not occur during such signal reception. The present invention is based, however, on a recognition that certain transient conditions can exist in the operation of the FM detector during PAL signal reception that may lead to false switching to a SECAM operating mode in the above-described mode control arrangement, unless a proper choice is made of the sampling interval location within the "backporch" region of the horizontal blanking period.
During PAL signal reception, the trailing edge of each horizontal sync pulse initiates a ringing of the "cloche" bandpass filter that precedes the limiter and FM detector. While the ringing amplitude is small, the high gain of the limiter elevates the ringing component input to the FM detector to a significant level. When the succeeding PAL burst signal arrives, the input to the FM detector undergoes a phase jump of a nature dependent upon the phase relationship between the burst signal and the sync induced oscillation upon which it is superimposed. Unfortunately, the PAL burst, while the same in frequency in successive line intervals, is phase shifted by 90° from line to line. As a consequence, during an initial settling period (e.g., about one microsecond) following the burst beginning, the FM detector output exhibits a transient of one nature during odd line intervals and of a different nature during even line intervals, with the amplitude, direction and shape of the transient dependent upon the aforementioned phase relationship. Because of the noted difference in such transients, it becomes important to minimize sampling of such transients by the sample-and-hold circuits (at least during the periods in which they exhibit significant differences), if false switching to a SECAM operating mode is to be precluded.
Pursuant to the principles of the present invention, the initiation of the sampling intervals for the sample-and-hold circuits of the above-described arrangement is desirably delayed relative to the beginning of burst appearance so that the periods of significant transient difference are excluded from the sampling intervals. In order that the initiation delay does not shorten the sampling interval to a degree compromising reliability of level detection for SECAM identification purposes, it is further recognized as desirable that the sampling interval should extend for the remainder of the period occupied by lead-in oscillations during SECAM signal reception, wherefore the termination of the sampling interval is desirably in substantial coincidence with the end of the horizontal blanking interval.
In a desirable form of implementation of a SECAM-PAL transcoder incorporating an identification system pursuant to the principles of the present invention, major elements of the transcoder are realized in integrated circuit (IC) form on a common substrate. In such IC realization, a useful input to a terminal of the IC chip is a "sandcastle" pulse train. A conventional "sandcastle" pulse form, provided by many currently available horizontal processor IC's (e.g., Philips TDA 2593), is a two level pulse in which a burst gating pulse is superimposed upon a horizontal blanking pulse. Typical timing for the burst gating pulse locates it in the "backporch" region of the horizontal blanking pulse (i.e., subsequent to the horizontal sync interval), with the leading edge occurring slightly before the beginning of the interval occupied by standard PAL bursts (and the similarly timed beginning of the interval occupied by SECAM lead-in oscillations), and with the trailing edge occurring subsequent to the end of the PAL burst interval but prior to the end of the horizontal blanking interval (and thus prior to the end of the SECAM lead-in interval).
In accordance with an illustrative embodiment of the present invention, the development of a suitable line rate sampling control pulse for the above-described identification and mode control system is achieved by circuitry responding to the respective components of a sandcastle pulse of the aforementioned type.
After separation of the horizontal blanking and burst gating components of the sandcastle pulse by conventional amplitude-sensitive sandcastle decoding techniques, circuitry responsive to the separated components develops a pulse having a leading edge coinciding with the leading edge of the burst gating component and a trailing edge coinciding with the trailing edge of the horizontal blanking component. The developed pulse is supplied to delay means which slows the rise of the leading edge. A threshold device responsive to the output of the delay means provides as its output the desired sampling control pulse, with its leading edge delayed (e.g., for about one microsecond) relative to the beginning of a burst interval, and with its trailing edge substantially coinciding with the end of the horizontal blanking interval. Use of such sampling control pulses in conjunction with respective flip-flop output waves to control the respective sample-and-hold circuits in an identification system of the previously described type, enables provision of an operating mode control free of the aforementioned false switching problem during PAL signal reception. The identification system additionally functions reliably to establish correct flip-flop phasing conditions during SECAM signal reception.
PHILIPS 26P1195 MULTISTANDARD Receiver tuning circuit PHILIPS CHASSIS TVC11
A receiver tuning circuit in which without operation of extra switches a change-over can be made from tuning by means of a continuously varying tuning voltage to tuning by means of one of a number of adjusted tuning voltages by using a capacitor controlled by an automatic tuning correction current source circuit for obtaining said voltage, and an automatic switch for applying the desired tuning voltages to this capacitor.
2. A receiver tuning circuit as claimed in claim 1, wherein said switch comprises a current source which can be influenced by an operating signal, said source being coupled to two parallel branches the first of which includes a transistor having an emitter coupled to said current source, a base coupled to an input of the switch, and a collector, a current mirror circuit having an input coupled to said collector and an output, the second branch including a pair of series connected diodes coupled to the current source and to said output of the current mirror circuit, and output of the switch being coupled to the pair of diodes.
3. A circuit as claimed in claim 1, further comprising a manually operable second switch means for obtaining a continuous coupling between said potentiometer means and said capacitor.
4. A circuit as claimed in claim 1 further comprising a supply circuit means for obtaining a desired tuning voltage, said memory means being independent of said supply circuit, said first switch further comprising a second time constant circuit means coupled to said supply circuit means for temporarily applying a tuning voltage determined by the potentiometer to said capacitor when the supply voltage is switched on.
5. A receiver tuning circuit comprising a tuning section having a tuning input, a capacitor means coupled to said tuning input for applying a tuning voltage thereto, a controllable current source coupled to said capacitor, a tuning correction signal detector means coupled between said tuning section and said current source for applying an automatic tuning correction signal to said capacitor through said current source, means coupled to said capacitor for immediately tuning said tuning section to a selected frequency independently of the previous voltage on said capacitor, a memory means coupled to said immediate tuning means for storing a tuning voltage corresponding to a selected frequency and signal amplitude detector means coupled to said immediate tuning means for effecting that said tuning voltage stored in said memory means is applied to said capacitor through said immediate tuning means when said signal amplitude goes below a selected value.
PHILIPS 26P1195 MULTISTANDARD CHASSIS TVC11 Line synch Switched Mode Power Supply with Line deflection output Transistor Drive Circuit:
A stabilized supply voltage circuit for a picture display device comprising a chopper wherein the switching signal has the line frequency and is duration-modulated. The coil of the chopper constitutes the primary winding of a transformer a secondary winding of which drives the line output transistor so that the switching transistor of the chopper also functions as a driver for the line output stage. The oscillator generating the switching signal may be the line oscillator. In a special embodiment the driver and line output transistor conduct simultaneously and in order to limit the base current of the line output transistor a coil shunted by a diode is incorporated in the drive line of the line output transistor. Other secondary windings of the transformer drive diodes which conduct simultaneously with the efficiency diode of the chopper so as to generate further stabilized supply voltages.
The invention relates to a circuit arrangement in a picture display device wherein the input direct voltage between two input terminals, which is obtained be rectifying the mains alternating voltage, is converted into a stabilized output direct voltage by means of a switching transistor and a coil and wherein the transistor is connected to a first input terminal and an efficiency diode is connected to the junction of the transistor and the coil. The switching transistor is driven by a pulsatory voltage of line frequency which pulses are duration-modulated in order to saturate the switching transistor during part of the period dependent on the direct voltage to be stabilized and to cut off this transistor during the remaining part of the period. The pulse duration modulation is effected by means of a comparison circuit which compares the direct voltage to be stabilized with a substantially constant voltage, the coil constituting the primary winding of a transformer.
Such a circuit arrangement is known from German "Auslegeschrift" 1.293.304. wherein a circuit arrangement is described which has for its object to convert an input direct voltage which is generated between two terminals into a different direct voltage. The circuit employs a switch connected to the first terminal of the input voltage and periodically opens and closes so that the input voltage is converted into a pulsatory voltage. This pulsatory voltage is then applied to a coil. A diode is arranged between the junction of the switch and the coil and the second terminal of the input voltage whilst a load and a charge capacitor in parallel thereto are arranged between the other end of the coil and the second terminal of the input voltage. The assembly operates in accordance with the known efficiency principle i.e., the current supplied to the load flows alternately through the switch and through the diode. The function of the switch is performed by a switching transistor which is driven by a periodical pulsatory voltage which saturates this transistor for a given part of the period. Such a configuration is known under different names in the literature; it will be referred to herein as a "chopper." A known advantage thereof, is that the switching transistor must be able to stand a high voltage or provide a great current but it need not dissipate a great power.
The output voltage of the chopper is compared with a constant reference voltage. If the output voltage attempts to vary because the input voltage and/or the load varies, a voltage causing a duration modulation of the pulses is produced at the output of the comparison arrangement. As a result the quantity of the energy stored in the coil varies and the output voltage is maintained constant. In the German "Auslegeschrift" referred to it is therefore an object to provide a stabilized supply voltage device.
In the circuit arrangement according to the mentioned German "Auslegeschrift" the frequency of the load variations or a harmonic thereof is chosen as the frequency for the switching voltage. Particularly when the load fed by the chopper is the line deflection circuit of a picture display device, wherein thus the impedance of the load varies in the rhythm of the line frequency, the frequency of the switching voltage is equal to or is a multiple of the line frequency.
It is to be noted that the chopper need not necessarily be formed as that in the mentioned German "Auslegeschrift." In fact, it is known from literature that the efficiency diode and the coil may be exchanged. It is alternatively possible for the coil to be provided at the first terminal of the input voltage whilst the switching transistor is arranged between the other end and the second terminal of the input voltage. The efficiency diode is then provided between the junction of said end and the switching transistor and the load. It may be recognized that for all these modifications a voltage is present across the connections of the coil which voltage has the same frequency and the same shape as the pulsatory switching voltage. The control voltage of a line deflection circuit is a pulsatory voltage which causes the line output transistor to be saturates and cut off alternately. The invention is based on the recognition that the voltage present across the connections of the coil is suitable to function as such a control voltage and that the coil constitutes the primary of a transformer. To this end the circuit arrangement according to the invention is characterized in that a secondary winding of the transformer drives the switching element which applies a line deflection current to line deflection coils and by which the voltage for the final anode of a picture display tube which forms part of the picture display device is generated, and that the ratio between the period during which the switching transistor is saturated and the entire period, i.e., the switching transistor duty cycle is between 0.3 and 0.7 during normal operation.
The invention is also based on the recognition that the duration modulation which is necessary to stabilize the supply voltage with the switching transistor does not exert influence on the driving of the line output transistor. This resides in the fact that in case of a longer or shorter cut-off period of the line output transistor the current flowing through the line deflection coils thereof is not influenced because of the efficiency diode current and transistor current are taken over or, in case of a special kind of transistor, the collector-emitter current is taken over by the base collector current and conversely. However, in that case the above-mentioned ratios of 0.3 : 0.7 should be taken into account since otherwise this take-over principle is jeopardized.
As will be further explained the use of the switching transistor as a driver for the line output transistor in an embodiment to be especially described hereinafter has the further advantage that the line output transistor automatically becomes non-conductive when this switching transistor is short circuited so that the deflection and the EHT for the display tube drop out and thus avoid damage thereof.
Due to the step according to the invention the switching transistor in the stabilized supply functions as a driver for the line deflection circuit. The circuit arrangement according to the invention may in addition be equipped with a very efficient safety circuit so that the reliability is considerably enhanced, which is described in the U.S. Pat. No. 3,629,686. The invention is furthermore based on the recognition of the fact that the pulsatory voltage present across the connections of the coil is furthermore used and to this end the circuit arrangement according to the invention is characterized in that secondary windings of the transformer drive diodes which conduct simultaneously with the efficiency diode so as to generate further stabilized direct voltages, one end of said diodes being connected to ground.
In order that the invention may be readily carried into effect, a few embodiments thereof will now be described in detail by way of example with reference to the accompanying diagrammatic drawings in which:
FIG. 1 shows a principle circuit diagram wherein the chopper and the line deflection circuit are further shown but other circuits are not further shown.
FIGS. 2a, 2b and 2c show the variation as a function of time of two currents and of a voltage occurring in the circuit arrangement according to FIG. 1.
FIGS. 3a 3b, 3c and 3d show other embodiments of the chopper.
FIGS. 4a and 4b show modifications of part of the circuit arrangement of FIG. 1.
In FIG. 1 the reference numeral 1 denotes a rectifier circuit which converts the mains voltage supplied thereto into a non-stabilized direct voltage. The collector of a switching transistor 2 is connected to one of the two terminals between which this direct voltage is obtained, said transistor being of the npn-type in this embodiment and the base of which receives a pulsatory voltage which originates through a control stage 4 from a modulator 5 and causes transistor 2 to be saturated and cut off alternately. The voltage waveform 3 is produced at the emitter of transistor 2. In order to maintain the output voltage of the circuit arrangement constant, the duration of the pulses provided is varied in modulator 5. A pulse oscillator 6 supplies the pulsatory voltage to modulator 5 and is synchronized by a signal of line frequency which originates from the line oscillator 6' present in the picture display device. This line oscillator 6' is in turn directly synchronized in known manner by pulses 7' of line frequency which are present in the device and originate for example from a received television signal if the picture display device is a television receiver. Pulse oscillator 6 thus generates a pulsatory voltage the repetition frequency of which is the line frequency.
The emitter of switching transistor 2 is connected at one end to the cathode of an efficiency diode 7 whose other end is connected to the second input voltage terminal and at the other end to primary winding 8 of a transformer 9. Pulsatory voltage 3 which is produced at the cathode of efficiency diode 7 is clamped against the potential of said second terminal during the intervals when this diode conducts. During the other intervals the pulsatory voltage 3 assumes the value V i . A charge capacitor 10 and a load 11 are arranged between the other end of winding 8 and the second input voltage terminal. The elements 2,7,8,10 and 11 constitute a so-called chopper producing a direct voltage across charge capacitor 10, provided that capacitor 10 has a sufficiently great value for the line frequency and the current applied to load 11 flowing alternately through switching transistor 2 or through efficiency diode 7. The output voltage V o which is the direct voltage produced across charge capacitor 10 is applied to a comparison circuit 12 which compares the voltage V o with a reference voltage. Comparison circuit 12 generates a direct voltage which is applied to modulator 5 so that the duration of the effective period δ T of switching transistor 2 relative to the period T of pulses 3 varies as a function of the variations of output voltage V 0 . In fact, it is readily evident that output voltage V o is proportional to the ratio δ :
V o = V i . δ
Load 11 of the chopper consists in the consumption of parts of the picture display device which are fed by output voltage V 0 . In a practical embodiment of the circuit arrangement according to FIG. 1 wherein the mains alternating voltage has a nominal effective value of 220 V and the rectified voltage V i is approximately 270 V, output voltage V o for δ = 0.5 is approximately 135 V. This makes it also possible, for example, to feed a line deflection circuit as is shown in FIG. 1 wherein load 11 then represents different parts which are fed by the chopper. Since voltage V o is maintained constant due to pulse duration modulation, the supply voltage of this line deflection circuit remains constant with the favorable result that the line amplitude(= the width of the picture displayed on the screen of the picture display tube) likewise remains constant as well as the EHT required for the final anode of the picture display tube in the same circuit arrangement independent of the variations in the mains voltage and the load on the EHT generator (= variations in brightness).
However, variations in the line amplitude and the EHT may occur as a result of an insufficiently small internal impedance of the EHT generator. Compensation means are known for this purpose. A possibility within the scope of the present invention is to use comparison circuit 12 for this purpose. In fact, if the beam current passes through an element having a substantially quadratic characteristic, for example, a voltage-dependent resistor, then a variation for voltage V o may be obtained through comparison circuit 12 which variation is proportional to the root of the variation in the EHT which is a known condition for the line amplitude to remain constant.
In addition this facilitates smoothing of voltage V o since the repetition frequency of pulsatory voltage 3 is many times higher than that of the mains and a comparatively small value may be sufficient for charge capacitor 10. If charge capacitor 10 has a sufficiently high value for the line frequency, voltage V o is indeed a direct voltage so that a voltage having the same form as pulsatory voltage 3 is produced across the terminals of primary winding 8. Thus voltages which have the same shape as pulsatory voltage 3 but have a greater or smaller amplitude are produced across secondary windings 13, 14 of transformer 9 (FIG. 1 shows only 2 secondary windings but there may be more). The invention is based on the recognition that one end of each secondary winding is connected to earth while the other end thereof drives a diode, the winding sense of each winding and the direction of conductance of each diode being chosen to be such that these diodes conduct during the same period as does efficiency diode 7. After smoothing, stabilized supply voltages, for example, at terminal 15 are generated in this manner at the amplitudes and polarities required for the circuit arrangements pre
sent in the picture display device. In FIG. 1 the voltage generated at terminal 15 is, for example, positive relative to earth. It is to be noted that the load currents of the supply voltages obtained in this manner cause a reduction of the switching power which is economized by efficiency diode 7. The sum of all diode currents including that of diode 7 is in fact equal to the current which would flow through diode 7 if no secondary winding were wound on transformer 9 and if no simultaneous diode were used. This reduction may be considered an additional advantage of the circuit arrangement according to the invention, for a diode suitable for smaller powers may then be used. However, it will be evident that the overall secondary load must not exceed the primary load since otherwise there is the risk of efficiency diode 7 being blocked so that stabilization of the secondary supply voltages would be out of the question.
It is to be noted that a parabola voltage of line frequency as shown at 28 is produced across the charge capacitor 10 if this capacitor is given a smaller capacitance so that consequently the so-called S-correction is established.
In FIG. 1 charge capacitors are arranged between terminals 15 etc. and earth so as to ensure that the voltages on these points are stabilized direct voltages. If in addition the mean value of the voltage on one of these terminals has been made equal to the effective value of the alternating voltage which is required for heating the filament of the picture display tube present in the picture display device, this voltage is suitable for this heating. This is a further advantage of the invention since the cheap generation of a stabilized filament voltage for the picture display tube has always been a difficult problem in transistorized arrangements.
A further advantage of the picture display device according to the invention is that transformer 9 can function as a separation transformer so that the different secondary windings can be separated from the mains and their lower ends can be connected to ground of the picture display device. The latter step makes it possible to connect a different apparatus such as, for example, a magnetic recording and/or playback apparatus to the picture display device without earth connection problems occurring.
In FIG. 1 the reference numeral 14 denotes a secondary winding of transformer 9 which in accordance with the previously mentioned recognition of the invention can drive line output transistor 16 of the line deflection circuit 17. Line deflection circuit 17 which is shown in a simplified form in FIG. 1 includes inter alia line deflection coils 18 and an EHT transformer 19 a secondary winding 20 of which serves for generating the EHT required for the acceleration anode of the picture display tube. Line deflection circuit 17 is fed by the output voltage V o of the chopper which voltage is stabilized due to the pulse duration modulation with all previously mentioned advantages. Line deflection circuit 17 corresponds, for example, to similar arrangements which have been described in U.S. Pat. No. 3,504,224 issued Mar. 31, 1970 to J.J. Reichgelt et al., U.S. patent application Ser. No. 737,009 filed June 14, 1968 by W. H. Hetterscheid and U.S. application Ser. No. 26,497 filed April 8, 1970 by W. Hetterscheid et al. It will be evident that differently formed lined deflection circuits are alternatively possible.
It will now be shown that secondary winding 14 can indeed drive a line deflection circuit so that switching transistor 2 can function as a driver for the line deflection. FIGS. 2a and b show the variation as a function of time of the current i C which flows in the collector of transistor 16 and of the drive voltage v 14 across the terminals of secondary winding 14. During the flyback period (0, t 1 ) transistor 16 must be fully cut off because a high voltage peak is then produced at its collector; voltage v 14 must then be absolutely negative. During the scan period (t 1 , t 4 ) a sawtooth current i C flows through the collector electrode of transistor 16 which current is first negative and then changes its direction. As the circuit arrangement is not free from loss, the instant t 3 when current i C becomes zero lies, as is known, before the middle of the scan period. At the end t 4 of the scan period transistor 16 must be switched off again. However, since transistor 16 is saturated during the scan period and since this transistor must be suitable for high voltages and great powers so that its collector layer is thick, this transistor has a very great excess of charge carriers in both its base and collector layers. The removal of these charge carriers takes a period t s which is not negligible whereafter the transistor is indeed switched off. Thus the fraction δ T of the line period T at which v 14 is positive must end at the latest at the instant (t 4 - t s ) located after the commencement (t = 0) of the previous flyback.
The time δ T may be initiated at any instant t 2 which is located between the end t 1 of the flyback period and the instant t 3 when collector current i C reverses its direction. It is true that emitter current flows through transistor 16 at the instant t 2 , but collector current i C is not influenced thereby, at least not when the supply voltage (= V o ) for line deflection circuit 17 is high enough. All this has been described in the U.S. Pat. No. 3,504,224. The same applies to line deflection circuits wherein the collector base diode does not function as an efficiency diode as is the case in the described circuit 17, but wherein an efficiency diode is arranged between collector and emitter of the line output transistor. In such a case the negative part of the current i C of FIG. 2a represents the current flowing through the said efficiency diode.
After the instant t 3 voltage v 14 must be positive. In other words, the minimum duration of the period T when voltage v 14 must be positive is (t 4 - t s ) - t 3 whilst the maximum duration thereof is (t 4 - t s ) - t 1 . In a television system employing 625 lines per raster the line period t 4 is approximately 64 μus and the flyback period is approximately 12 μus. Without losses in the circuit arrangement instant t 3 would be located approximately 26 μus after the instant t 1 , and with losses a reasonable value is 22 μus which is 34 μus after the commencement of the period. If for safety's sake it is assumed that t s lasts approximately 10 μus, the extreme values of δ T are approximately 20 and 42 μus and consequently the values for δ are approximately 0.31 and 0.66 at a mean value which is equal to approximately 0.49. It was previously stated that a mean value of δ = 0.5 was suitable. Line deflection circuit 17 can therefore indeed be used in combination with the chopper in the manner described, and the relative variation of δ may be (0.66 - 0.31) : 0.49 = 71.5 percent. This is more than necessary to obviate the variations in the mains voltage or in the various loads and to establish the East-West modulation and ripple compensation to be described hereinafter. In fact, if it is assumed that the mains voltage varies between -15 and +10 percent of the nominal value of 220 V, while the 50 Hz ripple voltage which is superimposed on the input voltage V i has a peak-to-peak value of 40 V and V i is nominally 270 V, then the lowest occurring V i is:
0.85 × 270 V - 20 V = 210 V and the highest occurring V i is
1.1 × 270 V + 20 V = 320 V. For an output voltage V o of 135 V the ratio must thus vary between
δ = 135 : 210 = 0.64 and δ = 135 : 320 = 0.42.
A considerable problem presenting itself is that of the simultaneous or non-simultaneous drive of line output transistor 16 with switching transistor 2, it being understood that in case of simultaneous drive both transistors are simultaneously bottomed, that is during the period δ T. This depends on the winding sense of secondary winding 14 relative to that of primary winding 8. In FIG. 1 it has been assumed that the drive takes place simultaneously so that the voltage present across winding 14 has the shape shown in FIG. 2b. This voltage assumes the value n(V i - V o ) in the period δ T and the value -nVo in the period (1 - δ )T, wherein n is the ratio of the number of turns on windings 14 and 8 and wherein V o is maintained constant at nominal mains voltage V o = δ V inom . However, if as a result of an increase or a decrease of the mains voltage V i increases or decreases proportionally therewith, i.e., V i = V i nom + Δ V, the positive portion of V 14 becomes equal to n(V i nom - V o +Δ V) = n [(1 -δ)V i nom +ΔV] = n(0.5 V inom +ΔV) if δ = 0.5 for V i = V i nom. Relatively, this is a variation which is twice as great. For example, if V i nom = 270 V and V o = 135 V, a variation in the mains voltage of from -15 to +10 percent causes a variation of V i of from -40.5 V to +27 V which ranges from -30 to +20 percent of 135 V which is present across winding 8 during the period δ T. The result is that transistor 16 can always be bottomed over a large range of variation. If the signal of FIG. 2b would be applied through a resistor to the base of transistor 16, the base current thereof would have to undergo the same variation while the transistor would already be saturated in case of too low a voltage. In this case it is assumed that transformer 9 is ideal (without loss) and that coil 21 has a small inductance as is explained in the U.S. patent application Ser. No. 737,009 above mentioned. It is therefore found to be desirable to limit the base current of transistor 16.
This may be effected by providing a coil 22 having a large value inductance, approximately 100 μH, between winding 14 and the small coil 21. The variation of said base current i b is shown in FIG. 2c but not to the same scale as the collector current of FIG. 2a. During the conducting interval δ T current i b varies as a linear function of time having a final value of wherein L represents the inductance of coil 22. This not only provides the advantage that this final value is not immediately reached, but it can be shown that variation of this final value as a function of the mains voltage has been reduced, for there applies at nominal mains voltage that: If the mains voltage V i = V i nom +Δ V, then ##SPC1## because V i nom = 2 V o . Thus this variation is equal to that of the mains voltage and is not twice as great.
During switching off, t 2 , of transistor 16 coil 22 must exert no influence and coil 21 must exert influence which is achieved by arranging a diode 23 parallel to coil 22. Furthermore the control circuit of transistor 16 in this example comprises the two diodes 24 and 25 as described in U.S. application Ser. No. 26,497 above referred to, wherein one of these diodes, diode 25 in FIG. 1, must be shunted by a resistor.
The control circuit of transistor 16 may alternatively be formed as is shown in FIG. 4. In fact, it is known that coil 21 may be replaced by the parallel arrangement of a diode 21' and a resistor 21" by which the inverse current can be limited. To separate the path of the inverse current from that of the forward current the parallel arrangement of a the diode 29' and a resistor 29" must then be present. This leads to the circuit arrangement shown in the upper part of FIG. 4. This circuit arrangement may now be simplified if it is noted that diodes 25 and 21' on the one hand and diodes 23 and 29' on the other hand are series-arranged. The result is shown in the lower part of FIG. 4 which, as compared with the circuit arrangement of FIG. 1, employs one coil less and an additional resistor.
FIG. 3 shows possible modifications of the chopper. FIG. 3a shown in a simplified form the circuit arrangement according to FIG. 1 wherein the pulsatory voltage present across the connections of windings 8 has a peak-to-peak amplitude of V i - V o = 0.5 V i for δ = 0.5, As has been stated, the provision of coil 22 gives a relative variation for the base current of transistor 16 which is equal to that of the mains voltage. In the cases according to FIG. 3b, 3c and 3d the peak-to-peak amplitude of the voltage across winding 8 is equal to V i so that the provision of coil 22 results in a relative variation which is equal to half that of the mains voltage which is still more favorable than in the first case.
Transistors of the npn type are used in FIG. 3. If transistors of the pnp type are used, the relevant efficiency diodes must of course be reversed.
In this connection it is to be noted that it is possible to obtain an output voltage V o with the aid of the modifications according to FIGS. 3b, c and d, which voltage is higher than input voltage V i . These modifications may be used in countries such as, for example, the United of America or France where the nominal mains voltage is 117 or 110 V without having to modify the rest of the circuit arrangement.
The above-mentioned remark regarding the sum of the diode currents only applies, however, for the modifications shown in FIGS. 3a and d.
If line output transistor 16 is not simultaneously driven with switching transistor 2, efficiency diodes 7 conducts simultaneously with transistor 16 i.e., during the period which is denoted by δ T in FIGS. 1 and 2b. During that period the output voltage V o of the chopper is stabilized so that the base current of transistor 16 is stabilized without further difficulty.
However, a considerable drawback occurs. In FIG. 1 the reference numeral 26 denotes a safety circuit the purpose of which is to safeguard switching transistor 2 when the current supplied to load 11 and/or line deflection circuit 17 becomes to high, which happens because the chopper stops. After a given period output voltage V o is built up again, but gradually which means that the ratio δ is initially small in the order of 0.1. All this is described in U.S. patent No. 3,629,686. The same phenomenon occurs when the display device is switched on. Since δ = 0.1 corresponds to approximately 6 μs when T = 64 μs, efficiency diode 7 conducts in that case for 64 - 6 = 58 μus so that transistor 16 is already switched on at the end of the scan or at a slightly greater ratio δ during the flyback. This would cause an inadmissibly high dissipation. For this reason the simultaneous drive is therefore to be preferred.
The line deflection circuit itself is also safeguarded: in fact, if something goes wrong in the supply, the driver voltage of the line deflection circuit drops out because the switching voltage across the terminals of primary winding 8 is no longer present so that the deflection stops. This particularly happens when switching transistor 2 starts to constitute a short-circuit between emitter and collector with the result that the supply voltage V o for the line deflection circuit in the case of FIG. 1 becomes higher, namely equal to V i . However, the line output transformer is now cut off and is therefore also safe as well as the picture display tube and other parts of the display device which are fed by terminal 15 or the like. However, this only applies to the circuit arrangement according to FIG. 1 or 3a.
Pulse oscillator 6 applies pulses of line frequency to modulator 5. It may be advantageous to have two line frequency generators as already described, to wit pulse oscillator 6 and line oscillator 6' which is present in the picture display device and which is directly synchronized in known manner by line synchronizing pulses 7'. In fact, in this case line oscillator 6' applies a signal of great amplitude and free from interference to pulse oscillator 6. However, it is alternatively possible to combine pulse oscillator 6 and line oscillator 6' in one single oscillator 6" (see FIG. 1) which results in an economy of components. It will be evident that line oscillator 6' and oscillator 6" may alternatively be synchronized indirectly, for example, by means of a phase discriminator. It is to be noted neither pulse oscillator 6, line oscillator 6' and oscillator 6" nor modulator 5 can be fed by the supply described since output voltage V o is still not present when the mains voltage is switched on. Said circuit arrangements must therefore be fed directly from the input terminals. If as described above these circuit arrangements are to be separated from the mains, a small separation transformer can be used whose primary winding is connected between the mains voltage terminals and whose secondary winding is connected to ground at one end and controls a rectifier at the other end.
Capacitor 27 is
arranged parallel to efficiency diode 7 so as to reduce the dissipation in switching transistor 2. In fact, if transistor 2 is switched off by the pulsatory control voltage, its collector current decreases and its collector-emitter voltage increases simultaneously so that the dissipated power is not negligible before the collector current has becomes zero. If efficiency diode 7 is shunted by capacitor 27 the increase of the collector-emitter voltage is delayed i.e., this voltage does not assume high values until the collector current has already been reduced. It is true that in that case the dissipation in transistor 2 slightly increases when it is switched on by the pulsatory control voltage but on the other hand since the current flowing through diode 7 has decreased due to the presence of the secondary windings, its inverse current is also reduced when transistor 2 is switched on and hence its dissipation has become smaller. In addition it is advantageous to delay these switching-on and switching-off periods to a slight extent because the switching pulses then contain fewer Fourier components of high frequency which may cause interferences in the picture display device and which may give rise to visible interferences on the screen of the display tube. These interferences occupy a fixed position on the displayed image because the switching frequency is the line frequency which is less disturbing to the viewer. In a practical circuit wherein the line frequency is 15,625 Hz and wherein switching transistor 2 is an experimental type suitable for a maximum of 350 V collector-emitter voltage or 1 A collector current and wherein efficiency diode 7 is of the Philips type BA 148 the capacitance of capacitor 27 is approximately 680 pF whilst the load is 70 W on the primary and 20 W on the secondary side of transformer 9. The collector dissipation upon switching off is 0.3 W (2.5 times smaller than without capacitor 27) and 0.7 W upon switching on.
As is known the so-called pincushion distortion is produced in the picture display tubes having a substantially flat screen and large deflection angles which are currently used. This distortion is especially a problem in color television wherein a raster correction cannot be brought about by magnetic means. The correction of the so-called East-West pincushion distortion i.e., in the horizontal direction on the screen of the picture display tube can be established in an elegant manner with the aid of the circuit arrangement according to the invention. In fact, if the voltage generated by comparison circuit 12 and being applied to modulator 5 for duration-modulating pulsatory voltage 3 is modulated by a parabola voltage 28 of field frequency, pulsatory voltage 3 is also modulated thereby. If the power consumption of the line deflection circuit forms part of the load on the output voltage of the chopper, the signal applied to the line deflection coils is likewise modulated in the same manner. Conditions therefore are that the parabola voltage 28 of field frequency has a polarity such that the envelope of the sawtooth current of line frequency flowing through the line deflection coils has a maximum in the middle of the scan of the field period and that charge capacitor 10 has not too small an impedance for the field frequency. On the other hand the other supply voltages which are generated by the circuit arrangement according to the invention and which might be hampered by this component of field frequency must be smoothed satisfactorily.
A practical embodiment of the described example with the reference numerals given provides an output for the supply of approximately 85 percent at a total load of 90 W, the internal resistance for direct current loads being 1.5 ohms and for pulsatory currents being approximately 10 ohms. In case of a variation of ± 10 percent of the mains voltage, output voltage V o is stable within 0.4 V. Under the nominal circumstances the collector dissipation of switching transistor 2 is approximately 2.5 W.
Since the internal resistance of the supply is so small, it can be used advantageously, for example, at terminal 15 for supplying a class-B audio amplifier which forms part of the display device. Such an amplifier has the known advantages that its dissipation is directly proportional to the amplitude of the sound to be reproduced and that its output is higher than that of a class-A amplifier. On the other hand a class-A amplifier consumes a substantially constant power so that the internal resistance of the supply voltage source is of little importance. However, if this source is highly resistive, the supply voltage is modulated in the case of a class-B amplifier by the audio information when the sound intensity is great which may detrimentally influence other parts of the display device. This drawback is prevented by means of the supply according to the invention.
The 50 Hz ripple voltage which is superimposed on the rectified input voltage V i is compensated by comparison circuit 12 and modulator 5 since this ripple voltage may be considered to be a variation of input voltage V i . A further compensation is obtained by applying a portion of this ripple voltage with suitable polarity to comparison circuit 12. It is then sufficient to have a lower value for the smoothing capacitor which forms part of rectifier circuit 1 (see FIG. 3). The parabola voltage 28 of field frequency originating from the field time base is applied to the same circuit 12 so as to correct the East-West pincushion distortion.
The PHILIPS CHASSIS TVC11 Shows even the use of the TEXAS INSTRUMENTS TMS1000:
Texas Instruments TMS1000
General
General Information
Texas Instruments was locked in a race with Intel to create the first microprocessor. By most accounts Intel won with the 4004, but there are a few die hard TI fans who say the TMS1000 was first, because it was the first “computer on a chip” and that the 4004 was just a calculator chip.
Texas Instruments followed the Intel 8080 with the 4-bit TMS1000. So, while Intel was leading the industry in microprocessors, TI led with this industry unique design "a computer on a chip", specifically designed for control and automation purposes. The 1000 was the first MCU (MicroComputer Unit) , which is an MPU (MicroProcessor Unit) with other support chips (such as RAM, ROM, counters, timers, I/O interfaces) integrated on to the same silicon chip.
The original 1000 family consists of 6 chips the TMS1000 and TMS1200 are basic chips, the TMS1070 and TMS1270 are high voltage versions to interface to displays, the TMS1100 and TMS1300 provide twice the on-board ROM and RAM. The TMS1000, TMS1070, and TMS1100 are 28-lead packages, the TMS1200, TMS1270, and TMS1300 are 40-lead versions of the same chips (just 200 to the 28-lead chip numbers).
In the 80's TI added to the 1000 family. The 28-lead TMS1170 started with a TMS1100 base and added fluorescent display drive capability and expanded memory (2KB ROM). The TMS1370 was the same as the TMS1170 and added 27 I/O lines. An expanded memory group based on the original TMS1000 chips was also created. They were the TMS1400, TMS1470, and TMS1700 (64 Bytes RAM, 4KB ROM). There were 40-lead versions of the TMS1400 and TMS1470, which because the TMS1600 and TMS1670. CMOS versions were also added, denoted with a "C" suffix, such as TMS1200C.
The TMS1000 also had system evaluator chips. The original evaluator chips were the TMS1098 and TMS1099. These 64-lead evaluator chips were ROM-less versions of their corresponding standard chips. The TMS1099 supported the TMS1000/TMS1200 and the TMS1070/1270. The TMS1098 supported the TMS1100/1300. Later evaluators were introduced to support the entire TMS1000 family, they were the SE1000P (supports TMS1000,1070,1200,1700), SE2200P (supports TMS1100,1170,1300,1370), and the SE1400P (supports 1400, 1470, 1600, 1670).
The success of the the TMS1000 is demonstrated by its long lifecycle (over 20 years) and its expanded product line. The TMS1000 is found in many appliances, control systems, and games. Most of these chips were sourced by companies for direct use in their products and will have custom or house numbers on the chips (not the standard numbers listed above). Even TI used custom numbers in its products.
PHILIPS 26P1195 MULTISTANDARD CHASSIS TVC11 Channel selector having a plurality of tuning systems:
A channel selector characterized in that a plurality of receivers capable of simultaneously performing a receiving operation have a main part of a phase
-locked loop frequency synthesizer connected in common thereto, the frequency synthesizer having a programmable frequency divider, a phase comparator, a reference oscillator and a reference frequency divider. The frequency synthesizer is controlled so that a local oscillation frequency corresponding to a determined frequency close to a broadcast signal of a desired receiving channel is synthesized, and one of a plurality of search tuning systems searches and tunes the broadcast signal from the local oscillation frequency.
1. A channel selector for controlling the tuning frequency of a plurality of receivers capable of simultaneously performing receiving operations, each of said plurality of receivers having a portion of a phase-locked loop frequency synthesizer; wherein another portion of a phase-locked loop frequency synthesizer is commonly used by said portions of said synthesizers whereby each of said plurality of receivers has an equivalent complete phase-locked loop frequency synthesizer;
and wherein each of said plurality of receivers has its own low pass filter included in its equivalent phase-locked loop frequency synthesizer, and an output of a phase comparator is switched to an input terminal of one low pass filter from among said plurality of low pass filters by a 3-st
ate switching circuit.
2. A channel selector according to claim 1, wherein said common portion of each of said equivalent phase-locked loop frequency synthesizers comprises a programmable frequency divider, a phase comparator, a reference oscillator and a reference frequency divider.
3. A channel selector according to claim 1, wherein said common portion of each of said equivalent phase-locked loop frequency synthesizers comprises a prescaler.
4. A channel selector according to claim 1, wherein said common portion of each of said equivalent phase-locked loop frequency synthesizers comprises a channel entry means and a code converter means.
5. A channel selector for controlling the tuning frequency of a plurality of receivers capable of simultaneously performing rec
eiving operations, each of said plurality of receivers having a portion of a phase-locked loop frequency synthesizer; wherein another portion of a phase-locked loop frequency synthesizer is commonly used by said portions of said synthesizers whereby each of said plurality of receivers has an equivalent complete phase-locked loop frequency synthesizer;
and wherein each of said equivalent phase-locked loop frequency synthesizers is controlled so that a local oscillation frequency corresponding to a predetermined frequency close to a broadcast signal of a desired receiving channel is synthesized, and one of a plurality of search tuning systems searches and tunes said broadcast signal from said local oscillation frequency whereby said broadcast signal of said desired receiving channel is tuned.
6. A channel selector for controlling the tuning frequency of a plurality of receivers capable of simultaneously performing receiving operations, each of said plurality of receivers having a portion of a phase-locked loop frequency synthesizer; wherein another portion of a phase-locked loop frequency synthesizer is commonly used by said portions of said synthesizers whereby each of said plurality of receivers has an equivalent complete phase-locked loop frequency synthesizer;
and wherein each of said phase-locked loop frequency synthesizers selects a desired receiving channel, and wherein a tuning voltage of said desired receiving channel is stored in a voltage memory means, and wherein said channel selector further comprises a tuning means provided for each of said plurality of receivers so that while receiving, said tuning means tunes in accordance with the output of said voltage memory means.
7. A channel selector according to claims 5 or 6, wherein said common portion of each of said equivalent phase-locked loop frequency synthesizers comprises a programmable frequency divider, a phase comparator, a reference oscillator and a reference frequency divider.
8. A channel selector according to claims 5 or 6, wherein said common portion of each of said equivalent phase-locked loop frequency synthesizers comprises a prescaler.
9. A channel selector according to claims 5 or 6, wherein said common portion of each of said equivalent phase-locked loop frequency synthesizers comprises a channel entry means and a code converter means.
This invention relates to a channel selector for use in television receivers, FM (frequency modulation) radio receivers, AM (amplitude modulation) radio receivers and so on.
TDA2581 CONTROL CIRCUIT FOR SMPS
The TDA2581 is a monolithic integrated circuit for controlling switched-mode power supplies (SMPS) which are provided with the drive for the horizontal deflection stage.
The circuit features the following:
— Voltage controlled horizontal oscillator.
— Phase detector.
— Duty factor control for the positive-going transient of the output signal.
— Duty factor increases from zero to its normal operation value.
— Adjustable maximum duty factor.
- Over-voltage and over-current protection with automatic re-start after switch-off.
— Counting circuit for permanent switch-off when n~times over~current or over-voltage is sensed
-Protection for open-reference voltage.
- Protection for too low supply voltage.
Protection against loop faults.
Positive tracking of duty factor and feedback voltage when the feedback voltage is smaller than the
reference voltage minus 1,5 V.
TDA2541 IF AMPLIFIER WITH DEMODULATOR AND AFC
DESCRIPTION
The TDA2540 and 2541 are IF amplifier and A.M.
demodulator circuits for colour and black and white
television receivers using PNP or NPN tuners. They
are intended for reception of negative or positive
modulation CCIR standard.
They incorporate the following functions : .Gain controlled amplifier .Synchronous demodulator .White spot inverter .Video preamplifier with noise protection .Switchable AFC .AGC with noise gating .Tuner AGC output (NPN tuner for 2540)-(PNP
tuner for 2541) .VCR switch for video output inhibition (VCR
play back).
.SUPPLYVOLTAGE : 12V TYP
.SUPPLYCURRENT : 50mATYP
.I.F. INPUT VOLTAGE SENSITIVITY AT
F = 38.9MHz : 85mVRMS TYP
.VIDEO OUTPUT VOLTAGE (white at 10% of
top synchro) : 2.7VPP TYP
.I.F. VOLTAGE GAIN CONTROL RANGE :
64dB TYP .SIGNAL TO NOISE RATIO AT VI = 10mV :
58dB TYP
.A.F.C. OUTPUT VOLTAGE SWING FOR
Df = 100kHz : 10V TYP
TPHILIPS 26P1195 MULTISTANDARD CHASSIS TVC11 Television intermediate frequency amplifier with feedback stabilization:
An I.F. amplifier is provided in which gain control is accomplished by varying the A.C. impedances of variable impedance devices, which devices are coupled as load and emitter degeneration impedances for amplifying transistors. Variable D.C. gain control currents are applied to the variable impedance devices to vary their impedance. Substantially all of the D.C. gain control currents flow through the variable impedance devices in current paths which are separate from the amplifying transistors, thereby avoiding variation of the operating points of the amplifying transistors. The I.F. amplifier includes a D.C. feedback path which does not require the use of feedback amplification, due to the lack of any changes in the operating points of the amplifying stages during gain control. Elimination of the need for feedback amplification also prevents the introduction of noise into the amplified I.F. signals.
1. A feedback stabilized television intermediate frequency amplifier system comprising:
an automatic gain control system for supplying a gain control signal;
a plurality of gain controlled differential amplifiers direct current coupled in a cascade configuration for amplifying intermediate frequency signals, each of said amplifiers being coupled to said automatic gain control system and responsive to said gain control signal for varying the intermediate frequency signal gain of each of said amplifiers, the
D.C. biasing of at least one of said amplifiers being substantially invariant to changes of said gain control signal, the first of said cascade coupled amplifiers including first and second differentially coupled amplifying transistors having base electrodes coupled to respective first and second input terminals, and the last of said cascade coupled amplifiers including third and fourth differentially coupled amplifying transistors having respective collector electrodes comprising first and second output electrodes of said amplifying system; and
a first D.C. feedback path coupled between said first output electrode and said first input terminal, and a second D.C. feedback path coupled between said second output electrode and said second input terminal, said feedback paths each exhibiting a voltage gain not greater than unity over a range of frequencies including D.C. and said television intermediate frequencies.
2. The feedback stabilized television intermediate frequency amplifier system of claim 1,
wherein said cascade coupled amplifiers and said first and second feedback paths comprise an amplifier and feedback loop, and
wherein said first D.C. feedback path comprises first, second and third resistors serially coupled between said first output electrode and said first input terminal, and said second D.C. feedback path comprises fourth, fifth and sixth resistors serially coupled between said second output electrode and said second input terminal; and further comprising
a first bypass capacitor coupled between the junction of said second and third resistors and the junction of said fifth and sixth resistors for providing a loop gain which is less than unity at said television intermediate frequencies; and
a second bypass capacitor coupled between the junction of said first and second resistors and the junction of said fourth and fifth resistors, said second bypass capacitor and said first and fourth resistors forming a decoupling network for decoupling said output electrodes from said input terminals.
3. The feedback stabilized television intermediate frequency amplifier system of claim 2, further comprising:
a video detector having first and second input terminals;
a fifth transistor having a base coupled to said first output electrode and an emitter coupled to said first resistor and said first input terminal of said video detector; and
a sixth transistor having a base coupled to said second output electrode and an emitter coupled to said fourth resistor and said second input terminal of said video detector,
wherein said fifth and sixth transistors buffer said output electrodes from said input terminals of said video detector.
4. The feedback stabilized television intermediate frequency amplifier system of claim 2, wherein the phase shift around said amplifier and feedback loop is substantially equal to an odd multiple of 180 degrees for frequencies at which the gain of said amplifier and feedback loop is equal to or greater than unity. 5. A feedback stabilized television intermediate frequency amplifying system comprising:
a first amplifying stage including first and second amplifying transistors coupled in a differential amplifier configuration, a first resistor coupled between the collector of said first transistor and a source of supply potential and passing a first direct current therebetween, a second resistor coupled between the collector of said second transistor and a source of supply potential and passing a second direct current therebetween, and means direct current coupled in shunt with said first and second resistors and responsive to variations of a first gain control current for causing gain variations for said first amplifying stage with negligible disturbance of the magnitude of said first and second direct currents; and
a second amplifying stage direct current coupled in cascade with said first amplifying stage, and including third and fourth amplifying transistors coupled in a differential amplifier configuration, a third resistor coupled between said emitter of said third transistor and a point of signal reference potential and passing a third direct current therebetween, a fourth resistor coupled between said emitter of said fourth transistor and a point of signal reference potential and passing a fourth direct current therebetween, and means direct current coupled in shunt with said third and fourth resistors and responsive to variations of a second gain control current for causing gain variations for said second amplifying stage with negligible disturbance of the magnitude of said third and fourth direct currents; and
a first D.C. feedback path coupled between the collector of said third transistor and the base of said first transistor, and a second D.C. feedback path coupled between the collector of said fourth transistor and the base of said second transistor, said feedback paths each exhibiting a voltage gain not greater than unity over a range of frequencies including D.C. and said television intermediate frequencies.
6. The feedback stabilized television intermediate frequency amplifier system of claims 1 or 5, wherein said differential amplifiers and said first and second D.C. feedback paths comprise a D.C. feedback amplifier loop exhibiting a loop voltage gain not greater than unity over a first range of frequencies including said television intermediate frequencies and a loop phase shift which is approximately equal to 180 degrees over a second range of frequencies located between D.C. and said first range of frequencies.
This invention relates to television intermediate frequency (I.F.) amplifiers and, in particular, to a multistage I.F. amplifier in which two techniques of gain control are advantageously combined to produce a high gain amplification system utilizing a simplified feedback path for D.C. stabilization.
In a conventional television I.F. amplifying section, several amplifier stages are usually cascaded to provide high amplification for the I.F. signal which is received from the tuner and mixer circuitry. Since the received I.F. signal may be of varying signal strength, one or more of the amplifier stages is generally gain controlled, so that the final I.F. amplifier stage will provide a substantially constant strength signal to the video detector.
However, as the gain of the gain controlled stage or stages is varied by the usual techniques of forward or reverse gain control, the operating points of the amplifier stages are unavoidably changed as the D.C. currents conducted by the amplifier stages change. These D.C. operating point shifts will be applied to subsequent stages in the amplifier when the amplifiers are direct current coupled to each other, which is the conventional technique currently in use. This will result in undesirable alteration of the operating points of the subsequent stages, as the changing D.C. currents are propagated through the cascaded amplifier stages. Furthermore, the D.C. currents will cause changes in the D.C. level of the amplified signal, which can adversely affect the operation of the video detector. It is therefore desirable for the I.F. amplifier to be gain controlled in a manner which avoids shifts in the operating points of the amplifying devices.
In accordance with the principles of the present invention, an I.F. amplifier is provided in which gain control is accomplished by varying the A.C. impedances of variable impedance devices, which devices are coupled as load and emitter degeneration impedances for amplifying transistors. Variable D.C. gain control currents are applied to the variable impedance devices to vary their impedance. Substantially all of the D.C. gain control currents flow through the variable impedance devices in current paths which are separate from the amplifying transistors, thereby avoiding variation of the operating points of the amplifying transistors. Since the operating points of the various stages are substantially unaffected during gain control, the individual stages may be designed to operate at optimum, substantially unvarying bias points.
In order to stabilize the operating points of the amplifying stages in I.F. amplifiers against changes such as those due to the aforementioned D.C. shifts, as well as temperature induced shifts and variation in device characteristics from one amplifier to another, a D.C. feedback path is generally coupled between the first and last amplifying stages. The complexity of the D.C. feedback path is dependent upon the magnitude of D.C. correction which the amplifiers are expected to require for stable operation. In some I.F. amplifiers, such as the one used in the TDA2540 TV I.F. IC, the D.C. gain of the I.F. amplifier and feedback loop is relatively low. This can result in insufficient D.C. feedback under certain low gain operating conditions. In order to provide the required amount of feedback, a separate amplifier is coupled in its own feedback loop at the output of the final I.F. stage. This amplifier is used to provide the required amount of feedback for the I.F. system, which prevents a lockout condition from occurring during channel switching. Pursuant to the principles of the present invention, the I.F. amplifier includes a D.C. feedback path which does not require the use of such a feedback amplifier, due to the lack of any changes in the operating points of the amplifying stages during gain control. Elimination of the feedback amplifier also prevents the introduction of noise into the amplified I.F. signals by this amplifier.
The sole drawing FIGURE illustrates in schematic and block diagram form a three stage I.F. amplifier constructed in accordance with the principles of the present invention.
Referring to the drawing, three differential I.F. amplifier stages 1, 100 and 200 are coupled in cascade, with a feedback path 300 coupled between the third and first stages 200 and 1. The three stages are gain controlled by control currents supplied by an AGC system 40, and bias voltages for the system are provided by a bias supply 70.
A push-pull video I.F. signal is applied across input terminals 32 and 34, which are coupled to the bases of buffer transistors 50 and 52 of the first stage 1. The collectors of the buffer transistors 50 and 52 are coupled to the bias supply 70, and their respective emitter electrodes are coupled to the bases of amplifying transistors 10 and 12. Biasing for the emitter-base connections of transistors 50 and 10, and 52 and 12, is provided by resistors 54, 56 and 58. A D.C. ground return path for the emitters of transistors 10 and 12 is provided by resistors 66, 67 and 69, and pinch resistor 68. The pinch resistor 68 is also used to stabilize beta variations in the transistors of the first stage, which variations may occur from one circuit to another during volume production of the amplifier in integrated circuit form.
The A.C. emitter impedance of transistors 10 and 12 is dominated by a resistor 62 and a peaking capacitor 64, which are coupled in parallel between the emitters of the transistors. Each amplifying transistor 10 or 12 has a load impedance comprising a resistor 18 or 20 coupled between the collector of the respective transistor and the bias supply 70, and a variable impedance device. The collector of transistor 10 is coupled to the base of a variable impedance device 14, and the collector of transistor 12 is coupled to the base of a variable impedance device 16. The variable impedance devices 14 and 16 have collectors which are coupled to a reference potential (ground) and joined emitters, which are coupled to receive control current from the AGC system 40 by way of a resistor 22.
The output signals at the collectors of the amplifying transistors 10 and 12 are direct current coupled to the bases of buffer transistors 150 and 152 of the second amplifying stage 100. The second amplifying stage 100 is constructed in a similar manner as the first amplifying stage 1, and respective similar circuit elements have reference numerals which are increased by one hundred as compared with their counterparts in the first stage. The second stage 100 differs from the first stage in that it does not include a peaking capacitor or a pinch resistor. A forward biased diode 170 is coupled between the emitter resistor 169 and ground. This diode cooperates with the amplifying and buffer transistors in the second stage to provide the collectors of transistors 10 and 12 with a 3 Vbe D.C. term for bias and temperature stabilization purposes. It may be seen that the collector of transistor 10 is D.C. biased by the base-emitter junctions of transistors 150 and 110, and the junction of diode 170. Similarly, the collector of transistor 12 is D.C. biased by the base-emitter junctions of transistors 152 and 112, and the junction of diode 170.
The construction and operation of the first and second amplifying stages 1 and 100 is described in detail in my copending United States Patent Application Ser. No. 143,032, entitled "VARIABLE LOAD IMPEDANCE GAIN-CONTROLLED AMPLIFIER", filed Apr. 23, 1980, the subject matter of which is incorporated by reference. There it is explained that the gain of the amplifying stages is varied by varying the voltage and hence the current supplied to the variable impedance devices 14, 16 and 114, 116. Under maximum gain conditions, little or no current is supplied to the devices, and their base-to-emitter A.C. impedance is relatively high. The device impedance is in parallel with a respective collector load resistor 18, 20, 118 or 120, which combined impedance determines the load line of the amplifier. As the I.F. signal supplied to the amplifiers increases in amplitude, the current supplied to the variable impedance devices by the AGC system 40 also increases. This causes the base-to-emitter impedance of the devices to decrease, as charge is stored in the base-emitter regions of the devices. The decreased impedance of the devices reduces the collector impedance of the amplifying transistors 10, 12, 110, 112, which shifts their load lines to a lower gain condition. When the amplifying stages are in a full gain-reduced condition, the current supplied to the variable impedance devices is at a maximum value, which is of the order of several milliamperes. The primary current paths for the current supplied by the AGC system 40 is through the emitter-to-collector paths of the variable impedance devices 14, 16, 114 and 116. Thus, substantially no D.C. gain control current from the AGC system flows in the collectors of the amplifying transistors 10, 12, 110 and 112. The D.C. biasing of the amplifying transistors is therefore substantially constant as the ranges of gain control of the amplifying stages are traversed.
The collectors of the second stage amplifying transistors 110 and 112 are respectively direct current coupled to the bases of buffer transistors 250 and 252 of the third amplifying stage 200. The collectors of buffer transistors 250 and 252 are coupled to receive bias voltage from the bias supply 70, and their emitters are returned to ground by resistors 254, 256 and 258. The emitters of buffer transistors 250 and 252 are also coupled to the bases of amplifying transistors 210 and 212, respectively.
The collectors of the amplifying transistors 210 and 212 are coupled to the bias supply 70 by way of respective load resistors 218 and 220. The emitters of the amplifying transistors 210 and 212 are returned to ground through resistors 262, 264 and 266. A forward biased diode 270 is coupled between resistor 266 and ground. Diode 270 performs a similar function as that of diode 170, as it cooperates with the buffer and amplifying transistors 250, 252, 210 and 212 to provide the collectors of the second stage amplifying transistors 110 and 112 with a quiescent D.C. voltage term of 3 Vbe.
A resistor 260 is coupled between the emitters of transistors 210 and 212. The emitters of transistors 210 and 212 are also coupled to the bases of respective variable impedance devices 214 and 216. The collectors of the variable impedance devices 214 and 216 are coupled to ground, and their emitters are coupled to receive gain control current from AGC system 40 by way of a resistor 222.
The third amplifying stage 200 is constructed and operates in a similar manner as the amplifier described in my copending United States Patent Application Ser. No. 143,035, entitled "VARIABLE EMITTER DEGENERATION GAIN-CONTROLLED AMPLIFIER," filed Apr. 23, 1980, which is incorporated by reference. Briefly, the emitter resistance of each amplifying transistor includes one-half of the value of resistor 260 (due to the complementary operation of the amplifying transistors in response to push-pull I.F. signals), in parallel with the base-to-emitter impedance of a variable impedance device and a further bias resistor. The variably impedance devices 214 and 216 may be constructed in the same manner as variable impedance devices 14, 16, 114 and 116, and are characterized by a base-to-emitter A.C. impedance which decreases as the current supplied to them by the AGC system 40 increases. For the maximum gain condition of the third amplifying stage 200, the current supplied to the variable impedance devices is at a maximum. This provides a low emitter impedance to the amplifying transistors 214 and 216, causing a relatively low level of emitter degeneration. As the gain control range of the amplifier is traversed toward its minimum gain condition, the current supplied to the variable impedance devices is decreased, which increases the A.C. impedance presented to the amplifying transistors by the devices. The emitter degeneration is increased, and hence the gain of the amplifier is reduced. As in the case of the variable impedance devices described previously, the primary current path for the control current supplied by the AGC system 40 is through the emitter-to-collector paths of devices 214 and 216, which minimizes changes in the D.C. biasing of the amplifying transistors 210 and 212 as the gain control range of the amplifier is traversed.
The use of collector-controlled variable load line gain control in the first two amplifying stages and controlled emitter degeneration in the third stage reduces the maximum amount of current required for gain control and therefore the power dissipation in the I.F. amplifier system. Control current is supplied to the variable impedance devices of the first two stages by way of a common terminal 42 of the AGC system 40. The gain of these two stages is reduced by increasing the flow of control current. Control current is supplied to the variable impedance devices of the third stage by way of a separate terminal 44. The gain of this stage is reduced by decreasing the flow of control current from the AGC system 40 to the third stage. An advantageous sequence of gain control for the illustrated embodiment is described in my copending United States Patent Application Ser. No. 163,143, entitled "TELEVISION INTERMEDIATE FREQUENCY AMPLIFIER", concurrently filed herewith.
An amplified I.F. signal is developed across the collector load resistors 218 and 220, and is applied to a video detector 400 from the collectors of transistors 210 and 212 by way of transistors 301 and 303. Transistors 301 and 303 are coupled in emitter follower configurations, with their collector coupled to receive a supply potential from bias supply 70, and their emitters coupled to ground by respective resistors 304 and 306. These transistors buffer the load resistors 218 and 220 of the third amplifying stage 200 from the input impedance of the video detector, and provide a low impedance drive at their emitters. The emitters of transistors 301 and 303 are also coupled to the feedback path 300. Transistors 301 and 303 provide a quiescent D.C. voltage term at the collectors of transistors 210 and 212 of 3 Vbe, in combination with first stage transistors 10, 50, 12 and 52, through the feedback path 300.
The feedback path 300 is comprised of two D.C. paths, one for each side of the balanced amplifier configuration. A feedback path including serially coupled resistors 318, 314, 324 and 328 is coupled between the emitter of transistor 301 and the base of first stage transistor 52. A second feedback path including serially coupled resistors 310, 316, 326 and 330 is coupled between the emitter of transistor 303 and the base of transistor 50.
The feedback path 300 includes two decoupling networks which decouple the amplified output I.F. signals from the input of stage 1. A first decoupling network includes buffer resistors 310 and 318 and a capacitor 312, and the second decoupling network includes buffer resistors 314 and 316, and bypass capacitors 322 and 320. Resistors 310 and 318 isolate the output at the emitters of transistors 301 and 303 from capacitor 312. The capacitor 312 is coupled across the two D.C. paths to significantly attenuate the complementary I.F. signals which are produced on the two paths. Any remaining I.F. signal components which appear on the two plates of capacitor 312 are then applied to bypass capacitors 322 and 320 by buffer resistors 314 and 316, respectively. The bypass capacitors 322 and 320 will then shunt any remaining I.F. signal components to ground. The decoupling networks act as low pass filters for the I.F. signals, with breakpoints below the desired range of I.F. signals, so that substantially only D.C. signals are applied to buffer resistors 324 and 326. The values of the resistors are chosen so that the D.C. feedback signals are not attenuated beyond a level at which they will provide the desired amount of feedback compensation in the first stage 1.
It is seen that bypass capacitors 322 and 320 are each coupled between a D.C. path and ground, whereas the capacitor 312 of the first decoupling network is coupled between the two D.C. paths. The coupling of capacitor 312 is the preferred technique, since capacitors 322 and 320 bypass I.F. signals to ground, and capacitor 312 does not. The I.F. signals which are conducted by capacitors 322 and 320 will be conducted through the ground plane of the system until they cancel each other. If the ground points to which the capacitors are connected are in close proximity to each other, the ill effects resulting from ground plane conduction of the I.F. signals will be partially mitigated. However, adjacent location of the two capacitors 322 and 320 is not always possible, especially when the system is constructed in integrated circuit form, wherein other considerations may govern the placement of the two capacitors. In that case, the I.F. signals may contaminate undesirably large areas of the I.C. ground plane, resulting in undesirable I.F. signal coupling to other circuitry in the system through ground connections. This problem is eliminated through the use of a capacitor coupled between the two D.C. paths, as is capacitor 312, since no I.F. signals are coupled to the ground plane by this decoupling network. If desired, the second decoupling network, including resistors 314 and 316, and capacitors 322 and 320, may be dispensed with in an embodiment of the illustrated arrangement, depending upon the level of I.F. signal cancellation desired and provided by the first decoupling network.
Buffer resistors 324 and 326 are coupled to the input transistors 52 and 50 by way of terminals 334 and 332 and isolation resistors 328 and 330, respectively. A further bypass capacitor 333 is coupled between terminals 332 and 334. The isolation resistors 328 and 330 serve to isolate the inputs to the first amplifying stage 1 from bypass capacitor 333. The bypass capacitor 333, together with resistors 324, 314, 318, and 326, 316, 310, determine the 3 db point of the I.F. amplifier and feedback loop, to assure system stability.
At maximum gain, the I.F. amplifying stages shown in the illustrated embodiment will have a gain of approximately 60 db. The system bandwidth is assumed to be approximately 100 MHz. In order to assure that the system will be stable, the phase and gain of the signal which is fed back from the third to the first stage must be controlled to prevent system oscillation. System oscillation will be prevented as long as the loop phase delay does not approach an even multiple of 180 degrees at any frequency at which the loop gain is equal to or greater than unity.
The I.F. signals which are applied to input terminals 32 and 34 undergo a phase reversal in each I.F. amplifying stage. If the I.F. system had unlimited bandwidth, the I.F. signals at the output of the third stage would be 180 degrees out of phase with respect to the input signals, thus readily providing a negative feedback signal. However, the system is assumed to have a limited bandwidth of 100 MHz, which introduces some phase delay into the amplified I.F. signals. This phase delay may only amount to a few degrees at low frequencies, but can amount to 80 degrees or more at I.F. frequencies around 50 MHz. The output I.F. signals will undergo even further delay in the decoupling networks of the feedback path. If the additional feedback delay should cause the signals to have a net delay which approaches an even multiple of 180 degrees around the loop at any frequency, the feedback will be positive and the system will be subject to oscillation at that frequency.
The value of capacitor 333 is chosen in combination with the values of resistors 324, 314, 318, and 326, 316, 310 to establish a pole at a frequency which is referred to as the 3 db frequency. Above the 3 db frequency, the amplitudes of higher frequency signal components will roll off at approximately 6 db per octave, or 20 db per decade of frequency. If the rolloff were chosen to be greater, such as 18 db per octave, each additional db of attenuation will cause the phase shift of the feedback path to increase proportionately, so that the feedback path phase shift will rapidly approach 180 degrees at higher frequencies, which could lead to oscillation at these higher frequencies.
The placement of the pole at the 3 db frequency must guarantee no greater than unity gain at all frequencies above a higher, unity gain frequency and including the I.F. frequency range about 50 MHz, which permits phase shifts in that frequency range to be neglected. For purposes of illustration, assume that the loop including the amplifiers and the feedback path provides 6 degrees of phase shift at 1 MHz, (plus the three signal inversions of the three amplifiers, which will be assumed to be present at all frequencies). Further assume that the feedback 3 db pole is located at 1 KHz, and provides a rolloff of 6 db per octave, or 20 db per decade. This rolloff will therefore provide 20 db of attenuation at 10 KHz, 40 db of attenuation at 100 KHz, and 60 db of attenuation at 1 MHz. Frequencies greater than 1 MHz will be attenuated by more than 60 db. Since the maximum gain of the amplifying stages is assumed to be 60 db, the 1 MHz frequency is the unity gain frequency for the amplifier and feedback loop. Although the delay in the 1 to 50 MHz range varies from 6 degrees to upwards of 80 degrees, the feedback attenuation is greater than 60 db over this range, which prevents loop gain of unity or greater over the range. Thus, one of the criteria for oscillation, unity gain, is not met, and the system will not oscillate at frequencies within this range. Furthermore, at frequencies below 1 MHz, the phase shift of the feedback path is 6 degrees or less, which prevents the occurrence of loop phase shifts approaching an even multiple of 180 degrees, which is the second condition necessary for oscillation.
Therefore, the system is seen to be stable for a 1 KHz 3 db pole and a rolloff of 6 db per octave.
Unlike the prior art I.F. amplifier system described previously, the I.F. amplifier of the present invention does not require an additional amplifier in the feedback path 300. This additional amplifier was needed in the prior art arrangement because that arrangement is characterized by low D.C. gain due to the exclusive use of emitter degeneration type amplifying stages. As the gain of those stages is reduced, the D.C. gain is also reduced, and hence the additional amplifier is required to amplify the D.C. feedback signal. Of the three amplifying stages of the present invention, only the third stage uses emitter degeneration gain control. The third stage D.C. gain is dominated by the emitter resistors 260, 262 and 264, which gives the third stage a high input impedance and a low frequency gain of approximately 10 db. The first and second amplifying stages, which rely upon load line variation for gain control, have respective D.C. gains of approximately 20 db. The D.C. gain of the three cascaded states is fairly constant over the full range of gain control, and has been found to vary by no more than 6 db over the range. This stability in D.C. gain is attributed to the nonvarying D.C. biasing of the amplifying stages, as a result of the use of variable impedance devices, the control of which does not substantially affect the D.C. biasing of the amplifying transistors.
PHILIPS 26P1195 MULTISTANDARD CHASSIS TVC11 COLOR AMPLIFIER WITH Constant bandwidth RGB output amplifiers having simultaneous gain and DC output voltage control :
A color television receiver includes conventional circuitry for processing and detecting a received color television signal. Three chrominance-luminance matrices combine detected color difference and luminance signals forming color red, blue and green video signals. Emitter follower coupling stages apply the color video signals individually to each
of three output amplifiers which in turn drive the cathode electrodes of a unitized gun CRT. Potentiometers couple the emitter electrodes of the output amplifiers to a source of operating potential providing a simultaneous signal gain and DC output voltage adjustment for each amplifier during CRT color temperature setup. A voltage divider controls the voltage applied to the common screen grid electrode of the CRT providing a master setup adjustment.
1. In a color televison receiver, for processing and displaying a received television signal bearing modulation components of picture information, having a cathode ray tube including a trio of electron source means producing individual electron beams impinging an image screen to form three substantially overlying images and in which the respective operating points and relative conduction levels of said electron source means determine the color temperature of the reproduced image, the combination comprising:
master conduction means, coupled to said trio of electron source means simultaneously varying said conduction levels;
a plurality of substantially equal bandwidth amplifiers, each coupled to a different one of said electron source means, separately influencing said conduction levels;
low output impedance signal translation means recovering said picture information and supplying it to each of said plurality of amplifiers; and
separate adjusting means individually coupled to at least two of said amplifiers for simultaneously producing predetermined same sense variations in gain and DC output voltage of its associated amplifier while preserving said bandwidths.
2. The combination set forth in claim 1, wherein the transconductance and cutoff voltage of each of said electron source means bear a predetermined relationship and wherein said simultaneous predetermined variations in gain and DC output voltage are determined by said transconductance-cutoff voltage relationship. 3. The combination set forth in claim 2, wherein said plurality of amplifiers each include a gain and DC output voltage determining impedance and wherein each of said separate adjusting means include:
a variable impedance, coupling said gain and DC output voltage determining impedance of said associated amplifier to a source of bias current and forming a shunt path for signals within said amplifier.
4. The combination set forth in claim 3, wherein each of said electron source means include a cathode electrode and wherein each of said amplifiers include:
a transistor having input, common, and output electrodes, said output electrode being coupled to said electron source means cathode.
5. The combination set forth in claim 4, wherein said gain and DC output voltage determining impedance is coupled to said common electrode. 6. The combination set forth in claim 5, wherein said input, common, and output electrodes of said transistors are defined by base, emitter, and collector electrodes, respectively. 7. The combination set forth in claim 6, wherein said gain and DC output voltage determining impedance includes a resistor coupling said emitter electrode to ground and wherein said variable impedance includes:
a resistive control, having a variable resistance, coupling said emitter electrode to a source of operating potential.
8. The combination set forth in claim 7, wherein said three electron source means include control grid and screen grid electrodes common to said three electron guns and wherein variations of cathode electrode voltages permit changes of said relative conduction levels and said respective operating points. 9. The combination set forth in claim 8, wherein said master conduction means includes a variable bias potential source coupled to said common screen grid electrode.
This invention relates to color television receivers and in particular to cathode ray tubes (CRT) drive systems therefor. Each of the several types of color television cathode ray tubes in current use includes a trio of individual electron sources producing distinct electron beams which are directed toward an image screen formed by areas of colored-light-emitting phosphors deposited on the inner surface of the CRT. The phosphors emit light of a given additive primary color (red, blue or green) when struck by high energy electrons. A "delta" electron gun arrangement, in which the electron sources comprise three electron guns disposed at the vertice
s of an equilateral triangle, having its base oriented in a horizontal plane and its apex above or below the base plane, may be used. Alternatively, the three electron sources may be "in line", that is, positioned in a horizontal line. In either case, the three beams produced are subjected to deflection fields and scan the image screen in both the horizontal and vertical directions thereby forming three substantially overlying rasters.
The phosphor deposits forming the image screen may alternatively comprise round dots, elongated areas, or uninterrupted vertical lines. A parallax barrier or shadow mask, defining apertures generally corresponding to the shape of the phosphor areas, is interposed between the electron guns and the image screen to "shadow" or block each phosphor area from electrons emitted from all but its corresponding electron gun.
A color television signal includes both luminance (monochrome) and chrominance (color) picture components. In the commonly used RGB drive systems the separately processed luminance and chrominance information is matrixed (or combined) before application to the CRT cathodes. Three output amplifiers apply the respective red, blue and green video signals thus produced for controlling the respective electron source currents.
The luminance components have substantially the same effect on all three electron sources whereas the color components are differential in nature, causing relative changes in electron source currents. In the absence of video signals, the combined raster should be a shade of grey. At high gun currents, the grey is very near white and at low settings, it is near black. The "color", commonly called color temperature, of the monochrome raster depends upon the relative contributions of red, blue and green light. At high color temperatures, the raster may appear blue and at low color temperatures it may appear sepia. While the most pleasing color temperature is largely a matter of design preference, ideally the receiver should not change color temperature under high and low brightness nor for high and low frequency picture information.
Generally, the electron sources comprise individual electron guns each including separately adjustable cathode, control grid and screen grid electrodes and a desired color temperature is achieved by adjustment of each electrode voltage during black and white setup. While the exact setup procedure employed varies with the manufacturer and specific CRT configuration, all manufacturers attempt to achieve consistent color temperature throughout the usable range of CRT beam current variations.
A typical color temperature adjustment involves setting the low light color temperature condition of each electron gun by adju
sting its screen grid electrode voltage to produce the required DC conditions between electron guns at minimum beam currents. A high light or dive adjustment at increased CRT beam current is then made to insure consistent color temperature. In receivers utilizing CRT's with separately adjustable screen grid electrode voltages, the drive adjustment may take the form of a minor change in signal gain of the output amplifiers. The process is, in essence, one of configuring the operating points of the three electron guns to conform to three substantially identical output amplifiers.
The recently developed economical "unitized gun" type CRT has a combined electron source structure in which three common control grids and three common screen grids are used with the cathodes being the only electrically separate electrodes. The greatly simplified and more economical unitized gun structure, however, imposes some restrictions on the circuitry used to drive the electron sources. Perhaps most significant is the absence of
the flexibility previously provided by individually adjustable screen grid electrode voltages. Due in part to the inverse relationship between electron source transconductance, which may be thought of as "gain" of the electron source, and cutoff voltage, the typical individual low level color temperature or equal cutoff adjustment described above also performs the additional function of establishing nearly equal transconductances for the three electron sources. As a result only minor relative changes in electron source currents occur at higher CRT beam currents.
Color temperature adjustment in a receiver with a unitized gun CRT involves a somewhat different process, namely, configuring the drive and bias applied to each of the gun cathodes to accommodate differences in relative electron source characteristics which, without the equalizing effect of separate screen electrode adjustments, may be considerable.
Initially television receivers using unitized gun CRT's utilized a variable DC voltage divider operative upon each output amplifier to provide adjustment of the DC cutoff voltage. Drive, or signal gain, adjustment to accommodate differences in electron source transconductances was generally accomplished by separate individual gain controls operative on each of the output amplifiers.
However, the more recently developed unitized gun systems combine the DC voltage (cutoff) and signal gain (drive) adjustments for each electron source by simultaneously varying the signal gain and DC voltage in the same direction in a predetermined relationship. One such system used three CRT coupling networks each of which includes a variable impedance simultaneously operative on both the amplitude of coupled signal and DC voltage. Another system uses a variable collector load impedance for each of the output amplifiers, making use of the changes in amplifier signal gain and DC output voltage resulting from collector load variations.
While such systems provide an adequate range of adjustment to achieve color temperature setup using a reduced number of controls, they often degrade image quality. Ideally, the luminance portion of the signal is applied uniformly to each of the three electron sources. Although the relative signal amplitudes may be varied to accommodate transconductance differences between electron sources, it is desirable that each applied signal be an otherwise identical replica of the others. The variable impedance elements in the voltage divider networks and variable collector loads of the prior art interact with the capacities inherent in the output amplifiers and electron gun structures to produce unequal bandwidths for the different color video signals, which cause color changes in their high frequency components (which correspond to detailed picture information). The resulting effect upon the displayed image is similar in appearance to the well-known "color fringing" or misconvergence effect.
OBJECTS OF THE INVENTION
It is an object of the present invention to provide an improved color television receiver.
It is a further object of this invention to provide a novel CRT color temperature setup system.
SUMMARY OF THE INVENTION
In a color television receiver, for processing and displaying a received television signal bearing modulation components of picture information, a
cathode ray tube includes three electron source means producing individual electron beams which impinge an image screen to form three substantially overlying images. The respective operating points and relative conduction levels of the electron source means determine the color temperature of the reproduced image. Master conduction means, coupled to the three electron source means, simultaneously vary the conduction levels and a plurality of substantially equal bandwidth amplifiers, each coupled to a different one of the electron source means, separately influence the conduction levels. Low output impedance signal translation means recover the picture information and supply it to each of the amplifiers. Separate adjusting means are individually coupled to at least two of the amplifiers for simultaneously producing predetermined variations in the gain and DC output voltage of the amplifiers while preserving the bandwidths.
BRIEF DESCRIPTION OF THE DRAWING
The drawing shows a partial-schematic, partial-block diagram representation of a color television receiver constructed in accordance with the present invention.
DESCRIPTION OF THE PREFERRED EMBODIMENT
Referring to the drawing, a signal processor 10 includes conventional circuitry (not shown) for amplifying a received television signal and detectingthe modulated components of luminance and chrominance information therein. The output of signal processor 10 is coupled to a luminance amplifier 11 and a chrominance processor 30. Luminance amplifier 11 is conventional and includes circuitry controlling brightness and contrast of the luminance signal. The output of luminance amplifier 11 is coupled to three luminance-chrominance matrices 12, 13 and 14. Chrominance processor 30 includes conventional chrominance information detection circuitry for providing three color difference or color-minus-luminance output signals (R-Y, G-Y and B-Y) which are individually coupled to luminance-chrominance matrices 12, 13 and 14, respectively. The signal from luminance amplifier 11 is combined with the color-minus-luminance signals from chrominance processor 30 to form the respective red, green and blue video signals which are coupled to the R, G and B output amplifiers 15, 16 and 17, respectively. The outputs of amplifiers 15, 16 and 17 are coupled to the cathode electrodes 23, 24 and 25, respectively, of a CRT 20 having an image screen 21. A voltage divider, formed by a series combination of resistors 83 and 84, is coupled between a source of operating potential +V2 and ground. The junction of resistors 83 and 84 is connected to a common control grid electrode 28 and to ground by a filter capacitor 85 which provides a signal bypass. A potentiometer 80 and a resistor 81 are series coupled between a source of operating potential +V1 and ground, forming another voltage divider. The junction of potentiometer 80 and resistor 81 is connected to common screen grid electrode 29 and to ground by a bypass capacitor 82. Cathode electrodes 23-25, control grid electrode 28 and screen grid electrode 29 are part of a unitized gun structure in CRT 20 with the control grid and screen grid being common to each of the three electron sources defined by the separate cathode electrodes.
While luminance-chrominance matrices 12 and 13 are shown in block form, it should be understood that they are identical to the detailed structure of matrix 14. Similarly, red output amplifier 15 and green output amplifier 16 are identical to the detailed structure of blue output amplifier 17. Further, the receiver shown is understood to include conventional circuitry for horizontal and vertical electron beam deflection together with means deriving a CRT high voltage accelerating potential, all of which have, for clarity, been omitted from the drawing.
Luminance-chrominance matrix 14 includes a matrix transistor 40 having an emitter electrode 41 coupled to ground by a resistor 55 and by a series combination of resistors 46 and 47, a base electrode 42 coupled to the output of luminance amplifier 11, and a collector electrode 43 coupled to a source of operating potential +V3 by a resistor 45. The B-Y output of chroma processor 30 is connected to the junction of resistors 46 and 47. An emitte
r-follower transistor 50 has an emitter electrode 51 coupled to ground by a resistor 56, a base electrode 52 connected to the collector of matrix transistor 40, and a collector electrode 53 connected to +V3.
Blue amplifier 17 includes an output transistor 60 having an emitter electrode 61 coupled to ground by a series combination of resistors 67 and 68, a base electrode 62 connected to the emitter of transistor 50, and a collector electrode 63 coupled to +V2 by a resistor 66. A series combination of a potentiometer 70 and a resistor 69 couples the junction of resistors 67 and 68 to +V3. Collector 63, which is the output of amplifer 17, is connected to cathode 25 of CRT 20.
During signal reception, the separately processed luminance and B-Y color difference signals are applied to matrix transistor 40. The combined signal developed at its collector 43 forms the blue video signal which controls the blue electron beam in CRT 20 and represents the relative contribution of blue light in the image produced.
The blue video signal at collector 43 is coupled via transistor 50 to base 62 of output transistor 60. The low source impedance of emitter follower transistor 50 obviates any detrimental effects upon the blue video signal due to loading at the input to amplifier 17 caused by gain or frequency dependent input impedance variations of amplifier 17. The blue video signal applied to base 62 is amplified by transistor 60 to a level sufficient to control the conduction of its respective electron source.
During color temperature setup, a predetermined setup voltage (corresponding to black) is applied to matrices 12, 13 and 14. The voltage on common screen grid electrode 29 is adjusted, by varying potentiometer 80 which together with resistor 81 and capacitor 82 form master conduction means, to cause a low brightness raster to appear on image screen 21. As will be seen, adjustment of potentiometer 70 and the corresponding potentiometers in amplifiers 15 and 16 establish the correct combination of DC electron source cathode voltages and output amplifier gains to produce the selected color temperature at both low and high CRT beam currents.
Amplifier 17 includes a common emitter transistor stage in which the impedance coupled to emitter electrode 6 is a gain and DC output voltage determining impedance. Signal gain is approximately equal to the ratio of the collector impedance (resistor 66), to this gain and DC voltage determining impedance (ignoring the effects of capacities associated with the tr
ansistor and the electron gun which will be considered later). Because the source of operating potential +V3 coupled to potentiometer 70 forms a good AC or signal ground, the series combination of resistor 69 and potentiometer 70 are effectively in parallel with resistor 68 and the total impedance coupling emitter 61 to signal ground comprises resistor 67 in series with this combination of resistors 68 and 69 and potentiometer 70. Variations in this impedance caused by adjustment of potentiometer 70 changes the ratio of collector to emitter impedances and thereby the gain of amplifier 17. If potentiometer 70 is varied to present increased resistance, gain is reduced and if varied to present decreased resistance, gain is increased.
The DC voltage at collector 63 of transistor 60 is determined by the product of the collector resistance and quiescent collector current (current in the absence of applied signal) and V2. The voltage at base 62 is established by the emitter voltage of transistor 50. Variations in the resistance of potentiometer 70 cause variations in current flow in the series path including potentiometer 70 and resistors 69 and 68. The voltage developed across resistor 68 is supplied to emitter 61 through resistor 67.
In the absence of signal, the DC voltage at base 62 is constant and the relative voltage between base 62 and emitter 61, which controls the conduction level of transistor 60, is a function of the voltage at emitter 61. Increases in the resistance of potentiometer 70 reduce the emitter voltage, increase the relative base-emitter voltage of transistor 60, and increase collector current. The increased collector current develops a greater voltage drop across collector resistor 66 and reduces the DC voltage at collector 63 (and cathode 25). Conversely, a decrease in the resistance of potentiometer 70 increases the voltage at emitter 61, reducing the relative base-emitter voltage and decreasing collector current. The smaller voltage drop across resistor 66 increases the DC voltage at collector 63 and cathode 25.
Thus, increasing the resistanceof potentiometer 70 produces proportionate simultaneous reduction of the DC voltage applied to cathode 25 and the voltage gain of amplifier 17, whereas decreasing the resistance of potentiometer 70 produces proportionate simultaneous increase of the DC voltage and signal gain. As mentioned above, amplifiers 15 and 16 are identical to amplifier 17. In practice only two of the three output amplifiers require adjustment to achieve color temperature setup. However, greater flexibility and optimum use of amplifier signal handling capability is realized if all three output amplifiers are adjustable.
As previously mentioned capacities associated with transistor 60, cathode 25 and corresponding interconnections (such as those used to couple collector 63 to cathode 25) are effectively in parallel with collector load resistor 66 forming a partially reactive "coupling network" which exhibits a frequency characteristic (bandwidth) affecting signals coupled therethrough. In practice, the other coupling networks have identical bandwidths and affect their signals in an equal manner. The setup control adjustments of the present invention do not change the characteristics of these coupling networks and the uniformity of signal coupling for the different color signals is preserved. In contrast, conventional adjustment circuitry (whether variable collector load or voltage divider) place variable impedances within these couplings. The varied adjustments of these impedances to effect color temperature control adjustment disturb the bandwidth characteristics of the coupling networks causing differential variations in the individual color video signals.
What has been shown is an RGB CRT drive system which includes output amplifiers each having a single control which simultaneously achieves changes of the DC output voltage and signal gain of the amplifier in a predetermined relationship. The bandwidths of all three output amplifiers and their associated coupling networks remain substantially undisturbed by these control adjustments during CRT color temperature setup.
While particular embodiments of the invention have been shown and described, it will be obvious to those skilled in the art that changes and modifications may be made without departing from the invention in its broader aspects, and, therefore, the aim in the appended claims is to cover all such changes and modifications as fall within the true spirit and scope of the invention.
The chassis is a complex and a big combination of multi boards with many discretes and ASIC's.
On the left side the small signal boards with all IF / Video / luminance / chrominance / remote controls.
On the right side all large signal boards with synchronized power supply and line deflection and EHT and frame deflection and synchronization unit.
Left side in the cabinet upside the audio stages and power amplifier.
On bottom of the aforementioned the tuning drawbar.
The chassis is capable of multistandard and multi sound with stereo and spatial stereo feature.
ICS USED:
TDA1038
TCA660B Contrast/Saturation and Brightness Control Circuit
TDA2541 IF VIDEO
LM324 AMP OP
TDA1026 SYNCHRO
TDA2581 SUPPLY
TBA120T SOUND IF
TCA640 Chrominance Amplifier for SECAM or PAL/SECAM Decoders
TCA650 Chrominance Demodulator for Secam or PAL/Secam Decoders
TCA740 D.c. Treble Amd Bass Stereo Control Circuit (1980)
TCA730 15V 35mA D.C. volume and balance stereo control circuit
PHILIPS 26P1195 MULTISTANDARD CHASSIS TVC11 Dual-standard SECAM/PAL color TV receiver with automatic control of operating mode:
1. In a dual-standard color television receiver having multiple operating modes and subject to alternative reception of (a) composite color television signals inclusive of a chrominance component encoded in a SECAM format and (b) composite color television signals inclusive of a chrominance component encoded in a PAL format; said SECAM-encoded chrominance component being accompanied by lead-in oscillations of a first subcarrier frequency during a terminal segment of the blanking portion of alternate active line intervals, and lead-in oscillations of a second subcarrier frequency during a similarly timed terminal segment of the blanking portion of the intervening active line intervals; said PAL-encoded chrominance component being accompanied by bursts of reference oscillations of a third subcarrier frequency, said bursts occupying a period of the blanking portion of each active line interval which corresponds in timing to an initial part of each of said terminal segments; apparatus comprising:
an FM detector responsive to the received signals;
means for generating line rate pulses having leading edges delayed relative to the beginning of said initial part of said terminal segments and trailing edges substantially coinciding with the termination of said terminal segments;
means, responsive to an output of said FM detector and to said line rate pulses, for developing a control signal indicative of the relationship between the amplitudes of (a) the output developed by said FM detector during alternate appearances of said line-rate pulses and (b) the output developed by said FM detector during the intervening appearances of said line rate pulses;
means, responsive to said control signal, for controlling the operating mode of said dual-standard color television receiver.
. 2. Apparatus in accordance with claim 1,
wherein said FM detector is subject to operation in either a first state with center frequency tuning corresponding to said first subcarrier frequency, or a second state with center frequency tuning corresponding to said second subcarrier frequency;
wherein said apparatus also includes a triggered flip-flop circuit for providing, when enabled, a pair of half line rate wave outputs of mutually opposite phase; and means for controlling the operating state of said FM detector such that said FM detector operates in respectively different ones of said states during the image portions of successive active line intervals but operates in only said first state during the blanking portion of each active line interval; and
wherein said control signal developing means includes first sampling means, coupled to receive an output of said FM detector, and responsive to said line rate pulses and to one of said pair of half line rate wave outputs, for sampling the output of said FM detector during a restricted portion of alternate ones of the terminal segments of the blanking portions of active line intervals, with initiation of said restricted portions substantially coinciding with said delayed leading edges and termination thereof substantially coinciding with said trailing edges; second sampling means, coupled to receive an output of said FM detector, and responsive to said line rate pulses and to the other of said pair of half line rate wave outputs, for sampling the output of said FM detector during a restricted portion of the intervening ones of the terminal segments of the blanking portions of active line intervals, with initiation of said restricted portions substantially coinciding with said delayed leading edges and termination thereof substantially coinciding with said trailing edges; and a voltage comparator responsive to the outputs of said first and second sampling means for producing said control signal.
3. Apparatus in accordance with claim 2 also including:
means, responsive to an output of said FM detector, for forming a quasi-PAL chrominance component;
a path for received signals bypassing said FM detector and said quasi-PAL chrominance component forming means; and
a PAL chrominance component decoder; and
wherein said receiver operating mode controlling means comprises switching means for supplying the output of said quasi-PAL chrominance component forming means to said decoder when in a first switching state and for supplying the output of said bypassing path to said decoder when in a second switching state; and
wherein the control signal produced by said comparator causes said switching means to assume said first switching state only when the output level of a given one of said sampling means significantly exceeds the output level of the other of said sampling means.
.
4. Apparatus in accordance with claim 3 also including a source of sandcastle pulses inclusive of a horizontal blanking pulse component and a burst gating pulse component; a sandcastle pulse decoder responsive to said sandcastle pulses for separately deriving therefrom horizontal blanking pulses and burst gating pulses, said horizontal blanking pulses having trailing edges substantially coinciding with the termination of said terminal segments, and said burst gating pulses having leading edges occurring before said initial part of said terminal segments, and trailing edges occurring subsequent to said initial part of said terminal segments but prior to the termination of said terminal segments; and means for rendering said line rate pulse generating means responsive to said horizontal blanking pulses and said burst gating pulses derived by said sandcastle pulse decoder. 5. Apparatus in accordance with claim 4 wherein said quasi-PAL chrominance component forming means includes means responsive to said burst gating pulses derived by said sandcastle pulse decoder for forming bursts of reference oscillations to accompany said quasi-PAL crhominance component. . 6. Apparatus in accordance with claim 5 wherein said line rate pulse generating means includes means for developing a train of pulses having leading edges substantially coinciding with the leading edges of said burst gating pulses derived by said sandcastle pulse decoder and trailing edges substantially coinciding with the trailing edges of said horizontal blanking pulses derived by sandcastle pulse decoder, delay means responsive to said train of pulses for slowing the rise time of the leading edges of said train of pulses, and a threshold device responsive to the output of said delay means for developing said line rate pulses having said delayed leading edges. 7. Apparatus in accordance with claim 3, wherein said FM detector operating state controlling means is responsive to one of said pair of half line rate wave outputs and to the horizontal blanking pulses derived by said sandcastle pulse decoder; said apparatus also including means, responsive to the outputs of said first and second sampling means, for disabling said flip-flop circuit when the output level of said other of said sampling means significantly exceeds the output level of said given one of said sampling means. 8. Apparatus in accordance with claim 1 wherein the delay of said delayed leading edges relative to the beginning of the initial part of said terminal segments is approximately one microsecond.
an FM detector responsive to the received signals;
means for generating line rate pulses having leading edges delayed relative to the beginning of said initial part of said terminal segments and trailing edges substantially coinciding with the termination of said terminal segments;
means, responsive to an output of said FM detector and to said line rate pulses, for developing a control signal indicative of the relationship between the amplitudes of (a) the output developed by said FM detector during alternate appearances of said line-rate pulses and (b) the output developed by said FM detector during the intervening appearances of said line rate pulses;
means, responsive to said control signal, for controlling the operating mode of said dual-standard color television receiver.
. 2. Apparatus in accordance with claim 1,
wherein said FM detector is subject to operation in either a first state with center frequency tuning corresponding to said first subcarrier frequency, or a second state with center frequency tuning corresponding to said second subcarrier frequency;
wherein said apparatus also includes a triggered flip-flop circuit for providing, when enabled, a pair of half line rate wave outputs of mutually opposite phase; and means for controlling the operating state of said FM detector such that said FM detector operates in respectively different ones of said states during the image portions of successive active line intervals but operates in only said first state during the blanking portion of each active line interval; and
wherein said control signal developing means includes first sampling means, coupled to receive an output of said FM detector, and responsive to said line rate pulses and to one of said pair of half line rate wave outputs, for sampling the output of said FM detector during a restricted portion of alternate ones of the terminal segments of the blanking portions of active line intervals, with initiation of said restricted portions substantially coinciding with said delayed leading edges and termination thereof substantially coinciding with said trailing edges; second sampling means, coupled to receive an output of said FM detector, and responsive to said line rate pulses and to the other of said pair of half line rate wave outputs, for sampling the output of said FM detector during a restricted portion of the intervening ones of the terminal segments of the blanking portions of active line intervals, with initiation of said restricted portions substantially coinciding with said delayed leading edges and termination thereof substantially coinciding with said trailing edges; and a voltage comparator responsive to the outputs of said first and second sampling means for producing said control signal.
3. Apparatus in accordance with claim 2 also including:
means, responsive to an output of said FM detector, for forming a quasi-PAL chrominance component;
a path for received signals bypassing said FM detector and said quasi-PAL chrominance component forming means; and
a PAL chrominance component decoder; and
wherein said receiver operating mode controlling means comprises switching means for supplying the output of said quasi-PAL chrominance component forming means to said decoder when in a first switching state and for supplying the output of said bypassing path to said decoder when in a second switching state; and wherein the control signal produced by said comparator causes said switching means to assume said first switching state only when the output level of a given one of said sampling means significantly exceeds the output level of the other of said sampling means.
.
Description:
The present invention relates generally to operating mode control apparatus for a dual-standard SECAM-PAL color TV receiver, and particularly to novel apparatus for reliably effecting automatic control of the operating mode of such a receiver in response to parameters of the received signals. In such use of a single FM detector for sequential demodulation of the respective SECAM subcarriers, an identification system is required for identification and correction of an incorrect mode of line-by-line switching of the detector's center frequency tuning. One source of information for such identification purposes is found in the lead-in bursts of oscillations which precede the image portion of each active line interval (with a lead-in burst at the R-Y resting frequency preceding the image portion of an active line interval that conveys R-Y image information, and with a lead-in burst at the B-Y resting frequency preceding the image portion of an active line interval that conveys B-Y image information). In the identification system disclosed in U.S. Pat. No. 4,240,102-Groeneweg, a flip-flop develops half line rate control waves for use in switching the center frequency tuning of the detector employed for demodulating received SECAM signals. When the phasing of the flip-flop output is correct, the detector is provided with center frequency tuning (4.40625 MHz.) appropriate to demodulation of the R-Y modulated subcarrier during the image portion of an R-Y line interval of the SECAM signal, and tuning (4.250 MHz.) appropriate for demodulation of the B-Y modulated subcarrier during the image portion of a B-Y line interval of the SECAM signal. Through the supplemental association of line rate pulses in the tuning control, however, the timing of the changes in detector center frequency tuning is so controlled that during the lead-in bursts preceding the image portions of both of such R-Y and B-Y line intervals, the detector center frequency tuning is always the same (e.g., tuned for a center frequency corresponding to the R-Y subcarrier resting frequency).
As disclosed in the aforesaid Groeneweg patent for instances of use of the above-described identification system in a dual-standard SECAM/PAL color TV receiver, information suitable for automatically controlling the operating mode of the dual-standard receiver can also be derived by comparison of the outputs of the respective sample-and-hold circuits. When SECAM signals are being received under conditions of correct phasing for the flip-flop, there will be a significant difference of a predetermined sense between the outputs of the respective sample-and-hold circuits. In the arrangement of the aforesaid Groeneweg patent, the receiver is switched into a SECAM operating mode (with the quasi-PAL output of the SECAM-PAL transcoder fed to the receiver's PAL decoder apparatus) only when such a relationship between the sample-and-hold circuit outputs is obtained. In all other instances (i.e., when the outputs are substantially equal, or when a difference of the opposite sense is obtained), the receiver is maintained in a PAL operating mode (with the PAL decoder receiving its input from a signal path bypassing the SECAM-PAL transcoder).
Since the frequency of the PAL burst remains the same in successive line intervals, one would expect the outputs of two sample-and-hold circuits to be the same during reception of a PAL signal, whereby false switching to a SECAM operating mode could not occur during such signal reception. The present invention is based, however, on a recognition that certain transient conditions can exist in the operation of the FM detector during PAL signal reception that may lead to false switching to a SECAM operating mode in the above-described mode control arrangement, unless a proper choice is made of the sampling interval location within the "backporch" region of the horizontal blanking period.
Pursuant to the principles of the present invention, the initiation of the sampling intervals for the sample-and-hold circuits of the above-described arrangement is desirably delayed relative to the beginning of burst appearance so that the periods of significant transient difference are excluded from the sampling intervals. In order that the initiation delay does not shorten the sampling interval to a degree compromising reliability of level detection for SECAM identification purposes, it is further recognized as desirable that the sampling interval should extend for the remainder of the period occupied by lead-in oscillations during SECAM signal reception, wherefore the termination of the sampling interval is desirably in substantial coincidence with the end of the horizontal blanking interval.
In a desirable form of implementation of a SECAM-PAL transcoder incorporating an identification system pursuant to the principles of the present invention, major elements of the transcoder are realized in integrated circuit (IC) form on a common substrate. In such IC realization, a useful input to a terminal of the IC chip is a "sandcastle" pulse train. A conventional "sandcastle" pulse form, provided by many currently available horizontal processor IC's (e.g., Philips TDA 2593), is a two level pulse in which a burst gating pulse is superimposed upon a horizontal blanking pulse. Typical timing for the burst gating pulse locates it in the "backporch" region of the horizontal blanking pulse (i.e., subsequent to the horizontal sync interval), with the leading edge occurring slightly before the beginning of the interval occupied by standard PAL bursts (and the similarly timed beginning of the interval occupied by SECAM lead-in oscillations), and with the trailing edge occurring subsequent to the end of the PAL burst interval but prior to the end of the horizontal blanking interval (and thus prior to the end of the SECAM lead-in interval). In accordance with an illustrative embodiment of the present invention, the development of a suitable line rate sampling control pulse for the above-described identification and mode control system is achieved by circuitry responding to the respective components of a sandcastle pulse of the aforementioned type.
PHILIPS 26P1195 MULTISTANDARD Receiver tuning circuit PHILIPS CHASSIS TVC11
A receiver tuning circuit in which without operation of extra switches a change-over can be made from tuning by means of a continuously varying tuning voltage to tuning by means of one of a number of adjusted tuning voltages by using a capacitor controlled by an automatic tuning correction current source circuit for obtaining said voltage, and an automatic switch for applying the desired tuning voltages to this capacitor.
1. A receiver tuning circuit comprising a tuning section having a tuning input, a capacitor means coupled to said tuning input for applying a tuning voltage thereto, a controllable current source coupled to said capacitor, a tuning correction signal detector means coupled between said tuning section and said current source for applying an automatic tuning correction signal to said capacit
or means through said current source, and means for immediately tuning said tuning section to a selected frequency independently of the previous voltage on said capacitor comprising a first switch coupled to said capacitor and an operating device means for controlling said switch for an operating period, said operating device including a memory means for storing the last adjusted state of said operating device, at least one potentiometer and a generator means for effecting that a signal from said potentiometer is applied to said capacitor through said switch upon operation of said operating device, and said first switch including a first time constant circuit means coupled to said generator for maintaining said switch in an on position for a selected period of time independent of said operating period.
2. A receiver tuning circuit as claimed in claim 1, wherein said switch comprises a current source which can be influenced by an operating signal, said source being coupled to two parallel branches the first of which includes a transistor having an emitter coupled to said current source, a base coupled to an input of the switch, and a collector, a current mirror circuit having an input coupled to said collector and an output, the second branch including a pair of series connected diodes coupled to the current source and to said output of the current mirror circuit, and output of the switch being coupled to the pair of diodes.
3. A circuit as claimed in claim 1, further comprising a manually operable second switch means for obtaining a continuous coupling between said potentiometer means and said capacitor.
4. A circuit as claimed in claim 1 further comprising a supply circuit means for obtaining a desired tuning voltage, said memory means being independent of said supply circuit, said first switch further comprising a second time constant circuit means coupled to said supply circuit means for temporarily applying a tuning voltage determined by the potentiometer to said capacitor when the supply voltage is switched on.
5. A receiver tuning circuit comprising a tuning section having a tuning input, a capacitor means coupled to said tuning input for applying a tuning voltage thereto, a controllable current source coupled to said capacitor, a tuning correction signal detector means coupled between said tuning section and said current source for applying an automatic tuning correction signal to said capacitor through said current source, means coupled to said capacitor for immediately tuning said tuning section to a selected frequency independently of the previous voltage on said capacitor, a memory means coupled to said immediate tuning means for storing a tuning voltage corresponding to a selected frequency and signal amplitude detector means coupled to said immediate tuning means for effecting that said tuning voltage stored in said memory means is applied to said capacitor through said immediate tuning means when said signal amplitude goes below a selected value.
Description:
The invention relates to a receiver tuning circuit having a tuning section tunable by means of a tuning voltage obtained from a capacitor whose charge can be changed by means of a current source circuit controllable by a
t least an automatic tuning correction signal, while furthermore a desired tuning voltage can temporarily be applied to said capacitor with the aid of a switch controllable by an operating device so as to make it possible to immediately tune to a desired frequency independently of the previous charge condition of said capacitor.
A tuning circuit of the kind described above is known from German Offenlegungsschrift No. 2,025,369 in which the said capacitor is optionally connected to a tuning potentiometer by means of a push-button switch for applying a voltage determined by said potentiometer to said capacitor as long as the push-button switch is operated, whereafter a tuning frequency thus selected is corrected with the automatic tuning correction signal through the current source circuit and the charge of said capacitor.
It is an object of the invention to enhance the comfort of operation of such a tuning circuit.
To this end a tuning circuit of the kind described in the preamble is characterized in that the operating device includes a memory for storing the last adjusted state of said operating device, and a signal generator which upon operation of the operating device applies a signal to an output thereof, which output is coupled to a time-constant circuit coupled to said switch for maintaining said switch switched on for a period determined by the time-constant circuit independently of the operating duration of the operating device.
Due to the step according to the invention it is possible at any moment to ascertain, by means of the state of the memory, the last operating action of the operating device, maintaining the advantage of a temporary tuning voltage supply to the capacitor so that subsequently other functions such as, for example, a tuning correction device or a search tuning device can become active on said capacitor through the current source circuit.
The invention will now be described with reference to the drawing.
FIG. 1 shows by way of a block-schematic diagram a receiver tuning circuit according to the invention;
FIG. 2 shows by way of a principle circuit diagram a possible embodiment of part of the receiver tuning circuit according to the invention.
In FIG. 1 a tuning section 1 has an input 3 to which a received RF signal is applied and an output 5 from which an IF signal is obtained. This IF signal is applied to an input 7 of an IF amplifier 9 and derived in an amplified form fr
om an output 11 thereof and applied to an input 13 of a tuning correction signal detector 15 and an input 17 of a signal amplitude detector 19.
Furthermore, the tuning section 1 has an input 21 which receives a tuning voltage from a capacitor 23. The charge of the capacitor 23 can be changed with the aid of a current source circuit 25 for which purpose an output 27 thereof is connected to the capacitor 23 whose other end is connected to ground.
An input 29 of the current source circuit 25 is controlled by a tuning correction signal originating from an output 31 of the tuning correction signal detector 15. This correction signal can be rendered inactive with the aid of a switch-off device 33 incorporated in the connection between the output 31 and the input 29, and with the aid of signals applied to an input 35 or 37 thereof.
For this purpose the input 35 of the switch-off device 33 is connected to an output 39 of a station finder 41 two outputs 43, 45 of which are connected to inputs 47, 49 of the current source circuit 25. Thus, the station finder 41 can continuously bring about a charge or discharge of the capacitor 23 when the automatic tuning correction is switched off so that the tuning section 1 is continuously detuned. When a station is found, a signal is produced at the output 31 of the tuning correction signal detector 15, which signal causes stop signal at an input 55 of the station finder through a polarity correction circuit 51 and a delay circuit 53, and this for a certain period, for example, 1.5 seconds so that station finding is temporarily discontinued and the automatic tuning correction is activated. As a result, tuning is effected immediately and correctly at the frequency of the received station. If this station is not desired, further station finding can be continued after 1.5 seconds.
The capacitor 23 providing the tuning voltage for the tuning section 1 may be controlled not only by the current source circuit 25, but also by an output 57 of a switch 59 an input 61 of which is connected to an output 63 of an operating device 65.
A voltage originating from one of a plurality of tuning potentiometers 67, 69, 71 can be temporarily applied to the capacitor 23 with the aid of the operating device 65. When the device 65 is operated a signal is obtained to that end from a signal generator 73. This signal is applied through an output 75 of the operating device to an input 77 of a time-constant circuit 79. The time constant circuit 79 is coupled to the switch 59 and closes it for a certain time so that the capacitor 23 assumes the desired voltage of a selected potentiometer 67, 69 or 71.
The operating device 65 has a memory which is symbolically shown in the figure as a block 81. This memory 81 ensures that it can always be seen which potentiometers 67, 69 or 71 is interconnected to the output 63 of the operating device 65, while due to the action of the time-constant circuit 79 the voltage originating from this potentiometer is not continuously present at the capacitor 23. The said memory 81 may be either a mechanical or an electrical memory. When using a mechanical memory, the signal generator 73 may be an AFC switch which is present on many operating devices. When using an electrical memory, as is common practice with touch controls in the operating device 65, any change of state of this memory may be converted in a simple manner into a signal applied to the output 75.
The switch 59 has an output 83 which applies a signal to the input 37 of the switch-off device 33. This signal renders the automatic tuning correction inactive as long as the switch 59 is closed, as is the case when a tuning voltage is applied to the capacitor 23 with the aid of the operating device 65. The tuning correction is active again immediately when the switch 59 is open so that tuning is effected immediately and correctly when a selected station is received.
To be able to adjust the potentiometers 67, 69 or 71, easily, a switch 85, which can be operated manually, is connected to a further input 87 of the switch 59 which can be maintained closed with the aid of the manually operated switch 85 as long as is desired for adjustment.
Coupled to the switch 59 is a further time-constant circuit 89 which has an input 91 connected to an output 93 of a supply circuit 95. Thus, whenever the receiver is switched on, the switch 59 is maintained closed for some time so that firstly the station to which the operating device 65 is adjusted is tuned to, even if the station finder 41 were switched on. In that case the operating device 65 must have, for example, a mechanical memory 81, which is independent of the supply voltage, in order to maintain its adjustment also when the supply voltage is switched off.
Furthermore, the switch 59 has an input 97 which is connected to an output 99 of the signal amplitude detector 19. When the signal received by the receiver becomes too weak, the switch 59 can be closed via this path so that tuning to a frequency selected by the operating device 65 is maintained and is stil present when the received signal becomes stronger again. A further possibility, which may be particularly attractive for motorcar radios, is to incorporate a switch which can be operated in this manner between the capacitor and an output of a memory which can be coupled to that capacitor. When the field strength is sufficient, this memory may be written in with the voltage on the capacitor and when the field strength is insufficient, an output of this memory may be coupled to the capacitor for transferring the memory voltage to the capacitor. This memory may be, for example, a motor adjusting a potentiometer and operated with the aid of a control system. When the supply voltage drops out, the last adjusted state of the potentiometer is maintained.
The described tuning circuit may immediately change over from, for example, a search tuning state to a state tuned to a desired station without operating extra switches and only by operating the relevant operating members.
It will be evident that the switch tuning may be omitted, if desired.
FIG. 2 shows a possible embodiment of the switch 59 and, coupled thereto, the time-constant circuits 79 and 89 of the receiver tuning circuit of FIG. 1. The inputs and outputs have the same reference numerals as the corresponding inputs and outputs in FIG. 1.
The input 61 of the switch 59 is connected to the base of a npn transistor 201. The emitter of this transistor 201 is connected through a diode 203 to the collector of an npn transistor 205 arranged as a current source whose emitter is connected to the output 83 and is furthermore connected to ground through a resistor 207.
The collector of the transistor 201 is connected through a diode 209 to the input 91 to which the supply voltage is applied. The diode 209 shunts the base-emitter path of a pnp transistor 211 which together with the diode 209 constitutes a current mirror circuit. The collector of the transistor 211 allows a
current to flow through a series arrangement of two diodes 215, 217, which current has substantially the same intensity as the current flowing through the diode 203. Furthermore, the diode 217 is connected to the collector of the transistor 205, while the junction of the collector of the transistor 205 and the diode 215 is connected to the output 57.
The base of the transistor 205 is connected to a tap on a potential divider 219, 221 between the supply voltage and ground. This potential divider will raise the voltage at the base of the transistor 205 to such an extent that it produces a current, which is further determined by the emitter resistor 207, equally distributed over the collector branches with the diode 203 and the transistor 201 and with the diodes 217 and 215, respectively. When the circuit is designed in a integrated form, it can be achieved in a simple manner that the output 57 will always assume the same voltage as the input 61. Since the output 57 is connected to the capacitor 23, both a discharge and a charge of this capacitor 23 is possible. Charging is effected through the transistor 211 and discharging is effected through the diodes 215, 217. The circuit is independent of temperature influences. The diode 203 and consequently the diode 217 are provided to prevent a too large voltage difference at the base-emitter junction of the transistor 201.
The current source 205 can be turned off by connecting the base of transistor 205 to ground with the aid of a npn transistor 223 connected across the resistor 221. This is effected when the base of this transistor receives a voltage from a potential divider comprising three resistors 225, 227, 229. However, when the base of the transistor 223 receives a low voltage through the input 87 or the input 97, the transistors 223 is cut off and the transistor 205 conducts so that the switch 59 is closed.
The voltage at the base of the transistor 223 remains low for some time after switching on the supply voltage because a capacitor 231, which is connected to the junction between the resistors 225 and 227, must firstly be charged. Thus, the switch 59 is closed during that period.
Furthermore, the voltage at the base of the transistor 223 may be decreased by discharging the capacitor 231 through a resistor 233 to the input 77 when this input is earthed for a moment during operating device 65. The voltage at the capacitor 231 will subsequently increase in accordance with a certain time constant and after a certain time the transistor 223 conducts again and the switch 59, which was closed when the transistor 223 was cut off, will be open again.
The input 97 is interconnected to the input 87 so that the transistor 223 is also cut off and the switch 59 starts to conduct when the voltage at the input 97 becomes low upon a drop-out of a transmitter signal.
The switch 59 in this embodiment also acts as an amplifier so that the adjustments of the tuning potentiometer 67, 69 or 71 do not have any influence on the rate at which the charge of the capacitor 23 is changed.
A tuning circuit of the kind described above is known from German Offenlegungsschrift No. 2,025,369 in which the said capacitor is optionally connected to a tuning potentiometer by means of a push-button switch for applying a voltage determined by said potentiometer to said capacitor as long as the push-button switch is operated, whereafter a tuning frequency thus selected is corrected with the automatic tuning correction signal through the current source circuit and the charge of said capacitor.
It is an object of the invention to enhance the comfort of operation of such a tuning circuit.
Due to the step according to the invention it is possible at any moment to ascertain, by means of the state of the memory, the last operating action of the operating device, maintaining the advantage of a temporary tuning voltage supply to the capacitor so that subsequently other functions such as, for example, a tuning correction device or a search tuning device can become active on said capacitor through the current source circuit.
The invention will now be described with reference to the drawing.
FIG. 1 shows by way of a block-schematic diagram a receiver tuning circuit according to the invention;
FIG. 2 shows by way of a principle circuit diagram a possible embodiment of part of the receiver tuning circuit according to the invention.
In FIG. 1 a tuning section 1 has an input 3 to which a received RF signal is applied and an output 5 from which an IF signal is obtained. This IF signal is applied to an input 7 of an IF amplifier 9 and derived in an amplified form fr
om an output 11 thereof and applied to an input 13 of a tuning correction signal detector 15 and an input 17 of a signal amplitude detector 19. Furthermore, the tuning section 1 has an input 21 which receives a tuning voltage from a capacitor 23. The charge of the capacitor 23 can be changed with the aid of a current source circuit 25 for which purpose an output 27 thereof is connected to the capacitor 23 whose other end is connected to ground.
An input 29 of the current source circuit 25 is controlled by a tuning correction signal originating from an output 31 of the tuning correction signal detector 15. This correction signal can be rendered inactive with the aid of a switch-off device 33 incorporated in the connection between the output 31 and the input 29, and with the aid of signals applied to an input 35 or 37 thereof.
For this purpose the input 35 of the switch-off device 33 is connected to an output 39 of a station finder 41 two outputs 43, 45 of which are connected to inputs 47, 49 of the current source circuit 25. Thus, the station finder 41 can continuously bring about a charge or discharge of the capacitor 23 when the automatic tuning correction is switched off so that the tuning section 1 is continuously detuned. When a station is found, a signal is produced at the output 31 of the tuning correction signal detector 15, which signal causes stop signal at an input 55 of the station finder through a polarity correction circuit 51 and a delay circuit 53, and this for a certain period, for example, 1.5 seconds so that station finding is temporarily discontinued and the automatic tuning correction is activated. As a result, tuning is effected immediately and correctly at the frequency of the received station. If this station is not desired, further station finding can be continued after 1.5 seconds.
The capacitor 23 providing the tuning voltage for the tuning section 1 may be controlled not only by the current source circuit 25, but also by an output 57 of a switch 59 an input 61 of which is connected to an output 63 of an operating device 65.
A voltage originating from one of a plurality of tuning potentiometers 67, 69, 71 can be temporarily applied to the capacitor 23 with the aid of the operating device 65. When the device 65 is operated a signal is obtained to that end from a signal generator 73. This signal is applied through an output 75 of the operating device to an input 77 of a time-constant circuit 79. The time constant circuit 79 is coupled to the switch 59 and closes it for a certain time so that the capacitor 23 assumes the desired voltage of a selected potentiometer 67, 69 or 71.
The operating device 65 has a memory which is symbolically shown in the figure as a block 81. This memory 81 ensures that it can always be seen which potentiometers 67, 69 or 71 is interconnected to the output 63 of the operating device 65, while due to the action of the time-constant circuit 79 the voltage originating from this potentiometer is not continuously present at the capacitor 23. The said memory 81 may be either a mechanical or an electrical memory. When using a mechanical memory, the signal generator 73 may be an AFC switch which is present on many operating devices. When using an electrical memory, as is common practice with touch controls in the operating device 65, any change of state of this memory may be converted in a simple manner into a signal applied to the output 75.
The switch 59 has an output 83 which applies a signal to the input 37 of the switch-off device 33. This signal renders the automatic tuning correction inactive as long as the switch 59 is closed, as is the case when a tuning voltage is applied to the capacitor 23 with the aid of the operating device 65. The tuning correction is active again immediately when the switch 59 is open so that tuning is effected immediately and correctly when a selected station is received.
To be able to adjust the potentiometers 67, 69 or 71, easily, a switch 85, which can be operated manually, is connected to a further input 87 of the switch 59 which can be maintained closed with the aid of the manually operated switch 85 as long as is desired for adjustment.
Coupled to the switch 59 is a further time-constant circuit 89 which has an input 91 connected to an output 93 of a supply circuit 95. Thus, whenever the receiver is switched on, the switch 59 is maintained closed for some time so that firstly the station to which the operating device 65 is adjusted is tuned to, even if the station finder 41 were switched on. In that case the operating device 65 must have, for example, a mechanical memory 81, which is independent of the supply voltage, in order to maintain its adjustment also when the supply voltage is switched off.
The described tuning circuit may immediately change over from, for example, a search tuning state to a state tuned to a desired station without operating extra switches and only by operating the relevant operating members.
It will be evident that the switch tuning may be omitted, if desired.
FIG. 2 shows a possible embodiment of the switch 59 and, coupled thereto, the time-constant circuits 79 and 89 of the receiver tuning circuit of FIG. 1. The inputs and outputs have the same reference numerals as the corresponding inputs and outputs in FIG. 1.
The input 61 of the switch 59 is connected to the base of a npn transistor 201. The emitter of this transistor 201 is connected through a diode 203 to the collector of an npn transistor 205 arranged as a current source whose emitter is connected to the output 83 and is furthermore connected to ground through a resistor 207.
The collector of the transistor 201 is connected through a diode 209 to the input 91 to which the supply voltage is applied. The diode 209 shunts the base-emitter path of a pnp transistor 211 which together with the diode 209 constitutes a current mirror circuit. The collector of the transistor 211 allows a
current to flow through a series arrangement of two diodes 215, 217, which current has substantially the same intensity as the current flowing through the diode 203. Furthermore, the diode 217 is connected to the collector of the transistor 205, while the junction of the collector of the transistor 205 and the diode 215 is connected to the output 57. The base of the transistor 205 is connected to a tap on a potential divider 219, 221 between the supply voltage and ground. This potential divider will raise the voltage at the base of the transistor 205 to such an extent that it produces a current, which is further determined by the emitter resistor 207, equally distributed over the collector branches with the diode 203 and the transistor 201 and with the diodes 217 and 215, respectively. When the circuit is designed in a integrated form, it can be achieved in a simple manner that the output 57 will always assume the same voltage as the input 61. Since the output 57 is connected to the capacitor 23, both a discharge and a charge of this capacitor 23 is possible. Charging is effected through the transistor 211 and discharging is effected through the diodes 215, 217. The circuit is independent of temperature influences. The diode 203 and consequently the diode 217 are provided to prevent a too large voltage difference at the base-emitter junction of the transistor 201.
The current source 205 can be turned off by connecting the base of transistor 205 to ground with the aid of a npn transistor 223 connected across the resistor 221. This is effected when the base of this transistor receives a voltage from a potential divider comprising three resistors 225, 227, 229. However, when the base of the transistor 223 receives a low voltage through the input 87 or the input 97, the transistors 223 is cut off and the transistor 205 conducts so that the switch 59 is closed.
The voltage at the base of the transistor 223 remains low for some time after switching on the supply voltage because a capacitor 231, which is connected to the junction between the resistors 225 and 227, must firstly be charged. Thus, the switch 59 is closed during that period.
Furthermore, the voltage at the base of the transistor 223 may be decreased by discharging the capacitor 231 through a resistor 233 to the input 77 when this input is earthed for a moment during operating device 65. The voltage at the capacitor 231 will subsequently increase in accordance with a certain time constant and after a certain time the transistor 223 conducts again and the switch 59, which was closed when the transistor 223 was cut off, will be open again.
The input 97 is interconnected to the input 87 so that the transistor 223 is also cut off and the switch 59 starts to conduct when the voltage at the input 97 becomes low upon a drop-out of a transmitter signal.
The switch 59 in this embodiment also acts as an amplifier so that the adjustments of the tuning potentiometer 67, 69 or 71 do not have any influence on the rate at which the charge of the capacitor 23 is changed.
PHILIPS 26P1195 MULTISTANDARD CHASSIS TVC11 Line synch Switched Mode Power Supply with Line deflection output Transistor Drive Circuit:
1. An electrical circuit arrangement for a picture display device operating at a given line scanning frequency, comprising a source of unidirectional voltage, an inductor, first switching transistor means for periodically energizing said inductor at said scanning frequency with current from said source, an electrical load circuit coupled to said inductor and having applied thereto a voltage as determined by the ratio of the ON and OFF periods of said transistor, means for maintaining the voltage across said load circuit at a given value comprising means for comparing the voltage of said load circuit with a reference voltage, means responsive to departures of the value of the load circuit voltage from the value of said reference voltage for varying the conduction ratio of the ON and OFF periods of said transistor thereby to stabilize said load circuit voltage at the given value, a line deflection coil system for said picture display device, means for energizing said line deflection coil system from said load voltage circuit means, means for periodically interrupting the energization of said line deflection coil comprising second switching means and means coupled to said inductor for deriving therefrom a switching current in synchronism with the energization periods of said transistor and applying said switching current to said switching means thereby to actuate the same, and means coupled to said switching means and to said load voltage circuit for producing a voltage for energizing said 2. A circuit as claimed in claim 1 wherein the duty cycle of said switching 3. A circuit as claimed in claim 1 further comprising an efficiency first 4.
A circuit as claimed in claim 3 further comprising at least a second diode coupled to said deriving means and to ground, and being poled to 5. A circuit as claimed in claim 1 wherein said second switching means comprises a second transistor coupled to said deriving means to conduct simultaneously with said first transistor, and further comprising a coil coupled between said driving means and said second transistor and a third diode shunt coupled to said coil and being poled to conduct when said 6. A circuit as claimed in claim 1 further comprising a horizontal oscillator coupled to said first transistor, said oscillator being the 7. A circuit as claimed in claim 1 further comprising means coupled to said inductor for deriving filament voltage for said display device.
Description:
In the circuit arrangement according to the mentioned German "Auslegeschrift" the frequency of the load variations or a harmonic thereof is chosen as the frequency for the switching voltage. Particularly when the load fed by the chopper is the line deflection circuit of a picture display device, wherein thus the impedance of the load varies in the rhythm of the line frequency, the frequency of the switching voltage is equal to or is a multiple of the line frequency.
It is to be noted that the chopper need not necessarily be formed as that in the mentioned German "Auslegeschrift." In fact, it is known from literature that the efficiency diode and the coil may be exchanged. It is alternatively possible for the coil to be provided at the first terminal of the input voltage whilst the switching transistor is arranged between the other end and the second terminal of the input voltage. The efficiency diode is then provided between the junction of said end and the switching transistor and the load. It may be recognized that for all these modifications a voltage is present across the connections of the coil which voltage has the same frequency and the same shape as the pulsatory switching voltage. The control voltage of a line deflection circuit is a pulsatory voltage which causes the line output transistor to be saturates and cut off alternately. The invention is based on the recognition that the voltage present across the connections of the coil is suitable to function as such a control voltage and that the coil constitutes the primary of a transformer. To this end the circuit arrangement according to the invention is characterized in that a secondary winding of the transformer drives the switching element which applies a line deflection current to line deflection coils and by which the voltage for the final anode of a picture display tube which forms part of the picture display device is generated, and that the ratio between the period during which the switching transistor is saturated and the entire period, i.e., the switching transistor duty cycle is between 0.3 and 0.7 during normal operation.As will be further explained the use of the switching transistor as a driver for the line output transistor in an embodiment to be especially described hereinafter has the further advantage that the line output transistor automatically becomes non-conductive when this switching transistor is short circuited so that the deflection and the EHT for the display tube drop out and thus avoid damage thereof.
In order that the invention may be readily carried into effect, a few embodiments thereof will now be described in detail by way of example with reference to the accompanying diagrammatic drawings in which:
FIG. 1 shows a principle circuit diagram wherein the chopper and the line deflection circuit are further shown but other circuits are not further shown.
FIGS. 2a, 2b and 2c show the variation as a function of time of two currents and of a voltage occurring in the circuit arrangement according to FIG. 1.
FIGS. 3a 3b, 3c and 3d show other embodiments of the chopper.
FIGS. 4a and 4b show modifications of part of the circuit arrangement of FIG. 1.
In FIG. 1 the reference numeral 1 denotes a rectifier circuit which converts the mains voltage supplied thereto into a non-stabilized direct voltage. The collector of a switching transistor 2 is connected to one of the two terminals between which this direct voltage is obtained, said transistor being of the npn-type in this embodiment and the base of which receives a pulsatory voltage which originates through a control stage 4 from a modulator 5 and causes transistor 2 to be saturated and cut off alternately. The voltage waveform 3 is produced at the emitter of transistor 2. In order to maintain the output voltage of the circuit arrangement constant, the duration of the pulses provided is varied in modulator 5. A pulse oscillator 6 supplies the pulsatory voltage to modulator 5 and is synchronized by a signal of line frequency which originates from the line oscillator 6' present in the picture display device. This line oscillator 6' is in turn directly synchronized in known manner by pulses 7' of line frequency which are present in the device and originate for example from a received television signal if the picture display device is a television receiver. Pulse oscillator 6 thus generates a pulsatory voltage the repetition frequency of which is the line frequency.
The emitter of switching transistor 2 is connected at one end to the cathode of an efficiency diode 7 whose other end is connected to the second input voltage terminal and at the other end to primary winding 8 of a transformer 9. Pulsatory voltage 3 which is produced at the cathode of efficiency diode 7 is clamped against the potential of said second terminal during the intervals when this diode conducts. During the other intervals the pulsatory voltage 3 assumes the value V i . A charge capacitor 10 and a load 11 are arranged between the other end of winding 8 and the second input voltage terminal. The elements 2,7,8,10 and 11 constitute a so-called chopper producing a direct voltage across charge capacitor 10, provided that capacitor 10 has a sufficiently great value for the line frequency and the current applied to load 11 flowing alternately through switching transistor 2 or through efficiency diode 7. The output voltage V o which is the direct voltage produced across charge capacitor 10 is applied to a comparison circuit 12 which compares the voltage V o with a reference voltage. Comparison circuit 12 generates a direct voltage which is applied to modulator 5 so that the duration of the effective period δ T of switching transistor 2 relative to the period T of pulses 3 varies as a function of the variations of output voltage V 0 . In fact, it is readily evident that output voltage V o is proportional to the ratio δ :
V o = V i . δ
However, variations in the line amplitude and the EHT may occur as a result of an insufficiently small internal impedance of the EHT generator. Compensation means are known for this purpose. A possibility within the scope of the present invention is to use comparison circuit 12 for this purpose. In fact, if the beam current passes through an element having a substantially quadratic characteristic, for example, a voltage-dependent resistor, then a variation for voltage V o may be obtained through comparison circuit 12 which variation is proportional to the root of the variation in the EHT which is a known condition for the line amplitude to remain constant.In addition this facilitates smoothing of voltage V o since the repetition frequency of pulsatory voltage 3 is many times higher than that of the mains and a comparatively small value may be sufficient for charge capacitor 10. If charge capacitor 10 has a sufficiently high value for the line frequency, voltage V o is indeed a direct voltage so that a voltage having the same form as pulsatory voltage 3 is produced across the terminals of primary winding 8. Thus voltages which have the same shape as pulsatory voltage 3 but have a greater or smaller amplitude are produced across secondary windings 13, 14 of transformer 9 (FIG. 1 shows only 2 secondary windings but there may be more). The invention is based on the recognition that one end of each secondary winding is connected to earth while the other end thereof drives a diode, the winding sense of each winding and the direction of conductance of each diode being chosen to be such that these diodes conduct during the same period as does efficiency diode 7. After smoothing, stabilized supply voltages, for example, at terminal 15 are generated in this manner at the amplitudes and polarities required for the circuit arrangements pre
In FIG. 1 charge capacitors are arranged between terminals 15 etc. and earth so as to ensure that the voltages on these points are stabilized direct voltages. If in addition the mean value of the voltage on one of these terminals has been made equal to the effective value of the alternating voltage which is required for heating the filament of the picture display tube present in the picture display device, this voltage is suitable for this heating. This is a further advantage of the invention since the cheap generation of a stabilized filament voltage for the picture display tube has always been a difficult problem in transistorized arrangements.
In FIG. 1 the reference numeral 14 denotes a secondary winding of transformer 9 which in accordance with the previously mentioned recognition of the invention can drive line output transistor 16 of the line deflection circuit 17. Line deflection circuit 17 which is shown in a simplified form in FIG. 1 includes inter alia line deflection coils 18 and an EHT transformer 19 a secondary winding 20 of which serves for generating the EHT required for the acceleration anode of the picture display tube. Line deflection circuit 17 is fed by the output voltage V o of the chopper which voltage is stabilized due to the pulse duration modulation with all previously mentioned advantages. Line deflection circuit 17 corresponds, for example, to similar arrangements which have been described in U.S. Pat. No. 3,504,224 issued Mar. 31, 1970 to J.J. Reichgelt et al., U.S. patent application Ser. No. 737,009 filed June 14, 1968 by W. H. Hetterscheid and U.S. application Ser. No. 26,497 filed April 8, 1970 by W. Hetterscheid et al. It will be evident that differently formed lined deflection circuits are alternatively possible.
It will now be shown that secondary winding 14 can indeed drive a line deflection circuit so that switching transistor 2 can function as a driver for the line deflection. FIGS. 2a and b show the variation as a function of time of the current i C which flows in the collector of transistor 16 and of the drive voltage v 14 across the terminals of secondary winding 14. During the flyback period (0, t 1 ) transistor 16 must be fully cut off because a high voltage peak is then produced at its collector; voltage v 14 must then be absolutely negative. During the scan period (t 1 , t 4 ) a sawtooth current i C flows through the collector electrode of transistor 16 which current is first negative and then changes its direction. As the circuit arrangement is not free from loss, the instant t 3 when current i C becomes zero lies, as is known, before the middle of the scan period. At the end t 4 of the scan period transistor 16 must be switched off again. However, since transistor 16 is saturated during the scan period and since this transistor must be suitable for high voltages and great powers so that its collector layer is thick, this transistor has a very great excess of charge carriers in both its base and collector layers. The removal of these charge carriers takes a period t s which is not negligible whereafter the transistor is indeed switched off. Thus the fraction δ T of the line period T at which v 14 is positive must end at the latest at the instant (t 4 - t s ) located after the commencement (t = 0) of the previous flyback.
The time δ T may be initiated at any instant t 2 which is located between the end t 1 of the flyback period and the instant t 3 when collector current i C reverses its direction. It is true that emitter current flows through transistor 16 at the instant t 2 , but collector current i C is not influenced thereby, at least not when the supply voltage (= V o ) for line deflection circuit 17 is high enough. All this has been described in the U.S. Pat. No. 3,504,224. The same applies to line deflection circuits wherein the collector base diode does not function as an efficiency diode as is the case in the described circuit 17, but wherein an efficiency diode is arranged between collector and emitter of the line output transistor. In such a case the negative part of the current i C of FIG. 2a represents the current flowing through the said efficiency diode.
0.85 × 270 V - 20 V = 210 V and the highest occurring V i is
1.1 × 270 V + 20 V = 320 V. For an output voltage V o of 135 V the ratio must thus vary between
δ = 135 : 210 = 0.64 and δ = 135 : 320 = 0.42.
During switching off, t 2 , of transistor 16 coil 22 must exert no influence and coil 21 must exert influence which is achieved by arranging a diode 23 parallel to coil 22. Furthermore the control circuit of transistor 16 in this example comprises the two diodes 24 and 25 as described in U.S. application Ser. No. 26,497 above referred to, wherein one of these diodes, diode 25 in FIG. 1, must be shunted by a resistor.
The control circuit of transistor 16 may alternatively be formed as is shown in FIG. 4. In fact, it is known that coil 21 may be replaced by the parallel arrangement of a diode 21' and a resistor 21" by which the inverse current can be limited. To separate the path of the inverse current from that of the forward current the parallel arrangement of a the diode 29' and a resistor 29" must then be present. This leads to the circuit arrangement shown in the upper part of FIG. 4. This circuit arrangement may now be simplified if it is noted that diodes 25 and 21' on the one hand and diodes 23 and 29' on the other hand are series-arranged. The result is shown in the lower part of FIG. 4 which, as compared with the circuit arrangement of FIG. 1, employs one coil less and an additional resistor.
FIG. 3 shows possible modifications of the chopper. FIG. 3a shown in a simplified form the circuit arrangement according to FIG. 1 wherein the pulsatory voltage present across the connections of windings 8 has a peak-to-peak amplitude of V i - V o = 0.5 V i for δ = 0.5, As has been stated, the provision of coil 22 gives a relative variation for the base current of transistor 16 which is equal to that of the mains voltage. In the cases according to FIG. 3b, 3c and 3d the peak-to-peak amplitude of the voltage across winding 8 is equal to V i so that the provision of coil 22 results in a relative variation which is equal to half that of the mains voltage which is still more favorable than in the first case.
Transistors of the npn type are used in FIG. 3. If transistors of the pnp type are used, the relevant efficiency diodes must of course be reversed.
In this connection it is to be noted that it is possible to obtain an output voltage V o with the aid of the modifications according to FIGS. 3b, c and d, which voltage is higher than input voltage V i . These modifications may be used in countries such as, for example, the United of America or France where the nominal mains voltage is 117 or 110 V without having to modify the rest of the circuit arrangement.
The above-mentioned remark regarding the sum of the diode currents only applies, however, for the modifications shown in FIGS. 3a and d.
If line output transistor 16 is not simultaneously driven with switching transistor 2, efficiency diodes 7 conducts simultaneously with transistor 16 i.e., during the period which is denoted by δ T in FIGS. 1 and 2b. During that period the output voltage V o of the chopper is stabilized so that the base current of transistor 16 is stabilized without further difficulty.
The line deflection circuit itself is also safeguarded: in fact, if something goes wrong in the supply, the driver voltage of the line deflection circuit drops out because the switching voltage across the terminals of primary winding 8 is no longer present so that the deflection stops. This particularly happens when switching transistor 2 starts to constitute a short-circuit between emitter and collector with the result that the supply voltage V o for the line deflection circuit in the case of FIG. 1 becomes higher, namely equal to V i . However, the line output transformer is now cut off and is therefore also safe as well as the picture display tube and other parts of the display device which are fed by terminal 15 or the like. However, this only applies to the circuit arrangement according to FIG. 1 or 3a.
Pulse oscillator 6 applies pulses of line frequency to modulator 5. It may be advantageous to have two line frequency generators as already described, to wit pulse oscillator 6 and line oscillator 6' which is present in the picture display device and which is directly synchronized in known manner by line synchronizing pulses 7'. In fact, in this case line oscillator 6' applies a signal of great amplitude and free from interference to pulse oscillator 6. However, it is alternatively possible to combine pulse oscillator 6 and line oscillator 6' in one single oscillator 6" (see FIG. 1) which results in an economy of components. It will be evident that line oscillator 6' and oscillator 6" may alternatively be synchronized indirectly, for example, by means of a phase discriminator. It is to be noted neither pulse oscillator 6, line oscillator 6' and oscillator 6" nor modulator 5 can be fed by the supply described since output voltage V o is still not present when the mains voltage is switched on. Said circuit arrangements must therefore be fed directly from the input terminals. If as described above these circuit arrangements are to be separated from the mains, a small separation transformer can be used whose primary winding is connected between the mains voltage terminals and whose secondary winding is connected to ground at one end and controls a rectifier at the other end.
Capacitor 27 is
As is known the so-called pincushion distortion is produced in the picture display tubes having a substantially flat screen and large deflection angles which are currently used. This distortion is especially a problem in color television wherein a raster correction cannot be brought about by magnetic means. The correction of the so-called East-West pincushion distortion i.e., in the horizontal direction on the screen of the picture display tube can be established in an elegant manner with the aid of the circuit arrangement according to the invention. In fact, if the voltage generated by comparison circuit 12 and being applied to modulator 5 for duration-modulating pulsatory voltage 3 is modulated by a parabola voltage 28 of field frequency, pulsatory voltage 3 is also modulated thereby. If the power consumption of the line deflection circuit forms part of the load on the output voltage of the chopper, the signal applied to the line deflection coils is likewise modulated in the same manner. Conditions therefore are that the parabola voltage 28 of field frequency has a polarity such that the envelope of the sawtooth current of line frequency flowing through the line deflection coils has a maximum in the middle of the scan of the field period and that charge capacitor 10 has not too small an impedance for the field frequency. On the other hand the other supply voltages which are generated by the circuit arrangement according to the invention and which might be hampered by this component of field frequency must be smoothed satisfactorily.
A practical embodiment of the described example with the reference numerals given provides an output for the supply of approximately 85 percent at a total load of 90 W, the internal resistance for direct current loads being 1.5 ohms and for pulsatory currents being approximately 10 ohms. In case of a variation of ± 10 percent of the mains voltage, output voltage V o is stable within 0.4 V. Under the nominal circumstances the collector dissipation of switching transistor 2 is approximately 2.5 W.
Since the internal resistance of the supply is so small, it can be used advantageously, for example, at terminal 15 for supplying a class-B audio amplifier which forms part of the display device. Such an amplifier has the known advantages that its dissipation is directly proportional to the amplitude of the sound to be reproduced and that its output is higher than that of a class-A amplifier. On the other hand a class-A amplifier consumes a substantially constant power so that the internal resistance of the supply voltage source is of little importance. However, if this source is highly resistive, the supply voltage is modulated in the case of a class-B amplifier by the audio information when the sound intensity is great which may detrimentally influence other parts of the display device. This drawback is prevented by means of the supply according to the invention.
The PHILIPS CHASSIS TVC11 Shows even the use of the TEXAS INSTRUMENTS TMS1000:
General
General Information
Texas Instruments was locked in a race with Intel to create the first microprocessor. By most accounts Intel won with the 4004, but there are a few die hard TI fans who say the TMS1000 was first, because it was the first “computer on a chip” and that the 4004 was just a calculator chip.
Texas Instruments followed the Intel 8080 with the 4-bit TMS1000. So, while Intel was leading the industry in microprocessors, TI led with this industry unique design "a computer on a chip", specifically designed for control and automation purposes. The 1000 was the first MCU (MicroComputer Unit) , which is an MPU (MicroProcessor Unit) with other support chips (such as RAM, ROM, counters, timers, I/O interfaces) integrated on to the same silicon chip.
The original 1000 family consists of 6 chips the TMS1000 and TMS1200 are basic chips, the TMS1070 and TMS1270 are high voltage versions to interface to displays, the TMS1100 and TMS1300 provide twice the on-board ROM and RAM. The TMS1000, TMS1070, and TMS1100 are 28-lead packages, the TMS1200, TMS1270, and TMS1300 are 40-lead versions of the same chips (just 200 to the 28-lead chip numbers).
In the 80's TI added to the 1000 family. The 28-lead TMS1170 started with a TMS1100 base and added fluorescent display drive capability and expanded memory (2KB ROM). The TMS1370 was the same as the TMS1170 and added 27 I/O lines. An expanded memory group based on the original TMS1000 chips was also created. They were the TMS1400, TMS1470, and TMS1700 (64 Bytes RAM, 4KB ROM). There were 40-lead versions of the TMS1400 and TMS1470, which because the TMS1600 and TMS1670. CMOS versions were also added, denoted with a "C" suffix, such as TMS1200C.
The TMS1000 also had system evaluator chips. The original evaluator chips were the TMS1098 and TMS1099. These 64-lead evaluator chips were ROM-less versions of their corresponding standard chips. The TMS1099 supported the TMS1000/TMS1200 and the TMS1070/1270. The TMS1098 supported the TMS1100/1300. Later evaluators were introduced to support the entire TMS1000 family, they were the SE1000P (supports TMS1000,1070,1200,1700), SE2200P (supports TMS1100,1170,1300,1370), and the SE1400P (supports 1400, 1470, 1600, 1670).
The success of the the TMS1000 is demonstrated by its long lifecycle (over 20 years) and its expanded product line. The TMS1000 is found in many appliances, control systems, and games. Most of these chips were sourced by companies for direct use in their products and will have custom or house numbers on the chips (not the standard numbers listed above). Even TI used custom numbers in its products.
PHILIPS 26P1195 MULTISTANDARD CHASSIS TVC11 Channel selector having a plurality of tuning systems:
A channel selector characterized in that a plurality of receivers capable of simultaneously performing a receiving operation have a main part of a phase
-locked loop frequency synthesizer connected in common thereto, the frequency synthesizer having a programmable frequency divider, a phase comparator, a reference oscillator and a reference frequency divider. The frequency synthesizer is controlled so that a local oscillation frequency corresponding to a determined frequency close to a broadcast signal of a desired receiving channel is synthesized, and one of a plurality of search tuning systems searches and tunes the broadcast signal from the local oscillation frequency.and wherein each of said plurality of receivers has its own low pass filter included in its equivalent phase-locked loop frequency synthesizer, and an output of a phase comparator is switched to an input terminal of one low pass filter from among said plurality of low pass filters by a 3-st
ate switching circuit.2. A channel selector according to claim 1, wherein said common portion of each of said equivalent phase-locked loop frequency synthesizers comprises a programmable frequency divider, a phase comparator, a reference oscillator and a reference frequency divider.
3. A channel selector according to claim 1, wherein said common portion of each of said equivalent phase-locked loop frequency synthesizers comprises a prescaler.
4. A channel selector according to claim 1, wherein said common portion of each of said equivalent phase-locked loop frequency synthesizers comprises a channel entry means and a code converter means.
5. A channel selector for controlling the tuning frequency of a plurality of receivers capable of simultaneously performing rec
and wherein each of said equivalent phase-locked loop frequency synthesizers is controlled so that a local oscillation frequency corresponding to a predetermined frequency close to a broadcast signal of a desired receiving channel is synthesized, and one of a plurality of search tuning systems searches and tunes said broadcast signal from said local oscillation frequency whereby said broadcast signal of said desired receiving channel is tuned.
6. A channel selector for controlling the tuning frequency of a plurality of receivers capable of simultaneously performing receiving operations, each of said plurality of receivers having a portion of a phase-locked loop frequency synthesizer; wherein another portion of a phase-locked loop frequency synthesizer is commonly used by said portions of said synthesizers whereby each of said plurality of receivers has an equivalent complete phase-locked loop frequency synthesizer;
and wherein each of said phase-locked loop frequency synthesizers selects a desired receiving channel, and wherein a tuning voltage of said desired receiving channel is stored in a voltage memory means, and wherein said channel selector further comprises a tuning means provided for each of said plurality of receivers so that while receiving, said tuning means tunes in accordance with the output of said voltage memory means.
7. A channel selector according to claims 5 or 6, wherein said common portion of each of said equivalent phase-locked loop frequency synthesizers comprises a programmable frequency divider, a phase comparator, a reference oscillator and a reference frequency divider.
8. A channel selector according to claims 5 or 6, wherein said common portion of each of said equivalent phase-locked loop frequency synthesizers comprises a prescaler.
9. A channel selector according to claims 5 or 6, wherein said common portion of each of said equivalent phase-locked loop frequency synthesizers comprises a channel entry means and a code converter means.
Description:
BACKGROUND OF THE INVENTIONThis invention relates to a channel selector for use in television receivers, FM (frequency modulation) radio receivers, AM (amplitude modulation) radio receivers and so on.
TDA2581 CONTROL CIRCUIT FOR SMPS
The TDA2581 is a monolithic integrated circuit for controlling switched-mode power supplies (SMPS) which are provided with the drive for the horizontal deflection stage.
The circuit features the following:
— Voltage controlled horizontal oscillator.
— Phase detector.
— Duty factor control for the positive-going transient of the output signal.
— Duty factor increases from zero to its normal operation value.
— Adjustable maximum duty factor.
- Over-voltage and over-current protection with automatic re-start after switch-off.
— Counting circuit for permanent switch-off when n~times over~current or over-voltage is sensed
-Protection for open-reference voltage.
- Protection for too low supply voltage.
Protection against loop faults.
Positive tracking of duty factor and feedback voltage when the feedback voltage is smaller than the
reference voltage minus 1,5 V.
TDA2541 IF AMPLIFIER WITH DEMODULATOR AND AFC
DESCRIPTION
The TDA2540 and 2541 are IF amplifier and A.M.
demodulator circuits for colour and black and white
television receivers using PNP or NPN tuners. They
are intended for reception of negative or positive
modulation CCIR standard.
They incorporate the following functions : .Gain controlled amplifier .Synchronous demodulator .White spot inverter .Video preamplifier with noise protection .Switchable AFC .AGC with noise gating .Tuner AGC output (NPN tuner for 2540)-(PNP
tuner for 2541) .VCR switch for video output inhibition (VCR
play back).
.SUPPLYVOLTAGE : 12V TYP
.SUPPLYCURRENT : 50mATYP
.I.F. INPUT VOLTAGE SENSITIVITY AT
F = 38.9MHz : 85mVRMS TYP
.VIDEO OUTPUT VOLTAGE (white at 10% of
top synchro) : 2.7VPP TYP
.I.F. VOLTAGE GAIN CONTROL RANGE :
64dB TYP .SIGNAL TO NOISE RATIO AT VI = 10mV :
58dB TYP
.A.F.C. OUTPUT VOLTAGE SWING FOR
Df = 100kHz : 10V TYP
TPHILIPS 26P1195 MULTISTANDARD CHASSIS TVC11 Television intermediate frequency amplifier with feedback stabilization:
Other References:
Phillips Technical Information 034, TDA2540 and TDA2541, Aug. 18, 1977. Monolithic TV IF System TBA 440 by E. Schatter, pub. in IEEE Transactions on Broadcast & Television Receivers, Aug. 1972, vol. BTR-18, beginning on p. 158. An I.F. amplifier is provided in which gain control is accomplished by varying the A.C. impedances of variable impedance devices, which devices are coupled as load and emitter degeneration impedances for amplifying transistors. Variable D.C. gain control currents are applied to the variable impedance devices to vary their impedance. Substantially all of the D.C. gain control currents flow through the variable impedance devices in current paths which are separate from the amplifying transistors, thereby avoiding variation of the operating points of the amplifying transistors. The I.F. amplifier includes a D.C. feedback path which does not require the use of feedback amplification, due to the lack of any changes in the operating points of the amplifying stages during gain control. Elimination of the need for feedback amplification also prevents the introduction of noise into the amplified I.F. signals.
1. A feedback stabilized television intermediate frequency amplifier system comprising:
an automatic gain control system for supplying a gain control signal;
a plurality of gain controlled differential amplifiers direct current coupled in a cascade configuration for amplifying intermediate frequency signals, each of said amplifiers being coupled to said automatic gain control system and responsive to said gain control signal for varying the intermediate frequency signal gain of each of said amplifiers, the
D.C. biasing of at least one of said amplifiers being substantially invariant to changes of said gain control signal, the first of said cascade coupled amplifiers including first and second differentially coupled amplifying transistors having base electrodes coupled to respective first and second input terminals, and the last of said cascade coupled amplifiers including third and fourth differentially coupled amplifying transistors having respective collector electrodes comprising first and second output electrodes of said amplifying system; and a first D.C. feedback path coupled between said first output electrode and said first input terminal, and a second D.C. feedback path coupled between said second output electrode and said second input terminal, said feedback paths each exhibiting a voltage gain not greater than unity over a range of frequencies including D.C. and said television intermediate frequencies.
wherein said cascade coupled amplifiers and said first and second feedback paths comprise an amplifier and feedback loop, and
wherein said first D.C. feedback path comprises first, second and third resistors serially coupled between said first output electrode and said first input terminal, and said second D.C. feedback path comprises fourth, fifth and sixth resistors serially coupled between said second output electrode and said second input terminal; and further comprising
a first bypass capacitor coupled between the junction of said second and third resistors and the junction of said fifth and sixth resistors for providing a loop gain which is less than unity at said television intermediate frequencies; and
a second bypass capacitor coupled between the junction of said first and second resistors and the junction of said fourth and fifth resistors, said second bypass capacitor and said first and fourth resistors forming a decoupling network for decoupling said output electrodes from said input terminals.
3. The feedback stabilized television intermediate frequency amplifier system of claim 2, further comprising:
a video detector having first and second input terminals;
a fifth transistor having a base coupled to said first output electrode and an emitter coupled to said first resistor and said first input terminal of said video detector; and
a sixth transistor having a base coupled to said second output electrode and an emitter coupled to said fourth resistor and said second input terminal of said video detector,
wherein said fifth and sixth transistors buffer said output electrodes from said input terminals of said video detector.
4. The feedback stabilized television intermediate frequency amplifier system of claim 2, wherein the phase shift around said amplifier and feedback loop is substantially equal to an odd multiple of 180 degrees for frequencies at which the gain of said amplifier and feedback loop is equal to or greater than unity. 5. A feedback stabilized television intermediate frequency amplifying system comprising:
a first amplifying stage including first and second amplifying transistors coupled in a differential amplifier configuration, a first resistor coupled between the collector of said first transistor and a source of supply potential and passing a first direct current therebetween, a second resistor coupled between the collector of said second transistor and a source of supply potential and passing a second direct current therebetween, and means direct current coupled in shunt with said first and second resistors and responsive to variations of a first gain control current for causing gain variations for said first amplifying stage with negligible disturbance of the magnitude of said first and second direct currents; and
a second amplifying stage direct current coupled in cascade with said first amplifying stage, and including third and fourth amplifying transistors coupled in a differential amplifier configuration, a third resistor coupled between said emitter of said third transistor and a point of signal reference potential and passing a third direct current therebetween, a fourth resistor coupled between said emitter of said fourth transistor and a point of signal reference potential and passing a fourth direct current therebetween, and means direct current coupled in shunt with said third and fourth resistors and responsive to variations of a second gain control current for causing gain variations for said second amplifying stage with negligible disturbance of the magnitude of said third and fourth direct currents; and
a first D.C. feedback path coupled between the collector of said third transistor and the base of said first transistor, and a second D.C. feedback path coupled between the collector of said fourth transistor and the base of said second transistor, said feedback paths each exhibiting a voltage gain not greater than unity over a range of frequencies including D.C. and said television intermediate frequencies.
6. The feedback stabilized television intermediate frequency amplifier system of claims 1 or 5, wherein said differential amplifiers and said first and second D.C. feedback paths comprise a D.C. feedback amplifier loop exhibiting a loop voltage gain not greater than unity over a first range of frequencies including said television intermediate frequencies and a loop phase shift which is approximately equal to 180 degrees over a second range of frequencies located between D.C. and said first range of frequencies.
Description:
In a conventional television I.F. amplifying section, several amplifier stages are usually cascaded to provide high amplification for the I.F. signal which is received from the tuner and mixer circuitry. Since the received I.F. signal may be of varying signal strength, one or more of the amplifier stages is generally gain controlled, so that the final I.F. amplifier stage will provide a substantially constant strength signal to the video detector.
However, as the gain of the gain controlled stage or stages is varied by the usual techniques of forward or reverse gain control, the operating points of the amplifier stages are unavoidably changed as the D.C. currents conducted by the amplifier stages change. These D.C. operating point shifts will be applied to subsequent stages in the amplifier when the amplifiers are direct current coupled to each other, which is the conventional technique currently in use. This will result in undesirable alteration of the operating points of the subsequent stages, as the changing D.C. currents are propagated through the cascaded amplifier stages. Furthermore, the D.C. currents will cause changes in the D.C. level of the amplified signal, which can adversely affect the operation of the video detector. It is therefore desirable for the I.F. amplifier to be gain controlled in a manner which avoids shifts in the operating points of the amplifying devices.
In accordance with the principles of the present invention, an I.F. amplifier is provided in which gain control is accomplished by varying the A.C. impedances of variable impedance devices, which devices are coupled as load and emitter degeneration impedances for amplifying transistors. Variable D.C. gain control currents are applied to the variable impedance devices to vary their impedance. Substantially all of the D.C. gain control currents flow through the variable impedance devices in current paths which are separate from the amplifying transistors, thereby avoiding variation of the operating points of the amplifying transistors. Since the operating points of the various stages are substantially unaffected during gain control, the individual stages may be designed to operate at optimum, substantially unvarying bias points.
In order to stabilize the operating points
of the amplifying stages in I.F. amplifiers against changes such as those due to the aforementioned D.C. shifts, as well as temperature induced shifts and variation in device characteristics from one amplifier to another, a D.C. feedback path is generally coupled between the first and last amplifying stages. The complexity of the D.C. feedback path is dependent upon the magnitude of D.C. correction which the amplifiers are expected to require for stable operation. In some I.F. amplifiers, such as the one used in the TDA2540 TV I.F. IC, the D.C. gain of the I.F. amplifier and feedback loop is relatively low. This can result in insufficient D.C. feedback under certain low gain operating conditions. In order to provide the required amount of feedback, a separate amplifier is coupled in its own feedback loop at the output of the final I.F. stage. This amplifier is used to provide the required amount of feedback for the I.F. system, which prevents a lockout condition from occurring during channel switching. Pursuant to the principles of the present invention, the I.F. amplifier includes a D.C. feedback path which does not require the use of such a feedback amplifier, due to the lack of any changes in the operating points of the amplifying stages during gain control. Elimination of the feedback amplifier also prevents the introduction of noise into the amplified I.F. signals by this amplifier. The sole drawing FIGURE illustrates in schematic and block diagram form a three stage I.F. amplifier constructed in accordance with the principles of the present invention.
Referring to the drawing, three differential I.F. amplifier stages 1, 100 and 200 are coupled in cascade, with a feedback path 300 coupled between the third and first stages 200 and 1. The three stages are gain controlled by control currents supplied by an AGC system 40, and bias voltages for the system are provided by a bias supply 70.
A push-pull video I.F. signal is applied across input terminals 32 and 34, which are coupled to the bases of buffer transistors 50 and 52 of the first stage 1. The collectors of the buffer transistors 50 and 52 are coupled to the bias supply 70, and their respective emitter electrodes are coupled to the bases of amplifying transistors 10 and 12. Biasing for the emitter-base connections of transistors 50 and 10, and 52 and 12, is provided by resistors 54, 56 and 58. A D.C. ground return path for the emitters of transistors 10 and 12 is provided by resistors 66, 67 and 69, and pinch resistor 68. The pinch resistor 68 is also used to stabilize beta variations in the transistors of the first stage, which variations may occur from one circuit to another during volume production of the amplifier in integrated circuit form.
The A.C. emitter impedance of transistors 10 and 12 is dominated by a resistor 62 and a peaking capacitor 64, which are coupled in parallel between the emitters of the transistors. Each amplifying transistor 10 or 12 has a load impedance comprising a resistor 18 or 20 coupled between the collector of the respective transistor and the bias supply 70, and a variable impedance device. The collector of transistor 10 is coupled to the base of a variable impedance device 14, and the collector of transistor 12 is coupled to the base of a variable impedance device 16. The variable impedance devices 14 and 16 have collectors which are coupled to a reference potential (ground) and joined emitters, which are coupled to receive control current from the AGC system 40 by way of a resistor 22.
The output signals at the collectors of the amplifying transistors 10 and 12 are direct current coupled to the bases of buffer transistors 150 and 152 of the second amplifying stage 100. The second amplifying stage 100 is constructed in a similar manner as the first amplifying stage 1, and respective similar circuit elements have reference numerals which are increased by one hundred as compared with their counterparts in the first stage. The second stage 100 differs from the first stage in that it does not include a peaking capacitor or a pinch resistor. A forward biased diode 170 is coupled between the emitter resistor 169 and ground. This diode cooperates with the amplifying and buffer transistors in the second stage to provide the collectors of transistors 10 and 12 with a 3 Vbe D.C. term for bias and temperature stabilization purposes. It may be seen that the collector of transistor 10 is D.C. biased by the base-emitter junctions of transistors 150 and 110, and the junction of diode 170. Similarly, the collector of transistor 12 is D.C. biased by the base-emitter junctions of transistors 152 and 112, and the junction of diode 170.
s 10, 12, 110 and 112. The D.C. biasing of the amplifying transistors is therefore substantially constant as the ranges of gain control of the amplifying stages are traversed. The collectors of the second stage amplifying transistors 110 and 112 are respectively direct current coupled to the bases of buffer transistors 250 and 252 of the third amplifying stage 200. The collectors of buffer transistors 250 and 252 are coupled to receive bias voltage from the bias supply 70, and their emitters are returned to ground by resistors 254, 256 and 258. The emitters of buffer transistors 250 and 252 are also coupled to the bases of amplifying transistors 210 and 212, respectively.
The collectors of the amplifying transistors 210 and 212 are coupled to the bias supply 70 by way of respective load resistors 218 and 220. The emitters of the amplifying transistors 210 and 212 are returned to ground through resistors 262, 264 and 266. A forward biased diode 270 is coupled between resistor 266 and ground. Diode 270 performs a similar function as that of diode 170, as it cooperates with the buffer and amplifying transistors 250, 252, 210 and 212 to provide the collectors of the second stage amplifying transistors 110 and 112 with a quiescent D.C. voltage term of 3 Vbe.
A resistor 260 is coupled between the emitters of transistors 210 and 212. The emitters of transistors 210 and 212 are also coupled to the bases of respective variable impedance devices 214 and 216. The collectors of the variable impedance devices 214 and 216 are coupled to ground, and their emitters are coupled to receive gain control current from AGC system 40 by way of a resistor 222.
The third amplifying stage 200 is constructed and operates in a similar manner as the amplifier described in my copending United States Patent Application Ser. No. 143,035, entitled "VARIABLE EMITTER DEGENERATION GAIN-CONTROLLED AMPLIFIER," filed Apr. 23, 1980, which is incorporated by reference. Briefly, the emitter resistance of each amplifying transistor includes one-half of the value of resistor 260 (due to the complementary operation of the amplifying transistors in response to push-pull I.F. signals), in parallel with the base-to-emitter impedance of a variable impedance device and a further bias resistor. The variably impedance devices 214 and 216 may be constructed in the same manner as variable impedance devices 14, 16, 114 and 116, and are characterized by a base-to-emitter A.C. impedance which decreases as the current supplied to them by the AGC system 40 increases. For the maximum gain condition of the third amplifying stage 200, the current supplied to the variable impedance devices is at a maximum. This provides a low emitter impedance to the amplifying transistors 214 and 216, causing a relatively low level of emitter degeneration. As the gain control range of the amplifier is traversed toward its minimum gain condition, the current supplied to the variable impedance devices is decreased, which increases the A.C. impedance presented to the amplifying transistors by the devices. The emitter degeneration is increased, and hence the gain of the amplifier is reduced. As in the case of the variable impedance devices described previously, the primary current path for the control current supplied by the AGC system 40 is through the emitter-to-collector paths of devices 214 and 216, which minimizes changes in the D.C. biasing of the amplifying transistors 210 and 212 as the gain control range of the amplifier is traversed.
The use of collector-controlled variable load line gain control in the first two amplifying stages and controlled emitter degeneration in the third stage reduces the maximum amount of current required for gain control and therefore the power dissipation in the I.F. amplifier system. Control current is supplied to the variable impedance devices of the first two stages by way of a common terminal 42 of the AGC system 40. The gain of these two stages is reduced by increasing the flow of control current. Control current is supplied to the variable impedance devices of the third stage by way of a separate terminal 44. The gain of this stage is reduced by decreasing the flow of control current from the AGC system 40 to the third stage. An advantageous sequence of gain control for the illustrated embodiment is described in my copending United States Patent Application Ser. No. 163,143, entitled "TELEVISION INTERMEDIATE FREQUENCY AMPLIFIER", concurrently filed herewith.
The feedback path 300 is comprised of two D.C. paths, one for each side of the balanced amplifier configuration. A feedback path including serially coupled resistors 318, 314, 324 and 328 is coupled between the emitter of transistor 301 and the base of first stage transistor 52. A second feedback path including serially coupled resistors 310, 316, 326 and 330 is coupled between the emitter of transistor 303 and the base of transistor 50.
The feedback path 300 includes two decoupling networks which decouple the amplified output I.F. signals from the input of stage 1. A first decoupling network includes buffer resistors 310 and 318 and a capacitor 312, and the second decoupling network includes buffer resistors 314 and 316, and bypass capacitors 322 and 320. Resistors 310 and 318 isolate the output at the emitters of transistors 301 and 303 from capacitor 312. The capacitor 312 is coupled across the two D.C. paths to significantly attenuate the complementary I.F. signals which are produced on the two paths. Any remaining I.F. signal components which appear on the two plates of capacitor 312 are then applied to bypass capacitors 322 and 320 by buffer resistors 314 and 316, respectively. The bypass capacitors 322 and 320 will then shunt any remaining I.F. signal components to ground. The decoupling networks act as low pass filters for the I.F. signals, with breakpoints below the desired range of I.F. signals, so that substantially only D.C. signals are applied to buffer resistors 324 and 326. The values of the resistors are chosen so that the D.C. feedback signals are not attenuated beyond a level at which they will provide the desired amount of feedback compensation in the first stage 1.
It is seen that bypass capacitors 322 and 320 are each coupled between a D.C. path and ground, whereas the capacitor 312 of the first decoupling network is coupled between the two D.C. paths. The coupling of capacitor 312 is the preferred technique, since capacitors 322 and 320 bypass I.F. signals to ground, and capacitor 312 does not. The I.F. signals which are conducted by capacitors 322 and 320 will be conducted through the ground plane of the system until they cancel each other. If the ground points to which the capacitors are connected are in close proximity to each other, the ill effects resulting from ground plane conduction of the I.F. signals will be partially mitigated. However, adjacent location of the two capacitors 322 and 320 is not always possible, especially when the system is constructed in integrated circuit form, wherein other considerations may govern the placement of the two capacitors. In that case, the I.F. signals may contaminate undesirably large areas of the I.C. ground plane, resulting in undesirable I.F. signal coupling to other circuitry in the system through ground connections. This problem is eliminated through the use of a capacitor coupled between the two D.C. paths, as is capacitor 312, since no I.F. signals are coupled to the ground plane by this decoupling network. If desired, the second decoupling network, including resistors 314 and 316, and capacitors 322 and 320, may b
e dispensed with in an embodiment of the illustrated arrangement, depending upon the level of I.F. signal cancellation desired and provided by the first decoupling network. Buffer resistors 324 and 326 are coupled to the input transistors 52 and 50 by way of terminals 334 and 332 and isolation resistors 328 and 330, respectively. A further bypass capacitor 333 is coupled between terminals 332 and 334. The isolation resistors 328 and 330 serve to isolate the inputs to the first amplifying stage 1 from bypass capacitor 333. The bypass capacitor 333, together with resistors 324, 314, 318, and 326, 316, 310, determine the 3 db point of the I.F. amplifier and feedback loop, to assure system stability.
At maximum gain, the I.F. amplifying stages shown in the illustrated embodiment will have a gain of approximately 60 db. The system bandwidth is assumed to be approximately 100 MHz. In order to assure that the system will be stable, the phase and gain of the signal which is fed back from the third to the first stage must be controlled to prevent system oscillation. System oscillation will be prevented as long as the loop phase delay does not approach an even multiple of 180 degrees at any frequency at which the loop gain is equal to or greater than unity.
The I.F. signals which are applied to input terminals 32 and 34 undergo a phase reversal in each I.F. amplifying stage. If the I.F. system had unlimited bandwidth, the I.F. signals at the output of the third stage would be 180 degrees out of phase with respect to the input signals, thus readily providing a negative feedback signal. However, the system is assumed to have a limited bandwidth of 100 MHz, which introduces some phase delay into the amplified I.F. signals. This phase delay may only amount to a few degrees at low frequencies, but can amount to 80 degrees or more at I.F. frequencies around 50 MHz. The output I.F. signals will undergo even further delay in the decoupling networks of the feedback path. If the additional feedback delay should cause the signals to have a net delay which approaches an even multiple of 180 degrees around the loop at any frequency, the feedback will be positive and the system will be subject to oscillation at that frequency.
The value of capacitor 333 is chosen in combination with the values of resistors 324, 314, 318, and 326, 316, 310 to establish a pole at a frequency which is referred to as the 3 db frequency. Above the 3 db frequency, the amplitudes of higher frequency signal components will roll off at approximately 6 db per octave, or 20 db per decade of frequency. If the rolloff were chosen to be greater, such as 18 db per octave, each additional db of attenuation will cause the phase shift of the feedback path to increase proportionately, so that the feedback path phase shift will rapidly approach 180 degrees at higher frequencies, which could lead to oscillation at these higher frequencies.
The placement of the pole at the 3 db frequency must guarantee no greater than unity gain at all frequencies above a higher, unity gain frequency and including the I.F. frequency range about 50 MHz, which permits phase shifts in that frequency range to be neglected. For purposes of illustration, assume that the loop including the amplifiers and the feedback path provides 6 degrees of phase shift at 1 MHz, (plus the three signal inversions of the three amplifiers, which will be assumed to be present at all frequencies). Further assume that the feedback 3 db pole is located at 1 KHz, and provides a rolloff of 6 db per octave, or 20 db per decade. This rolloff will therefore provide 20 db of attenuation at 10 KHz, 40 db of attenuation at 100 KHz, and 60 db of attenuation at 1 MHz. Frequencies greater than 1 MHz will be attenuated by more than 60 db. Since the maximum gain of the amplifying stages is assumed to be 60 db, the 1 MHz frequency is the unity gain frequency for the amplifier and feedback loop. Although the delay in the 1 to 50 MHz range varies from 6 degrees to upwards of 80 degrees, the feedback attenuation is greater than 60 db over this range, which prevents loop gain of unity or greater over the range. Thus, one of the criteria for oscillation, unity gain, is not met, and the system will not oscillate at frequencies within this range. Furthermore, at frequencies below 1 MHz, the phase shift of the feedback path is 6 degrees or less, which prevents the occurrence of loop phase shifts approaching an even multiple of 180 degrees, which is the second condition necessary for oscillation.
Unlike the prior art I.F. amplifier system described previously, the I.F. amplifier of the present invention does not require an additional amplifier in the feedback path 300. This additional amplifier was needed in the prior art arrangement because that arrangement is characterized by low D.C. gain due to the exclusive use of emitter degeneration type amplifying stages. As the gain of those stages is reduced, the D.C. gain is also reduced, and hence the additional amplifier is required to amplify the D.C. feedback signal. Of the three amplifying stages of the present invention, only the third stage uses emitter degeneration gain control. The third stage D.C. gain is dominated by the emitter resistors 260, 262 and 264, which gives the third stage a high input impedance and a low frequency gain of approximately 10 db. The first and second amplifying stages, which rely upon load line variation for gain control, have respective D.C. gains of approximately 20 db. The D.C. gain of the three cascaded states is fairly constant over the full range of gain control, and has been found to vary by no more than 6 db over the range. This stability in D.C. gain is attributed to the nonvarying D.C. biasing of the amplifying stages, as a result of the use of variable impedance devices, the control of which does not substantially affect the D.C. biasing of the amplifying transistors.
PHILIPS 26P1195 MULTISTANDARD CHASSIS TVC11 COLOR AMPLIFIER WITH Constant bandwidth RGB output amplifiers having simultaneous gain and DC output voltage control :
A color television receiver includes conventional circuitry for processing and detecting a received color television signal. Three chrominance-luminance matrices combine detected color difference and luminance signals forming color red, blue and green video signals. Emitter follower coupling stages apply the color video signals individually to each
1. In a color televison receiver, for processing and displaying a received television signal bearing modulation components of picture information, having a cathode ray tube including a trio of electron source means producing individual electron beams impinging an image screen to form three substantially overlying images and in which the respective operating points and relative conduction levels of said electron source means determine the color temperature of the reproduced image, the combination comprising:
master conduction means, coupled to said trio of electron source means simultaneously varying said conduction levels;
a plurality of substantially equal bandwidth amplifiers, each coupled to a different one of said electron source means, separately influencing said conduction levels;
low output impedance signal translation means recovering said picture information and supplying it to each of said plurality of amplifiers; and
separate adjusting means individually coupled to at least two of said amplifiers for simultaneously producing predetermined same sense variations in gain and DC output voltage of its associated amplifier while preserving said bandwidths.
2. The combination set forth in claim 1, wherein the transconductance and cutoff voltage of each of said electron source means bear a predetermined relationship and wherein said simultaneous predetermined variations in gain and DC output voltage are determined by said transconductance-cutoff voltage relationship. 3. The combination set forth in claim 2, wherein said plurality of amplifiers each include a gain and DC output voltage determining impedance and wherein each of said separate adjusting means include:
a variable impedance, coupling said gain and DC output voltage determining impedance of said associated amplifier to a source of bias current and forming a shunt path for signals within said amplifier.
4. The combination set forth in claim 3, wherein each of said electron source means include a cathode electrode and wherein each of said amplifiers include:
a transistor having input, common, and output electrodes, said output electrode being coupled to said electron source means cathode.
5. The combination set forth in claim 4, wherein said gain and DC output voltage determining impedance is coupled to said common electrode. 6. The combination set forth in claim 5, wherein said input, common, and output electrodes of said transistors are defined by base, emitter, and collector electrodes, respectively. 7. The combination set forth in claim 6, wherein said gain and DC output voltage determining impedance includes a resistor coupling said emitter electrode to ground and wherein said variable impedance includes:
a resistive control, having a variable resistance, coupling said emitter electrode to a source of operating potential.
8. The combination set forth in claim 7, wherein said three electron source means include control grid and screen grid electrodes common to said three electron guns and wherein variations of cathode electrode voltages permit changes of said relative conduction levels and said respective operating points. 9. The combination set forth in claim 8, wherein said master conduction means includes a variable bias potential source coupled to said common screen grid electrode.
Description:
BACKGROUND OF THE INVENTIONThis invention relates to color television receivers and in particular to cathode ray tubes (CRT) drive systems therefor. Each of the several types of color television cathode ray tubes in current use includes a trio of individual electron sources producing distinct electron beams which are directed toward an image screen formed by areas of colored-light-emitting phosphors deposited on the inner surface of the CRT. The phosphors emit light of a given additive primary color (red, blue or green) when struck by high energy electrons. A "delta" electron gun arrangement, in which the electron sources comprise three electron guns disposed at the vertice
The phosphor deposits forming the image screen may alternatively comprise round dots, elongated areas, or uninterrupted vertical lines. A parallax barrier or shadow mask, defining apertures generally corresponding to the shape of the phosphor areas, is interposed between the electron guns and the image screen to "shadow" or block each phosphor area from electrons emitted from all but its corresponding electron gun.
A color television signal includes both luminance (monochrome) and chrominance (color) picture components. In the commonly used RGB drive systems the separately processed luminance and chrominance information is matrixed (or combined) before application to the CRT cathodes. Three output amplifiers apply the respective red, blue and green video signals thus produced for controlling the respective electron source currents.
The luminance components have substantially the same effect on all three electron sources whereas the color components are differential in nature, causing relative changes in electron source currents. In the absence of video signals, the combined raster should be a shade of grey. At high gun currents, the grey is very near white and at low settings, it is near black. The "color", commonly called color temperature, of the monochrome raster depends upon the relative contributions of red, blue and green light. At high color temperatures, the raster may appear blue and at low color temperatures it may appear sepia. While the most pleasing color temperature is largely a matter of design preference, ideally the receiver should not change color temperature under high and low brightness nor for high and low frequency picture information.
Generally, the electron sources comprise individual electron guns each including separately adjustable cathode, control grid and screen grid electrodes and a desired color temperature is achieved by adjustment of each electrode voltage during black and white setup. While the exact setup procedure employed varies with the manufacturer and specific CRT configuration, all manufacturers attempt to achieve consistent color temperature throughout the usable range of CRT beam current variations.
A typical color temperature adjustment involves setting the low light color temperature condition of each electron gun by adju
sting its screen grid electrode voltage to produce the required DC conditions between electron guns at minimum beam currents. A high light or dive adjustment at increased CRT beam current is then made to insure consistent color temperature. In receivers utilizing CRT's with separately adjustable screen grid electrode voltages, the drive adjustment may take the form of a minor change in signal gain of the output amplifiers. The process is, in essence, one of configuring the operating points of the three electron guns to conform to three substantially identical output amplifiers.The recently developed economical "unitized gun" type CRT has a combined electron source structure in which three common control grids and three common screen grids are used with the cathodes being the only electrically separate electrodes. The greatly simplified and more economical unitized gun structure, however, imposes some restrictions on the circuitry used to drive the electron sources. Perhaps most significant is the absence of
Color temperature adjustment in a receiver with a unitized gun CRT involves a somewhat different process, namely, configuring the drive and bias applied to each of the gun cathodes to accommodate differences in relative electron source characteristics which, without the equalizing effect of separate screen electrode adjustments, may be considerable.
Initially television receivers using unitized gun CRT's utilized a variable DC voltage divider operative upon each output amplifier to provide adjustment of the DC cutoff voltage. Drive, or signal gain, adjustment to accommodate differences in electron source transconductances was generally accomplished by separate individual gain controls operative on each of the output amplifiers.
However, the more recently developed unitized gun systems combine the DC voltage (cutoff) and signal gain (drive) adjustments for each electron source by simultaneously varying the signal gain and DC voltage in the same direction in a predetermined relationship. One such system used three CRT coupling networks each of which includes a variable impedance simultaneously operative on both the amplitude of coupled signal and DC voltage. Another system uses a variable collector load impedance for each of the output amplifiers, making use of the changes in amplifier signal gain and DC output voltage resulting from collector load variations.
While such systems provide an adequate range of adjustment to achieve color temperature setup using a reduced number of controls, they often degrade image quality. Ideally, the luminance portion of the signal is applied uniformly to each of the three electron sources. Although the relative signal amplitudes may be varied to accommodate transconductance differences between electron sources, it is desirable that each applied signal be an otherwise identical replica of the others. The variable impedance elements in the voltage divider networks and variable collector loads of the prior art interact with the capacities inherent in the output amplifiers and electron gun structures to produce unequal bandwidths for the different color video signals, which cause color changes in their high frequency components (which correspond to detailed picture information). The resulting effect upon the displayed image is similar in appearance to the well-known "color fringing" or misconvergence effect.
OBJECTS OF THE INVENTION
It is an object of the present invention to provide an improved color television receiver.
It is a further object of this invention to provide a novel CRT color temperature setup system.
SUMMARY OF THE INVENTION
In a color television receiver, for processing and displaying a received television signal bearing modulation components of picture information, a
BRIEF DESCRIPTION OF THE DRAWING
The drawing shows a partial-schematic, partial-block diagram representation of a color television receiver constructed in accordance with the present invention.
DESCRIPTION OF THE PREFERRED EMBODIMENT
Referring to the drawing, a signal processor 10 includes conventional circuitry (not shown) for amplifying a received television signal and detecting
the modulated components of luminance and chrominance information therein. The output of signal processor 10 is coupled to a luminance amplifier 11 and a chrominance processor 30. Luminance amplifier 11 is conventional and includes circuitry controlling brightness and contrast of the luminance signal. The output of luminance amplifier 11 is coupled to three luminance-chrominance matrices 12, 13 and 14. Chrominance processor 30 includes conventional chrominance information detection circuitry for providing three color difference or color-minus-luminance output signals (R-Y, G-Y and B-Y) which are individually coupled to luminance-chrominance matrices 12, 13 and 14, respectively. The signal from luminance amplifier 11 is combined with the color-minus-luminance signals from chrominance processor 30 to form the respective red, green and blue video signals which are coupled to the R, G and B output amplifiers 15, 16 and 17, respectively. The outputs of amplifiers 15, 16 and 17 are coupled to the cathode electrodes 23, 24 and 25, respectively, of a CRT 20 having an image screen 21. A voltage divider, formed by a series combination of resistors 83 and 84, is coupled between a source of operating potential +V2 and ground. The junction of resistors 83 and 84 is connected to a common control grid electrode 28 and to ground by a filter capacitor 85 which provides a signal bypass. A potentiometer 80 and a resistor 81 are series coupled between a source of operating potential +V1 and ground, forming another voltage divider. The junction of potentiometer 80 and resistor 81 is connected to common screen grid electrode 29 and to ground by a bypass capacitor 82. Cathode electrodes 23-25, control grid electrode 28 and screen grid electrode 29 are part of a unitized gun structure in CRT 20 with the control grid and screen grid being common to each of the three electron sources defined by the separate cathode electrodes.While luminance-chrominance matrices 12 and 13 are shown in block form, it should be understood that they are identical to the detailed structure of matrix 14. Similarly, red output amplifier 15 and green output amplifier 16 are identical to the detailed structure of blue output amplifier 17. Further, the receiver shown is understood to include conventional circuitry for horizontal and vertical electron beam deflection together with means deriving a CRT high voltage accelerating potential, all of which have, for clarity, been omitted from the drawing.
Luminance-chrominance matrix 14 includes a matrix transistor 40 having an emitter electrode 41 coupled to ground by a resistor 55 and by a series combination of resistors 46 and 47, a base electrode 42 coupled to the output of luminance amplifier 11, and a collector electrode 43 coupled to a source of operating potential +V3 by a resistor 45. The B-Y output of chroma processor 30 is connected to the junction of resistors 46 and 47. An emitte
Blue amplifier 17 includes an output transistor 60 having an emitter electrode 61 coupled to ground by a series combination of resistors 67 and 68, a base electrode 62 connected to the emitter of transistor 50, and a collector electrode 63 coupled to +V2 by a resistor 66. A series combination of a potentiometer 70 and a resistor 69 couples the junction of resistors 67 and 68 to +V3. Collector 63, which is the output of amplifer 17, is connected to cathode 25 of CRT 20.
During signal reception, the separately processed luminance and B-Y color difference signals are applied to matrix transistor 40. The combi
ned signal developed at its collector 43 forms the blue video signal which controls the blue electron beam in CRT 20 and represents the relative contribution of blue light in the image produced.The blue video signal at collector 43 is coupled via transistor 50 to base 62 of output transistor 60. The low source impedance of emitter follower transistor 50 obviates any detrimental effects upon the blue video signal due to loading at the input to amplifier 17 caused by gain or frequency dependent input impedance variations of amplifier 17. The blue video signal applied to base 62 is amplified by transistor 60 to a level sufficient to control the conduction of its respective electron source.
During color temperature setup, a predetermined setup voltage (corresponding to black) is applied to matrices 12, 13 and 14. The voltage on common screen grid electrode 29 is adjusted, by varying potentiometer 80 which together with resistor 81 and capacitor 82 form master conduction means, to cause a low brightness raster to appear on image screen 21. As will be seen, adjustment of potentiometer 70 and the corresponding potentiometers in amplifiers 15 and 16 establish the correct combination of DC electron source cathode voltages and output amplifier gains to produce the selected color temperature at both low and high CRT beam currents.
Amplifier 17 includes a common emitter transistor stage in which the impedance coupled to emitter electrode 6 is a gain and DC output voltage determining impedance. Signal gain is approximately equal to the ratio of the collector impedance (resistor 66), to this gain and DC voltage determining impedance (ignoring the effects of capacities associated with the tr
The DC voltage at collector 63 of transistor 60 is determined by the product of the collector resistance and quiescent collector current (current in the absence of applied signal) and V2. The voltage at base 62 is established by the emitter voltage of transistor 50. Variations in the resistance of potentiometer 70 cause variations in current flow in the series path including potentiometer 70 and resistors 69 and 68. The voltage developed across resistor 68 is supplied to emitter 61 through resistor 67.
In the absence of signal, the DC voltage at base 62 is constant and the relative voltage between base 62 and emitter 61, which controls the conduction level of transistor 60, is a function of the voltage at emitter 61. Increases in the resistance of potentiometer 70 reduce the emitter voltage, increase the relative base-emitter voltage of transistor 60, and increase collector current. The increased collector current develops a greater voltage drop across collector resistor 66 and reduces the DC voltage at collector 63 (and cathode 25). Conversely, a decrease in the resistance of potentiometer 70 increases the voltage at emitter 61, reducing the relative base-emitter voltage and decreasing collector current. The smaller voltage drop across resistor 66 increases the DC voltage at collector 63 and cathode 25.
Thus, increasing the resistance
of potentiometer 70 produces proportionate simultaneous reduction of the DC voltage applied to cathode 25 and the voltage gain of amplifier 17, whereas decreasing the resistance of potentiometer 70 produces proportionate simultaneous increase of the DC voltage and signal gain. As mentioned above, amplifiers 15 and 16 are identical to amplifier 17. In practice only two of the three output amplifiers require adjustment to achieve color temperature setup. However, greater flexibility and optimum use of amplifier signal handling capability is realized if all three output amplifiers are adjustable.As previously mentioned capacities associated with transistor 60, cathode 25 and corresponding interconnections (such as those used to couple collector 63 to cathode 25) are effectively in parallel with collector load resistor 66 forming a partially reactive "coupling network" which exhibits a frequency characteristic (bandwidth) affecting signals coupled therethrough. In practice, the other coupling networks have identical bandwidths and affect their signals in an equal manner. The setup control adjustments of the present invention do not change the characteristics of these coupling networks and the uniformity of signal coupling for the different color signals is preserved. In contrast, conventional adjustment circuitry (whether variable collector load or voltage divider) place variable impedances within these couplings. The varied adjustments of these impedances to effect color temperature control adjustment disturb the bandwidth characteristics of the coupling networks causing differential variations in the individual color video signals.
What has been shown is an RGB CRT drive system which includes output amplifiers each having a single control which simultaneously achieves changes of the DC
output voltage and signal gain of the amplifier in a predetermined relationship. The bandwidths of all three output amplifiers and their associated coupling networks remain substantially undisturbed by these control adjustments during CRT color temperature setup.While particular embodiments of the invention have been shown and described, it will be obvious to those skilled in the art that changes and modifications may be made without departing from the invention in its broader aspects, and, therefore, the aim in the appended claims is to cover all such changes and modifications as fall within the true spirit and scope of the invention.
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