The SABA CHASSIS CM was first monocarrier tv chassis with isolated from mains SMPS power supply circuit with modular design. The CM designator was saying "Computer Modular" explaining the fact that these TV Chassis series was designed with the help of Computer aided design for first time.
- Line deflection UNIT: Horiz-Ablenk-Modul 75 204 200 32 d
- Frame deflection Unit: Vertikal-Ablenk-Modul 75 204 210 00 with MJ900 MJ1000
(Motorola)
- E/W Correction Unit: Ost-West-Modul 75 204 214 00
- Convergence unit
- RGB Ampl Unit: Rgb-Endst-Modul M 75 204 010 00 TBA530- Tymer Clock feature Unit: Uhr/Einblend-Modul 75 209 016 00 AY-5-1232 + AY-5-8320
- Power Supply Unit: Schalt NetzModul M 75 204 007 00
- IF Det /Ampl Unit: ZF/AFC Modul 75 209 401 00 TDA2541
- Luminance / Chrominance Unit : Pal DecoderModul M 75 204 011 00 TDA2522 + TDA2560
- Sound Amplifier Unit: Ton Modul 75 204 012 00 TDA1035 (ITT)
- Synchronization Unit: Synchronisier Modul M 75 204 212 00 TDA2590 (PHILIPS)
TDA2530 RGB MATRIX PREAMPLIFIER
The TDA2530 is an integrated RGB -matrix preamplifier for colour television receivers,
incorporating a matrix preamplifier for RGB cathode drive of the picture tube with
clamping circuits.
The three channels have the same layout to ensure identical frequencybehaviour.
This integrated circuit has been designed to be driven from the TDA2522 Synchronous
demodulator and oscillator IC.
TDA2522 PAL TV CHROMA DEMODULATOR COMBINATION
FAIRCHILD LINEAR INTEGRATED CIRCUIT
GENERAL DESCRIPTION- The TDA2522 is a monolithic integrated circuit designed as
a synchronous demodulator for PAL color television receivers. It includes an 8,8 MHz
oscillator and divider to generate two 4.4 MHz reference signals and provides color difference outputs.
PACKAGE OUTLINE 9B
The TDA2522 is Intended to Interface directly with the TDA2560 with a minimum oF external components. The TDA2530 may be added if RGB drive is required. The TDA2522
is constructed using the Fairchild Planar* process.
TDA2560 LUMINANCE AND CHROMINANCE CONTROL COMBINATION
The TDA2560 is a monolithic integrated circuit for use in decoding systems of COLOR
television receivers. The circuit consists of a luminance and chrominance amplifier.
The luminance amplifier has a
low input impedance so that matching of the luminancedelay line is very easy.
It also incorporates the following functions:
- d.c. contrast control;
- d.c. brightness control;
- black level clamp;
- blanking;
- additional video output with positive-going sync.
The chrominance amplifier comprises:
- gain controlled amplifier;
- chrominance gain control tracked with contrast control;
- separate d.c. satur
ation control:- combined chroma and burst output, burst signal amplitude not affected by contrast and
saturation control;
- the delay line can be driven directly ‘by the IC.
APPLICATION INFORMATION (continued)
The function is quoted against the corresponding pin number
Balanced chrominance input signal (in conjunction with pin 2)
This is derived from the chrominance signal bandpass filter, designed to provide a
push-pull input. A signal amplitude of at least 4 mV peak-to-peak is required
between pins l and 2. The chrominance amplifier is stabilized by an external feedback
loop from the output (pin 6) to the input (pins I and 2). The required level at pins l
and 2 will be 3 V.
All figures for the chrominance signals are based on a colour bar signal with 75%
saturation: i.e. burst-to-chrominance ratio of input signal is 1 1 2.
Chrominance signal input (see pin 1)
A. C.C. input
A negative-going potential, starting at +l,2 V, gives a 40 dB range of a. c. c.
Maximum gain reduction is achieved at an input voltage of 500 mV.
Chrominance saturation control
A control range of +6 dB to >-14 dB is provided over a range of d. c. potential on
pin 4 from +2 to +4 V. The saturation control is a linear function of the control
voltage.
Negative supply (earth)
Chro minance signal output
For nominal settings of saturation and contrast controls (max. -6 dB for saturation,
and max. -3 dB for contrast) both the chroma' and burst are available at this pin, and
in the same ratio as at the input pins 1 and 2. The burst signal is not affected by the
saturation and contrast controls. The a.c. c. circuit of the TDA2522 will hold
constant the colour burst amplitude at the input of the TDA2522. As the PAL delay
line is situated here between the TDA256O and TDA2522 there may be some variation
of the nominal 1 V peak-to-peak burst output of the TDA2560, according to the
tolerances of the delay line. An external network is required from pin 6 of the
TDA256O to provide d. c. negative feedback in the chroma channel via pins I and 2.
Burst gating and clamping pulse input
A two-level pulse is required at this pin to be used for burst gate and black level
clamping. The black level clamp is activated when the pulse level is greater than
7 V. The timing of this interval should be such that no appreciable encroachment
occurs into the sync pulse on picture line periods during normal operation of the
receiver. The burst gate, which switches the gain of the chroma amplifier to
maximum, requires that the input pulse at pin 7 should be sufficiently wide, at least
8 ps, at the actuating level of 2,3 V.
+12 V power supply
Correct operation occurs within the range 10 to 14 V. All signal and control levels
have a linear dependency on supply voltage but, in any given receiver design, this
range may be restricted due to considerations of tracking between the power supply
variations and picture contrast and chroma levels.
Flyback blanking input waveform
This pin is used for blanking the luminance amplifier. When the input pulse exceeds
the +2, 5 Vlevel, the output signal is blanked to a level of about 0 V. When the input
exceeds a +6 V level, a fixed level of about 1, 5 V is inserted in the output. This
level can be used for clamping purposes.
Luminance sigal output
An emitter follower provides a low impedance output signal of 3 V black-to-white
amplitude at nominal contrast setting having a black level in the range 1 to 3 V. An
external emitter load resistor is not required.
The luminance amplitude available for nominal contrast may be modified according
to the resistor value from pin 13 to the +12 V supply. At an input bias current
114 of 0,25 mA during black level the amplifier is compensated so that no black
level shift more than 10 mV occurs at contrast control. When the input current
deviates from the quoted value the black level shift amounts to 100 mV/rnA.
Brightness control
The black level at the luminance output (pin 10) is identical to the control voltage
required at this pin, A range of black level from l to 3 V may be obtained.
Black level clamp capacitor
Luminance gain setting resistor
The gain of the luminance amplifier may be adjusted by selection of the resistor
value from pin 13 to +12 V. Nominal luminance output amplitude is then 3 V
black-to-white at pin 10 when this resistor is 2, 7 l
TDA2541 IF AMPLIFIER WITH DEMODULATOR AND AFC
DESCRIPTION
The TDA2540 and 2541 are IF amplifier and A.M.
demodulator circuits for colour and black and white
television receivers using PNP or NPN tuners. They
are intended for reception of negative or positive
modulation CCIR standard.
They incorporate the following functions : .Gain controlled amplifier .Synchronous demodulator .White spot inverter .Video preamplifier with noise protection .Switchable AFC .AGC with noise gating .Tuner AGC output (NPN tuner for 2540)-(PNP
tuner for 2541) .
VCR switch for video output inhibition (VCRplay back).
.SUPPLYVOLTAGE : 12V TYP
.SUPPLYCURRENT : 50mATYP
.I.F. INPUT VOLTAGE SENSITIVITY AT
F = 38.9MHz : 85mVRMS TYP
.VIDEO OUTPUT VOLTAGE (white at 10% of
top synchro) : 2.7VPP TYP
.I.F. VOLTAGE GAIN CONTROL RANGE :
64dB TYP .SIGNAL TO NOISE RATIO AT VI = 10mV :
58dB TYP
.A.F.C. OUTPUT VOLTAGE SWING FOR
Df = 100kHz : 10V TYP
TDA2590 horizontal oscillator combination
GENERAL DESCRIPTION
— The TDA2590 is a monolithic integrated circuit designed
as a horizontal oscillator combination for TV receivers and monitors.
It is constructed using the Fairchild Planar* process.
LINE OSCILLATOR USING THE THRESHOLD SWITCHING PRINCIPLE
PHASE COMPARISON BETWEEN SYNC PULSE AND OSCILLATOR VOLTAGE (d>1)
PHASE COMPARISON BETWEEN LINE FLYBACK PULSE AND OSCILLATOR VOLTAGE
(<62) Y
SWITCH FOR CHANGING THE FILTER CHARACTERISTIC AND THE GATE CIRCUIT
{WHEN USED FOR VCR)
COINCIDENCE DETECTOR (¢3)
SYNC SEPARATOR
NOISE SEPARATOR
VERTICAL SYNC SEPARATOR AND OUTPUT STAGE
COLOR BURST KEYING AND LINE FLYBACK BLANKING PULSE GENERATOR
PHASE SHIFTER FOR THE OUTPUT PULSE
OUTPUT PULSE DURATION SWITCHING
OUTPUT STAGE FOR DIRECT DRIVE OF THYRISTOR DEFLECTION CIRCUITS
SYNC GATING PULSE GENERATOR
LOW SUPPLY VOLTAGE PROTECTION.
SABA ULTRACOLOR CHASSIS CM Controlled power supply for a television receiver equipped with remote control:BLAUPUNKT SWITCH MODE POWER SUPPLY.Blaupunkt-Werke GmbH (Hildesheim, DT)
A single isolation transformer supplies both the remote control receiver and the television receiver. A pulse generator such as a blocking oscillator which energizes the primary winding of the isolation transformer has its pulse width controlled in response to the loading of the circuit of the secondary winding of the isolation transformer, as measured by the voltage across a resistor in the circuit of a primary winding. This measuring resistor is interposed between the emitter of the switching transistor of the blocking oscillator and the receiver chassis. A transistor switching circuit for cutting off the low voltage supply to the scanning circuit oscillators of the television receiver is responsive to the output of the remote control receiver, to a signal from an operating control of the television receiver, and to an indication of overcurrent in the picture tube, independently.
an on-off switch for connecting and disconnecting the television receiver and its power supply circuit respectively to and from the electricity supply mains;
pulse generating means arranged for energization through said on-off switch;
an isolation transformer having its primary winding supplied with the output of said pulse generating means;
a power conversion circuit connected to the secondary winding of said isolation transformer for energization thereby, for supplying an operating voltage for the scanning circuits of the television receiver and for supplying a plurality of other voltages to said receiver, at least one of which other voltages is also supplied to said scanning circuits;
means for reducing energy transfer through said pulse generating means to said isolation transformer when said television receiver is in the stand-by condition.
2. A power supply circuit as defined in claim 1, in which said pulse generating means includes rectifying means energized through said on-off switch for supplying direct current for energization of said pulse generating means. 3. A power supply circuit as defined in claim 2, in which said energy transfer reducing means includes means for varying the width (duration) of pulses generated by said pulse generating means in response to the extent of loading of the secondary circuit of said isolating transformer as measured in the primary circuit of said transformer. 4. A power supply circuit as defined in claim 2, in which said pulse generating means includes a blocking oscillator and said energy transfer reducing means includes means for reducing the width (duration) of the pulses generated by said blocking oscillator. 5. A power supply circuit as defined in claim 4, in which said blocking oscillator includes a switching transistor (5) and a load measuring resistor (7) interposed in a connection between the emitter of said switching transistor and the receiver chassis, and in which said pulse width reducing means is responsive to the voltage drop across said load measuring resistor. 6. A power supply circuit as defined in claim 5, in which said pulse width reducing means includes a controllable resistance (10) in the circuit of said blocking oscillator controlled in response to the voltage drop across said load measuring resistor. 7. A power supply circuit as defined in claim 1, in which said operating voltage connected and disconnected to said scanning circuits by said controlled switching means is the low voltage supply voltage (U 3') of the line scan and picture scan oscillators of the television receiver and in which said controlled switching means is controlled so as to switch off said low voltage supply voltage to put the television receiver in the stand-by condition. 8. A power supply circuit as defined in claim 7, in which said controlled switching means includes a first switching transistor (15) at the collector of which there is applied a direct current supply voltage (U 3) energized through said isolating transformer and a second switching transistor (24) for controllably short-circuiting the base bias of said first switching transistor, whereby a stabilized low voltage (U 3') exists at the emitter of said first switching transistor (15) when a positive signal is supplied from an operating control of the television receiver or from said remote control receiver to the base of said second switching transistor (24). 9. A power supply circuit as defined in claim 7, in which said controlled switching means is responsive independently to an overcurrent condition in the picture tube for switching off said low voltage supply voltage (U 3') in response to said overcurrent condition.
Description:
In recent times television receivers have frequently been provided with ultrasonic remote control devices for the purpose of offering easier control. As more and more television receivers are utilized in combination with additional equipment, it becomes increasingly necessary to connect the receivers only indirectly to the electric power mains (house wiring). In a known advantageous solution of this problem, a power supply unit includes an isolating transformer which is wired up with a blocking oscillator in the primary circuit. The blocking oscillator is supplied with a d-c voltage which is obtained by rectification of the supply voltage. Compared to the isolating transformers which are directly mains-operated, these so-called switch-mode power supply units have the advantage that they can be made in considerably smaller size, as they are operated at a significantly higher frequency, and the further advantage that they require less expensive means for rectification.
It is necessary to supply television receivers equipped with ultrasonic remote control with the possibility for a stand-by operation in which only the ultransonic receiver is supplied with power and, in some cases, also the heating current for the picture tube. Usually a separate power supply unit is provided for the ultrasonic receiver and the heating of the picture tube, a unit that includes an isolating transformer of its own, the primary winding of which is directly mains-fed. Upon transition from normal operation to stand-by operation, the power supply unit of the blocking osciallator is switched off, so that the television receiver receives only the relatively small quantity of energy required for the ultrasonic receiver and, in some cases, also for the heating of the picture tube.
Because of the required second isolating transformer, this known circuit has the disadvantages that it requires both greater space and greater expenditure.
It is the object of the present invention to develop a simplified power supply unit which does not have the above-mentioned disadvantages.
SUMMARY OF THE INVENTION
Briefly, the television receiver and the ultrasonic receiver are connected to the same isolating transformer; means for the switching from normal operation to stand-by operation and vice versa are placed in the secondary circuit of the isolating transformer, and means are arranged in the primary circuits of the isolating transformer for reducing the amount of energy made available for stand-by operation purposes.
The main advantages of the present invention are that no separate isolating transformer is required for supplying the current during the stand-by operation, and that, during the stand-by operation, it is nevertheless only the power required for this operation which is consumed.
An advantageous embodiment of the present invention obtains reduction of the energy quantum transmitted through the power supply during stand-by by reduction of the pulse width of the pulses generated by the blocking oscillator.
Another advantageous embodiment of the present invention utilizes measurement in the primary circuit of the isolating transformer of variation in load occurring in the secondary circuit as a control variable for determining the pulse width.
A further advantageous embodiment of the present invention obtains the control variable for the pulse width across a measuring resistor interposed in the connection of the emitter of the switching transistor of the blocking oscillator to the chassis.
Still another advantageous embodiment of the present invention provides that the voltage drop across the measuring resistor controls a controllable resistor.
The advantageous embodiments described above offer highly simple and advantageous possibilities for measuring the variation in load upon switching between normal and stand-by operation, as well as for the consequent control of the energy transmitted via the isolating transformer.
The possibility of a simple and inexpensive switching between normal and stand-by operation is achieved by effecting the switching between normal and stand-by operation by means of switching on or switching off, respectively, the low voltage supply of the line scan oscillator, and, especially, by a first switching transistor which short-circuits the base bias of a second switching transistor at the collector of which a direct current supply voltage is present and at the emitter of which a stabilized low voltage exists, when a positive signal is supplied from the operating control of the television receiver or from the remote control receiver to the base of the first switching transistor.
The circuit arrangements just mentioned offer the advantage that they may simultaneously be utilized as a protective circuit. This is achieved by a switching-off device for the low voltage which can also be triggered at any time by a signal built up by overcurrent in the picture tube.
The invention is further described by way of illustrative example by reference to the annexed drawings in which:
FIG. 1 is a circuit diagram, partly in block form, of an embodiment of the invention;
FIG. 2 is a circuit diagram of one form of means for interrupting the power to the picture circuits in the stand-by condition in connection with the circuit of FIG. 1, and
FIG. 3 is a circuit diagram of one way of controlling the pulse width of the blocking oscillator 4 in response to the switching circuit 8 in the circuit of FIG. 1.
DESCRIPTION OF THE PREFERRED EMBODIMENT
An on-off power switch 2 of the television receiver is connected to the supply terminals 1, providing a primary operating control for the receiver. Consquently, the supply voltage is also present at the output of the operating control 2 when the television receiver is turned on thereby, and arrives at a rectifying stage 3 comprising means for rectifying and smoothing the supply current as well as for suppressing interference. A d-c voltage, feeding a blocking oscillator stage 4, is present at the output of the recifying stage 3. The main part of the blocking oscillator 4, symbolically represented in FIG. 1 by a fragmentary circuit diagram, is a switching transistor 5, in the load circuit of which the primary winding of an isolating tranformer 6 is placed. A measuring resistor 7 is connected between the emitter of the switching transistor 5 and the chassis, across which measuring resistor a voltage is taken and applied to a load-dependent control circuit 8. The voltage taken at the measuring resistor 7 is fed via a resistor 9 to the base of a transistor 10 which serves as a controllable load for the blocking oscillator 4. A resistor 11 and a capacitor 12, each of which is connected to chassis with its other terminal, are also connected to the base of the transistor 10. The emitter of transistor 10 is connected to chassis, while the collector of the transistor 10 is connected back to the blocking oscillator stage 4.In the secondary circuit of the isolating transformer 6, a d-c voltage supply stage or power conversion circuit 13 is placed, substantially consisting of a rectifying circuit 14, which, in the example shown, is provided with six outputs at which the voltages U 1 to U 5 can be taken off with respect to the sixth output connected to the chassis. At the terminal U 3, there is, in addition, a branch feeding both the collector-to-emitter path of the transistor 15 and also, through a resistor 16, the collector-to-emitter path of the transistor 15a. The emitter of the transistor 15a is directly connected to the base of transistor 15. The emitter of the transistor 15 is connected to chassis via a series connection of a resistor 17, a potentiometer 18, and a further resistor 19. The tap of the potentiometer 18 is connected to the base of a further transistor 20. The transistor 20 is connected to chassis by means of its emitter via a Zener diode 21, the collector of the transistor 20 controlling the base of the transistor 15a. The emitter of the transistor 20 is connected to the emitter of the transistor 15 via a resistor 22. A terminal for tapping off the voltage U 3' is connected to the emitter of the transistor 15.The base of the transistor 15a is connected to a switching stage 23 responsive to a remote control ultrasonic receiver by a conductor leading to the collector of a switching transistor 24 which is connected to chassis via its emitter. The base of the switching transistor 24 is connected to an input terminal 28 leading into the television receiver via two resistors 25, 26 and a capacitor 27 connected in series, that input terminal 28 passing on switching signals from the receiver to the switching transistor 24, as will be explained in more detail below.
The cathode of a diode 29, which is connected to chassis via its anode, is connected to the junction point of the resistor 26 and the capacitor 27. The junction point of the two resistors 25, 26 is connected to chassis via a capacitor 30. The base of the switching transistor 24 is connected to chassis via a resistor 31. Furthermore, that base electrode is also connected to a terminal 32 to which an electrical switching signal is applied which is either built up in response to an ultrasonic signal received by the remote control receiver 32' or is supplied from an operating control of the television receiver. At the terminal 32, the switching transistor 24 receives the signal containing the information whether the television receiver is to work in the normal operating condition, i.e. to receive and process the sound and video signals, or in the stand-by condition in which it is substantially only the ultrasonic receiver that is supplied with current.
When a positive signal arrives at the base of the switching transistor 24, the latter becomes conductive, and causes chassis potential to be present at the base of transistor 15a. The transistor 15 is thereby blocked, and there is no longer any voltage at the terminal U 3'. Since the voltage U 3' serves as an operating voltage for the line and picture scan oscillator, the deflecting stages of the receiver cannot work and no high voltage and other related supply voltages are generated at the line circuit transformer. In consequence, by means illustrated diagrammatically in
FIG. 2, the electric circuits connected to the terminals U 1 to U 3 are interrupted. The voltages U 4 and U 5 serve for supplying the ultrasonic receiver, i.e. they are required for the stand-by operation.In case no counteracting means should be provided for, the variation in load would cause a voltage rise in the secondary circuit of the isolating transformer 6, which effect is, of course, not desired. Therefore, a measuring resistor is connected in the primary circuit in the emitter line of the switching transistor 5 of the blocking oscillator 6, the variation in load in the secondary circuit appearing at the measuring resistor 7 as a current variation. The current change thus produced, causes a variation in the base bias of the transistor 10, the capacitor 12 having an integrating effect to avoid undesired effects due to interference pulses and abrupt load fluctuations.
The change of the working point of the transistor 10 causes a change in the pulse width in the blocking oscillator stage 4, as more fully shown in FIG. 3, so that the energy quantum transmitted via the isolating transformer 6 is such that the required voltages are present in the secondary circuit. It should also be mentioned that the load-dependent switch 8 and the circuit of FIG. 3 are represented only by way of illustration and that many circuit arrangements may be devised by straight-forward application of known principles for controlling the pulse width.
Using the circuit diagram according to FIG. 3 it is possible in a simple manner to control the pulse width of the blocking oscillator 4 in response to the switching circuit 8.
According to the circuit diagram of FIG. 2 the terminal U1 is connected to a line scan oscillator circuit 40, the terminal U2 to a picture scan oscillator circuit 41 and the terminal U3 to a circuit 42 for a sound output stage. The circuits 40, 41, 42 get their operating voltage from the terminal U3'. If the operating voltage U3' is zero, the circuits 40, 41, 42 are interrupted. In this case the voltages at the terminals U1, U2, U3 remain.
The blocking oscillator stage 4 shown in detail in FIG. 3 incorporates an externally triggered blocking oscillator arranged to be triggered through an oscillator operating preferably at the line scanning frequency, which is to say its wave form is not particularly critical and it should be provided with means to keep it in step with the line scanning frequency, as is known to be desirable. The transistors 51 and 52 of the triggered output stage of the blocking oscillator circuit could be regarded as constituting a differential amplifier the inputs of which are defined by the base connections of the respective transistors 51 and 52. The input voltage applied to the base connection of transistor 52 is the Zener voltage of the Zener diode 53, thus a constant reference voltage. The operating voltage for the transistors 51 and 52 and for the Zener diode 53 is obtained from the supply voltage UB, which is to say from the rectifier 3. The diode 67 protects the transistor 52, for example at the time of the apparatus being switched on, against damage from an excessively high emitter-base blocking voltage. The capacitor 65 prevents undesired oscillation of the circuit of transistors 51 and 52, which could give rise to undesired disturbances.
At the base of the transistor 51, there is present as input voltage for the circuit a composite voltage that is the sum of three voltages. These are, first, the line scan frequency trigger voltage coupled through the capacitor 63; second, a bias voltage dependent upon the loading of the blocking oscillator stage resulting from the load on the secondary of the transformer 6, but detected by the voltage across the resistor 7 and actually controlled by the load-sensitive control circuit 8, and, third, a regulating voltage applied at the terminal 71 of the resistor 70, which regulating voltage is proportional to the voltage of the secondary winding of the transformer 6 and can accordingly be provided by one or another of the output circuits of the rectifier 14 of FIG. 1 or by a separate winding of the transformer 6 and a separate rectifier element connected in circuit therewith. This regulating voltage and the control voltage provided by the control circuit 8 are applied to the resistor 61 which completes the circuit for both of these bias voltages and their combined effect constitutes the bias voltage for the transistor 51 which determines its working point.
The circuit of the transistors 51 and 52 operates as an overdriven differential amplifier. When the trigger voltage exceeds the threshold determined by the base voltage of the transistor 51, the circuit produces an approximately rectangular output voltage pulse of constant amplitude. Since the trigger voltage is recurrent, the result is a periodic succession of rectangular output voltage pulses, but the duration or pulse width of these pulses depends upon the loading and the output voltage of the stage. The output voltage of the circuit constituted by the transistors 51 and 52 comes from the emitter connection of the transistor 52 and is furnished to the switching transistor 5, preferably through a driver stage 54, such as a transformer or another transistor stage for better matching of the circuit impedances. Of course, the collector circuit of the transistor 5 includes the primary winding of the transformer 6 of FIG. 1.
SABA ULTRACOLOR T6771 I32 CM TELECOMMANDER CHASSIS CM110 75 205 000 30 Receiver tuning circuit with automatic search and AFC using common capacitor:
The most common type of voltage-dependent variable-reactance device is a diode which has an interelectrode capacitance directly proportional to its reverse-bias voltage, commonly referred to as a "Varicap" or "varactor" diode. By placing one or more such diodes in the frequency-selecting portion of a tuner, station selection may be achieved by progressively increasing or decreasing the voltage applied to the diode(s) until the desired frequency is obtained. Moreover, by combining a varactor-diode tuner with a progressively variable DC control voltage generator, a signal detector, and a feedback control loop, a satisfactory solid-state signal-seeking system may be created.
In conventional signal-seeking systems employing varactor diodes, however, a temporary loss of signal resulting from "airplane flutter," transmitter failure, etc., or even receiver deenergization, varies (or eliminates) the control voltage and/or interrupts the recognition signal from the signal detector and therefore sends the system seeking for a new station. The addition of complex delay circuitry for temporarily maintaining the DC control voltage not only adds appreciable cost to the system but also does not compensate for the loss of control voltage due to receiver deenergization such as when the receiver is turned off for a while.
It is therefore an object of the invention to provide a new and improved signal-seeking system for a voltage-controlled tuner.
It is a more specific object of the invention to provide such a new and improved signal-seeking tuning system which is immune to undesired signal-seeking resulting from a temporary loss of signal or receiver deenergization.
A station finder which switches to automatic frequency control during automatic finding in case of reception of a transmitter and, if desired, continues to find a transmitter some time later with the frequency control switched off.
1. A receiver tuning circuit f
2. A receiver tuning circuit as claimed in claim 1, wherein said operating device has a supply lead and the time constant circuit is coupled to the supply lead of the operating device.
3. A receiver tuning circuit as claimed in claim 1, wherein the detection circuit is coupled to an output of a frequency detector and includes a means for preventing pulling in on the same transmitter upon activation of said search tuning circuit.
Description:
The invention relates to a receiver tuning circuit including a search tuning circuit which can be activated by a control device in which the search tuning circuit is automatically switched off when a received station is detected by a detection circuit and an automatic frequency control circuit is switched on, and in which a time constant circuit changes the state of the receiver tuning circuit after a certain time.A receiver tuning circuit of the kind described above is known from German Offenlegungsschrift 2,023,352 which after activation of the search tuning stops the search action when a transmitter transmitting a pilot signal is received and switches on an automatic frequency control circuit. The search tuning circuit must again be a
This known tuning circuit is only suitable for special receivers. An object of the invention is to provide a tuning circuit which is more suitable for other receiver types.
To this end a receiver tuning circuit of the kind described in the preamble according to the invention is characterized in that the time constant circuit is incorporated in the tuning circuit in such a manner that again and again it switches on the search tuning circuit a certain time after having automatically switched it off and switches off the automatic frequency control as long as the search tuning circuit is maintained operative with the aid of the operating device.
By using the step according to the invention a receiver is obtained which upon activation of the search tuning circuit receives without distortion transmitter after transmitter each during a time determined by the time constant circuit. The search tuning can be rendered inactive with the aid of the operating device after the desired station has been found. The tuning circuit is very suitable for radio or television receivers for domestic use.
SABA ULTRACOLOR T6771 I32 CM TELECOMMANDER CHASSIS CM110 75 205 000 30 Method and system for increasing the number of instructions transmitted in digital systems, I.A. in systems for remote control of television receiver:ITT VOLTAGE SYNTHESIZER TUNING SEARCH SYSTEM
Method of increasing the number of instructions according to the invention consists therein that withing the command signal (6) additional instructions are transmitted, which after being decoded in the instruction decoder (1) and processed in the strobbin signal generation circuit (4) strobes the operation of additional controlled units (5) and control the transmission of the signal through the register (2) to the controlled units (3).
In the system according to the invention, between one of the outputs od the instruction decoder (1) and the unit (3) to be controlled the register (2) is connected, provided with an additional input for the record inhibiting instruction (10), whereas to the second output of the instruction decoder (1) the strobbing signal generation circuit (4) is connected aimed at controlling the additional controlled units (5). The register (2) and the strobbing signal generation circuit (4), employed in the system according to the invention, can be built-in into each of the integrated circuits or made in form of a separate integrated circuit.1. A method of increasing the number of instructions transmitted in remote control systems of television receivers and the like in which decoded signals directly control receiving units, comprising transmitting coded instructions in a command signal (6), decoding said instructions into a first part of an instruction signal (8), processing said first part of the instruction signal (8) in a strobing signal generation circuit (4) to provide a first signal (10) in a form for enabling the transmission of a control signal (7) through a register (2) in the form of a stored signal (11) to first receiving units (3) to be controlled while simultaneously providing a second signal (9) in a form for blocking the reception of one of said instruction signal (8) and said control signal (7) by additional receiving units (5) to be controlled, transmitting an additional coded instruction in said command signal, decoding said additional instruction into a second part of the instruction signal (8), processing said second part of the instruction signal (8) in said strobing signal generation circuit (4) to provide said first signal (10) in a form for blocking furthe
Description:
This invention relates to a method and a system making it possible to increase the number of instructions transmitted in systems of remote control of television or radio receivers, and the like.
One of the known remote control systems is a system based on integrated circuits of the firm ITT. Similarly as in other systems, the instructions transmitted remotely are coded by a transmitter, for instance SAA1024, in an electric signal modulating a wave being able to propagate in the environment. In the receiver for instance SAA 1130, the coded electric signal is received and gives at its outputs the completely decoded output information signal and decoded output control signals.
In known application notes of the firm ITT the decoded output control signals control directly the receiving devices SAA1021, SAA1020. The decoder of information transmits also other decoded control signals, for instance analog adjustment signals, turning a signal on the power supply, and other signals necessary for the operation of the system. A certain part of the total number of instructions transmitted in the coded input signal constitutes a group of additional instructions for decoding by an additional instructions decoder controlled by the output signal.
The method of increasing the number of instructions transmitted in digital systems, i.a. in remote control systems of television receivers, according to the invention comprises transmitting in the control signal additional instructions which, on being decoded in an instruction decoder and after processing in a circuit for generating strobing signals, strobe the operation of additional controlled devices and control the transmission of the control signal through a register to main controlled units. In the system according to the invention two variants of operation of the system are distinguished. In the first variant an inhibiting signal coming out of the strobing signal generation circuit enables storage by the register of the real values being decoded, the output control signals, and controls with a suitable signal the main controlled units, while blocking by another suitable signal the additional controlled devices. In the second variant of the method according to the invention, after transmission of the additional instruction in the input signal, the storage inhibiting signal inhibits the register which stores the previous instruction and interruptedly controls the controlled unit, whereby simultaneously another strobing signal enables the additional controlled units to receive the controlling instruction.
In the system according to the invention the controlling of additional units is performed in the course of uninterrupted operation of controlled units.
In the system for increasing the number of instructions transmitted in digital systems, i.a. in remote control systems of television receivers, according to the invention, between one output of the instruction decoder and first controlled units a register is connected, having an additional input for a recording inhibiting signal, whereas to another output of the instruction decoder a strobing signal generation circuit is connected for controlling additional controlled units.
The inputs of the additional controlled units are connected with any outputs of the instruction decoder and with outputs of a register of the strobing circuit. The register and the strobing generation circuit, employed in the system according to the invention, can be built-in in one integrated circuit or may be made in the form of separate integrated circuits.
Referring to the aforement
ioned system of the firm ITT, the list of instructions thereof comprises 10 instructions used for basic servicing of the television receivers, 16 instructions for program selection and 5 additional instructions. In the method according to the invention, by using all the additional instructions, additionally 5×16 instructions are obtained. The number of all useful instructions in the method according to the invention amounts to 10+16+5×16=106 instructions, and thus by 75 instructions more than it was foreseen by the manufacturer of said systems.
Employing of the method and the system in a simple constructional arrangement enables one to multiply the number of transmitted signals, and simultaneously the number of units to be controlled. With reference to the system of the firm ITT, based on integrated circuits SAA1024, SAA1130, SAA1021, SAA1020, this enables one to employ additionally a teletext, a time programmer, an electronic watch, remote control of a radio receiver, tuning of a second head to observe another program, and other uses that were not possible and not foreseen by the manufacturer of said circuits.
The method and system according to the invention will be now described by means of an exemplary embodiment with reference to the accompanying drawing, wherein:
FIG. 1 is the block diagram of the system, and
FIG. 2 is the connection diagram of the strobing circuit.
The system of an instruction invention consists of the decoder 1, one output of which is connected through a register 2 with units 3 to be controlled. Another output of the instruction decoder 1 is connected with a strobing signal generation system 4 to the output of which is connected an additional controlled unit 5 having inputs connected with either output of the decoder 1.
The strobing circuit 4 is equipped with a decoder 12 an output 13 of which is connected with the clearing input of a register 14, and outputs 15, 16, 17, 18 of which are connected with the recording inputs of the register 14. The registers outputs 19, 20, 21, and 22, however, are connected with the additional unit 5 (FIG. 1) and with an adding gate 23, the output 10 of which is connected with the record inhibiting input of the register 14 and with the record inhibiting input of the register 2.
In the method according to the invention, the control signal 6 received by the instruction decoder 1 is decoded into groups of instructions 7 and 8. The instructions 8 after being processed in the strobing signal generating circuit 4 strobe the operation of additional devices 5 in the form of a signal 9, and in the form of the inhibiting signal 10 they control the operation of the register 2. A part of instructions 8, after processing in the strobbing circuit 4, enables with the signal 10 the transmission of the instructions 7 through the reg
ister 2 to the controlled units 3 in the form of the decoded control signal 11. Simultaneously, the decoded instruction 8 blocks with the strobing signal 9 the receiving of instructions 7 or 8 by the additional units 5 to be controlled. After transmitting the additional information from the second part of the instructions 8 in the signal 6, the instruction 8 after processing in the strobing signal generating circuit 4 blocks with the signal 10 the register 2, which stores the previous signal 7 and uninterruptedly controls the units 3 to be controlled, and simultaneously enables the additional controlled units 5 to receive instructions 7 or 8. The transmission of an erasing instruction in the signal 6 causes the return to the previous way of transmission and the turning off of the additional units 5.
The controlling of additional units 5 in the method according to the invention by means of the signal 7 or 8 is performed in the course of uninterrupted controlling of the units 3 by means of the signal 11 from the register 2.
One of the known remote control systems is a system based on integrated circuits of the firm ITT. Similarly as in other systems, the instructions transmitted remotely are coded by a transmitter, for instance SAA1024, in an electric signal modulating a wave being able to propagate in the environment. In the receiver for instance SAA 1130, the coded electric signal is received and gives at its outputs the completely decoded output information signal and decoded output control signals.
In known application notes of the firm ITT the decoded output control signals control directly the receiving devices SAA1021, SAA1020. The decoder of information transmits also other decoded control signals, for instance analog adjustment signals, turning a signal on the power supply, and other signals necessary for the operation of the system. A certain part of the total number of instructions transmitted in the coded input signal constitutes a group of additional instructions for decoding by an additional instructions decoder controlled by the output signal.
The method of increasing the number of instructions transmitted in digital systems, i.a. in remote control systems of television receivers, according to the invention comprises transmitting in the control signal additional instructions which, on being decoded in an instruction decoder and after processing in a circuit for generating strobing signals, strobe the operation of additional controlled devices and control the transmission of the control signal through a register to main controlled units. In the system according to the invention two variants of operation of the system are distinguished. In the first variant an inhibiting signal coming out of the strobing signal generation circuit enables storage by the register of the real values being decoded, the output control signals, and controls with a suitable signal the main controlled units, while blocking by another suitable signal the additional controlled devices. In the second variant of the method according to the invention, after transmission of the additional instruction in the input signal, the storage inhibiting signal inhibits the register which stores the previous instruction and interruptedly controls the controlled unit, whereby simultaneously another strobing signal enables the additional controlled units to receive the controlling instruction.
In the system according to the invention the controlling of additional units is performed in the course of uninterrupted operation of controlled units.
In the system for increasing the number of instructions transmitted in digital systems, i.a. in remote control systems of television receivers, according to the invention, between one output of the instruction decoder and first controlled units a register is connected, having an additional input for a recording inhibiting signal, whereas to another output of the instruction decoder a strobing signal generation circuit is connected for controlling additional controlled units.
The inputs of the additional controlled units are connected with any outputs of the instruction decoder and with outputs of a register of the strobing circuit. The register and the strobing generation circuit, employed in the system according to the invention, can be built-in in one integrated circuit or may be made in the form of separate integrated circuits.
Referring to the aforement
Employing of the method and the system in a simple constructional arrangement enables one to multiply the number of transmitted signals, and simultaneously the number of units to be controlled. With reference to the system of the firm ITT, based on integrated circuits SAA1024, SAA1130, SAA1021, SAA1020, this enables one to employ additionally a teletext, a time programmer, an electronic watch, remote control of a radio receiver, tuning of a second head to observe another program, and other uses that were not possible and not foreseen by the manufacturer of said circuits.
The method and system according to the invention will be now described by means of an exemplary embodiment with reference to the accompanying drawing, wherein:
FIG. 1 is the block diagram of the system, and
FIG. 2 is the connection diagram of the strobing circuit.
The system of an instruction invention consists of the decoder 1, one output of which is connected through a register 2 with units 3 to be controlled. Another output of the instruction decoder 1 is connected with a strobing signal generation system 4 to the output of which is connected an additional controlled unit 5 having inputs connected with either output of the decoder 1.
The strobing circuit 4 is equipped with a decoder 12 an output 13 of which is connected with the clearing input of a register 14, and outputs 15, 16, 17, 18 of which are connected with the recording inputs of the register 14. The registers outputs 19, 20, 21, and 22, however, are connected with the additional unit 5 (FIG. 1) and with an adding gate 23, the output 10 of which is connected with the record inhibiting input of the register 14 and with the record inhibiting input of the register 2.
In the method according to the invention, the control signal 6 received by the instruction decoder 1 is decoded into groups of instructions 7 and 8. The instructions 8 after being processed in the strobing signal generating circuit 4 strobe the operation of additional devices 5 in the form of a signal 9, and in the form of the inhibiting signal 10 they control the operation of the register 2. A part of instructions 8, after processing in the strobbing circuit 4, enables with the signal 10 the transmission of the instructions 7 through the reg
ister 2 to the controlled units 3 in the form of the decoded control signal 11. Simultaneously, the decoded instruction 8 blocks with the strobing signal 9 the receiving of instructions 7 or 8 by the additional units 5 to be controlled. After transmitting the additional information from the second part of the instructions 8 in the signal 6, the instruction 8 after processing in the strobing signal generating circuit 4 blocks with the signal 10 the register 2, which stores the previous signal 7 and uninterruptedly controls the units 3 to be controlled, and simultaneously enables the additional controlled units 5 to receive instructions 7 or 8. The transmission of an erasing instruction in the signal 6 causes the return to the previous way of transmission and the turning off of the additional units 5.The controlling of additional units 5 in the method according to the invention by means of the signal 7 or 8 is performed in the course of uninterrupted controlling of the units 3 by means of the signal 11 from the register 2.
SABA ULTRACOLOR T6771 I32 CM TELECOMMANDER CHASSIS CM110 75 205 000 30 UniLine Assymetric top-bottom pincushion correction circuit
In a top-bottom pincushion correction circuit having a saturable reactor with a control winding coupled to a source of deflection current at a horizontal scan frequency and an output winding coupled to a source of deflection
current at a vertical scan frequency, a means coupled to the control winding unbalances the waveform applied thereto from the source of deflection current at a vertical scan frequency to provide asymmetric top-bottom pincushion correction.
1. In a cathode ray tube scanning system having a cathode ray tube with an associated deflection yoke which includes horizontal and vertical deflection windings coupled to a source of deflection current at horizontal and vertical scan frequencies and a top and bottom pincushion correction circuit having a saturable reactor with a control winding coupled to the source of deflection current at a horizontal scan frequency and an output winding coupled to a source of deflection current at a vertical scan frequency and to a shunt connected capacitor and impedance, the improvement comprising:
In a top-bottom pincushion correction circuit having a saturable reactor with a control winding coupled to a source of deflection current at a horizontal scan frequency and an output winding coupled to a source of deflection
current at a vertical scan frequency, a means coupled to the control winding unbalances the waveform applied thereto from the source of deflection current at a vertical scan frequency to provide asymmetric top-bottom pincushion correction.1. In a cathode ray tube scanning system having a cathode ray tube with an associated deflection yoke which includes horizontal and vertical deflection windings coupled to a source of deflection current at horizontal and vertical scan frequencies and a top and bottom pincushion correction circuit having a saturable reactor with a control winding coupled to the source of deflection current at a horizontal scan frequency and an output winding coupled to a source of deflection current at a vertical scan frequency and to a shunt connected capacitor and impedance, the improvement comprising:
means coupled to said output winding for unbalancing the waveform applied thereto from said source of deflection current at a vertical s
can frequency to provide asymmetric top-bottom pincushion correction, said means of a form to provide a substantially constant crossover point of said waveform.
can frequency to provide asymmetric top-bottom pincushion correction, said means of a form to provide a substantially constant crossover point of said waveform.
2. The improvement of claim 1 wherein said means for unbalancing the waveform applied to said control winding is in the form of a series connected unidirectional conduction device and impedance shunting said control winding. 3. The improvement of claim 2 wherein said series connected unidirectional conduction device and impedance are in the form of a series connected diode and alterable impedance. 4. The improvement of claim 2 wherein said impedance shunting said control winding is alterable to effect control of the amount of unbalance or asymmetry between top and bottom pincushion correction waveform. 5. In a top and bottom pincushion correction circuit for a cathode ray tube scanning system wherein the correction circuit includes a saturable reactor with a control winding coupled to a source of deflection current at a horizontal scan frequency and an output winding shunted by a parallel coupled capacitor and impedance and coupled to a source of deflection current at a vertical scan frequency, the improvement comprising:
a series connected unidirectional conduction device and impedance coupled to said output winding for controlling the asymmetry of a top and bottom pincushion correction waveform.
6. The improvement of claim 5 wherein said means for controlling the assymetry of a top and bottom pincushion correction waveform is in the form of a series connected diode and alterable resistor shunting said control winding. 7. The improvement of claim 6 wherein said alterable resistor provides control of the amount of asymmetry of the top to bottom pincushion correction waveform. 8. The improvement of claim 6 wherein said series connected diode and alterable resistor effect unbalance of said pincushion correction waveform with respect to a substantially constant crossover point.
Description:
CROSS-REFERENCE TO OTHER APPLICATIONS
A co-pending application entitled "Top-Bottom Pincushion Correction Circuit" bearing U.S. Ser. No. 622,134, now U.S. Pat. No. 3,982,156, filed Oct. 14, 1975 in the name of Tex K. Monroe and assigned to the Assignee of the present application provides a pincushion correction circuit of improved efficiency wherein ringing current of a control winding are transferred to an output winding.
BACKGROUND OF THE INVENTION
This invention relates to top-bottom pincushion correction circuits and more particularly to apparatus for providing an unbalanced top-bottom pincushion correction signal.
As is well known in the cathode ray tube scanning art, the displayed raster of a cathode ray tube is composed of successively spaced horizontal scan lines forming a substantially rectangular-shaped raster. Although the raster is desirably rectangular under normal operation conditions, it is well known that such a desirable condition fails to exist in almost all instances and the raster is distorted in a manner which has become known as top-bottom pincushion distortion.
As is well-known, top-bottom pincushion distortion is indicated by the departure of the horizontal scan lines from a straight-line configuration. Specifically, the horizontal scan lines at the top half of the raster tend to bow downwardly toward the center while the horizontal scan lines at the bottom half of the raster tend to bow upwardly toward the center of the raster.
Also, it is well-known, many modern television receivers have picture tubes mounted near the floor or at least below the normal level of viewer observation. Thus, the average viewer looks down at the raster on the picture tube which has the effect of making normally straight lines near the top of the raster appear bowed inwardly at the center. At the bottom of the raster, the normally straight lines appear to be bowed outward or barrelled at the center of the raster.
One known prior art technique for overcoming the above-described distortion problems was to utilize a movable bias magnet whereby a magnetic field was employed to set up a field in the pincushion transformer to compensate for the distortions. In another method, a DC current was added to the ramp-like waveform of the pincushion correction voltage applied to the vertical windings of the deflection yoke in an effort to provide a desired upbalance in the resultant raster of the cathode ray tube.
Although the above-mentioned methods provided some relief and were reasonably successful, they did leave much to be desired. For example, altering the magnetic flux with a magnet or adding a DC current to effect unbalance of the pincushion correction waveform tends to undesirably alter the crossover point or the point whereat the waveform shifts from one polarity to the other. As a result, the total raster is affected rather than only the positive or negative portion of the waveform which requires correction.
OBJECTS AND SUMMARY OF THE INVENTION
An object of the present invention is to provide an improved cathode ray tube scanning system. Another object of the invention is to enhance the top-bottom pincushion correction of a cathode ray tube scanning system. Still another object of the invention is to provide improved apparatus for unbalancing the amount of top-bottom pincushion correction in a cathode ray tube scanning system. A further object of the invention is to provide circuitry for controlling the unbalance of a top-bottom pincushion control circuit.
provide improved apparatus for unbalancing the amount of top-bottom pincushion correction in a cathode ray tube scanning system. A further object of the invention is to provide circuitry for controlling the unbalance of a top-bottom pincushion control circuit.
These and other advantages and capabilities are achieved in one aspect of the invention by a top-bottom pincushion correction circuit having a saturable reactor with a control winding coupled to a source of deflection current at a horizontal scan frequency and an output winding coupled to a source of deflection current at a vertical scan frequency and a means coupled to the output winding for unbalancing the waveform applied thereto from the source of deflection current at a vertical scan frequency.
BRIEF DESCRIPTION OF THE DRAWINGS
The sole FIGURE is a block and schematic diagram of a television receiver utilizing a preferred form of asymmetric top-bottom pincushion correction circuitry.
PREFERRED EMBODIMENT OF THE INVENTION
For a better understanding of the present invention, together with other and further objects, advantages and capabilities thereof, reference is made to the following disclosure and appended claims in conjunction with the accompanying drawing.
r understanding of the present invention, together with other and further objects, advantages and capabilities thereof, reference is made to the following disclosure and appended claims in conjunction with the accompanying drawing.
Referring to the drawing, a color television receiver includes an antenna 3 for intercepting and applying transmitted color television signals to a signal receiver 5. The signal receiver 5 includes the usual radio frequency (RF), intermediate frequency (IF), and video amplifier and detector stages to provide a composite color video signal.
The composite color video signal from the signal receiver 5 is applied to a video amplifier stage 7. The video amplifier stage 7 provides an output signal which is applied to a chrominance signal channel 9 wherefrom are derived signals representative of color information in the transmitted signal. These color information signals from the chrominance signal channel 9 are applied to a color cathode ray tube 11 to effect the desired display of color information.
Another output from the video amplifier stage 7 is applied to a luminance signal channel 13 wherein signals representative of image information are derived and applied to the color cathode ray tube 11. Still another output from the video amplifier stage 7 is applied to a sync pulse separator stage 15 wherein sync pulse signals at the vertical scan rate are separated from the video signal and applied to a vertical drive circuit 17. Also, sync pulse signals at the horizontal scan rate are separated from the video signal and applied to a horizontal drive circuit 19.
The horizontal drive circuit 19 is coupled to a horizontal output circuit 21 which includes a transistor 23 having an emitter connected to circuit ground and a collector coupled by a winding 25 of a horizontal flyback transformer 27 to a potential source B+. A parallel connected capacitor 29 and damper diode 31 couple the collector of the transistor 23 to circuit ground while a series connected "S" curve correction capacitor 33 and a horizontal deflection yoke winding 35 shunt the parallel connected capacitor 29 and damper diode 31. The horizontal deflection yoke winding 35 is a part of a deflection yoke 37 associated with the cathode ray tube 11 as indicated by the arrows labeled "H".
A winding 39 on the horizontal flyback transformer 27 has one end grounded and the opposite end coupled to a pair of series connected control windings 41 and 43 disposed on an outer pair of leg members of a saturable reactor 45. The saturable reactor 45 is of the well-known "E" type construction and the control windings 41 and 43 are connected in a magnetically opposing manner to circuit ground.
An output from the vertical drive circuit 17 is AC coupled by a capacitor 47 to a vertical deflection yoke winding 49 which is a part of the deflection yoke 37 as indicated by the arrows labeled "V". The vertical deflection yoke winding 49 is coupled to an output winding 51 affixed to the center leg member of the saturable reactor 45. The output winding 51 is shunted by a capacitor 53 to provide a resonant circuit and an adjustable resistor 55 shunts the output winding 51 and capacitor 55 to provide for varying the Q of the resonant circuit.
Also, a series connected alterable impedance, depicted as an adjustable resistor, 57 and a unidirectional conduction device, illustrated as a diode 59, are shunted across the parallel connected output winding 51, capacitor 53, and alterable impedance 57. This series connected adjustable resistor 57 and diode 59 serve to effect unbalance of the waveform applied thereto whereby asymmetric top-bottom pincushion correction is effected without undesired alteration of the crossover point of the waveform.
As to operation, the winding 39 coupled to the flyback transformer 27 provides horizontal flyback pulse signals 61 which are applied to the series connected control windings 41 and 43 affixed to the saturable reactor 45. Since the control windings 41 and 43 are oppositely poled, they tend to drive horizontal flux through the center leg of the saturable reactor 45 in opposite directions. Thus, equal flux contributions from the control windings 41 and 43 cause cancellation of horizontal frequency flux variations whereupon no energy is transferred into the center leg whereon the output winding 51 is disposed. However, a difference in flux contribution by the control windings 41 and 43 produces horizontal frequency variations to the output winding 51.
he series connected control windings 41 and 43 affixed to the saturable reactor 45. Since the control windings 41 and 43 are oppositely poled, they tend to drive horizontal flux through the center leg of the saturable reactor 45 in opposite directions. Thus, equal flux contributions from the control windings 41 and 43 cause cancellation of horizontal frequency flux variations whereupon no energy is transferred into the center leg whereon the output winding 51 is disposed. However, a difference in flux contribution by the control windings 41 and 43 produces horizontal frequency variations to the output winding 51.
As to dynamic control of the relative horizontal flux contributions, the vertical drive circuit 17 provides a vertical scanning current, waveform 63, having a crossover point 65 with a ramp-like portion 67 of one polarity and a ramp-like portion 69 of the opposite polarity. During a first portion of vertical scanning, the vertical scanning current, portion 67, induces a flux into the center leg of the saturable reactor 45 which opposes the flux linkages of the center leg to one outside leg and adds to the flux linkages of the center leg to the other outside leg. The opposite flux conditions exist when the second portion, portion 69, of the vertical scanning current is applied to the winding 51. Thus, a maximum amplitude of horizontal frequency signals is transferred to the output winding 51 when the vertical scanning current is maximum and a polarity crossover occurs intermediate the maximum horizontal signal amplitude transfer.
Additionally, an unbalance of the vertical scanning current, waveform 63, modulated by the horizontal frequency variations is obtainable by adding the series connected adjustable resistor 57 and diode 59. In accordance with the connections of the diode 59, the diode 59 is reverse biased and does not affect the resultant pincushion correction waveform when the correction waveform is of one polarity. However, when the polarity of the correction waveform reverses, the diode 59 conducts which causes the adjustable resistor 57 to load down the circuit and reduce the magnitude of the pincushion correction waveform.
of the correction waveform reverses, the diode 59 conducts which causes the adjustable resistor 57 to load down the circuit and reduce the magnitude of the pincushion correction waveform.
Obviously, reversing the connections of the diode 59 will result in a reversal of the unbalance of the resultant pincushion correction waveform. The magnitude of the unbalance or correction is selectively chosen by altering the adjustable resistor 57. Moreover, it can readily be seen that the unbalance circuitry has no effect upon the crossover point 65 since loading of the circuitry is dependent upon current flow through the series connected resistor 57 and diode 59 whereas current flow is not present or at a minimum at the crossover point.
Thus, there has been provided a unique asymmetric top-bottom pincushion control circuit. The circuit is inexpensive of components and construction while enhancing the capabilities of a cathode ray tube scanning system. Also, the circuit provides a technique to effect unbalance of the top-bottom pincushion correction signals without undesired alterations in the crossover point of the correction signals. Moreover, the circuit provides apparatus for easily controlling the degree of unbalance desired.
While there has been shown and described what is at present considered the preferred embodiment of the invention, it will be obvious to those skilled in the art that various changes and modifications may be made therein without departing from the invention as defined by the appended claims.
Circuit Description:
The display chip chosen for this post is the AY-5-8320. This provides a four digit clock display with decimal point and a channel number display from 1-16. Both displays appear on a background rectangle for easy viewing. The time and channel displays can be enabled independently. To the display chip we must add a digital clock. This is again an l.s.i. MOS chip, the G.I. AY-5-1203A. Like most digital clocks it uses the 50Hz mains as a clock input, with digital counters to produce the time display output. Pin connections for the two l.s.i. chips, and a typical TV display, are shown on Fig. 1.
The circuit diagram of the digital clock and the character generator is shown on Fig. 2: ICI is the 1203 digital clock chip and IC2 the display chip. The digital clock produces a four -digit output. To transmit this in binary form would require sixteen lines. The clock chip economises on pin connections by sending each digit (four binary bits) in turn. This is called multiplexing. These four binary bits are available at pins 16 to 19 of the 1203. To identify the digits as they are sent, the 1203 provides four multiplex slot signals MX1-4 which appear at pins 3-6. When MX1 is at a
binary 1 the minutes units binary bits are on pins 16 to 19, when MX2 is at a 1 the minutes tens binary bits are present and so on. A strobe output is provided at pin 20. This occurs in the centre of each multiplex slot, and is used by the display chip to gate the data from the clock. The display chip thus obtains and stores all four digits of the time display. The multiplexing frequency is determined by a capacitor (C2) from pin 23 to the positive supply. It is nominally set to 50kHz, although this is not critical. The AY5-8320 display chip IC2 requires (in addition to the time data) line and field sync pulses to position the display, and a 1.1MHz oscillator input. The 1.1MHz oscillator has to be inhibited by the line sync pulse and synchronised on each TV line to prevent ragged edges appearing on the characters. The oscillator consists of the quad CMOS nand IC3, with the frequency of oscillation determined by R3, RV1, C1.
The sync pulses are produced by the sync extraction circuit shown in Fig. 3 (to be described later).
These pulses may be positive -going or negative -going depending on the TV set being used. The circuit requires positive -going line sync pulses at pins 8 and 9 of IC3, and negative -going field sync pulses at pin 7 of IC2. The inverters (IC4 a -d) and the wire links allow the correct polarity signal to be chosen. There is little data available as to what actually goes on inside the 8320 display chip, although it is probably along the lines of the score display article in the September 1975 Practical Wireless . The necessary delays will be generated by digital counters from the 1.1MHz clock. The display chip IC2 produces two outputs, a time output on pin 3 and a background output on pin 2. These are at a binary 1 in the asserted state. These outputs are buffered by IC5 and inverters IC4 e and f to produce the following signals for the video switching: (a) Gate Video. This is at a binary 1 when the normal TV picture is present on its own and at a 0 when the background and time display are added. (b) Gate Time. This is the video output for the time/channel digits and is at a 1 in the asserted state. (c) Background a (IC5 pin 11). This is the background output, inhibited during the time display. It's at a 1 during the background but at a 0 during the time/channel display. (d) Background b (IC4 pin 6). This is a 1 for the entire background and time display. Depending on the colours required for the number and background, the "gate hue" and "gate background" outputs can be taken from background a or b by selecting the corresponding wire links. The time display is produced by taking pin 22 of IC2 to a binary 1. Capacitor C5 keeps the display on for about six seconds after the 1 input is removed. Pin 22 can be triggered by a momentary contact on a push-button or, ultimate luxury, from an ultrasonic remote transmitter.
The time is set by connections A and B. Taking A to a 1 advances the minutes display at two per second; taking B to a 1 similarly advances the hours. The 50Hz clock arrives via C3 and is clipped and buffered by R7, R8, D2, D3. The clock chip IC1 produces at pin 7 a 50kHz burst for 0.5 seconds every second. This is smoothed by R4, D I, C4 and presented to the colon input (pin 20) on the display chip to give a flashing colon display. Some people find flashing colons annoying: if R4, D 1 and C4 are omitted and R6 is inserted the colon becomes steady. The colon output from the clock also drives Tr4 to give a front panel LED display. The colon stops flashing after a power failure, and starts again when either of the set time buttons is pressed. The front panel LED thus indicates that the clock is healthy. The channel data is presented in binary form at terminals W, X, Y, Z, W being the least significant bit. The display is offset by one bit, i.e. 0000 gives 1, 0100 gives 5 and so on. The channel display is enabled by taking terminal V to a binary 1.
Interfacing with the Television Receiver:
Fig. 3 shows the sync extraction circuits and a general purpose video mixing circuit. Before describing these it's probably best to outline the basic requirements of the television interface. The display system needs field and line sync signals from the television receiver. It's highly unlikely that these would be available at the correct levels, and depending on the set and the take off point chosen they can be of either polarity. If oscillograms are shown in the service manual, suitable signals should be easily found - in most if not all television sets. They will probably be found in either the sync separator, the flyback blanking circuits or around the scan output stages. If oscillograms are not available it will be necessary to do a bit of detective work around likely points in the circuit. It's preferable to use scan flyback pulses because of their amplitude and the low source impedance (this avoids loading the sync circuits).
The sync extraction circuits shown in Fig. 3 will accept either positive- or negative -going signals. For negative - going inputs, Trl and Tr2 are forward biased by R14/R18: with positive -going inputs R13/R17 are used instead. The input resistors R12 and R16 form a potential divider with the selected resistor, and the transistors are turned on for positive inputs or off for negative inputs. The wire links shown in Fig. 2 allow the correct polarity signals to be chosen for the display circuit. The values for R12-14 and R16-18 depend on the amplitude of the incoming waveforms. Transistors Tr 1/Tr2 need about 0.1mA base current, so the values will be of the order of 100kS2. This should not load the TV circuit to which it's connected. With some waveforms which are close to or cross OV, capacitors C6 and C7 can be replaced with wire links. If C6 and C7 are used they should be of suitable voltage rating for the circuit to which they are connected. The connection to the video stages presents many options. The majority of colour TV sets today are cathode driven with RGB signals. The description of techniques for interfacing the time display with the set's video circuitry will be mainly directed at cathode drive therefore.
A, typical simple RGB output stage is shown in Fig. 4. The RGB signal from the demodulator i.c. is fed first to a preamplifier or buffer (generally a one transistor stage) then to the high -voltage transistor which drives the appropriate c.r.t. cathode.
A "brute force and ignorance" method of inserting the time and background display is to parallel three high - voltage transistors Tr 1 etc. with the RGB outputs along the lines shown in Fig. 5. The signals driving these could be
picked up from the "gate time", "gate background a and b" outputs (Fig. 2). The trimpots RV1 etc. set the current through the output transistors and hence the cathode potentials when the logic signals are at a binary 1. By selection of the right logic signals and suitable settings of the trimpots almost any colour combination for the time and its background could be chosen.
To prevent the display appearing superimposed on the video from unused cathodes, it will again be necessary to resort to brute force. Transistors Tr2 etc. pull down the bases of the buffer preamplifier transistor, turning the television RGB signals off. These transistors are driven from the "background b" signal which is present for the entire display on each line. A more subtle method is to use the 4016 CMOS analogue switch to intercept the video from the demodulator i.c. and substitute in its place the time display. The 4016 i.c. looks like a perfect switch in series with a 300E2 resistor. The switch is controlled by the logic gate input, the switch being closed for a binary 1 and open for a binary 0. The operating time is around 200nS, which is adequate for our application. Cathode drive RGB output stages fall into two categories: direct coupled from the demodulator to. the cathode with clamping earlier in the circuit, or a.c. coupled with clamping at the c.r.t. cathodes. Direct coupled amplifiers are the easiest ones to modify, so these will be dealt with first.
All that's usually required here is to insert the 4016 switch in the base circuit of the output transistor. Fig. 6 shows a suitably modified red drive circuit. Switch SW1 controls the video and SW2 the voltage set by RV1. Switch SW1 is closed by the "gate video" signal from Fig. 2, and SW2 from the selected logic output (gate time, background or hue). The other two amplifiers are dealt with in a similar manner. One small modification is required to the output from the demodulator i.c. This doesn't like having no load, tending to wander off and do its own thing when the video switches are open. To prevent this, a 10k52 resistor should be added from pins 1, 2 and 4 to OV as shown. Next we must deal with a.c. coupled circuits.
A typical example is the tv chassis here described.
The RGB output circuit (red one) used in this chassis is shown in Fig. 7. The simplest way to deal with this is to insert the 4016 switch at the point shown. Because the video is unclamped at this point, the time display levels will vary according to the picture content. For the best results it's necessary to clamp the video before substituting the time display. This is done by the transistor clamp shown in Fig. 7. The video is a.c. coupled and clamped by Tr 1. The clamp voltage of 4.7V is chosen to bias the 4016 switches in the centre of their range. The clamped video is then switched, along with the d.c. levels from the trimpot RV I, to insert the time display. The modified video is then a.c. coupled back to 3RV8 on the TV chassis. The 30052 resistance of the 4016 is effectively connected in series with 3RV8 etc. These may require slight adjustment therefore. Alternatively the dearer 4066 chip may be used. This is identical to the 4016, but has a resistance of 6052. With the general description over we can turn to the circuit in Fig. 3. IC6 and IC7 are two quad CMOS switches. IC6 gates the video from the three demodulator outputs. IC7 gates the levels on RV2 RV4 to give the three outputs on pins K, L, M. The fourth, Y, is used in older colour -difference sets and will be described later. The gating of the levels on RV2 - RV4 is done by the gate logic signals from Fig. 2. Also shown in Fig. 3 is the power supply. This is a fairly conventional i.c. regulator, made adjustable by the inclusion of Tr3 in the common return line. The operating voltage range for IC I is 12-18V, for IC2 it's 16-19V, and for the B picked up from the "gate time", "gate background a and b" outputs (Fig. 2). The trimpots RV1 etc. set the current through the output transistors and hence the cathode potentials when the logic signals are at a binary 1. By selection of the right logic signals and suitable settings of the trimpots almost any colour combination for the time series CMOS it's less than 18V. The supply chosen is 16- 17V therefore. A wire link is included so that the power supply can be adjusted before it's connected to the rest of the circuit.
DIGITAL CLOCK ON SCREEN DISPLAY MEYHOD:
The introduction of l.s.i. MOS integrated circuits has allowed semiconductor manufacturers to include many complex functions on one chip. General Instruments have produced several such chips for the TV industry, amongst the more interesting being the AY-5-8300 8320 series of channel and time display chips. These provide video outputs which superimpose a digital clock or the channel number on the television picture. It's interesting to see how fast semiconductor technology has advanced even in the 70's.
Circuit Description:
The display chip chosen for this post is the AY-5-8320. This provides a four digit clock display with decimal point and a channel number display from 1-16. Both displays appear on a background rectangle for easy viewing. The time and channel displays can be enabled independently. To the display chip we must add a digital clock. This is again an l.s.i. MOS chip, the G.I. AY-5-1203A. Like most digital clocks it uses the 50Hz mains as a clock input, with digital counters to produce the time display output. Pin connections for the two l.s.i. chips, and a typical TV display, are shown on Fig. 1.
binary 1 the minutes units binary bits are on pins 16 to 19, when MX2 is at a 1 the minutes tens binary bits are present and so on. A strobe output is provided at pin 20. This occurs in the centre of each multiplex slot, and is used by the display chip to gate the data from the clock. The display chip thus obtains and stores all four digits of the time display. The multiplexing frequency is determined by a capacitor (C2) from pin 23 to the positive supply. It is nominally set to 50kHz, although this is not critical. The AY5-8320 display chip IC2 requires (in addition to the time data) line and field sync pulses to position the display, and a 1.1MHz oscillator input. The 1.1MHz oscillator has to be inhibited by the line sync pulse and synchronised on each TV line to prevent ragged edges appearing on the characters. The oscillator consists of the quad CMOS nand IC3, with the frequency of oscillation determined by R3, RV1, C1.
The sync pulses are produced by the sync extraction circuit shown in Fig. 3 (to be described later).
These pulses may be positive -going or negative -going depending on the TV set being used. The circuit requires positive -going line sync pulses at pins 8 and 9 of IC3, and negative -going field sync pulses at pin 7 of IC2. The inverters (IC4 a -d) and the wire links allow the correct polarity signal to be chosen. There is little data available as to what actually goes on inside the 8320 display chip, although it is probably along the lines of the score display article in the September 1975 Practical Wireless . The necessary delays will be generated by digital counters from the 1.1MHz clock. The display chip IC2 produces two outputs, a time output on pin 3 and a background output on pin 2. These are at a binary 1 in the asserted state. These outputs are buffered by IC5 and inverters IC4 e and f to produce the following signals for the video switching: (a) Gate Video. This is at a binary 1 when the normal TV picture is present on its own and at a 0 when the background and time display are added. (b) Gate Time. This is the video output for the time/channel digits and is at a 1 in the asserted state. (c) Background a (IC5 pin 11). This is the background output, inhibited during the time display. It's at a 1 during the background but at a 0 during the time/channel display. (d) Background b (IC4 pin 6). This is a 1 for the entire background and time display. Depending on the colours required for the number and background, the "gate hue" and "gate background" outputs can be taken from background a or b by selecting the corresponding wire links. The time display is produced by taking pin 22 of IC2 to a binary 1. Capacitor C5 keeps the display on for about six seconds after the 1 input is removed. Pin 22 can be triggered by a momentary contact on a push-button or, ultimate luxury, from an ultrasonic remote transmitter.
The time is set by connections A and B. Taking A to a 1 advances the minutes display at two per second; taking B to a 1 similarly advances the hours. The 50Hz clock arrives via C3 and is clipped and buffered by R7, R8, D2, D3. The clock chip IC1 produces at pin 7 a 50kHz burst for 0.5 seconds every second. This is smoothed by R4, D I, C4 and presented to the colon input (pin 20) on the display chip to give a flashing colon display. Some people find flashing colons annoying: if R4, D 1 and C4 are omitted and R6 is inserted the colon becomes steady. The colon output from the clock also drives Tr4 to give a front panel LED display. The colon stops flashing after a power failure, and starts again when either of the set time buttons is pressed. The front panel LED thus indicates that the clock is healthy. The channel data is presented in binary form at terminals W, X, Y, Z, W being the least significant bit. The display is offset by one bit, i.e. 0000 gives 1, 0100 gives 5 and so on. The channel display is enabled by taking terminal V to a binary 1.
Interfacing with the Television Receiver:
Fig. 3 shows the sync extraction circuits and a general purpose video mixing circuit. Before describing these it's probably best to outline the basic requirements of the television interface. The display system needs field and line sync signals from the television receiver. It's highly unlikely that these would be available at the correct levels, and depending on the set and the take off point chosen they can be of either polarity. If oscillograms are shown in the service manual, suitable signals should be easily found - in most if not all television sets. They will probably be found in either the sync separator, the flyback blanking circuits or around the scan output stages. If oscillograms are not available it will be necessary to do a bit of detective work around likely points in the circuit. It's preferable to use scan flyback pulses because of their amplitude and the low source impedance (this avoids loading the sync circuits).
The sync extraction circuits shown in Fig. 3 will accept either positive- or negative -going signals. For negative - going inputs, Trl and Tr2 are forward biased by R14/R18: with positive -going inputs R13/R17 are used instead. The input resistors R12 and R16 form a potential divider with the selected resistor, and the transistors are turned on for positive inputs or off for negative inputs. The wire links shown in Fig. 2 allow the correct polarity signals to be chosen for the display circuit. The values for R12-14 and R16-18 depend on the amplitude of the incoming waveforms. Transistors Tr 1/Tr2 need about 0.1mA base current, so the values will be of the order of 100kS2. This should not load the TV circuit to which it's connected. With some waveforms which are close to or cross OV, capacitors C6 and C7 can be replaced with wire links. If C6 and C7 are used they should be of suitable voltage rating for the circuit to which they are connected. The connection to the video stages presents many options. The majority of colour TV sets today are cathode driven with RGB signals. The description of techniques for interfacing the time display with the set's video circuitry will be mainly directed at cathode drive therefore.
A "brute force and ignorance" method of inserting the time and background display is to parallel three high - voltage transistors Tr 1 etc. with the RGB outputs along the lines shown in Fig. 5. The signals driving these could bepicked up from the "gate time", "gate background a and b" outputs (Fig. 2). The trimpots RV1 etc. set the current through the output transistors and hence the cathode potentials when the logic signals are at a binary 1. By selection of the right logic signals and suitable settings of the trimpots almost any colour combination for the time and its background could be chosen.
To prevent the display appearing superimposed on the video from unused cathodes, it will again be necessary to resort to brute force. Transistors Tr2 etc. pull down the bases of the buffer preamplifier transistor, turning the television RGB signals off. These transistors are driven from the "background b" signal which is present for the entire display on each line. A more subtle method is to use the 4016 CMOS analogue switch to intercept the video from the demodulator i.c. and substitute in its place the time display. The 4016 i.c. looks like a perfect switch in series with a 300E2 resistor. The switch is controlled by the logic gate input, the switch being closed for a binary 1 and open for a binary 0. The operating time is around 200nS, which is adequate for our application. Cathode drive RGB output stages fall into two categories: direct coupled from the demodulator to. the cathode with clamping earlier in the circuit, or a.c. coupled with clamping at the c.r.t. cathodes. Direct coupled amplifiers are the easiest ones to modify, so these will be dealt with first.
A typical example is the tv chassis here described.
The RGB output circuit (red one) used in this chassis is shown in Fig. 7. The simplest way to deal with this is to insert the 4016 switch at the point shown. Because the video is unclamped at this point, the time display levels will vary according to the picture content. For the best results it's necessary to clamp the video before substituting the time display. This is done by the transistor clamp shown in Fig. 7. The video is a.c. coupled and clamped by Tr 1. The clamp voltage of 4.7V is chosen to bias the 4016 switches in the centre of their range. The clamped video is then switched, along with the d.c. levels from the trimpot RV I, to insert the time display. The modified video is then a.c. coupled back to 3RV8 on the TV chassis. The 30052 resistance of the 4016 is effectively connected in series with 3RV8 etc. These may require slight adjustment therefore. Alternatively the dearer 4066 chip may be used. This is identical to the 4016, but has a resistance of 6052. With the general description over we can turn to the circuit in Fig. 3. IC6 and IC7 are two quad CMOS switches. IC6 gates the video from the three demodulator outputs. IC7 gates the levels on RV2 RV4 to give the three outputs on pins K, L, M. The fourth, Y, is used in older colour -difference sets and will be described later. The gating of the levels on RV2 - RV4 is done by the gate logic signals from Fig. 2. Also shown in Fig. 3 is the power supply. This is a fairly conventional i.c. regulator, made adjustable by the inclusion of Tr3 in the common return line. The operating voltage range for IC I is 12-18V, for IC2 it's 16-19V, and for the B picked up from the "gate time", "gate background a and b" outputs (Fig. 2). The trimpots RV1 etc. set the current through the output transistors and hence the cathode potentials when the logic signals are at a binary 1. By selection of the right logic signals and suitable settings of the trimpots almost any colour combination for the time series CMOS it's less than 18V. The supply chosen is 16- 17V therefore. A wire link is included so that the power supply can be adjusted before it's connected to the rest of the circuit.
A Cockcroft-Walton cascade circuit comprises an input voltage source and a pumping and storage circuit with a series array of capacitors with pumping and storage portions of the circuit being interconnected by silicon rectifiers, constructed and arranged so that at least the capacitor nearest the voltage source, and preferably one or more of the next adjacent capacitors in the series array, have lower tendency to internally discharge than the capacitors in the array more remote from the voltage source.
1. An improved voltage multiplying circuit comprising,
2. An improved voltage multiplying circuit in accordance with claim 1 wherein said first pumping capacitor is a self-healing impregnated capacitor which is impregnated with a high voltage impregnant.
3. An improved voltage multiplying circuit in accordance with claim 1 wherein said first pumping capacitor comprises a foil capacitor.
Description:
BACKGROUND OF THE INVENTION
The invention relates in general to Cockcroft-Walton cascade circuits for voltage multiplication and more particularly to such circuits with a pumping circuit and a storage circuit composed of capacitors connected in series, said pumping circuits and storage circuit being linked with one another by a rectifier circuit whose rectifiers are preferably silicon rectifiers, especially for a switching arrangement sensitive to internal discharges of capacitors, and more especially a switching arrangement containing transistors, and especially an image tube switching arrangement.
Voltage multiplication cascades composed of capacitors and rectifiers are used to produce high D.C. voltages from sinusoidal or pulsed alternating voltages. All known voltage multiplication cascades and voltage multipliers are designed to be capacitance-symmetrical, i.e., all capacitors used have the same capacitance. If U for example is the maximum value of an applied alternating voltage, the input capacitor connected directly to the alternating voltage source is charged to a D.C. voltage with a value U, while all other capacitors are charged to the value of 2U. Therefore, a total voltage can be obtained from the series-connected capacitors of a capacitor array.
In voltage multipliers, internal resistance is highly significant. In order to obtain high load currents on the D.C. side, the emphasis in the prior art has been on constructing voltage multipliers with internal resistances that are as low as possible.
Internal resistance of voltage multipliers can be reduced by increasing the capacitances of the individual capacitors by equal amounts. However, the critical significance of size of the assembly in the practical application of a voltage multiplier, limits the extent to which capacitance of the individual capacitors can be increased as a practical matter.
In television sets, especially color television sets, voltage multiplication cascades are required whose internal resistance is generally 400 to 500 kOhms. Thus far, it has been possible to achieve this low internal resistance with small dimensions only by using silicon diodes as rectifiers and metallized film capacitors as the capacitors.
When silicon rectifiers are used to achieve low internal resistance, their low forward resistance produces high peak currents and therefore leads to problems involving the pulse resistance of the capacitors. Metallized film capacitors are used because of space requirements, i.e., in order to ensure that the assembly will have the smallest possible dimensions, and also for cost reasons. These film capacitors have a self-healing effect, in which the damage caused to the capacitor by partial evaporation of the metal coating around the point of puncture (pinhole), which develops as a result of internal spark-overs, is cured again. This selfhealing effect is highly desirable as far as the capacitors themselves are concerned, but is not without its disadvantages as far as the other cirucit components are concerned, especially the silicon rectifiers, the image tubes, and the components which conduct the image tube voltage.
It is therefore an important object of the invention to improve voltage multiplication cascades of the type described above.
It is a further object of the invention to keep the size of the entire assembly small and the internal resistance low.
It is a further object of the invention to increase pulse resistance of the entire circuit.
It is a further object of the invention to avoid the above-described disadvantageous effects on adjacent elements.
It is a further object of the invention to achieve multiples of the foregoing objects and preferably all of them consistent with each other.
SUMMARY OF THE INVENTION
In accordance with the invention, the foregoing objects are met by making at least one of the capacitors in the pumping circuit, preferably including the one which is adjacent to the input voltage source, one which is less prone to internal discharges than any of the individual capacitors in the storage circuit.
The Cockcroft-Walton cascade circuit is not provided with identical capacitors. Instead, the individual capacitors are arranged according to their loads and designed in such a way that a higher pulse resistance is attained only in certain capacitors. It can be shown that the load produced by the voltage in all the capacitors in the multiplication circuit is approximately the same. But the pulse currents of the capacitors as well as their forward flow angles are different. In particular, the capacitors of the pumping circuit are subjected to very high loads in a pulsed mode. In the voltage multiplication cascade according to the invention, these capacitors are arranged so that they exhibit fewer internal discharges than the capacitors in the storage circuit.
The external dimensions of the entire assembly would be unacceptably large if one constructed the entire switching arrangement using such capacitors.
The voltage multiplication cascade according to the invention also makes it possible to construct a reliably operating
arrangement which has no tendency toward spark-overs, consistent with satisfactory internal resistance of the voltage multiplication cascade and small dimensions of the entire assembly. This avoids the above cited disadvantages with respect to the particularly sensitive components in the rest of the circuit and makes it possible to design voltage multiplication cascades with silicon rectifiers, which are characterized by long lifetimes. Hence, a voltage multiplication cascade has been developed particularly for image tube circuits in television sets, especially color television sets, and this cascade satisfies the highest requirements in addition to having an average lifetime which in every case is greater than that of the television set.
A further aspect of the invention is that at least one of the capacitors that are less prone to internal discharges is a capacitor which is impregnated with a high-voltage impregnating substance, especially a high-voltage oil such as polybutene or silicone oil, or mixtures thereof. In contrast to capacitors made of metallized film which have not been impregnated, this allows the discharge frequency due to internal discharges or spark-overs to be reduced by a factor of 10 to 100.
According to a further important aspect of the invention, at least one of the capacitors that are less prone to internal discharges is either a foil capacitor or a self-healing capacitor. In addition, the capacitor in the pumping circuit which is adjacent to the voltage source input can be a foil capacitor which has been impregnated in the manner described above, while the next capacitor in the pumping circuit is a self-healing capacitor impregnated in the same fashion.
Other objects, features and advantages of the invention will be apparent from the following detailed description of preferred embodiments, taken in connection with the accompanying drawing, the single FIGURE of which:
BRIEF DESCRIPTION OF THE DRAWING
is a schematic diagram of a circuit made according to a preferred embodiment of the invention.
DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS
The voltage multiplier comprises capacitors C1 to C5 and rectifiers D1 to D5 connected in a cascade. An alternating voltage source UE is connected to terminals 1 and 2, said voltage source supplying for example a pulsed alternating voltage. Capacitors C1 and C2 form the pumping circuit while capacitors C3, C4 and C5 form the storage circuit.
In the steady state, capacitor C1 is charged to the maximum value of the alternating voltage UE as are the other capacitors C2 to C5. The desired high D.C. voltage UA is picked off at terminals 3 and 4, said D.C. voltage being composed of the D.C. voltages from capacitors C3 to C5. Terminal 3 and terminal 2 are connected to one pole of the alternating voltage source UE feeding the circuit, which can be at ground potential. In the circuit described here, a D.C. voltage UA can be picked off whose voltage value is approximately 3 times the maximum value of the pulsed alternating voltage UE. By using more than five capacitors, a correspondingly higher D.C. voltage can be obtained.
The individual capacitors are discharged by disconnecting D.C. voltage UA. However, they are constantly being recharged by the electrical energy supplied by the alternating voltage source UE, so that the voltage multiplier can be continuously charged on the output side.
According to the invention, in this preferred embodiment, capacitor C1 and/or C2 in the pumping circuit are designed so that they have a lower tendency toward internal discharges than any of the individual capacitors C3, C4 and C5 in the storage circuit.
It is evident that those skilled in the art, once given the benefit of the foregoing disclosure, may now make numerous other uses and modifications of, and departures from the specific embodiments described herein without departing from the inventive concepts. Consequently, the invention is to be construed as embracing each and every novel feature and novel combination of features present in, or possessed by, the apparatus and techniques herein disclosed and limited solely by the scope and spirit of the appended claims.
Inventors:Petrick, Paul (Landshut, DT)
Schwedler, Hans-peter (Landshut, DT)
Holzer, Alfred (Schonbrunn, DT)
ERNST ROEDERSTEIN SPEZIALFABRIK
US Patent References:
3714528 ELECTRICAL CAPACITOR WITH FILM-PAPER DIELECTRIC 1973-01-30 Vail
3699410 SELF-HEALING ELECTRICAL CONDENSER 1972-10-17 Maylandt
3463992 ELECTRICAL CAPACITOR SYSTEMS HAVING LONG-TERM STORAGE CHARACTERISTICS 1969-08-26 Solberg
3457478 WOUND FILM CAPACITORS 1969-07-22 Lehrer
3363156 Capacitor with a polyolefin dielectric 1968-01-09 Cox
2213199 Voltage multiplier 1940-09-03 Bouwers et al.
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