PHILIPS 21GR2552/08B BRAQUE CHASSIS G90AE SVHS
Microcom - TMP47C434N-3555
Memory - X24C02P
SMPS - BUT11AF (PHILIPS SOPS)
TR Chopper - 3215.1
SAW - G1961
Video - TDA3561A
VIF - TDA8341
Vertical - BD939F *2
Synchro - TDA2579A
Sound - TDA8191
Tuner - UV615S
Band - LA7910
TV/AV - TDA5850
TELETEXT:SAA5243; M5165AL-12, MAB8461 W107
FBT - 37741 (HR7549)
HOT - BUT11AF
RGB Amp. - BF422
SERVICING DETAILS:
A. REGULATIONS
1. +95V supply voltage Connect a voltmeter (DC) between pin 5 of connector A5 and ground. Control with potentiometer 3635 the voltage down to +95V.
2. Horizontal sync Connect pins 5 and 9 of IC7470 together. Apply an antenna signal and tune the receiver. Adjust potentiometer 3457 until the image is straight. Remove the jumper.
3. Horizontal centering Is set with potentiometer 3461.
4. Image width Is set with potentiometer 3525.
5. Vertical centering Set with switch SK11.
6. Image height Is set with potentiometer 3510.
7. Focusing Adjusted with the focus potentiometer on the line transformer set
8. The chroma assist oscillator Enter a color bar pattern. Connect the pins 23 and 24 of IC7350 together. Bring one resistor of 470Q between pins 1 and 6 of IC7350. Adjust 2352 so that the color runs out the screen has almost stopped. Remove the resistor and the jumper.
9. The PAL delay line Apply a generator signal from a PM5515. Sets the generator in the "DEM" position. Set the contrast and the brightness to normal and the saturation control at 3/4 of its reach. Control potentiometer 3334 so that the "Venetian blinds" effect takes place in the 3rd bar disappears (see Fig. 9). Then line 5330 to the "Venetian blinds" effect in the 1st and 4th bar disappears. Readjust potentiometer 3334.
10. The image demodulator. Connect a signal generator (e.g. PM5326) as is
indicated in fig. 10 and set its frequency at 38.9MHz (PAL I: 39.5MHz). Modulate (AM) it signal with 1 kHz. Solder resistor 3001 to a side loose (supply voltage for the tuner). Connect an oscilloscope to pin 22 of IC7020 and adjust 5035 to a maximum (undistorted) signal. Make sure the demodulator is not overdriven. Solder resistor 3001 back on.
11.AFC Connect a signal generator (e.g. PM 5326) as shown indicated in fig. 10 and set its frequency at 38.9MHz (PAL I: 39.5MHz). Connect a voltmeter to pin 5 of IC7020 and adjust with 5034 the voltage to 6V (DC).
12. H.F.-A.V.R. If the picture is from a strong local channel distorted, potentiometer 3012 adjust until the image is undistorted.
13. The sound part Apply a generator signal, whose sound carrier (FM) is modulated with a frequency of 1 kHz. Set the generator to mono mode. Adjust with 5115 for maximum sound.
14. Setting on the teletext decoder. Connect pin 22 of IC7830 to ground. Close one frequency counter to pin 17 of IC7830 and adjust with 5803 the frequency decreases to 6.010 MHz ± 2.5 kHz. Remove the jumper.
B. DISPLAY PANEL SETTINGS
1. Picture tube pinch points Apply a blank grid signal. Connect pin 7 of IC7350 with ground. Adjust the brightness and contrast so that about potentiometer 3380 is the DC voltage OV. Control with potentiometers 3412, 3422 and 3432 black level on the collectors of the transistors 7406, 7416 and 7426 at 105V for 11" devices. For devices larger than 11" the black level serves to be adjusted to 130V. Now adjust the Vg2 potentiometer on the line transformer until the gun that gives the first light is correct is no longer visible. Arrange the other two guns with their associated controllers (3412, 3422 or 3432) until no light is visible again. Remove the jumper.
2. Grayscale setting Apply a test picture signal and set the device normal. Let the appliance heat up for approx. 10 minutes. Adjust 3380 and 3384 until the desired gray scale is obtained.
C. ADJUSTMENTS ON THE SECAM/PAL TRANSCODER IF PRESENT
1. "Circuit Cloche" Disconnect bridge wire 9302 on one side. Apply a signal from a signal generator capacitor 2316. Set the signal generator frequency to 4.286 MHz. Connect an oscilloscope to pin 3 of IC7310. Adjust 5316 to maximum amplitude. Close bridge wire 9302 again.
2. Auxiliary Carrier Wave Off Oscillator Apply a 75% SECAM color bar pattern Connect pin 6 of IC7310 using a resistance of 10 kΩ to ground. Connect a frequency counter with a high input impedance (via a probe C = s 2pF) on pin 26 of IC7350. Set the frequency to 8.867236 MHz with C2332. Remove the resistance.
3. SECAM demodulator Apply a SECAM black screen signal. Connect an oscilloscope to pin 14 of IC7310. Line 3347 and 5347 such that there are minimal modulation occurs.
4. The delay line a.Amplitude Apply a SECAM red grid signal. Connect an oscilloscope to pin 28 of IC7350. Line 3335 such that the amplitude of each line equal. b. Phase Set the brightness and contrast normally. Connect an oscilloscope to pin 16 of IC7350. Enter a 75% PAL color bar pattern. Adjust the saturation control so that the signal is as flat as possible. Then run a 75% SECAM color bars pattern please. Line 5337 such that the signal is almost again flat.
COMMENTS AND REMARKS:
1. The DC voltages and oscillograms serve to be measured relative to the nearest adjacent ground point on the printed circuit board.
2. The DC voltages should be under the following conditions to be measured: No antenna signal supply, minimum brightness, maximum saturation and contrast.
3. The oscillograms serve under the following conditions are measured: a. Use a color bar pattern as the input signal of pattern generator PM5515. b. Set the voltage of the saturation control to pin 6 of IC7350 to 3V DC. c. Connect an oscilloscope (mode: 1 V/cm-10Jsec/cm). on pin 16 of IC7350. Set the brightness control so that the level of the black bar in the video signal reaches 2.7V . Use the contrast control to adjust the amplitude of the video signal to 5 V.
4. The oscillograms and DC voltages are true there needed with (~ \~) and without antenna signal (^K^) measured. Tensions in the power supply are both for normal operation (®) and in standby (c!)) measured. These values are through the corresponding symbols are indicated.
5. The parts listed in the parts lists are completely interchangeable with the parts in each position the device, regardless of any type designations.
6. The picture tube print is provided with printed spark gaps. Every spark gap is switched between an electrode of the picture tube and the aqua day coat.
7. Connectors used for the modules (board to board) are of the gold-plated type and are only allowed through be replaced the same.
8. In the event of troubleshooting and/or repairs to the SECAM/PAL transcoder, the reachability of the circuit and parts are enlarged by using extension printing. The order numbers for these extension boards are: 4-fold 4822 395 30262 5 times 4822 395 30261
PHILIPS 21GR2552/08B BRAQUE CHASSIS G90AE SVHS PHILIPS TDA2579B Horizontal/vertical synchronization circuit
GENERAL DESCRIPTION
The TDA2579B generates and synchronizes horizontal and vertical signals. The device has a 3 level sandcastle output;
a transmitter identification signal and also 50/60 Hz identification.
Features
· Horizontal phase detector, (sync to oscillator), sync separator and noise inverter
· Triple current source in the phase detector with automatic selection
· Second phase detector for storage compensation of the horizontal output
· Stabilized direct starting of the horizontal oscillator and output stage from mains supply
· Horizontal output pulse with constant duty cycle value of 29 ms
· Internal vertical sync separator, and two integration selection times
· Divider system with three different reset enable windows
· Synchronization is set to 628 divider ratio when no vertical sync pulses and no video transmitter is identified
· Vertical comparator with a low DC feedback signal
· 50/60 Hz identification output combined with mute function
· Automatic amplitude adjustment for 50 and 60 Hz and blanking pulse duration
· Automatic adaption of the burst-key pulsewidth
FUNCTIONAL DESCRIPTION
Vertical part (pins 1,2,3,4)
The IC embodies a synchronized divider system for generating the vertical sawtooth at pin 3. The divider system has an
internal frequency doubling circuit, so the horizontal oscillator is working at its normal line frequency and one line period
equals 2 clock pulses. Due to the divider system no vertical frequency adjustment is needed. The divider has a
discriminator window for automatically switching over from the 60 Hz to 50 Hz system. The divider system operates with
3 different divider reset windows for maximum interference/disturbance protection.
The windows are activated via an up/down counter. The counter increases its counter value by 1 for each time the
separated vertical sync pulse is within the searched window. The count is decreased by 1 when the vertical sync pulse
is not present.
Large (search) window: divider ratio between 488 and 722
This mode is valid for the following conditions:
1. Divider is looking for a new transmitter.
2. Divider ratio found, not within the narrow window limits.
3. Up/down counter value of the divider system operating in the narrow window mode decreases below count 1.
4. Externally setting. This can be reached by loading pin 18 with a resistor of 220 kW to earth or connecting a 3.6 V
diode stabistor between pin 18 and ground.
Narrow window: divider ratio between 522-528 (60 Hz) or 622-628 (50 Hz).
The divider system switches over to this mode when the up/down counter has reached its maximum value of 12 approved
vertical sync pulses. When the divider operates in this mode and a vertical sync pulse is missing within the window the
divider is reset at the end of the window and the counter value is decreased by 1. At a counter value below count 1 the
divider system switches over to the large window mode.
Standard TV-norm
When the up/down counter has reached its maximum value of 12 in the narrow window mode, the information applied to
the up/down counter is changed such that the standard divider ratio value is tested. When the counter has reached a
value of 14 the divider system is changed over to the standard divider ratio mode. In this mode the divider is always reset
at the standard value even if the vertical sync pulse is missing. A missed vertical sync pulse decreases the counter value
by 1. When the counter reaches the value of 10 the divider system is switched over to the large window mode.
The standard TV-norm condition gives maximum protection for video recorders playing tapes with anti-copy guards.
No-TV-transmitter found: (pin 18 < 1.2 V)
In this condition, only noise is present, the divider is rest to count
628. In this way a stable picture display at normal height
is achieved.
It should be noted that some VTRs operating in the feature modes, such as picture search, generate such distorted
pictures that the no-TV-transmitter detection circuit can be activated as pin V18 drops below 1.2 V. This would imply a
rolling picture (see Phase detector, sub paragraph d). In general VTR-machines use a re-inserted vertical sync pulse in
the feature mode. Therefore the divider system has been made such that the automatic reset of the divider at count 628
when V18 is below 1.2 V is inhibited when a vertical sync pulse is detected.
The divider system also generates the anti-top-flutter pulse which inhibits the Phase 1 detector during the vertical sync.
pulse. The width of this pulse depends on the divider mode. For the divider mode a the start is generated at the reset of
the divider. In mode b and c the anti-top-flutter pulse starts at the beginning of the first equalizing pulse.
The anti-top-flutter pulse ends at count 8 for 50 Hz and count 10 for 60 Hz. The vertical blanking pulse is also generated
via the divider system. The start is at the reset of the divider while the pulse ends at count 34 (17 lines) for 60 Hz, and at
count 44 (22 lines) for 50 Hz systems. The vertical blanking pulse generated at the sandcastle output pin 17 is made by
adding the anti-top-flutter pulse and the blanking pulse. In this way the vertical blanking pulse starts at the beginning of
the first equalizing pulse when the divider operates in the b or c mode. For generating a vertical linear sawtooth voltage
a capacitor should be connected to pin 3. The recommended value is 150 nF to 330 nF (see Fig.1).
The capacitor is charged via an internal current source starting at the reset of the divider system. The voltage on the
capacitor is monitored by a comparator which is activated also at reset. When the capacitor has reached a voltage value
of 5.85 V for the 50 Hz system or 4.85 V for the 60 Hz system the voltage is kept constant until the charging period ends.
The charge period width is 26 clock pulses. At clock pulse 26 the comparator is switched off and the capacitor is
discharged by an npn transistor current source, the value of which can be set by an external resistor between pin 4 and
ground (pin 9). Pin 4 is connected to a pnp transistor current source which determines the current of the npn current
source at pin 3. The pnp current source on pin 4 is connected to an internal zener diode reference voltage which has a
typical voltage of » 7.5 volts. The recommended operating current range is 10 to 75 mA. The resistance at pin R4 should
be 100 to 770 kW. By using a double current mirror concept the vertical sawtooth pre-correction can be set on the desired
value by means of external components between pin 4 and pin 3, or by connecting the pin 4 resistor to the vertical current
measuring resistor of the vertical output stage. The vertical amplitude is set by the current of pin 4. The vertical feedback
voltage of the output stage has to be applied to pin 2. For the normal amplitude adjustment the values are DC = 1 V and
AC = 0.8 V. Due to the automatic system adaption both values are valid for 50 Hz and 60 Hz.
The low DC voltage value improves the picture bounce behaviour as less parabola compensation is necessary. Even a
fully DC coupled feedback circuit is possible.
Vertical guard
The IC also contains a vertical guard circuit. This circuit monitors the vertical feedback signal on pin 2. When the level
on pin 2 is below 0.35 V or higher than 1.85 V the guard circuit inserts a continuous level of 2.5 V in the sandcastle output
signal of pin 17. This results in the blanking of the picture displayed, thus preventing a burnt-in horizontal line. The guard
levels specified refer to the zener diode reference voltage source level.
Driver output
The driver output is at pin 1, it can deliver a drive current of 1.5 mA at 5 V output. The internal impedance is approximately
170 W. The output pin is also connected to an internal current source with a sink current of 0.25 mA.
Sync separator, phase detector and TV-station identification (pins 5,6,7,8 and 18)
The video input signal is connected to pin 5. The sync separator is designed such that the slicing level is independent of
the amplitude of the sync pulse. The black le
vel is measured and stored in the capacitor at pin 7. The slicing level valueis stored in the capacitor at pin 6.
Black level detector
A gating signal is used for the black level detector. This signal is composed of an internal horizontal reference pulse with
a duty factor of 50% and the flyback pulse at pin 12. In this way the TV-transmitter identification operates also for all DC
conditions at input pin 5 (no video modulation, plain carrier only).
During the frame interval the slicing level detector is inhibited by a signal which starts with the anti-top flutter pulse and
ends with the reset vertical divider circuit. In this way shift of the slicing level due to the vertical sync signal is reduced
and separation of the vertical sync pulse is improved.
Noise level detector
An internal noise inverter is activated when the video level at pin 5 decreases below 0.7 V. The IC also embodies a
built-in sync pulse noise level detection circuit. This circuit is directly connected to pin 5 and measures the noise level at
the middle of the horizontal sync pulse. When a signal-to-noise level of 19 dB is detected a counter circuit is activated.
A video input signal is processed as “acceptable noise free” when 12 out of 15 sync pulses have a noise level below
19 dB for two successive frame periods. The sync pulses are processed during a 15 line width gating period generated
by the divider system. The measuring circuit has a built-in noise level hysteresis of approximately 3 dB. When the
“acceptable noise free” condition is found the phase detector of pin 8 is switched to not gated and normal time constant.
When a higher sync pulse noise level is found the phase detector is switched over to slow time constant and gated sync
pulse phase detection. At the same time the integration time of the vertical sync pulse separator is adapted.
Phase detector
The phase detector circuit is connected to pin 8. This circuit consists of 3 separate phase detectors which are activated
depending on the voltage of pin 18 and the state of the sync pulse noise detection circuit. For normal and fast time
constants all three phase detectors are activated during the vertical blanking period, this with the exception of the
anti-top-flutter pulse period, and the separated vertical sync-pulse time. As a result, phase jumps in the video signal
related to the video head, take over of video recorders are quickly restored within the vertical blanking period. At the end
of the blanking period the phase director time constant is increased by 1.5 times. In this way there is no requirement for
external VTR time constant switching, and so all station numbers are suitable for signals from VTR, video games or home
computers.
For quick locking of a new TV station starting from a noise only signal condition (normal time constant) a special circuit
is incorporated. A new TV station which is not locked to the horizontal oscillator will result in a voltage decrease below
0.1 V at pin 18. This will activate a frame period counter which switches the phase detector to fast for 3 frame periods
during the vertical scan period.
The horizontal oscillator will now lock to the new TV-station and as a result, the voltage on pin 18 will increase to
approximately 6.5 V. When pin 18 reaches a level of 1.8 V the mute output transistor of pin 13 is switched OFF and the
divider is set to the large window. In general the mute signal is switched OFF within 5 ms (pin C18 = 47 nF) after reception
of a new TV-signal. When the voltage on pin 18 reaches a level of 5 V, usually within 15 ms, the frame counter is switched
OFF and the time constant is switched from fast to normal during the vertical scan period.
If the new TV station is weak, the sync-noise detector is activated. This will result in a change over of pin 18 voltage from
6.5 V to »10 V. When pin 18 exceeds the level of 7.8 V the phase detector is switched to slow time constant and gated
sync pulse condition. The current is also reduced during the vertical blanking period by 1 mA. When desired, most
conditions of the phase detector can also be set by external means in the following way:
a. Fast time constant TV transmitter identification circuit not active, connect pin 18 to earth (pin 9).
b. Fast time constant TV transmitter identification circuit active, connect a resistor of 220 kW between pin 18 and ground.
This condition can also be set by using a 3.6 V stabistor diode instead of a resistor.
c. Slow time constant, (with exception of frame blanking period), connect pin 18 via a resistor of 10 kW to + 12 V, pin 10.
In this condition the transmitter identification circuit is not active.
d. No switching to slow time constant desired (transmitter identification circuit active), connect a 6.8 V zener diode
between pin 18 and ground.
Supply (pins 9, 10 and 16)
The IC has been designed such that the horizontal oscillator and output stage can start operating by application of a very
low supply current into pin 16.
The horizontal oscillator starts at a supply current of approximately 4 mA. The horizontal output stage is forced into the
non-conducting stage until the supply current has a typical value of 5 mA. The circuit has been designed so that after
starting the horizontal output function a current drop of » 1 mA is allowed. The starting circuit has the ability to derive the
main supply (pin 10) from the horizontal output stage. The horizontal output signal can also be used as the oscillator
signal for synchronized switched mode power supplies. The maximum allowed starting current is 9.7 mA (Tamb = 25 °C).
The main supply should be connected to pin 10, and pin 9 should be used as ground. When the voltage on pin 10
increases from zero to its final value (typically 12 V) a part of the
supply current of the starting circuit is taken from pin 10
via internal diodes, and the voltage on pin 16 will stabilize to a typical value of 9.4 V.
In a stabilized condition (pin V10 > 10 V) the minimum required
supply current to pin 16 is » 2.5 mA. All other IC functions
are switched on via the main supply voltage on pin 10. When the voltage on pin 10 reaches a value of » 7 V the horizontal
phase detector circuit is activated and the vertical ramp on pin 3 is started. The second phase detector circuit and burst
pulse circuit are started when the voltage on pin 10 reaches the stabilized voltage value of pin 16 which is typically 9.4 V.
To close the second phase detector loop, a flyback pulse must be applied to pin 12. When no flyback pulse is detected
the duty factor of the horizontal output stage is 50%.
For remote switch-off pin 16 can be connected to ground (via a npn transistor with a series resistor of » 500 W) which
switches off the horizontal output.
Horizontal oscillator, horizontal output transistor, and second phase detector (pins 11, 12, 14 and 15)
The horizontal oscillator is connected to pin 15. The frequency is set by an external RC combination between pin 15 and
ground, pin 9. The open collector horizontal output stage is connected to pin 11. An internal zener diode configuration
limits the open voltage of pin 11 to » 14.5 V.
The horizontal output transistor at pin 11 is blocked until the current into pin 16 reaches a value of » 5 mA.
A higher current results in a horizontal output signal at pin 11, which starts with a duty factor of » 40% HIGH.
The duty factor is set by an internal current-source-loaded npn emitter follower stage connected to pin 14 during starting.
When pin 16 changes over to voltage stabilization the npn emitter follower and current source load at pin 14 are switched
OFF and the second phase detector circuit is activated, provided a horizontal flyback pulse is present at pin 12.
When no flyback pulse is detected at pin 12 the duty factor of the horizontal output stage is set to 50%.
The phase detector circuit at pin 14 compensates for storage time in the horizontal deflection output stage. The horizontal
output pulse duration is 29 ms HIGH for storage times between 1 ms and 17 ms (flyback pulse of 12 ms). A higher storage
time increases the HIGH time. Horizontal picture shift is possible by forcing an external charge or discharge current into
the capacitor at pin 14.
Mute output and 50/60 Hz identification (pin 13)
The collector of an npn transistor is connected to pin 13. When the voltage on pin 18 drops below 1.2 V
(no TV-transmitter) the npn transistor is switched ON.
When the voltage on pin 18 increases to a level of » 1.8 V (new TV-transmitter found) the npn transistor is switched OFF.
Pin 13 has also the possibility for 50/60 Hz identification. This function is available when pin 13 is connected to pin 10
(+ 12 V) via an external pull-up resistor of 10 to 20 kW. When no TV-transmitter is identified the voltage on pin 13 will be
LOW (< 0.5 V). When a TV-transmitter with a divider ratio >
576 (50 Hz) is detected the output voltage of pin 13 is HIGH
(+ 12 V).
When a TV-transmitter with a divider ratio < 576 (60 Hz) is found
an internal pnp transistor with its emitter connected to
pin 13 will force this pin output voltage down to » 7.6 V.
Sandcastle output (pin 17)
The sandcastle output pulse generated at pin 17, has three different voltage levels. The highest level, (10.4 V), can be
used for burst gating and black level clamping. The second level (4.5 V) is obtained from the horizontal flyback pulse at
pin 12, and is used for horizontal blanking. The third level (2.5 V) is used for vertical blanking and is derived via the
vertical divider system. For 50 Hz the blanking pulse duration is 44 clock pulses and for 60 Hz it is 34 clock pulses started
from the vertical divider reset. For TV-signals which have a divider ratio between 622 and 628 or between 522 and 528
the pulse is started at the first equalizing pulse. With the 50/60 Hz information the burst-key pulse width is switched to
improve the behaviour in multi-norm concepts.
GENERAL BASIC TRANSISTOR LINE OUTPUT STAGE OPERATION:
The
basic essentials of a transistor line output stage are shown in Fig.
1(a). They comprise: a line output transformer which provides the d.c.
feed to the line output transistor and serves mainly to generate the
high -voltage pulse from which the e.h.t. is derived, and also in
practice other supplies for various sections of the receiver; the line
output transistor and its parallel efficiency diode which form a
bidirectional switch; a tuning capacitor which resonates with the line
output transformer primary winding and the scan coils to determine the
flyback time; and the scan coils, with a series capacitor which provides
a d.c. block and also serves to provide slight integration of the
deflection current to compensate for the scan distortion that would
otherwise be present due to the use of flat screen, wide deflection
angle c.r.t.s. This basic circuit is widely used in small -screen
portable receivers with little elaboration - some use a pnp output
transistor however, with its collector connected to chassis.
Circuit Variations:
Variations
to the basic circuit commonly found include: transposition of the scan
coils and the correction capacitor; connection of the line output
transformer primary winding and its e.h.t. overwinding
in series; connection of the deflection components to a tap on the
transformer to obtain correct matching of the components and conditions
in the stage; use of a boost diode which operates in identical manner to
the arrangement used in valve line output stages, thereby increasing
the effective supply to the stage; omission of the efficiency diode
where the stage is operated from an h.t. line, the collector -base
junction of the line output transistor then providing the efficiency
diode action without, in doing so, producing scan distortion; addition
of inductors to provide linearity and width adjustment; use of a pair of
series -connected line output transistors in some large -screen colour
chassis; and in colour sets the addition of line convergence circuitry
which is normally connected in series between the line scan coils and
chassis. These variations on the basic circuit do not alter the basic
mode of operation however.
Resonance
The most important fact to appreciate about the circuit is that when the transistor and diode are cut off during the flyback period - when the beam is being rapidly returned from the right-hand side of the screen to the left-hand side the tuning capacitor together with the scan coils and the primary winding of the line output transformer form a parallel resonant circuit: the equivalent circuit is shown in Fig. 1(b). The line output transformer primary winding and the tuning capacitor as drawn in Fig. 1(a) may look like a series tuned circuit, but from the signal point of view the end of the transformer primary winding connected to the power supply is earthy, giving the equivalent arrangement shown in Fig. 1(b).
The Flyback Period:
Since the operation of the circuit depends mainly upon what happens during the line flyback period, the simplest point at which to break into the scanning cycle is at the end of the forward scan, i.e. with the
beam deflected to the right-hand side of the screen, see Fig. 2. At
this point the line output transistor is suddenly switched off by the
squarewave drive applied to its base. Prior to this action a linearly
increasing current has been flowing in the line output transformer
primary winding and the scan coils, and as a result magnetic fields have
been built up around these components. When the transistor is switched
off these fields collapse, maintaining a flow of current which rapidly
decays to zero and returns the beam to the centre of the screen. This
flow of current charges the tuning capacitor, and the voltage at A rises
to a high positive value - of the order of 1- 2k V in large -screen
sets, 200V in the case of mains/battery portable sets. The e
nergy
in the circuit is now stored in the tuning capacitor which next
discharges, reversing the flow of current in the circuit with the result
that the beam is rapidly deflected to the left-hand side of the screen -
see Fig. 3. When the tuning capacitor has discharged, the voltage at A
has fallen to zero and the circuit energy is once more stored in the
form of magnetic fields around the inductive components. One half -cycle
of oscillation has occurred, and the flyback is complete.Energy Recovery:
First Part of Forward Scan The circuit then tries to continue the cycle of oscillation, i.e. the magnetic fields again collapse, maintaining a current flow which this time would charge the tuning capacitor negatively (upper plate). When the voltage at A reaches about -0.6V however the efficiency diode becomes forward biased and switches on. This damps the circuit, preventing further oscillation, but the magnetic fields continue to collapse and in doing so produce a linearly decaying current flow which provides the first part of the forward s
can,
the beam returning towards the centre of the screen - see Fig. 4. The
diode shorts out the tuning capacitor but the scan correction capacitor
charges during this period, its right-hand plate becoming positive with
respect to its left-hand plate, i.e. point A. Completion of Forward Scan
When the current falls to zero, the diode will switch off. Shortly
before this state of affairs is reached however the transistor is
switched on. In practice this is usually about a third of the way
through the scan. The squarewave applied to its base drives it rapidly
to saturation, clamping the vol
tage
at point A at a small positive value - the collector emitter saturation
voltage of the transistor. Current now flows via the transistor and the
primary winding of the line output transformer, the scan correction
capacitor discharges, and the resultant flow of current in the line scan
coils drives the beam to the right-hand side of the screen see Fig. 5.Efficiency:
The transistor is then cut off again, to give the flyback, and the cycle of events recurs. The efficiency of the circuit is high since there is negligible resistance present. Energy is fed into the circuit in the form of the magnetic fields that build up when the output transistor is switched on. This action connects the line output transformer primary winding across the supply, and as a result a linearly increasing current flows through it. Since the width is
dependent on the supply voltage, this must be stabilised.
Harmonic Tuning:
There is another oscillatory action in the circuit during the flyback period. The considerable leakage inductance between the primary and the e.h.t. windings of the line output transformer, and the appreciable self -capacitance present, form a tuned circuit which is shocked into oscillation by the flyback pulse. Unless this oscillation is controlled, it will continue into and modulate the scan. The technique used to overcome this effect is to tune the leakage inductance and the associated capacitance to an odd harmonic of the line flyback oscillation frequency. By doing this the oscillatory actions present at the beginning of the scan cancel. Either third or fifth harmonic tuning is used. Third harmonic tuning also has the effect of increasing the amplitude of the e.h.t. pulse, and is generally used where a half -wave e.h.t. rectifier is employed. Fifth harmonic tuning results in a flat-topped e.h.t. pulse, giving improved e.h.t. regulation, and is generally used where an e.h.t. tripler is employed to produce the e.h.t. The tuning is mainly built into the line output transformer, though an external variable inductance is commonly found in colour chassis so that the tuning can be adjusted. With a following post I will go into the subject of modern TV line timebases in greater detail with other models and technology shown here at Obsolete Technology Tellye !
PHILIPS 21GR2552/08B BRAQUE CHASSIS G90AE SVHS Switched-mode
self oscillating supply voltage circuit:PHILIPS POWER SUPPLY (SOPS -
Self Oscillating Power Supply)
1.
A switched-mode self-oscillating supply voltage circuit for
converting an input voltage into an output d.c. voltage which is
substantially independent of variations of the input voltage and/or of
a load connected to the terminals of the output voltage, comprising a
transformer having a primary and a feedback winding, a first
controllable switch connected in series with the primary winding, the
series arrangement thus formed being coupled between terminals for the
input voltage, a second controllable switch coupled via a turn-off
capacitor to the control electrode of the first switch to turn it off,
means coupling the feedback winding to said control electrode, a
transformer winding being coupled via a rectifier to an output
capacitor having terminals which supply the output voltage, an output
voltage-dependent control voltage being present on a control electrode
of the second switch for controlling the conduction period of the
first switch, the circuit being switchable between an operating state
and a stand-by state in which relative to the operating state the
supply energy supplied to the load is considerably reduced, a starting
network connected to a terminal for the input voltage, means for
adjusting the control voltage in the stand-by state to a value at which
the first controllable switch is cut-off, a connection which carries
current during the conduction period for the second controllable
switch being provided between the starting network and said second
switch, and means providing a connection between the starting network
and the control electrode of the first switch, which connection does
not carry current in the stand-by state.2. A supply voltage circuit as claimed in claim 1, further comprising a resistor included between the connection of the starting network to the second switch and a turn-off capacitor present in the connection to the control electrode of the first switch.
3. A supply voltage circuit as claimed in claim 2, characterized in that the second controllable switch comprises a thyristor having a main current path included in the control electrode connection of the first controllable switch, said thyristor having a first control gate electrode for adjusting the turn-off instant of the first switch and a second control electrode to which the starting network and the resistor are connected.
4. A supply voltage circuit as claimed in claim 1, characterized in that a resistor is included in the connection to the control electrode of the second controllable switch so that a current flows through said resistor in the stand-by state of a value sufficient to cut-off the first controllable switch.
Such a supply voltage circuit is disclosed in German Patent Application No. 2,651,196. With this prior art circuit supply energy can be applied in the operating state to the different portions of a television receiver. In the stand-by state the majority of the output voltages of the circuit are so low that the receiver is substantially in the switched-off condition. In the prior art circuit the starting network is formed by a resistor connected to the unstabilized input voltage and through which on turn-on of the circuit a current flows via the feedback winding to the control electrode of the first controllable switch, which is a switching transistor, and brings it to and maintains it in the conductive state, as a result of which the circuit can start.
The invention has for its object to provide an improved circuit of the same type in which in the stand-by state the supply energy applied to the load is reduced to zero. The prior art circuit cannot be improved in this respect without the use of mechanical switches, for example relays. According to the invention, the switched-mode self-oscillating supply voltage circuit does not comprise such relays and is characterized in that it further comprises means for adjusting the control voltage in the stand-by state to a value at which the first controllable switch is cut-off. A connection which carries current during the conduction period of the second controllable switch is provided between the starting network and said second switch while a connection present between the starting network and the control electrode of the first switch does not carry current in the stand-by state.
The invention is based on the recognition that the prior art supply voltage circuit cannot oscillate, so that the energy supplied by it is zero, if the control voltage obtains a value as referred to, while the starting network is connected in such a manner that in the stand-by state no current can flow through it to the control electrode of the first controllable switch.
It should be noted that in the said German Patent Application the starting network is in the form of a resistor which is connected to an unstabilized input d.c. voltage. It is, however, known, for example, from German Patent Specification No. 2,417,628 to employ for this purpose a rectifier network connected to an a.c. voltage from which the said input d.c. voltage is derived by rectification.
The invention will now be further described by way of example with reference to the accompanying drawing, which shows a basic circuit diagram of a switched-mode self-oscillating supply voltage circuit.
The self-oscillating supply circuit shown in the FIGURE comprises a npn-switching transistor Tr1 having its collector connected to the primary winding L1 of a transformer T, while the emitter is connected to ground via a small resistor R1, for example 1.5 Ohm. Resistor R1 is decoupled for the high frequencies by means of a 150 nF capacitor C1. One end of winding L1 is connected to a conductor which carries an unstabilized input d.c. voltage V B of, for example, 300 V. Voltage V B has a negative rail connected to ground and is derived from the electric power supply by rectification. One end of a feedback winding L2 is connected to the base of transistor Tr1 via the parallel arrangement of a small inductance L3 and a damping resistor R2. A terminal of a 47 μF capacitor C2 is connected to the junction of the elements L2, L3 and R2.
The junction of capacitor C2 and resistor R3 is connected to a 100 Ohm resistor R5 and to the emitter of a pnp-transistor Tr2. The base of transistor Tr2 is connected to the other terminal of resistor R5 and to the collector of an npn-transistor Tr3, whose emitter is connected to ground. The base of Tr3 is connected to the collector of transistor Tr2. Transistors Tr2 and Tr3 form an artificial thyristor, i.e. a controllable diode whose anode is the emitter of transistor Tr2 while the cathode is the emitter of transistor Tr3. The base of transistor Tr2 is the anode gate and the base of transistor Tr3 is the cathode gate of the thyristor formed. Between the last-mentioned base and the emitter of transistor Tr1 there is arranged the series network of a 2.2 kOhm resistor R6 with the parallel arrangement of a 2.2 kOhm resistor R7 and a 100 μF capacitor C4. The series arrangement of a diode D11 and a 220 Ohm limiting resistor R19 is arranged between the junction of components R6, R7 and C4 and the junction of components C2, L2, R2 and L3. The cathode of diode D11 is connected to capacitor C2.
Because
of the feedback the described circuit oscillates independently as
soon as the steady state is achieved. It will be described hereinafter
how this state is obtained. During the time transistor Tr1 conducts
the current flowing through the resistor R1 increases linearly. The
resistor R4 then partly determines the base current of transistor Tr1.
Capacitor C4 and resistor R7 form a voltage source the voltage of
which is subtracted from the voltage drop across resistor R1. As soon
as the voltage on the base of transistor Tr3 is equal to approximately
0.7 V this transistor becomes conductive, as a result of which the
thyristor formed by transistors Tr2 and Tr3 becomes rapidly conductive
and remains so. Across capacitor C2 there is a negative voltage by
means of which transistor Tr1 is turned off. The inverse base current
thereof flows through thyristor Tr2, Tr3. This causes charge to be
withdrawn from capacitor C2, while the charge carriers stored in
transistor Tr1 are removed with the aid of inductance L3. As soon as
the collector current of transistor Tr1 has been turned off, the
voltage across winding L2 reverses its polarity, which current
recharges the capacitor. Now the voltage at the junction of components
C2, R3 and R5 is negative, causing thyristor Tr2, Tr3 to extinguish.In parallel with winding L1 there is the series network of a 2.2 nF tuning capacitor C8 and a 100 Ohm limiting resistor R8. The anode of a diode D6 is connected to the junction of components R8 and C8, while the cathode is connected to the other terminal of resistor R8. Winding L1 and capacitor C8 form a resonant circuit across which an oscillation is produced after windings L4, L5 and L6 have become currentless. At a later instant the current through circuit L1, C8 reverses its direction. As a result thereof a current is generated in winding L2 which flows via diode D2 and resistor R4 to the base of transistor Tr1 and makes this transistor conductive and maintains it in this state. The dissipation in resistor R8 is reduced by means of diode D6. A clamping network formed by the parallel arrangement of a 22 kOhm resistor R9 and a 120 nF capacitor C9 is arranged in series with a diode D7. This whole assembly is in parallel with winding L1 and cuts-off parasitic oscillations which would be produced during the period of time in which transistor Tr1 is non-conductive. The output voltages of the supply circuit are kept substantially constant in spite of variations of voltage V B and/or the loads, thanks to a control of the turning-on instant of thyrisistor Tr2, Tr3. For this purpose the emitter of a light-sensitive transistor Tr4 is connected to the base of transistor
Tr3. The collector of transistor Tr4 is connected via a resistor R10 to the conductor which carries the voltage V B
and to a Zener diode Z1 which has a positive voltage of approximately
7.5 V, while the base is unconnected. The other end of diode Z1 is
connected to ground. A light-emitting diode D8, whose cathode is
connected to the collector of an npn-transistor Tr5, is optically
coupled to transistor Tr4. By means of a potentiometer R11 the base of
transistor Tr5 can be adjusted to a d.c. voltage which is derived from
the voltage V 0 of approximately 130 V across capacitor C6. The anode of diode D8 is connected to a d.c. voltage V 1 of approximately 13 V. A resistor R12 is also connected to voltage V 1 ,
the other end of the resistor being connected to the emitter of
transistor Tr5, to the cathode of a Zener diode Z2 which has a voltage
of approximately 7.5 V and to a smoothing capacitor C10. The other ends
of diode Z2 and capacitor C10 are connected to ground. Voltage V1 can
be generated by means of a transformer connected to the electric AC
supply and a rectifier, which are not shown for the sake of simplicity,
more specifically for a remote control to which constantly supply
energy is always applied, even when the majority of the components of
the receiver in what is referred to as the stand-by state are not
supplied with supply energy.The circuit is protected from overvoltage. This is ensured by a thyristor which is formed by a pnp-transistor Tr6 and an npn-transistor Tr7. The anode of a diode D9 is connected to the junction of components R3 and C2 and the cathode to the base of transistor Tr6 and to the collector of transistor Tr7. The base of transistor Tr7, which base is connected to the collector of transistor Tr6, is connected via a zener diode Z3 to a voltage which, by means of a potentiometer R13 is adjusted to a value derived from the voltage across capacitor C7. The emitter of transistor Tr6 also is connected to the voltage of capacitor C7, more specifically via a resistor R14 and a diode D10. If this voltage increases to above a predetermined value then thyristor Tr6, Tr7 becomes conductive. Since the emitter of transistor Tr7 is connected to ground, the voltage at its collector becomes very low, as a result of which diode D9 becomes conductive, which keeps transistor Tr1 in the non-conducting state. This situation is maintained as long as thyristor Tr6, Tr7 continues to conduct. This conduction time is predominantly determined by the values of capacitor C7, resistor R14 and a resistor R15 connected between the base and the emitter of transistor Tr6. A thyristor is advantageously used here to render it possible to switch off a large current even with a low level signal and to obtain the required hysteresis.
arting resistor R16, one end of which is connected to the base of transistor Tr2 and the other end to the conductor which carries the voltage V B . Upon turn-on of the circuit current flows through resistors R16 and R5 and through capacitor C2, which has as yet no charge, to the base of transistor Tr1. The voltage drop thus produced across resistor R5 keeps transistor Tr2, and consequently also transistor Tr3, in the non-conductive state, while transistor Tr1 is made conductive and is maintained so by this current. Current also flows through winding L2. In this manner the circuit can start as energy is built up in transformer T.
The supply circuit can be brought into the stand-by state by making an npn-transistor Tr8, which is non-conductive in the operating state, conductive. The emitter of transistor Tr8 is connected to ground while the collector is connected to the collector of transistor Tr5 via a 1.8 kOhm resistor R17. A resistor R18 has one end connected to the base of transistor Tr8 and the other end, either in the operating state to ground, or in the stand-by state to a positive voltage of, for example, 5 V. Transistor Tr8 conducts in response to this voltage. An additional, large current flows through diode D8 and consequently also through transistor Tr4, resulting in thyristor Tr2, Tr3 being made conductive and transistor Tr1 being made non-conductive and maintained so. So to all appearances a large control current is obtained causing the duty cycle to be reduced to zero. A condition for a correct operation is that the emitter current of transistor Tr4 be sufficiently large in all circumstances, which implies that the voltage drop produced across resistor R6 by this current is always higher than the sum of the voltage across voltage source R7, C4, of the base-emitter threshold voltage of transistor Tr3 in the conductive state thereof, and of the voltage at the emitter of transistor Tr1. So the said voltage drop must be higher than the sum of the first two voltages, which corresponds to the worst dimensioning case in which the stand-by state is initiated while transistor Tr1 is in the non-conductive state.
If thyristor Tr2, Tr3 conducts, either in the operating state or in the stand-by state, current flows through resistor R16 via the collector emitter path of transistor Tr3 to ground. This current is too small to have any appreciable influence on the behaviour of the circuit. When thyristor Tr2, Tr3 does not conduct, the voltage on the left hand terminal of capacitor C2 is equal to approximately 1 V, while the voltage across the capacitor is approximately -4 V. So transistor Tr1 remains in the non-conductive state and a premature turn-on thereof cannot occur.
If in the operating state transistor Tr1 conducts while thyristor Tr2,
Tr3 is cut-off, then the current flows through resistor R16 in the
same manner as it flows during the start to the base of transistor
Tr1, but has relatively little influence as the base current caused by
the energy stored in winding L2 is many times larger. If both
transistor Tr1 and thyristor Tr2, Tr3 are non-conductive, then the
current through resistor R16 flows through components R5, C2, L2, R4,
C3 and R1. In this stand-by state capacitor C2 has indeed
substantially no negative charge any longer but, in spite thereof,
transistor Tr1 cannot become conductive
since no current flows to its base. It will furthermore be noted that
the circuit is protected in the event that thyristor Tr2, Tr3 has an
interruption. Namely, in such a case the circuit cannot start.
In the foregoing a circuit is described which may be considered to be a
switched-mode supply voltage circuit of the parallel ("flyback")
type. It will be obvious that the invention may alternatively be used
in supply voltage circuits of a different type, for example converters
of the type commonly referred to as up-converters. It will also be
obvious that transistor Tr1 may be replaced by an equivalent switch,
for example a gate-turn-off switch.
PHILIPS PAL decoder TDA3561A
TDA3561A (PHILIPS) Luminance+Chrominance+RGB MATRIX
PAL decoder TDA3561A
GENERAL DESCRIPTION
The
PHILIPS TDA3561A is a decoder for the PAL colour television standard.
It combines all functions required for the identification
and demodulation of PAL signals.
Furthermore it contains a luminance amplifier, an RGB-matrix and amplifier. These
amplifiers supply output signals up to 5 V peak-to-peak (picture information) enabling direct drive of the discrete output
stages.
The
circuit also contains separate inputs for data insertion, analogue as
well as digital, which can be used for text display systems (e.g.
(Teletext/broadcast antiope), channel number display, etc. Additional to
the TDA3560, the
circuit includes the following features:
· The peak white limiter is only active during the time that the 9,3 V level at the output is exceeded.
The start of the
limiting
function is delayed by one line period. This avoids peak white limiting
by test patterns which have abrupt transitions from colour to white
signals.
· The brightness
control is obtained by inserting a variable pulse in the luminance
channel. Therefore the ratio of brightness variation and signal
amplitude at the three outputs will be identical and independent of the
difference in gain of the three channels. Thus discolouring due to
adjustment of contrast and brightness is avoided.
· Improved suppression of the internal RGB signals when the device is switched to external signals, and vice versa.
· Non-synchronized external RGB signals do not disturb the black level of the internal signals.
· Improved suppression of the residual 4,4 MHz signal in the RGB output stages.
· Cascoded stages in the demodulators and burst phase detector minimize the radiation of the colour demodulator
inputs.
· High current capability of the RGB outputs and the chrominance output.
APPLICATION INFORMATION
The function is described against the corresponding pin
number.
1. + 12 V power supply
The circuit gives good operation in a supply voltage range
between 8 and 13,2 V provided that the supply voltage for
the controls is equal to the supply voltage for the
TDA3561A. All signal and control levels have a linear
dependency on the supply voltage. The current taken by
the device at 12 V is typically 85 mA. It is linearly
dependent on the supply voltage.
2. Control voltage for identification
This pin requires a detection capacitor of about 330 nF for
correct operation. The voltages available under various
signal conditions are given in the specification.
3. Chrominance input
The chroma signal must be a.c.-coupled to the input.
Its amplitude must be between 55 mV and 1100 mV
peak-to-peak (25 mV to 500 mV peak-to-peak burst
signal). All figures for the chroma signals are based on a
colour bar signal with 75% saturation, that is the
burst-to-chroma ratio of the input signal is 1 : 2,25.
4. Reference voltage A.C.C. detector
This pin must be decoupled by a capacitor of about 330
nF. The voltage at this pin is 4,9 V.
5. Control voltage A.C.C.
The A.C.C. is obtained by synchronous detection of the
burst signal followed by a peak detector. A good noise
immunity is obtained in this way and an increase of the
colour for weak input signals is prevented. The
recommended capacitor value at this pin is 2,2 µF.
6. Saturation control
The saturation control range is in excess of 50 dB.
The control voltage range is 2 to 4 V. Saturation control is
a linear function of the control voltage.
When the colour killer is active, the saturation control
voltage is reduced to a low level if the resistance of the
external saturation control network is sufficiently high.
Then the chroma amplifier supplies no signal to the
demodulator. Colour switch-on can be delayed by proper
choice of the time constant for the saturation control
setting circuit.
When the saturation control pin is connected to the power
supply the colour killer circuit is overruled so that the colour
signal is visible on the screen. In this way it is possible to
adjust the oscillator frequency without using a frequency
counter (see also pins 25 and 26).
7. Contrast control
The contrast control range is 20 dB for a control voltage
change from + 2 to + 4 V. Contrast control is a linear
function of the control voltage. The output signal is
suppressed when the control voltage is 1 V or less. If one
or more output signals surpasses the level of 9 V the peak
white limiter circuit becomes active and reduces the output
signals via the contrast control by discharging C2 via an
internal current sink.
8. Sandcastle and field blanking input
The output signals are blanked if the amplitude of the input
pulse is between 2 and 6,5 V. The burst gate and clamping
circuits are activated if the input pulse exceeds a level of
7,5 V.
The higher part of the sandcastle pulse should start just
after the sync pulse to prevent clamping of video signal on
the sync pulse. The width should be about 4 µs for proper
A.C.C. operation.
9. Video-data switching
The insertion circuit is activated by means of this input by
an input pulse between 1 V and 2 V. In that condition, the
internal RGB signals are switched off and the inserted
signals are supplied to the output amplifiers. If only normal
operation is wanted this pin should be connected to the
negative supply. The switching times are very short
(< 20 ns) to avoid coloured edges of the inserted signals
on the screen.
10. Luminance signal input
The input signal should have a peak-to-peak amplitude of
0,45 V (peak white to sync) to obtain a black-white output
signal to 5 V at nominal contrast. It must be a.c.-coupled to
the input by a capacitor of about 22 nF. The signal is
clamped at the input to an internal reference voltage.
A 1 kΩ luminance delay line can be applied because the
luminance input impedance is made very high.
Consequently the charging and discharging currents of the
coupling capacitor are very small and do not influence the
signal level at the input noticeably. Additionally the
coupling capacitor value may be small.
11. Brightness control
The black level of the RGB outputs can be set by the
voltage on this pin (see Fig.5). The black level can be set
higher than 4 V however the available output signal
amplitude is reduced (see pin 7). Brightness control also
operates on the black level of the inserted signals.
12, 14, 16. RGB outputs
The output circuits for red, green and blue are identical.
Output signals are 5,25 V (R, G and B) at nominal input
signals and control settings. The black levels of the three
outputs have the same value. The blanking level at the
outputs is 2,1 V. The peak white level is limited to 9,3 V.
When this level exceeded the output signal amplitude is
reduced via the contrast control (see pin 7).
13, 15, 17. Inputs for external RGB signals
The external signals must be a.c.-coupled to the inputs via
a coupling capacitor of about 100 nF. Source impedance
should not exceed 150 Ω. The input signal required for
a 5 V peak-to-peak output signal is 1 V peak-to-peak.
At the RGB outputs the black level of the inserted signal is
identical to that of normal RGB signals. When these inputs
are not used the coupling capacitors have to be connected
to the negative supply.
18, 19, 20. Black level clamp capacitors
The black level clamp capacitors for the three channels are
connected to these pins. The value of each capacitor
should be about 100 nF.
21, 22. Inputs (B-Y) and (R-Y) demodulators
The input signal is automatically fixed to the required level
by means of the burst phase detector and A.C.C.
generator which are connected to pin 21 and pin 22. As the
burst (applied differentially to those pins) is kept constant
by the A.C.C., the colour difference signals automatically
have the correct value.
23, 24. Burst phase detector outputs
At these pins the output of the burst phase detector is
filtered and controls the reference oscillator. An adequate
catching range is obtained with the time constants given in
the application circuit (see Fig.6).
25, 26. Reference oscillator
The frequency of the oscillator is adjusted by the variable
capacitor C1. For frequency adjustment interconnect pin
21 and pin 22. The frequency can be measured by
connecting a suitable frequency counter to pin 25.
28. Output of the chroma amplifier
Both burst and chroma signals are available at the output.
The burst-to-chroma ratio at the output is identical to that
at the input for nominal control settings. The burst signal is
not affected by the controls. The amplitude of the input
signal to the demodulator is kept constant by the A.C.C.
Therefore the output signal at pin 28 will depend on the
signal loss in the delay line.
- IF DEM + AMPL with TDA3541
DESCRIPTION
The TDA3541;Q are integrated IF
amplifier and demodulator circuits for colour or black/white
television receivers, the TDA8340;Q is for application with
n-p-n tuners and the TDA8341;Q for p-n-p tuners.
The TDA8340;Q and TDA8341;Q are pin-compatible
successors with improved performance to types
TDA2540/2541;Q and TDA3540/3541;Q.
Features
· Full range gain-controlled wide-band IF amplifier
· Linear synchronous demodulator with excellent
intermodulation performance
· White spot inverter
· Wide-band video amplifier with noise protection
· AFC circuit with AFC on/off switching and
sample-and-hold function
· Low impedance AFC output
· AGC circuit with noise gating
· Tuner AGC output for n-p-n tuners (TDA8340) or p-n-p
tuners (TDA8341)
· External video switch for switching-off the video output
· Reduced sensitivity for high sound carriers
· Integrated filter to limit second harmonic IF signals
· Wide supply voltage range
· Requires few external components.
PHILIPS 21GR2552/08B BRAQUE CHASSIS G90AE SVHS Rapid access teletext - Videotextx decoder arrangement:A teletext decoder includes a background or buffer memory operating as a first-in, first-out (FIFO)
memory. The buffer memory is used for storing a large number of
teletext pages. A given video line that contains teletext information
is identified as such by the detection of part of a clock run-in
sequence followed by the framing code. The video line is then stored in
the background memory. After a user page request occurs, the
background memory is read-out by a data processor operating in a full
channel mode of operation for obtaining the information of the
requested page. As long as the read-out operation has not been
terminated, incoming teletext data is stored in the background memory.
This enables teletext data received prior to termination of the read-out
operation to be read out and processed by the data processor.
1.
A television apparatus responsive to an incoming television signal
containing video lines that carry text data, defining corresponding
data lines, for generating an output signal that is capable of
providing picture information to a display device, comprising:
means
for generating a first control signal in order to select one of said
data lines to be used in conjunction with the generation of said output
signal;
a source of said television signal;
a first-in, first-out background memory having a data input that is coupled to an output of said source;
first
control means coupled to said background memory for controlling
storage therein of corresponding data lines of said television signal,
wherein prior to the time said first control signal is generated, said
background memory already contains a substantial number of stored data
lines of said television signal;
second control means responsive
to said first control signal and coupled to said background memory for
controlling during a given interval that follows the generation of
said first control signal, read-out from said background memory of a
plurality of data lines of said television signal that have been stored
before the end of said given interval, said given interval having a
duration that is substantially shorter than that of a corresponding
interval between the occurrence of an initial data line of said
plurality of data lines and the occurrence of a final data line thereof
so as to reduce access time to said plurality of data lines, said
second control means controlling read-out of said plurality of data
lines in a first-in, first-out manner for generating during said given
interval a data signal that contains the data of said plurality of data
lines including data lines that have been stored in said background
memory during said given interval; and
a data processor
responsive to said data signal for selecting said one data line to
generate in accordance therewith said output signal.
2. An
apparatus according to claim 1 wherein said data lines occur in said
television signal only during, corresponding vertical blanking
intervals, wherein, during said given interval, said data processor
operates in a full channel mode of operation, and wherein, prior to the
time when said first control signal is generated, said data processor
operates in a field flyback mode of operation.
3. An apparatus according to claim 1 further comprising,
means for coupling said data signal and said television signal to said
data processor such that prior to the time said first control signal is
generated said television signal is coupled to said data processor in a
manner that bypasses said background memory.
4. An apparatus according to claim 3 wherein, throughout
said given interval, said coupling means decouples said signal that
bypasses said background memory from said data processor.
5. An apparatus according to claim 1 further
comprising, a switch having a first input that is coupled between said
output of said source of said television signal and said data input of
said background memory, a second input that is coupled to a data output
of said background memory and a switch output that is coupled to an
input of said data processor. 6.
An apparatus according to claim 5 further comprising, means for
generating a second control signal that is coupled to a control input
of said switch, said second control signal having a first state for
enabling said switch to couple the signal that is developed at said
second input of said switch to said data processor following the time
when said first control signal is generated and having a second state,
for enabling said switch to couple the signal that is developed at said
first input thereof to said data processor following the occurrence of
the earlier of (a) a time when all the data stored in said background
memory has been read out, and (b) a time when a first time-out interval
has elapsed from a time when said data processor selects the data of a
Page Header data line. 7. An
apparatus according to claim 5 further comprising, means coupled to
said background memory, for generating, in accordance with the data of
said plurality of data lines, a serial bit data signal that contains
corresponding data lines that are read out of said background memory in
a first-in, first-out manner, said serial bit data signal being
coupled to said second input of said switch, said switch coupling said
serial bit data signal to said input of said data processor, during
said given interval, and coupling the signal that is developed at said
first input of said switch to said input of said data processor, outside
said given interval. 8. An
apparatus according to claim 1 wherein, as a result of reading out t
he
data of said plurality of data lines in the first-in, first-out manner,
memory addresses, where said plurality of data lines are stored in
said background memory are transparent to the operation of said data
processor. 9. An apparatus
according to claim 1 wherein said data processor is included in an
integrated circuit of the same type used in a conventional teletext
decoder such that said background memory provides an add-on feature.
10. An apparatus according to claim 1
wherein said television signal comprises a teletext signal and wherein
said television apparatus comprises a teletext decoder.
11. An apparatus according to claim 10 wherein
said data lines of said television signal define corresponding pages of
teletext data, wherein said background memory is capable of containing
at a given time the data of a substantial number of said pages and
wherein, during said given interval, said data processor selects from
the data that is read out of said background memory the data of a first
page, in accordance with said one of said data lines that is a
Page-Header data line, to generate from the data of said first page
said output signal. 12. An
apparatus according to claim 1 further comprising, a page memory
wherein said output signal is stored in said page memory during said
given interval. 13. An apparatus
according to claim 1 further comprising, a switch for coupling one of
said data signal that is generated at an output of said background
memory and a second data signal, that bypasses said background memory,
to an input of said data processor when a second control signal that is
developed at a control input of said switch is at first state and for
coupling the other one of said to said input of said data processor
when said second control signal is at a second state.
14. An apparatus according to claim 13 further
comprising, means for generating, during said given interval, a first
time-out signal after an interval having a predetermined duration has
elapsed from a time when the data of said one of said data line that is
a Page Header data line has been identified in said data signal and
means responsive to said first time-out signal for generating said
second control signal in accordance with said first time-out signal .
15. An apparatus according to
claim 13 further comprising, means for generating a signal that is
indicative
of when the data of all the da&a lines that are stored in said
background memory have been read out and that is coupled to said
control input of said switch to control the state of said second
control signal. 16. A television
apparatus according to claim 1 wherein said data processor is
responsive, outside said given interval, to data lines of said
television signal that are coupled to said data processor in a manner
that bypasses said background memory.
17. An apparatus according to claim 1 further comprising, a
parallel-to-serial converter that is coupled between an output of said
background memory and an input of said data processor.
18. A television apparatus according to claim 1
wherein said background memory comprises a random access memory,
wherein said first control means comprises first sequencing means that
is coupled to an address input of said random access memory for
generating a write-in address word and wherein said second control
means comprises second sequencing means for generating a read-out
address word that is coupled to said address input.
19. An apparatus according to claim 18 wherein at
least one of said first and second sequencing means comprises a linear
feedback shift register counter.
20. An apparatus according to claim 18 wherein each of said data lines
includes a corresponding plurality of data line portions that are
stored in corresponding locations in said background memory having
corresponding addresses, wherein said first sequencing means changes
states in a cyclical manner each time a given one of said portions of
each data line is stored such that the number of states in each cycle is
equal to an integer multiple of the total number of data lines that
can be stored in said background memory in each cycle.
21. An apparatus according to claim 20 wherein
the number of memory addresses that are required for storing a given
data line is equal to 86. 22. An
apparatus according to claim 20 wherein the number of said states in
each cycle is equal to. 23. A
television apparatus according to claim 1 further comprising, a page
memory responsive to said output signal for storing said output signal
therein. 24. An apparatus
according to claim 1 wherein said data processor operates in a full
channel mode of operation throughout said given interval and wherein
said television signal contains said data lines only during
corresponding vertical blanking intervals thereof.
25. An apparatus according to claim 1 wherein said
first control means identifies, in a given video line signal, data of a
clock run-in portion of said video line signal and stores in said
background memory text data of such video line signal provided that
said data of said clock run-in portion is identified.
26. An apparatus according to claim 25 wherein said
said first control means identifies said given data line also in
accordance with data of a framing code.
27. An apparatus according to claim 1 wherein said first control
signal is indicative of when a user initiated page request has occurred
and causes said data processor to operate in a full channel mode of
operation during said given interval.
28. An apparatus according to claim 27 further comprising, means
for generating a second control signal that is indicative when a
predetermined time-out interval has elapsed from the time said first
control signal is generated, said second control signal being coupled to
said data processor for causing said data processor to start operating
in a field flyback mode of operation following said time-out interval
irrespective of whether said one of said data lines that is a Page
Header of the page requested has been selected.
29. An apparatus according to claim 28 wherein said
second control signal is generated in a microprocessor such that said
time out interval is determined by a program thereof.
30. A television apparatus responsive to an
incoming television signal containing video line signals that carry
text data, defining corresponding data lines, for generating an output
signal that is capable of providing picture information to a display
device, comprising: means for generating a first control signal in order to select one of said data lines to be used in conjunction with the generation of said output signal;
a source of said television signal;
a first-in, first-out background memory having a data input that is coupled to said source;
first control means coupled to said background memory for controlling storage therein of corresponding data lines of said television signal, wherein prior to the time said first control signal is generated, said background memory already contains a substantial number of stored data lines of said television signal;
second control means responsive to said first control signal and coupled to said background memory for controlling during a given interval that follows the generation of said first control signal, read-out from said background memory of a plurality of stored data lines of said television signal, such that the duration of said given interval is substantially shorter than that of a corresponding interval between the occurrence of an initial data line of said plurality of data lines and the occurrence of a final data line thereof, so as to reduce access time to said plurality of data lines, said second control means controlling read-out of said plurality of data lines in a first-in, first-out manner for generating during said given interval a data signal that contains the data of said plurality of data lines;
a switch having a first input that is coupled to said source of said television signal, having a second input that is coupled to a data output of said background memory and having an output for generating a second data signal;
a data processor responsive to said second data signal for selecting said one data line to generate in accordance therewith said output signal; and
means for generating a second control signal that is coupled to a control input of said switch, said second control signal having a first state for enabling said switch to couple to said data processor after said first control signal is generated the signal that is developed at said switch second input, and having a second state for enabling said switch to couple to said data processor the signal that is developed at said first switch input following the occurrence of the earlier of (a) a time when all the data stored in said background memory has been read out, and (b) a time when a time-out interval has elapsed from a time when said data processor selects said one data line that is a Page Header.
31. A television apparatus responsive to an incoming television signal containing video lines that carry text data, defining corresponding data lines, for generating an output signal that is capable of providing picture information to a display device, comprising:
first means for generating a first control signal in order to select one of said data lines to be used in conjunction with the generation of said output signal;
second means responsive to said television signal for generating a clock signal that is indicative of timings of individual bits of a data sequence of a clock run-in portion of a data line;
a source of said television signal;
a first-in, first-out background memory having a data input that is coupled to said source;
third means coupled to said background memory and responsive to said television signal and to said clock signal for identifying in a given video line, said data sequence of said clock run-in portion of said data line and for storing in said background memory such video lines that are identified as data lines but only when individual bits of said data sequence of said clock run-in portion are correct, said first means storing said data lines such that prior to the generation of said first control signal, said background memory already contains a substantial number of stored data lines of said television signal;
fourth means responsive to said first control signal and coupled to said background memory for controlling during a given interval that follows the generation of said first control signal, read-out from said background memory of a plurality of stored data lines of said television signal, suc
h that the duration of said given interval is substantially
shorter than that of a corresponding interval between the occurrence
of an initial data line of said plurality of data lines and the
occurrence of a final data line thereof, so as to reduce access time to
said plurality of data lines, said fourth means controlling read-out
of said plurality of data lines in a first-in, first-out manner for
generating during said given interval, a data signal that contains the
data of said plurality of data lines; and a data processor responsive to said data signal for selecting said one data line to generate in accordance therewith said output signal.
32. An apparatus according to claim 31 wherein said third means identifies said video line as data line when data sequence of a framing code portion immediately follows said data sequence of said clock run-in portion. 33. An apparatus according to claim 31 wherein said third means identifies said video line as data line by identifying a 12 bit sequence (101011100100) in data that are derived from said video line.
This
invention relates to a teletext decoder employing a so-called
background or buffer memory for storing multipages of teletext incoming
data. 
Teletext is a television-based communication technique in which a given horizontal video line is utilized for broadcasting textual and graphical information encoded in a digital binary representation. Such horizontal video line signal that contains teletext data is referred to herein as a Data-line. It is assumed herein, for explanation purposes, that teletext is sent by the broadcaster only during the vertical blanking interval (VBI), when no other picture information is sent. The organization of the binary information in the broadcast signal is determined by the standard employed by the broadcaster. By way of an example only, references are made herein to a teletext based on a standard referred to by the British Broadcasting Corporation (BBC) as CEEFAX.
Each Data-line carries data synchronizing and address information and the codes for a Row of 40 characters. The synchronizing information includes a clock run-in sequence followed by an 8-bit framing code sequence. Each Data-line contains a 3 bit code referred to as the Magazine number. A teletext Page includes 24 Rows of 40 characters, including a special top Row called the Page-Header. Each ROW is contained in a corresponding Data-line. A user selected Page is intended to be displayed in place of, or added to a corresponding television picture frame. A Magazine is defined to include Pages having Data-lines containing a corresponding Magazine number. The transmission of a selected Page begins with, and includes its Page Header and ends with and excludes the next Page Header of the selected Magazine number. All intermediate Data lines carrying the selected Magazine number relate to the selected Page.
FIG.
1 illustrates a block diagram of a conventional teletext decoder that
includes an integrated circuit (IC) referred to herein as video input
processor (VIP) such as, for example, of the type SAA5231 made by
Philips Corporation. The VIP receives a baseband composite video signal
VIDEO that contains Data-lines. The VIP performs data slicing, clock
regeneration and timing synchronization functions and generates a serial
data signal DATA and an associated clock signal CLOCK Signals DATA and
CLOCK represent the data contained in the horizontal video lines.
Signals DATA and CLOCK are coupled to a second IC of the decoder,
referred to herein as computer controlled teletext IC (CCT) that
includes a data processor responsive to signals DATA and CLOCK. An
example of such CCT is IC SAA5243 made by Philips Corporation. The CCT performs data acquisition and interface function with a page memory that is included in the teletext decoder. For example, only a teletext Page requested by the user is derived by the CCT from the serial data and clock signals and stored in the page memory. The CCT also generates video display signals R,G, and B from the teletext data stored in the page memory to provide corresponding drive signals that contain picture information for display in the receiver picture tube (CRT), not shown.
A control microcomputer, not shown in FIG. 1, that is responsive to user initiated commands, generates control and status messages. The messages are coupled via, for example, a standard IIC bus to the CCT, for controlling the operation of the CCT.
A total of, for example, 500 Pages may be periodically transmitted during each interval of 15-45 seconds, depending on the number of Data-lines used for teletext during the VBI. Consequently, if the teletext Page is not already stored in memory when a new user page request occurs, the user may experience a nuisance as a result of waiting a maximum of 15-45 seconds until the requested Page is displayed. It may be desirable to reduce such Page access time. It may also be desirable to utilize in the teletext decoder a standard CCT such that the reduction of the access time is provided as an add-on feature to the teletext decoder.
A teletext decoder, embodying an aspect of the invention, includes a background or buffer memory that is capable of storing multi-Pages of teletext data. The portion of serial data signal DATA generated by the VIP that meets a predetermined identification criteria and, therefore, assumed to represent a Data-line is stored in the buffer memory. At any given time after the operation of the buffer memory is enabled, such as immediately after the user turns on the television receiver, the buffer memory contains, for example, the most recently received teletext Pages. The maximum number of such Pages that can be contained in the buffer memory at any given time is determined by the buffer memory Page storage capacity.
In order to reduce the size of the hardware required to identify each video line that is assumed to be a Data-line, only a limited, rather than a complete identification operation, is initially performed. The complete identification is accomplished in the CCT, during a read-out operation, when the data is read-out of the buffer memory.
In
accordance with a feature of the invention, the limited identification
operation for identifying a given Data-line is accomplished by
identifying in a video line signal data of a sequence of the clock
run-in that is immediately followed by a sequence of the framing code.
When, for example, both sequences are identified it is assumed that a
Data-line is identified. Therefore, a portion of such identified
Data-line that contains relevant data bits is stored in the buffer
memory. Otherwise, the video line information is not stored in the
buffer memory. The inclusion of the test for the data of the clock
run-in sequence, advantageously, reduces the probability that the data
that is stored is, in fact, not a Data-line. When the user's page request occurs, the data processor of the CCT receives the data that have been stored in the buffer memory and searches for the presence of a Data-line representing a Page Header of the requested Page. The search operation that is included in the read-out operation begins when the first data is read out of the buffer memory following the occurrence of the user's page request.
Memory read-out cycles occur between VBI's, when no teletext data is received. If the Page Header of the user requested teletext Page is found in the buffer memory in the course of such memory scan or search operation, the stored data of the Page Header is transferred to the page memory.
During the search operation, the CCT operates in the full channel operation mode. In the full channel operation mode, the Data-lines in the buffer memory are read out and transferred to the page memory in a first-in, first-out manner and without encountering large time gaps. Such large time gaps occur when teletext information is received by th
e CCT only
during the VBI's. Therefore, the search operation occurs faster than if
the Data lines were received, unbuffered, only during the VBI's. For
example, the access time to a teletext Page that is already contained
in a buffer memory capable of storing 500 teletext Pages may be reduced
to, for example, 0.8 seconds that is, advantageously, substantially
shorter than the 15-45 seconds maximum access time, referred to before.
Furthermore, should more than, for example, 600 pages be transmitted,
the access time for a page which, at the time the user page request
occurs, is not already stored in the memory, is reduced by the time
required to fill the buffer memory with teletext data. 
After the Page Header is identified in the CCT, other Data-lines that are associated with the requested Page and that are stored in the buffer memory are read-out. On the other hand, if no Page Header Data-line of the requested teletext Page is found in the buffer memory in the course of the search operation, the unbuffered data received from the VIP will be coupled, after the end of the search operation, directly to the data processor of the CCT such that the buffer memory is bypassed.
When a buffer memory with large storage capacity is utilized, the read-out operation that was explained before may require a longer interval than the interval between consecutive VBI's. It may be desirable to store incoming Data-lines in the buffer memory that occur during the intervening VBI's prior to the completion of the read-out operation. If such incoming Data-lines of the Page requested by the user were not stored, an undesirable situation might have occurred in which only a partial Page is temporarily displayed on the CRT. Such temporary condition may continue until after the time when the same Page is re-transmitted.
In the teletext decoder, embodying an aspect of
the invention, the read-out operation in the buffer memory occurs only
outside the VBI's. Data-lines are stored in the buffer memory during
the VBI's that occur prior to the completion time of the read-out
operation. Therefore, Data-lines that were stored in the buffer memory
after the read-out operation has been initiated and prior to its
termination may be read-out and processed by the CCT. In this way,
advantageously an incoming Data-line that is included in the teletext
Page that is requested may be processed during the read-out operation 
Each Data-line is stored in the background memory and provided to the CCT in a format that can be readily processed by the CCT. For example, a Data-line is stored as 344 bits that include a byte containing the framing code, two bytes containing hamming codes and forty bytes containing the remaining data.
The buffer memory of the decoder of the invention is organized as a serial memory such as, for example, a first-in, first-out memory (FIFO). For example, immediately after teletext signal is received in the television receiver, the Data-lines are stored in the FIFO even if no user page request occurs. Thus, at the time the user changes the mode of operation of the television receiver from providing normal picture program to providing teletext information, the most recently received teletext data are already stored in the buffer memory.
The buffer memory may utilize, advantageously, a dynamic random access memory (DRAM) of a large capacity that operates as a FIFO. The DRAM may be refreshed between VBI's. A given storage location of the FIFO may be addressed by a read address pointer during the memory read-out operation and by a write address pointer during the VBI's when memory store-in operation occurs. By using separate read and write address pointers, the aforementioned advantage of storing Data-lines while the read-out operation is incomplete may be realized.
A television apparatus, embodying an aspect of the invention, is responsive t
o an incoming television
signal containing video lines that carry text data, defining
corresponding data lines for generating an output signal that is
capable of providing picture information to a display device. A first
control signal is generated in order to select one of the data lines to
be used in conjunction with the generation of the output signal. A
first-in, first-out background memory has a data input that is coupled
to an output of a source of the television signal. Storage of
corresponding data lines of the television signal in the background
memory occurs each time such corresponding data lines occur. Prior to
the time the first control signal is generated, the background memory
already contains a substantial number of stored data lines of the
television signal. During a given interval that follows the generation
of the first control signal, read-out from the background memory of a
plurality of data lines of the television signal that have been stored
before the end of the given interval occurs. The given interval has a
duration that is substantially shorter than that of a corresponding
interval between the occurrence of the first one of the plurality of
data lines and the occurrence of the last one so as to reduce access
time to the plurality of data lines. Read-out of the plurality of data
lines occurs in a first-in, first-out manner for generating during the
given interval a data signal that contains the data of the plurality of
data lines, including data lines that have been stored in the
background memory during the given interval. A data processor is
responsive to the data signal for selecting the one data line to
generate in accordance therewith the output signal. FIG. 1 illustrates a prior art teletext decoder;
FIG. 2 illustrates a rapid access teletext decoder, embodying a feature of the invention;
FIG. 3 illustrates a diagram that is useful for explaining the operation of a first-in, first-out background memory of FIG. 2;
FIG. 4 illustrates a flow chart that is useful for explaining the operation of the teletext decoder of FIG. 2; and
FIG. 5 illustrates a detail schematic of a linear feedback shift register that is used to provide an address pointer for a background memory of FIG. 2.
FIG.
2 illustrates a block diagram of a rapid access teletext decoder,
embodying an aspect of an invention. Similar symbols and numerals in
FIGS. 1 and 2 indicate similar items or functions. A baseband composite video signal VIDEO of FIGURE 2 is coupled from a video detector, not shown, to a VIP 20, such as, for example, of the type SAA5231. VIP 20 generates from signal VIDEO a serial data signal TTDout at a bit rate of 6.9375 MHz and a corresponding clock signal CLOCK that provides timing information of the bits of signal TTDout. VIP 20 also generates a video composite sync signal VCS derived from signal VIDEO. Signal VCS is coupled to a CCT 30 such as, for example, of the SAA5243 IC type. In turn, CCT 30 generates a signal SAND containing the phase locking and color burst blanking information. Signal SAND is coupled back to VIP 20 to provide horizontal phase-locking information to an oscillator of VIP 20, not shown.
The serial data contained in signal TTDout are coupled to a serial-to-parallel converter 35 that includes a shift register, not shown. Serial-to-parallel converter 35 generates a parallel word 35a that is coupled to an identification unit 40.
In accordance with an aspect of the invention, unit 40 tests for the occurrence, in signal TTDout, of a 12-bit sequence (101011100100) of bits in the data stream, representing a 4-bit clock run-in sequence immediately followed by the framing code. The checking for the occurrence of such 12-bit sequence is performed during a time window of 2.7 microsecond, starting 11.8 microseconds after the leading edge of a horizontal sync portion, not shown, of signal VIDEO. Such checking is done for each video line during the possible teletext lines, 6-22 and 319-335, that occur in the VBI's of the corresponding field portions of signal VIDEO.
When the 12-bit sequence is recognized, it is assumed that the video line represents a Data-line of teletext. After an assumed Data-line is identified, only, for example, 344 bits of the assumed data-line are stored in a buffer memory 45, operating as a FIFO. Advantageously, the checking for the 4-bit clock run-in sequence reduces a probability that nonteletext data of a video line that is not a Data-line will be stored in memory 45.
A timing and control unit 100 receives signals SAND, VCS and CLOCK and generates corresponding control signals that, for example, control the operations associated with memory 45, such as the operation of identification unit 40.
It may be desirable to utilize a DRAM IC of a large storage capacity such as, for example, of the 1,098,586 (2 20 ) bit organization as the main storage element of buffer memory 45. This is so in order to provide a storage capacity for a substantial number of teletext Pages. Also, in order to reduce the cost and power dissipation of memory 45 it may be desirable to utilize DRAM's with slow access or cycle time that are typically less expensive. Therefore, the serial teletext data in signal TTDout is converted by converter 35 to 4-bit parallel words, or nibbles 35b. The bits of each nibble 35b are stored simultaneously in buffer memory 45, organized as, for example, a four-bit-wide DRAM. In this way, the DRAM cycle time may be longer than the teletext bit rate.
For each assumed Data-line, the nibble that is firstly stored in buffer memory 45 corresponds to the most significant nibble of the framing code. Thereafter, the remaining consecutively occurring 85 nibbles are stored. The clock run-in bits need not be stored.
A write counter 55 generates a write address pointer, or word W-COUNT that is coupled via a multiplexer/comparator 60 to an address port 45a of memory 45. FIG. 5 illustrates a combination of a schematic diagram and a block diagram of counter 55 of FIG. 2. Similar numerals and symbols in FIGS. 2 and 5 indicate similar items or functions.
Write counter 55 of FIG. 5 includes a 6-bit conventional binary counter 551 that produces 6 bits, A0-A5, of word W-COUNT. The most significant bit of counter 551, bit A5, is coupled to a corresponding clock input terminal CP of each flip-flop of a conventional 14-bit linear feedback shift register (LFSR) counter 552. Counter 552 includes 14 D-type flip-flops that form a shift register The input to a data input terminal of a first flip-flop 552a in the shift register chain of the flip-flops is formed by applying suitable EXCLUSIVE 0R operations on output signals of the first, third, fifth and fourteenth flip-flops in the shift register chain, in a well known manner.
LFSR counter
552 requires less hardware and is faster than a conventional binary
counter since it avoids the carry propagation associated with the
conventional binary counter. LFSR counter 552 goes through a complete
sequence cycle every 2 14 -1 pulses of bit A5 of binary counter 551. Binary counter 551 goes through a complete sequence cycle every 2 6
clock pulses at an input terminal 551a of counter 551. Consequently,
each of counter 55 and word W-COUNT sequences through a complete
predetermined cyclical sequence every 2 20 -64 clock pulses that occur at input terminal 551a. The address of each nibble that is stored is supplied by word W-COUNT of counter 55 of FIG. 2. The value of word W-COUNT is changed to the next or consecutive value in the predetermined cyclical sequence of counter 55 after each nibble is stored. The number of different values in such cyclical sequence that is, for example, (2 20 -64), is equal to the number of nibble storage locations utilized in memory 45. Therefore, advantageously, each DRAM, having 2 20 locations, is substantially fully utilized. The number (2 20 -64) is equal to an integer multiple of 86, the number of nibbles required for storing the 344 bits of each Data-line. As a result of the FIFO operation, a maximum of (2 20 -64) divided by 86 of the most recently received Data-lines can be stored in buffer memory 45 of FIG. 2.
FIG. 3 illustrates, schematically, the cyclical sequence of word W-COUNT of write counter 55. Similar numbers and symbols in FIGS. 2, 3 and 5 depict similar items or functions. The cyclical sequence includes 2 20 -64 values distributed in a circular manner from a l to a Q where Q=2 20 -64. Thus, for example, after a nibble location, depicted as a n in FIG. 3, is stored in memory 45 of FIG. 2, the next nibble to be stored in memory 45 is stored in a location depicted as a n +1 in FIG. 3, and so forth.
The number of different values in the cyclical sequence of counter 55 of FIG. 2 is equal to an integer multiple of 86. Therefore, Data lines are stored, for example, always in the same corresponding groups of
86 nibbles of memory 45, such as, for example, a 1 -a 86
of FIG. 3. The most significant nibble of the framing code is stored,
for example, always at the same memory locations of memory 45. This
feature, advantageously, simplifies the hardware complexity of unit 100
of FIG. 2 that controls memory 45. FIG. 4 is a flow chart depicting the operation of the teletext decoder of FIG. 2 after a page request for displaying requested Page on a CRT, not shown, is initiated by the user. Similar numerals and symbols in FIGS. 2-5 indicate similar items or functions. A given user page request that is communicated to a microcomputer 65 of FIG. 2 via a keyboard, not shown, causes microcomputer 65 to generate a clear page memory command signal. Such command signal is coupled via a conventional IIC bus to CCT 30. CCT 30 stores in all the memory locations of a page memory 70, in response to the clear page memory command signal, "blank" characters, referred to as page memory clearing operation. After a 22 millisecond interval of the memory clearing operation has elapsed, microcomputer 65 sends a second command signal to CCT 30 that causes CCT 30 to begin operating in a mode of operation referred to as full channel operation mode, as shown in step d of FIG. 4.
In the full channel operation mode, data is received by CCT 30 of FIG. 2 during each video line in a given frame interval of signal VIDEO. In comparison, in normal field flyback operation mode, data is received for processing by CCT 30 only during lines 6-22 and 319-325 of the VBI's of the corresponding field intervals of signal VIDEO.
In a next step, e, of FIG. 4
,
microcomputer 65 30 of FIG. 2 sends a corresponding page request
command signal to CCT 30. As a result, CCT 30 stores, via a bus 70a, a
corresponding word in page memory 70 containing a bit referred to as
Page Being Looked For (PBLF) bit at a TRUE state. Simultaneously,
timing and control unit 100 decodes the information on bus 70a and a
corresponding flip-flop, not shown, of unit 100 causes a control signal
FLAG to assume a TRUE state that initiates a read-out interval, or
operation in memory 45. To perform the read-out operation in memory 45, a read address counter 50, controlled by unit 100, is utilized. Counter 50 that may be constructed similarly to Counter 55 generates a read address pointer, of word R-COUNT that is coupled via multiplexer/comparator 60 to address port 45a of memory 45. Immediately prior to the time in which the first memory location of memory 45 is read out following the page request command signal, that defines the beginning time of the read-out operation, counter 50 is preset to form word R-COUNT having a value that is identical to that already contained in word W-COUNT. Word W-COUNT is coupled via timing and control unit 100 to an input port 50a of read address counter 50. In order to preset counter 50, a control signal is coupled to a corresponding terminal of port 50a, thereby causing the value of word W-COUNT to be stored in counter 50. The result is that word R-COUNT is made equal to word W-COUNT. An example of an initial condition of the read-out operation is depicted in FIG. 3 by the arrows representing words R-COUNT and W-COUNT that point both to location a n .
A parallel-to-serial converter 75 of FIG. 2, converts each nibble 45b generated at a read-out output port of memory 45 to a serial data signal TTDin. The bits of signal TTDin at a terminal 75a of converter 75 occur at the standard teletext bit-rate. After each location is read out from memory 45, word R-COUNT changes to contain the consecutive value in the cyclical sequence that was mentioned before and the content of the next consecutive location is read out. Thus, the arrow in FIG. 3 that represents schematically word R-COUNT "moves" angularly in the same angular direction that has been associated with the "movement" of &he arrow representing word W-COUNT. As a result, signal TTDin of FIG. 2 contains data lines that correspond with the originally stored data-lines of signal VIDEO and that are read out from memory 45 in a first-in, first-out manner.
Serial data signal TTDin is coupled via a switch 80, controlled by signal FLAG, to a teletext data input terminal TTD of CCT 30 when signal FLAG is TRUE. Signal TTDin is processed by CCT 30 in the full channel operation mode. Therefore, advantageously, the length of the read-out interval that is required for reading out and processing in CCT 30 a given number of corresponding Data lines that are contained in signal TTDin is, advantageously, substantially shorter than if such Data lines were received at input terminal TTD of CCT 30 only during the VBI's.
In
steps f and g of FIG. 4, CCT 30 of FIG. 2 performs a search operation
for identifying, in signal TTDin, a Data-line representing the Page
Header data line of the user requested page, as depicted in an exit
point "yes" from step f of FIG. 4. The Page Header is recognized in CCT
30 of FIG. 2, unlike in unit 40, by utilizing also hamming code
checking When the Page-Header data line is identified, CCT 30 stores a
corresponding word in page memory 70 via bus 70a that is related to the
Page-Header and that causes bit PBLF to become FALSE. Afterwards, as
shown in steps k, 1 and m of FIG. 4, Data lines are read out from
memory 45 of FIG. 2. Each Data line that is related to the requested
Page is identified in a well known manner and stored in page memory 70.
In accordance with another feature of the invention, at the end of a time-out interval TO1 following the time when bit PBLF becomes FALSE, timer 100a of FIG. 2 causes signal FLAG to become FALSE. This situation is shown in an exit point "yes" in step m of FIG. 4. Consequently, the read-out operation that is controlled by unit 100 terminates. Termination of the read-out operation may also occur prior to the end time of interval TO1, as described later on. Time-out interval TO1, has a length of, for example, between 20-40 milliseconds, from the time bit PBLF became FALSE. During interval TO1, the read out operation continues in a similar manner that was explained before in the full channel operation mode of CCT 30.
It is assumed that the entire requested Page can be read out of memory 45 during interval TO1 following the time the Page-Header data line is identified. Thus, if, for example, two Page Headers that represent the same requested Page are stored in memory 45, only the first one to be read out during interval TO1 is processed by CCT 30; whereas, the other Page Header and the corresponding Data-lines associated with that Page are not read out of memory 45 during interval TO1 and are neither received nor processed in CCT 30.
Terminating the read-out operation after interval TO1 has elapsed, advantageously, prevents a visually undesirable condition from occurring in which the teletext picture on the CRT, not shown, changes, for example, twice for a given user page request. Such undesirable condition could have occurred as a result the aforementioned two Page-Headers that are stored in memory 45.
The read-out operation also terminates, prior to the end of interval TO1, when it is detected that all the data stored in memory 45 have been read out. Such situation occurs, for example, if no Data-line stored in memory 45 that contains the Page Header is identified, as shown in step g of FIG. 4. Such situation also occurs at an exit point "yes" in step 1.
When all the data stored in memory 45 of FIG. 4 have been read out, prior to the end of interval TO1, an output signal EQUAL of the comparator portion o
f
multiplexer/comparator 60 of FIG. 2 becomes TRUE. Signal EQUAL becomes
TRUE when word R-COUNT becomes equal to word W-COUNT. Signal EQUAL at
the TRUE state causes signal FLAG to become FALSE that causes the
read-out operation to terminate. Signal FLAG is prevented from assuming
the TRUE state until after word R-COUNT is incremented at least once.
Thus, signal FLAG will not assume prematurely the TRUE state. The situation when signal EQUAL becomes TRUE in step 1 or g of FIG. 4 is depicted by the position of the arrow in FIG. 3 representing word R-COUNT. After moving angularly around the circle, that arrow points to the same location, at the end of the read-out operation of memory 45 of FIG. 2, as the arrow representing word W-COUNT of FIG. 3.
During the read-out operation, read out memory cycles in memory 45 of FIG. 2, depicted in steps f, g, k, 1 and m of the flow chart of FIG. 4, occur only outside the VBI of each field interval of signal VIDEO of FIG. 2. Because the storage capacity of memory 45 is large, the read-out operation may require a substantially longer period than o
ne period
between a pair of consecutive VBI's. In accordance with another aspect of the invention, during the intervening VBI's, that occur from the time the read-out operation begins to the time the read-out operation terminates, the Data-lines that occur then in signal VIDEO are stored in memory 45 that operates as a FIFO. Data-lines that are stored in memory 45, during the intervening VBI's of the read-out operation, or interval, are made available for processing by CCT 30, if required, during the read-out operation. Advantageously, this feature prevents an undesirable situation in which, instead of a complete Page, only a partial Page is derived from the data lines stored in memory 45 and displayed on the CRT, not shown. Such partial Page might have been displayed if some Data-lines, associated with the same requested Page, occur in signal VIDEO but were not stored in memory 45 during the intervening VBI's that occur after the time the read-out operation began. If such Data-lines were not stored in memory 45, they cannot be processed in CCT 30 in step k of FIG. 4. Consequently, they will not be stored in page memory 70 of FIG. 2.
Assume, for explanation purpose, that the position of the arrow representing word W-COUNT in FIG. 3 has changed angularly as a result of storing Data-lines in memory 45 of FIG. 2 during the intervening VBI's that occur prior to the termination of the read-out operation. The position of such arrow has changed from the initial position, pointing to location a n of FIG. 3, to a new position pointing to location a p . During the read-out operation, the data of the data lines that were stored during the intervening VBI's may be read out and the position of the other arrow, representing word R-COUNT, may "move" angularly around the circle more than a full circle, as shown by a helix 666. Thus, when the arrow representing word R-COUNT points to the same location, a p , at the end of such read-out operation, signal EQUAL of FIG. 2 will become TRUE. Signal EQUAL indicates that of all the data in the FIFO has been read out, as shown in exit point "yes" of step 1 of FIG. 4.
The
read-out operation from memory 45 of FIG. 2 may
terminate, in an exit point "yes" step g of FIG. 4, when no Page-Header
data line has been identified or in an exit point "yes" of step 1.
Termination at each of these exit points occurs prior to the end time
of interval TO1 and after all the memory locations of memory 45 of FIG.
2 have been read out. It is assumed that all the memory locations of memory 45 have been read out after a second time-out interval TO2 of, for example, 0.8 seconds, has elapsed from the time microcomputer 65 has sent the page request command signal to CCT 30. The page request command signal has been referred to in step e of FIG. 4.
In accordance with a further aspect of the invention, after interval TO2 has elapsed, microcomputer 65 of FIG. 2 sends a command signal to CCT 30 that causes CCT 30 to operate in a field flyback operation mode. Advantageously, microcomputer 65 establishes time out interval TO2 by a software routine without the need for obtaining information from CCT 30 or from unit 100.
At the end of the read-out operation, signal FLAG of FIG. 2 becomes FALSE, as explained before. In the FALSE state of signal FLAG, switch 80 couples signal TTDout of VIP 20 to terminal TTD of CCT 30, directly, in preparation for field flyback operation mode of CCT 30 that follows, as described below.
In the field flyback operation mode, signal FLAG is FALSE, as explained before, and signal TTDout is coupled to terminal TTD and processed by CCT 30 such that memory 45 is bypassed. Thus, incoming teletext Data-lines related to the Page that is displayed on the CRT are processed in the field flyback operation mode of CCT 30 only during the VBI's, in a conventionally known manner.
Because memory 45 is a serial memory, or FIFO, the memory location in memory 45 in which a given Data line of signal VIDEO or of signal TTDin is stored is "transparent" with respect to CCT 30. Therefore, advantageously, CCT 30 can be implemented using the same type IC, such as of the SAA5243 type, that is used in the prior art teletext decoder of FIG. 1. Thus, inclusion of memory 45 of FIG. 2 in the teletext decoder does not have to affect the hardware complexity of CCT 30.
Timing and control unit 100 controls the appropriate timing of the identification operation of unit 40 during the VBI window. It controls the store-in and the read-out operations and the refreshing of the DRAM's of memory 45. Modern DRAM's may have to go through a refresh cycle every, for example, 8 msec, in each of 512 address rows of the DRAM. To accomplish the refresh cycles during the read-out operation, nine (9) predetermined bits of word R-COUNT of read address counter 50, such as, for example, A0-A6, A13 and A15 of FIG. 5, are applied to the row address lines of the DRAM's during the read-out operation The nine predetermined bits change in counter 50 during the read-out operation in such a way that at least all the 512 possible binary combinations of the nine bits occur within each 8 millisecond interval. A read cycle, besides accessing a particular memory location, also performs a refresh cycle of the memory address row that is addressed. In this way, during the read-out operation, all the 512 address rows of the DRAM's are refereshed.
When no read-out operation occurs in memory 45, such as when no page request is pending, unit 100 effectuates what is known as "CAS before RAS" refresh operation. In the "CAS before RAS" refresh operation, CAS and RAS control signals of the DRAM's, not shown, are generated by unit 100 at a predetermined rate to form refresh cycles. On the other hand, when a page request is pending, the read-out operation occurs and the aforementioned "CAS before RAS" refresh operation is replaced by read cycles that occur during the read-out operation. Thus complete refresh operation of the DRAM's is guaranteed.
Data sheet for videotext data slicer and clock regenerator SL9100EXP, publ. by Plessey Semiconductors Ltd. (Attention to Fig. 4).
"Applications of Picture Memories in Television Receivers", Berkhoff, et al., published in IEEE Transactions on Consumer Electronics, vol. CE-29, No. 3, Aug. 1983.
Philips publication No. 9398 401 30011, dated
Jan. 1985, entitled "ICS for Computer Controlled TV Memory Based
Feature", pp. 27-41. Development data sheet, dated 1986, entitled "SAA9030 Background Memory Controller", published by Philips Corp.
Development data sheet, dated 1988, entitled "SAA9040 Computer Controlled Teletext Extension (CCTE)", published by Philips Corp.
User's Manual, entitled "Computer Controlled Teletext User's Manual", dated 1983, by J. R. Kinghorn, published by Mullard Application Laboratory.
IBA Technical Review, No. ISSN 0308-423 X entitled "Specification of Standard for Broadcast Teletext Signals."
Design Handbook entitled "The Programmable Gate Array Design Handbook", dated 1986, published by Xilinx Co., San Jose, California, pp. 2-114 to 2-117.
Data Book Entitled "the Programmable Gate Array Data Book", including a note entitled Megabit FIFO in two Chips: One LCA and One Dram, by Alfke, published 1988 by Xilinx Co., pp. 6-35 and 6-36.
MAB8461P
8-Bit Microcontroller-Microcomputer - Use w/8080/85 periph,8-bit LED driver
Various
8-Bit Microcontrollers,LEDs,LED Drivers
Clock Frequency - Max. (Hz)=6.0M
Clock Frequency - Min. (Hz)=1.0M
Min Instruction Length (bits)=8
Max Instruction Length (bits)=16
Memory Addressing Range=8k
Number of Addressing Modes=5
On-Chip RAM (Bytes)=128
On-Chip ROM (bytes)=6k
Number of Interrupt Lines=2
No. of Non-Maskable Interrupts=0
Number of Maskable Interrupts=0
Number of I/O Lines=20
No. of I/O Ports=4
Vsup Nom.(V) Supply Voltage=5.0
Status=Discontinued
Package=DIP
Pins=28
Military=N
Technology=NMOS
--------------------------------------
PHILIPS CHASSIS G90AE FAULT/DEFECTS SERVICING:
Philips G90 Frame collapse. Drys on left hand side of convergence panel.
Philips G90 bright raster - poor field lin 163v line low at 90v - R3570 8R2 o/c
Philips G90 Continuous page header display in subtitle Change text IC to type MAB8461P/W196 part No4822 209 62479
Philips G90 CONTRAST CONTROL LIMITED C2560 ( 33nf ) LEAKY PIN 7 , LOPT.
Philips G90 Dead chopper transistor s/c. Also change CNX83A optocoupler part No.4822 130 82034
Philips G90 Dead. Check for drys on chip diodes.
Philips G90 field collapse D6465 sm
Philips G90 Frame collapse. Wickman fuse to o/p transis o/c , R3503/07 , R3501 390k o/c.
Philips G90 Int loss of tuning X2402 eeprom chip
Philips G90 No blue. D6416 ( BAS32 ) leaky.
Philips
G90 NO LINE OSC IF VOLTAGE ON PIN 16 TDA2579 IF NOT 9v CHECK ACROSS
D6455 5v6 ZENER IF OK HERE REPLACE T7455 IF NOT REPLACE ZENER
Philips G90 no start up - tripping D6611, 6613, 6614 BAS32
Philips G90 off with s/by led flashing ht low & pulsing - R3632 15k in prot cct u/s - C2630 & R3668 also possible
Philips G90 Picture too big Replace T7652 & CNX83 opto
Philips G90 SET WORKS BUT NO TEXT AND F7 DISPLAYED ON SCREEN NO RESET PULSE TO IC7800 CHECK TR7846 AND C2843 220uF
Philips G90 snowy pic check pin 6 tuner. If absent check R3001 15R
Philips
G90 Tripping R3668 sm 150R Philips G90 Tripping - works on reduced HT
D6656 33v prot zener in HT sensing faulty - replace all 3
Philips G90 trips after few mins operation Tr7652 BC557C
Philips G90 Tuning - drift but green line moves. ZTK33B 33v stabiliser.
Philips G90 Verticals corrugated C2630 ( 47uF )
Philips G90AE Blank raster - text Ok. C2569 ( 33nf ) o/c.
Philips
G90AE Blank raster - Txt OK pin 7 TDA3561A was -ve instead of 3.4v;
C2560 33nF o/c Philips G90AE Blank raster , no sound , no OSD. IC
TMP47C434N-3555 IC7720.
Philips G90AE Blank raster with no sound.
OSD or response to R/C IC7720 reset line pin 33 stuck at 2v - chip had
internal leak TMP47C434N-3555 Philips G90AE BLANK SCREEN NO SOUND RESET
AT 2v IC7720 PIN 33 IF DROPS WHEN PIN 33 ISOLATED REPLACE IC
TMP47C434N-3555 Philips G90AE Blocks/Wrong OSD-indication Disconnect
pins 2 and 3 IC 7800 (TXT-uP), set functions normally. Replace IC 7800
(MAB 8461P/W196; 4822 209 62479).
Mount metal shielding 4822 466 82783 on uP (IC 7720) with earth to jumper 9711.
Philips G90AE Characters wrong Replace IC 7820 (SAA 5243P/E; 4822 209 30556) and
replace IC 7800 (MAB 8461P/W196; 4822 209 62479)
Philips
G90AE Cogging effect C2630 47µ 160v HT res cap also change C2631
smoother Philips G90AE Dark picture - no remote commands. Replace IC
7720.
Philips G90AE Dead D6617 6v2 zener s/c; R3668 150R sm dry joint
Philips
G90AE Dead - BIT11AF chopper s/c fit repair kit Pt no 4822 310 20496
tells you to fit 2 x 1N5061. Connect in series between chopper tr base -
emitter (anode to base)
Philips G90AE Dead - blows BUT11AF chopper
even with kit fitted o/c between pin 18 of chopper tfrmr & D6645 due
to o/c sm link 3645
Philips G90AE Dead - Full HT 95v with 120v ac I/p HT reduces as mains I/p is increased - D6653 BAS32 in psu sec s/c
Philips
G90AE Dead - mains fuse shattered BUT11AF s/c - fitted repair kit &
dry joint R3610 24k; 3 x BZV55/F33 6657/8/9 s/c sm. MAKE SURE SET IS
NOT IN ST/BY WHEN CHECKING- IF SW OFF OIN ST/BY WILL COME BACK ON IN
ST/BY
Philips G90AE Dead - no 95v HT to LOP stage Crack in print by runner at edge of pcb in 95v supply line
Philips G90AE Dead - no o/p from psu Thy 6670 SFOR5D43 s/c
Philips G90AE Dead - PSU o/ps low Tr7654 BC847C leaky
Philips G90AE Dead - s/c on lop stage LOPTx faulty though tested ok on tester
Philips G90AE Display - shows F4 or F7. Replace IC 7720.
Philips
G90AE Displaying error code F7 extremely intermittently. Error code
denotes fault in text circuit. If possible when fault condition present,
check +5 volts to text chips. If 5 volts is missing, check/replace SMD
link - 3901 in text circuit.
Philips G90AE Does not function Voltage +95 V not present
Mount SOPS repair kit (SBC 7023; codenumber 4822 310 20496)
Philips
G90AE Does not function well Wrong characters on screen. Replace IC
7720 by repairkit 4822 310 31848. This repairkit consists of IC7720
(TMP47C434N-3555) and a metal shielding. Philips G90AE Does not tune
optimally Re-adjust S5034 and S5035. See service manual CHASSIS G90AE
(4822 727 16447) page 4 points 10 and 11.
Philips G90AE Error code
F7 after loptx replacement F7 code denotes fault in Txt - C2843 220µ 16v
& replace C2640 & C2660 680µ
Philips G90AE F7 displayed, no snd, pic ok. (all OK when warm) C2843 (220uf 25V; 4822 124 41545).
Philips G90AE Fault codes F4 or F7 with no sigs & LED orange EEPROM
or Txt chip faulty - use of heat & freezer usually determines
faulty comp. If reset with EEPROM chip hot does not work then chip is
faulty
Philips G90AE Field collapse Wickman fuse in supply to FOP
chip o/c but R3503 & 3507 22R overheat when fuse replaced - R3501
390R leaky
Philips G90AE Field reduced height with top foldover R3508 24k hi res
Philips G90AE Flash-overs on the CRT board. Replace C2397 by a new type code 4822 121 41926.
REMARKS
: The code number published in the report "complaints of the steco
segment" dated 1992-02-14 was not correct. Production has been adapted
from week 9149 onwards.
Philips G90AE Foldover with fb lines - only present in 4:3 Voltage at cathode of diode 6570 95V Should be 163V. O/C R3570
Philips G90AE For 5 minutes zigzag edges in the picture C2630 (47uF/160V; 4822 124 41056).
Philips G90AE Humming, ticking Replace thyristor 6670. (SFOR5D43, 4822 130 20245).
Philips G90AE If +95V is 1) 30V, 2) 50V, 3) 80V 1) diode 6546 (BYD33M; 4822 130 42489)
2) diode 6653 (BAS32; 4822 130 80446) 3) diode 6613 (BAS32; 4822 130 80446)
Philips G90AE Int dead Dry joints R3671 sm res - feeds from Tr7671 to thy 6670 gate
Philips G90AE Int loss of col, sound, random chan change & "F4" int shows Replace micro/EEPROM IC7600 & IC7601
Philips G90AE Int loss of line/field sync Resolder 6k8 sm under C2473
Philips G90AE INT SOUND D6272 BAS32 INT OC IN 20v FEED TO TDA8191
Philips G90AE Int st/by, loss of sigs, col, contrast Proc chip TMP47C43N-3555 faulty - replacement has metal shield
Philips G90AE Intercarrier-hum Adjust coil S 5115 for minimum hum.
See service manual CHASSIS G90AE (4822 727 16447) page 4 point 13
Philips G90AE Keeps interrupting R3672 (4K7; 5322 111 90111).
Philips G90AE LED blinks in stand-by mode Check/replace thyristor 6670 (SFOR5D43; 4822 130 20245).
Philips
G90AE LINE PAIRING TOP HALF OF SCREEN C2475 ( 33n ) DECOUPLES PIN 2
OF IC7470 Philips G90AE Lines - fine dark horiz when heated Dry joints
tuner
Philips G90AE Lines in picture. Check/replace R 3570 (8,2 Ohm; 4822 052 10828)
Philips
G90AE Low EHT with LOPTx making fizzing noise Noise stopped when pin 2
LOPTx dis'd - IC7470 TDA2579A timebase chip faulty (internal s/c on
supply pin 10)
Philips G90AE Nicam -int Check joints on grey sm caps on NICAM pcb - will often req a quick solder round
Philips G90AE No Blue D6416 BAS32 u/s
Philips G90AE No chan store X2402 EEPROM
Philips G90AE No col (s/c pins 1 & 6 dec chip to overide col kill) Ref osc could not be locked by C2352; C2359 leaky
Philips G90AE No colour C2359 leaky.
Philips
G90AE No line osc Check pin 16 IC7470 TDA2579 for 9v - if low check
volts across D6455 5v6 zener - if low replace D6455 BZX55F5V6; if ok
replace Tr7455 BC858
Philips G90AE No OSD - no sound , blank raster. IC TMP47V434N-3555 IC7720
Philips
G90AE No pic at sw on - just lines across screen - ok when heated C2580
1000µ Philips G90AE NO PIC TEXT OK TDA3561A PIN 7 -ve NOT 3.4v C2560
33nF
Philips G90AE No picture, no sound Voltage +95 V present.
Replace IC 7470 (TDA 2579/N6; 4822 209 72363) and replace TS 7455 (BC
858A; 5322 130 42012)
Philips G90AE No picture, sound OK. Video
signal present on pin 19 SCART, video signal not present on pin 3 IC
7350. Replace TS 7881 (BC 848; 4822 130 61207)
Philips G90AE No picture, sound OK. Vertical signal not present on basis TS 7503. Replace TS 7471 (BC 848C; 5322 130 42136)
Philips
G90AE No picture, sound OK. Video signal present on pin 3 IC 7350.
RGB-Signal not present on pin 12, 14, 16 IC 7350. Replace IC 7350 (TDA
3561A/N8; 4822 209 71518)
Philips G90AE No red D6854 BAS32 sm diode s/c
Philips G90AE No sound Check sm diode near audio ic for dry joints
Philips G90AE No sound - blank raster , no OSD. IC TMP47C434N-3555 IC7720
Philips G90AE No sound with "F7" in display C2661 22µ in 5v reg cct
Philips G90AE No sound, picture OK Picture present, program selection functions. Replace IC 7220 (TDA 8191; 4822 209 60103)
Philips G90AE No sound, picture OK Picture present, audio signal present on pin 17 of IC 7220.
Replace BU 5 (4822 267 60188)
Philips G90AE No startup. D6653 leaky.
Philips G90AE No synchronization, pin 7-IC7470 low Check C2469 (22uF; 4822 124 20698) for short-circuit.
Philips
G90AE No text, front controls perform wrong task. i.e. brightness
varies when volume buttons are pressed. Check 5 volts to uP. If supply
voltage low eg. 3 volts instead of 5 volts, check/replace D6662 in Power
Supply Part. D6662 - 5.1 Volt zener diode (4822 130 80905) Philips
G90AE no tuning caused by the SDA3202-2 in the tuner If there is no
oscillation at the Xtal, change the IC , the same is true for the
CUC3400 Grundig
Philips G90AE No Txt & "F7" in display with sound possibly missing C2843 220µ
Philips
G90AE No vertical deflection No vertical control signal on pin 1 IC
7470 Replace IC 7470 (TDA 2579/N6; 4822 209 72363) Replace D 6465 (BAS
32L; 4822 130 80446)
Philips G90AE Oscillation wide in weak
field on the right side. It moves to the left and disappears after the
set has warmed. Check/replace transistor 7533 (BC636; 4822 130 44283) in
east-west circuit.
Philips G90AE Over-voltage circuit active
Disconnect connector A5 and connect a bulb to +95 Volt. Bulb burns.
Check/replace TS7545 (BUT11AF;4822 130 42679) and S5545 (line
transformer; 4822 1040 10306)
Philips G90AE Pic goes dark aft 2hrs & no chan change Display shows F4 IC7720 faulty
Philips
G90AE Picture becomes dark from time to time, cannot be adjusted
Transistor 7869 (PMBT2369; 4822 209 73852) base not soldered.
Philips G90AE Picture too dark Voltage on pin 7 S 5545 (line transformer) < 3,2V Replace C 2560 (33 nF; 4822 121 51385).
Philips G90AE Poor contrast range C2560 33nF leaky in beam current limiter cct
Philips G90AE Popping from spkrs only at sw on C2630/31 smoothing caps 47µ 250v
Philips
G90AE Power supply failure In the event of a failure in the switch-mode
power supply, the switching transistor IC7625 may have failed. In this
case it is recommended that the opto-coupler IC7614 should also be
replaced. 7625: BUT11AF; 4822 130 42679 7614: CNX83A; 4822 130 82034
Philips
G90AE Pulsing/rolling/jagged white line at top of screen IC7470 TDA2579
timebase chip Philips G90AE Ragged pic, dim display C2640 680µ 22v
smoother, C2580 470µ 12v smoother Philips G90AE Ragged verticals on some
pictures. C2630 ( 47uF ) HT reservoir con.
Philips G90AE Ragged verts C2630 47µ HT res cap leaky Philips G90AE REDUCED HEIGHT , TOP FOLDOVER R3508 24k HIGH
Philips G90AE Remote control inoperative - dark picture. Replace IC 7720.
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