The Thomson chassis ICC3 is a monocarrier type featuring all functions of the receiver except the frontend commands unit.
The metal box is containing the tuner VHF UHF unit plus the if stages and the PLL synthesizer section.
The power supply is derived from a mains transformer generating all supply.
Additional +B power supply is generated on the ICC3 chassis board via SMPS power step-up type with line synchronized signals.
Is the last chassis type followed by the ICC3000 using a separation mains transformer in "BIG" Style.
NORDMENDE COLOR 3537 CHASSIS F11 (THOMSON ICC3) Function description Power supply unit
Start-up function Power supply
After actuation of the line power switch the primary Power supply section with line transformer UP 41 supplies the operating voltages required for the controlled Power supply section. An L-level originating at the operating electronics and passing through RP 21 and RP 24 is applied to the base of TP 21. This switches through since the primary Power supply section sup- plies a positive voltage to the emitter through DP 21, DP 24 and DP O03. The collector voltage now switched through RP 27 serves as temporary Start-up operation voltage and is applied to pin 14 of IL 01, the line generator of which oscillates up- wards of 5,5 V. Driver transistor TL 01 is triggered with horizontal-frequency pulses Originating at pin 2 of IL 01 and passing through RL 19. The required collector voltage is supplied by the primary Power supply section through DP 13, which serves as a decoupling diode. The threshold voltages of the three diodes, DP 21, DP 24 and DP 03, insure that first the collector voltage of TL 01 is present and only then is the triggering signal applied. TL 02 receives via driver transformer UL 01 the base current required for its switching function. The collector voltage of TL 02 is supplied through fuses FP 02, LP 01 and DP 14 and the line transformer. The horizontal deflection starts and gene- rates in the secondary Power supply section the operational voltages which the receiver requires. These are initially, during the Start-up phase, too low and non stabilised until the controlled Power supply section begins to function.
Start-up function of the controlled Power supply section
CP 10 is charged through RP 25 and DP 12. If the voltage potential at the emitter of TP 05 achieves the base voltage, elevated by threshold value, the transistor switches through and charges CP 12 through RP 23. The time constant of the RC network causes a saw- tooth voltage to be generated.
From the line transformer positive horizontal pulses reach the base of TP 04 through RP O6. The transistor is blocked during the negative line sweep phase and is conductive during the fly back phase. As a result a line-frequency saw tooth is present at the collector of TP 04 as A triggering signal for TPO6.CP 12is discharged by TP 04 during the horizontal fly- back phase. When threshold voltage is reached, TP 06 and TP O02 switch through, whereby TP 01 also becomes conductive, allowing a saw- tooth current to flow to ground through RP 03. With this current the LP 01 charging coil collects magnetic energy. From terminal 11 of the line transformer the negative line fly back pulse is supplied through DP 43, DP 42 and RP 05 to the basis of TP 01, which blocks. As the magnetic field of LP 01 collapses it generates an elevated voltage which makes DP 14 conductive and charges CP 14. The voltage adjustable at PP O01 serves as a reference for the control of the energy requirements in the receiver. DP 10, RP 08 and CP 23 damp the voltage peaks created when TP 01 switches out. Control circuit Operation voltage +1 is supplied to the base of TP O05 through voltage splitter RP 11,PP01 and RP 09. When in a steady state 6,2 V are available at the emitter of the transistor, which — stabilised by +2a — are drained through decoupling diodes DP 15, TP 21 and RP 25. TP O5is also to be seen as the current source for the RC network, RP 23 and CP 12, which generates the saw tooth. Depending on the internal resistance of TPO5, the steepness of the saw-tooth voltage at TP 06 is low- ered or elevated. The switching point of the transistor can thus be advanced or retarded. Under the influence of TP 02, TP 01 will be- come conductive during the line sweep either earlier or later, depending on the energy requirements. Thus the strength of the magnetic fleld in LP 01 is controlled.
Example:
As the receiver's power requirements in- crease, operational voltage +1 drops slight- ly. As a result the base voltage at TPO5 is also reduced. The impedance drops, causing faster charging of CP 12, Due to the steeper saw tooth voltage, TP 06, TP 02 and TP 01 be- come conductive earlier. The charging coil can collect more energy and, once TP O01 has switched off, discharge the energy through feed diode DP 14 to charging condenser CP 14. Voltage again rises to its rescribed value,
Protective circuits in the controlled Power supply section
1. If due to fauity adjustment of PP 01, for example, or in case operational voltage +1 becomes in admissible high due to a failure in the vertical section, secondary operating voltage +3, 23,5 V, also rises. The zener voltage of DP 18 is exceeded TP 18 becomes conductive and TP 21 blocks. Thus the horizontal deflection and the controlled Power supply section are taken out of service. After voltage +3 has dropped and CP 21 has discharged through RP 21, TP 21 switches through, putting the horizontal deflection and the controlled Power supply section back into service. The switching cycle is determined by the time constants of RC network RP 21, CP 21.
2. If the power drawn by the set rises to an unacceptable level, TP 01 is overloaded. At RP 03 a voltage drop ts effected which corresponds to the current through TP0O1, and this drop switches transistor TP 04 via OP 17 and RP O04. TP O1-is- thus: also blocked by TP 06 and TP O2, and as a result protected against excessive power requirements.
NORDMENDE COLOR 3537 CHASSIS F11 (THOMSON ICC3) Switching regulator power supply device combined with the horizontal
deflection circuit of a television receiver which it supplies
Step-up switching regulator power supply device comprising, connected
between the poles of a rectifier circuit supplied by an isolating
voltage step-down transformer and loaded by a first filter capacitor,
and inductance and the collector-emitter path of a first switching
transistor of NPN type, a first diode whose anode is connected to the
junction of the inductance and to the collector of said transistor and
whose cathode is connected to a second filter and storage capacitor
supplying a voltage at its output which supplies a horizontal deflection
circuit of a television receiver.
This horizontal deflection circuit which comprises in cascade a
horizontal oscillator, a driver stage and an output stage, forms an
integral part of the circuit controlling said first transistor and
determines the repetition period of the switching, because it is started
under an initial voltage slightly less than the unregulated input
voltage of the device.
The switching transistor is being turned off in synchronism with the
turning off of the trace switch transistor by using flyback pulses of
negative polarity to bias the base thereof.
1. A power supply device with switching regulation and boosting of its
DC output voltage, combined with a horizontal deflection circuit of a
television receiver, supplied thereby and which comprises in cascade a
horizontal oscillator, a driver stage and an output stage including a
trace switch transistor and a line transformer, this device comprising
an inductance and the collector-emitter path of a switching transistor
connected in series between the poles of a DC input voltage source, a
rectifying diode connected by its anode to the junction between the
inductance and the collector of said switching transistor and by its
cathode to one of the terminals of a filtering and storage capacitor
whose other terminal is connected to the emitter of said transistor, so
as to apply across its terminals an initial DC voltage slightly lower
than said input voltage, when said switching transistor is turned off,
and a regulated DC output voltage with a level higher than said input
voltage, when said transistor is recurrently, alternately turned on and
off, the level of said output voltage depending on the duty cycle of
said switching transistor states, and a control circuit feeding the base
of said switching transistor and including a regulator stage comparing
an adjustable fraction of said output voltage to a fixed reference
voltage and supplying a regulating current or voltage proportional to
the difference between said compared voltages, a pulse-width modulator
triggered by means of a recurrent signal and supplying a rectangular
signal whose duty cycle varies as a function of said regulating current
or voltage, another driver stage receiving the rectangular signal and
controlling said switching transistor, the regulation and boosting of
said output voltage being controlled by the initially independent
starting up of the entire horizontal deflection circuit when supplied by
said initial voltage from said power supply device as soon as a DC
input voltage is applied thereto and which then delivers recurrent
trigger pulses to said pulse-width modulator, one of the supply inputs
of said other driver stage receiving directly a first voltage waveform
whose positive alternations comprise constant-voltage plateau and whose
negative alternations comprise negative-going horizontal flyback pulses
provided by a first secondary winding of said line transformer, so as to
control the turning off of said switching transistor substantially
simultaneously with that of the trace switch transistor.
2. A power supply device as claimed in claim 1, wherein said other
driver circuit comprises a third transistor whose emitter is connected
to the base of said switching transistor and which is of the same type
as the latter, whose collector is connected, through said supply input,
to said first secondary winding of said line transformer to receive
therefrom said first waveform and whose base is coupled to the output of
said pulse-width modulator.
3. A power supply device as claimed in claim 2, wherein the collector of
said third transistor is connected, through a resistor to the supply
input and its emitter is connected, furthermore, to that of the
switching transistor through another resistor so that the negative-going
flyback pulses, applied to the collector of said third transistor,
control the symmetric (reverse) saturation thereof so as to reversely
bias the base-emitter junction of said switching transistor.
4. A power supply device as claimed in claim 2, wherein the collector of
said third transistor is connected to said power supply input through a
fourth diode conducting in the normal direction of its
collector-emitter path, and wherein its emitter is further connected, on
the one hand, through a resistor, to the emitter of the switching
transistor and, on the other hand, through another resistor and a fifth
diode conducting in the reverse direction to that of the base-emitter
junction of the switching transistor, so as to transmit to the base
thereof negative-going flyback pulses through a voltage divider formed
by said two resistors in series.
5. A power supply device as claimed in claim 1, wherein said other
driver circuit comprises a third transistor whose emitter is connected
to the base of said switching transistor, whose collector is connected
to that of this latter so as to form a so-called Darlington circuit and
whose base coupled, moreover, to said pulse-width modulator is further
connected, through a resistor and a diode in series, to said first
secondary winding of said line transformer so as to control the
simultaneous turn off of both transistors of said Darlington circuit by
simultaneously reversely biasing their respective base-emitter
junctions, connected in series, by means of negative-going flyback
pulses.
6. A power supply device as claimed in any one of the preceding claims,
wherein said pulse-width modulator, supplied at its input with a voltage
waveform whose positive alternations comprise positive-going flyback
pulses and whose negative alternations comprise constant
negative-voltage plateaux, comprises a passive circuit which forms a
simple integrator during positive alternations because one of its
resistors is shunted by a diode and which is a cascaded double
integrator during negative alternations of this waveform so as to
deliver during the trace periods of the scan a linearly decreasing
negative current which, added to the positive regulating current,
supplies the base of a fourth comparator transistor, so that the turning
off of this latter through equality of the negative and positive
currents supplied to this base controls the beginnings of the saturation
of said switching transistor in such a manner that the duration of this
saturation varies inversely with variation of said output voltage.
7. A power supply device as claimed in claim 6, wherein said comparator
transistor is biased, furthermore, at its base by means of a resistor
which connects it to the positive pole of said input voltage source, so
that it remains saturated in the absence of flyback pulses supplied by
said horizontal deflection circuit so as to maintain the switching
transistor in a cut off state.
8. A power supply device as claimed in any one of the preceding claims,
wherein said control circuit, except for the regulator stage which is
supplied by said output voltage, is supplied by said input voltage.
9. A power supply device as claimed in any one of the preceding claims 1
to 6, wherein said DC supply voltage of said control circuit, with the
exception of one of the inputs of said regulator stage receiving said
output voltage, is supplied by a secondary winding of said line
transformer, through a rectifier circuit including a diode and a
filtering capacitor.
Description:
The present invention relates to a switching voltage regulator power supply dev
ice
combined with the horizontal deflection circuit of a television
receiver which it supplies with DC voltage. It relates, more
particularly, to DC voltage supply devices of the type which boost or
increase the voltage supplied at the output of the device in relation to
the level of a DC voltage applied to its input and which regulate this
level by recurrent switching of this input voltage, this switching being
synchronous with the (horizontal) line frequency of the television
receiver supplied by this device. 
Switched step-up or boost voltage regulator devices of this type are known, particularly from the publications U.S. Pat. Nos. 3,571,697 (or 3,736,496) and they are related to switched mode power supply devices or DC-DC converters of the so-called unisolated flyback type, in which the collector-emitter path of a bipolar switching transistor is connected in series with a commutating inductance between the terminals of a DC source supplying an input voltage and a rectifying diode is connected between the junction of the inductance with the transistor and one of the plates of a filtering or storage capacitor (in parallel with the load), so that the current stored in the inductance during the conducting period of the transistor is used for charging the capacitor (and supplying the load) through the diode during its consecutive cut-off period. The use of a switched-mode power supply device of this type in television receivers for supplying, particularly, the horizontal deflection circuit thereof has been described, for example, in two articles by VAN SCHAIK entitled respectively "AN INTRODUCTION TO SWITCHED-MODE POWER SUPPLIES IN TV RECEIVERS" and "CONTROL CIRCUITS FOR SMPS IN TV RECEIVERS," appearing respectively on pages 93 to 108 of No. 3, Vol. 34, of September 1976 and on pages 162 to 180 of No. 4 of this same volume, of December 1976, in the English language Dutch review "ELECTRONIC APPLICATIONS BULLETIN" of PHILIPS', or on pages 181 to 195 of No. 135 of July 1977 and on pages 210 to 226 of No. 136 of October 1977 of the British review "MULLARD TECHNICAL COMMUNICATIONS." Since none of the switched-mode power supply devices described in these articles, isolated or not from the mains, whether they use a forward or a flyback converter, supplies at its output a DC voltage for supplying the horizontal deflection circuit before the switching transistor has been turned on (saturated or conducting) one or more times, the control circuit of this transistor must comprise an independent relaxation oscillator and must be supplied by the same DC input voltage (rectified and smoothed voltage of the AC mains) as the switching circuit comprising the inductance and the transistor in series. Synchronization of the switching with the horizontal deflection can only occur subsequently, when the horizontal oscillator and/or the horizontal deflection circuit as a whole have begun to operate, as soon as the supply voltage supplied thereto by the device which operates independently on starting up, has become sufficient. This synchronization of the switching with the horizontal deflection, advantageous for reducing or eliminating the interferences visible on the screen which are caused by high-frequency energy radiation due to abrupt transitions of power switching, particularly when the switching transistor is being cutt off, is generally carried out by means of a signal comprising flyback or retrace pulses, taken at the terminals of an auxiliary secondary winding of the line tranformer whose primary winding is generally connected between the output of the switched-mode power supply device and one of the terminals of the trace switch which is provided in the output stage. It is also possible to use for this purpose the signal provided by the horizontal oscillator (see, for example, the publication FR-A-2 040 217).
In a switched-mode supply for a television receiver described in the publication FR-A-2 261 670, the circuit for controlling the switching transistor of a forward-type converter, supplied with the rectified and smoothed voltage of the mains, comprises a bistable trigger circuit of flip-flop one of whose outputs is coupled back to one of its trigger inputs through a regulating circuit comprising a sawtooth voltage generator and a voltage comparator providing transitions which control the setting of the flip-flop, when the sawtooth voltage reaches the level of a voltage proportional to the amplitude of the flyback pulse. The other one of the two complementary outputs of this flip-flop is coupled back to its other trigger input through a so-called starting loop comprising an ascending voltage wave-form which approaches asymptotically a predetermined voltage level smaller than a predetermined fraction of the nominal level which the amplitude of the flyback pulse must reach in normal operation, and a voltage comparator providing transitions which control the recurrent resetting of the flip-flop to its initial state until the flyback pulse has reached or exceeded a threshold amplitude slightly below its nominal amplitude. When this threshold amplitude has been exceeded, resetting of the flip-flop is controlled by the flyback pulses themselves, negative-going in the present case, which supplant the starting pulses. Such an arrangement is equivalent to an astable multivibrator during the starting period, which later becomes a monostable one and triggered by the flyback pulses and whose quasi-stable state has a variable duration, depending on the amplitude of these pulses so as to obtain regulation thereof by the duty cycle. The pulse which controls the closing of the switch (saturation of the switching transistor) begins here with the leading edge of the flyback pulse and its duration or length is modulated as a function of the current drawn by the load and of the variation of the rectified and smoothed voltage, so that its end controlling the opening of the supply switch
(cutting off the transistor) occurs during the trace portion of the
horizontal deflection. Thus it can be seen that this switched-mode
supply, like most of the known ones, effects regulation of its output
voltage by varying the duty cycle as a reverse function of the level
thereof. Since the high-frequency radiation is precisely at its most intense during abrupt transitions of current in the switching inductance and of the voltage accross its terminals, the appearance of one or more vertical lines (light or dark according to the sense of the modulation of the carrier wave by the video signal) may be observed, contrasting with the normal contents of the picture, whose location on the screen depends on the duration of the pulse controlling the switching transistor. The effect of this radiation becomes particularly troublesome when the input signal of the radio-frequency stages or tuner is small, particularly when the selected channel is situated in the lower part of the VHF band, for the automatic gain-control device of the receiver acts on the gain of the high-frequency and/or intermediate-frequency input stages, so that the sensitivity (amplification) of the receiver is then maximum and this also as concerns the spurious radiated signals.
The present invention, on the one hand, avoids or at least appreciably reduces the interferences visible on the screen by controlling the cutting off of the switching transistor in synchronism with the leading edge or the flyback pulse and, on the other hand, the starting of the horizontal deflection circuit by means of a simple circuit without any special oscillator, and provides efficient protection of the switching transistor which remains cut off when the horizontal deflection circuit is not operating. This is made possible by using a step-up switching regulator supply device of the type described in the publication U.S. Pat. No. 3,571,697 and whose control circuit includes, in accordance with the invention, the horizontal deflection circuit, which it supplies.
The object of the present invention is a power supply device with boosting and regulation of its output voltage by switching, combined with a horizontal sweep circuit of a television receiver, which it supplies and which comprises a horizontal oscillator, a driver stage and an output stage including a line transformer, this device comprising an inductance and the collector-emitter path of a switching transistor connected in series between the poles of a DC input voltage source, a rectifiying diode connected by its anode to the junction between the inductance and the collector of the transistor and by its cathode to one of the terminals of a filtering capacitor whose other terminal is connected to the emitter of the transistor so as to supply between its terminals an initial output voltage, slightly lower than the input voltage, when the transistor is cut off permanently, and a regulated DC output voltage with a level higher than the input voltage, when the transistor is recurrently alternately turned on and off, the level of this output voltage depending on the duty cycle of the respective states of this transistor, and a control circuit for driving the base of the transistor and including a regulator stage comparing an adjustable fraction of the output voltage to a fixed reference voltage and supplying a regulating current or voltage proportional to the difference between these compared voltages, to a pulse-width modulator triggered by means a recurrent signal and supplying a rectangular signal whose duty cycle varies as a function of this regulating current or voltage, and another driver stage receiving the rectangular signal and controlling the switching transistor.
In accordance with the invention, the horizontal deflection forming an integral part of the circuit controlling the switching transistor, determines therefor, from the start, the repetition period of the rectangular signal controlling it, and one of the supply inputs of the other driver stage receives directly a first voltage waveform whose positive alternations, comprise DC voltage plateaux
and
whose negative alternations comprise negative-going flyback pulses
supplied by a first secondary winding of the line transformer, so as to
control the cut-off the switching transistor substantially
simultaneously with that of the trace switch transistor. The invention will be better understood and other of its objects, characteristics, features and advantages will become clear from the following description and the accompanying drawings which refer thereto, given solely by way of example, in which:
FIG. 1 is partly a block diagram and partly a schematic diagram of a power supply device combined with the horizontal deflection circuit in accordance with the invention;
FIG. 2 shows waveforms of two voltages and of a current at different points of the circuit of FIG. 1;
FIG. 3 is a block diagram of the circuit for controlling the switching transistor;
FIGS. 4 and 5 are schematic diagrams of two different embodiments of the driver circuit 20 forming the output stage of the control circuit of FIG. 3;
FIG. 6 is the block diagram of one embodiment of the pulse-width modulator 10 of the circuit of FIG. 3;
FIG. 7 shows three voltage waveforms at different points of the circuit of FIG. 6;
FIG. 8 is a schematic diagram of one embodiment of the pulse-width modulator 10 of the circuit of FIG. 3, using discrete components;
FIG. 9 shows a current waveform and two voltage waveforms at different points of the circuit of FIG. 8;
FIG. 10 is a schematic diagram of a conventional embodiment of a regulator stage 30 adapted to supply the modulation input of the modulator of FIG. 8; and
FIGS. 11 and 12 are partial respective schematic diagrams of two embodiments of a power supply device in accordance with the invention.
FIG.
1 shows the schematic diagram of the power stages of the power supply
device and of the horizontal deflection circuit of the television
receiver, which it supplies and in block diagram form the respective
circuits which control them. The DC input voltage VE which is not regulated is supplied by a rectifier bridge R with four diodes, supplied at its input by the secondary winding of an insulating step-down transformer TS, whose primary winding is supplied by the AC mains. The output terminals of rectifier bridge R are connected respectively to the terminals of a first filtering capacitor C1 across which this input voltage VE is taken.
The positive pole P of this source of the input voltage VE is connected to one of the terminals of an energy-storage inductance L, whereas its negative pole N is connected to ground G of the receiver, which is isolated from the mains. The other terminal of inductance L is connected, on the one hand, to the collector of a first NPN bipolar switching transistor T1, whose emitter is connected to ground G and, on the other hand, to the anode of a first diode D1 whose cathode is connected to the positive terminal of a second filtering and storage capacitor C2. With the negative terminal of this second capacitor C2 connected to ground G, the output voltage VS which supplies the load is taken between its terminals.
Such a supply device BS provides both step-up or boost and regulation of its output voltage level, because the first switching transistor T1 and the first diode D1 thereof are connected so as to conduct respectively currents flowing through inductance L in the same direction, it supplies at its output formed by the terminals of the second capacitor C2, an initial DC voltage VSI as soon as the primary winding of the insulating transformer TS is connected to the mains. This initial voltage VSI which is equal to the input voltage VE less the forward voltage drop VD1 across the first diode D1, is then supplied to the load until the control circuit SC is started up, whose output 6 is connected to the base of the first transistor T1 so as to cause it to be alternately turned on and off.
When the first transistor T1 is turned on by positively biasing its base-emitter junction, its collector-emitter path connects the junction of the inductance L with the anode of the first diode D1 to ground G. Diode D1 being then reversely biased, it ceases to conduct and the inductance L connected by the first transistor T1 between the positive P and negative N poles of the source supplying the unregulated DC input voltage VE, then conducts a linearly increasing current IL so as to store the energy which increases with the square of the conduction duration of the first transistor T1, until this latter is cut off. At the instant when the first transistor T1 is cut off after the control circuit SC has brought its base-emitter voltage to zero or below, the voltage at the terminals of inductance L is reversed so that, at its junction with the collector of transistor T1 and the anode of diode D1, there appears a voltage VM greater than the input voltage VE, which results in the forward biasing of diode D1. Consequently, from the instant when transistor T1 is cut off, diode D1 conducts a linearly decreasing current until the energy stored in the form of a current IL in the inductance L, which charges the second capacitor C2 to an output voltage VS greater than the input voltage VE, disappears. The regulation of the level of the output voltage VS is here effected in a conventional way, by varying the duty cycle, i.e. the radio (quotient) between the duration of the conducting period of transistor T1 and the sum of the respective durations of two of its successive conducting and cut off periods, as a function of the desired output voltage VS (determined by comparison to a stable reference voltage).
According to the invention, a supply device BS of the above-described type is combined with the horizontal deflection circuit SH of a television receiver, which it supplies, so that this latter forms an integral part of its control circuit SC and for determining the repetition period of its operation and so that the above-mentioned regulation by varying the duty cycle maintains a stable peak-to-peak amplitude of the sawtooth scanning current and/or the very high voltage for biasing the electrodes (anode, focusing electrode and accelerating grid) of the cathode-ray tube, which are obtained by rectifying the horizontal flyback pulses supplied by a step-up secondary winding (not shown) of the line transformer TL.
The horizontal deflection circuit SH which comprises in cascade the horizontal oscillator OH whose known phase control circuit with respect to the horizontal sync signal separated from the composite video signal has not been shown here, the driver stage HD controlled by the horizontal oscillator OH and controlling the output stage OS of the horizontal deflection, is as a whole supplied by the above-described regulated power supply device BS. In fact, the positive supply input AL of the horizontal deflection circuit SH is connected by means of a fuse FS to the junction of the cathode of the first diode D1 with the positive terminal of the second capacitor C2, which forms the positive output terminal SP of the regulated power supply device BS. This supply input AL is connected directly to that of the driver circuit HD and, preferably, through a conventional Zener diode or series ballast transistor voltage regulator VR, to that of the horizontal oscillator OH, which are moreover connected to the isolated ground G.
The supply input AL of the horizontal deflection circuit SH is furthermore connected to one of the primary winding terminals B1 of the line transformer TL, whose other terminal AB is connected in parallel to the collector of another switching transistor TH, of NPN type, called trace switch transistor, to the cathode of a second so-called shun
t
recovery diode DR, to one of the terminals of another capacitor CR,
called line-retrace capacitor, and to one of the plates of an additional
capacitor CS, called trace capacitor, which supplies the horizontal
deflection coils LH one terminal of which is connected to its other
terminal during the trace periods of the scanning. The emitter of the
scanning transistor TH, the anode of the "shunt" recovery diode DR, the
other terminal of the retrace capacitor CR and the other terminal of the
horizontal deflection coils LH are all connected to ground G. This
assembly of components thus connected forms the output stage OS whose
operation is well-known and does not form part of the invention. As was mentioned above, as soon as the primary winding of the step-down isolating transformer TS is connected to the mains, rectifier R supplies the first filtering capacitor C1 so as to provide between its terminals P and N a unregulated low DC voltage VE. With the first transistor T1 then turned off, this input voltage is applied through the inductance L and the first diode D1 to the second capacitor C2 so as to obtain between the terminal SP and ground G an initial output voltage VSI substantially equal to VE-VD1, which is approximately equal to 60 percent of the regulated output voltage VS. This initial output voltage VSI (equal to about 0.6 VS) is sufficient to cause the generation of autonomous oscillations by the horizontal oscillator OH. This latter supplies at its output, connected to the input of driver circuit HD, pulses at an independent frequency close to the line frequency. In response to these pulses, driver circuit HD, also supplied by device BS, provides at the base of the trace switch transistor TH pulses controlling its periodical cut off at this independent frequency and its consecutive turning on after a period greater than the duration of the flyback period, so that the recovery diode DR may take the current from the deflector LH during substantially the first half of the trace portion of the scan. During flyback or retrace, with both transistor TH and diode DR cut off, the energy stored in the form of currents respectively in the inductances of deflector LH and of the primary winding B1 of the line transformer TL which are then, from the AC current point of view, connected in parallel, flow in an oscillating manner through the retrace capacitor CR which forms therewith a parallel resonant circuit whose resonance period determines the duration of the flyback period.
There then appears periodically between point AB and ground G a voltage pulse VTH having substantially a sinusoidal half-wave form, which is shown in Diagram A of FIG. 2. The average value of this voltage VTH being then equal to VSI, at start-up, and to VS, during established operation. The line transformer TL comprises, in addition to a very-high-voltage winding and other windings for supplying rectifying circuits, not shown, two secondary windings B2, B3 respectively supplying across their terminals, voltage waveforms comprising flyback pulses with zero average values and with respectively negative and positive polarities.
This means that the first secondary winding B2 supplies a voltage waveform -VTL which, between two successive flyback pulses, comprises a positive plateau whose level is equal to the average value of these pulses and which is used, in accordance with the invention, to control the turn off of the first transistor T1 so that the interferences which would otherwise be visible only occur during the line-blanking periods comprising the line-retrace periods. The second secondary winding B3 then supplies a voltage waveform +VTL which is the reverse of or complementary to the preceding one -VTL.
O
ne
of the terminals of each of these secondary windings B2, B3 is
connected to ground G, whereas their other terminals are respectively
connected to two inputs 2 and 1 of the control circuit SC. A third input
3 of this latter is connected to the SP output of the supply device BS
and a fourth input 4 is connected to the positive pole P of the input
voltage source VE. A fifth terminal 5 of the control circuit SC is
connected to ground G (or negative pole N) and its output 6 is connected
to the base of the first transistor T1. This control circuit SC causes,
following the start up of the horizontal deflection circuit SH, a first
saturation of the first transistor T1 at a time determined by a
pulse-width modulator operating by conventional comparison of a sawtooth
voltage waveform the elaboration of which is controlled by a first
flyback pulse, with a regulating voltage, depending on the output
voltage VS. During this saturation period of transistor T1 which extends
as far as the leading edge of the next flyback pulse, energy is stored
in inductance L. 
From the instant when transistor T1 is turned off, diode D1 transfers this stored energy to the second capacitor C2, at the terminals of which it causes an increase of the voltage VS with respect to its initial value VSI, until the current in diode D1 is canceled out, when it becomes reverse biased.
The collector-emitter voltage waveforms VTH of the trace switch transistor TH and VCE of the switching transistor T1 in established operation have been shown respectively by the diagrams A and B of FIG. 2. Diagram C of FIG. 2 shows the corresponding waveform of the current IL flowing through the inductance L.
When the base of the first transistor T1 receives from the output 6 of the control circuit SC a rectangular signal which turns it on at time instant t1, its collector-emitter voltage VCE (Diagram B) becomes close to zero (V CEsat ) and a linearly increasing current IL (Diagram C) flows through inductance L from time t1 until time t2 when transistor T1 is again turned off, which is controlled by the leading edge of the flyback pulse VTH (Diagram A). With the collector current of transistor T1 canceled at the end of the storage time of the excess minority carriers in the base, the voltage across the terminals of the inductance L inverses its polarity so as to be added to the input voltage VE, so that the collector-emitter voltage VCE (Diagram B) then reaches a level VM greater than VS (as well as VE), so as to apply forward bias to the first diode D1, which then conducts the current IL through the inductance L. This current IL, from time instant t2 when it reaches its maximum value IM, becomes linearly decreasing and it flows through the first diode D1 in the passing direction in order to recharge the second capacitor C2 and supply, in particular, the horizontal deflection circuit SH.
When the current IL passing through the first diode D1 is canceled out at time t3, the collector-emitter voltage VCE of the first transistor T1 becomes equal to the unregulated input voltage VE until the next turn on of the transistor T1, and the first diode D1 remains reversely biased until the time when this latter is cut off again.
From the above it can be easily seen that the principal advantage of this combined device resides in the fact that a single oscillator OH belonging to the horizontal deflection circuit SH is sufficient for controlling the two power switching transistors TH and T1.
Furthermore, a possible overload in the circuitry of the television receiver, such for example as a short-circuit of the trace switch transistor TH, results in overloading the diode D and the inductance L. The first transistor T1 which is consequently cut off is not subjected to this overload and is therefore protected. In order to protect the rest of the television receiver as well as inductance L and the first diode D1, a fuse FS may be connected in series in the supply line from the second capacitor C2. This fuse FS may also be inserted between pole P and inductance L.
It is moreover known that it is difficult to construct switched supplies for obtaining correct operation when it is not fully charged (for supplying, for example, a ready-state remote-control receiver). In the present case, the problem does not come up since, when the supply is in operation, there is always a minimum load formed by the horizontal deflection circuit. When this circuit is not operating, the supply circuit BS does not operate either, but it supplies an output voltage VSI of a value less than the nominal voltage VS which cannot cause damage and which may, for example, supply a ready-state receiver for television receivers having a remote control.
Finally, the control circuit SC allows transistor T1 to be cut off at the beginning of each flyback period, when the blanking circuit has extinguished the spot (s) on the cathode-ray tube. Thus, the spurious signals radiated into the receiver input circuits will cause no visible effect on the screen of the cathode-ray tube.
FIG. 3 shows in block diagram form the control circuit SC of FIG. 1. This control circuit SC comprises a pulse-width modulator stage 10 a first input 11 of which, connected to input 1, receives flyback pulses of positive polarity +VTL from the second secondary winding B3 of the line transformer TL (see FIG. 1 and a second input 12 of which receives a so-called regulating voltage or current whose level is proportional to the difference between the actual output voltage VS and a constant reference value, delivered by the output 32 of a regulating circuit or stage 30 whose input 31 is connected through input 3 to the positive output pole SP of the supply device BS supplying the regulated voltage VS. The variation of the regulating current or voltage causes the variation of the time instant when the instantaneous amplitude of a sawtooth voltage waveform, either with substantially constant slope and amplitude, reaches the level of this regulating voltage, or with a slope variable depending of the regulating current (which is added to the current for linearly charging a capacitor), reaches the predetermined level of a fixed reference (threshold) voltage, with respect to the beginning or the end of the sawtooth waveform. Thus a two-level rectangular signal with constant periodicity is generated, whose duty cycle varies as a function of the regulating current or voltage. If it is arranged, which is possible, for a reduction of the output voltage VS with respect to its nominal value defined by the reference voltage, to cause an increase in the duty cycle and for an increase in VS to have the opposite effect, regulation of this output voltage VS is provided, which tends to be stabilized to this nominal value.
The output 14 of modulator 10 supplies a first input 21 of the driver stage 20 of the first switching transistor T1, a second input 22 of which receives the flyback pulses of negative polarity -VTL, coming from the first secondary winding B2 of the line transformer TL.
FIGS. 4 and 5 illustrate two different embodiments of the driver stage 20 of FIG. 3, providing efficient turn off of the first transistor T1.
In FIG. 4, the driver stage 20A comprises a third supply input 23 which connected to the positive pole (P) of the source of the (unregulated) input voltage VE and to one of the terminals of a first resistor R1 (1.8 kiloohms) whose other terminal is connected in parallel to the anodes of two diodes D2 and D3 (of type 1N4148). The second of these diodes D3 has its cathode connected to the base of a third NPN transistor T2 and to one of the terminals of a second resistor R2 (220 ohms). The emitter of the third transistor T2 is connected to the other terminal of the second resistor R2 and to the o
utput
24 of stage 20A, which is connected through the output 6 of the control
circuit SC to the base of the first transistor T1. The collector of the
second transistor T2 is connected through a third resistor R3 (10 ohms)
to the second input 22 of stage 20A receiving the signal -VTL which
comprises the negative-going flyback pulses and, between them, plateaux
of a constant positive level (zero average value). The base of the first
transistor T1 is coupled to its emitter and to ground G, through a
fourth resistor R4 (100 ohms). The third transistor T2 is thus mounted
as a common collector (emitter-follower) stage. When the output 14 of modulator 10 (FIG. 3) which is connected to the input 21 of stage 20A supplies a low state (level), i.e. a voltage close to zero, the thus positively biased diode D2 becomes conducting so that its anode will be at a voltage of a few tenths of a volt (0.7+V CEsat ) which is less than the voltage required for making the three series PN junctions orientated in the same direction conductive, the first of which is formed by the third diode D3, the second is the base-emitter junction of a third transistor T2 and the third that of the first transistor T1, which will thus remain turned off. When, on the other hand, output 14 supplies a high state or forms an open circuit (the output stage of modulator 10 being formed by an open-collector transistor), diode D2 is cut off by its reverse bias and the voltage VE applied to the input 23 causes a current to flow through the first resistor R1, the diode D3 and the respective base-emitter junctions of transistors T2 and T1 connected in series. Under these circumstances and if, at the same time, the voltage waveform -VTL applied to the collector of transistor T3 presents its constant positive level portion, coinciding with the trace periods of the horizontal scan, transistors T2 and T1 become simultaneously saturated with the effect previously described insofar as the supply device BS of FIG. 1 is concerned. On the other hand, when the voltage waveform -VTL applied to the collector of the third transistor T2 becomes negative, during flyback periods, the current then flows between terminals 23 and 22 of driver stage 20 A, through resistor R1, diode D3, the base-collector junction of the third transistor T2 and resistor R3. The third transistor T2 then operates along its symmetrical saturation characteristics, i.e. it is inverted so that its collector becomes emitter and vice versa. It then conducts a current in the reverse direction between ground and the input 22 (negative) through the resistor R4 across the terminals of which it causes, after removal of the excess minority carriers from the base of the first transistor T1 through the third transistor T2, a voltage drop biasing said base negatively with respect to the emitter. This negative voltage applied to the base of reversely saturated transistor T3 allows a considerable reduction in the storage time and a rapid turnoff of the first transistor T1. Since the sawtooth generator of the pulse-widt
h
modulator 10 described above is controlled by positive-going flyback
pulses, the rectangular signal applied by its output 14 (FIG. 14) to
input 21 of stage 20A undergoes, during the flyback period following the
turn off of the first transistor T1, a transition from its high state
to its low state which causes diode D2 to conduct and, consequently, the
third transistor T2 (reversed) to be cut off before the waveform -VTL
becomes positive again and rebiases this transistor T2 the right way
round. FIG. 5 shows the schematic diagram of another embodiment of the driver circuit 20 of FIG. 3, designated by 20B, which has only been modified with respect to circuit 20A of FIG. 4 insofar as the collector circuit of the third transistor T2 and the base circuit of the first transistor T1 are concerned.
This modification is more particularly intented for the case where the negative peak amplitude of the voltage waveform -VTL applied to the base of the first transistor T1 through resistor R3 and the emitter-collector path of the reversely saturated third transistor T2, exceeds the reverse (Zener) avalanche-effect breakdown voltage of one of the base-emitter or base-collector junctions of the first transistor T1. This may occur when the first secondary winding B2 of the line transformer TL is also used for other functions in the television receiver.
To prevent the third transistor T2 from being reversely saturated (symmetrically), the circuit 20B comprises a fourth diode D4 inserted between the input 22 receiving the voltage waveform -VTL and the collector thereof, in series with the resistor R3 and connected to conduct in the same direction as its collector-emitter path. The input 22 is more over connected to the cathode of a fifth diode D5 (1N4148) whose anode is connected through a circuit formed by a fifth resistor R5 (330 ohms) and a third capacitor C3 (1nF) connected in parallel, to the base of the first transistor T1.
Diode D5 isolates the base of transistor T1 from the input 22, when the waveform -VTL is positive, and connects them together through a resistive voltage divider formed by resistors R5 and R4 in series, when it becomes negative. Capacitor C3 accelerates the turn-off by favoring the transmission to the base of T1 of abrupt transitions of the negative flybacd pulses.
FIG.
6 is a diagram, partly in block form, of a possible embodiment of the
pulse-width modulator 10 of the control circuit SC of FIG. 3. Diagrams
D, E and F of FIG. 7 show the voltage waveforms applied respectively to
the input 11 (+VTL) and supplied by the output SI (VI) of the sawtooth
generator GD and by the output 14 (VP) of circuit 10A. Modulator 10A of FIG. 5 comprises a sawtooth generator GD formed by a conventional integrator circuit comprising a first amplifier A1 (integrated operational amplifier, for example), an integrating resistor R1 inserted in series between the input 11 receiving the voltage waveform +VTL illustrated by Diagram D of FIG. 7 and supplied by the second secondary winding B3 of the line transformer TL, and the input (inverting) of amplifier A1, as well as an interating capacitor CI connected between this input and the output SI of amplifier A1 (capacitive feedback). In response to this waveform +VTL, the output of amplifier A1 forming the output SI of sawtooth generator GD, supplies a voltage waveform VI illustrated by the diagram E of FIG. 7 which comprises, during the period between time instants t0 and t2 corresponding to the trace period TA of the scan, a voltage decreasing linearly between a maximum value (positive) and a minimum value (negative), and during the flyback intervals preceding time instant t0 and succeding to time instant t2, an increasing voltage of substantially semi-cosinusoidal shape.
Voltage VI is applied to one of the inputs (-) of an analog voltage comparator which may be formed by means of a second differential-type amplifier A2 (integrated operational amplifier), whose other input (+) connected to the input 12 of modulator 10A, receives the regulating voltage VR supplied by the regulator stage (30 of FIG. 3). This regulating voltage VR, which is obtained by com
paring
the output voltage VS of the supply device BS of the circuit of FIG. 1
with a reference voltage (VZ supplied by a Zener diode, for example), is
a DC voltage undergoing slow variations, shown in Diagram E of FIG. 7
by a dash-dot line. When the waveform VI applied to the inverting input (-) of comparator A2 is greater than the regulating voltage VR, which is the case during the period between time instants t0 and t1, its output connected to the output 14 of modulator 10A provides a low state. When, on the other hand, it (VI) reaches or becomes less than VR, which occurs from the time instant t1, the output 14 of modulator 10A provides a high state (which causes saturation of the first transistor T1). This high state continues until time instant t4 subsequent to the time instant t2 of the beginning of the following flyback pulse whose leading edge controls the turn-off of the first transistor T1, when the waveform VI becomes greater than the regulating voltage VR. Thus there is obtained at the output 14 of modulator 10A a rectangular signal VP shown in Diagram F of FIG. 7, formed successively of a low-level (zero or negative) beginning during the first half of the flyback period TR and ending at time instant t1, and a high level going from time instant t1 to time instant t4. Time instant t1 of the positive transition of signal VP, which determines the beginning of conduction of the first transistor T1 is then situated during the trace period of the scan TA and its position with respect to the beginning t0 or to the end t2 thereof varies as a function of the regulating voltage VR. When the regulating voltage VR is negative (as on the Diagram E of FIG. 7), a predetermined fraction of the output voltage VS is greater than the reference voltage, the duration of the high level state (t2-t1) is less than half of the trace period of the scan T1. In the opposite case, this duration (t2-t1) is greater than TA/2. The modification of this duration (t2-t1) and thus of the duty cycle is carried out in the reverse direction of the variation of the output voltage VS so as to stabilize it at a previously adjusted level, with respect to this reference voltage. The waveform -VTL may also be applied to the input 11 of modulator 10A. In this case, the input of comparator A2 must also be inverted.
To obtain suitable operating limits, while taking into consideration particularly the value of inductance L, the duty cycle or the durations (t2-t1) must vary between 0, the case where the input voltage VE is equal to the nominal output voltage VS, and about two-thirds, the case where the maximum power is supplied for a minimum voltage at the input.
The ratio between the residual alternating voltage (hum) at the output and the alternating voltage at the input must also allow an image to be obtained which is not perturbed for the eye. A value less than or equal to a hundredth for this ratio gives satisfactory results.
FIG.
8 shows the simplified diagram of a practical embodiment (by means of
discrete components) of the pulse-width modulator 10 of FIG. 3.
Different waveforms of a current I1 and input +VTL and output VP
voltages are respectively illustrated by the Diagrams H, J and K of FIG.
9. The input 11 of modulator 10B of FIG. 3 receives the voltage waveform +VTL which may be suppled either directly by the second secondary winding B3 of line transformer TL, or through a coupling capacitor whose one terminal is connected to the collector of the trace switch transistor TH (see FIG. 1). This input 11 supplies a passive shaping circuit, supplying negative-going (decreasing) sawtooth waveforms during the trace periods of scan T1. This passive circuit comprises a fourth coupling capacitor C4 (0.1μ) one terminal of which is connected to the input 11 and the other of which is connected to one of the terminals of a sixth resistor R6 (10 Kohms). The other terminal of this resistor R6 is connected to one of the terminals of a seventh resistor R7 (5.6 Kohms), to one of the terminals of a fifth capacitor C5 (5.6 nF) and to the anode of a sixth diode D6. The other terminal of capacitor C5 is connected to ground G. The cathode of the sixth diode D6 and the other terminal of resistor R7 are both connected to one of the terminals of an eighth resistor R8 (33 kohms), to that of a ninth resistor R9 (470 ohms), to that of a sixth capacitor C6 (4.7 nF) and to the regulation input 12 of modulator 10B, which is connected to the output 32 of the regulator stage 30 (see FIG. 3). The other terminal of capacitor C6 is connected to ground. The other terminal of resistor R8 is connected to the supply input 13 of modulator 10B receiving the input voltage VE. The other terminal of the ninth resistor R9 is connected to the base of a fourth NPN transistor T3, which forms the voltage comparator stage, whose emitter is connected to ground and whose collector (open), which forms the output 14 of modulator 10 B, is connected to the input 21 of the driver stage 20A (of FIG. 4) or 20B (of FIG. 5), formed by the cathode of the second diode D2. The value of capacitor C6 has been chosen so as to limit the maximum negative voltage applied to the base-emitter junction of transistor T3 to a value less than its reverse avalanche breakdown voltage. When the input voltage waveform
+VTL
is positive, as during the major portion of the flyback periods TR,
diode D6 short-circuits resistor R7 and we have then a simple passive RC
integrator formed by resistor R6 in series and two capacitors C5 and C6
in parallel, whose output is connected to the base of transistor T3
through resistor R9. Transistor T3 becomes conducting when its base
current IB formed by the sum of currents I1 and I2 becomes positive. The
current I1 shown by an arrow in FIG. 8 and on the Diagram H of FIG. 9,
results from the application of the +VTL waveform of Diagram J to the
above-mentionned simple integrator, during its positive alternation, and
to the cascaded double integrator R6, C5, R7, C6 during its negative
plateau going from t0 to t2. During this negative voltage plateau of the
+VTL signal, the current I1 becomes negative and linearly decreasing.
When the instantaneous negative amplitude of current I1 becomes equal to
the positive current I2 shown by another arrow in FIG. 8 and by means
of a reversed constant level (-I2) shown by a broken line in diagram H
of FIG. 7, which occurs at time t1, the base current of transistor T3 is
cancelled out and this latter is cut off. Since the current I2 is due
for a large part to the regulating current IR supplied by the output of
the regulator stage (30 in FIG. 3) and proportional to the error
voltage, the duration of the cut-off state (t4-t1) of transistor T3 and,
consequently, that (t2-t1) of the saturated state of the first
transistor T1 (as well as the duty cycle) will vary reversely to the
variation of this current IR. The current IE shown by an arrow in FIG.
8, which flows through the high-value resistor R8 from the input voltage
source VE and which is one of the components with IR of current I2,
forms a small current for maintaining transistor T3 saturated in the
absence of flyback pulses and thus of horizontal deflection. The fact
that resistor R8 is supplied by the unregulated input voltage VE allows
another parameter to be added for acting on the duty cycle of transistor
T3 as a function thereof. Diagram K of FIG. 9 illustrates the
rectangular signal VP obtained at the output 14 of the modulator 10B of
FIG. 8. 
FIG.
10 is a schematic diagram of a conventional regulator stage 30 of the
control circuit of FIG. 3. It is formed essentially by a well-known
circuit called differential amplifier having two inputs, the first of
which receives an adjustable fraction of the voltage to be stabilized,
formed, in the present case, by the output voltage VS of the power
supply device (BS, FIG. 1) and the second input of which receives a
stable reference voltage which is generally generated within this stage
(as in most known ballast or switched-mode voltage regulator). The reference voltage VZ is here produced by means of a Zener diode D7 (of the BZX83C type having a stabilized Zener voltage of 7.5 V) whose cathode is connected to the input 31 receiving the output voltage VS of the device BS (FIG. 1) and whose anode is connected through an eleventh resistor R11 (10 Kohms) to ground G. The second input of the differential amplifier used here is formed by the emitter of a fifth PNP transistor T4 which is connected to the anode of the Zener diode D7. The voltage (VS-VZ) biasing this emitter is then fixed with respect to the output voltage VS. The first input of the differential amplifier is here formed by the base of transistor T4 which is biased by a voltage-divider circuit, formed from a fifteenth resistor R15 (4.7 Kohms), a potentiometer R16 (5 Kohms) and a fourteenth resistor R14 (22 Kohms) connected in series between the input terminal 31 and ground G. The base of transistor T4, connected to the slider of potentiometer R16 receives then a previously adjusted fraction of the output voltage VS supplying the horizontal deflection circuit (SH), so that it forms a constant current generator supplying a current proportional to its emitter-base voltage which is equal to the difference (error voltage) between the reference voltage VZ and the selected fraction of the output voltage VS supplied by potentiometer R16. The collector of the fourth transistor T4, connected by a tenth resistor R10 (2.2 Kohms) to the output 32, supplies then the regulating current IR to the regulating input (12, FIGS. 3 and 8) of the pulse-width modulator (10 or 10B, FIGS. 3 and 8).
It will be noted here that a feedback circuit comprising a twelfth resistor R12 (5.6 Kohms) and a seventh capacitor C7 (4.7 nF) in series connects the collector of transistor 14 to its base.
The difference between the voltage respectively provided by the potentiometer R16 and the Zener diode D7 causes more or less heavy conduction of transistor T4 which delivers the current IR.
In short, when the output voltage VS increases, the voltage (VS-VZ) at the emitter of transistor T4 increases more than that applied to its base and current IR increases. The value of I1 at which transistor T3 is cut off increases then in absolute value and this transistor T3 is turned off later, which reduces the conducting period of transistor T1. The peak current in inductance L then diminishes, which causes a reduction of the output voltage VS which comes back to its nominal value, taking into account the residual error required for controlled operation.
FIG. 11 shows the complete simplified diagram of a power supply device BS of FIG. 1 whose control circuit SCA is respectively formed by the driver circuit 20A of FIG. 4, by the modulator 10B of FIG. 8 and the regulator stage 30 of FIG. 10, except for a few variations.
The variations concern a damping resistor R17 of 1 kiloohm shunting the inductance L, resistor R8 and resistor R10 which are both connected directly to the base of transistor T3 instead of being connected to the cathode of diode D6, resistor R11 which has been omitted and a resistor R13 which shunts the slider of potentiometer R16 to ground. These details of construction have no influence at all on the operation of the circuit such as it has been described above, but simply allow easier adjustment.
Another
embodiment is shown in FIG. 12. It allows more especially a television
set to be supplied with power in which the horizontal deflection circuit
operates from a higher DC voltage VS, of about 100 volts for example,
itself obtained from an initial output voltage VSI of about 60 volts.
The operation of the circuit is fundamentally the same as that of FIG.
11 and only the differences will be described below. The components
playing the same role in both diagrams bear the same references. The
values may however be different but their dimensioning is within the
scope of a man skilled in the art. The voltage VS delivered by the power
supply is used principally in the horizontal deflection circuit which
is the component consuming most power in the television set. The power
supply circuit components receiving permanently a voltage when the
horizontal deflection circuit is not operating, but when the mains is
connected, are solely those indispensable for activating the power
supply, i.e. the first switching transistor T1 and the circuit for
measuring the output voltage in the regulator stage 300. To simplify the driver stage 100, instead of the single switching transistor T1, an integrated Darlington circuit T10 is used of the BU 807 type, for example. Therefore, the gain is sufficient to omit a discrete driver transistor T2 and to connect the cathode of diode D3 directly to the base input of T10. The negative -VTH pulses, coming from an intermediate tapping on coil B2 of the line output transformer, are applied directly to the base of T10 through resistor R3 which is connected in series with a diode D9 whose cathode is connected to this intermediate tapping.
Instead of the input voltage VE, the power supply input 4 of the control circuit SCB is fed by a voltage obtained by rectifying the positive half-waves (plateaux) of the -VTL voltage supplied by the first secondary winding B2, by means of a diode D8 and a capacitor C8. Thus considerably lower voltage may be obtained than that supplying the horizontal deflection circuit, of the order of 13 volts, for example. A voltage of this value allows video amplification circuits as well as other circuit
s
of the television set to be supplied while providing for these latter a
very great reliability. This voltage is applied through resistor R1 to
the anodes of diodes D2 and D3 and through resistor R8 to the base of
the transistor T3 of modulator 10B. The regulator stage 300 here comprises two PNP transistors T4 and T5 connected differentially. For that, their emitters receive the voltage rectified by D8 through a resistor R18 of 1.5 kiloohms. The collector of transistor T5 is connected to ground through a resistor R20 of 3.9 kiloohms and the collector of transistor T4, which supplies the regulating current IR, is connected to the cathode of diode D6 through a resistor R10 of 4.7 kiloohms.
The reference voltage (6.2 volts) is supplied by a Zener diode D7 whose anode is connected to ground, and cathode to a resistor R19 (6.8 kiloohms) which receives the voltage rectified by D8. This reference voltage is applied to the base of transistor 14. A capacitor C9 (49 microfarads) shunts diode D7 so as to cause the reference voltage to rise gradually when the apparatus is switched on, which allows a gradual rise of the output voltage VS to be obtained.
A potentiometer R16 of 10 kiloohms connected between two stopper resistors R15 (68 kiloohms) and R14 (5.6 kiloohms) receives the voltage VS through the resistor R15 and is connected to ground through resistor R14. The sliding contact of potentiometer R16 allows a fraction of the voltage VS to be applied to the base T5. A resistor R13 (47 kiloohms) also connects this base to the common point between R15 and R16.
An anti-oscillation capacitor C10 (15 nanofarads) connects the base of the collector of transistor T5.
Thus the regulating current IR supplied by resistor R10 is directly dependent on the difference between the output voltage VS, applied to the horizontal deflection circuit, and the reference voltage determined by the Zener diode D7. The power supply BS thus stabilizes this voltage VS and at the same time the rectified voltage supplied by diode D8.
To stop this power supply, as well as that of FIG. 11 moreover, it is sufficient to stop by means of a remote control receiver, for example, the operation of the horizontal oscillator.
In this case, the input voltage VE is still present, but is considerably smaller than voltage VS. For the power supply of FIG. 12, this reduced voltage is only applied to the Darlington transistor T10 and a fraction thereof to the base of transistor T5 of the regulator stage 300. Thus the life expectation of the other components of the device BS is increased. Since the voltage supplied by diode D8 is itself regulated, it may be used for supplying a major portion of the television set, except for the horizontal deflection circuit supplied by voltage VS and the remote control receiver which must be capable of operating permanently (also in the ready state) so as to detect the turn-on control signal. The protection which was mentioned earlier on is then extended to the greatest part of the components of the television set.
It will be noted here that the three stages 10, 20 and 30 of control circuit SC (see FIGS. 1 and 3) may be formed by means of circuits different from those described and shown and which are known per se, and that it is sufficient to have a secondary winding B2 (in addition to the very-high-voltage winding) of the line transformer TL, supplying negative line-flyback pulses which may be used for generating a decreasing or increasing sawtooth voltage waveform as well as for controlling the cutting off of the first switching transistor T1.
East-West Correction Circuit SIEMENS TDA4610 Bipolar circuit
The TDA 4610 is used for pin cushion correction in colour TV sets. Moreover, the circuit offers the possibility of performing trapezoidal corrections as well as setting the picture width and the degree of the pin cushion correction. By making use of the switching operation, the diode modulation is controlled directly, thus resulting in very low power dissipation.
• Low power dissipation
• Wide regulating range
• Simple tuning
• Few external components.
Circuit description
The vertical saw-tooth voltage (2 V PP increasing from 0, fly-back time <0.1 msec) is applied to two differential amplifiers. Anti phase signals are available at the outputs of the differential amplifiers. Differential amplifier 1 controls the multiplexer which converts the saw tooth signal into a symmetrical parabola. The differential amplifier 2 controls a correction voltage circuit by which the shape of the parabola can be suited to the characteristics of the tube. The parabola signal is amplified and fed to the pulse width modulator. The modulator controls the final output transistor.
NORDMENDE COLOR 3537 CHASSIS F11 (THOMSON ICC3) Circuit arrangement for producing a vertical frequency deflection current CLASS D FRAME DEFLECTION CIRCUIT.A
circuit for generating a vertical frequency deflection current for the
electron beams in the picture tube of a television receiver includes a
current sensor resistor having one end connected to direct voltage
potential by two resistors connected in series and a second end
connected to a vertical frequency sawtooth signal by two additional
resistors connected in series. An error signal generator has one input
terminal connected to the junction the first two resistors and another
input terminal connected the junction of the second two resistors. An
output stage supplies the deflection current. The output terminal of
the error signal generator is connected to the input terminal of the
output stage. The error amplifier is a transconductance amplifier
having an output terminal connected to reference potential by a series
connection of a resistor and a capacitor.
1. In a circuit for generating
a vertical frequency deflection current for the electron beams in the
picture tube of a television receiver, said circuit including a
current sensor resistor having a first end connected to direct voltage
potential by first and second resistors connected in series at a
first junction and a second end connected to a vertical frequency
sawtooth signal by third and fourth resistors connected in series at a
second junction, an error amplifier having a first input terminal
connected to said first junction and a second input terminal connected
to said second junction, said circuit having an output stage for
supplying said deflection current, an output terminal of said error
amplifier being connected to an input terminal of said output stage,
an improvement wherein:
said error amplifier comprises a transconductance amplifier and
wherein said output terminal of said error amplifier is coupled via an
RC network formed by a series connection of a resistor and a
capacitor to a reference potential.
2. The improvement of claim 1 wherein said output stage operates in a
D-operation and further includes a pulse width modulator and an
electronic switch means, the output terminal of said transconductance
amplifier being connected to said RC network.
3. The improvement of claim 1 wherein said output stage
includes an amplifier working in A-B operation and an electronic
switch means, the output terminal of said transconductance amplifier
being connected to said RC network.
4. The improvement of claim 2 wherein the time constant of said RC
network is in an order of magnitude of several lines times of said
picture tube. 5. The improvement
of claim 3 wherein the time constant of the RC network is in an order
of magnitude of several lines times of said picture tube.
Description:
This is a continuation of PCT application PCT/EP 91/00531 filed Mar.
19, 1991 by Rudolf Koblitz and titled "Circuit Arrangement For
Producing A Vertical Frequency Deflection Current".
In modern television receivers, the deflection current is generated by means of a class D amplifier. An electronic switch is triggered by pulse width modulated pulses running at line frequency to periodically switch the deflection coils to frame potential using a line transformer. The deflection current is regulated by an error amplifier, the output terminal of which is connected to one of the input terminals of a pulse width modulator. The other input terminal of the pulse width modulator receives a horizontal frequency sawtooth signal. The error amplifier is connected across one diagonal of a resistance bridge, whereby the two input terminals of the error amplifier are connected to a fixed operat
ing
voltage by equal size resistors. Also, a direct voltage reference
potential and a vertical frequency sawtooth signal, are applied to the
input terminals of the error amplifier by two additional resistors
which are the same size as the other two resistors. A sensing
resistor, having very low resistance, is connected between the two
resistors which are connected to the fixed operating voltage. Such an
arrangement is disadvantageous in that the bridging resistors, the error
amplifier and the DC behavior of the horizontal frequency sawtooth
signal are subject to temperature and other environmental changes. Also,
the various circuit components have inherent tolerances which
frequently negatively impact the stability of the circuit.
It is an object of the invention to eliminate the undesirable effects of such drifting and tolerances so that the stability of the circuit arrangement is reduced to the thermal stability of the resistance bridge and of the input offset behavior of the error amplifier, so that the circuit can be realized by way of integrated circuit technology.
Preferred embodiments are described with reference to the drawings, in which:
FIG. 1 is a first preferred embodiment of the invention.
FIG. 2 is a second preferred embodiment of the invention.
In FIG. 1, a vertical deflection circuit includes vertical deflection coils LV which are connected to an operating direct voltage UB by a current sensor resistor RS which measures the deflection current. The defl
ection
coils LV are switched to reference potential by a controllable
electronic switch TH. A winding W of a line transformer ZT and an
inductive impedance L connects the switch to the deflection coils LV.
The junction of the vertical deflection coils LV and the winding W of
the line transformer ZT is connected to frame potential by an
integrated capacitor C2. A diode D is connected in parallel to an
electronic switch TH to permit a reflux, or free-running operation the
circuit. The electronic switch TH is triggered by line frequency pulses
which are pulse width modulated so that the intervals during which
the vertical deflection coils LV are at frame potential, are adapted
to the deflection angle. The line frequency trigger pulses are
supplied by a pulse width modulator PBM having two input terminals.
The negative input terminal is connected to a horizontal frequency
sawtooth signal UH and the positive input terminal is connected to the
signal from an error amplifier FV. The error amplifier-FV has two
input terminals which are wired in a bridge consisting of two pairs of
resistors R1, R1' and R2, R2'. The two resistors R1 and R1' are
connected to the operating voltage UB and a capacitor C1. The current
sensor resistor RS is located between these resistors. One of the two
other branches of the bridge receive a fixed reference potential VDC
from resistor R2 and the other branch receives a vertical frequency
sawtooth signal UV from resistor R2'. The error amplifier FV regulates
the width of the pulses, and thus the deflection current, in such a
way that the bridge voltage Ub is zero.
In the FIG. 1 embodiment, a transconductance amplifier, which has the ability to convert an input voltage into an output current, is used as the error amplifier FV. In the example, the transconductance amplifier supplies a current of 1 to 2 mA per 1 V change in input voltage, i.e. it has a g of 1 to 2 mA/V. The output terminal of the amplifier FV is connected to an input stage including an RC network, pulse width generator PBM, and the switching circuit thyristor TH and diode D. The RC circuit is composed of a resistor Ra and a capacitor Ca and is connected to the output terminal of the transconductance amplifier. The RC circuit has a RC time constant in the order of several line times and therefore complete correction is carried out in a few lines. In this embodiment the output stage operates in a D-type operation. In a circuit design tested in practice, a resistance Ra of 33 kOhm and a capacitance Ca of 15 nF were used. A capacitor Cb is parallel to the RC circuit to filter out the remaining line frequency components. In this way, the drift of the horizontal sawtooth signal and the drift of the electronic switch are eliminated. The resistor Ra of the RC circuit supplies the P-portion of the PI controller which also guarantees stability of regulation.
Another prefer
red
embodiment is shown in FIG. 2. In this embodiment the output stage is
an amplifier which works in A-B operation. The positive input
terminal of the amplifier V is connected to a fixed reference voltage
Uref. The signal from the transconductance amplifier FV is connected to
the negative, input of terminal of the amplifier V. The same
considerations regarding drift and temperature behavior are valid for
this arrangement as with the preferred embodiment shown in FIG. 1.
In modern television receivers, the deflection current is generated by means of a class D amplifier. An electronic switch is triggered by pulse width modulated pulses running at line frequency to periodically switch the deflection coils to frame potential using a line transformer. The deflection current is regulated by an error amplifier, the output terminal of which is connected to one of the input terminals of a pulse width modulator. The other input terminal of the pulse width modulator receives a horizontal frequency sawtooth signal. The error amplifier is connected across one diagonal of a resistance bridge, whereby the two input terminals of the error amplifier are connected to a fixed operat
ing
voltage by equal size resistors. Also, a direct voltage reference
potential and a vertical frequency sawtooth signal, are applied to the
input terminals of the error amplifier by two additional resistors
which are the same size as the other two resistors. A sensing
resistor, having very low resistance, is connected between the two
resistors which are connected to the fixed operating voltage. Such an
arrangement is disadvantageous in that the bridging resistors, the error
amplifier and the DC behavior of the horizontal frequency sawtooth
signal are subject to temperature and other environmental changes. Also,
the various circuit components have inherent tolerances which
frequently negatively impact the stability of the circuit. It is an object of the invention to eliminate the undesirable effects of such drifting and tolerances so that the stability of the circuit arrangement is reduced to the thermal stability of the resistance bridge and of the input offset behavior of the error amplifier, so that the circuit can be realized by way of integrated circuit technology.
Preferred embodiments are described with reference to the drawings, in which:
FIG. 1 is a first preferred embodiment of the invention.
FIG. 2 is a second preferred embodiment of the invention.
In FIG. 1, a vertical deflection circuit includes vertical deflection coils LV which are connected to an operating direct voltage UB by a current sensor resistor RS which measures the deflection current. The defl
ection
coils LV are switched to reference potential by a controllable
electronic switch TH. A winding W of a line transformer ZT and an
inductive impedance L connects the switch to the deflection coils LV.
The junction of the vertical deflection coils LV and the winding W of
the line transformer ZT is connected to frame potential by an
integrated capacitor C2. A diode D is connected in parallel to an
electronic switch TH to permit a reflux, or free-running operation the
circuit. The electronic switch TH is triggered by line frequency pulses
which are pulse width modulated so that the intervals during which
the vertical deflection coils LV are at frame potential, are adapted
to the deflection angle. The line frequency trigger pulses are
supplied by a pulse width modulator PBM having two input terminals.
The negative input terminal is connected to a horizontal frequency
sawtooth signal UH and the positive input terminal is connected to the
signal from an error amplifier FV. The error amplifier-FV has two
input terminals which are wired in a bridge consisting of two pairs of
resistors R1, R1' and R2, R2'. The two resistors R1 and R1' are
connected to the operating voltage UB and a capacitor C1. The current
sensor resistor RS is located between these resistors. One of the two
other branches of the bridge receive a fixed reference potential VDC
from resistor R2 and the other branch receives a vertical frequency
sawtooth signal UV from resistor R2'. The error amplifier FV regulates
the width of the pulses, and thus the deflection current, in such a
way that the bridge voltage Ub is zero. In the FIG. 1 embodiment, a transconductance amplifier, which has the ability to convert an input voltage into an output current, is used as the error amplifier FV. In the example, the transconductance amplifier supplies a current of 1 to 2 mA per 1 V change in input voltage, i.e. it has a g of 1 to 2 mA/V. The output terminal of the amplifier FV is connected to an input stage including an RC network, pulse width generator PBM, and the switching circuit thyristor TH and diode D. The RC circuit is composed of a resistor Ra and a capacitor Ca and is connected to the output terminal of the transconductance amplifier. The RC circuit has a RC time constant in the order of several line times and therefore complete correction is carried out in a few lines. In this embodiment the output stage operates in a D-type operation. In a circuit design tested in practice, a resistance Ra of 33 kOhm and a capacitance Ca of 15 nF were used. A capacitor Cb is parallel to the RC circuit to filter out the remaining line frequency components. In this way, the drift of the horizontal sawtooth signal and the drift of the electronic switch are eliminated. The resistor Ra of the RC circuit supplies the P-portion of the PI controller which also guarantees stability of regulation.
Another prefer
red
embodiment is shown in FIG. 2. In this embodiment the output stage is
an amplifier which works in A-B operation. The positive input
terminal of the amplifier V is connected to a fixed reference voltage
Uref. The signal from the transconductance amplifier FV is connected to
the negative, input of terminal of the amplifier V. The same
considerations regarding drift and temperature behavior are valid for
this arrangement as with the preferred embodiment shown in FIG. 1.
NORDMENDE COLOR 3537 CHASSIS F11 (THOMSON ICC3) THOMSON CHASSIS ICC3 Switched-mode frame-scan control circuit for a videofrequency receiver
Fundamentals (see Figure 80)
The secondary winding of EHT transformer provides
the energy required by frame yoke.
The frame current modulation is achieved by
modulating the horizontal saw-tooth current and
subsequent integration by a ”L.C” network to reject
the horizontal frequency component.
General Description
The basic circuit is the phase comparator ”C1”
which compares the horizontal saw-tooth and the
output voltage of Error Amplifier ”A”.
The comparator output will go ”high” when the
horizontal saw-tooth voltage is higher than the ”A”
output voltage. Thus, the Pin 4 output signal is
switched in synchronization with the horizontal frequency
and the duty cycle is modulated at frame
frequency.
A driver stage delivers the current required by the
external power switch.
The external thyristor provides for energy transfer
between transformer and frame yoke.
The thyristor will conduct during the last portion of
horizontal trace phase and for half of the horizontal
retrace.
The inverse parallel-connected diode ”D” conducts
during the second portion of horizontal retrace and
at the beginning of horizontal trace phase.
Main advantages of this system are :
- Power thyristor soft ”turn-on”
Once the thyristor has been triggered, the current
gradually rises from 0 to IP, where IP will reach
the maximumvalue at the end of horizontal trace.
The slope current is determined by, the current
available through the secondary winding, the
yoke impedance and the ”L.C.” filter characteristics.
- Power thyristor soft ”turn-off”
The secondary output current begins decreasing
and falls to 0 at the middle of retrace. The thyristor
is thus automatically ”turned-off”.
- Excellent efficiency of power stage dueto very
low ”turn-on” and ”turn-off” switching losses.
Frame Flyback
During flyback, due to the loop time constant, the
frame yoke current cannot be locked onto the
reference saw-tooth. Thus the output of amplifier
”A” will remain high and the thyristor is blocked.
The scanning current will begin flowing through
diode ”D”. As a consequence, the capacitor ”C”
starts charging upto the flyback voltage.The thyristor
is triggered as soon as the yoke current reaches
the maximum positive value.
This circuit comprises a saw-tooth signal generating circuit having a
single active switch monodirectional in voltage and bidirectional in
current, controlled by a cyclic ratio control circuit connected, on the
one hand, to a static servo-control circuit so as to ensure optimum
operation of the active-switch circuit and, on the other hand, to a
dynamic servo-control circuit so as to ensure conformity of the law of
variation of the current in the deflector with respect to an S-corrected
frame saw-tooth law.
Such a circuit is used in transistorized videofrequency receivers.
1. A switched-mode frame-scan control circuit comprising a circuit for
generating a saw-tooth signal having an active switch monodirectional
in voltage and bidirectional in current, connected to the terminals of a
load comprising the vertical deflector in series with a measuring
resistor and a connecting capacitor, wherein the active switch is
controlled by a cyclic ratio control circuit connected, on the one
hand, to a static servo-control circuit one input terminal of which is
connected to the positive terminal of the connecting capacitor and the
other input terminal to a reference DC voltage generator, so as to
maintain a sufficiently high and stable voltage at the terminals of
this capacitor for optimum operation of the active-switch circuit and,
on the other hand, to a dynamic servo-control circuit one input
terminal of which is connected to the measuring resistor and the other
input terminal to a circuit for generating frame saw-teeth corrected
into an S, so as to ensure conformity of the law of variation of the
current in the deflector with respect to this corrected frame saw-tooth
law; these two servo-control circuits taking effect on the moment when
the active switch is triggered.
2. The frame-scan control circuit as claimed in claim 1, wherein the
cyclic ratio control circuit comprises a switching transistor receiving
at its base, on the one hand, a synchronizing line saw-tooth signal
and, on the other hand, the correction signals coming from the static
and dynamic servo-control circuits, its collector being connected to
the control electrode of the active switch.
3. The frame-scan control circuit as claimed in claim 2, wherein the
active switch comprises a thyristor whose anode is connected to the
cathode of a diode and the cathode to the anode of this same diode, the
gate of this thyristor being connected through an interface shaping
circuit to the collector of the transistor of the cyclic ratio control
circuit.
4. The frame-scan control circuit as claimed in claim 3, wherein the
interface shaping circuit comprises a resistor one terminal of which is
connected to the collector of the transistor of the cyclic ratio
control circuit and the other is connected, on the one hand, to a
terminal of a network comprising a resistor in parallel with a capacitor
whose other terminal is to ground and, on the other hand, to the gate
of the thyristor.
5. The frame-scan control circuit as claimed in one of claims 1 to 4,
wherein the static servo-control circuit comprises a servo-control
transistor receiving at its base, on the one hand, an error signal
coming from the difference between
a reference voltage and the voltage at the terminals of the connecting
capacitor and, on the other hand, the error signal from the dynamic
servo-control circuit comprising two resistors in series, one of these
resistors being connected to the corrected frame saw-tooth generating
circuit, the other to the measuring resistor, and their common
connection point through a capacitor to the base of the servo-control
transistor whose collector is connected to the input of the cyclic
ratio control circuit.
6. The frame-scan control circuit as claimed in claim 5, wherein the
reference voltage of the static servo-control circuit is fixed by a
resistor connected between the base of the servo-control transistor and
ground.
7. The frame-scan control circuit as claimed in claim 5 or 6, wherein
the collector circuit of the servo-control transistor comprises a
resistor for protecting against unduly high variations of the collector
current of this servo-control transistor.
8. A videofrequency receiver, equipped with a switched-mode frame-scan
control circuit as claimed in one of claims 1 to 7.
Description:
BACKGROUND OF THE INVENTION
The invention relates to a switched-mode frame-scan control circuit used in particular in television receivers.
The vertical movement of the spot on the screen of a cathode-ray tube is provided by coils, called vertical-deflection or frame-scan coils, through which flows a current generally in saw-tooth form. In the case of the French standard, this current has a period of 20 milliseconds and a frame scan return time less than 1 ms.
In the prior art, this current is generated by means of electronic devices comprising generally a disabled oscillator supplying a saw-tooth voltage synchronized with the frame frequency, a connecting stage with high input impedance and low output impedance, and an output stage supplying to the vertical deflection coils the current having the amplitude and shape required for vertical deflection of the spot of the cathode-ray tube. This output stage may be a class A biased power amplifier, or else a complementary-symmetry or class AB biased "push-pull" amplifier.
Chopper devices, provided with active switches such as thyristors, are also used for generating the frame-scan current.
In this case, one of the active switches ensures the vertical scan of the upper half of the screen, by charging a capacitor connected in parallel with the vertical deflection winding by means of voltage pulses of decreasing width in time and of a given polarity.
The second switch ensures the vertical scan of the lower half of the screen, by charging the condenser by means of voltage pulses of decreasing width in time and of a polarity opposite the preceding one.
The discharge of this condenser causes in fact a saw-tooth current to flow through the vertical deflection winding.
The two paths of these chopper devices are monodirectional in current flow, each in a different direction.
The French patent application filed under the No. 78/22266 on July 27, 1978, in the name of the applicant proposes a single-path chopper device, i.e. a single active switch.
In fact, for this the vertical deflector is connected in series with a measuring resistance and a connecting capacitor whose value is sufficiently high for
the voltage at the terminals of the unit thus formed to keep the same
polarity whatever the direction of the current flowing through the
vertical deflector. This unit then behaves sometimes as generator,
sometimes as a receiver, and is connected to a circuit for generating a
saw-tooth signal from the line-scan return signal, monodirectional in
voltage and bidirectional in current, controlled by a control circuit
synchronized to the line frequency.
In accordance with the previously mentioned French patent application No. 78/22266, the active switch is enabled during the outward line scan, the time when it starts to conduct defining the current flowing through the deflector.
SUMMARY OF THE INVENTION
The present invention proposes, so as to obtain for such a single-path chopper device stable amplitude and linearity of the image despite the drift and non-linearity shortcomings of the electronic components, elaborating a simple and efficient servo-control system.
In fact, the switched-mode frame-scan control circuit of the invention comprises a circuit for generating a saw-tooth signal with an active switch monodirectional in voltage and bidirectional in current, connected to the terminals of a load comprising the vertical deflector in series with a measuring resistance and a connecting capacitor, and is characterized in that the active switch is controlled by a cyclical ratio control circuit connected, on the one hand, to a static servo-control circuit one input terminal of which is connected to the positive terminal of the connecting capacitor and the other terminal to a reference DC voltage generator, so as to maintain a sufficiently high and stable voltage at the terminals of this capacitor for optimum operation of the active switch circuit and, on the other hand, to a dynamic servo-control circuit one input terminal of which is connected to the measuring resistance and the other input terminal to a generator of frame saw-teeth corrected into an S, so as to ensure conformity of the law of variation of the current in the deflector with respect to this corrected frame saw-tooth law; these two servo-control circuits taking effect on the moment when the active switch is energized.
DESCRIPTION OF THE DRAWINGS
Other characteristics and advantages of the invention will become clear from the following description, given by way of non-limiting example and illustrated by the accompanying figures in which:
FIG. 1 is a block diagram of a switched-mode frame-scan circuit comprising a control circuit in accordance with the invention;
FIG. 2 is a diagram of one embodiment of the switched-mode frame-scan control circuit of the invention;
FIGS. 3a, b and c are graphical representations of different voltages measured on the circuit shown in FIG. 2.
DESCRIPTION OF THE PREFERRED EMBODIMENTS
FIG. 1 shows a block diagram of a switched-mode frame-scan circuit.
Load 1 comprises the vertical deflector D v protected by a parallel resistor R p , a connecting capacitor C L and a measuring resistor R m .
The value of capacitor C L is chosen so as to have at its terminals a sufficiently high voltage, such as described in the above-mentioned patent application No. 78/22266, so as to obtain at the terminals of the load a positive voltage whatever the direction of the current through the deflector. The load behaves then in a first stage as a receiver of energy and in a second stage as a generator.
This load 1 is connected to the terminals of a circuit 2 generating a saw-tooth signal.
This circuit 2 generates in the vertical deflector D v a saw-tooth signal from line-scan return signals.
In fact, during the scan return, there appears in the secondary windings of the line transformer a periodic alternating signal at the line frequency.
The saw-tooth current is obtained by chopping this alternating signal generated in a secondary winding of the line transformer T L . This chopping is effected by means of an active switch I S1 bidirectional in current and monodirectional in voltage, connected in series with the secondary winding S 1 of transformer T L , as well as with an inductance L S not coupled to the line transformer, the whole being mounted in parallel with a filtering capacitor C f .
The value of capacitor C f is chosen sufficiently high for the alternating part of the voltage at its terminals to be very small with respect to the signal at the terminals of winding S 1 , and so negligible.
Another secondary winding S 2 of the line transformer is connected to the input of a line saw-tooth generating circuit 4. This circuit 4 supplies from the signal available at the terminals of winding S 2 a saw-tooth signal during the outward travel of the line scan.
This saw-tooth signal is injected into an input e 1 of a cyclic ratio control circuit 3, which delivers a rectangular signal at the input of an interface circuit 10 whose output is connected to the control electrode of the active switch I S1 .
This interface circuit enables the rectangular control signal available at the output of the cyclic ratio control circuit 3 to be adapted with respect to the electrical characteristics of active switch I S1 .
The leading edge of the rectangular signal corresponding to the moment when active switch I S1 is closed.
Now, the position of this leading edge, and so the moment when active switch I S1 is closed, depend on the signal applied to the input e 2 of the cyclic ratio control circuit.
As was described in patent application No. 78/22266, the more active switch I S1 is triggered in advance of the moment when the line return begins, the more the average current in inductance Ls decreases with respect to its maximum value corresponding to the case when the active switch is still disabled.
It is thus possible to control the value of the average current in inductance Ls, so the value of the current in deflector Dv by controlling the moment when active switch I S1 is closed. During the outward travel of the frame scan, so that the current in vertical deflector D v follows a frame saw-tooth law, it is sufficient then to suitably control the successive moments when active switch I S1 is closed.
This suitable control will be ensured by the signal applied to the input e 2 of the cyclic ratio control circuit 3.
This signal comes, on the one hand, from a dynamic servo-control circuit 7 the input e 4 of which is connected to the terminals of measuring resistor R m and the input e 3 to a corrected saw-tooth generating circuit 5.
The voltage of the terminals of Rm depends on the current flowing through vertical deflector D v . The servo-control circuit 7 supplies then an error signal depending on the difference between the vertical deflection current and the corrected saw-tooth voltage.
A frame-separator circuit 9 receives at its input E the complete synchronizing signals taken from the video signal, and after integration and clipping delivers a frame-synchronization signal.
This frame-synchronization signal is applied to the input of an oscillator circuit 8. This latter drives the circuit generating the corrected saw-teeth whose form prefigures the current required in the vertical deflector coil D v . There is in general available at this level a linearity and amplitude adjustment, symbolized by the potentiometers P L and P a .
The input e 2 of cyclic ratio control circuit 3 is moreover connected to a static servo-control circuit 6 which ensures the maintenance and the monitoring of the average voltage at the terminals of connecting capacitor C L with respect to a reference defined so as to ensure correct and optimum operation of the switched-mode frame-scan circuit.
FIG. 2 shows one simple embodiment of a frame-scan control circuit in accordance with the invention.
The complete synchronization signals taken from the video signal are applied to input E.
The frame-separator circuit is formed, on the one hand, from an integrator stage R S1 , C S1 and R S2 mounted in T and, on the other hand, a transistor T S1 biased by resistors R S3 and R S4 .
The input E is effected on a terminal of resistor R S1 , and the base of transistor T S1 is connected to a terminal of resistor R S2 .
Resistors R S3 and R S4 cause emitter biasing creating the threshold for triggering transistor T S1 .
When the synchronization signal applied to input E characterizes the frame-synchronization signal, transistor T S1 passes from a disabled state to a saturated state.
The collector of transistor T S1 is connected through a resistor R S5 to the input of an oscillator circuit.
This oscillator circuit comprises two transistors T O1 and T O2 operating simultaneously in disabled or saturated states.
When these two transistors T O1 and T O2 are saturated (frame return), with the collector-emitter voltage practically zero, the voltage V O1 at the terminals of resistor R O1 is small. The current then flowing through resistors R O7 , R O6 , R O4 connected in the emitter circuit of transistor T O2 , must then be insufficient to maintain the saturated state of the two transistors T O1 , T O2 . Thus, when capacitors C O1 and C O2 are sufficiently discharged, transistors T O1 and T O2 are disabled. Voltage V O1 passes then suddenly from a low value to a higher value, this value being imposed by the divider bridge formed by resistors R O1 and R O2 .
Resistors R O7 and R O6 ensure the charging of capacitors C O1 and C O2 until the moment when transistor T O2 becomes saturated again.
The frequency of the oscillator thus obtained, if resistor R S5 is disconnected, is slightly less than the frame frequency, i.e. 50 Hz.
At the moment of the frame-synchronization signal, with transistor T S1 becoming saturated and transistors T O1 and T O2 being disabled, voltage V O1 drops to assume a value depending on resistor R S5 . For transistors T O1 and T O2 to pass to the saturated state, voltage V O2 at the terminals of series capacitors C O1 and C O2 must at this same moment become greater than the voltage V O1 at the terminals of resistor R O1 .
The saturation pulse delivered by the collector of transistor T S1 will only be taken into account for a certain part of the period of the oscillator corresponding to the end of charging of capacitors C O1 and C O2 , i.e. when the charging voltage is greater than voltage V O1 .
This enables the immunity of the oscillator to be improved in part with respect to the parasite pulses causing saturation of transistor T S1 .
This oscillator circuit is connected to a buffer circuit comprising transistor T t1 , resistor R t1 and potentiometer P t1 .
The voltage V O2 at the terminals of capacitors C O1 and C O2 varies in accordance with an approximate saw-tooth law.
Since the resistance of resistor R O7 is very high, transistor T t1 whose base is connected to the junction point of the two resistors R O7 and R O6 , forms an impedance-lowering stage, so as to connect between the emitter of transistor T t1 and the common connection point of capacitors C O1 and C O2 , the network comprising a resistor R t1 in series with a potentiometer P t1 .
Thus there is added to the saw-tooth voltage available at the terminals of series capacitors C O1 and C O2 , a parabolic voltage due to P t1 , P t1 and to capacitor C O2 .
Thus there is obtained at V t2 between the emitter of transistor T t1 and ground a voltage in the form of saw-teeth corrected to an S corresponding to the law of the current required in frame deflector D v .
Thus there is obtained at output V t1 the corrected saw-tooth signal required for the dynamic servo-control circuit of the invention which will be described further on.
The cyclic ratio control circuit of the invention only comprises a single active stage, the switching-biased transistor T c1 .
This transistor T c1 has its base connected to a circuit for generating line saw-teeth from the line return signal.
In fact, the circuit formed by capacitor C c2 in series with resistor R c2 and capacitor C c1 forms an integrator transforming the line-scan return voltage V c1 , shown in FIG. 3a, taken from the winding S 2 of line transformer T L , into a triangular signal.
This triangular signal available between the base and the emitter of transistor T c1 is shown in FIG. 3b.
The collector of transistor T c1 is connected through an interface circuit (R f1 ; R f2 , C f2 ) for matching to the gate of a thyristor TH 1 forming with diode D f1 and resistor R f3 in series with capacitor C f3 , the active switch I S1 .
In fact, in accordance with FIG. 1, the vertical deflector formed from inductance L v and series resistor R v , protected by resistor R p , is connected in series with the connecting capacitor C L and measuring resistor R m .
The load thus formed is c
onnected in parallel with the saw-tooth signal generator comprising capacitor C f connected in parallel with the inductance, the unit formed from inductance L S in series with winding S 1 of line transformer T L and the active switch TH 1 , D f1 , C f3 and R 3 .
The cathode of diode D f1 is connected to the anode of thyristor TH 1 and to a terminal of winding S 1 . The anode of this diode D f1 is connected to the cathode of the thyristor and to a terminal of capacitor C f .
This thyristor TH 1 operates as a switch, when its gate current is sufficient for it to be conducting, it short-circuits diode D f1 .
This active switch is bidirectional in current and monodirectional in voltage, for in fact when it is closed, it may have flowing therethrough currents in opposite directions and when it is open it has at its terminals a voltage of given polarity corresponding to the inverse voltage of diode D f1 .
The form of the current in the vertical deflector is linked to the moment when this active switch is closed such as this is described in patent application No. 78/22266 filed in the name of the applicant.
The dynamic servo-control circuit is formed by resistor R a2 one terminal of which is connected to resistor R m and the other to resistor R a1 in series with potentiometer P a1 , capacitor C a1 and transistor T a1 .
Potentiometer P a1 receives at one of its terminals the corrected saw-tooth signal available at the emitter of T t1 .
The emitter of transistor T a1 is connected to ground and its collector to the base of transistor T c1 through a resistor R c1 .
The direction of the current in the frame deflector is such that, during the outward travel of the frame scan, the voltage at the terminals of measuring resistor R m is in phase opposition with the corrected saw-tooth voltage V t1 . The corrected saw-tooth voltage is then compared with the voltage at the terminals of measuring resistor R m by the resistor bridge R a2 , R a1 , P a1 .
Transistor T a1 amplifies the possible dynamic error signal between the voltage at the terminals of resistor R m and the correct saw-tooth voltage.
Since the voltage at the terminals of R m depends on the current flowing through the vertical deflector, the error signal depends then on the difference between the vertical deflection current and the corrected saw-tooth voltage.
This error signal is then found again in the collector circuit of transistor T a1 .
Moreover, the static servo-control is obtained by resistors R a4 , R a3 and the same transistor T a1 .
The reference voltage is the base voltage threshold of transistor T a1 fixed by resistor R a3 .
The base of transistor T a1 is connected through a resistor R a4 to the positive terminal of the electrochemical capacitor C L . If the average voltage at the terminals of capacitor C L tends to increase, the base current of transistor T a1 increases and so its collector current as well.
This increase of the collector current causes an increase of the duration in the saturated state of transistor T c1 of the cyclic ratio control circuit and an advance in the triggering of thyristor TH 1 causing thereby a reduction in the mean voltage of capacitor C L .
In fact, in the absence of a collector current of transistor T a1 , capacitors C c1 and C c2 take on a mean charge sufficient to maintain transistor T c1 disabled. And when a DC current appears in the collector circuit of transistor T a1 , the combination of this current with that due to the line saw-tooth generating circuit (C c2 , R c2 , C c1 ) causes the saturating of transistor T c1 during the end of the outward travel of the line scan.
There is then obtained at the collector of transistor T c1 a square-wave signal such as shown in FIG. 3c.
The conduction time of transistor T c1 , i.e. the time T c of FIG. 3c, depends on the collector current of transistor T a1 , which modifies the form of the base-emitter control voltage of transistor T c1 such as shown in FIG. 3b.
The moment when TH 1 begins to close corresponds to the leading edge of the square-wave signal available at the collector output of transistor T c1 .
Furthermore, resistor R c1 serves to limit the collector current of transistor T a1 and the base current of transistor T c1 when transistor T a1 tends to be saturated in the case of accidental phenomena.
The gain of the transistor is chosen so that, during the outward travel of the frame scan, the variation of the base voltage of T a1 is negligible with respect to the corrected saw-tooth alternating voltage and the voltage at the terminals of resistor R m . The alternating current flowing through capacitor C a1 is then small with respect to the current flowing through the resistor bridge P a1 +R a1 , R a2 . The law of variation of the voltage at the terminals of resistor R m is then the same as the corrected saw-tooth voltage except for the sign since they are in phase opposition.
The dynamic servo-control thus achieved is such that the current flowing through the deflector is the image of the corrected saw-tooth voltage.
And furthermore, the proper operation of the output stage when switching is ensured by the previously described static servo-control.
This single-active-switch frame-scan control circuit has then the advantage of having a simplified and servo-controlled cyclic ratio control circuit.
This control circuit for switched-mode frame scanning in accordance with the invention is principally used in transistorized television receivers.
The invention relates to a switched-mode frame-scan control circuit used in particular in television receivers.
The vertical movement of the spot on the screen of a cathode-ray tube is provided by coils, called vertical-deflection or frame-scan coils, through which flows a current generally in saw-tooth form. In the case of the French standard, this current has a period of 20 milliseconds and a frame scan return time less than 1 ms.
In the prior art, this current is generated by means of electronic devices comprising generally a disabled oscillator supplying a saw-tooth voltage synchronized with the frame frequency, a connecting stage with high input impedance and low output impedance, and an output stage supplying to the vertical deflection coils the current having the amplitude and shape required for vertical deflection of the spot of the cathode-ray tube. This output stage may be a class A biased power amplifier, or else a complementary-symmetry or class AB biased "push-pull" amplifier.
Chopper devices, provided with active switches such as thyristors, are also used for generating the frame-scan current.
In this case, one of the active switches ensures the vertical scan of the upper half of the screen, by charging a capacitor connected in parallel with the vertical deflection winding by means of voltage pulses of decreasing width in time and of a given polarity.
The second switch ensures the vertical scan of the lower half of the screen, by charging the condenser by means of voltage pulses of decreasing width in time and of a polarity opposite the preceding one.
The discharge of this condenser causes in fact a saw-tooth current to flow through the vertical deflection winding.
The two paths of these chopper devices are monodirectional in current flow, each in a different direction.
The French patent application filed under the No. 78/22266 on July 27, 1978, in the name of the applicant proposes a single-path chopper device, i.e. a single active switch.
In fact, for this the vertical deflector is connected in series with a measuring resistance and a connecting capacitor whose value is sufficiently high for
the voltage at the terminals of the unit thus formed to keep the same
polarity whatever the direction of the current flowing through the
vertical deflector. This unit then behaves sometimes as generator,
sometimes as a receiver, and is connected to a circuit for generating a
saw-tooth signal from the line-scan return signal, monodirectional in
voltage and bidirectional in current, controlled by a control circuit
synchronized to the line frequency. 
In accordance with the previously mentioned French patent application No. 78/22266, the active switch is enabled during the outward line scan, the time when it starts to conduct defining the current flowing through the deflector.
SUMMARY OF THE INVENTION
The present invention proposes, so as to obtain for such a single-path chopper device stable amplitude and linearity of the image despite the drift and non-linearity shortcomings of the electronic components, elaborating a simple and efficient servo-control system.
In fact, the switched-mode frame-scan control circuit of the invention comprises a circuit for generating a saw-tooth signal with an active switch monodirectional in voltage and bidirectional in current, connected to the terminals of a load comprising the vertical deflector in series with a measuring resistance and a connecting capacitor, and is characterized in that the active switch is controlled by a cyclical ratio control circuit connected, on the one hand, to a static servo-control circuit one input terminal of which is connected to the positive terminal of the connecting capacitor and the other terminal to a reference DC voltage generator, so as to maintain a sufficiently high and stable voltage at the terminals of this capacitor for optimum operation of the active switch circuit and, on the other hand, to a dynamic servo-control circuit one input terminal of which is connected to the measuring resistance and the other input terminal to a generator of frame saw-teeth corrected into an S, so as to ensure conformity of the law of variation of the current in the deflector with respect to this corrected frame saw-tooth law; these two servo-control circuits taking effect on the moment when the active switch is energized.
DESCRIPTION OF THE DRAWINGS
Other characteristics and advantages of the invention will become clear from the following description, given by way of non-limiting example and illustrated by the accompanying figures in which:
FIG. 1 is a block diagram of a switched-mode frame-scan circuit comprising a control circuit in accordance with the invention;
FIG. 2 is a diagram of one embodiment of the switched-mode frame-scan control circuit of the invention;
FIGS. 3a, b and c are graphical representations of different voltages measured on the circuit shown in FIG. 2.
DESCRIPTION OF THE PREFERRED EMBODIMENTS
FIG. 1 shows a block diagram of a switched-mode frame-scan circuit. Load 1 comprises the vertical deflector D v protected by a parallel resistor R p , a connecting capacitor C L and a measuring resistor R m .
The value of capacitor C L is chosen so as to have at its terminals a sufficiently high voltage, such as described in the above-mentioned patent application No. 78/22266, so as to obtain at the terminals of the load a positive voltage whatever the direction of the current through the deflector. The load behaves then in a first stage as a receiver of energy and in a second stage as a generator.
This load 1 is connected to the terminals of a circuit 2 generating a saw-tooth signal.
This circuit 2 generates in the vertical deflector D v a saw-tooth signal from line-scan return signals.
In fact, during the scan return, there appears in the secondary windings of the line transformer a periodic alternating signal at the line frequency.
The saw-tooth current is obtained by chopping this alternating signal generated in a secondary winding of the line transformer T L . This chopping is effected by means of an active switch I S1 bidirectional in current and monodirectional in voltage, connected in series with the secondary winding S 1 of transformer T L , as well as with an inductance L S not coupled to the line transformer, the whole being mounted in parallel with a filtering capacitor C f .
The value of capacitor C f is chosen sufficiently high for the alternating part of the voltage at its terminals to be very small with respect to the signal at the terminals of winding S 1 , and so negligible.
Another secondary winding S 2 of the line transformer is connected to the input of a line saw-tooth generating circuit 4. This circuit 4 supplies from the signal available at the terminals of winding S 2 a saw-tooth signal during the outward travel of the line scan.
This saw-tooth signal is injected into an input e 1 of a cyclic ratio control circuit 3, which delivers a rectangular signal at the input of an interface circuit 10 whose output is connected to the control electrode of the active switch I S1 .
This interface circuit enables the rectangular control signal available at the output of the cyclic ratio control circuit 3 to be adapted wi
th respect to the electrical characteristics of active switch I S1 . The leading edge of the rectangular signal corresponding to the moment when active switch I S1 is closed.
Now, the position of this leading edge, and so the moment when active switch I S1 is closed, depend on the signal applied to the input e 2 of the cyclic ratio control circuit.
As was described in patent application No. 78/22266, the more active switch I S1 is triggered in advance of the moment when the line return begins, the more the average current in inductance Ls decreases with respect to its maximum value corresponding to the case when the active switch is still disabled.
It is thus possible to control the value of the average current in inductance Ls, so the value of the current in deflector Dv by controlling the moment when active switch I S1 is closed. During the outward travel of the frame scan, so that the current in vertical deflector D v follows a frame saw-tooth law, it is sufficient then to suitably control the successive moments when active switch I S1 is closed.
This suitable control will be ensured by the signal applied to the input e 2 of the cyclic ratio control circuit 3.
This signal comes, on the one hand, from a dynamic servo-control circuit 7 the input e 4 of which is connected to the terminals of measuring resistor R m and the input e 3 to a corrected saw-tooth generating circuit 5.
The voltage of the terminals of Rm depends on the current flowing through vertical deflector D v . The servo-control circuit 7 supplies then an error signal depending on the difference between the vertical deflection current and the corrected saw-tooth voltage.
A frame-separator circuit 9 receives at its input E the complete synchronizing signals taken from the video signal, and after integration and clipping delivers a frame-synchronization signal.
This frame-synchronization signal is applied to the input of an oscillator circuit 8. This latter drives the circuit generating the corrected saw-teeth whose form prefigures the current required in the vertical deflector coil D v . There is in general available at this level a linearity and amplitude adjustment, symbolized by the potentiometers P L and P a .
The input e 2 of cyclic ratio control circuit 3 is moreover connected to a static servo-control circuit 6 which ensures the maintenance and the monitoring of the average voltage at the terminals of connecting capacitor C L with respect to a reference defined so as to ensure correct and optimum operation of the switched-mode frame-scan circuit.
FIG. 2 shows one simple embodiment of a frame-scan control circuit in accordance with the invention. The complete synchronization signals taken from the video signal are applied to input E.
The frame-separator circuit is formed, on the one hand, from an integrator stage R S1 , C S1 and R S2 mounted in T and, on the other hand, a transistor T S1 biased by resistors R S3 and R S4 .
The input E is effected on a terminal of resistor R S1 , and the base of transistor T S1 is connected to a terminal of resistor R S2 .
Resistors R S3 and R S4 cause emitter biasing creating the threshold for triggering transistor T S1 .
When the synchronization signal applied to input E characterizes the frame-synchronization signal, transistor T S1 passes from a disabled state to a saturated state.
The collector of transistor T S1 is connected through a resistor R S5 to the input of an oscillator circuit.
This oscillator circuit comprises two transistors T O1 and T O2 operating simultaneously in disabled or saturated states.
When these two transistors T O1 and T O2 are saturated (frame return), with the collector-emitter voltage practically zero, the voltage V O1 at the terminals of resistor R O1 is small. The current then flowing through resistors R O7 , R O6 , R O4 connected in the emitter circuit of transistor T O2 , must then be insufficient to maintain the saturated state of the two transistors T O1 , T O2 . Thus, when capacitors C O1 and C O2 are sufficiently discharged, transistors T O1 and T O2 are disabled. Voltage V O1 passes then suddenly from a low value to a higher value, this value being imposed by the divider bridge formed by resistors R O1 and R O2 .
Resistors R O7 and R O6 ensure the charging of capacitors C O1 and C O2 until the moment when transistor T O2 becomes saturated again.
The frequency of the oscillator thus obtained, if resistor R S5 is disconnected, is slightly less than the frame frequency, i.e. 50 Hz.
At the moment of the frame-synchronization signal, with transistor T S1 becoming saturated and transistors T O1 and T O2 being disabled, voltage V O1 drops to assume a value depending on resistor R S5 . For transistors T O1 and T O2 to pass to the saturated state, voltage V O2 at the terminals of series capacitors C O1 and C O2 must at this same moment become greater than the voltage V O1 at the terminals of resistor R O1 . The saturation pulse delivered by the collector of transistor T S1 will only be taken into account for a certain part of the period of the oscillator corresponding to the end of charging of capacitors C O1 and C O2 , i.e. when the charging voltage is greater than voltage V O1 .
This enables the immunity of the oscillator to be improved in part with respect to the parasite pulses causing saturation of transistor T S1 .
This oscillator circuit is connected to a buffer circuit comprising transistor T t1 , resistor R t1 and potentiometer P t1 .
The voltage V O2 at the terminals of capacitors C O1 and C O2 varies in accordance with an approximate saw-tooth law.
Since the resistance of resistor R O7 is very high, transistor T t1 whose base is connected to the junction point of the two resistors R O7 and R O6 , forms an impedance-lowering stage, so as to connect between the emitter of transistor T t1 and the common connection point of capacitors C O1 and C O2 , the network comprising a resistor R t1 in series with a potentiometer P t1 .
Thus there is added to the saw-tooth voltage available at the terminals of series capacitors C O1 and C O2 , a parabolic voltage due to P t1 , P t1 and to capacitor C O2 .
Thus there is obtained at V t2 between the emitter of transistor T t1 and ground a voltage in the form of saw-teeth corrected to an S corresponding to the law of the current required in frame deflector D v .
Thus there is obtained at output V t1 the corrected saw-tooth signal required for the dynamic servo-control circuit of the invention which will be described further on.
The cyclic ratio control circuit of the invention only comprises a single active stage, the switching-biased transistor T c1 .
This transistor T c1 has its base connected to a circuit for generating line saw-teeth from the line return signal.
In fact, the circuit formed by capacitor C c2 in series with resistor R c2 and capacitor C c1 forms an integrator transforming the line-scan return voltage V c1 , shown in FIG. 3a, taken from the winding S 2 of line transformer T L , into a triangular signal.
This triangular signal available between the base and the emitter of transistor T c1 is shown in FIG. 3b.
The collector of transistor T c1 is connected through an interface circuit (R f1 ; R f2 , C f2 ) for matching to the gate of a thyristor TH 1 forming with diode D f1 and resistor R f3 in series with capacitor C f3 , the active switch I S1 .
In fact, in accordance with FIG. 1, the vertical deflector formed from inductance L v and series resistor R v , protected by resistor R p , is connected in series with the connecting capacitor C L and measuring resistor R m .
The load thus formed is c
onnected in parallel with the saw-tooth signal generator comprising capacitor C f connected in parallel with the inductance, the unit formed from inductance L S in series with winding S 1 of line transformer T L and the active switch TH 1 , D f1 , C f3 and R 3 . The cathode of diode D f1 is connected to the anode of thyristor TH 1 and to a terminal of winding S 1 . The anode of this diode D f1 is connected to the cathode of the thyristor and to a terminal of capacitor C f .
This thyristor TH 1 operates as a switch, when its gate current is sufficient for it to be conducting, it short-circuits diode D f1 .
This active switch is bidirectional in current and monodirectional in voltage, for in fact when it is closed, it may have flowing therethrough currents in opposite directions and when it is open it has at its terminals a voltage of given polarity corresponding to the inverse voltage of diode D f1 .
The form of the current in the vertical deflector is linked to the moment when this active switch is closed such as this is described in patent application No. 78/22266 filed in the name of the applicant.
The dynamic servo-control circuit is formed by resistor R a2 one terminal of which is connected to resistor R m and the other to resistor R a1 in series with potentiometer P a1 , capacitor C a1 and transistor T a1 .
Potentiometer P a1 receives at one of its terminals the corrected saw-tooth signal available at the emitter of T t1 .
The emitter of transistor T a1 is connected to ground and its collector to the base of transistor T c1 through a resistor R c1 .
The direction of the current in the frame deflector is such that, during the outward travel of the frame scan, the voltage at the terminals of measuring resistor R m is in phase opposition with the corrected saw-tooth voltage V t1 . The corrected saw-tooth voltage is then compared with the voltage at the terminals of measuring resistor R m by the resistor bridge R a2 , R a1 , P a1 .
Transistor T a1 amplifies the possible dynamic error signal between the voltage at the terminals of resistor R m and the correct saw-tooth voltage.
Since the voltage at the terminals of R m depends on the current flowing through the vertical deflector, the error signal depends then on the difference between the vertical deflection current and the corrected saw-tooth voltage.
This error signal is then found again in the collector circuit of transistor T a1 .
Moreover, the static servo-control is obtained by resistors R a4 , R a3 and the same transistor T a1 .
The reference voltage is the base voltage threshold of transistor T a1 fixed by resistor R a3 .
The base of transistor T a1 is connected through a resistor R a4 to the positive terminal of the electrochemical capacitor C L . If the average voltage at the terminals of capacitor C L tends to increase, the base current of transistor T a1 increases and so its collector current as well.
This increase of the collector current causes an increase of the duration in the saturated state of transistor T c1 of the cyclic ratio control circuit and an advance in the triggering of thyristor TH 1 causing thereby a reduction in the mean voltage of capacitor C L .
In fact, in the absence of a collector current of transistor T a1 , capacitors C c1 and C c2 take on a mean charge sufficient to maintain transistor T c1 disabled. And when a DC current appears in the collector circuit of transistor T a1 , the combination of this current with that due to the line saw-tooth generating circuit (C c2 , R c2 , C c1 ) causes the saturating of transistor T c1 during the end of the outward travel of the line scan.
There is then obtained at the collector of transistor T c1 a square-wave signal such as shown in FIG. 3c.
The conduction time of transistor T c1 , i.e. the time T c of FIG. 3c, depends on the collector current of transistor T a1 , which modifies the form of the base-emitter control voltage of transistor T c1 such as shown in FIG. 3b.
The moment when TH 1 begins to close corresponds to the leading edge of the square-wave signal available at the collector output of transistor T c1 .
Furthermore, resistor R c1 serves to limit the collector current of transistor T a1 and the base current of transistor T c1 when transistor T a1 tends to be saturated in the case of accidental phenomena.
The gain of the transistor is chosen so that, during the outward travel of the frame scan, the variation of the base voltage of T a1 is negligible with respect to the corrected saw-tooth alternating voltage and the voltage at the terminals of resistor R m . The alternating current flowing through capacitor C a1 is then small with respect to the current flowing through the resistor bridge P a1 +R a1 , R a2 . The law of variation of the voltage at the terminals of resistor R m is then the same as the corrected saw-tooth voltage except for the sign since they are in phase opposition.
The dynamic servo-control thus achieved is such that the current flowing through the deflector is the image of the corrected saw-tooth voltage.
And furthermore, the proper operation of the output stage when switching is ensured by the previously described static servo-control.
This single-active-switch frame-scan control circuit has then the advantage of having a simplified and servo-controlled cyclic ratio control circuit.
This control circuit for switched-mode frame scanning in accordance with the invention is principally used in transistorized television receivers.
PHILIPS TDA3505 Video control combination circuit with automatic cut-off control
GENERAL DESCRIPTION
The TDA3505 and TDA3506 are monolithic integrated circuits which perform video control functions in a PAL/SECAM
decoder. The TDA3505 is for negative colour difference signals -(R-Y), -(B-Y) and the TDA3506 is for positive colour
difference signals +(R-Y), +(B-Y).
The required input signals are: luminance and colour difference (negative or positive) and a 3-level sandcastle pulse for
control purposes. Linear RGB signals can be inserted from an external source. RGB output signals are available for
driving the video output stages. The circuits provide automatic cut-off control of the picture tube.
Features
· Capacitive coupling of the colour difference and
luminance input signals with black level clamping in the
input stages
· Linear saturation control acting on the colour difference
signals
· (G-Y) and RGB matrix
· Linear transmission of inserted signals
· Equal black levels for inserted and matrixed signals
· 3 identical channels for the RGB signals
· Linear contrast and brightness controls, operating on
both the inserted and matrixed RGB signals
· Peak beam current limiting input
· Clamping, horizontal and vertical blanking of the three
input signals controlled by a 3-level sandcastle pulse
· 3 DC gain controls for the RGB output signals (white
point adjustment)
· Emitter-follower outputs for driving the RGB output
stages
· Input for automatic cut-off control with compensation for
leakage current of the picture tube
Notes
1. < 110 mA after warm-up.
2. Values are proportional to the supply voltage.
3. When V11-24 < 0,4 V during clamping time - the black levels of the inserted RGB signals are clamped on the black
levels of the internal RGB signals.
When V11-24 > 0,9 V during clamping time - the black levels of the inserted RGB signals are clamped on an internal
DC voltage (correct clamping of the external RGB signals is possible only when they are synchronous with the
sandcastle pulse).
4. When pins 21, 22 and 23 are not connected, an internal bias voltage of 5,5 V is supplied.
5. Automatic cut-off control measurement occurs in the following lines after start of the vertical blanking pulse:
line 20: measurement of leakage current (R + G + B)
line 21: measurement of red cut-off current
line 22: measurement of green cut-off current
line 23: measurement of blue cut-off current
6. Black level of the measured channel is nominal; the other two channels are blanked to ultra-black.
7. All three channels blanked to ultra-black.
The cut-off control cycle occurs when the vertical blanking part of the sandcastle pulse contains more than 3 line
pulses.
The internal blanking continues until the end of the last measured line.
The vertical blanking pulse is not allowed to contain more than 34 line pulses, otherwise another control cycle begins.
8. The sandcastle pulse is compared with three internal thresholds (proportional to VP) and the given levels separate
the various pulses.
9. Blanked to ultra-black (-25%).
10. Pulse duration ³ 3,5 ms.
TDA1950, Line Circuits for TV Receivers (18-Pin Plastic Package)
These integrated circuits are advanced versions of the well-known types TDA1940, TDA1940F, TDA1950 and TDA1950F are identical
TBA940/950, TDA9400/9500 etc. integrated line oscillator circuits.
except the following: at pin 2 the types having the suffix "F" supply ,
They comprise all stages for sync separation and line synchronisation
horizontal output pulses of longer duration compared with the basic I
in TV receivers in one single silicon chip. Due to their high degree of
types Integration, the number of external components is very small.
This integrated circuit contains the horizontal sweep generator (HO),
the amplitude filter (AS), the sync-signal separating circuit (SA) and
the frequency/phase comparator (FP). For the purpose of suppressing
noise pulses which are caused via the operating voltage during the upper
and the lower inversion point of the horizontal sweep generator (HO)
which contains a single capacitor (C) and a first threshold stage
circuit (SS1) with two fixed thresholds, there are provided a second and
a third threshold stage circuit (SS2, SS3), to the inputs of which the
sawtooth signal is applied, and with the thresholds thereof,
approximately 2 μs prior to reaching the upper or the lower peak value
of the sawtooth signal, are being passed through thereby. The output
signal of the second threshold circuit (SS2) and the output signal of
the third thresh
old
stage circuit (SS3) which is applied via the pulse shaper circuit
(IF), are superimposed linearly and, via the stopper circuit (blocking
stage) (SP) serve to control the application of the composite video
signal (BAS) to the amplitude filter (AS), or else they are applied to a
clamping circuit which serves to apply the operating points of the
amplitude filter (AS) and/or of the sync-signal separating circuit (SA)
to such a potential that these two stages, for the time duration of
these output pulses, are prevented from operating. 1. An integrated circuit for color television receivers, comprising a voltage- or current-controlled horizontal sweep generator (HO), an amplitude filter (AS), a synchronizing-signal separating circuit (SA) and a frequency/phase comparator (FP) which serves to synchronize the horizontal sweep generator (HO), with said generator being a sawtooth generator containing a single capacitor (C) and a first threshold stage circuit (SS1) having two fixed thresholds, said integrated circuit further comprising:
a second and a third threshold stage circuit (SS2, SS3) each being supplied with the sawtooth signal on the input side, comprising each time one threshold which, approximately 2μs prior to the reaching of the upper or the lower peak value of the sawtooth signal, is being passed thereby;
a pulse shaper circuit (IF) coupled to the output of said third threshold stage circuit (SS3) which pulse shaper circuit reduces the duration of the output pulse thereof to about the duration of the output pulse of said second threshold stage circuit (SS2), and
a stopper circuit (blocking stage) (SP) coupled to the outputs of both said pulse shaper circuit (IF) and said second threshold stage circuit (SS2), said stopper circuit having a signal input to which there is applied a composite video signal (BAS) and a signal output which is coupled to the input of said amplitude filter (AS).
2. The invention of claim 1 wherein the outputs of both said pulse shaper circuit (IF) and said second threshold stage circuit (SS2) are coupled to a clamping circuit which applies the operating points of said amplitude filter (AS) and said sync-separating signal (SA) to such a potential that they are prevented from operating.
3. An integrated horizontal sweep circuit comprising:
a generator for generating a sawtooth signal;
an amplitude filter having an input for receiving a composite video signal and having an output;
a sync-signal separating circuit having an input coupled to said amplitude filter output and having an output;
a frequency/phase comparator having a first input coupled to said separating circuit output,
a second input receiving said sawtooth signal and an output for controlling said generator; and
a control circuit responsive to said sawtooth signal for inhibiting said composite video signal when said sawtooth signal is within predetermined signal level ranges about the upper and lower inversion points of said sawtooth signal.
4. An integrated circuit in accordance with claim 3 wherein:
said generator comprises a capacitor, circuit means for charging and discharging said capacitor, and a first threshold circuit controlling said circuit means in response to said sawtooth signal reaching a first level corresponding to said first inversion point and a second level corresponding to said second inversion point.
5. An integrated horizontal sweep circuit comprising:
a sawtooth signal generator;
an amplitude filter having an input receiving a composite video signal and having an output;
a sync-signal separating circuit having an input coupled to said amplitude filter output and having an output;
a frequency/phase comparator having a first input coupled to said separating circuit output, a second input receiving said sawtooth signal and an output for controlling said generator; and
a control circuit responsive to said sawtooth signal for inhibiting operation of said amplitude filter and/or said sync-signal separating circuit when said sawtooth signal is within predetermined signal level ranges about the upper and lower inversion point of said sawtooth signal.
6. An integrated circuit in accordance with claim 5 wherein:
said generator comprises a capacitor, circuit means for charging and discharging said capacitor and a first threshold circuit controlling said circuit means in response to said sawtooth signal reaching a first level corresponding to said first inversion point and a second level corresponding to said second inversion point.
Description:
BACKGROUND OF THE INVENTION
The invention relates to an integrated circuit for (color) television receivers, comprising a voltage- or current-controlled horizontal-sweep generator,
an amplitude filter, a synchronizing signal separating circuit
(sync-separator) and a frequency/phase comparator which serves to
synchronize the horizontal sweep generator which is a sawtooth generator
consisting of a single capacitor and of a first threshold stage having
two fixed switching thresholds, cf. preamble of the patent claim. Such
types of integrated circuits, for example, are known from the
technical journal "Elektronik aktuell", 1976, No. 2, pp. 7 to 14 where
they are referred to as TDA 9400 and TDA 9500.
Especially on account of the fact that the amplitude filter as well as the horizontal sweep generator in the form of the aforementioned sawtooth generator, are integrated on a single semiconductor body, it is likely that noise interference pulses coming from the individual stages, and via the supply voltage line, may have a disturbing influence upon the horizontal sweep generator, i.e. upon the threshold stage thereof, in such a way that either the lower or the upper or successively both switching thresholds are exceeded before the time by the voltage at the capacitor, owing to the noise superposition, so that the generator will show to have a "wrong" frequency or phase position. This frequency/phase variation, of course, is compensated for by the circuit, with the aid of the synchronzing pulses, but only in such a way that the noise effect remains visible in the television picture.
SUMMARY OF THE INVENTION
The invention is characterized in the claim is aimed at overcoming this drawback by solving the problem of designing an integrated circuit of the type described in greater detail hereinbefore, in such a way that noise pulses acting upon the capacitor voltage or the internal reference voltages for the switching thresholds (see below) in the proximity of the two switching thresholds, are prevented from having the described disadvantageous effect. Accordingly, an advantage of the invention results directly from solving the given problem.
Other objects, features and advantages of the present invention will become more fully apparent from the following detailed description of the preferred embodiment, the appended claims and the accompanying drawing in which:
BRIEF DESCRIPTION OF THE INVENTION
The invention will now be described in greater detail with reference to the accompanying drawing. This drawing, in the form of a schematical circuit diagram, shows the construction of an integrated circuit according to the invention.
DETAILED DESCRIPTION OF THE INVENTION
The horizontal sweep generator HO comprises the capacitor C as connected to the zero point of the circuit, and which is charged and discharged via the two shown constant current sources CS1 and CS2, thus causing the intended sawtooth voltage to appear thereat. Moreover, the horizontal sweep generator HO comprises the first threshold stage circuit SS1, having an upper and a lower threshold. As soon as the capacitor voltage exceeds one of the thresholds, the first threshold stage circuit SS1 switches over to the other threshold. The two thresholds are defined by the voltage divider P as connected to the operating voltage U, and in which the corresponding threshold inputs are connected to corresponding tapping points. The output of the threshold stage circuit SS1 controls the electronic switch S, so that the constant current source CS2 as connected thereto, is either disconnected from or connected to the zero point of the circuit. Accordingly, in the disconnected state, the capacitor C is charged via the constant current source CS1 arranged in series therewith while in the connected state the capacitor C is discharged across the aforementioned constant current source CS2 arranged in parallel therewith, if, as a matter of fact, the current of the constant current source CS1 arranged in series with the capacitor C, is smaller than that of the parallel-arranged constant current source CS2.
Now, for the purpose of avoiding the aforementioned drawbacks, there is provided a second and a third threshold stage circuit SS2 and SS3, respectively, as well as the pulse shaper circuit IF. To the respective input of the two threshold stage circuits SS2, SS3, there is applied the capacitor voltage, in the form of the sawtooth signal, and these stages have a threshold voltage which, approximately 2 μs prior to the reaching of the upper or the lower peak value of the sawtooth voltage, is being passed thereby. This means to imply that the threshold voltage of the second threshold stage circuit SS2 is somewhat lower than the voltage of the upper threshold of the first threshold stage circuit SS1, and that the threshold voltage of the third threshold stage circuit SS3 is somewhat higher than the voltage of the lower threshold of the first threshold stage circuit SS1. The two thresholds of the threshold stage circuits SS2, SS3 can thus be realized in a simple way by providing further tapping points at the voltage divider P, as is shown in the accompanying drawing. Thus, the second threshold stage circuit SS2 is provided for at a voltage divider tapping point below the tapping point chosen for the upper threshold, and the tapping point for the third threshold stage circuit SS3 is provided for above the tapping point which has been chosen for the lower threshold of the first threshold stage circuit SS1.
Since, within the area of the lower inversion point of the sawtooth signal there results an excessively wide output pulse of the third threshold stage circuit SS3, the pulse shaper circuit IF is arranged subsequently thereto, for reducing the duration of the output pulse as applied to its input, to about the duration of the output pulse of the second threshold stage circuit SS2. This pulse shaper circuit IF, for example, may be realized by a monoflop, in particular by a digital monoflop (=monostable circuit).
The output pulses of the second threshold stage circuit SS2 and of the pulse shaper circuit IF are then super-positioned linearly, with this being denoted in the drawing by a simple interconnection of the two respective lines. The combined signal is applied to the input of the stopper circuit (blocking stage) SP, to the signal input of which there is fed the composite video signal BAS, and the output thereof controls both the amplitude filter AS and thesynchronizing signal separating circuit SA.
The combined signal may also be used to control a clamping circuit applying the operating points of the amplitude filter AS and/or of the sync-signal-separating circuit SA to such a potential which prevents it from operating.
If now the sawtooth signal reaches the range of its upper or its lower inversion point, the composite video signal BAS is not applied to either the amplitude filter AS or the sync-signal separating circuit SA, so that shortly before and shortly after the inversion points, signals are prevented from being processed in the two stages AS, SA. This, in turn, has the consequence that during these times noise pulses are prevented from superimposing upon the operating voltage U, so that there is also prevented an unintended triggering of the first threshold stage circuit SS1.
Moreover, it is still shown in the drawing that the amplitude filter AS, the sync-signal separating circuit SA and the frequency/phase comparator FP are arranged in series in terms of signal flow, with the latter, in addition, receiving the sawtooth signal, and with the output signal thereof acting upon the two current sources in a regulating sense. In the drawing, this is indicated by the setting arrows at the two current sources.
While the present invention has been disclosed in connection with the preferred embodiment thereof, it should be understood that there may be other embodiments which fall within the spirit and scope of the invention as defined by the following claims.
The invention relates to an integrated circuit for (color) television receivers, comprising a voltage- or current-controlled horizontal-sweep generator,
an amplitude filter, a synchronizing signal separating circuit
(sync-separator) and a frequency/phase comparator which serves to
synchronize the horizontal sweep generator which is a sawtooth generator
consisting of a single capacitor and of a first threshold stage having
two fixed switching thresholds, cf. preamble of the patent claim. Such
types of integrated circuits, for example, are known from the
technical journal "Elektronik aktuell", 1976, No. 2, pp. 7 to 14 where
they are referred to as TDA 9400 and TDA 9500. Especially on account of the fact that the amplitude filter as well as the horizontal sweep generator in the form of the aforementioned sawtooth generator, are integrated on a single semiconductor body, it is likely that noise interference pulses coming from the individual stages, and via the supply voltage line, may have a disturbing influence upon the horizontal sweep generator, i.e. upon the threshold stage thereof, in such a way that either the lower or the upper or successively both switching thresholds are exceeded before the time by the voltage at the capacitor, owing to the noise superposition, so that the generator will show to have a "wrong" frequency or phase position. This frequency/phase variation, of course, is compensated for by the circuit, with the aid of the synchronzing pulses, but only in such a way that the noise effect remains visible in the television picture.
SUMMARY OF THE INVENTION
The invention is characterized in the claim is aimed at overcoming this drawback by solving the problem of designing an integrated circuit of the type described in greater detail hereinbefore, in such a way that noise pulses acting upon the capacitor voltage or the internal reference voltages for the switching thresholds (see below) in the proximity of the two switching thresholds, are prevented from having the described disadvantageous effect. Accordingly, an advantage of the invention results directly from solving the given problem.
Other objects, features and advantages of the present invention will become more fully apparent from the following detailed description of the preferred embodiment, the appended claims and the accompanying drawing in which:
BRIEF DESCRIPTION OF THE INVENTION
The invention will now be described in greater detail with reference to the accompanying drawing. This drawing, in the form of a schematical circuit diagram, shows the construction of an integrated circuit according to the invention.
DETAILED DESCRIPTION OF THE INVENTION
The horizontal sweep generator HO comprises the capacitor C as connected to the zero point of the circuit, and which is charged and discharged via the two shown constant current sources CS1 and CS2, thus causing the intended sawtooth voltage to appear thereat. Moreover, the horizontal sweep generator HO comprises the first threshold stage circuit SS1, having an upper and a lower threshold. As soon as the capacitor voltage exceeds one of the thresholds, the first threshold stage circuit SS1 switches over to the other threshold. The two thresholds are defined by the voltage divider P as connected to the operating voltage U, and in which the corresponding threshold inputs are connected to corresponding tapping points. The output of the threshold stage circuit SS1 controls the electronic switch S, so that the constant current source CS2 as connected thereto, is either disconnected from or connected to the zero point of the circuit. Accordingly, in the disconnected state, the capacitor C is charged via the constant current source CS1 arranged in series therewith while in the connected state the capacitor C is discharged across the aforementioned constant current source CS2 arranged in parallel therewith, if, as a matter of fact, the current of the constant current source CS1 arranged in series with the capacitor C, is smaller than that of the parallel-arranged constant current source CS2.
Now, for the purpose of avoiding the aforementioned drawbacks, there is provided a second and a third threshold stage circuit SS2 and SS3, respectively, as well as the pulse shaper circuit IF. To the respective input of the two threshold stage circuits SS2, SS3, there is applied the capacitor voltage, in the form of the sawtooth signal, and these stages have a threshold voltage which, approximately 2 μs prior to the reaching of the upper or the lower peak value of the sawtooth voltage, is being passed thereby. This means to imply that the threshold voltage of the second threshold stage circuit SS2 is somewhat lower than the voltage of the upper threshold of the first threshold stage circuit SS1, and that the threshold voltage of the third threshold stage circuit SS3 is somewhat higher than the voltage of the lower threshold of the first threshold stage circuit SS1. The two thresholds of the threshold stage circuits SS2, SS3 can thus be realized in a simple way by providing further tapping points at the voltage divider P, as is shown in the accompanying drawing. Thus, the second threshold stage circuit SS2 is provided for at a voltage divider tapping point below the tapping point chosen for the upper threshold, and the tapping point for the third threshold stage circuit SS3 is provided for above the tapping point which has been chosen for the lower threshold of the first threshold stage circuit SS1.
Since, within the area of the lower inversion point of the sawtooth signal there results an excessively wide output pulse of the third threshold stage circuit SS3, the pulse shaper circuit IF is arranged subsequently thereto, for reducing the duration of the output pulse as applied to its input, to about the duration of the output pulse of the second threshold stage circuit SS2. This pulse shaper circuit IF, for example, may be realized by a monoflop, in particular by a digital monoflop (=monostable circuit).
The output pulses of the second threshold stage circuit SS2 and of the pulse shaper circuit IF are then super-positioned linearly, with this being denoted in the drawing by a simple interconnection of the two respective lines. The combined signal is applied to the input of the stopper circuit (blocking stage) SP, to the signal input of which there is fed the composite video signal BAS, and the output thereof controls both the amplitude filter AS and the
synchronizing signal separating circuit SA. The combined signal may also be used to control a clamping circuit applying the operating points of the amplitude filter AS and/or of the sync-signal-separating circuit SA to such a potential which prevents it from operating.
If now the sawtooth signal reaches the range of its upper or its lower inversion point, the composite video signal BAS is not applied to either the amplitude filter AS or the sync-signal separating circuit SA, so that shortly before and shortly after the inversion points, signals are prevented from being processed in the two stages AS, SA. This, in turn, has the consequence that during these times noise pulses are prevented from superimposing upon the operating voltage U, so that there is also prevented an unintended triggering of the first threshold stage circuit SS1.
Moreover, it is still shown in the drawing that the amplitude filter AS, the sync-signal separating circuit SA and the frequency/phase comparator FP are arranged in series in terms of signal flow, with the latter, in addition, receiving the sawtooth signal, and with the output signal thereof acting upon the two current sources in a regulating sense. In the drawing, this is indicated by the setting arrows at the two current sources.
While the present invention has been disclosed in connection with the preferred embodiment thereof, it should be understood that there may be other embodiments which fall within the spirit and scope of the invention as defined by the following claims.
THOMSON TEA5620 COLOR TV PAL DECODER
It combines all functions required for the identilication and demodulation of PAL signal USE OF A STANDARD 4.43 MHz
ACC AND IDENTIFICATION DETECTORS
Compatible to TEA5630 SECAM DECODER
NORDMENDE COLOR 3537 CHASSIS F11 (THOMSON ICC3) Receiver stage for radio or television receiver:
A receiver stage for radio or television receiver. A single case
enclosing a device comprises inside a tuner, an intermediate frequency
amplifier connected to the tuner, a demodulator connected to the
intermediate frequency amplifier, and a phase locked loop provision
connected to the tunner. The joint case allows joint shielding of all
components with shield plates mounted inside the case, avoids unreliable
plug connections and reduces the production cost of radio and
television receiver sets.
e frequency amplifier, and a phase locked loop provision
connected to the tunner. The joint case allows joint shielding of all
components with shield plates mounted inside the case, avoids unreliable
plug connections and reduces the production cost of radio and
television receiver sets.
1. A single case having first, second side walls and first, second end walls for housing the circuitry of a radio or television receiver comprising a tuner section wherein the tuner section comprises a VHF section and a UHF section which are disposed about in parallel between said first and second side walls and between an antenna input filter section and a phase locked loop section, data inputs mounted on said first side wall of the case near the phase locked loop section, the VHF section being located next to the first side wall of the case with the data inputs; the phase locked loop section being connected to the tuner section and separated from the tuner section by a first subdivision metal shielding plate;
the antenna input filter section located between an antenna input end on the first end wall of the case and the tuner section;
a second subdividing metal shielding plate for separating the tuner section from the antenna input filter section;
a third subdividing metal shielding plate attached to the first and second subdividing metal shielding plates for providing a separation between the UHF section and the VHF section;
an intermediate frequency amplifier connected to the tuner section and located between the phase locked loop section and the second end wall of the case and separated from the phase locked loop section by a fourth subdividing metal shielding plate, the first, second, third and fourth subdividing shielding plates each comprising
brackets at the top for attaching a cover plate; and,
a demodulator connected to the intermediate frequency amplifier.
2. The single case for housing the circuits of a radio or a television receiver according to claim 1 wherein the phase locked loop section co
mprises
a quartz oscillator reference source; a phase detector connected to the reference source;
a low pass filter connected to the output of the phase detector and to the tuner section;
a programmable predivider having its output connected to the phase detector and having an input connected to the tuner section;
a shift register having an output connected to the tuner and having an output connected to the programmable predivider,
wherein the phase locked loop section is disposed near the middle of the case where data inputs are disposed on the case next to the phase locked loop section.
3. The single case for housing the circuits of a radio or a television receiver according to claim 2 wherein the tuner section comprises an oscillator;
a preamplifier; and
a mixer stage connected to the preamplifier and to the oscillator and having its output connected to the intermeidate frequency amplifier; and
a band switch having inputs connected to the shift register and having outputs connected to the preamplifier and to the oscillator.
4. The single case for housing the circuits of a radio or a television receiver according to claim 1 wherein the case comprises metal as a structural element.
5. The single case for housing the circuits of a radio or a television receiver according to claim 1 wherein the case comprises plastic as a structural element.
6. The single case for housing the circuits of a radio or a television receiver according to claim 1 wherein leads between the circuits of the phase locked loop section and a tuner circuit section are at most 5 centimeters.
7. The single case for housing the circuits of a radio or a television receiver according to claim 1 wherein the leads between the circuits of the phase locked loop section and the tuner circuit section are at most 2 centimeters.
Description:
BACKGROUND OF THE INVENTION1. Field of the Invention
The present invention relates to a receiver stage for a radio or a television receiver comprising a tuner, an intermediate frequency amplifier, a demodulator and a phase locked loop circuit.
2. Brief Description of the Background of the Invention Including Prior Art
Such receivers are provided with a tuner for selecting the different emitter frequencies of the radio and television station signals. These antenna signals fed to the tuner are transformed in the tuner by mixing with an oscillator frequen
cy to an intermediate frequency. The intermediate
frequency signals taken from the tuner are amplified in a following
intermediate frequency amplifier. A demodulator following to the
intermediate frequency amplifier demodulates the high frequency
modulated signal to an audio frequency sound signal or respectively to a
video frequency picture signal, which is fed to the final stages for
reproduction in a loudspeaker or respectively on the screen of a
television set. The individual electronic components such as tuner,
intermediate frequency amplifier and demodulator have been
conventionally disposed in separate component parts and were connected
to each other via lines. These lines have to be shielded and are
expensive for this reason. The required plug connections are susceptible
to disturbances and form the sources of interferences, which can pass
from the outside into the receiver station. Therefore, it has been
taught to gather these named device units in a case. Thus there results
an optimal shielding and the elimination of long connecting lines
subject to the influence of disturbances (German Patent Laid Out DE-AS
No. 1,958,993). Receiver stations of more recent technology comprise capacitor diodes in the tuning circuits. The tuning voltage required for tuning is generated in this case with the aid of a phase locked loop circuit. This phase locked loop circuit provides a D.C. voltage, which results depending on a preselectable divider ratio of a frequency divider of the phase locked loop circuit. The phase locked loop circuit serving tuning purposes is disposed in a separate device component part. This arrangement with separation from the tuner unit however again results in the disadvantage, that interfering pulses can pass to the lines for the data input of the phase locked loop circuit as well as to the tuning voltage carrying line to the tuner unit, which can interfere with the tuning.
SUMMARY OF THE INVENTION
1. Purposes of the Invention
It is an object of the present invention to eliminate a possibility of disturbances from radio or television receiver apparatus.
It is another object of the present invention to provide a compact device comprising major elements employed in tuning of a radio or television receiver.
It is a further object of the invention to simplify the assembly and servicing of radio and television sets.
These and other objects and advantages of the present invention will become evident from the description which follows.
2. Brief Description of the Invention
The present invention provides a receiver stage for a radio or a television receiver wherein a single case encloses a device which comprises a tuner, an intermediate frequency amplifier connected to the tuner, a demodulator connected to the intermediate frequency amplifier, and a phase locked loop provision connected to the tuner.
The phase locked loop can comprise a reference source, a phase detector connected to the reference source, a low pass filter connected to the output of the phase detector and to the tuner, and a programmable divider having its output connected to the phase detector and having an input connected to the tuner. The phase locked loop can comprise a shift register having an output connected to the programmable predivider. The tuner can comprise an oscillator, a preamplifier and a mixer stage connected to the preamplifier and to the oscillator and having its output connected to the intermediate frequency amplifier. The tuner can comprise a band switch having inputs connected to the shift register and having outputs connected to the preamplifier and to the oscillator.
The case can be comprised of metal and/or plastic as a structural element. The connecting leads between the phase locked amplifier and the tuner can be not more than 5 centimeters and are preferably less than 2 centimeters.
A shielding metal plate can be disposed between the tuner section and the phase locked loop provision area and between the phase locked loop provision area and the intermediate frequency amplifier and automatic gain control area. In addition, a separating shielding metal plate can be disposed between an antenna input filter section and the tuner. Furthermore, a metal shielding plate can be disposed between an UHF area and a VHF area of the tuner, where this plate is attached to the plate separating the antenna input filter section from the tuner and to the metal plate separating the tuner and the phase locked loop provision area.
The novel features which are considered as characteristic for the invention are set forth in particular in the appended claims. The invention itself, however, both as to its construction and its method of operation, together with additional objects and advantages thereof, will be best understood from the following description of specific embodiments when read in connection with the accompanying drawing.
BRIEF DESCRIPTION OF THE DRAWING
In the accompanying drawing in which is shown one of the various possible embodiments of the present invention:
FIG. 1 is a view of a schematic diagram showing the construction according to the invention,
FIG. 2 is a perspective view of the construction according to the invention .
Corresponding numerals in the Figs. designate corresponding items and features.
DESCRIPTION OF INVENTION AND PREFERRED EMBODIMENTS
The signals received by the antenna 1 are amplified in a conventional way in a preamplifier 2. The preamplifier is disposed in the tuner area 26 of the receiver. The output of the preamplifier 2 together with the frequency obtained from an oscillator is mixed to an intermediate frequency in the mixing stage 3. The oscillations are amplified in the intermediate amplifier 5 and are demodulated with the aid of the demodulator 6 and the output signal FBAS of the demodulator 6 can be picked up at the connection 7. The components intermediate amplifier 5 and demodulator 6 form part of an intermediate amplifier and automatic gain control section 24. The recited stages are provided in a case and in a single shielding container possibly of the kind described in the German Patent Laid Out DE-AS No. 1,958,993.
In accordance with the teaching of the invention the device components for the phase locked loop (PLL) circuit 22 including programmable predivider 8, reference source 9, phase detector stage 10 and low pass filter 1 are integrated in the same case 12 for generating the tuning voltage. The reference source can be provided by a voltage controlled or by a current controlled oscillator. The output of the input unit 13 is connected to a shift register 14. The shift register 14 is connected to the band switch 15 and to the predivider 8. The data determined for the selected channel can be entered via an input unit 13 connected from the outside to the case 12. These data can set the predivider
8 as well as the
bandswitch 15. After the input of the data via the data line 16 as well
as via the clock input C1 and the enable input EN these can be
disconnected such that also disturbing pulses cannot any longer
influence the phase locked loop circuit. The elementary devices employed
in the circuits of the present invention are preferably provided by
large scale integrated circuits or very large scale integrated circuits.
The case for the composite device can be constructed in a similar way
as the case taught in German Patent Laid Out DE-AS No. 1,958,993. The
leads between the phase locked loop and the tuning circuit can be quite
small, that is less than about 5 centimeters and preferably less than
about 2 centimeters.
The invention provides advantages by way of the construction layout. By the elimination of a separate PLLunit, the tuner receiver part can form a compact unit from the antenna input to the demodulator output including the electronic components required for the tuning and the band switching.
It will be understood that each of the elements described above, or two or more together, may also find a useful application in other types of receiver station system configurations and received signal processing procedures differing from the types described above.
While the invention has been illustrated and described as embodied in the context of a receiver for a radio or a television receiver, it is not intended to be limited to the details shown, since various modifications and structural changes may be made without departing in any way from the spirit of the present invention.
Without further analysis, the foregoing will so fully reveal the gist of the present invention that others can, by applying current knowledge, readily adapt it for various applications without omitting features that, from the standpoint of prior art, fairly constitute essential characteristics of the generic or specific aspects of this invention.
NORDMENDE COLOR 3537 CHASSIS F11 (THOMSON ICC3) PLL MICROCOMPUTER Frequency synthesizer tuning system for television receivers:
" A method for tuning a television receiver having automatic frequency control to the carrier frequency of a selected broadcast channel with an associated channel number including generating a variable frequency signal by means of a local oscillator, generating a reference frequency signal by means of a reference oscillator, and generating a local oscillator correction signal for matching an intermediate frequency signal derived from said local oscillator signal and the carrier frequency signal with a predetermined nominal intermediate frequency signal, said method being characterized by the use of a microcomputer and comprising:
generating binary signals representing first and second digital tune words, said digital tune words representing a selected channel;
storing said first and second digital tune words in a first data memory in said microcomputer;
reading said first and second digital tune words from said first memory and generating a divided-down local oscillator frequency by the use of said first digital tune word and a divided-down reference oscillator frequency by the use of said second digital tune word;
comparing said divided-down local oscillator and reference frequencies and generating a control signal representative of the difference in frequency of said divided-down local oscillator and reference frequencies;
coupling said control signal to said local oscillator for causing it to be locked to the frequency of said received carrier signal;
mixing the local oscillator frequency signal and the carrier frequency signal to generate an intermediate frequency signal;
comparing said intermediate frequency signal with said predetermined nominal intermediate frequency signal and providing a tuning voltage to said microcomputer, said tuning voltage being indicative of the magnitude and direction of a tuning error between said intermediate frequency signal and said predetermined nominal intermediate frequency signal;
incrementally adjusting the reference oscillator frequency by means of a tuning signal provided to said reference oscillator by said microcomputer in response to said tuning voltage;
detecting when the incrementally changing, divided-down reference oscillator frequency causes the intermediate frequency signal to pass said predetermined nominal intermediate frequency signal; and
incrementally stepping the divided-down reference oscillator frequency back a predetermined number of steps following the passage of said predetermined nominal intermediate frequency signal by said intermediate frequency signal in tuning said television receiver to the selected channel.
"
A
television tuning system employs a frequency synthesizer system for
establishing the tuning of the receiver. A programmable frequency
divider counter is connected between the output of a reference
oscillator and a phase comparator to which the output of the local
oscillator in the tuner also is applied. The phase comparator output
provides a tuning voltage for controlling the tuning of the local
oscillator. A microprocessor is used to control the count of the
programmable frequency divider and initially to set a count
corresponding to the selected channel in a counter connected between the
output of the local oscillator and the phase comparator. The tuning
consists of three discrete time periods. First, a settling time to
allow channel change transients to settle; second, a short period of
forced search at a relatively rapid rate to insure proper tuning; and
third, a slower rate of step-by-step correction to accomodate for
station drift and the like during reception. This third time period is
initiated either by the passage of a fixed length of time following
the start of the forced search period or by sensing a preestablished
number of changes of state in the output of the frequency
discriminator during the forced/search period.
1. A tuning system for the tuner of a television receiver capable of receiving a composite television signal and including frequency discriminator (AFT) circuit means, said system including in combination:
a reference oscillator providing a reference signal at a predetermined frequency;
a local oscillator in the tuner providing a variable output frequency in response to the application of a control signal thereto;
a programmable frequency divider means having first and second inputs coupled respectively to the output of said reference oscillator and said local oscillator for producing signals on first and second outputs having frequencies which are a programmable fraction of the frequency of the signals applied to the inputs thereto;
phase comparator means having one input coupled with the first output of said programmable frequency divider means and having another input coupled with the second output of said programmable frequency divider means for developing a control signal and applying such control signal to said local oscillator for controlling the output frequency thereof;
counter circuit means coupled with said programmable frequency divider means for initially setting said divider means to a predetermined division ratio and operating to change the programmable fraction of division thereof in accordance with changes in the count in said counter circuit means;
control circuit means coupled with the output of said frequency discriminator means and further coupled with said counter circuit means for causing said counter circuit means to count at a first rate in a predetermined direction determined by the state of the output signal from said discriminator means in the absence of a predetermined signal output from said frequency discriminator means until a predetermined maximum count is attained, thereupon resetting said counter circuit means to a count which is a predetermined amount less than said maximum predetermined count and continuing to count at said first rate in the same predetermined direction from said new count to continuously change the programmable fraction of said frequency divider means in accordance with the state of operation of said counter circuit means, said control means operating in response to said predetermined signal output from the frequency discriminator means for terminating operation of said counter circuit means; and
further means for terminating operation of said counter circuit means at said first rate and causing operation thereof at a second slower rate.
2. The combination according to claim 1 wherein said further means includes timing means initiated into operation simultaneously with the setting of said divider means to a predetermined division ratio, and after a predetermined time interval said timing means producing an output signal applied to said counter circuit means to cause operation thereof to take place at said second slower rate. 3. The combination according to claim 1 wherein said counter circuit means includes a reversible digital counter coupled with said programmable frequency divider, means and said control circuit means causes said counter circuit means to count in said predetermined direction when the output of said frequency discriminator is of a first state and to count in the opposite direction when the output of said frequency discriminator is of second state; and said further means comprises means coupled with the output of said frequency discriminator and with said counter circuit means to take place at said second slower rate in response to a predetermined number of changes of state of frequency discriminator. 4. The combination according to claim 3 further including means responsive to the selection of a new channel in said television receiver for resetting said further means to an initial condition of operation. 5. The combination according to claim 4 wherein said further means comprises a search termination counter means operative to provide an output signal applied to said counter circuit means in response to a count thereby of a predetermined number of changes of state of said frequency discriminator to cause said counter circuit means to be operated at said second slower rate.
" A method for tuning a television receiver having automatic frequency control to the carrier frequency of a selected broadcast channel with an associated channel number including generating a variable frequency signal by means of a local oscillator, generating a reference frequency signal by means of a reference oscillator, and generating a local oscillator correction signal for matching an intermediate frequency signal derived from said local oscillator signal and the carrier frequency signal with a predetermined nominal intermediate frequency signal, said method being characterized by the use of a microcomputer and comprising:
generating binary signals representing first and second digital tune words, said digital tune words representing a selected channel;
storing said first and second digital tune words in a first data memory in said microcomputer;
reading said first and second digital tune words from said first memory and generating a divided-down local oscillator frequency by the use of said first digital tune word and a divided-down reference oscillator frequency by the use of said second digital tune word;
comparing said divided-down local oscillator and reference frequencies and generating a control signal representative of the difference in frequency of said divided-down local oscillator and reference frequencies;
coupling said control signal to said local oscillator for causing it to be locked to the frequency of said received carrier signal;
mixing the local oscillator frequency signal and the carrier frequency signal to generate an intermediate frequency signal;
comparing said intermediate frequency signal with said predetermined nominal intermediate frequency signal and providing a tuning voltage to said microcomputer, said tuning voltage being indicative of the magnitude and direction of a tuning error between said intermediate frequency signal and said predetermined nominal intermediate frequency signal;
incrementally adjusting the reference oscillator frequency by means of a tuning signal provided to said reference oscillator by said microcomputer in response to said tuning voltage;
detecting when the incrementally changing, divided-down reference oscillator frequency causes the intermediate frequency signal to pass said predetermined nominal intermediate frequency signal; and
incrementally stepping the divided-down reference oscillator frequency back a predetermined number of steps following the passage of said predetermined nominal intermediate frequency signal by said intermediate frequency signal in tuning said television receiver to the selected channel.
"
A
television tuning system employs a frequency synthesizer system for
establishing the tuning of the receiver. A programmable frequency
divider counter is connected between the output of a reference
oscillator and a phase comparator to which the output of the local
oscillator in the tuner also is applied. The phase comparator output
provides a tuning voltage for controlling the tuning of the local
oscillator. A microprocessor is used to control the count of the
programmable frequency divider and initially to set a count
corresponding to the selected channel in a counter connected between the
output of the local oscillator and the phase comparator. The tuning
consists of three discrete time periods. First, a settling time to
allow channel change transients to settle; second, a short period of
forced search at a relatively rapid rate to insure proper tuning; and
third, a slower rate of step-by-step correction to accomodate for
station drift and the like during reception. This third time period is
initiated either by the passage of a fixed length of time following
the start of the forced search period or by sensing a preestablished
number of changes of state in the output of the frequency
discriminator during the forced/search period.
1. A tuning system for the tuner of a television receiver capable of receiving a composite television signal and including frequency discriminator (AFT) circuit means, said system including in combination:
a reference oscillator providing a reference signal at a predetermined frequency;
a local oscillator in the tuner providing a variable output frequency in response to the application of a control signal thereto;
a programmable frequency divider means having first and second inputs coupled respectively to the output of said reference oscillator and said local oscillator for producing signals on first and second outputs having frequencies which are a programmable fraction of the frequency of the signals applied to the inputs thereto;
phase comparator means having one input coupled with the first output of said programmable frequency divider means and having another input coupled with the second output of said programmable frequency divider means for developing a control signal and applying such control signal to said local oscillator for controlling the output frequency thereof;
counter circuit means coupled with said programmable frequency divider means for initially setting said divider means to a predetermined division ratio and operating to change the programmable fraction of division thereof in accordance with changes in the count in said counter circuit means;
control circuit means coupled with the output of said frequency discriminator means and further coupled with said counter circuit means for causing said counter circuit means to count at a first rate in a predetermined direction determined by the state of the output signal from said discriminator means in the absence of a predetermined signal output from said frequency discriminator means until a predetermined maximum count is attained, thereupon resetting said counter circuit means to a count which is a predetermined amount less than said maximum predetermined count and continuing to count at said first rate in the same predetermined direction from said new count to continuously change the programmable fraction of said frequency divider means in accordance with the state of operation of said counter circuit means, said control means operating in response to said predetermined signal output from the frequency discriminator means for terminating operation of said counter circuit means; and
further means for terminating operation of said counter circuit means at said first rate and causing operation thereof at a second slower rate.
2. The combination according to claim 1 wherein said further means includes timing means initiated into operation simultaneously with the setting of said divider means to a predetermined division ratio, and after a predetermined time interval said timing means producing an output signal applied to said counter circuit means to cause operation thereof to take place at said second slower rate. 3. The combination according to claim 1 wherein said counter circuit means includes a reversible digital counter coupled with said programmable frequency divider, means and said control circuit means causes said counter circuit means to count in said predetermined direction when the output of said frequency discriminator is of a first state and to count in the opposite direction when the output of said frequency discriminator is of second state; and said further means comprises means coupled with the output of said frequency discriminator and with said counter circuit means to take place at said second slower rate in response to a predetermined number of changes of state of frequency discriminator. 4. The combination according to claim 3 further including means responsive to the selection of a new channel in said television receiver for resetting said further means to an initial condition of operation. 5. The combination according to claim 4 wherein said further means comprises a search termination counter means operative to provide an output signal applied to said counter circuit means in response to a count thereby of a predetermined number of changes of state of said frequency discriminator to cause said counter circuit means to be operated at said second slower rate.
Description:
BACKGROUND OF THE INVENTION
Both
of the above mentioned patents are directed to frequency synthesizer
tuning systems for use with television receivers to enable operation
of the receivers with minimal viewer fine tuning adjustments. By the
utilization of the frequency synthesizer tuning systems of these
patents, the fine tuning adjustment which is necessary with conventional
types of television receiver tuning systems has been substantially
eliminated. The system employed in the '953 patent permits utilization
of a frequency synthesizer tuning system which correctly tunes to a
desired television station or channel even if the transmitted signals
from that station are not precisely maintained at the proper
frequencies. The '535 patent is directed to a signal seek tuning system
adaptation of the frequency synthesizer tuning system of the '953
patent which still permits implementation of all of the desired
wide-band pull in range of the frequency synthesizer system of the '953
patent.
The systems of the foregoing patents operate effectively to correct automatically for frequency offsets in a frequency synthesizer tuning system without affecting the operation of the conventional frequency synthesizer used in the system. The systems of these patents are in widespread use commercially and permit direct selection, with automatic fine tuning adjustment, of any desired VHF channel which the viewer wishes to observe. In addition, the signal seek adaptation disclosed in the '535 patent couples all of the advantages of the frequency synthesizer tuning system of the '953 patent with the desirability of providing bidirectional signal seek operation.
While the systems disclosed in the foregoing patents operate in a highly satisfactory manner to accomplish the desired results of accurate tuning without the necessity of fine tuning adjustments, the circuitry for accomplishing the desired results is somewhat complex. It is desirable to reduce the circuit complexity and the number of signal detectors for accomplishing these results without compromising the accuracy of operation of the system.
SUMMARY OF THE INVENTION
Accordingly, it is an object of this invention to provide an improved tuning system for a television receiver.
It is an additional object of this invention to provide an improved frequency synthesizer tuning system for a television receiver.
It is another object of this invention to provide an improved frequency synthesizer tuning system for a television receiver which includes a provision for adjusting the synthesizer loop for frequency offsets in the received signal with a minimum number of signal detectors.
It is a further object of this invention to tune the local RF oscillator of a television receiver to the correct frequency for a selected channel with a frequency synthesizer tuning system, and automatically to change the reference frequency of the synthesizer system, or adjust the count of a programmable divider that produces a signal that divides the frequency of the local oscillator of the tuner, if the AFT signal produced by the AFT frequency discriminator of the receiver is outside a predetermined range corresponding to correct tuning.
It is still another object of this invention to provide an improved frequency synthesizer tuning system for a television receiver which operates to adjust the synthesizer loop for frequency offsets in the received signal over a relatively wide pull in range in response to the output of the receiver frequency discriminator by changing the division ratio of a programmable frequency divider in the reference oscillator leg or local oscillator leg of the synthesizer loop at a first relatively high rate from an initial nominal value to a pre-established maximum in one direction, and then resetting the division ratio to a second nominal value once the maximum is reached and continuing to incrementally change the division ratio in the same direction from the second nominal value until a properly tuned condition is indicated by the output of the receiver AFT frequency discriminator, followed by control at a lower rate of operation to maintain tuning during transmitting station drifts.
In accordance with a preferred embodiment of this invention, the frequency synthesizer tuning system for a television receiver includes a stable reference oscillator and a voltage controlled local oscillator in the tuner. A programmable frequency divider is connected between the output of the reference oscillator and one input to a phase comparator, the other input of which is supplied by the output of the local oscillator. The output of the phase comparator then comprises a control signal which is supplied to the local oscillator to control the frequency of its operation.
A counter circuit is connected to the programmable frequency divider for initially setting the divider to a predetermined division ratio upon selection of a desired channel by the viewer. The counter then operates to change the programmable fraction of the division ratio at a first relatively high rate in a direction controlled by the output from the receiver picture carrier discriminator in the absence of a predetermined signal output derived from the discriminator. A control means causes the counter circuit to count in this direction until it is determined that a station is tuned or a predetermined maximum count is attained if no station is correctly tuned, thereupon resetting the counter circuit to a count which is a predetermined amount less than the maximum predetermined count. Counting is continued in the same predetermined direction from the new lesser count to continuously change the programmable fraction of the frequency divider in accordance with the state of operation of the counter.
The
high rate operation of the counter is terminated by the control
means in response to a predetermined signal from the output of the
discriminator, indicating that a station is correctly tuned, or after a
fixed time-out interval; so that the system automatically adjusts
for frequency offsets of the received signal which otherwise would
cause the station to be mistuned if a conventional frequency
synthesizer tuning system were used. After termination of the high
rate operation of the counter, it is switched to a lower rate
operation for maintaining tuning during transmitting station drifts.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a block diagram of a television receiver employing a preferred embodiment of the invention;
FIG. 2 is a detailed block diagram of a portion of the circuit of the preferred embodiment shown in FIG. 1;
FIG. 3 is a detailed circuit diagram of a portion of a circuit shown in FIG. 1;
FIG. 4 is a flow chart of the control sequence of operation of the circuit shown in FIG. 1 and 2; and
FIG. 5 shows a waveform and time/frequency chart, respectively, useful in explaining the operation of the circuit shown in FIGS. 1, 2 and 3.
DETAILED DESCRIPTION
Referring now to the drawings, the same reference numbers are used throughout the several figures to designate the same or similar components.
FIG. 1 is a block diagram of a television receiver, which may be a black and white or color television receiver. Mo
st
of the circuitry of this receiver is conventional, and for that
reason it has not been shown in FIG. 1. Added to the conventional
television receiver circuitry of FIG. 1, however, is a frequency
synthesizer tuning system, in accordance with a preferred embodiment
of the invention, which is capable of automatically changing the
reference frequency when a frequency offset exists in the received
signal for a particular channel.
Transmitted composite television signals, either received over the air or distributed by means of a master antenna TV distribution system, are received by an antenna 10 or on antenna input terminals to the receiver. As is well known, these composite signals include picture and sound carrier components and synchronizing signal components, with the composite signal applied to an RF and tuner stage 11 of the receiver. The stage 11 includes the conventional RF amplifiers and tuner sections of the receiver, including a VHF oscillator section and a UHF oscillator section. Preferably, the UHF and VHF oscillators are voltage controlled oscillators, the freuency of operation of which are varied in response to a tuning voltage applied to them to effect the desired tuning of the receiver.
The output of the RF and tuner stages 11 is applied to the remainder of the television receiver 14, which includes the IF amplifier stages for supplying conventional picture (video) and sound IF signals to the video and sound processing stages of the receiver 14. The circuitry of the receiver 14 may be of any conventional type used to separate, amplify and otherwise process the signals for application to a cathode ray tube 16 and to a loudspeaker 17 which reproduce the picture and sound components, respectively, of the received signal.
The
receiver 14 also includes a conventional AFT or automatic fine
tuning discriminator circuit and additionally may include a synch
separator circuit for producing an output in response to the presence
of vertical synchronizatin pulses, a picture carrier detection
circuit, and an automatic gain control (AGC) amplifier. Outputs
representative of these sensor components are shown as being coupled
over a group of lead 20 to sensory circuitry 22, which in turn
couples outputs representative of the operation of these various
sensor circuits to a microprocessor unit 23 for controlling the
operation of the microprocessor unit.
The microprocessor unit 23 is utilized in the system of FIG. 1 for controlling the operation of a frequency synthesizer tuning system capable of automatic offset correction. When the viewer desires to select a new channel, he enters the desired channel number into a channel selection keyboard 25. There are a number of different keyboards which may be employed to accomplish this function, and the particular design is not important to this invention. The channel selector keyboard 25 also may include switches or keys for initiating a signal seek function in either the "up" or "down" direction.
Information represented by the selection of channel numbers on the keyboard 25 is supplied to the microprocessor unit 23 which provides output signals over a corresponding set of leads 27 to the tuners (local oscillators) 11 to effect the appropriate band switching control for the tuners 11 in accordance with the particular channel which has been selected. In addition, the keyboard 25, operating through the microprocessor unit 23, provides output signals which operate a channel number display 29 to provide an appropriate display of the selected channel number to the viewer.
The microprocessor M3870 unit 23 also processes the signals which are used to operate the channel number display 29 through a multiplexing circuit operation to decode the selected channel number into a parallel encoded signal. This signal is applied to corresponding inputs of the count-down counter or programmable frequency divider 31 to cause the division number of the divider 31 to relate to the divided down frequency of the tuner local oscillators connected to the input of the divider 31 through a prescaler divider circuit 32 to the frequency of the reference oscillator 34. Thus, the division number or division ratio of the local oscillator frequency obtained from the output of the programmable divider 31 is appropriately related to the frequency of the reference crystal oscillator 34.
The output of the oscillator 34 also is applied through a countdown circuit or programmable frequency divider 35. Conventional frequency synthesizer techniques are employed; and the microprocessor unit 23 automatically compensates, through appropriate code converter circuitry, for the non-uniform channel spacing of the television signals. It has been found most convenient to cause the programmable frequency divider 31 to divide by numbers corresponding directly to the oscillator frequency of the selected channel, for example, 101, 107, 113 . . . up to 931.
In accordance with the time division multiplex operation of the microprocessor 23, the count of the programmable frequency divider 35 initially is adjusted to a fixed count by the application of appropriate output signals from the microprocessor unit 23 to a point selected to be at or near the mid-point of the operating range of the programmable frequency divider 35. Thus, the output of the divider 35 is a stable reference frequency (because the input is from the reference crystal oscillator 34) which is used to establish initially and to maintain tuning of the receiver to the selected channel.
The output of the programmable divider 35 is applied to one of two inputs of a phase comparator circuit 37. The other input to the phase comparator circuit 37 is supplied from the selected one of the VHF or UHF oscillators in the tuner stages 11 through the programmable frequency divider 31. The phase comparator circuit 37 operates in a conventional manner to supply a DC tuning control signal through a phase locked loop filter circuit 39 and over a lead 40 to the oscillators in the tuner system 11 to change and maintain their operating frequency.
With the exception of the use of the microprocessor unit 23, the operation of the system which has been described thus far is that of a relatively conventional frequency synthesizer system incorporated into a television receiver. This system is similar to the system of the '953 patent. As in the system of that patent, the system shown in FIG. 1, when the transmitted station or station received on a master antenna distribution system provides the station or channel signals at the proper frequency, operates as a relatively conventional frequency synthesizer system. If, however, there is a frequency offset in the received signal to cause the carrier of the received signal to be displaced from the frequency which it should have to some other frequency, it is possible that the system would give the appearance of mistuning to the received station. The microprocessor 23, operating in conjunction with the sensory circuitry 22, is employed in conjunction with the countdown or programmable frequency divider circuit 35 to eliminate this disadvantage and still retain the advantages of frequency synthesizer tuning.
Reference now should be made to FIG. 2 which shows details of t
he
interface between the keyboard 25, the microprocessor unit 23, and
the circuitry used in the frequency synthesizer portions of the
system. A commercially available microprocessor which has been used
for the microprocessor 23, and which forms the basis for the
diagramatic representation of the microprocessor in FIG. 2, is the
Matsushita Electronics Corporation MN1402 four-bit single-chip
microcomputer. This microcomputer has two, four-bit parallel input
ports labeled "A" and "B". In addition, three output ports, a five-bit
output port "C" and two four-bit output ports "D" and "E" are
provided. The internal configuration of the microcomputer 23 includes
an arithmetic logic unit (ALU), a read only memory (ROM) for storing
instructions and constants, and a random access memory (RAM) used for
data memory, arranged into four files, each file containing 16
four-bit words. These words are selected by X and Y registers and this
memory is used, for example, for timers, counters, etc., and also is
used to hold intermediate results. To facilitate an understanding of
the operation of the system, a portion of this memory is shown in
FIG. 2 as a clock 81 and a reversible counter 82 connected between
the "B" input port and the "D" output port. The microcomputer 23 is
programmed to permit it to operate in conjunction with the remainder
of the circuits shown in FIG. 2. The programming techniques are
standard, and the microcomputer 23 itself is a standard commercially
available circuit component.
There are several system parameters that must be selected in the operation of the system shown in FIG. 2. The selection of the nominal frequency of the two signals that feed the phase comparator circuit 37 is an example. Channel selection is provided by changing the frequency division ratio of the selector counter 31 which divides the local oscillator signal after this signal is passed through a prescaler circuit 32 and a divide-by-two divider circuit 41. The nominal frequency from the programmable frequency divider 31 (selector counter) is selected so that the local oscillator (tuner) 11 can be set exactly on frequency for all channels.
Since the frequency divider 31 is able to divide only by integer numbers, one distinct frequency possibility in the range of one KHz is obtained, another in the range of two KHz, etc. A choice must be made as to which of these values is optimum. Each value yields the nominal frequency of all of the 82 channels by simply multiplying by an appropriate integer for each channel. To simplify the phase locked loop filtering problem by the filter 39, it is desirable that the frequencies of the signals supplied to the phase comparator 37 are as high as possible. This permits rapid acquisition of a new channel along with a very clean DC control signal to adjust the local oscillator. A trade-off for this, however, must be made to permit fine tunning adjustment of the local oscillator automatically to correctly tune in stations which are off their assigned frequency, or to manually provide this feature, if desired. The two-speed operation of the system in accordance with the present invention allows a better trade-off to be made by allowing rapid acquisition and then a slower speed for precise tuning.
A compromise solution which is utilized in the circuit of FIG. 2 is to cause the frequency division chain from the local oscillator 11 in the tuner to the phase comparator 37 to be composed of the fixed divide-by-256 prescaler 32, and a fixed divide-by-4 division, which is accomplished by the divider 41 at the input of the counter 31 and a second divider 42 at the output of the counter 31. The variable frequency divider counter 31 then is loaded by means of three latch circuits 44, 45 and 46 at an appropriate time by the time division multiplex operation of the microcomputer 23 and a number that programs the programmable frequency divider counter 31 to divide by the numerical value of the frequency of the local oscillator in MHz for the channel selected. For example, if the receiver is to be tuned to channel 2, which has a nominal local oscillator frequency of 101 MHz, the programmable frequency divider 31 is set to divide by 101. If the receiver is to be tuned to channel 83, which has a nominal local oscillator frequency of 931 MHz, the programmable frequency divider 31 is set to divide by 931. In both cases, the variable divider 31 produces a 1 MHz signal. However, because of the fixed divide-by-256 and the two fixed divide-by-two dividers in series with the programmable divider 31, an output frequency of 976.5625 Hz is supplied from the output of the divider 42 to the upper input of the phase comparator 37.
The division ratio of the selector counter 31 is established by appropriate output signals from the latch circuits 44, 45 and 46, as mentioned above. The initial operation for changing, or maintaining, the division ratio of the divider 31 is established by an entry of the two digits of the selected channel number in the keyboard 25. The microcomputer 23 operates as a time division multiplex system for continuously monitoring the input ports and the output ports to control the operation of the remainder of the system. The selection of the two digits of the desired channel number is affected by a time division multiplex iscanning of the outputs of the D output port of microcomputer 23 and providing that information at the A input port. From here the information is translated again to the D output ports to the appropriate drivers of the channel number display circuit 29 and to the latches 44, 45 and 46, and to a pair of similar four bit latches 49 and 50 which control the divider ratio of the counter 35.
Although the D output ports of the microcomputer 23 are connected in common to all of these various portions of the circuit, the selection of which of the latches are enabled to respond to the particular output signals appearing on the D output ports at any given time is effected through the C and E output ports of the microcomputer 23 in a time division multiplex fashion. A decoder circuit 52, connected to the lowermost three outputs of the E output port of the microcomputer 23, is used to apply unique decoding signals at different times in the time division multiplex sequence of operation of the microcomputer 23 to the five latch circuits 44, 45, 46, 49 and 50, respectively. At any given time in the sequence, only one of these latch circuits is enabled for operation. A latch load signal is applied from the upper output (EO3) at each cycle of operation of the signals appearing on the E output port to set the latch circuit which is enabled by the output of the decoding circuit 52 with the data appearing on the other inputs to the latch circuit. This data simultaneously appears on the four outputs of the D output port of the microcomputer 23.
Thus, in rapid sequence, the latch circuits 44, 45 and 46 are set to store the division number corresponding to the selected channel entered onto the keyboard 25, and the latch circuits 49 and 50 are each operated to set the programmable divider reference counter 35 to a center or nominal count, which is always the same upon the selection of a new channel on the keyboard 25. Similarly, the two right-hand outputs of the C output port (CO6 and CO5) enter the two digits of the selected channel number in the drivers of the display circuit 29 at the proper time in the binary encoded sequence when these digits appear on the four-bit binary encoded representation of the D output port. This results in a visual display of the channel number selected.
In addition to the selection of a channel number directly by the keyboard 25, the keyboard also may include an additional switch 56, which is scanned in the time division multiplex sequence to determine if the receiver is placed in a "seek" mode of operation (when the signal seek capability is incorporated into such a receiver). Operating in conjunction with the signal seek switch 56 are a pair of "up" and "down" seek direction input switches shown with a graphic representation of the seek directions on the keyboard 25. A further provision is provided by two keys labeled "U" and "D", which are used for "manual" fine tuning of the receiver in the "up" or "down" directions depending upon which of the two keys U or D has been operated. The keyboard 25 includes one additional switch 58 which may be used to disable the automatic fine tuning (AFT) portion of the circuit by rendering the microcomputer insensitive to the signal output from the AFT circuit, in a manner described more fully subsequently.
As is apparent from the foregoing, the
microcomputer 23 provides the intelligence, decision making, and
control for the system operation. It is a complete self contained
computer. The decisions or signal inputs upon which the microcomputer
23 bases its operation include, in addition to the inputs from the
keyboard 25, inputs on sensory inputs into the B input port and into
the SNS1 and SNS0 inputs as shown in FIG. 2. These input signals are
used to provide an indication to the microcomputer 23 of the presence
or absence of a received signal; and if the presence of such a
signal is indicated, the inputs provide a further indication of the
accuracy of the tuning of the receiver to that signal. If the system
is being operated solely in a manual mode of operation (AFT switch 58
open), the microcomputer 23 disregards all of this sensory information
and tunes to the frequency allocation of the channel selected in the
manner described above. The system will stay tuned to this
condition, operating as a conventional frequency synthesizer, whether
or not a station is present in the received signal.
When the system is placed in its automatic mode of operation (similar to the mode of operation of the above mentioned '953 patent), the counter 82, integrally formed as part of the microcomputer 23, continuously adds or subtracts one number at a time from the nominal value or programmable division fraction entered into the programmable frequency divider 35 at the outset of each new channel number selection when frequency offset (mistuning) is present. The counter 82 is driven at a relatively high counting rate by clock pulses from the clock 81 during this initial or forced search mode of operation. Thus, automatic offset correction is provided for any channel which is off its assigned frequency. The offset correction automatically adjusts the frequency of the local oscillator by changing the division ratio of the signal from the reference oscillator 35 applied to the lower input of the phase comparator 37. By doing this, the output of the phase comparator 37 applied to the local oscillator 11 varies to cause the oscillator to be tuned in the proper direction to compensate for the transmitting station mistuning.
When the system is operating in its automatic mode of operation, the microcomputer 23 responds to the sensor information applied to it on its B input ports and on the S1 input port shown in FIG. 2. These inputs are obtained from the various outputs of the operational amplifiers shown connected to the corresponding input ports in the detailed circuit of FIG. 3. Depending upon whether the receiver is provided with a signal seek feature or not, one or more of the sensory inputs of the circuit of FIG. 3 are used. The s
ystem
shown in the drawings has a capability of correcting for frequency
offsets larger than 1.5 MHz on channels 2 and 7 and approximately 2
MHz on channels 6 and 13. The remainder of the channels have a range
between these two values.
If the receiver is not tuned properly, the micromputer 23 executes the localized search of the tuning range mentioned above. Since there is a necessary settling down time for the tuning of a television receiver immediately following selection of a new channel, a time interval of 250 milliseconds has been selected to prevent any localized search or offset frequency correction until the expiration of this "settling down" time period. If, at the end of this 250 millisecond time interval, a properly tuned station is present, this is indicated by the sensory outputs from the television receiver and no localized search is effected to change the division ratio or programmable divider count in the reference counter 35 for a system that also has signal seek.
A system with no signal seek capability is described later that requires less sensory input but which uses a time period where a forced search is required directly after the settling time interval.
Upon termination of the 250 millisecond settling down period, the microcomputer 23 is rendered responsive to the sensory input signals on its sensory input signal ports. In the simplest form, only the output of the frequency discriminator 60 (FIG. 3) applied to three comparators 61, 62 and 63 is used to provide the necessary tuning information to the microcomputer 23. The outputs of these comparators are applied to the B12 and B11 inputs of the microcomputer.
The
comparator 61 simply is a conventional comparator for determining
whether or not the output of the frequency discriminator is positive
or negative, as indicated in the upper waveform of FIG. 5. The
comparators 62 and 63 are each adjusted with appropriate reference
input levels to provide a narrow window centered about the center
tuning frequency (fc) of the receiver. If the tuning of the receiver,
as indicated by the output of the frequency discriminator 60, is
outside this window on either side of the central axis shown in FIG.
5, one output condition is indicated on the input terminal B11 of the
microcomputer. Only when the tuning frequency is within the tuning
window, indicative of a properly tuned receiver, is the appropriate
input applied to the microcomputer input terminal B11. This input
overrides any other input that may be present on the input terminal
B12 and is indicative of a properly tuned receiver. The input from the
frequency discriminator 60, as applied to the microcomputer on its
input port B12, is used to determine the direction of operation of the
counter 82 of the microcomputer for the localized search count
signals applied to the latch circuits 49 and 50 to change the count of
the reference programmable divider counter 35 on a step-by-step
basis.
The lower graph of FIG. 5 plots the relative frequency of the local oscillator 11 to the received signal frequency with respect to time. The various arrows are used to indicate the manner of operation of the counter 82 in the microcomputer 23 in conjunction with the reference counter 35 for adjusting for any mistuning conditions which may exist after the initial station selection has been effected in the manner described above.
If the receiver is properly tuned, the outputs from the comparators 62 and 63 of FIG. 3 which are combined together and applied to the input port B11 of the microcomputer 23, provide an indication that the tuning is within the properly tuned center frequency window. As a consequence, no further operation of the microcomputer to change any of the outputs applied to the latch circuits 49 and 50 for the duration of this condition is effected. On the other hand, if the receiver is mistuned on either side of the proper tuning frequency, the various operating characteristics shown in FIG. 5 are effected.
Assume initially that the receiver is capable of making tuning adjustments over a range of fc plus Δf to fc minus Δf, as indicated in the top waveform of FIG. 5. Three specific examples of mistuning will then be considered. Initially, assume that the local oscillator is mistuned relative to the received signal to a frequency f1 as shown in the lower graph of FIG. 5. In this condition, the outout of the frequency discriminator 60 is positive since this signal frequency lies to the lefthand side of the center or properly tuned region of operation of the discriminator. Under this condition of the operation, the input signal applied to the sensor port B12 of the microcomputer 23 is such that the microcomputer counter 82 is caused to advance in a positive direction to change the programmable division ratio or count of the reference counter 35 in a manner to force the output of the phase comparator 37 to adjust the frequency of the local oscillator until the proper tuning indicated at point B in the lower graph of FIG. 5 is reached. The time interval for accomplishing this result is measured from the upper end of the arrow representative of the frequency f1 to the point B.
Now assume that the receiver mistuning is to a frequency f2 which as shown in FIG. 5 as located on the righthand-side of the center axis fc. In this condition, the discriminator output is negative. This is reflected in the output of the comparator 61 applied to the input port B12 of the microcomputer 23. The polarity of this signal is identified by the microcomputer 23 to cause the counter 82 in it to operate in the reverse direction. As this count is applied on a step-by-step basis through the latch circuits 49 and 50 to the reference counter 35, the division ratio or count of the reference counter (divider) 35 is changed. As a result, the reference oscillator signal applied to the phase comparator 37 causes the phase comparator 37 output to drive the local oscillator frequency in a direction opposite to that considered in the first example. This is shown by the vector interconnecting the top of the arrow representative of f2 to point A on the time/frequency graph of FIG. 5.
As discussed in the general discussion above, whenever the tuning frequency reaches the narrow window on either side of fc, the outputs of the comparators 62 and 63 provide the necessary indication on the sensory input port terminal B11 to cause termination of the operation of the counter 82 in the microcomputer 23. Then the reference counter 35 remains set to the count attained just prior to the appearance of this input signal on the input port B11 of the microcomputer 23.
A third mistuning condition can exist, and ordinarily this condition results in an ambiguity which cannot be corrected simply by responding to the signal polarity at the output of the frequency discriminator. This is indicated by the mistuned condition where the difference between the local oscillator frequency f3 and the transmitter frequency is such that the signal f3 lies in the range to the right of the negative portion of the discriminator output shown in the upper waveform of FIG. 5. In this condition, the associated sound causes the discriminator output to be positive; so that the television receiver normally would attempt to tune toward the next adjacent channel and away from the properly tuned center frequency of the channel which is desired. The output of the discriminator 60 in this situation is the same as it was in th
e
first example considered for frequency f1; so that the counter 82 of
the microprocessor 23 operates to change the count in the reference
counter 35 in a manner to cause the local oscillator frequency to go
higher toward a frequency f3 +Δf, as shown in FIG. 5.
A predetermined number of counts of the counter 82 in the microcomputer 23 are necessary for the microcomputer to count through the frequency range Δf, and this range is selected to be within the pull in or operating range of the system. Once this count has been attained, the microcomputer counter 82 immediately is reset back to a count which corresponds to a frequency 2 Δf lower than the frequency attained by the maximum count. This is indicated in FIG. 5 by the frequency f3-Δf. Because the microcomputer counter 82 is limited to counting a number of counts equal to Δf, this new frequency now is on the lefthand side of the center line fc, shown in both waveforms of FIG. 5. This places the local oscillator frequency at a point such that the frequency discriminator output is the positive output shown on the lefthand-side of the upper waveform of FIG. 5. Counting continues in the same direction as previously. This time, however, it is in a proper direction to bring about correct tuning; and when the center frequency is reached, the output of the comparators 62 and 63 cause the microcomputer 23 to stop its count. The proper tuning point attained is indicated at point C on the graph of the lower part of FIG. 5.
Because the counter 82 of the microcomputer is limited to a maximum count equivalent to Δf above its initial count and thereupon is reset to a new count equivalent to 2 Δf lower than the maximum count, it is not necessary to utilize any other sensory inputs in order to properly tune the receiver over a wide pull in range (as much as plus or minus 2 MHz). Only the output of the conventional frequency discriminator 60 is used to provide the necessary sensory inputs.
The
counter 82 of the microcomputer 23 is operated by the clock 81
during the foregoing sequence of operation, immediately following the
selection of a new channel by the operation of the keyboard 25, at a
fast or high speed operation. Typically, the counter steps are 10
milliseconds per step; so that there are no initial visual effects
which can be noticed by an observer of the television screen of the
receiver being tuned. The maximum forced search period is
approximately 900 milliseconds in duration. At the end of this time
interval, a timer in the microcomputer 23 causes a signal to be
applied through the outputs of the E output port to the decoder
circuit 52 indicative of the completion of this time interval. The
decoder 52 then applies a pulse on an output lead connected to the B13
input of the B input port of the microcomputer 23. This pulse is
sensed by the microcomputer 23 and is applied to the clock 81 to
change the clock rate to a much slower rate, approximately one-third
(1/3) or one-fourth (1/4) the rate used previously during the forced
search mode of operation. This then permits the system to accomodate
station drifts which normally occur at a very slow rate during the
transmission and reception of a television signal. As a consequence,
it is possible to use more filtering in the filter 39 on the tuning
line (FIG. 1) and employ a smaller frequency window for the channel
verification sensed by the circuitry shown in FIG. 3. The result is a
more precise tuning from the receiver than is otherwise possible if
only a high speed operation of the clock 81 is utilized.
When the channel once again is changed by operation of the keys in the keyboard 25 or operation of the channel selection circuitry from a remote control unit, this new channel input is sensed by the microcomputer 23 from the signals applied to the A input port and the clock 81 is reset to its fast time or the forced search mode of operation; and the process resumes.
Instead of employing an additional decoding function in the decoder 52, a separate decoder also could be connected to the outputs of the D output ports to feed back the signal to the B13 input terminal of the B input port of the microcomputer 23. The operation of the system to change the rate or frequency of the pulses applied by the clock 81 to the counter 82 otherwise is the same as described above.
Although applicant has found that it is preferable to correct for mistuning or frequency offsets by adjusting the count or division ratio of the counter 35, such offset adjustments also could be effected by adjusting the count in the counter 31 in the local oscillator signal line. The operation in such a case is the same as described above for adjusting the count in the counter 35.
If the receiver is to be used with an automatic signal seek mode of operation, however, additional sensory inputs are necessary. These inputs operate in conjunction with the output of the frequency discriminator 60. The operation of the microcomputer 23 in controlling the count of the reference programmable frequency counter divider 35 is the same as described
above. The additional sensory inputs simply are used in conjunction
with the outputs of the comparators 62 and 63 to signal the
microcomputer 23 to assure that tuning is to a picture channel rather
than an adjacent sound channel. This is accomplished by utilizing
the output of the synchronizing signal separator 65 which is applied
to a comparator 67 to produce an output signal to the SNS1 sensory
input of the microcomputer 23 only when vertical synchronizing signal
components are present.
In addition, the output of a picture carrier detector 69 is applied to the input of a comparator 70 to produce an output to the B10 sensory input of the microcomputer 23. If the picture carrier detector 69 is producing an output indicative of the presence of a carrier, but no output is being obtained from the vertical synch separator 65 at the same time, the system is mistuned to a sound carrier and the microcomputer 23 is permitted to continue its localized search until a properly tuned station is found. Only when there is coincidence of signals from the picture carrier detector 69, the synch signal separator 65, and the automatic frequency discriminator window as determined by the comparators 62 and 63, is the microcomputer operation terminated to indicate that a properly tuned channel is present.
Further insurance of tuning the receiver only to a strong signal also can be provided by the addition of an AGC amplifier 72. This is connected to a comparator 74 coupled to the B10 input port along with the output of the picture carrier detector comparator 70. When the AGC amplifier 72 is used as a sensory input, the microcomputer operation, when the system is used in a signal seek mode, is only terminated to indicate reception of a valid signal when that signal is strong enough to produce the desired output from the comparator 74. The signal level which is acceptable is set by a potentiometer 75.
It should be noted that when the system is operated in a signal seek mode, the sensory inputs must indicate the reception of a properly tuned signal within a pre-established time period. If no signal is sensed by the various sensory input circuits operating in conjunction with one another as described above, the microcomputer 23 automatically steps to the next channel number and repeats the sequence of operation described above. This is when it is placed in its signal seek mode of operation. If signal seek is not employed, the additional sensory circuits 65, 69 and 72 are not necessary, and the inputs to the microcomputer which are provided from these sensory circuits are not utilized. The sensory signal input which is used both for a receiver without a signal seek capability of operation and for a receiver which has a signal seek mode of operation in it, is the output of the frequency discriminator 60 operating in conjunction with the comparators 61, 62 and 63 as described above.
As indicated above, the wideband method of tuning precisely to an incoming signal that is at the wrong frequency described here only needs the frequency discriminator sensory information. The method that uses the additional sensors described above is needed to make this system operate compatibly with signal seek but it is not restricted to seek operation.
For
a system that does not use signal seek operation, only the frequency
discriminator sensory input is required for proper operation. The
discriminator 60 is used for both fine tuning direction information and
to produce a frequency window to indicate the presence of a
correctly tuned station (channel verification). Initially, after a
channel change, there is a 250 millisecond settling time, the same as
the operation described above with compatible seek. After that,
however, comes a period of time where a forced localized search is
produced by the microcomputer 23. The forced search is needed to
insure that the system will correctly tune to stations that initially
may be tuned to the undesired zero voltage crossover in the right
half of the upper curve of FIG. 5. Such signals may be within the
frequency window of the discriminator 60; and if a search is not
forced, this system will not correctly tune. The compatible seek
system described previously correctly tunes the local oscillator
without a forced search, because the picture carrier detector and
vertical detector do not give an output for this situation and the
system automatically goes into its search mode of operation. However,
the non-seek system does not have a picture carrier sensor input and
must be forced to search for an initial period of time sufficient to
allow the system to tune up to its maximum frequency and then reset
(loop) back to a frequency of 2 Δf lower. Then it is tuned to the
positive left half portion of the discriminator curve (FIG. 5) and
the frequency window created by the discriminator 60 is sufficient to
insure proper tuning. If the discriminator output produced by the
desired incoming signal created an initial situation that produces
the correct tuning direction information, i.e., in the left half of
the curve of FIG. 5, or in the right half portion that gives the
correct direction and
frequency
window information, the forced search would not be needed. However,
the forced search will produce a correct tuning situation anyway. In
these cases, the tuning either is correct to begin with or correct
tuning is reached quickly. Then, even though the forced search is
active, it simply alternates up and down through the correct tuning
point because each time the receiver is tuned a little high in
frequency, it produces a negative output from the discriminator 60;
and the tuning direction signal causes the system to tune down in
frequency.
Then,
a positive discriminator output is produced, and the system tunes up
in frequency. This continues until the forced search is removed by
time-out of the microcomputer 23 (a fraction of a second). At such
time, the receiver is correctly tuned by the frequency window of the
discriminator to be very near fc. The system cannot tune to the
undesired discriminator crossover shown in the right half portion of
FIG. 5 because the polarity of the tuning direction signal always
causes it to tune away from that point.
The fast time or forced search operation of the system can be terminated in a different way other than the preestablished time-out period described above in conjunction with the operation of the circuit shown in FIG. 2. Generally, it is desirable to build into the system (or program into the system by means of software) such a maximum time-out period to effect the operation which has been described above to terminate the search and cause the clock 81 thereafter to operate in a low speed mode of operation. Termination also can be accomplished by sensing the number of changes in the direction sensor input applied to the B12 terminal of the B input port to cause the search to be terminated when this direction changes three times (or more). By doing this, any flicker that might be observed on the screen of the television receiver is minimized, since the forced search still takes place at the high rate of application of clock pulses from the clock 81 to the counter 82 in the same manner described above.
Termination of the search, however, also may be effected by means of a search terminate counter 78 (FIG. 3), which is advanced by pulses applied to it each time the output of the comparator 61 changes its sign (indicative of a change in direction for the counter 82) as applied to it through the B12 input port, as described earlier. After three of these changes, or some other number if desired, an output pulse is obtained from the search terminate counter 78 and is applied to the SNS0 input of the microcomputer 23. This causes the operation of the clock 81 to be switched to its low speed mode of operation to terminate the fast or "forced search" mode of operation. The next time a new channel number is entered on the keyboard 25, a reset pulse is applied to the search terminate counter 78 to reset it to its original or zero count, thereby readying it for another sequence of operation. It is apparent that the search terminate counter 78 may not always be operated to terminate the count, since the time-out interval which is sensed by the decode circuit 52 and applied to the B13 input port of the microcomputer 23 may occur before there are three changes of direction of the search. In any event, the next time a new channel number is entered into the keyboard 25, the search terminate counter 78 is reset; so that it is irrelevant whether this counter reaches a full count or not to effect the termination of the forced search operation of the system.
FIG. 4 shows the control sequence of the system which is stored in the ROM (Read Only Memory) of the microcomputer 23. The microcomputer 23 operates by always running through the flow sequence, via loops L1, L2 and L3. Loop L1 corresponds to a new channel selection by two digit number entry. Loop L2 corresponds to channel number increment or decrement by an up or down key operation, respectively, or by seek operation. Loop L3 corresponds to fine tuning, either manual or automatic. To obtain exact timing for system control, the microcomputer 23 receives a standard timing pulse from the output of the reference counter 35 divided in a divide-by-five counter 80 and applied to the A13 input port of the microcomputer 23. The control functions which are programmed into the microcomputer 23, as indicated in the flow chart of FIG. 4, are outlined in the following paragraphs.
Channel Number Correction: An invalid two digit channel number entry (0, 1, 84, 99) is corrected. When the operation of the receiver is in the signal seek mode, the next channel up from 83 is channel 2, and the next lower channel from channel 2 is 83.
PLL Control I: For a
given channel number, a corresponding binary code for the PLL selector
counter 31 is derived as described previously. For UHF channels, the
local oscillator frequency separation between two adjacent channels
is 6 MHz and the code for PLL is generated by the microcomputer 23
through means of a simple calculation. This code then is transferred
from the microcomputer 23 to the latches 44, 45 and 46 as described
previously.
PLL Control II: This routine of the microcomputer 23 is used to transfer the fine tuning data to the latches 49 and 50 which control the count of the reference counter 35 in the PLL circuit.
Channel Number Display: The channel number is transferred from the microcomputer 23 to the driver latches of the display driver circuit 29.
Key Input Detection: The keyboard is arranged as the matrix circuit shown in FIG. 2. ROM programming for scanning and acknowledging a keyboard entry only after successive indications provides protection against false entry due to contact bounce. The four data output lines of the D output port of the microcomputer 23 are used to transfer data to the phase lock loop section of the circuit and to the display circuit 29, as well as for scanning the keyboard matrix circuit.
Time Count: The microcomputer 23 receives a basic timing pulse of approximately 200 Hz from the output of the divider 80 and performs various controls for each timing pulse. By way of example, sensing for the vertical synch input (when the system is used with a signal seek capability) on the input port SNS1 takes place every 2.5 milliseconds. Automatic seek timing is selected to be 133 milliseconds for UHF channels. All of these timing pulses are derived from the basic synchronization timing pulse applied to the microcomputer on the A13 input port from the output of the divider 80. Various other timing values used in the microcomputer to properly time multiplex sequence the operation are derived from this basic timing pulse.
Sensor Input Detection: As described previously, the output of the comparators shown in FIG. 3 reflect the status of the tuning of the television receiver. If no signal seek mode of operation is used, only the frequency discriminator or AFT discriminator 60 is necessary. When a system is being used in a signal seek mode, a proper television signal receipt is indicated by the presence of a vertical synch signal at the output of the synch signal separator 65 and corresponding outputs are applied to the input leads B10 and B11 (high level input signals) indicative of tuning to the "correct tuned" frequency discriminator window and reception of a picture carrier. As stated previously, the signal present on the B12 input lead is used to determine the direction of tuning when the receiver is operated in its automatic mode.
Mode Detection: The status of the seek and automatic/manual (A/M) switches are detected. If the A/M switch (not shown) is in its automatic position, automatic seek and offset correction are active. If only the seek switch is on, only seek is performed. If the A/M switch is in manual, manual fine tuning (MFT) is active.
Automatic Mode: If the TV receiver is not properly tuned for VHF channels in automatic, the local oscillator frequency is shifted automatically toward proper tuning. The fine tuning data is generated in the microcomputer 23 and is transferred to the latches 49 and 50 for the reference counter 35 in the PLL circuit.
Manual Fine Tuning (MFT) Control: The local oscillator frequency is shifted by pushing the fine tuning up (U) or down (D) pushbutton or switch. This MFT control can be applied to VHF channels as well as to UHF channels.
Channel Up/Down: When a channel up (upward pointing arrow) or down (downward pointing arrow) key closure in the keyboard 25 is detected, or upon a direct access to an unused channel, this routine is activated and the system will advance to the next channel in the selected direction.
The foregoing embodiment of the invention which has been described above and which is illustrated in the drawings is to be considered illustrative of the invention, which is not limited to the specific embodiment selected for this purpose. For example, hard-wired logic could be used to achieve the various circuit operations which are accomplished by the microcomputer 23 in conjunction with the other portions of the system. The relative ease of programming and debugging the microcomputer 23, however, make it much simpler to implement the system operation with the microcomputer than with hard-wired logic. With respect to the sensor circuit inputs to the system, an added degree of operating assurance can be provided by the addition of a sound carrier sensor in addition to the picture carrier sensor shown in FIG. 3. If this feature is desired, the output of the comparator for the sound carrier is combined with the outputs of the comparators 70 and 74 at the input terminal B10 of the B input port of the microcomputer 23. Because of the manner of the circut operation which has been described previously, however, the addition of a sound carrier detector to the system is not considered necessary, even for a system operating in the signal seek mode of operation. This is in contrast to conventional television receivers having a signal seek operation, in which detection of the sound carrier generally is a necessity to insure that mistuning of the receiver to an adjacent sound carrier does not take place.
Both
of the above mentioned patents are directed to frequency synthesizer
tuning systems for use with television receivers to enable operation
of the receivers with minimal viewer fine tuning adjustments. By the
utilization of the frequency synthesizer tuning systems of these
patents, the fine tuning adjustment which is necessary with conventional
types of television receiver tuning systems has been substantially
eliminated. The system employed in the '953 patent permits utilization
of a frequency synthesizer tuning system which correctly tunes to a
desired television station or channel even if the transmitted signals
from that station are not precisely maintained at the proper
frequencies. The '535 patent is directed to a signal seek tuning system
adaptation of the frequency synthesizer tuning system of the '953
patent which still permits implementation of all of the desired
wide-band pull in range of the frequency synthesizer system of the '953
patent.
The systems of the foregoing patents operate effectively to correct automatically for frequency offsets in a frequency synthesizer tuning system without affecting the operation of the conventional frequency synthesizer used in the system. The systems of these patents are in widespread use commercially and permit direct selection, with automatic fine tuning adjustment, of any desired VHF channel which the viewer wishes to observe. In addition, the signal seek adaptation disclosed in the '535 patent couples all of the advantages of the frequency synthesizer tuning system of the '953 patent with the desirability of providing bidirectional signal seek operation.
While the systems disclosed in the foregoing patents operate in a highly satisfactory manner to accomplish the desired results of accurate tuning without the necessity of fine tuning adjustments, the circuitry for accomplishing the desired results is somewhat complex. It is desirable to reduce the circuit complexity and the number of signal detectors for accomplishing these results without compromising the accuracy of operation of the system.
SUMMARY OF THE INVENTION
Accordingly, it is an object of this invention to provide an improved tuning system for a television receiver.
It is an additional object of this invention to provide an improved frequency synthesizer tuning system for a television receiver.
It is another object of this invention to provide an improved frequency synthesizer tuning system for a television receiver which includes a provision for adjusting the synthesizer loop for frequency offsets in the received signal with a minimum number of signal detectors.
It is a further object of this invention to tune the local RF oscillator of a television receiver to the correct frequency for a selected channel with a frequency synthesizer tuning system, and automatically to change the reference frequency of the synthesizer system, or adjust the count of a programmable divider that produces a signal that divides the frequency of the local oscillator of the tuner, if the AFT signal produced by the AFT frequency discriminator of the receiver is outside a predetermined range corresponding to correct tuning.
It is still another object of this invention to provide an improved frequency synthesizer tuning system for a television receiver which operates to adjust the synthesizer loop for frequency offsets in the received signal over a relatively wide pull in range in response to the output of the receiver frequency discriminator by changing the division ratio of a programmable frequency divider in the reference oscillator leg or local oscillator leg of the synthesizer loop at a first relatively high rate from an initial nominal value to a pre-established maximum in one direction, and then resetting the division ratio to a second nominal value once the maximum is reached and continuing to incrementally change the division ratio in the same direction from the second nominal value until a properly tuned condition is indicated by the output of the receiver AFT frequency discriminator, followed by control at a lower rate of operation to maintain tuning during transmitting station drifts.
In accordance with a preferred embodiment of this invention, the frequency synthesizer tuning system for a television receiver includes a stable reference oscillator and a voltage controlled local oscillator in the tuner. A programmable frequency divider is connected between the output of the reference oscillator and one input to a phase comparator, the other input of which is supplied by the output of the local oscillator. The output of the phase comparator then comprises a control signal which is supplied to the local oscillator to control the frequency of its operation.
A counter circuit is connected to the programmable frequency divider for initially setting the divider to a predetermined division ratio upon selection of a desired channel by the viewer. The counter then operates to change the programmable fraction of the division ratio at a first relatively high rate in a direction controlled by the output from the receiver picture carrier discriminator in the absence of a predetermined signal output derived from the discriminator. A control means causes the counter circuit to count in this direction until it is determined that a station is tuned or a predetermined maximum count is attained if no station is correctly tuned, thereupon resetting the counter circuit to a count which is a predetermined amount less than the maximum predetermined count. Counting is continued in the same predetermined direction from the new lesser count to continuously change the programmable fraction of the frequency divider in accordance with the state of operation of the counter.
matically adjusts
for frequency offsets of the received signal which otherwise would
cause the station to be mistuned if a conventional frequency
synthesizer tuning system were used. After termination of the high
rate operation of the counter, it is switched to a lower rate
operation for maintaining tuning during transmitting station drifts.BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a block diagram of a television receiver employing a preferred embodiment of the invention;
FIG. 2 is a detailed block diagram of a portion of the circuit of the preferred embodiment shown in FIG. 1;
FIG. 3 is a detailed circuit diagram of a portion of a circuit shown in FIG. 1;
FIG. 4 is a flow chart of the control sequence of operation of the circuit shown in FIG. 1 and 2; and
FIG. 5 shows a waveform and time/frequency chart, respectively, useful in explaining the operation of the circuit shown in FIGS. 1, 2 and 3.
DETAILED DESCRIPTION
Referring now to the drawings, the same reference numbers are used throughout the several figures to designate the same or similar components.
FIG. 1 is a block diagram of a television receiver, which may be a black and white or color television receiver. Mo
st
of the circuitry of this receiver is conventional, and for that
reason it has not been shown in FIG. 1. Added to the conventional
television receiver circuitry of FIG. 1, however, is a frequency
synthesizer tuning system, in accordance with a preferred embodiment
of the invention, which is capable of automatically changing the
reference frequency when a frequency offset exists in the received
signal for a particular channel.Transmitted composite television signals, either received over the air or distributed by means of a master antenna TV distribution system, are received by an antenna 10 or on antenna input terminals to the receiver. As is well known, these composite signals include picture and sound carrier components and synchronizing signal components, with the composite signal applied to an RF and tuner stage 11 of the receiver. The stage 11 includes the conventional RF amplifiers and tuner sections of the receiver, including a VHF oscillator section and a UHF oscillator section. Preferably, the UHF and VHF oscillators are voltage controlled oscillators, the freuency of operation of which are varied in response to a tuning voltage applied to them to effect the desired tuning of the receiver.
The output of the RF and tuner stages 11 is applied to the remainder of the television receiver 14, which includes the IF amplifier stages for supplying conventional picture (video) and sound IF signals to the video and sound processing stages of the receiver 14. The circuitry of the receiver 14 may be of any conventional type used to separate, amplify and otherwise process the signals for application to a cathode ray tube 16 and to a loudspeaker 17 which reproduce the picture and sound components, respectively, of the received signal.
The
receiver 14 also includes a conventional AFT or automatic fine
tuning discriminator circuit and additionally may include a synch
separator circuit for producing an output in response to the presence
of vertical synchronizatin pulses, a picture carrier detection
circuit, and an automatic gain control (AGC) amplifier. Outputs
representative of these sensor components are shown as being coupled
over a group of lead 20 to sensory circuitry 22, which in turn
couples outputs representative of the operation of these various
sensor circuits to a microprocessor unit 23 for controlling the
operation of the microprocessor unit.The microprocessor unit 23 is utilized in the system of FIG. 1 for controlling the operation of a frequency synthesizer tuning system capable of automatic offset correction. When the viewer desires to select a new channel, he enters the desired channel number into a channel selection keyboard 25. There are a number of different keyboards which may be employed to accomplish this function, and the particular design is not important to this invention. The channel selector keyboard 25 also may include switches or keys for initiating a signal seek function in either the "up" or "down" direction.
Information represented by the selection of channel numbers on the keyboard 25 is supplied to the microprocessor unit 23 which provides output signals over a corresponding set of leads 27 to the tuners (local oscillators) 11 to effect the appropriate band switching control for the tuners 11 in accordance with the particular channel which has been selected. In addition, the keyboard 25, operating through the microprocessor unit 23, provides output signals which operate a channel number display 29 to provide an appropriate display of the selected channel number to the viewer.
The microprocessor M3870 unit 23 also processes the signals which are used to operate the channel number display 29 through a multiplexing circuit operation to decode the selected channel number into a parallel encoded signal. This signal is applied to corresponding inputs of the count-down counter or programmable frequency divider 31 to cause the division number of the divider 31 to relate to the divided down frequency of the tuner local oscillators connected to the input of the divider 31 through a prescaler divider circuit 32 to the frequency of the reference oscillator 34. Thus, the division number or division ratio of the local oscillator frequency obtained from the output of the programmable divider 31 is appropriately related to the frequency of the reference crystal oscillator 34.
The output of the oscillator 34 also is applied through a countdown circuit or programmable frequency divider 35. Conventional frequency synthesizer techniques are employed; and the microprocessor unit 23 automatically compensates, through appropriate code converter circuitry, for the non-uniform channel spacing of the television signals. It has been found most convenient to cause the programmable frequency divider 31 to divide by numbers corresponding directly to the oscillator frequency of the selected channel, for example, 101, 107, 113 . . . up to 931.
In accordance with the time division multiplex operation of the microprocessor 23, the count of the programmable frequency divider 35 initially is adjusted to a fixed count by the application of appropriate output signals from the microprocessor unit 23 to a point selected to be at or near the mid-point of the operating range of the programmable frequency divider 35. Thus, the output of the divider 35 is a stable reference frequency (because the input is from the reference crystal oscillator 34) which is used to establish initially and to maintain tuning of the receiver to the selected channel.
The output of the programmable divider 35 is applied to one of two inputs of a phase comparator circuit 37. The other input to the phase comparator circuit 37 is supplied from the selected one of the VHF or UHF oscillators in the tuner stages 11 through the programmable frequency divider 31. The phase comparator circuit 37 operates in a conventional manner to supply a DC tuning control signal through a phase locked loop filter circuit 39 and over a lead 40 to the oscillators in the tuner system 11 to change and maintain their operating frequency.
With the exception of the use of the microprocessor unit 23, the operation of the system which has been described thus far is that of a relatively conventional frequency synthesizer system incorporated into a television receiver. This system is similar to the system of the '953 patent. As in the system of that patent, the system shown in FIG. 1, when the transmitted station or station received on a master antenna distribution system provides the station or channel signals at the proper frequency, operates as a relatively conventional frequency synthesizer system. If, however, there is a frequency offset in the received signal to cause the carrier of the received signal to be displaced from the frequency which it should have to some other frequency, it is possible that the system would give the appearance of mistuning to the received station. The microprocessor 23, operating in conjunction with the sensory circuitry 22, is employed in conjunction with the countdown or programmable frequency divider circuit 35 to eliminate this disadvantage and still retain the advantages of frequency synthesizer tuning.
Reference now should be made to FIG. 2 which shows details of t
he
interface between the keyboard 25, the microprocessor unit 23, and
the circuitry used in the frequency synthesizer portions of the
system. A commercially available microprocessor which has been used
for the microprocessor 23, and which forms the basis for the
diagramatic representation of the microprocessor in FIG. 2, is the
Matsushita Electronics Corporation MN1402 four-bit single-chip
microcomputer. This microcomputer has two, four-bit parallel input
ports labeled "A" and "B". In addition, three output ports, a five-bit
output port "C" and two four-bit output ports "D" and "E" are
provided. The internal configuration of the microcomputer 23 includes
an arithmetic logic unit (ALU), a read only memory (ROM) for storing
instructions and constants, and a random access memory (RAM) used for
data memory, arranged into four files, each file containing 16
four-bit words. These words are selected by X and Y registers and this
memory is used, for example, for timers, counters, etc., and also is
used to hold intermediate results. To facilitate an understanding of
the operation of the system, a portion of this memory is shown in
FIG. 2 as a clock 81 and a reversible counter 82 connected between
the "B" input port and the "D" output port. The microcomputer 23 is
programmed to permit it to operate in conjunction with the remainder
of the circuits shown in FIG. 2. The programming techniques are
standard, and the microcomputer 23 itself is a standard commercially
available circuit component.There are several system parameters that must be selected in the operation of the system shown in FIG. 2. The selection of the nominal frequency of the two signals that feed the phase comparator circuit 37 is an example. Channel selection is provided by changing the frequency division ratio of the selector counter 31 which divides the local oscillator signal after this signal is passed through a prescaler circuit 32 and a divide-by-two divider circuit 41. The nominal frequency from the programmable frequency divider 31 (selector counter) is selected so that the local oscillator (tuner) 11 can be set exactly on frequency for all channels.
Since the frequency divider 31 is able to divide only by integer numbers, one distinct frequency possibility in the range of one KHz is obtained, another in the range of two KHz, etc. A choice must be made as to which of these values is optimum. Each value yields the nominal frequency of all of the 82 channels by simply multiplying by an appropriate integer for each channel. To simplify the phase locked loop filtering problem by the filter 39, it is desirable that the frequencies of the signals supplied to the phase comparator 37 are as high as possible. This permits rapid acquisition of a new channel along with a very clean DC control signal to adjust the local oscillator. A trade-off for this, however, must be made to permit fine tunning adjustment of the local oscillator automatically to correctly tune in stations which are off their assigned frequency, or to manually provide this feature, if desired. The two-speed operation of the system in accordance with the present invention allows a better trade-off to be made by allowing rapid acquisition and then a slower speed for precise tuning.
A compromise solution which is utilized in the circuit of FIG. 2 is to cause the frequency division chain from the local oscillator 11 in the tuner to the phase comparator 37 to be composed of the fixed divide-by-256 prescaler 32, and a fixed divide-by-4 division, which is accomplished by the divider 41 at the input of the counter 31 and a second divider 42 at the output of the counter 31. The variable frequency divider counter 31 then is loaded by means of three latch circuits 44, 45 and 46 at an appropriate time by the time division multiplex operation of the microcomputer 23 and a number that programs the programmable frequency divider counter 31 to divide by the numerical value of the frequency of the local oscillator in MHz for the channel selected. For example, if the receiver is to be tuned to channel 2, which has a nominal local oscillator frequency of 101 MHz, the programmable frequency divider 31 is set to divide by 101. If the receiver is to be tuned to channel 83, which has a nominal local oscillator frequency of 931 MHz, the programmable frequency divider 31 is set to divide by 931. In both cases, the variable divider 31 produces a 1 MHz signal. However, because of the fixed divide-by-256 and the two fixed divide-by-two dividers in series with the programmable divider 31, an output frequency of 976.5625 Hz is supplied from the output of the divider 42 to the upper input of the phase comparator 37.
The division ratio of the selector counter 31 is established by appropriate output signals from the latch circuits 44, 45 and 46, as mentioned above. The initial operation for changing, or maintaining, the division ratio of the divider 31 is established by an entry of the two digits of the selected channel number in the keyboard 25. The microcomputer 23 operates as a time division multiplex system for continuously monitoring the input ports and the output ports to control the operation of the remainder of the system. The selection of the two digits of the desired channel number is affected by a time division multiplex iscanning of the outputs of the D output port of microcomputer 23 and providing that information at the A input port. From here the information is translated again to the D output ports to the appropriate drivers of the channel number display circuit 29 and to the latches 44, 45 and 46, and to a pair of similar four bit latches 49 and 50 which control the divider ratio of the counter 35.
Although the D output ports of the microcomputer 23 are connected in common to all of these various portions of the circuit, the selection of which of the latches are enabled to respond to the particular output signals appearing on the D output ports at any given time is effected through the C and E output ports of the microcomputer 23 in a time division multiplex fashion. A decoder circuit 52, connected to the lowermost three outputs of the E output port of the microcomputer 23, is used to apply unique decoding signals at different times in the time division multiplex sequence of operation of the microcomputer 23 to the five latch circuits 44, 45, 46, 49 and 50, respectively. At any given time in the sequence, only one of these latch circuits is enabled for operation. A latch load signal is applied from the upper output (EO3) at each cycle of operation of the signals appearing on the E output port to set the latch circuit which is enabled by the output of the decoding circuit 52 with the data appearing on the other inputs to the latch circuit. This data simultaneously appears on the four outputs of the D output port of the microcomputer 23.
Thus, in rapid sequence, the latch circuits 44, 45 and 46 are set to store the division number corresponding to the selected channel entered onto the keyboard 25, and the latch circuits 49 and 50 are each operated to set the programmable divider reference counter 35 to a center or nominal count, which is always the same upon the selection of a new channel on the keyboard 25. Similarly, the two right-hand outputs of the C output port (CO6 and CO5) enter the two digits of the selected channel number in the drivers of the display circuit 29 at the proper time in the binary encoded sequence when these digits appear on the four-bit binary encoded representation of the D output port. This results in a visual display of the channel number selected.
In addition to the selection of a channel number directly by the keyboard 25, the keyboard also may include an additional switch 56, which is scanned in the time division multiplex sequence to determine if the receiver is placed in a "seek" mode of operation (when the signal seek capability is incorporated into such a receiver). Operating in conjunction with the signal seek switch 56 are a pair of "up" and "down" seek direction input switches shown with a graphic representation of the seek directions on the keyboard 25. A further provision is provided by two keys labeled "U" and "D", which are used for "manual" fine tuning of the receiver in the "up" or "down" directions depending upon which of the two keys U or D has been operated. The keyboard 25 includes one additional switch 58 which may be used to disable the automatic fine tuning (AFT) portion of the circuit by rendering the microcomputer insensitive to the signal output from the AFT circuit, in a manner described more fully subsequently.
As is apparent from the foregoing, the
microcomputer 23 provides the intelligence, decision making, and
control for the system operation. It is a complete self contained
computer. The decisions or signal inputs upon which the microcomputer
23 bases its operation include, in addition to the inputs from the
keyboard 25, inputs on sensory inputs into the B input port and into
the SNS1 and SNS0 inputs as shown in FIG. 2. These input signals are
used to provide an indication to the microcomputer 23 of the presence
or absence of a received signal; and if the presence of such a
signal is indicated, the inputs provide a further indication of the
accuracy of the tuning of the receiver to that signal. If the system
is being operated solely in a manual mode of operation (AFT switch 58
open), the microcomputer 23 disregards all of this sensory information
and tunes to the frequency allocation of the channel selected in the
manner described above. The system will stay tuned to this
condition, operating as a conventional frequency synthesizer, whether
or not a station is present in the received signal.When the system is placed in its automatic mode of operation (similar to the mode of operation of the above mentioned '953 patent), the counter 82, integrally formed as part of the microcomputer 23, continuously adds or subtracts one number at a time from the nominal value or programmable division fraction entered into the programmable frequency divider 35 at the outset of each new channel number selection when frequency offset (mistuning) is present. The counter 82 is driven at a relatively high counting rate by clock pulses from the clock 81 during this initial or forced search mode of operation. Thus, automatic offset correction is provided for any channel which is off its assigned frequency. The offset correction automatically adjusts the frequency of the local oscillator by changing the division ratio of the signal from the reference oscillator 35 applied to the lower input of the phase comparator 37. By doing this, the output of the phase comparator 37 applied to the local oscillator 11 varies to cause the oscillator to be tuned in the proper direction to compensate for the transmitting station mistuning.
When the system is operating in its automatic mode of operation, the microcomputer 23 responds to the sensor information applied to it on its B input ports and on the S1 input port shown in FIG. 2. These inputs are obtained from the various outputs of the operational amplifiers shown connected to the corresponding input ports in the detailed circuit of FIG. 3. Depending upon whether the receiver is provided with a signal seek feature or not, one or more of the sensory inputs of the circuit of FIG. 3 are used. The s
ystem
shown in the drawings has a capability of correcting for frequency
offsets larger than 1.5 MHz on channels 2 and 7 and approximately 2
MHz on channels 6 and 13. The remainder of the channels have a range
between these two values.If the receiver is not tuned properly, the micromputer 23 executes the localized search of the tuning range mentioned above. Since there is a necessary settling down time for the tuning of a television receiver immediately following selection of a new channel, a time interval of 250 milliseconds has been selected to prevent any localized search or offset frequency correction until the expiration of this "settling down" time period. If, at the end of this 250 millisecond time interval, a properly tuned station is present, this is indicated by the sensory outputs from the television receiver and no localized search is effected to change the division ratio or programmable divider count in the reference counter 35 for a system that also has signal seek.
A system with no signal seek capability is described later that requires less sensory input but which uses a time period where a forced search is required directly after the settling time interval.
Upon termination of the 250 millisecond settling down period, the microcomputer 23 is rendered responsive to the sensory input signals on its sensory input signal ports. In the simplest form, only the output of the frequency discriminator 60 (FIG. 3) applied to three comparators 61, 62 and 63 is used to provide the necessary tuning information to the microcomputer 23. The outputs of these comparators are applied to the B12 and B11 inputs of the microcomputer.
The
comparator 61 simply is a conventional comparator for determining
whether or not the output of the frequency discriminator is positive
or negative, as indicated in the upper waveform of FIG. 5. The
comparators 62 and 63 are each adjusted with appropriate reference
input levels to provide a narrow window centered about the center
tuning frequency (fc) of the receiver. If the tuning of the receiver,
as indicated by the output of the frequency discriminator 60, is
outside this window on either side of the central axis shown in FIG.
5, one output condition is indicated on the input terminal B11 of the
microcomputer. Only when the tuning frequency is within the tuning
window, indicative of a properly tuned receiver, is the appropriate
input applied to the microcomputer input terminal B11. This input
overrides any other input that may be present on the input terminal
B12 and is indicative of a properly tuned receiver. The input from the
frequency discriminator 60, as applied to the microcomputer on its
input port B12, is used to determine the direction of operation of the
counter 82 of the microcomputer for the localized search count
signals applied to the latch circuits 49 and 50 to change the count of
the reference programmable divider counter 35 on a step-by-step
basis.The lower graph of FIG. 5 plots the relative frequency of the local oscillator 11 to the received signal frequency with respect to time. The various arrows are used to indicate the manner of operation of the counter 82 in the microcomputer 23 in conjunction with the reference counter 35 for adjusting for any mistuning conditions which may exist after the initial station selection has been effected in the manner described above.
If the receiver is properly tuned, the outputs from the comparators 62 and 63 of FIG. 3 which are combined together and applied to the input port B11 of the microcomputer 23, provide an indication that the tuning is within the properly tuned center frequency window. As a consequence, no further operation of the microcomputer to change any of the outputs applied to the latch circuits 49 and 50 for the duration of this condition is effected. On the other hand, if the receiver is mistuned on either side of the proper tuning frequency, the various operating characteristics shown in FIG. 5 are effected.
Assume initially that the receiver is capable of making tuning adjustments over a range of fc plus Δf to fc minus Δf, as indicated in the top waveform of FIG. 5. Three specific examples of mistuning will then be considered. Initially, assume that the local oscillator is mistuned relative to the received signal to a frequency f1 as shown in the lower graph of FIG. 5. In this condition, the outout of the frequency discriminator 60 is positive since this signal frequency lies to the lefthand side of the center or properly tuned region of operation of the discriminator. Under this condition of the operation, the input signal applied to the sensor port B12 of the microcomputer 23 is such that the microcomputer counter 82 is caused to advance in a positive direction to change the programmable division ratio or count of the reference counter 35 in a manner to force the output of the phase comparator 37 to adjust the frequency of the local oscillator until the proper tuning indicated at point B in the lower graph of FIG. 5 is reached. The time interval for accomplishing this result is measured from the upper end of the arrow representative of the frequency f1 to the point B.
Now assume that the receiver mistuning is to a frequency f2 which as shown in FIG. 5 as located on the righthand-side of the center axis fc. In this condition, the discriminator output is negative. This is reflected in the output of the comparator 61 applied to the input port B12 of the microcomputer 23. The polarity of this signal is identified by the microcomputer 23 to cause the counter 82 in it to operate in the reverse direction. As this count is applied on a step-by-step basis through the latch circuits 49 and 50 to the reference counter 35, the division ratio or count of the reference counter (divider) 35 is changed. As a result, the reference oscillator signal applied to the phase comparator 37 causes the phase comparator 37 output to drive the local oscillator frequency in a direction opposite to that considered in the first example. This is shown by the vector interconnecting the top of the arrow representative of f2 to point A on the time/frequency graph of FIG. 5.
As discussed in the general discussion above, whenever the tuning frequency reaches the narrow window on either side of fc, the outputs of the comparators 62 and 63 provide the necessary indication on the sensory input port terminal B11 to cause termination of the operation of the counter 82 in the microcomputer 23. Then the reference counter 35 remains set to the count attained just prior to the appearance of this input signal on the input port B11 of the microcomputer 23.
A third mistuning condition can exist, and ordinarily this condition results in an ambiguity which cannot be corrected simply by responding to the signal polarity at the output of the frequency discriminator. This is indicated by the mistuned condition where the difference between the local oscillator frequency f3 and the transmitter frequency is such that the signal f3 lies in the range to the right of the negative portion of the discriminator output shown in the upper waveform of FIG. 5. In this condition, the associated sound causes the discriminator output to be positive; so that the television receiver normally would attempt to tune toward the next adjacent channel and away from the properly tuned center frequency of the channel which is desired. The output of the discriminator 60 in this situation is the same as it was in th
e
first example considered for frequency f1; so that the counter 82 of
the microprocessor 23 operates to change the count in the reference
counter 35 in a manner to cause the local oscillator frequency to go
higher toward a frequency f3 +Δf, as shown in FIG. 5.A predetermined number of counts of the counter 82 in the microcomputer 23 are necessary for the microcomputer to count through the frequency range Δf, and this range is selected to be within the pull in or operating range of the system. Once this count has been attained, the microcomputer counter 82 immediately is reset back to a count which corresponds to a frequency 2 Δf lower than the frequency attained by the maximum count. This is indicated in FIG. 5 by the frequency f3-Δf. Because the microcomputer counter 82 is limited to counting a number of counts equal to Δf, this new frequency now is on the lefthand side of the center line fc, shown in both waveforms of FIG. 5. This places the local oscillator frequency at a point such that the frequency discriminator output is the positive output shown on the lefthand-side of the upper waveform of FIG. 5. Counting continues in the same direction as previously. This time, however, it is in a proper direction to bring about correct tuning; and when the center frequency is reached, the output of the comparators 62 and 63 cause the microcomputer 23 to stop its count. The proper tuning point attained is indicated at point C on the graph of the lower part of FIG. 5.
Because the counter 82 of the microcomputer is limited to a maximum count equivalent to Δf above its initial count and thereupon is reset to a new count equivalent to 2 Δf lower than the maximum count, it is not necessary to utilize any other sensory inputs in order to properly tune the receiver over a wide pull in range (as much as plus or minus 2 MHz). Only the output of the conventional frequency discriminator 60 is used to provide the necessary sensory inputs.
The
counter 82 of the microcomputer 23 is operated by the clock 81
during the foregoing sequence of operation, immediately following the
selection of a new channel by the operation of the keyboard 25, at a
fast or high speed operation. Typically, the counter steps are 10
milliseconds per step; so that there are no initial visual effects
which can be noticed by an observer of the television screen of the
receiver being tuned. The maximum forced search period is
approximately 900 milliseconds in duration. At the end of this time
interval, a timer in the microcomputer 23 causes a signal to be
applied through the outputs of the E output port to the decoder
circuit 52 indicative of the completion of this time interval. The
decoder 52 then applies a pulse on an output lead connected to the B13
input of the B input port of the microcomputer 23. This pulse is
sensed by the microcomputer 23 and is applied to the clock 81 to
change the clock rate to a much slower rate, approximately one-third
(1/3) or one-fourth (1/4) the rate used previously during the forced
search mode of operation. This then permits the system to accomodate
station drifts which normally occur at a very slow rate during the
transmission and reception of a television signal. As a consequence,
it is possible to use more filtering in the filter 39 on the tuning
line (FIG. 1) and employ a smaller frequency window for the channel
verification sensed by the circuitry shown in FIG. 3. The result is a
more precise tuning from the receiver than is otherwise possible if
only a high speed operation of the clock 81 is utilized.When the channel once again is changed by operation of the keys in the keyboard 25 or operation of the channel selection circuitry from a remote control unit, this new channel input is sensed by the microcomputer 23 from the signals applied to the A input port and the clock 81 is reset to its fast time or the forced search mode of operation; and the process resumes.
Instead of employing an additional decoding function in the decoder 52, a separate decoder also could be connected to the outputs of the D output ports to feed back the signal to the B13 input terminal of the B input port of the microcomputer 23. The operation of the system to change the rate or frequency of the pulses applied by the clock 81 to the counter 82 otherwise is the same as described above.
Although applicant has found that it is preferable to correct for mistuning or frequency offsets by adjusting the count or division ratio of the counter 35, such offset adjustments also could be effected by adjusting the count in the counter 31 in the local oscillator signal line. The operation in such a case is the same as described above for adjusting the count in the counter 35.
If the receiver is to be used with an automatic signal seek mode of operation, however, additional sensory inputs are necessary. These inputs operate in conjunction with the output of the frequency discriminator 60. The operation of the microcomputer 23 in controlling the count of the reference programma
ble frequency counter divider 35 is the same as described
above. The additional sensory inputs simply are used in conjunction
with the outputs of the comparators 62 and 63 to signal the
microcomputer 23 to assure that tuning is to a picture channel rather
than an adjacent sound channel. This is accomplished by utilizing
the output of the synchronizing signal separator 65 which is applied
to a comparator 67 to produce an output signal to the SNS1 sensory
input of the microcomputer 23 only when vertical synchronizing signal
components are present.In addition, the output of a picture carrier detector 69 is applied to the input of a comparator 70 to produce an output to the B10 sensory input of the microcomputer 23. If the picture carrier detector 69 is producing an output indicative of the presence of a carrier, but no output is being obtained from the vertical synch separator 65 at the same time, the system is mistuned to a sound carrier and the microcomputer 23 is permitted to continue its localized search until a properly tuned station is found. Only when there is coincidence of signals from the picture carrier detector 69, the synch signal separator 65, and the automatic frequency discriminator window as determined by the comparators 62 and 63, is the microcomputer operation terminated to indicate that a properly tuned channel is present.
Further insurance of tuning the receiver only to a strong signal also can be provided by the addition of an AGC amplifier 72. This is connected to a comparator 74 coupled to the B10 input port along with the output of the picture carrier detector comparator 70. When the AGC amplifier 72 is used as a sensory input, the microcomputer operation, when the system is used in a signal seek mode, is only terminated to indicate reception of a valid signal when that signal is strong enough to produce the desired output from the comparator 74. The signal level which is acceptable is set by a potentiometer 75.
It should be noted that when the system is operated in a signal seek mode, the sensory inputs must indicate the reception of a properly tuned signal within a pre-established time period. If no signal is sensed by the various sensory input circuits operating in conjunction with one another as described above, the microcomputer 23 automatically steps to the next channel number and repeats the sequence of operation described above. This is when it is placed in its signal seek mode of operation. If signal seek is not employed, the additional sensory circuits 65, 69 and 72 are not necessary, and the inputs to the microcomputer which are provided from these sensory circuits are not utilized. The sensory signal input which is used both for a receiver without a signal seek capability of operation and for a receiver which has a signal seek mode of operation in it, is the output of the frequency discriminator 60 operating in conjunction with the comparators 61, 62 and 63 as described above.
As indicated above, the wideband method of tuning precisely to an incoming signal that is at the wrong frequency described here only needs the frequency discriminator sensory information. The method that uses the additional sensors described above is needed to make this system operate compatibly with signal seek but it is not restricted to seek operation.
e, there is a 250 millisecond settling time, the same as
the operation described above with compatible seek. After that,
however, comes a period of time where a forced localized search is
produced by the microcomputer 23. The forced search is needed to
insure that the system will correctly tune to stations that initially
may be tuned to the undesired zero voltage crossover in the right
half of the upper curve of FIG. 5. Such signals may be within the
frequency window of the discriminator 60; and if a search is not
forced, this system will not correctly tune. The compatible seek
system described previously correctly tunes the local oscillator
without a forced search, because the picture carrier detector and
vertical detector do not give an output for this situation and the
system automatically goes into its search mode of operation. However,
the non-seek system does not have a picture carrier sensor input and
must be forced to search for an initial period of time sufficient to
allow the system to tune up to its maximum frequency and then reset
(loop) back to a frequency of 2 Δf lower. Then it is tuned to the
positive left half portion of the discriminator curve (FIG. 5) and
the frequency window created by the discriminator 60 is sufficient to
insure proper tuning. If the discriminator output produced by the
desired incoming signal created an initial situation that produces
the correct tuning direction information, i.e., in the left half of
the curve of FIG. 5, or in the right half portion that gives the
correct direction andThen,
a positive discriminator output is produced, and the system tunes up
in frequency. This continues until the forced search is removed by
time-out of the microcomputer 23 (a fraction of a second). At such
time, the receiver is correctly tuned by the frequency window of the
discriminator to be very near fc. The system cannot tune to the
undesired discriminator crossover shown in the right half portion of
FIG. 5 because the polarity of the tuning direction signal always
causes it to tune away from that point.The fast time or forced search operation of the system can be terminated in a different way other than the preestablished time-out period described above in conjunction with the operation of the circuit shown in FIG. 2. Generally, it is desirable to build into the system (or program into the system by means of software) such a maximum time-out period to effect the operation which has been described above to terminate the search and cause the clock 81 thereafter to operate in a low speed mode of operation. Termination also can be accomplished by sensing the number of changes in the direction sensor input applied to the B12 terminal of the B input port to cause the search to be terminated when this direction changes three times (or more). By doing this, any flicker that might be observed on the screen of the television receiver is minimized, since the forced search still takes place at the high rate of application of clock pulses from the clock 81 to the counter 82 in the same manner described above.
Termination of the search, however, also may be effected by means of a search terminate counter 78 (FIG. 3), which is advanced by pulses applied to it each time the output of the comparator 61 changes its sign (indicative of a change in direction for the counter 82) as applied to it through the B12 input port, as described earlier. After three of these changes, or some other number if desired, an output pulse is obtained from the search terminate counter 78 and is applied to the SNS0 input of the microcomputer 23. This causes the operation of the clock 81 to be switched to its low speed mode of operation to terminate the fast or "forced search" mode of operation. The next time a new channel number is entered on the keyboard 25, a reset pulse is applied to the search terminate counter 78 to reset it to its original or zero count, thereby readying it for another sequence of operation. It is apparent that the search terminate counter 78 may not always be operated to terminate the count, since the time-out interval which is sensed by the decode circuit 52 and applied to the B13 input port of the microcomputer 23 may occur before there are three changes of direction of the search. In any event, the next time a new channel number is entered into the keyboard 25, the search terminate counter 78 is reset; so that it is irrelevant whether this counter reaches a full count or not to effect the termination of the forced search operation of the system.
FIG. 4 shows the control sequence of the system which is stored in the ROM (Read Only Memory) of the microcomputer 23. The microcomputer 23 operates by always running through the flow sequence, via loops L1, L2 and L3. Loop L1 corresponds to a new channel selection by two digit number entry. Loop L2 corresponds to channel number increment or decrement by an up or down key operation, respectively, or by seek operation. Loop L3 corresponds to fine tuning, either manual or automatic. To obtain exact timing for system control, the microcomputer 23 receives a standard timing pulse from the output of the reference counter 35 divided in a divide-by-five counter 80 and applied to the A13 input port of the microcomputer 23. The control functions which are programmed into the microcomputer 23, as indicated in the flow chart of FIG. 4, are outlined in the following paragraphs.
Channel Number Correction: An invalid two digit channel number entry (0, 1, 84, 99) is corrected. When the operation of the receiver is in the signal seek mode, the next channel up from 83 is channel 2, and the next lower channel from channel 2 is 83.
PLL Control I: For a
given channel number, a corresponding binary code for the PLL selector
counter 31 is derived as described previously. For UHF channels, the
local oscillator frequency separation between two adjacent channels
is 6 MHz and the code for PLL is generated by the microcomputer 23
through means of a simple calculation. This code then is transferred
from the microcomputer 23 to the latches 44, 45 and 46 as described
previously.PLL Control II: This routine of the microcomputer 23 is used to transfer the fine tuning data to the latches 49 and 50 which control the count of the reference counter 35 in the PLL circuit.
Channel Number Display: The channel number is transferred from the microcomputer 23 to the driver latches of the display driver circuit 29.
Key Input Detection: The keyboard is arranged as the matrix circuit shown in FIG. 2. ROM programming for scanning and acknowledging a keyboard entry only after successive indications provides protection against false entry due to contact bounce. The four data output lines of the D output port of the microcomputer 23 are used to transfer data to the phase lock loop section of the circuit and to the display circuit 29, as well as for scanning the keyboard matrix circuit.
Time Count: The microcomputer 23 receives a basic timing pulse of approximately 200 Hz from the output of the divider 80 and performs various controls for each timing pulse. By way of example, sensing for the vertical synch input (when the system is used with a signal seek capability) on the input port SNS1 takes place every 2.5 milliseconds. Automatic seek timing is selected to be 133 milliseconds for UHF channels. All of these timing pulses are derived from the basic synchronization timing pulse applied to the microcomputer on the A13 input port from the output of the divider 80. Various other timing values used in the microcomputer to properly time multiplex sequence the operation are derived from this basic timing pulse.
Sensor Input Detection: As described previously, the output of the comparators shown in FIG. 3 reflect the status of the tuning of the television receiver. If no signal seek mode of operation is used, only the frequency discriminator or AFT discriminator 60 is necessary. When a system is being used in a signal seek mode, a proper television signal receipt is indicated by the presence of a vertical synch signal at the output of the synch signal separator 65 and corresponding outputs are applied to the input leads B10 and B11 (high level input signals) indicative of tuning to the "correct tuned" frequency discriminator window and reception of a picture carrier. As stated previously, the signal present on the B12 input lead is used to determine the direction of tuning when the receiver is operated in its automatic mode.
Mode Detection: The status of the seek and automatic/manual (A/M) switches are detected. If the A/M switch (not shown) is in its automatic position, automatic seek and offset correction are active. If only the seek switch is on, only seek is performed. If the A/M switch is in manual, manual fine tuning (MFT) is active.
Automatic Mode: If the TV receiver is not properly tuned for VHF channels in automatic, the local oscillator frequency is shifted automatically toward proper tuning. The fine tuning data is generated in the microcomputer 23 and is transferred to the latches 49 and 50 for the reference counter 35 in the PLL circuit.
Manual Fine Tuning (MFT) Control: The local oscillator frequency is shifted by pushing the fine tuning up (U) or down (D) pushbutton or switch. This MFT control can be applied to VHF channels as well as to UHF channels.
Channel Up/Down: When a channel up (upward pointing arrow) or down (downward pointing arrow) key closure in the keyboard 25 is detected, or upon a direct access to an unused channel, this routine is activated and the system will advance to the next channel in the selected direction.
The foregoing embodiment of the invention which has been described above and which is illustrated in the drawings is to be considered illustrative of the invention, which is not limited to the specific embodiment selected for this purpose. For example, hard-wired logic could be used to achieve the various circuit operations which are accomplished by the microcomputer 23 in conjunction with the other portions of the system. The relative ease of programming and debugging the microcomputer 23, however, make it much simpler to implement the system operation with the microcomputer than with hard-wired logic. With respect to the sensor circuit inputs to the system, an added degree of operating assurance can be provided by the addition of a sound carrier sensor in addition to the picture carrier sensor shown in FIG. 3. If this feature is desired, the output of the comparator for the sound carrier is combined with the outputs of the comparators 70 and 74 at the input terminal B10 of the B input port of the microcomputer 23. Because of the manner of the circut operation which has been described previously, however, the addition of a sound carrier detector to the system is not considered necessary, even for a system operating in the signal seek mode of operation. This is in contrast to conventional television receivers having a signal seek operation, in which detection of the sound carrier generally is a necessity to insure that mistuning of the receiver to an adjacent sound carrier does not take place.
HITACHI HD44860 CMOS 4-bit single chip microcomputer in 54-pin QFP package. Operational temperature range from -20°C to 75°C.
The
HMCS47C is designed to perform efficient controller function as well as
arithmetic function for both binary and BCD data. The CMOS technology
of the HMCS47C provides the flexibility of microcomputers for battery
powered and battery Back-up applications. HMCS47C. HMCS47CL I -pin QFP package. Operational temperature range from -20°C to 75°C.FEATURES 4-bit Architecture 4,096 Words of Program ROM and Pattern ROM (10 bits/Word) 256 Digits of Data RAM (4 bits/Digit) 44 I/0 Lines and 2 External Interrupt Lines
- Timer/Counter IFP'54l Instruction Cycle Time; HMCSHC : Sm HMCS47C, HMCS47CL HMCS47CL : 20p:
- All Instructions except One Instruction; Single Word and Single Cycle
- BCD Arithmetic Instructions 0 Pattern Generation Instruction — Table Look Up Capability —
- Powerful Interrupt Function 3 Interrupt Sources 2 External Interrupt Lines Tirner/ Counter Multiple Interrupt Capability
- Bit Manipulation Instructions for Both RAM and I/O
- Option of I/0 Configuration Selectable on Each Pin; (DP-645) With Pull up M05 or CMOS or Open Drain
- Built-in Oscillator
- Built-in Power-on Reset Circuit (HMCS47C only)
- Low Operating Power Dissipation; 3_3mW typ_ A O Stand-by Mode (Halt Model; 66 uw max.
- CMOS Technology
CRT TV EHT VOLTAGE MULTIPLIER - KASKADE COCKCROFT-WALTON CASCADE CIRCUIT FOR VOLTAGE MULTIPLICATION:
A Cockcroft-Walton cascade circuit comprises an input voltage source and a pumping and storage circuit with a series array of capacitors with pumping and storage portions of the circuit being interconnected by silicon rectifiers, constructed and arranged so that at least the capacitor nearest the voltage source, and preferably one or more of the next adjacent capacitors in the series array, have lower tendency to internally discharge than the capacitors in the array more remote from the voltage source.
1. An improved voltage multiplying circuit comprising,
2. An improved voltage multiplying circuit in accordance with claim 1 wherein said first pumping capacitor is a self-healing impregnated capacitor which is impregnated with a high voltage impregnant.
3. An improved voltage multiplying circuit in accordance with claim 1 wherein said first pumping capacitor comprises a foil capacitor.
Description:
BACKGROUND OF THE INVENTION
The invention relates in general to Cockcroft-Walton cascade circuits for voltage multiplication and m
ore particularly to such circuits with a
pumping circuit and a storage circuit composed of capacitors connected
in series, said pumping circuits and storage circuit being linked with
one another by a rectifier circuit whose rectifiers are preferably
silicon rectifiers, especially for a switching arrangement sensitive to
internal discharges of capacitors, and more especially a switching
arrangement containing transistors, and especially an image tube
switching arrangement.
Voltage multiplication cascades composed of capacitors and rectifiers are used to produce high D.C. voltages from sinusoidal or pulsed alternating voltages. All known voltage multiplication cascades and voltage multipliers are designed to be capacitance-symmetrical, i.e., all capacitors used have the same capacitance. If U for example is the maximum value of an applied alternating voltage, the input capacitor connected directly to the alternating voltage source is charged to a D.C. voltage with a value U, while all other capacitors are charged to the value of 2U. Therefore, a total voltage can be obtained from the series-connected capacitors of a capacitor array.
In voltage multipliers, internal resistance is highly significant. In order to obtain high load currents on the D.C. side, the emphasis in the prior art has been on constructing voltage multipliers with internal resistances that are as low as possible.
Internal resistance of voltage multipliers can be reduced by increasing the capacitances of the individual capacitors by equal amounts. However, the critical significance of size of the assembly in the practical application of a voltage multiplier, limits the extent to which capacitance of the individual capacitors can be increased as a practical matter.
In television sets, especially color television sets, voltage multiplication cascades are required whose internal resistance is generally 400 to 500 kOhms. Thus far, it has been possible to achieve this low internal resistance with small dimensions only by using silicon diodes as rectifiers and metallized film capacitors as the capacitors.
When silicon rectifiers are used to achieve low internal resistance, their low forward resistance produces high peak currents and therefore leads to problems involving the pulse resistance of the capacitors. Metallized film capacitors are used because of space requirements, i.e., in order to ensure that the assembly will have the smallest possible dimensions, and also for cost reasons. These film capacitors have a self-healing effect, in which the damage caused to the capacitor by partial evaporation of the metal coating around the point of puncture (pinhole), which develops as a result of internal spark-overs, is cured again. This selfhealing effect is highly desirable as far as the capacitors themselves are concerned, but is not without its disadvantages as far as the other cirucit components are concerned, especially the silicon rectifiers, the image tubes, and the components which conduct the image tube voltage.
It is therefore an important object of the invention to improve voltage multiplication cascades of the type described above.
It is a further object of the invention to keep the size of the entire assembly small and the internal resistance low.
It is a further object of the invention to increase pulse resistance of the entire circuit.
It is a further object of the invention to avoid the above-described disadvantageous effects on adjacent elements.
It is a further object of the invention to achieve multiples of the foregoing objects and preferably all of them consistent with each other.
SUMMARY OF THE INVENTION
In accordance with the invention, the foregoing objects are met by making at least one of the capacitors in the pumping circuit, preferably including the one which is adjacent to the input voltage source, one which is less prone to internal discharges than any of the individual capacitors in the storage circuit.
The Cockcroft-Walton cascade circuit is not provided with identical capacitors. Instead, the individual capacitors are arranged according to their loads and designed in such a way that a higher pulse resistance is attained only in certain capacitors. It can be shown that the load produced by the voltage in all the capacitors in the multiplication circuit is approximately the same. But the pulse currents of the capacitors as well as their forward flow angles are different. In particular, the capacitors of the pumping circuit are subjected to very high loads in a pulsed mode. In the voltage multiplication cascade according to the invention, these capacitors are arranged so that they exhibit fewer internal discharges than the capacitors in the storage circuit.
The external dimensions of the entire assembly would be unacceptably large if one constructed the entire switching arrangement using such capacitors.
The voltage multiplication cascade according to the invention also makes it possible to construct a reliably operating
arrangement which has no tendency toward spark-overs, consistent with satisfactory internal resistance of the voltage multiplication cascade and small dimensions of the entire assembly. This avoids the above cited disadvantages with respect to the particularly sensitive components in the rest of the circuit and makes it possible to design voltage multiplication cascades with silicon rectifiers, which are characterized by long lifetimes. Hence, a voltage multiplication cascade has been developed particularly for image tube circuits in television sets, especially color television sets, and this cascade satisfies the highest requirements in addition to having an average lifetime which in every case is greater than that of the television set.
A further aspect of the invention is that at least one of the capacitors that are less prone to internal discharges is a capacitor which is impregnated with a high-voltage impregnating substance, especially a high-voltage oil such as polybutene or silicone oil, or mixtures thereof. In contrast to capacitors made of metallized film which have not been impregnated, this allows the discharge frequency due to internal discharges or spark-overs to be reduced by a factor of 10 to 100.
According to a further important aspect of the invention, at least one of the capacitors that are less prone to internal discharges is either a foil capacitor or a self-healing capacitor. In addition, the capacitor in the pumping circuit which is adjacent to the voltage source input can be a foil capacitor which has been impregnated in the manner described above, while the next capacitor in the pumping circuit is a self-healing capacitor impregnated in the same fashion.
Other objects, features and advantages of the invention will be apparent from the following detailed description of preferred embodiments, taken in connection with the accompanying drawing, the single FIGURE of which:
BRIEF DESCRIPTION OF THE DRAWING
is a schematic diagram of a circuit made according to a preferred embodiment of the invention.
DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS
The voltage multiplier comprises capacitors C1 to C5 and rectifiers D1 to D5 connected in a cascade. An alternating voltage source UE is connected to terminals 1 and 2, said voltage source supplying for example a pulsed alternating voltage. Capacitors C1 and C2 form the pumping circuit while capacitors C3, C4 and C5 form the storage circuit.
In the steady state, capacitor C1 is charged to the maximum value of the alternating voltage UE as are the other capacitors C2 to C5. The desired high D.C. voltage UA is picked off at terminals 3 and 4, said D.C. voltage being composed of the D.C. voltages from capacitors C3 to C5. Terminal 3 and terminal 2 are connected to one pole of the alternating voltage source UE feeding the circuit, which can be at ground potential. In the circuit described here, a D.C. voltage UA can be picked off whose voltage value is approximately 3 times the maximum value of the pulsed alternating voltage UE. By using more than five capacitors, a correspondingly higher D.C. voltage can be obtained.
The individual capacitors are discharged by disconnecting D.C. voltage UA. However, they are constantly being recharged by the electrical energy supplied by the alternating voltage source UE, so that the voltage multiplier can be continuously charged on the output side.
According to the invention, in this preferred embodiment, capacitor C1 and/or C2 in the pumping circuit are designed so that they have a lower tendency toward internal discharges than any of the individual capacitors C3, C4 and C5 in the storage circuit.
It is evident that those skilled in the art, once given the benefit of the foregoing disclosure, may now make numerous other uses and modifications of, and departures from the specific embodiments described herein without departing from the inventive concepts. Consequently, the invention is to be construed as embracing each and every novel feature and novel combination of features present in, or possessed by, the apparatus and techniques herein disclosed and limited solely by the scope and spirit of the appended claims.
Inventors:Petrick, Paul (Landshut, DT)
Schwedler, Hans-peter (Landshut, DT)
Holzer, Alfred (Schonbrunn, DT)
ERNST ROEDERSTEIN SPEZIALFABRIK
US Patent References:
3714528 ELECTRICAL CAPACITOR WITH FILM-PAPER DIELECTRIC 1973-01-30 Vail
3699410 SELF-HEALING ELECTRICAL CONDENSER 1972-10-17 Maylandt
3463992 ELECTRICAL CAPACITOR SYSTEMS HAVING LONG-TERM STORAGE CHARACTERISTICS 1969-08-26 Solberg
3457478 WOUND FILM CAPACITORS 1969-07-22 Lehrer
3363156 Capacitor with a polyolefin dielectric 1968-01-09 Cox
2213199 Voltage multiplier 1940-09-03 Bouwers et al.
A Cockcroft-Walton cascade circuit comprises an input voltage source and a pumping and storage circuit with a series array of capacitors with pumping and storage portions of the circuit being interconnected by silicon rectifiers, constructed and arranged so that at least the capacitor nearest the voltage source, and preferably one or more of the next adjacent capacitors in the series array, have lower tendency to internally discharge than the capacitors in the array more remote from the voltage source.
1. An improved voltage multiplying circuit comprising,
2. An improved voltage multiplying circuit in accordance with claim 1 wherein said first pumping capacitor is a self-healing impregnated capacitor which is impregnated with a high voltage impregnant.
3. An improved voltage multiplying circuit in accordance with claim 1 wherein said first pumping capacitor comprises a foil capacitor.
Description:
BACKGROUND OF THE INVENTION
The invention relates in general to Cockcroft-Walton cascade circuits for voltage multiplication and m
ore particularly to such circuits with a
pumping circuit and a storage circuit composed of capacitors connected
in series, said pumping circuits and storage circuit being linked with
one another by a rectifier circuit whose rectifiers are preferably
silicon rectifiers, especially for a switching arrangement sensitive to
internal discharges of capacitors, and more especially a switching
arrangement containing transistors, and especially an image tube
switching arrangement.Voltage multiplication cascades composed of capacitors and rectifiers are used to produce high D.C. voltages from sinusoidal or pulsed alternating voltages. All known voltage multiplication cascades and voltage multipliers are designed to be capacitance-symmetrical, i.e., all capacitors used have the same capacitance. If U for example is the maximum value of an applied alternating voltage, the input capacitor connected directly to the alternating voltage source is charged to a D.C. voltage with a value U, while all other capacitors are charged to the value of 2U. Therefore, a total voltage can be obtained from the series-connected capacitors of a capacitor array.
In voltage multipliers, internal resistance is highly significant. In order to obtain high load currents on the D.C. side, the emphasis in the prior art has been on constructing voltage multipliers with internal resistances that are as low as possible.
Internal resistance of voltage multipliers can be reduced by increasing the capacitances of the individual capacitors by equal amounts. However, the critical significance of size of the assembly in the practical application of a voltage multiplier, limits the extent to which capacitance of the individual capacitors can be increased as a practical matter.
In television sets, especially color television sets, voltage multiplication cascades are required whose internal resistance is generally 400 to 500 kOhms. Thus far, it has been possible to achieve this low internal resistance with small dimensions only by using silicon diodes as rectifiers and metallized film capacitors as the capacitors.
When silicon rectifiers are used to achieve low internal resistance, their low forward resistance produces high peak currents and therefore leads to problems involving the pulse resistance of the capacitors. Metallized film capacitors are used because of space requirements, i.e., in order to ensure that the assembly will have the smallest possible dimensions, and also for cost reasons. These film capacitors have a self-healing effect, in which the damage caused to the capacitor by partial evaporation of the metal coating around the point of puncture (pinhole), which develops as a result of internal spark-overs, is cured again. This selfhealing effect is highly desirable as far as the capacitors themselves are concerned, but is not without its disadvantages as far as the other cirucit components are concerned, especially the silicon rectifiers, the image tubes, and the components which conduct the image tube voltage.
It is therefore an important object of the invention to improve voltage multiplication cascades of the type described above.
It is a further object of the invention to keep the size of the entire assembly small and the internal resistance low.
It is a further object of the invention to increase pulse resistance of the entire circuit.
It is a further object of the invention to avoid the above-described disadvantageous effects on adjacent elements.
It is a further object of the invention to achieve multiples of the foregoing objects and preferably all of them consistent with each other.
SUMMARY OF THE INVENTION
In accordance with the invention, the foregoing objects are met by making at least one of the capacitors in the pumping circuit, preferably including the one which is adjacent to the input voltage source, one which is less prone to internal discharges than any of the individual capacitors in the storage circuit.
The Cockcroft-Walton cascade circuit is not provided with identical capacitors. Instead, the individual capacitors are arranged according to their loads and designed in such a way that a higher pulse resistance is attained only in certain capacitors. It can be shown that the load produced by the voltage in all the capacitors in the multiplication circuit is approximately the same. But the pulse currents of the capacitors as well as their forward flow angles are different. In particular, the capacitors of the pumping circuit are subjected to very high loads in a pulsed mode. In the voltage multiplication cascade according to the invention, these capacitors are arranged so that they exhibit fewer internal discharges than the capacitors in the storage circuit.
The external dimensions of the entire assembly would be unacceptably large if one constructed the entire switching arrangement using such capacitors.
The voltage multiplication cascade according to the invention also makes it possible to construct a reliably operating
arrangement which has no tendency toward spark-overs, consistent with satisfactory internal resistance of the voltage multiplication cascade and small dimensions of the entire assembly. This avoids the above cited disadvantages with respect to the particularly sensitive components in the rest of the circuit and makes it possible to design voltage multiplication cascades with silicon rectifiers, which are characterized by long lifetimes. Hence, a voltage multiplication cascade has been developed particularly for image tube circuits in television sets, especially color television sets, and this cascade satisfies the highest requirements in addition to having an average lifetime which in every case is greater than that of the television set.
A further aspect of the invention is that at least one of the capacitors that are less prone to internal discharges is a capacitor which is impregnated with a high-voltage impregnating substance, especially a high-voltage oil such as polybutene or silicone oil, or mixtures thereof. In contrast to capacitors made of metallized film which have not been impregnated, this allows the discharge frequency due to internal discharges or spark-overs to be reduced by a factor of 10 to 100.
According to a further important aspect of the invention, at least one of the capacitors that are less prone to internal discharges is either a foil capacitor or a self-healing capacitor. In addition, the capacitor in the pumping circuit which is adjacent to the voltage source input can be a foil capacitor which has been impregnated in the manner described above, while the next capacitor in the pumping circuit is a self-healing capacitor impregnated in the same fashion.
Other objects, features and advantages of the invention will be apparent from the following detailed description of preferred embodiments, taken in connection with the accompanying drawing, the single FIGURE of which:
BRIEF DESCRIPTION OF THE DRAWING
is a schematic diagram of a circuit made according to a preferred embodiment of the invention.
DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS
The voltage multiplier comprises capacitors C1 to C5 and rectifiers D1 to D5 connected in a cascade. An alternating voltage source UE is connected to terminals 1 and 2, said voltage source supplying for example a pulsed alternating voltage. Capacitors C1 and C2 form the pumping circuit while capacitors C3, C4 and C5 form the storage circuit.
In the steady state, capacitor C1 is charged to the maximum value of the alternating voltage UE as are the other capacitors C2 to C5. The desired high D.C. voltage UA is picked off at terminals 3 and 4, said D.C. voltage being composed of the D.C. voltages from capacitors C3 to C5. Terminal 3 and terminal 2 are connected to one pole of the alternating voltage source UE feeding the circuit, which can be at ground potential. In the circuit described here, a D.C. voltage UA can be picked off whose voltage value is approximately 3 times the maximum value of the pulsed alternating voltage UE. By using more than five capacitors, a correspondingly higher D.C. voltage can be obtained.
The individual capacitors are discharged by disconnecting D.C. voltage UA. However, they are constantly being recharged by the electrical energy supplied by the alternating voltage source UE, so that the voltage multiplier can be continuously charged on the output side.
According to the invention, in this preferred embodiment, capacitor C1 and/or C2 in the pumping circuit are designed so that they have a lower tendency toward internal discharges than any of the individual capacitors C3, C4 and C5 in the storage circuit.
It is evident that those skilled in the art, once given the benefit of the foregoing disclosure, may now make numerous other uses and modifications of, and departures from the specific embodiments described herein without departing from the inventive concepts. Consequently, the invention is to be construed as embracing each and every novel feature and novel combination of features present in, or possessed by, the apparatus and techniques herein disclosed and limited solely by the scope and spirit of the appended claims.
Inventors:Petrick, Paul (Landshut, DT)
Schwedler, Hans-peter (Landshut, DT)
Holzer, Alfred (Schonbrunn, DT)
ERNST ROEDERSTEIN SPEZIALFABRIK
US Patent References:
3714528 ELECTRICAL CAPACITOR WITH FILM-PAPER DIELECTRIC 1973-01-30 Vail
3699410 SELF-HEALING ELECTRICAL CONDENSER 1972-10-17 Maylandt
3463992 ELECTRICAL CAPACITOR SYSTEMS HAVING LONG-TERM STORAGE CHARACTERISTICS 1969-08-26 Solberg
3457478 WOUND FILM CAPACITORS 1969-07-22 Lehrer
3363156 Capacitor with a polyolefin dielectric 1968-01-09 Cox
2213199 Voltage multiplier 1940-09-03 Bouwers et al.
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