The CHASSIS FM 100-20 CKVS
was fitted in many models type from BLAUPUNKT and SIEMENS brand types.The CHASSIS CHASSIS FM 100-20 CKVS is developed by SIEMENS/BLAUPUNKT under joint venture with BOSCH.
This chassis is a complex type and it employs high quality components and it is highly engineered.
You will not find a dry joint on these chassis, soldering are Excellent even after 40 Years.
Was
highly reliable but the Line output EHT Transformer was failing Very
often causing from defocusing of picture to EHT discarge and even a no
start of the tellye at all.Basically the EHT Bleeder output was going "off limits" during aging landing to abnormal or no function at all.
Even the HR-DIEMEN replacement was failing since it was too much an exact replica !!!!!!
Even synchronization IC uses Hybrid IC Technology on Ceramic substrate.
And the Frame deflection driving / control circuitry IC uses Hybrid IC Technology on Ceramic substrate.
On a ceramic substrate, spiral-type inductors of a single layer wiring of a metal thin film are provided and respectively connected to a wiring pattern formed on another face of the substrate via through holes. A semiconductor chip is flip-chip mounted on the substrate in a face-down manner. On the face of the semiconductor chip, capacitors composed of a highly dielectric material, resistors formed by an ion implantation method or a thin-film forming method, and FETs are provided, respectively. Interconnection between the substrate and an external circuit board is achieved employing terminals formed at end faces of the substrate. The terminals have a concave shape with respect to the end face of the substrate. Thus, there is no need to use a package, and miniaturization and reduction in cost of a high-performance hybrid IC is achieved.
1. A hybrid IC comprising:
a substrate including a front face, a back face opposite the front face, and side faces interposed between the front face and the back face which define an outer perimeter of the substrate;
at least one inductor formed on at least one of the front face and the back face of the substrate;
a semiconductor chip mounted on the front face of the substrate by flip-chip bonding;
at least one terminal formed in a predetermined portion of the side faces of the substrate,
wherein the semiconductor chip comprises a plurality of circuit elements provided therein, at least one of the plurality of circuit elements being an MIM capacitor having a metal-insulation film-metal (MIM) structure, the insulation film being composed of a highly dielectric material.
2. A hybrid IC according to claim 1 further comprising at least one matching circuit for matching an input signal to the circuit elements provided inside the semiconductor chip, the matching circuit comprising at least one inductor.
3.
A hybrid IC according to claim 2, wherein a wiring pattern is formed of
a single metal layer on both the front and back faces of the substrate,
the wiring patterns on the respective front and back faces of the
substrate being interconnected with each other via through holes, and
the at least one inductor comprised in the matching circuit is formed in
the wiring pattern on one of the respective front and back faces of the
substrate.
4. A hybrid IC according to claim 2,
wherein the matching circuit is constituted only by inductors and
comprises at least one serial inductor and at least one parallel
inductor.
5. A hybrid IC according to claim 4, wherein
the parallel inductor comprised in the matching circuit is a spiral-type
inductor, outermost wiring of the spiral-type inductor being grounded.
6.
A hybrid IC according to claim 2, wherein the inductors comprised in
the matching circuit are a spiral-type inductor or a meander-type
inductor.
7. A hybrid IC according to claim 2, wherein
the matching circuit comprises an inductor and a capacitor, the
capacitor being formed inside the semiconductor chip.
8.
A hybrid IC according to claim 7, wherein the inductor comprised in the
matching circuit is a spiral-type inductor or a meander-type inductor.
9.
A hybrid IC according to claim 1, wherein the at least one terminal
includes at least an RF terminal functioning as an input terminal for an
RF signal, an LO terminal functioning as an input terminal for an LO
signal, an IF terminal functioning as an output terminal for an IF
signal, a ground terminal, and a supply terminal.
---------------------------------------
BLAUPUNKT MONTANA IP 32 STEREO VT COLOR (7 664 880) CHASSIS FM 100-20 CKVS POWER SUPPLY is based on TDA4600 (SIEMENS).
++++
Siemens Co., "Switched-Mode P
ower Supplies Using the TDA 4600", 2/81, pp. 6-15.
Funkschau 1975, "Ein Sperrwandler-Netzmodul mit Netztrennung", Dangschat et al., pp. 40 to 43.
"Schaltnetzteile", by Wuestehube et al., pp. 182 to 183.
"Schaltnetzteile mit der IS TDA 4600", Siemens publication, pp. 6 and 7.
The low cost, simplicity of design and intrinsic efficiency of flyback transformers have made them a popular solution for power supp
The
low cost, simplicity of design and intrinsic efficiency of flyback
transformers have made them a popular solution for power supply designs
of below 100W to 150W. Other advantages of the flyback transformer over
circuits with similar topology include isolation between primary and
secondary and the ability to provide multiple outputs and a choice of
positive or negative voltage for the output.
Flyback transformer, or,
line output transformers are a part of the power supplies in cathode
ray tubes. The flyback transformer generates a high voltage, as needed
by the CRT display or similar devices (e.g. plasma lamps). A flyback
transformer generates a voltage between a few kilovolts to 50 kilovolts
and uses high frequency switched currents between 17 kHz and 50 kHz.
The
chief difference between a flyback transformer and main/audio
transformer is that flybacks transfer as well as store energy, for a
just a fraction of an entire switching period. The secret behind that is
the coil winding on a ferrite core that has an air gap; it increases
the magnetic circuit reluctance for storing the energy.
The
reason it is called a flyback transformer is because the primary winding
uses a relatively low-voltage saw-tooth wave. The wave gets
strengthened first and then gets switched off abruptly; this causes the
beam to fly back from right to left on the display.
Applications
Cathode ray tube.
Televisions.
Plasma Lamps.
Any display requiring high voltage to operate and much more.
Siemens "Switched-Mode Power Supplies Using the TDA 4600":
A switching mode power supply (SMPS) may be used as an apparatus for
supplying power to electronic products. The SMPS converts input
alternating current (AC) voltages and outputs static voltages to operate
electronic products.The present invention relates to a switched-mode power supply. Such a
switched-mode power supply operates on the flyback converter principle,
in which a switching transistor is switched through during a switched-on
phase and magnetization is in consequence built up in a transformer,
and the switching transistor is switched off during a switched-off phase
and the magnetization is dissipated again via coupled windings of the
transformer.
In a typical switch mode power supply (SMPS) of a television receiver,
for example, the AC mains supply voltage is coupled directly to a bridge
rectifier for producing an unregulated direct current (DC) input supply
voltage that is, for example, referenced
to a common conductor,
referred to as "hot" ground, and that is conductively isolated from the
cold ground conductor. A pulse width modulator controls the duty cycle
of a chopper transistor switch that applies the unregulated supply
voltage across a primary winding of an isolating flyback transformer. In
principle a switched-mode power supply comprises at least the
following components: a switch, an inductor, a rectifier, capacitor and a
load. The load may be considered as a resistance which is in parallel
with the capacitor. During the part of the period in which the switch
conducts a current originating from the input voltage source passes
through the inductor so that energy which is derived from this source is
stored in the inductor. During the other part of the period, in which
the switch is not conducting, the energy stored in the inductor produces
a current through the rectifier which current recharges the capacitor
and, consequently, replenishes the energy losses caused by the load. By
the adjustment or control of the conducting period of the switch
relative to the cycle, the output D.C. voltage across the load can be
independent of variations of the input D.C. voltage, for example, it can
be kept constant. Such variations are caused by, for example,
fluctuations in the electric AC supply where the input voltage is
derived therefrom by rectification. A
flyback voltage at a frequency that is determined by the modulator is
developed at a secondary winding of the transformer and is rectified to
produce a DC output supply voltage such as a voltage B+ that energizes a
horizontal deflection circuit of the television receiver. The primary
winding of the flyback transformer is, for example, conductively coupled
to the hot ground conductor. The secondary winding of the flyback
transformer and voltage B+ may be conductively isolated from the hot
ground conductor by the hot-cold barrier formed by the transformer. Such
a switched mode power supply is generally called SMPS. A SMPS as it
is commonly used, for example, in consumer devices like television
receivers, video recorders, audio equipments etc. generally includes a
main switching transistor connected in series with the primary winding
of a transformer, a base drive circuit for periodically switching said
switching transistor between ON and OFF, and a control circuit for
controlling the base drive current for said main switching transistor in
such a way that output voltages derived from several secondary windings
of said transformer are stabilized.On the other hand such a SMPS generally includes a protection circuit
for case of overloading or a short circuit or any other failures within
the operating voltages. Said protection circuit is needed since without
protection means the collector-emitter current of the main switching
transistor can reach excessively high values in case of a failure which
might damage said switching transistor or cause any other damages of
circuit components.
For some uses a D.C. isolation between the input voltage source and
the output voltage is absolutely required. This is the case, for
example, with power supplies of television receivers especially where it
is desirable to connect additional apparatus to the receiver, such as,
for example, video storage devices or television game circuits. A
switched-mode power supply is eminently suitable for this purpose as the
transformer which must effect that isolation passes signals which
usually have a much higher frequency, for example 15 to 20 kHz, than
those of the electric AC supply source so that said transformer may be
relatively small in size.
With a switched-mode power supply of
the flyback converter type the inductor of the converter can be
implemented in a simple manner as a transformer. A primary winding
thereof is connected in series with the switch between the terminals of
the input voltage source whereas a secondary winding is in series with
the rectifier. The publication "Philips Application Information" 472:
"properties of d.c.-to d.c. converters for switched-mode power supplies"
of Mar. 18, 1975 describes such a circuit. Of the three types the
flyback converter has the best control properties which is evidenced by
the formula which expresses the output voltage as a function of the
input voltage and of the ratio of the time of conduction of the switch
to the entire cycle. However, it should be noted that the entire energy
which is supplied to the load by a flyback converter must be passed on
by the transformer which imposes higher requirements both on the
transformer and, particularly, on the storage capacity thereof as well
as on the switch.
SIEMENS TDA 4600-2 TDA 4600-2D
ControlIer for Switched-Mode Power Supplies / BipolarlC
In
addition to their use with TV receivers and video recorders, the ICs
TDA 4600-2 and TDA 4600-2 D can be applied in power supplied of hi-fi
sets and active speakers due to their wide operational ranges and
superior voltage stability during high load changes.
Features
• Direct driving of switching transistor
• Low start-up current
• Reversing linear overload characteristic
• Collector current - proportional to base-current input
TDA 4600-2 Circuit description
During
start-up, normal and overload operations the TDA 4600-2; or -2D
regulates, controls and protects the switching transistor installed in
the flyback converter power supplies.
I) Start-up operation
The
start-up operation is divided into three consecutive phases: 1. An
internal reference voltage is built up which supplies the voltage
regulator and effects the charging of the coupling electrolytic
capaCitor and the switching transistor. During these procedures an 19
current less than 3.2 mA will be maintained, if the supply voltage Vg
does not exceed", 12 V. 2. At Vg '" 12 V an internal reference voltage
V1 = 4 V is suddenly released to provide all IC components with the
exception of the control logic with a thermally stable and
overload-resistant current. 3. In concurrence with the release of the
reference voltage the control logic is activated by an additional
stabilization circuit, and the IC is now ready for operation. Above
sequential start-up phases ensure the charging of the switching
transistor by the coupling electrolytic capacitor and subsequent
precision switching.
II) Normal operation
Zero passages
of the feedback coil are registered at pin 2 and forwarded to the
control logic. At pin 3 (input control, overload, and standby
recognition) the rectified amplitude variations of the feedback coil are
applied. The regulating (control) amplifier operates with an input
voltage of about 2 V and a current of about 1.4 mA. According to the
internal reference voltage, ttie operating region of the regulating
amplifier will be defined by the collector current simulation pin 4 and
the overload recognition. The simulation of the collector current is
generated by an external RC network at pin 4 and an internally set
voltage level. By increasing the capacitance (10 nFl, the collector
current of the switching transistor is increased as well and establishes
the desired control range. The control range extends between a 2 V
clamped dc voltage and an ac voltage rising as a sawtooth wave, which
may vary up to a maximum amplitude of 4 V (reference voltage). By
reducing the secondary load to 20 W, the switching frequency increases
to about 50 kHz at an almost constant pulse duty factor (on-time to
period approx. 1/3). During additional secondary load reduction to about
1 W, the switching frequency will change to approx. 70 kHz, while the
pulse duty factor falls to approx. 1/11. At the same time, the collector
peak current falls below 1 A. The output level of the regulating
(control) amplifier, the overload recognition, and the collector current
simulation are compared in the trigger and the control logic is
instructed accordingly. Pin 5 will provide additional blocking
alternatives, i.e. the output at pin 8 is blocked at a voltage of equal
to or less than 2.2 Vat pin 5. Based on the start-up circuit, the zero
crossing identification, and the trigger-activated release, the control
logic flipflops are set which control both the base current
amplification and shut-down. The base current amplifier forwards the
sawtooth voltage V 4 to pin 8. Also, a current feedback with an external
resistance of R "" 0.68 Q is inserted between pin 8 and pin 7. The
resistance value determines the maximum amplitude of the base current
for the switch ing transistor. III) Safety features The base current
shut-down, released by the control logic, clamps the output of pin 7 at
1.6 V and thus blocks the driving of the switching transistor. This
preventive method will go into effect, if the voltage at pin 9 falls
below typo 7.4 V or if voltages of less than typo 22 V are present at
pin 5. In case of short-circuited secondary windings in the SMPS, the
fault condition will be continuously monitored by the IC. With the load
completely removed from the secondary winding in the SMPS, the IC is set
at a small pulse duty factor. The total power consumption of the SMPS
is kept below n = 6 to 10 W during both operating conditions. After the
output has been blocked at a supply voltage Vg of less than or equal to
typo 7.4 V, an additional voltage reduction of .1V g = 0.6 V will switch
off the reference voltage (4 V).
Thermal resistance (only applicable to TDA 4600-2 D)
Standardized, ambience-related thermal resistance Rth JA 1 versus lateral length 1of a square
copper-clad cooling area (35 IJ.m copper lamination).
Rth JA
(I = 0) = 60 K/W
Tamb:S;; 70°C
Pv= 1 W
PCB in Ifertical position circuit in vertical position static air.
Measurement diagram for overload operations
Pin configuration
(TDA 4600-2: Plastic Power Package - 9 pin SIP package)
(TDA 4600-2D: Plastic 18 pin DIP package)
Pin No,
Function
1 Vre! output
2 Zero passage identification
3 Input regulating amplifier, overload amplifier
4 Collector current simulation
5 Possible connection for additional protective circuit
6 Ground
7 DC voltage output for charging the coupling capacitor
8 Pulse output - driving the switching transistor
9 Current supply input
only applicable to TDA 4600-2 D
10
11
12
13
14
interconnected (ground)
15
16
17
18
TDA4601 Operation. * The TDA4601 device is a single in line, 9 pin chip. Its predecessor was the TDA4600 device, the TDA4601 however has improved switching, better protection and cooler running. The (SIEMENS) TDA4601 power supply is a fairly standard parallel chopper switch mode type, which operates on the same basic principle as a line output stage. It is turned on and off by a square wave drive pulse, when switched on energy is stored in the chopper transformer primary winding in the form of a magnetic flux; when the chopper is turned off the magnetic flux collapses, causing a large back emf to be produced. At the secondary side of the chopper transformer this is rectified and smoothed for H.T. supply purposes. The advantage of this type of supply is that the high chopping frequency (20 to 70 KHz according to load) allows the use of relatively small H.T. smoothing capacitors making smoothing easier. Also should the chopper device go short circuit there is no H.T. output. In order to start up the TDA4601 I.C. an initial supply of 9v is required at pin 9, this voltage is sourced via R818 and D805 from the AC side of the bridge rectifier D801, also pin 5 requires a +Ve bias for the internal logic block. (On some sets pin 5 is used for standby switching). Once the power supply is up and running, the voltage on pin 9 is increased to 16v and maintained at this level by D807 and C820 acting as a half wave rectifier and smoothing circuit. PIN DESCRIPTIONS Pin 1 This is a 4v reference produced within the I.C. Pin 2 This pin detects the exact point at which energy stored in the chopper transformer collapses to zero via R824 and R825, and allows Q1 to deliver drive volts to the chopper transistor. It also opens the switch at pin 4 allowing the external capacitor C813 to charge from its external feed resistor R810. Pin 3 H.T. control/feedback via photo coupler D830. The voltage at this pin controls the on time of the chopper transistor and hence the output voltage. Normally it runs at Approximately 2v and regulates H.T. by sensing a proportion of the +4v reference at pin 1, offset by conduction of the photo coupler D830 which acts like a variable resistor. An increase in the conduction of transistor D830 and therefor a reduction of its resistance will cause a corresponding reduction of the positive voltage at Pin 3. A decrease in this voltage will result in a shorter on time for the chopper transistor and therefor a lowering of the output voltage and vice versa, oscillation frequency also varies according to load, the higher the load the lower the frequency etc. should the voltage at pin 3 exceed 2.3v an internal flip flop is triggered causing the chopper drive mark space ratio to extend to 244 (off time) to 1 (on time), the chip is now in over volts trip condition. Pin 4 At this pin a sawtooth waveform is generated which simulates chopper current, it is produced by a time constant network R810 and C813. C813 charges when the chopper is on and is discharged when the chopper is off, by an internal switch strapping pin 4 to the internal +2v reference, see Fig 2. The amplitude of the ramp is proportional to chopper drive. In an overload condition it reaches 4v amplitude at which point chopper drive is reduced to a mark-space ratio of 13 to 1, the chip is then in over current trip. The I.C. can easily withstand a short circuit on the H.T. rail and in such a case the power supply simply squegs quietly. Pin 4 is protected by internal protection components which limit the maximum voltage at this pin to 6.5v. Should a fault occur in either of the time constant components, then the cho
pper transistor will probably be destroyed. Pin 5 This pin can be used for remote control on/off switching of the power supply, it is normally held at about +7v and will cause the chip to enter standby mode if it falls below 2v. Pin 6 Ground. Pin 7 Chopper switch off pin. This pin clamps the chopper drive voltage to 1.6v in order to switch off the chopper. Pin 8 Chopper base current output drive pin. Pin 9 L.T. pin, approximately 9v under start-up conditions and 16v during normal running, Current consumption of the I.C. is typically 135mA. The voltage at this pin must reach 6.7v in order for the chip to start-up.
Control lC for Switched-Mode Power Supplies THE SIEMENS TDA4600-3
Preliminary data SIP9 TYPE IC
The
integrated circuit TDA 4600-3 is designed for driving, controlling, and
protecting the switching transistor in self-oscillating flyback
converter power supplies. In addition to its application in TV receivers
and video tape recorders, this IC can also be used in hifi devices and
active loud speakers due to its wide control range and high voltage
stability.
•Direct control of the switching transistor
•Low start-up current
•Reversing linear overload characteristic
•Base current drive proportional to collector current
SIEMENS TDA4600-3 Description of functions and application:
This
IC is designed for driving a bipolar power transistor and for
performing all necessary control and protective functions in
self-oscillating flyback converter power supplies. Owing to the IC's
outstanding voltage stability, which is maintained even at major load
fluctuations, the IC is suited for consumer as well as for industrial
applications. The rectified line voltage is applied to the series
connection of the power transistor and the primary winding of the
flyback transformer. During the on-phase of the transistor, energy is
stored in the primary winding and released to the consumer via the
secondary winding. The IC controls the power transistor in such a way
that the secondary voltage is kept at a constant value independently of
changes in the line voltage or load. The control information required is
derived from the rectified line voltage during the on-phase as well as
from a secondary winding during the off-phase. Load differences are
compensated by altering the frequency, line voltage fluctuations are
additionally counteracted by changing the pulse duty factor. This
results in the following load-dependent modes of the SMPS:
- Open-loop or small load: Secondary voltage slightly above the desired value
- Control: Load-independent secondary voltage
-
Overload: In case of a secondary overload or short circuit, the
secondary voltage is decreased at the point of return as a function of
the load current, following a reversing characteristic.
Description of use
A
flyback converter designed for color TV sets, applicable between 30
Wand 120 Wand for line voltages ranging from 160 V to 270 V, is
described on one of the following pages. On the subsequent pages the
major pulses and diagrams can be found. The line voltage is rectified by
bridge rectifier Gr1 and smoothed by C3. During start-up the IC current
is supplied via the combination Gr2+Rl1 while, in the post-transient
condition, it is additionally supplied via winding 13/11 and rectifier
Gr3. The size of filter capacitor Cg determines the turn-on behavior.
Switching transistor T1 is a BU 208. Parallel capacitance Cll and
primary winding 1/7 form a resonant circuit, thus limiting the frequency
and amplitude of collector-emitter voltage overshoots upon turn-off of
n. R12 , Gr4, C 10, R 15 and Dr2 are elements to improve the switching
behavior of T1. The inductance of the primary winding determines the
current increase in T1. This sawtooth- shaped current rise is simulated
at network R5CS and applied to pin 4 of the IC. Depending of the
dimensions of the primary inductance, timing element R5CS is to be
adapted to the current rise angle in T1. Thus, during the on-phase, the
IC receives control information at pin 4 in the form of the simulated
energy content of the primary winding as a function of the line voltage
versus time.
Fluctuations at pin 3 are recognized by control winding 9/15. This measure requires fixed coupling to secondary winding 2/16. The control winding is also used for feedback and permits self-oscillating conditions in parallel circuit C11 /primary inductance if power transistor T1 is blocked. In this way the maximum open-loop frequency is determined. The control voltage required at pin 3 is rectified by diode Gr5 and smoothed by capacitor C6• Furthermore, resistor Rs and C6 form a timing element. Due to these circumstances, fast changes in the control voltage are filtered out, i.e. the controlling element does not respond until several periods have occured. The secondary voltage can be set by means of the voltage divider formed of resistors Ry, R 6, R3 and R 2
• Reason: in the IC the control voltage at pin 3 is compared with a stable, internal reference voltage. According to the result of this comparison, frequency and pulse duty factor are corrected until the secondary voltage selected by Ry has established itself. In the case of overload or short circuit on the secondary side, only a small voltage portion is passed to control winding 9/15; the reference voltage at pin 1 becomes directly active at control input pin 3 and activates an overload amplifier (point of return). which drives power transistor T1 down to a smaller pulse duty factor. The line power output is reduced to 6 VA. For all operating ranges of the SMPS, the zero passages of the voltage at the control winding contain information on pulse duty factor and switching frequency of switching transistor T1, or on the open-loop frequency. Conditioning of the corresponding signal at pin 2 is performed by series resistor R 4 , and by integrated limiter diodes. Timing network RS C 4 suppresses HF spikes at pin 2.
Before the line voltage drops below its
minimum value, the SMPS must be switched off in order to obtain defined
on/off conditions. Winding 11/13 is configured in such a way that the
voltage at pin 9 changes linearly with the rectified line voltage. The
IC goes into on-state if Vg ~12.3 V, and into off-state if Vg:S; 5.7 V.
The drive of the power transistor will be blocked as soon as V g :S; 6.7
V. Pin 5 is connected to pin 9 via resistor R g, since the IC's output
is not enabled until voltages V5 ~2.7 V prevail. On the secondary side
start-up voltages from V'sec to V4sec are available. If switch S1 is put
into open position, standby is set automatically, with a secondary
effective power of approx. 3 W being tapped from winding 12/16.
Resistors R'3 and R'4 form a basic load of voltages V'sec and V2sec.
They contribute to maintaining standby conditions, i.e. Vsec rise :S;
20%. Capacitors C'2 through C'5 prevent spikes caused by reversing
rectifiers Gr6 and Gr9. The secondary voltages are smoothed by the
charging electrolytic capacitors C'6 through C,g.
After the line voltage has been applied at time to, the following voltages start to increase:
- V g according to the half-cycle charge via R".
- V 4 to V 4 max (typ. 6.2 V)
- V5 to the value determined by Rg
In
this case the current consumption of the IC is smaller than 3.2 mA. If
Vg reaches the threshold 12.3 V, the IC will switch on the reference
voltage of pin 1. The current consumption rises to typically 80 mA. The
primary current voltage transformer adjusts V4 down to VREF/2 and the
start pulse generator produces the start pulse. Feedback to pin 2 starts
a subsequent pulse and so forth. The width of all pulses, including the
start pulse, is controlled by the control voltage at pin 3. During
turn-on the control voltage corresponds to standby conditions, i.e. V3 =
VREF/2 + 50 mV. The IC begins with narrow pulses, which become wider
depending on the feedback control voltage. Instantly, the IC operates in
the control mode. The control loop is in a post-transient state. If,
during start-up, voltage V g drops below the turn-off threshold V g :S;
7.8 V, the start- up phase will be terminated (pin 8 is switched to
Low). Since the IC remains in the on-state, Vg drops further to Vg:S;
5.7 V. The IC switches to the off-state, Vg is now able to rise again
and a new start-up phase may begin. After the IC has been started, it
will operate in the control mode. The voltage at pin 3 is typically
VREF/2 + 0.2 V. If the output is loaded, the control amplifier allows
wider charge pulses to occur (Va = H). The peak value of the voltage at
pin 4 rises to V 4 = V REF• Upon an increase in the secondary load the
overload amplifier begins adjusting the pulse width down. Since altering
of the pulse width is reversed, this is referred to as the reverse
point of the SMPS or point of return. In case of a short circuit on the
secondary side, the overload amplifier will adjust the pulse width to
typically 1.6 ~s and reduces the pulse duty factor to < 1 :100. The
SMPS decreases the line power consumption to typically 6 VA. A small
pulse duty factor entails a drop in supply voltage V g below the
threshold V g :S; 6.7 V causing a drive interrupt of the switching
transistor and a continued drop of supply voltage V g. If supply voltage
Vg:S; 5.7 V, the IC is turned off and enters into a new start-up phase.
This intermittent periodic duty operation is continued until the short circuit on the secondary side has been eliminated. If the secondary side is unloaded (standby), the control pulse width becomes narrower. The frequency rises. During open-loop operation the approximate natural frequency of the system (75 kHz) is obtained; pulse duty factor 1 :11. The rise of the secondary voltages is approx. 20%. If resistors R131R14 were absent, the IC would have to perform adjustment beyond the natural frequency of the system, with the zero passage identification only recognizing every 2nd, 3rd or 4th zero passage as a pulse start, i.e. the frequency would divide down to the 2nd, 3rd or 4th subharmonic. The pulse duty factor is thus diminished to 1 : 22, 1 : 33, or 1 : 44, respectively. The pulse width remains constant at approx. 1.2 j.l.sec. A certain small pulse duty factor causes supply voltage V9 to drop below the threshold voltage V 9 ::;: 6.7 V. Then, the interrogation intermittent periodic duty operation begins as already described for the short circuit case. Constant open-loop operation will not continue until resistors R131R14 have been loaded.
SIEMENS TDA4600-3 pin Circuit description:
Pin 1 :Reference voltage output, overload-protected.
I 1max
= 5 mA. All modules, excluding the IC's output stage, are supplied by the
internal reference voltage.
Pin 2:The zero passage identification driving the control logic identifies the discharged
status of the transformer at the zero passage of voltage V 2 from negative to positive
values and enables the logic for pulse start, which is driven by trigger start.
Pin 3:The control voltage supplied to this pin is compared with two stable reference
potentials in the control amplifier, in overload identification and during standby.
The outputs of these stages operate onto the trigger hold, thus terminating the
pulse.
Pin 4:A voltage proportional to the collector current of the switching transistor is generated
on the basis of the external RC combination in conjunction with the collector
current simulation block. This voltage introduces the beginning of a pulse at a stable
voltage via trigger start and determines at a second stable voltage (reverse point)
the absolute maximum pulse (with respect to time length) in trigger hold. At the
same time the rise angle of the voltage proportional to the collector current of the
switching transistor is impressed onto the base current amplifier, and, in accordance
with the smallest current amplification B of the switching transistor to be expected,
the base of the switching transistor is driven via pin 8.
Pin 5:If a voltage :?2.7 V is applied, the control logic is enabled via the trigger. Pins 7/8
are driven by the coupling capacitor charge circuit and the base current. In case
a voltage ~ 1.8 V prevails, base current switch-off pin 7 is clamped at a voltage
V 7 ~1.3 V; driving of the switching transistor is impossible. The IC will not be
enabled again until the voltage at pin 9 has dropped below 5.7 V, the IC has
been turned off and the SMPS has entered a new start-up phase.
Pin 6:GND
Pin 7/8:Via the voltage controller and the coupling capacitor charge circuit, the output
stage of the IC is dc-adjusted to the switching transistor. The switching transistor
is driven via a base current amplifier and pin 8, while it is blocked via the basic
current switch-off and pin 7.
Pin 9:Current supply of the IC.
 |
| TDA4600-3 BLOCK DIAGRAM |
 |
| SIEMENS TDA4600-3 MEASUREMENT APPLICATION CIRCUIT |
 |
| SIEMENS TDA4600-3 APPLICATION CIRCUIT |
THE SIEMENS TDA 4600 Semiconductor circuit description for supplying power to electrical
equipment, comprising a transformer having a primary winding connected,
via a parallel connection of a collector-emitter path of a transistor
with a first capacitor, to both outputs of a rectifier circuit supplied,
in turn, by a line a-c voltage; said transistor having a base
controlled via a second capacitor by an output of a control circuit
acted upon, in turn by the rectified a-c line voltage as actual value
and by a reference voltage; said transformer having a first secondary
winding to which the electrical equipment to be supplied is connected;
said transformer having a second secondary winding with one terminal
thereof connected to the emitter of said transistor and the other
terminal thereof connected to an anode of a first diode leading to said
control circuit; said transformer having a third secondary winding with
one terminal thereof connected, on the one hand, via a series connection
of a third capacitor with a first resistance, to the other terminal of
said third secondary winding and connected, on the other hand, to the
emitter of said transistor, the collector of which is connected to said
primary winding; a point between said third capacitor and said first
resistance being connected to the cathode of a second diode; said
control circuit having nine terminals including a first terminal
delivering a reference voltage and connected, via a voltage divider
formed of a third and fourth series-connected resistances, to the anode
of said second diode; a second terminal of said control circuit serving
for zero-crossing identification being connected via a fifth resistance
to said cathode of said second diode; a third terminal of said
control-circuit serving as actual value input being directly connected
to a divider point of said voltage divider forming said connection of
said first terminal of said control circuit to said anode of said second
diode; a fourth terminal of said control circuit delivering a sawtooth
voltage being connected via a sixth resistance to a terminal of said
primary winding of said transformer facing away from said transistor; a
fifth terminal of said control circuit serving as a protective input
being connected, via a seventh resistance to the cathode of said first
diode and, through the intermediary of said seventh resistance and an
eighth resistance, to the cathode of a third diode having an anode
connected to an input of said rectifier circuit; a sixth terminal of
said control circuit carrying said reference potential and being
connected via a fourth capacitor to said fourth terminal of said control
circuit and via a fifth capacitor to the anode of said second diode; a
seventh terminal of said control circuit establishing a potential for
pulses controlling said transistor being connected directly and an
eighth terminal of said control circuit effecting pulse control of the
base of said transistor being connected through the intermediary of a
ninth resistance to said first capacitor leading to the base of said
transistor; and a ninth terminal of said control circuit serving as a
power supply input of said control circuit being connected both to the
cathode of said first diode as well as via the intermediary of a sixth
capacitor to a terminal of said second secondary winding as well as to a
terminal of said third secondary winding.
Such a blocking oscillator switching
power supply is described in the German periodical, "Funkschau" (1975)
No. 5, pages 40 to 44. It is well known that the purpose of such a
circuit is to supply electronic equipment, for example, a television
set, with stabilized and controlled supply voltages. Essential for such
switching power supply is a power switching transistor i.e. a bipolar
transistor with high switching speed and high reverse voltage. This
transistor therefore constitutes an important component of the control
element of the control circuit. Furthermore, a high operating frequency
and a transformer intended for a high operating frequency are provided,
because generally, a thorough separation of the equipment to be supplied
from the supply naturally is desired. Such switching power supplies may
be constructed either for synchronized or externally controlled
operation or for non-synchronized or free-running operation. A blocking
converter is understood to be a switching power supply in which power is
delivered to the equipment to be supplied only if the switching
transistor establishing the connection between the primary coil of the
transformer and the rectified a-c voltage is cut off. The power
delivered by the line rectifier to the primary coil of the transformer
while the switching transistor is open, is interim-stored in the
transformer and then delivered to the consumer on the secondary side of
the transformer with the switching transistor cut off. In the blocking converter described in the aforementioned reference in the literature, "Funkschau" (1975), No. 5, Pages 40 to 44, the power switching transistor is connected in the manner defined in the introduction to this applic
ation. In addition, a so-called starting
circuit is provided. Because several diodes are generally provided in
the overall circuit of a blocking oscillator according to the definition
provided in the introduction hereto, it is necessary, in order not to
damage these diodes, that due to the collector peak current in the case
of a short circuit, no excessive stress of these diodes and possibly
existing further sensitive circuit parts can occur. Considering the operation of a blocking oscillator, this means that, in the event of a short circuit, the number of collector current pulses per unit time must be reduced. For this purpose, a control and regulating circuit is provided. Simultaneously, a starting circuit must bring the blocking converter back to normal operation when the equipment is switched on, and after disturbances, for example, in the event of a short circuit. The starting circuit shown in the literature reference "Funkschau" on Page 42 thereof, differs to some extent already from the conventional d-c starting circuits. It is commonly known for all heretofore known blocking oscillator circuits, however, that a thyristor or an equivalent circuit replacing the thyristor is essential for the operation of the control circuit.
It is accordingly an object of the invention to provide another starting circuit. It is a further object of the invention to provide a possible circuit for the control circuit which is particularly well suited for this purpose. It is yet another object of the invention to provide such a power supply which is assured of operation over the entire range of line voltages from 90 to 270 V a-c, while the secondary voltages and secondary load variations between no-load and short circuit are largely constant.
With the foregoing and other objects in view, there is provided, in accordance with the invention, a blocking oscillator-type switching power supply for supplying power to electrical equipment wherein a primary winding of a transformer, in series with an emitter-collector path of a first bipolar transistor, is connected to a d-c voltage obtained by rectification of a line a-c voltage fed-in via two external supply terminals, a secondary winding of the transformer being connectible to the electrical equipment for supplying power thereto, the first bipolar transistor having a base controlled by the output of a control circuit acted upon, in turn, by the rectified a-c line voltage as actual value and by a set-point transmitter, and including a starting circuit for further control of the base of the first bipolar transistor, including a first diode in the starting circuit having an anode directly connected to one of the supply terminals supplied by the a-c line voltage and a cathode connected via a resistor to an input serving to supply power to the control circuit, the input being directly connected to a cathode of a second diode, the second diode having an anode connected to one terminal of another secondary winding of the transformer, the other secondary winding having another terminal connected to the emitter of the first bipolar transmitter.
In accordance with another feature of the invention, there is provided a second bipolar transistor having the same conduction type as that of the first bipolar transistor and connected in the starting circuit with the base thereof connected to a cathode of a semiconductor diode, the semiconductor diode having an anode connected to the emitter of the first bipolar transistor, the second bipolar transistor having a collector connected via a resistor to a cathode of the first diode in the starting circuit, and having an emitter connected to the input serving to supply power to the control circuit and also connected to the cathode of the second diode which is connected to the other secondary winding of the transformer.
In accordance with a further feature of the invention, the base of the second bipolar transistor is connected to a resistor and via the latter to one pole of a first capacitor, the anode of the first diode being connected to the other pole of the first capacitor.
In accordance with an added feature of the invention, the input serving to supply power to the control circuit is connected via a second capacitor to an output of a line rectifier, the output of the line rectifier being directly connected to the emitter of the first bipolar transistor.
In accordance with an additional feature of the invention, the other secondary winding is connected at one end to the emitter of the first bipolar transistor and to a pole of a third capacitor, the third capacitor having another pole connected, on the one hand, via a resistor, to the other end of the other secondary winding and, on the other hand, to a cathode of a third diode, the third diode having an anode connected via a potentiometer to an actual value input of the control circuit and, via a fourth capacitor, to the emitter of the first bipolar transistor.
In accordance with yet another feature of the invention, the control circuit has a control output connected via a fifth capacitor to the base of the first bipolar transistor for conducting to the latter control pulses generated in the control circuit.
In accordance with a concomitant feature of the invention, there is provided a sixth capacitor shunting the emitter-collector path of the first transistor.
Other features which are considered as characteristic for the invention are set forth in the appended claim.
Although the invention is illustrated and described herein as embodied in a blocking oscillator type switching power supply, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings, in which:
FIGS. 1 and 2 are circuit diagrams of the blocking oscillator type switching power supply according to the invention; and
FIG. 3 is a circuit diagram of the control unit RS of FIGS. 1 and 2.
The cathode of the diode D1 and, therewith, the power supply terminal 9 of the control circuits RS are furthermore connected to one pole of a capacitor C3, the other pole of which is connected to the output 3' of the rectifier G. The capacitance of this capacitor C3 thereby smoothes the positive half-wave pulses and serves simultaneously as an energy storage device during the starting period. Another secondary windi
ng
III of the transformer Tr is connected by one of the leads thereof
likewise to the emitter of the first transistor T1, and by the other
lead thereof via a resistor R2, to one of the poles of a further
capacitor C4, the other pole of which is connected to the
first-mentioned lead of the other secondary winding III. This second
pole of the capacitor C4 is simultaneously connected to the output 3' of
the rectifier circuit G and, thereby, via the capacitor C3, to the
cathode of the diode D1 driven by the secondary winding II of the
transformer Tr as well as to the power supply input 9 of the control
circuit RS and, via a resistor R9, to the cathode of a second diode D4.
The second pole of the capacitor C4 is simultaneously connected directly
to the terminal 6 of the control circuit RS and, via a further
capacitor C 6, to the terminal 4 of the control circuit RS as well as,
additionally, via the resistor R6, to the other output 4' of the
rectifier circuit G. The other of the poles of the capacitor C4 acted
upon by the secondary winding II is connected via a further capacitor C5
to a node, which is connected on one side thereof, via a variable
resistor R4, to the terminals 1 and 3 of the control circuit RS, with
the intermediary of a fixed resistor R5 in the case of the terminal 1.
On the other side of the node, the latter and, therefore, the capacitor
C5 are connected to the anode of a third diode D2, the cathode of which
is connected on the one hand, to the resistor R2 mentioned hereinbefore
and leads to the secondary winding III of the transformer Tr and, on the
other hand, via a resistor R3 to the terminal 2 of the control circuit
RS.The nine terminals of the control circuit RS have the following purposes or functions:
Terminal 1 supplies the internally generated reference voltage to ground i.e. the nominal or reference value required for the control or regulating process;
Terminal 2 serves as input for the oscillations provided by the secondary winding III, at the zero point of which, the pulse start of the driving pulse takes place;
Terminal 3 is the control input, at which the existing actual value is communicated to the control circuit RS, that actual value being generated by the rectified oscillations at the secondary winding III;
Terminal 4 is responsive to the occurrence of a maximum excursion i.e. when the largest current flows through the first transistor T1 ;
Terminal 5 is a protective input which responds if the rectified line voltage drops too sharply; Terminal 6 serves for the power supply of the control process and, indeed, as ground terminal;
Terminal 7 supplies the d-c component required for charging the coupling capacitor C2 leading to the base of the first transistor T1 ;
Terminal 8 supplies the control pulse required for the base of the first transistor T1 ; and
Terminal 9 serves as the first terminal of the power supply of the control circuit RS.
Further details of the control circuit RS are described hereinbelow.
The capacity C3 smoothes the positive half-wave pulses which are provided by the secondary winding II, and simultaneously serves as an energy storage device during the starting time. The secondary winding III generates the control voltage and is simultaneously used as feedback. The time delay stage R2 /C4 keeps harmonics and fast interference spikes away from the control circuit RS. The resistor R3 is provided as a voltage divider for the second terminal of the control circuit RS. The diode D2 rectifies the control pulses delivered by the secondary winding III. The capacity C5 smoothes the control voltage. A reference voltage Uref, which is referred to ground i.e. the potential of terminal 6 is present at the terminal 1 of the control circuit RS. The resistors R4 and R5 form a voltage divider of the input-difference control amplifier at the terminal 3. The desired secondary voltage can be set manually via the variable resistor R4. A time-delay stage R6 /C6 forms a sawtooth rise which corresponds to the collector current rise of the first bipolar transistor T1 via the primary winding I of the transformer Tr. The sawtooth present at the terminal 4 of the control circuit RS is limited there between the reference voltage 2 V and 4 V. The voltage divider R7 /R8 (FIG. 2), brings to the terminal 5 of the control circuit RS the enabling voltage for the drive pulse at the output 8 of the control circuit RS.
The diode D4, together with the resistor R9 in cooperation with the diode D1 and the secondary winding II, forms the starting circuit provided, in accordance with the invention. The operation thereof is as follows:
In FIG. 2, there is shown a further embodiment of the circuit for a blocking oscillator type switching power supply, according to the invention, as shown in FIG. 1. Essential for this circuit of FIG. 2 is the presence of a second bipolar transistor T2 of the type of the first bipolar transistor T1 (i.e. in the embodiments of the invention, an npn-transistor), which forms a further component of the starting circuit and is connected with the collector-emitter path thereof between the resistor R9 of the starting circuit and the current supply input 9 of the control circuit RS. The base of this second transistor T2 is connected to a node which leads, on the one hand, via a resistor R10 to one electrode of a capacitor C7, the other electrode of which is connected to the anode of the diode D4 of the starting circuit and, accordingl
y,
to the terminal 1' of the supply input of the switching power supply G.
On the other hand, the last-mentioned node and, therefore, the base of
the second transistor T2 are connected to the cathode of a Zener diode
D3, the anode of which is connected to the output 3' of the rectifier G
and, whereby, to one pole of the capacitor C3, the second pole of which
is connected to the power supply input 9 of the control circuit RS as
well as to the cathode of the diode D1 and to the emitter of the second
transistor T2. In other respects, the circuit according to FIG. 2
corresponds to the circuit according to FIG. 1 except for the resistor
R11 which is not necessary in the embodiment of FIG. 2, and the missing
connection between the resistor R9 and the cathode of the diode D1,
respectively, and the protective input 5 of the control circuit RS.
Because of the time constant R9.C3, several positive half-waves are necessary in order to increase the voltage U9 at the supply terminal 9 of the control circuit RS to such an extent that the control circuit RS is energized. During the negative sine half-wave, a partial energy chargeback takes place from the capacitor C3 via the emitter-base path of the transistor T2 of the starting circuit and via the resistor R10 and the capacitor C7, respectively, into the supply network. At approximately 2/3 of the voltage U9, which is limited by the diode D3, the control circuit RS is switched on. At the terminal 1 thereof, the reference voltage Uref then appears. In addition, the voltage divider R5 /R4 becomes effective. At the terminal 3, the control amplifier receives the voltage forming the actual value, while the first bipolar transistor T1 of the blocking-oscillator type switching power supply is addressed pulsewise via the terminal 8.
Because the capacitor C6 is charged via the resistor R6, a higher voltage than Uref is present at the terminal 4 if the control circuit RS is activated. The control voltage then discharges the capacitor C6 via the terminal 4 to half the value of the reference voltage Uref, and immediately cuts off the addressing input 8 of the control circuit RS. The first driving pulse of the switching transistor T1 is thereby limited to a minimum of time. The power for switching-on the control circuit RS and for driving the transistor T1 is supplied by the capacitor C3. The voltage U9 at the capacitor C3 then drops. If the voltage U9 drops below the switching-off voltage value of the control circuit RS, the latter is then inactivated. The next positive sine half-wave would initiate the starting process again.
By switching the transistor T1, a voltage is transformed in the secondary winding II of the transformer Tr. The positive component is rectified by the diode D1, recharing of the capacitor C3 being thereby provided. The voltage U9 at the output 9 does not, therefore, drop below the minimum value required for the operation of the control circuit RS, so that the control circuit RS remains activated. The power supply continues to operate in the rhythm of the existing conditions. In operation, the voltage U9 at the supply terminal 9 of the control circuit RS has a value which meets the condition U9 >[UDs -UBE (T2)], so that the transistor T2 of the starting circuit remains cut off.
For the internal layout of the control circuit RS, the construction shown, in particular, from FIG. 3 is advisable. This construction is realized, for example, in the commercially available type TDA 4600 (Siemens AG).
The block diagram of the control circuit according to FIG. 3
shows
the power supply thereof via the terminal 9, the output stage being
supplied directly whereas all other stages are supplied via Uref. In the
starting circuit, the individual subassemblies are supplied with power
sequentially. The d-c output voltage potential of the base current gain
i.e. the voltage for the terminal 8 of the control circuit RS, and the
charging of the capacitor C2 via the terminal 7 are formed even before
the reference voltage Uref appears. Variations of the supply voltage U9
at terminal 9 and the power fluctuations at the terminal 8/terminal 7
and at the terminal 1 of the control circuit RS are leveled or smoothed
out by the voltage control. The temperature sensitivity of the control
circuit RS and, in particular, the uneven heating of the output and
input stages and input stages on the semiconductor chip containing the
control circuit in monolithically integrated form are intercepted by the
temperature compensation provided. The output values are constant in a
specific temperature range. The message for blocking the output stage,
if the supply voltage at the terminal 9 is too low, is given also by
this subassembly to a provided control logic.The outer voltage divider of the terminal 1 via the resistors R5 and R4 to the control tap U forms, via terminal 3, the variable side of the bridge for the control amplifier formed as a differential amplifier. The fixed bridge side is formed by the reference voltage Uref via an internal voltage divider. Similarly formed are circuit portions serving for the detection of an overload short circuit and circuit portions serving for the "standby" no-load detection, which can be operated likewise via terminal 3.
Within a provided trigger circuit, the driving pulse length is determined as a function of the sawtooth rise at the terminal 4, and is transmitted to the control logic. In the control logic, the commands of the trigger circuit are processed. Through the zero-crossing identification at input 2 in the control circuit RS, the control logic is enabled to start the control input only at the zero point of the frequency oscillation. If the voltages at the terminal 5 and at the terminal 9 are too low, the control logic blocks the output amplifier at the terminal 8. The output amplifier at the terminal 7 which is responsible for the base charge in the capacitor C2, is not touched thereby.
The base current gain for the transistor T1 i.e. for the first transistor in accordance with the definition of the invention, is formed by two amplifiers which mutually operate on the capacitor C2. The roof inclination of the base driving current for the transistor T1 is impressed by the collector current simulation at the terminal 4 to the amplifier at the terminal 8. The control pulse for the transistor T1 at the terminal 8 is always built up to the potential present at the terminal 7. The amplifier working into the terminal 7 ensures that each new switching pulse at the terminal 8 finds the required base level at terminal 7.
Supplementing the comments regarding FIG. 1, it should also be mentioned that the cathode of the diode D1 connected by the anode thereof to the one end of the secondary winding II of the transformer Tr is connected via a resistor R11 to the protective input 5 of the control circuit RS whereas, in the circuit acco
rding to FIG. 2, the protective input 5 of
the control circuit RS is supplied via a voltage divider R8, R7 directly
from the output 3', 4' of the rectifier G delivering the rectified line
a-c voltage, and which obtains the voltage required for executing its
function. It is evident that the first possible manner of driving the
protective input 5 can be used also in the circuit according to FIG. 2,
and the second possibility also in a circuit in accordance with FIG. 1.The control circuit RS which is shown in FIG. 3 and is realized in detail by the building block TDA 4600 and which is particularly well suited in conjunction with the blocking oscillator type switching power supply according to the invention has 9 terminals 1-9, which have the following characteristics, as has been explained in essence hereinabove:
Terminal 1 delivers a reference voltage Uref which serves as the constant-current source of a voltage divider R5.R4 which supplies the required d-c voltages for the differential amplifiers provided for the functions control, overload detection, short-circuit detection and "standby"-no load detection. The dividing point of the voltage divider R5 -R4 is connected to the terminal 3 of the control circuit RS. The terminal 3 provided as the control input of RS is controlled in the manner described hereinabove as input for the actual value of the voltage to be controlled or regulated by the secondary winding III of the transformer Tr. With this input, the lengths of the control pulses for the switching transistor T1 are determined.
A sawtooth-shaped voltage, the rise of which corresponds to the collector current of the switching transistor T1, is present at the terminal 4 and is minimally and maximally limited by two reference voltages. The sawtooth voltage serves, on the one hand as a comparator for the pulse length while, on the other hand, the slope or rise thereof is used to obtain in the base current amplification for the switching transistor T1, via the terminal 8, a base drive of this switching transistor T1 which is proportional to the collector current.
The terminal 7 of the control circuit RS as explained hereinbefore, determines the voltage potential for the addressing pulses of the transistor T2. The base of the switching transistor T1 is pulse-controlled via the terminal 8, as described hereinbefore. Terminal 9 is connected as the power supply input of the control circuit RS. If a voltage level falls below a given value, the terminal 8 is blocked. If a given positive value of the voltage level is exceeded, the control circuit is activated. The terminal 5 releases the terminal 8 only if a given voltage potential is present.
Foreign References:
DE2417628A1 1975-10-23 363/37
DE2638225A1 1978-03-02 363/49
Other References:
Grundig Tech. Info. (Germany), vol. 28, No. 4, (1981).
IBM Technical Disclosure Bulletin, vol. 19, No. 3, pp. 978, 979, Aug. 1976.
German Periodical, "Funkschau", (1975), No. 5, pp. 40 to 44.
Peruth, Gunther (Munich, DE) Siemens Aktiengesellschaft (Berlin and Munich, DE)
The CHASSIS FM 100-20 CKVS delivers a totally uncommon Frame deflection system, derived from previous chassis types. (YEARS 1978)
Plus the E/W Correection circuit uses the same Technology.
It's a system called S.S.V.D. which stays for Synchronized Switched Vertical Deflection.
The
system is highly reliable and does dissipate energy like linear
amplifier types like A class or AB class Types and should not be
confused with D Class amplifier.
Abstract:
1. A switched vertical deflection system comprising:
a horizontal deflection circuit including first means for generating horizontal rate energy signals;
a vertical deflection winding;
energy storage capacitance means coupled to said vertical deflection winding;
first and second switching means coupled to said first means and said energy storage capacitance means; and
second means coupled to said first and second switching means for switching conductive states of both of said switching means for coupling successively smaller portions of said horizontal rate energy signals to said energy storage capacitancemeans during a first part of a vertical trace interval and successively larger portions of said horizontal rate energy signals during a second part of said vertical trace interval for developing a vertical deflection current in said vertical deflectionwinding during said vertical trace interval,
said second means causing said first switching means to conduct during a vertical retrace interval for coupling substantial portions of said horizontal rate energy signals to said energy storage capacitance means during said vertical retraceinterval for preventing undesired oscillations within said horizontal deflection circuit.
2.
A system according to claim 1 wherein said first and second switching
means comprise controlled semiconductors, said second means coupling
first and second signals to said first and second switching means for
switching conductive states ofboth of said controlled semiconductors.
3. A system according to claim 2 wherein said second means includes transformer means for coupling said first signals to said first switching means.
4. A system according to claim 3 wherein said first switching means comprises a silicon controlled rectifier, a secondary winding of said transformer means coupled between the gate and cathode electrodes of said silicon controlled rectifier.
5. A system according to claim 2 including vertical signal means coupled to said second means for generating a vertical rate signal for modulating said first and second signals at a vertical rate.
6. A system according to claim 5 wherein said vertical signal means includes first circuitry for generating a component of said vertical rate signal that inhibits conduction of said second switching means during said vertical retrace interval.
7. A system according to claim 6 wherein said first circuitry comprises an RC differentiating circuit.
8. A system according to claim 7 wherein the time constant of said differentiating circuit is selected to provide a duration for said component of said vertical rate signal substantially equal to said vertical retrace interval.
9. In a television receiver including a horizontal deflection circuit comprising a horizontal deflection generator and a horizontal output transformer, a switched vertical deflection circuit comprising:
a vertical deflection winding;
energy storage capacitance means coupled to said vertical deflection winding;
first and second controllable switches coupled to said capacitance means and to respective secondary windings of said horizontal output transformer for coupling horizontal retrace signals to said capacitance means; and
a
modulator coupled to said first and second controllable switches and
responsive to a source of vertical rate signals for providing to said
controllable switches during said vertical trace interval horizontal
rate signals
modulated at a verticalrate for varying the amount of each horizontal
retrace signal coupled to said capacitance means for generating a
vertical deflection current in said vertical deflection winding during
said vertical trace interval, said switched vertical deflectioncircuit
substantially loading said horizontal deflection circuit at the
beginning and end of said vertical trace interval,said modulator providing signals to said first controllable switch during said vertical retrace interval for coupling said horizontal retrace signals to said capacitance means during said vertical retrace interval for substantially loading saidhorizontal deflection circuit during said retrace interval for preventing undesired oscillations within said horizontal deflection circuit.
10. A circuit according to claim 9 wherein said vertical rate signals cause said modulator to provide for conduction of said first controllable switch during said vertical retrace interval and for inhibiting conduction of said second controllable swith during said vertical retrace interval.
vertical
retrace, the second SCR switch which had previously been conducting is
maintained in cutoff. The vertical deflection winding and the capacitor
form a resonant retrace circuit. A disconnect diode coupled to the gate
ofthe first SCR switch is reversed biased, maintaining the SCR in cutoff
independent of the gating pulses generated by the modulator. With both
SCR's nonconducting, resonant retrace of the current in the vertical
deflection winding is accomplished. Atthe start of the subsequent
vertical trace interval, the disconnect diode is no longer reverse
biased. Pulse width modulated gating pulses to the first SCR enable the
SCR to couple the horizontal retrace pulses to the capacitor for
generating thesawtooth deflection current in the vertical deflection
winding.
To permit use of a circuit in which the energy derived during horizontal flyback is used to control ve
rtical
deflection, without damage to the vertical deflection system upon
vertical flyback, the vertical deflection output stage is dimensioned to
have a time constant which is less, preferably about half, of the time
constant of the sawtooth wave generator controlling vertical deflection.
The vertical deflection output stage forms, in essence, a parallel
oscillatory circuit which, to provide the lesser time constant, is
damped.1. In a television receiver,
having means (1, 2) coupling out a portion of the energy delivered by the horizontal deflection circuit during line flyback or retrace;
a vertical deflection output stage (V) including deflection means (LV1, LV2) and a charge capacitor element (C);
and a sawtooth wave generator (S), which controls application of the coupled-out energy derived from the horizontal deflection circuit to the vertical deflection means (LV1, LV2), a method to control vertical deflection
comprising, in accordance with the invention, the step of
additionally controlling application of the energy to the vertical deflection means by the sawtooth wave generator during the vertical flyback or retrace interval by reversely re-charging said capacitor element during said interval.
2. Method according to claim 1, wherein the re-charging step is carried out continuously.
3. Method according to claim 1, wherein the re-charging step is carried out linearly.
4. Method accordi
ng to claim 1, wherein the vertical deflection output stage includes, vertical deflection coil elements (LV1, LV2)
and forming with said charge capacitor element (C) said deflection
means, a feedback resistor element (R) and a vertical correction circuit
element (4), said charge capacitor element and said other elements
being connected to form a parallel oscillatory circuit; said method including the step of controlling the damping of the parallel oscillatory circuit by controlling the relative parameters of said elements.
5. In a television receiver, a vertical deflection system including means (1, 2) coupling out a portion of the energy delivered by the horizontal deflection circuit during line flyback or retrace;
a vertical deflection output stage (V) including vertical deflection means (LV1, LV2);
and a sawtooth wave generator (S) controlling application of the coupled-out energy to the vertical deflection means during the flyback interval
and wherein, in accordance with the invention,
the time constant (τS) of the sawtooth wave generator (S) is longer than the time constant (τV) of the vertical deflection output stage (V).
6. Vertical deflection system
according to claim 5, wherein the time constant of the vertical
deflection output stage is about twice as long as that of the sawtooth
wave generator (S).7. Vertical deflection system according to claim 5, wherein the ratio of time constants (τS /τV) is between about 1.5 to 2.5.
8. Vertical deflection system according to claim 5, wherein the vertical deflection output stage (V) includes a charge capacitor element (C), vertical deflection coil elements (LV1, LV2) forming said vertical deflection means, a feedback resistor element (R) and a vertical correction circuit element (4), said elements being connected to form a parallel oscillatory circuit;
and wherein said oscillatory circuit is a damped oscillatory circuit.
9. Vertical deflection system according to claim 8, wherein the elements of said oscillatory circuit are dimensioned to provide a time constant which is about half of the time constant of the sawtooth wave generator (S) and is in the order of about 0.5 ms.
Video scanning in television receivers is effected, as well known, by a vertical deflection circuit. A pulse generator is synchronized by pulses included in the video signal. The pulses are then applied over a pulse generator, a driver and an output stage to deflection systems, usually deflection coils.
Various types of solid-state circuits have been proposed; for example, U.S. Pat. No. 4,048,544 describes a transistorized vertical deflection circuit with additional circuitry to stabilize the pulses. The time constant of the pulse generator and of the driver stage of such circuits is less than
the time constant of the output or final power stage of the vertical
deflection circuit. Such vertical deflection circuits have some
disadvantages, particularly in that the transistors are operated at high
voltages which may result in flash-over and thus damage or destruction
of the transistor. The power required to control the final output
transistors is already substantial and thus the overall operating
efficiency of such a vertical deflection circuit is low. In earlier developments, a vertical deflection circuitry was proposed which avoids some of the disadvantages of this transistorized circuit; in this earlier circuit, a portion of the energy contained in the horizontal flyback is coupled out and is directly utilized in order to supply current for the vertical deflection coils. To control application of current, a controlled sawtooth wave generator is connected to the final output stage of the vertical deflection circuit, the sawtooth wave generator having a short retrace or flyback time. These vertical deflection circuits also have some disadvantages. The energy derived for vertical deflection is obtained from the horizontal flyback; thus, changes in loading in the vertical deflection circuitry affect the horizontal output stage. The vertical deflection circuit is subject to substantial changes in loading during the vertical flyback or retrace since, in accordance with the previously known circuit, the vertical deflection circuit is not controlled during the vertical flyback or retrace. The lack of control of the vertical deflection circuit causes abrupt changes in loading which result in undesired spurious oscillations in the vertical output stage. These oscillations can so feed back or react on the horizontal output stage that the horizontal flyback pulses are overloaded, the vertical stage starts to oscillate, and high voltages may occur therein during the vertical flyback. This, necessarily, degrades the image quality of the reproduced video picture. High-voltage flash-over may occur and electronic components, particularly solid-state semiconductor elements can be destroyed thereby.
It is an object of the present invention to provide a vertical deflection circuit for television receivers, which has the advantages of utilizing a portion of the energy contained in the horizontal deflection circuit during horizontal flyback without causing abrupt changes in loading on the horizontal out
put stage and preventing undesired spurious and uncontrolled oscillation of the vertical output stage. SUBJECT MATTER OF THE PRESENT INVENTION
Briefly, the sawtooth wave generator which controls charging of a charge capacitor of the vertical output stage is controlled to in turn control the charge on the capacitor also during vertical retrace; in accordance with a feature of the invention, this control is obtained by so arranging and relatively matching the time constants of the sawtooth wave generator and of the parallel oscillatory circuit formed by the vertical deflection coils of the T.V. receiver and the charge capacitor that the time constant of the vertical deflection output stage is less, preferably about half that of the time constant of the sawtooth wave generator. This matching can be obtained by so selecting the values of the components of the vertical deflection output stage that the resulting oscillatory circuit formed by the capacitor, resistance elements in the circuit, and the vertical deflection output stage form a damped oscillatory circuit.
The invention will be described by way of example with reference to the accompanying drawings, wherein the single FIGURE is a schematic diagram of a vertical deflection output stage in which the method of the present invention is carried out, and utilizing the system thereof.
A horizontal deflection output stage 1 is connected to a horizontal output transformer 2 which has coupling windings W 1 and W 2 to derive a portion of the energy contained in the line retrace. This energy is stored in the inductances L 1 and L 2 and then applied through thyristors Th 1 and Th 2 to a charge capacitor C. A control circuit 3 is provided triggering the thyristors Th 1 and Th 2 in such a manner that the charge capacitor C is positively charged during the first half of the video scan and negatively during the second half of the video scan. The charge capacitor C is discharged through the vertical deflection coils L V1 and L V2 , a vertical correction circuit 4 for vertical correction and a feedback resistor R. The voltage drop across feedback resistor R is fed back to the control circuit 3 in order to ensure exact triggering of the thyristors Th 1 and Th 2 and to control the desired deflection current.
Positive deflection current is obtained during the first half of the video scan by the triggered thyristor Th 1 ; negative deflection current is derived during the second half of the video scan by the triggered thyristor Th 2 . The thyristors Th 1 and Th 2 can be triggered during a portion of the video scan simultaneously to result in a linear deflection and provide overlapping, opposite deflection currents.
The control circuit 3, together with the thyristors Th 1 and Th 2 , and the inductances L 1 and L 2 , forms a sawtooth wave generator S. The vertical deflection output stage V is formed of the vertical deflection
coils L V1 , L V2 ,
the vertical correction circuit 4, the charge capacitor C and the
feedback resistor R. As can be seen from the FIGURE, the capacitor C on
the one hand, and the deflection coils, the correction circuit 4 and the
resistor R on the other hand form a parallel oscillatory circuit. The circuit, as far as the diagram is concerned, is known. Uncontrolled, undesired and spurious oscillations in the horizontal output stage can be avoided, in accordance with the invention, by reverse re-charging the capacitor C also during the vertical retrace interval. This re-charging of the capacitor C preferably is carried out continuously and desirably linearly. The controlled re-charging of the capacitor C can be readily obtained by arranging the relative values of the components in the sawtooth wave generator S and in the vertical output stage V such that the time constant τ S of the sawtooth wave generator is longer than the time constant τ V of the vertical deflection output stage. Mathematically: τ S >τ V (1)
preferably, the quotient of the time constants should be between 1.5 and 2.5, most desirably about 2, mathematically: 1.5>τ S /τ V <2.5 (2)
if the time constants of the respective circuits are properly arranged, the thyristors Th 1 and Th 2 can be precisely triggered also during the short time interval of the vertical flyback or retrace. Due to the short time constant, the vertical deflection circuit can then follow the control from the control circuit 3 exactly; the voltage dropped across the feedback resistor R will permit precise triggering, with respect to time, of the thyristors Th 1 and Th 2 also during the vertical flyback. In the first half of the video scan, the thyristor Th 2 is triggered; in the second half, thyristor Th 1 is triggered. This ensures linear flyback.
The time constant τ V is essentially determined by the vertical deflection coils L V1 , L V2 , the correction circuit 4, and the feedback resistor R which, together with the capacitor C, form a parallel oscillatory circuit. A short time constant corresponds to high damping of this parallel oscillatory circuit. Thus, in accordance with a feature of the present invention, by suitably arranging the ratio of the time constants, the parallel oscillatory circuit will not start undesired uncontrolled oscillations which could interfere with image reproduction quality, or proper operation of the components of the T.V. receiver. The ratio of the time constants can be selected by suitable adjustment of the damping of the oscillatory circuit.
The vertical deflection circuit has an essentially continuous, uniform and even power requirement. This avoids abrupt changes in loading during the vertical retrace. Excessive over-compensation of horizontal flyback pulses, and resulting high voltages which may lead to undesired distortion of the reproduced image and possibly to damage or destruction of components of the video system are avoided. The vertical deflection circuitry, as described, can be readily manufactured and has high operating reliability. The efficiency is high and the power requirement is low.
Various changes and modifications may be made within the scope of the inventive concept.
In a typical T.V. receiver using vertical deflection coils of 20 millihenry inductance, a suitable time constant τ V
is 0.5 ms. In such a circuit, the resistor R can have a value 1 Ω
capacitor C a value of 1.5 μF. and the reflected impedance of correction
circuit 4 a value of 1 Ω. The sawtooth wave generator has a time constant of 1 ms, providing for a slow rise time for 20 milliseconds. The circuit 3 is well known and described in U.S. Pat. No. 4,048,544.
CHASSIS FM100-20 CKVS BLAUPUNKT SSVD E/W CORRECTION Pincushion correction circuitA
side pincushion correction circuit having an impedance circuit in
series with the deflection coil. A controlled switch coupled
in a branch of the impedance circuit is operated at times during the
second half of the horizontal retrace interval which are progressively
advanced during the first half of vertical interval and retarded
during second half of vertical interval. Enhanced inside pincushion
distortion correction is provided when the impedance circuit includes a
capacitor coupled in series with the switch.1. A pincushion correction circuit for a kinescope deflection apparatus including horizontal and vertical deflection generator systems, comprising:
a horizontal deflection winding coupled to the horizontal deflection generator system for accepting scanning current therefrom;
an impedance circuit for presenting an impedance between first and second terminals and further including a third terminal, and first coupling means for coupling said first terminal to said third terminal;
second means for serially coupling said first and second terminals of said impedance circuit with said deflection windin
g; controllable switch means including a control electrode and a controlled current path coupled between said second and third terminals;
control means coupled to the horizontal and vertical deflection generator systems and to said control electrode for operating said controllable switch means at a time during the second half of the horizontal retrace interval which time is progressively advanced during a first portion of the vertical scan interval and which is progressively retarded during a second portion of the vertical scan interval for altering said scanning current in a manner to reduce pincushion distortion.
2. A pincushion correction circuit in accordance with claim 1 wherein said first coupling means comprises a direct connection.
3. A pincushion correction circuit in accordance with claim 1 wherein said impedance circuit comprises first inductance means coupled between said first and second terminals.
4. A pincushion correction circuit in accordance with claim 3 wherein said first coupling means comprises capacitance means coupled between said first and third terminals.
5. A pincushion correction circuit according to claim 3 wherein said first coupling means comprises:
capacitance means;
second inductance means;
means for serially coupling said capacitance means with said second inductance means; and
means for coupling the serial combination of said capacitance means and said second inductance means between said first and third terminals.
6. A pincushion correction circuit according to claim 3 wherein said coupling means comprises second inductance means coupled between said first and third terminals.
7. A pincushion correction circuit according to claim 6 further comprising means for magnetically coupling said first inductance means with said second inductance means.
8. A pincushion correction circuit according to claim 7 further comprising capacitance means serially coupled with said second inductance means.
9. A pincushion correction circuit according to claim 8 wherein said first and second inductance means have substantially the same self-inductance.
1
0.
A pincushion correction circuit according to claim 1 wherein said
controllable switch means comprises a controllable rectifier including
said control electrode and said controllable current path, a
unidirectional current conducting device, and wherein said controllable
current path is coupled in parallel with said unidirectional current
conducting device. 11. A pincushion correction circuit according to claim 10 wherein the anode of said unidirectional current conductive device is coupled to the cathode of said controllable rectifier and the cathode of said unidirectional current conducting device is coupled to the anode of said controllable rectifier.
12. A pincushion correction circuit according to claim 1 wherein said control means comprises gating pulse generator means coupled to said controllable switch and to the horizontal and vertical deflection generator systems for producing repetitive switch gating pulses during the second half of each horizontal retrace pulse interval, said gating pulses terminating substantially at the termination of said horizontal retrace pulse and initiating at a time which is progressively advanced during a first portion of the vertical scan interval and progressively retarded during a second portion of the vertical scan interval.
13. A pincushion correction circuit according to claim 12 wherein said gating pulse generator means comprises:
parabola generating means coupled to the vertical deflection generator system for generating a parabolic signal at the vertical deflection rate;
means coupled to the horizontal deflection generator system for generating a horizontal rate signal during the horizontal retrace pulse period;
modulating means coupled to said horizontal rate signal generating means and to said parabolic signal generating means for generating a horizontal rate pulse width modulated by said parabolic signal; and
gating means coupled to said horizontal rate signal generating means and to said modulating means for generating switch gating pulses representative of the absence of said horizontal rate signal and of said horizontal rate pulse.
14. A pincushion correction circuit according to claim 12 wherein said gating pulse generator means comprises: parabola generating means for generating a parabolic signal at the vertical deflection rate; means for generating a horizontal rate signal during the horizontal retrace pulse interval; and
comparator means coupled to said parabola generator means and to said horizontal rate signal generating means for producing said repetitive gating pulses.
15. A pincushion correction circuit according to claim 14 wherein said comparator means comprises: differential amplifier amplitude comparison means having a first and a second input;
said first input being coupled to said parabola generating means; and
said second input being coupled to an output of said horizontal rate signal generating means and said horizontal rate signal comprises a ramp.
16. A pincushion correction circuit for a kinescope deflection apparatus including horizontal and vertical deflection generator systems, comprising:
a horizontal deflection winding coupled to the horizontal deflection generator system for accepting scanning current therefrom;
an impedance circuit including a capacitor coupled in parallel with an inductor;
means for serially coupling said impedance circuit with said deflection winding;
controllable switch means including a control electrode and a controlled current path serially coupled with a branch of said impedance circuit; and
control means coupled to the horizontal and vertical deflection generator and to said control electrode for operating said controllable switch means at a time during the second half of the horizontal retrace interval which time is progressively advanced during a first portion of the vertical scan interval and which is progressively retarded during a second portion of the vertical scan interval for altering said scanning current in a manner to reduce pincushion distortion.
17. A pincushion correction circuit according to claim 16 wherein said controllable switch is serially coupled in the capacitive branch of said impedance circuit.
18. A pincushion correction circuit according to claim 17 wherein the inductive branch of said impedance circuit comprises an autotransformer.
19. A pincushion correction circuit according to claim 18 wherein said controllable switch comprises a controllable rectifier, a unidirectional current conducting device and having said controllable current path coupled in parallel with said unidirectional current conducting device.
20. A pincushion correction circuit according to claim 19 wherein the anode of said unidirectional current conducting device is coupled to the cathode of said controllable rectifier and the cathode of said unidirectional current conducting device is coupled to the anode of said controllable rectifier.
21. A p
incushion
correction circuit according to claim 16 wherein said control means
comprises gating pulse generator means coupled to said controllable
switch and to the horizontal and vertical deflection generator systems
for producing repetitive switch gating pulses during the second half
of each horizontal retrace pulse interval, said gating pulses
terminating substantially at the termination of said horizontal
retrace pulse and initiating at a time which is progressively advanced
during a first portion of the vertical scan interval and progressively
retarded during a second portion of the vertical scan interval.
22. A pincushion correction circuit according to claim 21 wherein said gating pulse generator means comprises:
parabola generating means coupled to the vertical deflection generator system for generating a parabolic signal at the vertical deflection rate;
means coupled to the horizontal deflection generator system for generating a horizontal rate signal during the horizontal retrace pulse period;
modulating means coupled to said horizontal rate signal generating means and to said parabolic signal generating means for generating a horizontal rate pulse width modulated by said parabolic signal; and
gating means coupled to said horizontal rate signal generating means and to said modulating means for generating switch gating pulses representative of the absence of said horizontal rate signal and of said horizontal rate pulse.
23. A pincushion correction circuit according to claim 21 wherein said gating pulse generator means comprises: parabola generating means for generating a parabolic signal at the vertical deflection rate; means for generating a horizontal rate signal during the horizontal retrace pulse interval; and
comparator means coupled to said parabola generator means and to said horizontal rate signal generating means for producing said repetitive gating pulses.
24. A pincushion correction circuit according to claim 23 wherein said comparator means comprises: differential amplifier amplitude comparison means having a first and a second input;
said first input being coupled to said parabola generating means; and
said second input being coupled to an output of said horizontal rate signal generating means and said horizontal rate signal comprises a ramp.
25. A television kinescope deflection apparatus comprising:
a vertical deflection generator coupled to a vertical deflection coil for producing vertical scanning current therethrough;
a horizontal deflection generator system for generating horizontal rate current;
a horizontal deflection winding coupled to said horizontal deflection generator for accepting horizontal rate current therefrom for scanning;
impedance means;
controllable switch means; first coupling means for coupling said horizontal deflection winding with a first terminal of said impedance means so as to form a series circuit, said impedance means having a second terminal remote from said first terminal; second coupling means coupling a first end of the controlled current path of said controllable switch means with said first terminal, and third coupling means for coupling the other end of the controlled current path of said controllable switch means with said second ter
minal; and 
control means coupled to said vertical and to said horizontal deflection generator systems and to said controllable switch means for operating said controllable switch means at a time during the horizontal retrace interval which is progressively advanced during a first portion of the vertical scan interval and which is progressively retarded during a second portion of the vertical scan interval for altering said scanning current in a manner to reduce pincushion distortion.
26. A television kinescope deflection apparatus according to Claim 25
wherein
said control means closes
said controllable switch means at a time during the horizontal
retrace interval which is progressively advanced during the first half
of the vertical scan interval and progressively retarded during the
second half of the vertical scan interval.27. A television kinescope deflection apparatus according to claim 26 wherein said impedance means comprises first inductance means coupled between said first and second terminals.
28. A television kinescope deflection apparatus according to claim 27 wherein said second coupling means comprises capacitance means coupling said first terminal of said impedance means to said first end of said controllable switch means.
29. A television kinescope deflection apparatus according to claim 27 wherein said second coupling means comprises second inductance means coupling said first terminal of said impedance means to said first end of said controllable switch means.
30. A television kinescope deflection apparatus in accordance with claim 27 wherein said second coupling means comprises second inductance means coupling said first terminal of said impedance means to said first end of said controllable switch means and further comprising magnetic coupling means for magnetically coupling said first inductance means with said second inductance means.
31. A television kinescope deflection apparatus according to Claim 27 wherein said second coupling means comprises capacitance means and second inductance means.
32. A television kinescope deflection apparatus according to claim 31 wherein said first and second inductance means have substantially the same self-inductance.
33. A television kinescope deflection apparatus according to claim 31 wherein said capacitance means and said second inductance means are serially coupled.
34. A television kinescope deflection apparatus according to claim 31 further comprising magnetic coupling means for magnetically coupling said first and second inductance means.
35. A tel
evision
kinescope deflection apparatus according to claim 31 wherein said
first and second inductance means are windings of an autotransformer.
36. A television kinescope deflection apparatus in accordance with claim 25 wherein said controllable switch means comprises a controllable rectifier including a control electrode and a controllable current path, a unidirectional current conducting device, and wherein said controllable current path is coupled in parallel with said unidirectional current conducting device.
37. A television kinescope deflection apparatus according to Claim 36 wherein the anode of said unidirectional current conductive device is coupled to the cathode of said controllable rectifier and the cathode of said unidirectional current conducting device is coupled to the anode of said controllable rectifier.
38. A television kinescope deflection apparatus according to Claim 25 wherein said control means comprises gating pulse generator means coupled to said controllable switch and to said horizontal and vertical deflection ge
nerators for producing repetitive switch gating pulses,
said gating pulses terminating substantially at the termination of said
horizontal retrace pulse. 39. A television kinescope deflection apparatus according to Claim 38 wherein said gating pulse generator means comprises: parabola generating means coupled to the vertical deflection generator for generating a parabolic signal at the vertical deflection rate; means coupled to said horizontal deflection generator system for generating a horizontal rate signal during said horizontal ratrace pulse period; modulating means coupled to said horizontal rate signal generating means and to said parabolic signal generating means for generating a horizontal rate pulse width-modulated by said parabolic signal.
40. A television kinescope deflection apparatus according to Claim 39 wherein said modulating means comprises: comparator means coupled to said parabola generator means and to said horizontal rate signal generating means for producing said repetitive gating pulses.
41. A television kinescope deflection apparatus according to Claim 40 wherein said comparator means comprises: differential amplifier amplitude comparison means having a first and a second input; said first input being coupled to said parabola generating means; and said second input being coupled to an output of said horizontal rate signal generating means and wherein said horizontal rate signal comprises a ramp.
42. A television kinescope deflection apparatus comprising: a vertical deflection generator coupled to a vertical deflection coil for producing vertical scanning current therethrough; a horizontal deflection generator system for generating horizontal rate current; a horizontal deflection w
inding
coupled to said horizontal deflection generator for accepting
horizontal rate current therefrom for scanning; impedance means;
controllable switch means; means coupling said impedance means and said
controllable switch means in series with said deflection winding for
defining a path for said horizontal rate current; control means
coupled to said vertical and to said horizontal deflection generator
systems and to said controllable switch means for operating said
controllable switch means at a time during the horizontal retrace
interval which is progressively advanced during the first half of the
vertical scan interval and which is progressively retarded during the
second half of the vertical scan interval for altering said scanning
current in a manner to reduce pincushion distortion.
This invention relates to a kinescope pincushion distortion correction circuit.
It is known in the art that side or East-West pincushion distortion of the raster on a kinescope such as utilized in a television receiver may be substantially eliminated by modulating the horizontal rate deflection current amplitude through the horizontal deflection coils by a substantially parabolic current component at a vertical scanning rate. Generally the desired modulation has been accomplished by passive currents in which a control or primary winding of a saturable reactor or transformer is energized by vertical rate energy and a secondary winding is placed in circuit with the horizontal deflection winding. The horizontal deflection current amplitude is modulated by the vertical deflection current such that the raster width is reduced at the top and bottom of the raster.
Another known arrangement for side pincushion distortion correction involves a capacitor coupled in parallel with the vertical deflection winding. As is disclosed in copending application Ser. No. 07161/75 for Peter E. Haferl and entitled "VERTICAL DEFLECTION SYSTEM", the capacitor is charged by energy from the horizontal retrace pulse under the control of switches. In both the passive saturable reactor circuits and in the switched vertical deflection circuit according to the aforementioned copending application, side pincushion correction is obtained by loading the high voltage transformer of the horizontal deflection system during the horizontal retrace time. In order to obtain correctly shaped side pincushion correction the loading of the high voltage transformer is modulated at the vertical deflection rate, as by the vertical deflection current. Thus, maximum loading occurs at the top and bottom of the picture and minimum loading occurs at the center of the picture.
The variable loading of the horizontal retrace pulse at the vertical rate results in the generation of a further pincushion distortion, known as inside pincushion distortion to distinguish from the outside or peripheral pincushion distortion ordinarily referred to. This further pincushion distortion occurs within the raster as a result of time modulation of the start of horizontal scan caused by the vertical rate loading.
Increased
trace duration resulting from time modulation of the horizontal
retrace pulse at the top and bottom of vertical scan increases the
portion of the resonant period of the deflection coil 26 with S
correction capacitor 28 subtended during trace. Thus, the inside
pincushion distortion appears in the region between the center line and
the extreme left and right sides of the picture as an insufficient
pincushion correction. The amount of inside pincushion correction depends upon the geometry of the picture tube and on the amount of outside pincushion distortion requiring correction. With the advent of wide-angle large viewing screen picture tubes it has been found that the inside pincushion distortion may be objectionable to the point that correction is required.
A prior art arrangement for the solution of the inside pincushion correction problem, in addition to structure utilized for conventional pincushion correction, uses a separate saturable reactor or transductor in series with the horizontal deflection winding. The control winding of the saturable reactor is driven by a vertical deflection rate signal and modulates the inductance of the horizontal deflection circuit to correct for the change in "S" shaping and thereby correct the inside pincushion distortion. This prior art solution has disadvantages which include critical design of the saturable reactor, temperature dependence of the saturable reactor, cost of the saturable reactor, and a control range so limited as to often be insufficient to compensate for construction tolerances.
SUMMARY OF THE INVENTION
A pincushion correction circuit includes an impedance coupled in series with a horizontal deflection winding. The impedance circuit contains two branches, one of which is always in series with the deflection winding. The second branch of the impedance circuit is paralleled with the first branch by a controllable switch. The controllable switch is gated on at a time during the second half of the horizontal retrace interval. The time during the second half of the horizontal retrace interval at which the switch is gated on is progressively advanced during a first portion of the vertical scan interval and is progressively retarded during the second portion of the vertical scan interval.
Description of the EHT FLYBACK Transformer used in Blaupunkt CHASSIS types. High-voltage-secondary transformer, particularly television line transformer:
To decr
ease
the internal resistance of a transformer operable as a television line
transformer of the "diode-split" type, the secondary winding sections
are matched to each other and to the frequency of operation of the
transformer in such a manner that the current in the respective sections
will flow at respectively different instants of time; in a preferred
form, the winding sections, on the average, are tuned to a harmonic of
the frequency of the signal applied to the primary and are positioned on
winding forms or holders such that the distance between the bottom wall
of the primary and the bottom wall of the secondary is constant over
the entire length of the windings. Preferably, the tuning of the
respective winding sections is effected by matching of the primary
winding to the secondary within the region of the secondary winding
sections.
1. High-voltage secondary transformer, particularly television line transformer, having a primary winding (5) and a secondary winding (7a, 7b, 7c) in which the secondary winding is subdivided into a plurality of windings sections (7a-7b-7c), and a plurality of rectifier diodes (10) connecting said secondary winding sections together,
wherein, in accordance with the invention,
the secondary winding sections (7a, 7b, 7c) are physically positioned with respect to the primary winding to form spatially separated winding sections, each having individual inductance and capacity values and with respect to the primary, and each other, said positioning on the primary winding being effected to result in current flow in the respective sections (7a, 7b, 7c) of the secondary at respectively different instants of time.
2. Transformer according to claim 1, wherein the secondary winding sections are tuned to a harmonic of the frequency of the signal applied to the primary winding (5).
3. Transformer according to claim 2, wherein the respective winding sections (7a, 7b, 7c) of the secondary are tuned to the primary (5) by matching the primary winding to the secondary in the region of the respective secondary winding section.
4. Transformer according to claim 3, wherein the distance between the inner dimension of the primary winding and the inner dimension of the secondary winding is constant throughout the length of a winding section.
5. Transformer according to claim 4, wherein said distance is constant throughout the length of all the winding sections.
6. Transformer according to claim 5, for use as a television
high-voltage transformer further comprising a resistor (R) connected to
one of the secondary winding sections to provide a bleeder voltage for
focussing of an image tube of a television apparatus, comprising a housing being formed with a first portion receiving said primary winding (5) and said secondary winding sections (7a, 7b, 7c) and a resistor chamber portion defining a chamber (16) in which said resistor (R) is located, said resistor chamber portion being separated from the portion retaining said windings by an air gap (15).
7. Transformer according to claim 3, for use as a television high-voltage transformer further comprising a resistor (R) connected to one of the secondary winding sections to provide a bleeder voltage for focussing of an image tube of a television apparatus,
comprising a housing being formed with a first portion receiving said primary winding (5) and said secondary winding sections (7a, 7b, 7c) and a resistor chamber portion defining a chamber (16) in which said resistor (R) is located, said resistor chamber portion being separated from the portion retaining said windings by an air gap (15).
BACKGROUND AND PRIOR ART Television line transformers frequently have divided secondaries, that is, secondaries which are subdivided into sections, connected by rectifier diodes. These transformers, particularly when used as line transformers in TV apparatus, are supplied at the primary with signals of line frequency, and then provide the anode voltage for the TV electron gun, image tube at the secondary. Line transformers in which the secondaries are subdivided and connected by diodes are referred to as "diode-split" transformers. The voltages induced in the partial secondary windings or winding sections add in the form of a voltage doubler or voltage multiplier until the desired high voltage is reached. The stray or leakage capacitances within the transformer and particularly the stray capacitances of the partial windings with respect to a reference voltage act as intermediate storage capacities for the portions of the voltages which are being added.
Transformers of this type have a disadvantage in that they have poor regulation. As a voltage source, they have a comparatively high inherent or internal resistance. Changes in loading which may occur thus lead to changes in output voltage. Applied to a TV system, instability of the format of the resulting image may occur. Changes in loading often are the consequence of changes in beam current.
THE INVENTION
It
is an object to provide a transformer, particularly suitable as a line
transformer, which has a suitable low internal resistance so that the
output power obtained therefrom will be at a voltage which is
essentially constant and independent of variations in loading
experienced in ordinary television sets, without the necessity of
complex circuitry. Briefly, a transformer of the diode-split type is so constructed that the secondary winding sections are matched to each other and to the frequency of operation of the transformer that the current in the respective section flows at respectively differently instants of time. In a preferred form, the winding sections, on the average, are tuned to a harmonic of the frequency of the signals applied to the primary. Tuning of the various winding sections can be effected by matching the configuration or winding arrangement or number of turns of the respective sections to the primary within the range of the inductive coupling between the primary and the particular section of the secondary. In accordance with a preferred feature, the primary is located within the secondary, and the distance between the inner winding portion of the coil of the primary and the inner winding portion of the coil forming the secondary is essentially constant over the entire width of the windings.
Transformers
of this type often are associated with external circuitry, and
particularly with a resistor which is connected to a specific secondary
section and on which the focussing voltage for the TV image tube can be
taken off. In accordance with a feature of the invention, the housing
for the transformer is formed with a lateral chamber, remote from the
transformer windings themselves and separated therefrom by an air gap.
The transformer windings, as well as the chamber for a resistor from
which the tapping voltage can be taken off, is filled with a potting
compound. This resistor, also referred to as a bleeder resistor, can be
applied by thin film or hybrid technology on a small ceramic plate and,
by the specific location, is removed from the field generated by the
transformer and thus provides a stable output voltage. The transformer construction in accordance with the present invention, when used as a line transformer in a TV set provides for a more stable picture since it has substantially improved regulation with respect to prior art transformers by having an inherent or inner resistance which is less than that of previously used units. Tuning of the sections of the secondary winding is simple by matching the configuration of the primary winding to the configuration of the secondary sections, which is easier to accomplish in manufacture than if the secondary is matched to the primary.
Drawings, illustrating an example, wherein:
FIG.
1 is a side view, partially in section, of a line transformer for
television use, having rectifier diodes located within the transformer
and connected between individual winding sections; and
FIG. 2 is a top view, with part of the housing cut away and in section, of the transformer of FIG. 1. The transformer is a "diode-split" transformer, the principle of which is known. The transformer 1 is located within a plastic, typically injection-molded plastic, housing 2 which receives a potting compound 3 after the transformer is assembled within the housing. In FIG. 1, the front wall of the housing has been removed. The housing 2 receives, or inherently forms, a coil form 4 for the primary winding 5 of the transformer. The coil form 4 may be part of the housing structure, that is, molded integrally therewith, the coil 5 being wound initially as a coreles
s or formless structure so that it can be slipped directly over
the form 4 which, as best seen from FIG. 2, is essentially a cylinder
open at one end. A different type of housing can be used, however, in
which the coil form 4 does not form an intergral, molded part, but
rather is inserted as a separate form or winding body for the primary. A coil carrier 6 is located on the primary 5 to receive the secondary of the transformer 1. In accordance with a feature of the invention, the secondary winding is wound in three sections 7a, 7b, 7c, which subdivide the secondary. The secondary winding sections 7a, 7b, 7c are each located in three winding chambers 6a, 6b, 6c of the form 6. The winding chambers 6a, 6b, 6c each have five winding grooves 8 in which the winding sections 7a, 7b, 7c each are uniformly distributed. These winding grooves 8 may, however, be non-uniformly distributed if it is desired to effect matching of the tuning of the winding sections to the primary by this distribution; in a preferred form, however, the distribution of the grooves 8 is uniform. The result of this subdivision of the windings into sections 7a, 7b, 7c, physically separated, i.e. axially spaced from each other
(see
FIG. 1), is a consequent division of capacity and inductance of the
secondary into respectively, individually positioned individual capacity
and inductance values and mutual capacity and inductance values of the
sections, resulting in different phasing of the current flow, i.e.
current flow in the respective sections at respectively different
instants of time. Holders 9 are located above each one of the winding chambers 6a, 6b, 6c, as best seen in
FIG.
2, preferably formed integrally with the winding holder or body 6. The
holders 9 receive the diodes 10. The diodes 10 are located in the
holders 9 with externally bent connecting wires 11. The connecting wires
extend through openings or passages of caps 12 snapped over the holders
9, thus securing the diodes 10 on the holders 9. The low-voltage
connection of the transformer 1 is effected by connecting pins 13; some
of the pins 13, shown in FIG. 1, may be left unconnected and serve as
positioning elements. The high-voltage load is connected by a
high-voltage cable--not shown--to a connecting bushing 14 located at the
side opposite the low-voltage terminals 13. 
The
housing is formed with a separately arranged chamber 16, separated from
the remainder of the transformer by an air gap 15. A ceramic plate 17
on which a resistor R, applied by hybrid technology is located, is
positioned in the chamber 16. Thus resistor, forming a bleeder resistor,
can be used to generate the focussing voltage for the image tube of the
TV set for which the transformer is particularly suitable by connection
to a tap point on one of the winding sections 7a, 7b, 7c, by a suitable
connection, not shown for simplicity. The average tuning frequency of the winding sections 7a, 7b, 7c is tuned to a harmonic of the frequency of the signal applied to the primary. The respective winding sections 7a, 7b, 7c are tuned by matching the primary winding to the secondary in the region of inductive coupling of the primary to the respective section of the secondary. The inner diameter of the form 4 for the primary winding and the inner diameter of the secondary winding form or holder 6 are concentric and equidistant throughout at least the length of one of the winding sections, and preferably uniform throughout their entire length.
The transformer will form a voltage source of low internal resistance and thus can be used without additional circuitry or without increasing the size of the transformer. Miniaturization of the transformer is thus possible which is particularly important in modern television equipment.
Making
the inner wall of the primary winding and the inner wall of the
secondary winding in such a manner that the distances between these two
walls are uniform reduces the overall size and substantially simplifies
manufacture of the tuned winding sections. It was previously thought
necessary to tune the winding sections with respect to each other by
varying the thickness of the windings or the distances of the inner
limits of the windings with respect to each other. In the transformer as
described, this is not necessary and, rather, the inner wall of the
transformer primary and the inner wall of the transformer secondary
winding sections is uniform which results in a structure in which the
comparatively complex secondary winding sections can be made identical
to each other, since tuning or matching of the output is obtained by
matching the secondary and primary by the shape of the primary winding.
The primary winding is matched to the secondary by different magnetic
coupling of the primary with respect to the sections of the secondary,
that is, with a coupling which differs between the sections of the
secondary; and by respectively different stray capacitances between the
sections of the secondary and the primary winding, that is, by so
arranging the coils that the stray capacitances of any one of the
sections 7a, 7b, 7c of the secondary with respect to the primary are
different. The potting compound 3 can be filled into the transformer after assembly; the resistor secured to the ceramic plate 17 is connected before potting to a tap of the secondary winding. The resistor, by being located in chamber 16 separated from the housing of the transformer itself, eliminates undesired capacitative losses or stray currents which otherwise occur between the secondary winding of the transformer and the resistor. Such stray currents are a minimum by the separation of the resistor from the remainder of the transformer by the air gap, and its positioning in a separate chamber. This separation effectively eliminates electric stray fields which have a disturbing effect at line frequency, since the focussing voltage is undesirably modulated thereby.
In an operating example, a transformer designed for 625 lines, 50 frames (PAL standard) was wound with a diameter of the bottom 4 of 22.5 mm, having 110 turns of 0.31 mm wire to form the primary; over this form, a secondary with an inner winding diameter for the winding sections 7a, 7b, 7c, of 24.1 mm was placed; the secondary was composed of 2910 turns of 0.071 mm wire, having each three sections of 5 grooves, interconnected by diodes.
BLAUPUNKT MONTANA IP 32 STEREO VT COLOR (7 664 880) CHASSIS FM 100-20 CKVS PLL Frequency synthesizer tuning system for television receivers:
generating binary signals representing first and second digital tune words, said digital tune words representing a selected channel;
storing said first and second digital tune words in a first data memory in said microcomputer;
reading said first and second digital tune words from said first memory and generating a divided-down local oscillator frequency by the use of said first digital tune word and a divided-down reference oscillator frequency by the use of said second digital tune word;
comparing said divided-down local oscillator and reference frequencies and generating a control signal representative of the difference in frequency of said divided-down local oscillator and reference frequencies;
coupling said control signal to sa
id local
oscillator for causing it to be locked to the frequency of said
received carrier signal; 
mixing the local oscillator frequency signal and the carrier frequency signal to generate an intermediate frequency signal;
comparing said intermediate frequency signal with said predetermined nominal intermediate frequency signal and providing a tuning voltage to said microcomputer, said tuning voltage being indicative of the magnitude and direction of a tuning error between said intermediate frequency signal and said predetermined nominal intermediate frequency signal;
incrementally adjusting the reference oscillator frequency by means of a tuning signal provided to said reference oscillator by said microcomputer in response to said tuning voltage;
detecting when the incrementally changing, divided-down reference oscillator frequency causes the intermediate frequency signal to pass said predetermined nominal intermediate frequency signal; and
incrementally stepping the divided-down reference oscillator frequency back a predetermined number of steps following the passage of said predetermined nominal intermediate frequency signal by said intermediate frequency signal in tuning said television receiver to the selected channel.
"
A television tuning system employs a frequency synthesizer system for establishing the tuning of the receiver. A programmable frequency divider counter is connected between the output of a reference oscillator and a phase comparator to which the output of the local oscillator in the tuner also is applied. The phase comparator output provides a tuning voltage for controlling the tuning of the local oscillator. A microprocessor is used to control the count of the programmable frequency divider and initially to set a count corresponding to the selected channel in a counter connected between the output of the local oscillator and the phase comparator. The tuning consists of three discrete time periods. First, a settling time to allow channel change transients to settle; second, a short period of forced search at a relatively rapid rate to insure proper tuning; and third, a slower rate of step-by-step correction to accomodate for station drift and the like during reception. This third time period is initiated either by the passage of a fixed length of time following the start of the forced search period or by sensing a preestablished number of changes of state in the output of the frequency discriminator during the forced/search period.
1. A tuning system for the tuner of a television receiver capable of receiving a composite television signal and including frequency discriminator (AFT) circuit means, said system including in combination:
a reference oscillator providing a reference signal at a predetermined frequency;
a local oscillator in the tuner providing a variable output frequency in response to the application of a control signal thereto;
a programmable frequency divider means having first and second inputs coupled respectively to the output of said reference oscillator and said local oscillator for producing signals on first and second outputs having frequencies which are a programmable fraction of the frequency of the signals applied to the inputs thereto;
phase comparator means having one input coupled with the first output of said programmable frequency divider means and having another input coupled with the second output of said programmable frequency divider means for developing a control signal and applying such control signal to said local oscillator for controlling the output frequency thereof;
counter circuit means coupled with said programmable frequency divider means for initially setting said divider means to a predetermined division ratio and operating to change the programmable fraction of division thereof in accordance with changes in the count in said counter circuit means;
control circuit means coupled with the output of said frequency discriminator means and further coupled with said counter circuit means for causing said counter circuit means to count at a first rate in a predetermined direction determined by the state of the output signal from said discriminator means in the absence of a predetermined signal output from said frequency discriminator means until a predetermined maximum count is attained, thereupon resetting said counter circuit means to a count which is a predetermined amount less than said maximum predetermined count and continuing to count at said first rate in the same predetermined direction from said new count to continuously change the programmable fraction of said frequency divider means in accordance with the state of operation of said counter circuit means, said control means operating in response to said predetermined signal output from the frequency discriminator means for terminating operati
on of said counter circuit means; and further means for terminating operation of said counter circuit means at said first rate and causing operation thereof at a second slower rate.
2. The combination according to claim 1 wherein said further means includes timing means initiated into operation simultaneously with the setting of said divider means to a predetermined division ratio, and after a predetermined time interval said timing means producing an output signal applied to said counter circuit means to cause operation thereof to take place at said second slower rate. 3. The combination according to claim 1 wherein said counter circuit means includes a reversible digital counter coupled with said programmable frequency divider, means and said control circuit means causes said counter circuit means to count in said predetermined direction when the output of said frequency discriminator is of a first state and to count in the opposite direction when the output of said frequency discriminator is of second state; and said further means comprises means coupled with the output of said frequency discriminator and with said counter circuit means to take place at said second slower rate in response to a predetermined number of changes of state of frequency discriminator. 4. The combination according to claim 3 further including means responsive to the selection of a new channel in said television receiver for resetting said further means to an initial condition of operation. 5. The combination according to claim 4 wherein said further means comprises a search termination counter means operative to provide an output signal applied to said counter circuit means in response to a count thereby of a predetermined number of changes of state of said frequency discriminator to cause said counter circuit means to be operated at said second slower rate.
Both of the above mentioned patents are di
rected
to frequency synthesizer tuning systems for use with television
receivers to enable operation of the receivers with minimal viewer
fine tuning adjustments. By the utilization of the frequency
synthesizer tuning systems of these patents, the fine tuning
adjustment which is necessary with conventional types of television
receiver tuning systems has been substantially eliminated. The system
employed in the '953 patent permits utilization of a frequency
synthesizer tuning system which correctly tunes to a desired
television station or channel even if the transmitted signals from
that station are not precisely maintained at the proper frequencies.
The '535 patent is directed to a signal seek tuning system adaptation
of the frequency synthesizer tuning system of the '953 patent which
still permits implementation of all of the desired wide-band pull in
range of the frequency synthesizer system of the '953 patent. 
The systems of the foregoing patents operate effectively to correct automatically for frequency offsets in a frequency synthesizer tuning system without affecting the operation of the conventional frequency synthesizer used in the system. The systems of these patents are in widespread use commercially and permit direct selection, with automatic fine tuning adjustment, of any desired VHF channel which the viewer wishes to observe. In addition, the signal seek adaptation disclosed in the '535 patent couples all of the advantages of the frequency synthesizer tuning system of the '953 patent with the desirability of providing bidirectional signal seek operation.
While the systems disclosed in the foregoing patents operate in a highly satisfactory manner to accomplish the desired results of accurate tuning without the necessity of fine tuning adjustments, the circuitry for accomplishing the desired results is somewhat complex. It is desirable to reduce the circuit complexity and the number of signal detectors for accomplishing these results without compromising the accuracy of operation of the system.
SUMMARY OF THE INVENTION
Accordingly, it is an object of this invention to provide an improved tuning system for a television receiver.
It is an additional object of this invention to provide an improved frequency synthesizer tuning system for a television receiver.
It is another object of this invention to provide an improved frequency synthesizer tuning system for a television receiver which includes a provision for adjusting the synthesizer loop for frequency offsets in the received signal with a minimum number of signal detectors.
It is a further object of this invention to tune the local RF oscillator of a television receiver to the correct frequency for a selected channel with a frequency synthesizer tuning system, and automatically to change the reference frequency of the synthesizer system, or adjust the count of a programmable divider that produces a signal that divides the frequency of the local oscillator of the tuner, if the AFT signal produced by the AFT frequency discriminator of the receiver is outside a predetermined range corresponding to correct tuning.
It is still another object of this invention to provide an improved frequency synthesizer tuning system for a television receiver which operates to adjust the synthesizer loop for frequency offsets in the received signal over a relatively wide pull in range in response to the output of the receiver frequency discriminator by changing the division ratio of a programmable frequency divider in the reference oscillator leg or local oscillator leg of the synthesizer loop at a first relatively high rate from an initial nominal value to a pre-established maximum in one direction, and then resetting the division ratio to a second nominal value once the maximum is reached and continuing to incrementally change the division ratio in the same direction from the second nominal value until a properly tuned condition is indicated by the output of the receiver AFT frequency discriminator, followed by control at a lower rate of operation to maintain tuning during transmitting station drifts.
In accordance with a preferred embodiment of this invention, the frequency synthesizer tuning system for a television receiver includes a stable reference oscillator and a voltage controlled local oscillator in the tuner. A programmable frequency divider is connected between the output of the reference oscillator and one input to a phase comparator, the other input of which is supplied by the output of the local oscillator. The output of the phase comparator then comprises a control signal which is supplied to the local oscillator to control the frequency of its operation.
A counter circuit is connected to the programmable frequency divider for initially setting the divider to a predetermined division ratio upon selection of a desired channel by the viewer. The counter then operates to change the programmable fraction of the division ratio at a first relatively high rate in a direction controlled by the output from the r
eceiver
picture carrier discriminator in the absence of a predetermined
signal output derived from the discriminator. A control means causes
the counter circuit to count in this direction until it is determined
that a station is tuned or a predetermined maximum count is attained
if no station is correctly tuned, thereupon resetting the counter
circuit to a count which is a predetermined amount less than the
maximum predetermined count. Counting is continued in the same
predetermined direction from the new lesser count to continuously
change the programmable fraction of the frequency divider in
accordance with the state of operation of the counter.The high rate operation of the counter is terminated by the control means in response to a predetermined signal from the output of the discriminator, indicating that a station is correctly tuned, or after a fixed time-out interval; so that the system automatically adjusts for frequency offsets of the received signal which otherwise would cause the station to be mistuned if a conventional frequency synthesizer tuning system were used. After termination of the high rate operation of the counter, it is switched to a lower rate operation for maintaining tuning during transmitting station drifts.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a block diagram of a television receiver employing a preferred embodiment of the invention;
FIG. 2 is a detailed block diagram of a portion of the circuit of the preferred embodiment shown in FIG. 1;
FIG. 3 is a detailed circuit diagram of a portion of a circuit shown in FIG. 1;
FIG. 4 is a flow chart of the control sequence of operation of the circuit shown in FIG. 1 and 2; and
FIG. 5 shows a waveform and time/frequency chart, respectively, useful in explaining the operation of the circuit shown in FIGS. 1, 2 and 3.
DETAILED DESCRIPTION
Referring now to the drawings, the same reference numbers are used throughout the several figures to designate the same or similar components.
FIG. 1 is a block diagram of a television receiver, which may be a black and white or color television receiver. Mo
st
of the circuitry of this receiver is conventional, and for that
reason it has not been shown in FIG. 1. Added to the conventional
television receiver circuitry of FIG. 1, however, is a frequency
synthesizer tuning system, in accordance with a preferred embodiment
of the invention, which is capable of automatically changing the
reference frequency when a frequency offset exists in the received
signal for a particular channel. Transmitted composite television signals, either received over the air or distributed by means of a master antenna TV distribution system, are received by an antenna 10 or on antenna input terminals to the receiver. As is well known, these composite signals include picture and sound carrier components and synchronizing signal components, with the composite signal applied to an RF and tuner stage 11 of the receiver. The stage 11 includes the conventional RF amplifiers and tuner sections of the receiver, including a VHF oscillator section and a UHF oscillator section. Preferably, the UHF and VHF oscillators are voltage controlled oscillators, the freuency of operation of which are varied in response to a tuning voltage applied to them to effect the desired tuning of the receiver.
The output of the RF and tuner stages 11 is applied to the remainder of the television receiver 14, which includes the IF amplifier stages for supplying conventional picture (video) and sound IF signals to the video and sound processing stages of the receiver 14. The circuitry of the receiver 14 may be of any conventional type used to separate, amplify and otherwise process the signals for application to a cathode ray tube 16 and to a loudspeaker 17 which reproduce the picture and sound components, respectively, of the received signal.
The receiver 14 also includes a conventional AFT or automatic fine tuning discriminator circuit and additionally may include a synch separator circuit for producing an output in response to the presence of vertical synchronizatin pulses, a picture carrier detection circuit, and an automatic gain control (AGC) amplifier. Outputs representative of these sensor components are shown as being coupled over a group of lead 20 to sensory circuitry 22, w
hich in turn couples outputs representative of the operation of
these various sensor circuits to a microprocessor unit 23 for
controlling the operation of the microprocessor unit. The microprocessor unit 23 is utilized in the system of FIG. 1 for controlling the operation of a frequency synthesizer tuning system capable of automatic offset correction. When the viewer desires to select a new channel, he enters the desired channel number into a channel selection keyboard 25. There are a number of different keyboards which may be employed to accomplish this function, and the particular design is not important to this invention. The channel selector keyboard 25 also may include switches or keys for initiating a signal seek function in either the "up" or "down" direction.
Information represented by the selection of channel numbers on the keyboard 25 is supplied to the microprocessor unit 23 which provides output signals over a corresponding set of leads 27 to the tuners (local oscillators) 11 to effect the appropriate band switching control for the tuners 11 in accordance with the particular channel which has been selected. In addition, the keyboard 25, operating through the microprocessor unit 23, provides output signals which operate a channel number display 29 to provide an appropriate display of the selected channel number to the viewer.
The microprocessor M3870 unit 23 also processes the signals which are used to operate the channel number display 29 through a multiplexing circuit operation to decode the selected channel number into a parallel encoded signal. This signal is applied to corresponding inputs of the count-down counter or programmable frequency divider 31 to cause the division number of the divider 31 to relate to the divided down frequency of the tuner local oscillators connected to the input of the divider 31 through a prescaler divider circuit 32 to the frequency of the reference oscillator 34. Thus, the division number or division ratio of the local oscillator frequency obtained from the output of the programmable divider 31 is appropriately related to the frequency of the reference crystal oscillator 34.
The output of the oscillator 34 also is applied through a countdown circuit or programmable frequency divider 35. Conventional frequency synthesizer techniques are employed; and the microprocessor unit 23 automatically compensates, through appropriate code converter circuitry, for the non-uniform channel spacing of the television signals. It has been found most convenient to cause the programmable frequency divider 31 to divide by numbers corresponding directly to the oscillator frequency of the selected channel, for example, 101, 107, 113 . . . up to 931.
In accordance with the time division multiplex operation of the microprocessor 23, the count of the programmable frequency divider 35 initially is adjusted to a fixed count by the application of appropriate output signals from the microprocessor unit 23 to a point selected to be at or near the mid-point of the operating range of the programmable frequency divider 35. Thus, the output of the divider 35 is a stable reference frequency (because the input is from the reference crystal oscillator 34) which is used to establish initially and to maintain tuning of the receiver to the selected channel.
The output of the programmable divider 35 is applied to one of two inputs of a phase comparator circuit 37. The other input to the phase compara
tor
circuit 37 is supplied from the selected one of the VHF or UHF
oscillators in the tuner stages 11 through the programmable frequency
divider 31. The phase comparator circuit 37 operates in a
conventional manner to supply a DC tuning control signal through a
phase locked loop filter circuit 39 and over a lead 40 to the
oscillators in the tuner system 11 to change and maintain their
operating frequency. With the exception of the use of the microprocessor unit 23, the operation of the system which has been described thus far is that of a relatively conventional frequency synthesizer system incorporated into a television receiver. This system is similar to the system of the '953 patent. As in the system of that patent, the system shown in FIG. 1, when the transmitted station or station received on a master antenna distribution system provides the station or channel signals at the proper frequency, operates as a relatively conventional frequency synthesizer system. If, however, there is a frequency offset in the received signal to cause the carrier of the received signal to be displaced from the frequency which it should have to some other frequency, it is possible that the system would give the appearance of mistuning to the received station. The microprocessor 23, operating in conjunction with the sensory circuitry 22, is employed in conjunction with the countdown or programmable frequency divider circuit 35 to eliminate this disadvantage and still retain the advantages of frequency synthesizer tuning.
Reference now should be made to FIG. 2 which shows details of t
he
interface between the keyboard 25, the microprocessor unit 23, and
the circuitry used in the frequency synthesizer portions of the
system. A commercially available microprocessor which has been used
for the microprocessor 23, and which forms the basis for the
diagramatic representation of the microprocessor in FIG. 2, is the
Matsushita Electronics Corporation MN1402 four-bit single-chip
microcomputer. This microcomputer has two, four-bit parallel input
ports labeled "A" and "B". In addition, three output ports, a five-bit
output port "C" and two four-bit output ports "D" and "E" are
provided. The internal configuration of the microcomputer 23 includes
an arithmetic logic unit (ALU), a read only memory (ROM) for storing
instructions and constants, and a random access memory (RAM) used for
data memory, arranged into four files, each file containing 16
four-bit words. These words are selected by X and Y registers and this
memory is used, for example, for timers, counters, etc., and also is
used to hold intermediate results. To facilitate an understanding of
the operation of the system, a portion of this memory is shown in
FIG. 2 as a clock 81 and a reversible counter 82 connected between
the "B" input port and the "D" output port. The microcomputer 23 is
programmed to permit it to operate in conjunction with the remainder
of the circuits shown in FIG. 2. The programming techniques are
standard, and the microcomputer 23 itself is a standard commercially
available circuit component. There are several system parameters that must be selected in the operation of the system shown in FIG. 2. The selection of the nominal frequency of the two signals that feed the phase comparator circuit 37 is an example. Channel selection is provided by changing the frequency division ratio of the selector counter 31 which divides the local oscillator signal after this signal is passed through a prescaler circuit 32 and a divide-by-two divider circuit 41. The nominal frequency from the programmable frequency divider 31 (selector counter) is selected so that the local oscillator (tuner) 11 can be set exactly on frequency for all channels.
Since the frequency divider 31 is able to divide only by integer numbers, one distinct frequency possibility in the range of one KHz is obtained, another in the range of two KHz, etc. A choice must be made as to which of these values is optimum. Each value yields the nominal frequency of all of the 82 channels by simply multiplying by an appropriate integer for each channel. To simplify the phase locked loop filtering problem by the filter 39, it is desirable that the frequencies of the signals supplied to the phase comparator 37 are as high as possible. This permits rapid acquisition of a new channel along with a very clean DC control signal to adjust the local oscillator. A trade-off for this, however, must be made to permit fine tunning adjustment of the local oscillator automatically to correctly tune in stations which are off their assigned frequency, or to manually provide this feature, if desired. The two-speed operation of the system in accordance with the present invention allows a better trade-off to be made by allowing rapid acquisition and then a slower speed for precise tuning.
A compromise solution which is utilized in the circuit of FIG. 2 is to cause the frequency division chain from the local oscillator 11 in the tuner to the phase comparator 37 to be composed of the fixed divide-by-256 prescaler 32, and a fixed divide-by-4 division, which is accomplished by the divider 41 at the input of the counter 31 and a second divider 42 at the output of the counter 31. The variable frequency divider counter 31 then is loaded by means of three latch circuits 44, 45 and 46 at an appropriate time by the time division multiplex operation of the microcomputer 23 and a number that programs the programmable frequency divider counter 31 to divide by the numerical value of the frequency of the local oscillator in MHz for the channel selected. For example, if the receiver is to be tuned to channel 2, which has a nominal local oscillator frequency of 101 MHz, the programmable frequency divider 31 is set to divide by 101. If the receiver is to be tuned to channel 83, which has a nominal local oscillator frequency of 931 MHz, the programmable frequency divider 31 is set to divide by 931. In both cases, the variable divider 31 produces a 1 MHz signal. However, because of the fixed divide-by-256 and the two fixed divide-by-two dividers in series with the programmable divider 31, an output frequency of 976.5625 Hz is supplied from the output of the divider 42 to the upper input of the phase comparator 37.
The division ratio of the selector counter 31 is established by appropriate output signals from the latch circuits 44, 45 and 46, as mentioned above. The initial operation for changing, or maintaining, the division ratio of the divider 31 is established by an entry of the two digits of the selected channel number in the keyboard 25. The microcomputer 23 operates as a time division multiplex system for continuously monitoring the input ports and the output ports to control the operation of the remainder of the system. The selection of the two digits of the desired channel number is affected by a time division multiplex iscanning of the outputs of the D output port of microcomputer 23 and providing that information at the A input port. From here the information is translated again to the D output ports to the appropriate drivers of the channel number display circuit 29 and to the latches 44, 45 and 46, and to a pair of similar four bit latches 49 and 50 which control the divider ratio of the counter 35.
Although the D output ports of the microcomputer 23 are connected in common to all of these various portions of the circuit, the selection of which of the latches are enabled to respond to the particular output signals appearing on the D output ports at any given time is effected through the C and E output ports of the microcomputer 23 in a time division multiplex fashion. A decoder circuit 52, connected to the lowermost three outputs of the E output port of the microcomputer 23, is used to apply unique decoding signals at different times in the time division multiplex sequence of operation of the microcomputer 23 to the five latch circuits 44, 45, 46, 49 and 50, respectively. At any given time in the sequence, only one of these latch circuits is enabled for operation. A latch load signal is applied from the upper output (EO3) at each cycle of operation of the signals appearing on the E output port to set the latch circuit which is enabled by the output of the decoding circuit 52 with the data appearing on the other inputs to the latch circuit. This data simultaneously appears on the four outputs of the D output port of the microcomputer 23.
Thus,
in rapid sequence, the latch circuits 44, 45 and 46 are set to store
the division number corresponding to the selected channel entered
onto the keyboard 25, and the latch circuits 49 and 50 are each
operated to set the programmable divider reference counter 35 to a
center or nominal count, which is always the same upon the selection
of a new channel on the keyboard 25. Similarly, the two right-hand
outputs of the C output port (CO6 and CO5) enter the two digits of
the selected channel number in the drivers of the display circuit 29
at the proper time in the binary encoded sequence when these digits
appear on the four-bit binary encoded representation of the D output
port. This results in a visual display of the channel number
selected. In addition to the selection of a channel number directly by the keyboard 25, the keyboard also may include an additional switch 56, which is scanned in the time division multiplex sequence to determine if the receiver is placed in a "seek" mode of operation (when the signal seek capability is incorporated into such a receiver). Operating in conjunction with the signal seek switch 56 are a pair of "up" and "down" seek direction input switches shown with a graphic representation of the seek directions on the keyboard 25. A further provision is provided by two keys labeled "U" and "D", which are used for "manual" fine tuning of the receiver in the "up" or "down" directions depending upon which of the two keys U or D has been operated. The keyboard 25 includes one additional switch 58 which may be used to disable the automatic fine tuning (AFT) portion of the circuit by rendering the microcomputer insensitive to the signal output from the AFT circuit, in a manner described more fully subsequently.
As is apparent from the foregoing, the microcomputer 23 provides the intelligence, decision making, and control for the system operation. It is a complete self contained computer. The decisions or signal inputs upon which the microcomputer 23 bases its operation include, in addition to the inputs from the keyboard 25, inputs on sensory inputs into the B input port and into the SNS1 and SNS0 inputs as shown in FIG. 2. These input signals are used to provide an indication to the microcomputer 23 of the presence or absence of a received signal; and if the presence of such a signal is indicated, the inputs provide a further indication of the accuracy of the tuning of the receiver to that signal. If the system is being operated solely in a manual mode of operation (AFT switch 58 open), the microcomputer 23 disregards all of this sensory information and tunes to the frequency allocation of the channel selected in the manner described above. The system will stay tuned to this condition, operating as a conventional frequency synthesizer, whether or not a station is present in the received signal.
When the system is placed in its automatic mode of operation (simila
r
to the mode of operation of the above mentioned '953 patent), the
counter 82, integrally formed as part of the microcomputer 23,
continuously adds or subtracts one number at a time from the nominal
value or programmable division fraction entered into the programmable
frequency divider 35 at the outset of each new channel number
selection when frequency offset (mistuning) is present. The counter
82 is driven at a relatively high counting rate by clock pulses from
the clock 81 during this initial or forced search mode of operation.
Thus, automatic offset correction is provided for any channel which
is off its assigned frequency. The offset correction automatically
adjusts the frequency of the local oscillator by changing the
division ratio of the signal from the reference oscillator 35 applied
to the lower input of the phase comparator 37. By doing this, the
output of the phase comparator 37 applied to the local oscillator 11
varies to cause the oscillator to be tuned in the proper direction to
compensate for the transmitting station mistuning. When the system is operating in its automatic mode of operation, the microcomputer 23 responds to the sensor information applied to it on its B input ports and on the S1 input port shown in FIG. 2. These inputs are obtained from the various outputs of the operational amplifiers shown connected to the corresponding input ports in the detailed circuit of FIG. 3. Depending upon whether the receiver is provided with a signal seek feature or not, one or more of the sensory inputs of the circuit of FIG. 3 are used. The s
ystem
shown in the drawings has a capability of correcting for frequency
offsets larger than 1.5 MHz on channels 2 and 7 and approximately 2
MHz on channels 6 and 13. The remainder of the channels have a range
between these two values. If the receiver is not tuned properly, the micromputer 23 executes the localized search of the tuning range mentioned above. Since there is a necessary settling down time for the tuning of a television receiver immediately following selection of a new channel, a time interval of 250 milliseconds has been selected to prevent any localized search or offset frequency correction until the expiration of this "settling down" time period. If, at the end of this 250 millisecond time interval, a properly tuned station is present, this is indicated by the sensory outputs from the television receiver and no localized search is effected to change the division ratio or programmable divider count in the reference counter 35 for a system that also has signal seek.
A system with no signal seek capability is described later that requires less sensory input but which uses a time period where a forced search is required directly after the settling time interval.
Upon termination of the 250 millisecond settling down period, the microcomputer 23 is rendered responsive to the sensory input signals on its sensory input signal ports. In the simplest form, only the output of the frequency discriminator 60 (FIG. 3) applied to three comparators 61, 62 and 63 is used to provide the necessary tuning information to the microcomputer 23. The outputs of these comparators are applied to the B12 and B11 inputs of the microcomputer.
The comparator 61 simply is a conventional comparator for determining whether or not the output of the frequency discriminator is positive or negative, as indicated in the upper waveform of FIG. 5. The comparators 62 and 63 are each adjusted with appropriate reference input levels to provide a narrow window centered about the center tuning frequency (fc) of the receiver. If the tuning of the receiver, as indicated by the output of the frequency discriminator 60, is outside this window on either side of the central axis shown in FIG. 5, one output condition is indicated on the input terminal B11 of the microcomputer. Only when the tuning frequency is within the tuning window, indicative of a properly tuned receiver, is the appropriate input applied to the microcomputer input terminal B11. This input overrides any other input that may be present on the input terminal B12 and is indicative of a properly tuned receiver. The input from the frequency discriminator 60, as applied to the microcomputer on its input port B12, is used to determine the direction of operation of the counter 82 of the microcomputer for the localized search count signals applied to the latch circuits 49 and 50 to change the count of the reference programmable divider counter 35 on a step-by-step basis.
The lower graph of FIG. 5 plots the relative frequency of the local oscillator 11 to the received signal frequency with respect to time. The various arrows are used to indicate the manner of operation of the counter 82 in the microcomputer 23 in conjunction with the reference counter 35 for adjusting for any mistuning conditions which may exist after the initial station selection has been effected in the manner described above.
If the receiver is properly tuned, the outputs from the comparators 62 and 63 of FIG. 3 which are combined together and applied to the input port B11 of the microcomputer 23, provide an indication that the tuning is within the properly tuned center frequency window. As a consequence, no further operation of the microcomputer to change any of the outputs applied to the latch circuits 49 and 50 for the duration of this condition is effected. On the other hand, if the receiver is mistuned on either side of the proper tuning frequency, the various operating characteristics shown in FIG. 5 are effected.
Assume initially
that the receiver is capable of making tuning adjustments over a
range of fc plus Δf to fc minus Δf, as indicated in the top waveform
of FIG. 5. Three specific examples of mistuning will then be
considered. Initially, assume that the local oscillator is mistuned
relative to the received signal to a frequency f1 as shown in the
lower graph of FIG. 5. In this condition, the outout of the frequency
discriminator 60 is positive since this signal frequency lies to the
lefthand side of the center or properly tuned region of operation of
the discriminator. Under this condition of the operation, the input
signal applied to the sensor port B12 of the microcomputer 23 is such
that the microcomputer counter 82 is caused to advance in a positive
direction to change the programmable division ratio or count of the
reference counter 35 in a manner to force the output of the phase
comparator 37 to adjust the frequency of the local oscillator until
the proper tuning indicated at point B in the lower graph of FIG. 5
is reached. The time interval for accomplishing this result is
measured from the upper end of the arrow representative of the
frequency f1 to the point B. Now assume that the receiver mistuning is to a frequency f2 which as shown in FIG. 5 as located on the righthand-side of the center axis fc. In this condition, the discriminator output is negative. This is reflected in the output of the comparator 61 applied to the input port B12 of the microcomputer 23. The polarity of this signal is identified by the microcomputer 23 to cause the counter 82 in it to operate in the reverse direction. As this count is applied on a step-by-step basis through the latch circuits 49 and 50 to the reference counter 35, the division ratio or count of the reference counter (divider) 35 is changed. As a result, the reference oscillator signal applied to the phase comparator 37 causes the phase comparator 37 output to drive the local oscillator frequency in a direction opposite to that considered in the first example. This is shown by the vector interconnecting the top of the arrow representative of f2 to point A on the time/frequency graph of FIG. 5.
As discussed in the general d
iscussion
above, whenever the tuning frequency reaches the narrow window on
either side of fc, the outputs of the comparators 62 and 63 provide
the necessary indication on the sensory input port terminal B11 to
cause termination of the operation of the counter 82 in the
microcomputer 23. Then the reference counter 35 remains set to the
count attained just prior to the appearance of this input signal on
the input port B11 of the microcomputer 23. A third mistuning condition can exist, and ordinarily this condition results in an ambiguity which cannot be corrected simply by responding to the signal polarity at the output of the frequency discriminator. This is indicated by the mistuned condition where the difference between the local oscillator frequency f3 and the transmitter frequency is such that the signal f3 lies in the range to the right of the negative portion of the discriminator output shown in the upper waveform of FIG. 5. In this condition, the associated sound causes the discriminator output to be positive; so that the television receiver normally would attempt to tune toward the next adjacent channel and away from the properly tuned center frequency of the channel which is desired. The output of the discriminator 60 in this situation is the same as it was in th
e
first example considered for frequency f1; so that the counter 82 of
the microprocessor 23 operates to change the count in the reference
counter 35 in a manner to cause the local oscillator frequency to go
higher toward a frequency f3 +Δf, as shown in FIG. 5. A predetermined number of counts of the counter 82 in the microcomputer 23 are necessary for the microcomputer to count through the frequency range Δf, and this range is selected to be within the pull in or operating range of the system. Once this count has been attained, the microcomputer counter 82 immediately is reset back to a count which corresponds to a frequency 2 Δf lower than the frequency attained by the maximum count. This is indicated in FIG. 5 by the frequency f3-Δf. Because the microcomputer counter 82 is limited to counting a number of counts equal to Δf, this new frequency now is on the lefthand side of the center line fc, shown in both waveforms of FIG. 5. This places the local oscillator frequency at a point such that the frequency discriminator output is the positive output shown on the lefthand-side of the upper waveform of FIG. 5. Counting continues in the same direction as previously. This time, however, it is in a proper direction to bring about correct tuning; and when the center frequency is reached, the output of the comparators 62 and 63 cause the microcomputer 23 to stop its count. The proper tuning point attained is indicated at point C on the graph of the lower part of FIG. 5.
Because the counter 82 of the microcomputer is limited to a maximum count equivalent to Δf above its initial count and thereupon is reset to a new count equivalent to 2 Δf lower than the maximum count, it is not necessary to utilize any other sensory inputs in order to properly tune the receiver over a wide pull in range (as much as plus or minus 2 MHz). Only the output of the conventional frequency discriminator 60 is used to provide the necessary sensory inputs.
The counter 82 of the microcomputer 23 is operated by the clock 81 during the foregoing sequence of operation, immediately following the selection of a new channel by the operation of the keyboard 25, at a fast or high speed operation. Typically, the counter steps are 10 milliseconds per step; so that there are no initial visual effects which can be noticed by an observer of the television screen of the receiver being tuned. The maximum forced search period is approximately 900 milliseconds in duration. At the end of this time interval, a timer in the
microcomputer 23 causes a signal to be
applied through the outputs of the E output port to the decoder
circuit 52 indicative of the completion of this time interval. The
decoder 52 then applies a pulse on an output lead connected to the B13
input of the B input port of the microcomputer 23. This pulse is
sensed by the microcomputer 23 and is applied to the clock 81 to
change the clock rate to a much slower rate, approximately one-third
(1/3) or one-fourth (1/4) the rate used previously during the forced
search mode of operation. This then permits the system to accomodate
station drifts which normally occur at a very slow rate during the
transmission and reception of a television signal. As a consequence,
it is possible to use more filtering in the filter 39 on the tuning
line (FIG. 1) and employ a smaller frequency window for the channel
verification sensed by the circuitry shown in FIG. 3. The result is a
more precise tuning from the receiver than is otherwise possible if
only a high speed operation of the clock 81 is utilized. When the channel once again is changed by operation of the keys in the keyboard 25 or operation of the channel selection circuitry from a remote control unit, this new channel input is sensed by the microcomputer 23 from the signals applied to the A input port and the clock 81 is reset to its fast time or the forced search mode of operation; and the process resumes.
Instead of employing an additional decoding function in the decoder 52, a separate decoder also could be connected to the outputs of the D output ports to feed back the signal to the B13 input terminal of the B input port of the microcomputer 23. The operation of the system to change the rate or frequency of the pulses applied by the clock 81 to the counter 82 otherwise is the same as described above.
Although applicant has found that it is preferable to correct for mistuning or frequency offsets by adjusting the count or division ratio of the counter 35, such offset adjustments also could be effected by adjusting the count in the counter 31 in the local oscillator signal line. The operation in such a case is the same as described above for adjusting the count in the counter 35.
If the receiver is to be used with an automatic signal seek mode of operation, however, additional sensory inputs are necessary. These inputs operate in conjunction with the output of the frequency discriminator 60. The operation of the microcomputer 23 in controlling the count of the reference programmable frequency counter divider 35 is the same as described above. The additional sensory inputs simply are used in conjunction with the outputs of the comparators 62 and 63 to signal the microcomputer 23 to assure that tuning is to a picture channel rather than an adjacent sound channel. This is accomplished by utilizing the output of the synchronizing signal separator 65 which is applied to a comparator 67 to produce an output sign
al to the SNS1 sensory
input of the microcomputer 23 only when vertical synchronizing signal
components are present. In addition, the output of a picture carrier detector 69 is applied to the input of a comparator 70 to produce an output to the B10 sensory input of the microcomputer 23. If the picture carrier detector 69 is producing an output indicative of the presence of a carrier, but no output is being obtained from the vertical synch separator 65 at the same time, the system is mistuned to a sound carrier and the microcomputer 23 is permitted to continue its localized search until a properly tuned station is found. Only when there is coincidence of signals from the picture carrier detector 69, the synch signal separator 65, and the automatic frequency discriminator window as determined by the comparators 62 and 63, is the microcomputer operation terminated to indicate that a properly tuned channel is present.
Further insurance of tuning the receiver only to a strong signal also can be provided by the addition of an AGC amplifier 72. This is connected to a comparator 74 coupled to the B10 input port along with the output of the picture carrier detector comparator 70. When the AGC amplifier 72 is used as a sensory input, the microcomputer operation, when the system is used in a signal seek mode, is only terminated to indicate reception of a valid signal when that signal is strong enough to produce the desired output from the comparator 74. The signal level which is acceptable is set by a potentiometer 75.
It should be noted that when the system is operated in a signal seek mode, the sensory inputs must indicate the reception of a properly tuned signal within a pre-established time period. If no signal is sensed by the various sensory input circuits operating in conjunction with one another as described above, the microcomputer 23 automatically steps to the next channel number and repeats the sequence of operation described above. This is when it is placed in its signal seek mode of operation. If signal seek is not employed, the additional sensory circuits 65, 69 and 72 are not necessary, and the inputs to the microcomputer which are provided from these sensory circuits are not utilized. The sensory signal input which is used both for a receiver without a signal seek capability of operation and for a receiver which has a signal seek mode of operation in it, is the output of the frequency discriminator 60 operating in conjunction with the comparators 61, 62 and 63 as described above.
As indicated above, the wideband method of tuning precisely to an incoming signal that is at the wrong frequency described here only needs the frequency discriminator sensory information. The method that uses the additional sensors described above is needed to make this system operate compatibly with signal seek but it is not restricted to seek operation.
For a system that does not use signal seek operation, only the frequency discriminator sensory input is required for proper operation. The discriminator 60 is used for both fine tuning direction information and to produce a frequency window to indicate the presence of a correctly tuned station (channel verification). Initially, after a channel change, there is a 250 millisecond settling time, the same as the operation described above with compatible seek. After that, however, comes a period of time where a forced localized search is produced by the microcomputer 23. The forced search is needed to insure that the system will correctly tune to stations that initially may be tuned to the undesired zero voltage crossover in the right half of the upper curve of FIG. 5. Such signals may be within the frequency window of the discriminator 60; and if a search is not forced, this system will not correctly tune. The compatible seek system described previously correctly tunes the local oscillator without a forced search, because the picture carrier detector and vertical detector do not give an output for this situation and the system automatically goes into its search mode of operation. However, the non-seek system does not have a picture carrier sensor input and must be forced to search for an initial period of time sufficient to allow the system to tune up to its maximum frequency and then reset (loop) back to a frequency of 2 Δf lower. Then it is tuned to the positive left half portion of the discriminator curve (FIG. 5) and the frequency window created by the discriminator 60 is sufficient to insure proper tuning. If the discriminator output produced by the desired incoming signal created an initial situation that produces the correct tuning direction information, i.e., in the left half of the curve of FIG. 5, or in the right half portion that gives the correct direction and
frequency window information, the forced search would not be needed. However, the forced search will produce a correct tuning situation anyway. In these cases, the tuning either is correct to begin with or correct tuning is reached quickly. Then, even though the forced search is active, it simply alternates up and down through the correct tuning point because each time the receiver is tuned a little high in frequency, it produces a negative output from the discriminator 60; and the tuning direction signal causes the system to tune down in frequency.
Then, a positive discriminator output is produced, and the system tunes up in frequency. This continues until the forced search is removed by time-out of the microcomputer 23 (a fraction of a second). At such time, the receiver is correctly tuned by the frequency window of the discriminator to be very near fc. The system cannot tune to the undesired discriminator crossover shown in the right half portion of FIG. 5 because the polarity of the tuning direction signal always causes it to tune away from that point.
The fast time or forced search operation of the system can be terminated in a different way other than the preestablished time-out period described above in conjunction with the operation of the circuit shown in FIG. 2. Generally, it is desirable to build into the system (or program into the system by means of software) such a maximum time-out period to effect the operation which has been described above to terminate the search and cause the clock 81 thereafter to operate in a low speed mode of operation. Termination also can be accomplished by sensing the number of changes in the direction sensor input applied to the B12 terminal of the B input port to cause the search to be terminated when this direction changes three times (or more). By doing this, any flicker that might be observed on the screen of the television receiver is minimized, since the forced search still takes place at the high rate of application of clock pulses from the clock 81 to the counter 82 in the same manner described above.
Termination of the search, however, also may be effected by means of a search terminate counter 78 (FIG. 3), which is advanced by pulses applied to it each time the output of the comparator 61 changes its sign (indicative of a change in direction for the counter 82) as applied to it through the B12 input port, as described earlier. After three of these changes, or some other number if desired, an output pulse is obtained from the search terminate counter 78 and is applied to the SNS0 input of the microcomputer 23. This causes the operation of the clock 81 to be switched to its low speed mode of operation to terminate the fast or "forced search" mode of operation. The next time a new channel number is entered on the keyboard 25, a reset pulse is applied to the search terminate counter 78 to reset it to its original or zero count, thereby readying it for another sequence of operation. It is apparent that the search terminate counter 78 may not always be operated to terminate the count, since the time-out interval which is sensed by the decode circuit 52 and applied to the B13 input port of the microcomputer 23 may occur before there are three changes of direction of the search. In any event, the next time a new channel number is entered into the keyboard 25, the search terminate counter 78 is reset; so that it is irrelevant whether this counter reaches a full count or not to effect the termination of the forced search operation of the system.
FIG. 4 shows the control sequence of the system whic
h
is stored in the ROM (Read Only Memory) of the microcomputer 23. The
microcomputer 23 operates by always running through the flow
sequence, via loops L1, L2 and L3. Loop L1 corresponds to a new
channel selection by two digit number entry. Loop L2 corresponds to
channel number increment or decrement by an up or down key operation,
respectively, or by seek operation. Loop L3 corresponds to fine
tuning, either manual or automatic. To obtain exact timing for system
control, the microcomputer 23 receives a standard timing pulse from
the output of the reference counter 35 divided in a divide-by-five
counter 80 and applied to the A13 input port of the microcomputer 23.
The control functions which are programmed into the microcomputer 23,
as indicated in the flow chart of FIG. 4, are outlined in the
following paragraphs. Channel Number Correction: An invalid two digit channel number entry (0, 1, 84, 99) is corrected. When the operation of the receiver is in the signal seek mode, the next channel up from 83 is channel 2, and the next lower channel from channel 2 is 83.
PLL Control I: For a given channel number, a corresponding binary code for the PLL selector counter 31 is derived as described previously. For UHF channels, the local oscillator frequency separation between two adjacent channels is 6 MHz and the code for PLL is generated by the microcomputer 23 through means of a simple calculation. This code then is transferred from the microcomputer 23 to the latches 44, 45 and 46 as described previously.
PLL Control II: This routine of the microcomputer 23 is used to transfer the fine tuning data to the latches 49 and 50 which control the count of the reference counter 35 in the PLL circuit.
Channel Number Display: The channel number is transferred from the microcomputer 23 to the driver latc
hes of the display driver circuit 29. Key Input Detection: The keyboard is arranged as the matrix circuit shown in FIG. 2. ROM programming for scanning and acknowledging a keyboard entry only after successive indications provides protection against false entry due to contact bounce. The four data output lines of the D output port of the microcomputer 23 are used to transfer data to the phase lock loop section of the circuit and to the display circuit 29, as well as for scanning the keyboard matrix circuit.
Time Count: The microcomputer 23 receives a basic timing pulse of approximately 200 Hz from the output of the divider 80 and performs various controls for each timing pulse. By way of example, sensing for the vertical synch input (when the system is used with a signal seek capability) on the input port SNS1 takes place every 2.5 milliseconds. Automatic seek timing is selected to be 133 milliseconds for UHF channels. All of these timing pulses are derived from the basic synchronization timing pulse applied to the microcomputer on the A13 input port from the output of the divider 80. Various other timing values used in the microcomputer to properly time multiplex sequence the operation are derived from this basic timing pulse.
Sensor Input Detection: As described previously, the output of the comparators shown in FIG. 3 reflect the status of the tuning of the television receiver. If no signal seek mode of operation is used, only the frequency discriminator or AFT discriminator 60 is necessary. When a system is being used in a signal seek mode, a proper television signal receipt is indicated by the presence of a vertical synch signal at the output of the synch signal separator 65 and corresponding outputs are applied to the input leads B10 and B11 (high level input signals) indicative of tuning to the "correct tuned" frequency discriminator window and reception of a picture carrier. As stated previously, the signal present on the B12 input lead is used to determine the direction of tuning when the receiver is operated in its automatic mode.
Mode Detection: The status of the seek and automatic/manual (A/M) switches are detected. If the A/M switch (not shown) is in its automatic position, automatic seek and offset correction are active. If only the seek switch is on, only seek is performed. If the A/M switch is in manual, manual fine tuning (MFT) is active.
Automatic Mode: If the TV receiver is not properly tuned for VHF channels in automatic, the local oscillator frequency is shifted automatically toward proper tuning. The fine tuning data is generated in the microcomputer 23 and is transferred to the latches 49 and 50 for the reference counter 35 in the PLL circuit.
Manual Fine Tuning (MFT) Control: The local oscillator frequency is shifted by pushing the fine tuning up (U) or down (D) pushbutton or switch. This MFT control can be applied to VHF channels as well as to UHF channels.
Channel Up/Down: When a channel up (upward pointing arrow) or down (downward pointing arrow) key closure in the keyboard 25 is detected, or upon a direct access to an unused channel, this routine is activated and the system will advance to the next channel in the selected direction.
The foregoing embodiment of the invention which has been described above and which is illustrated in the drawings is to be considered illustrative of the inventi
on,
which is not limited to the specific embodiment selected for this
purpose. For example, hard-wired logic could be used to achieve the
various circuit operations which are accomplished by the microcomputer
23 in conjunction with the other portions of the system. The relative
ease of programming and debugging the microcomputer 23, however,
make it much simpler to implement the system operation with the
microcomputer than with hard-wired logic. With respect to the sensor
circuit inputs to the system, an added degree of operating assurance
can be provided by the addition of a sound carrier sensor in addition
to the picture carrier sensor shown in FIG. 3. If this feature is
desired, the output of the comparator for the sound carrier is combined
with the outputs of the comparators 70 and 74 at the input terminal
B10 of the B input port of the microcomputer 23. Because of the
manner of the circut operation which has been described previously,
however, the addition of a sound carrier detector to the system is
not considered necessary, even for a system operating in the signal
seek mode of operation. This is in contrast to conventional
television receivers having a signal seek operation, in which
detection of the sound carrier generally is a necessity to insure
that mistuning of the receiver to an adjacent sound carrier does not
take place.
TDA3300 3301 TV COLOR PROCESSOR
This device will accept a PAL or NTSC composite video signal and output the
three color signals, needing only a simple driver amplifier to interface to the pic-
ture tube. The provision of high bandwidth on-screen display inputs makes it
suitable for text display, TV games, cameras, etc. The TDA3301 B has user con»
trol laws, and also a phase shift control which operates in PAL, as well as NTSC.
- 0 Automatic Black Level Setup
- 0 Beam Current Limiting
- 0 Uses Inexpensive 4.43 MHZ to 3.58 MHz Crystal
- 0 No Oscillator Adjustment Required
- 0 Three OSD Inputs Plus Fast Blanking Input
- 0 Four DC, High Impedance User Controls
- 0 lnterlaces with TDA33030B SECAM Adaptor
- 0 Single 12 V Supply
- 0 Low Dissipation, Typically 600 mW
The brilliance control operates by adding a pedestal to the output
signals. The amplitude of the pedestal is controlled by Pin 30.
During CRT beam current sampling a standard pedestal is
substituted, its value being equivalent tothe value given by V30 Nom
currents at the sampling level, i.e. 3x20 |.1A with 100 k reference
resistors on Pins 16, 19, and 22.
During picture blanking the brilliance pedestal is zero; therefore, the
output voltage during blanking is always the minimum brilliance black
level (Note: Signal channels are also gain blanked).
Chrominance Decoder
The chrominance decoder section of the TDA3301 B
consists of the following blocks:
Phase-locked reference oscillator;
Phase-locked 90 degree servo loop;
U and V axis decoders
ACC detector and identification detector; .
Identification circuits and PAL bistable; .
Color difference filters and matrixes with fast blanking
Circuits.
The major design considerations apart from optimum
performance were:
o A minimum number of factory adjustments,
o A minimum number of external components,
0 Compatibility with SECAM adapter TDA3030B,
0 Low dissipation,
0 Use of a standard 4.433618 Mhz crystal rather
than a 2.0 fc crystal with a divider.
The crystal VCO is of the phase shift variety in which thefrequency is controlled by varying the phase of the feedback.
A great deal of care was taken to ensure that the oscillator loop
gain and the crystal loading impedance were held constant in
order to ensure that the circuit functions well with low grade
crystal (crystals having high magnitude spurious responses
can cause bad phase jitter). lt is also necessary to ensure that
the gain at third harmonic is low enough to ensure absence of
oscillation at this frequency.
It can be seen that the
necessary 1 45°C phase shift is obtained by variable addition
ol two currents I1 and I2 which are then fed into the load
resistance of the crystal tuned circuit R1. Feedback is taken
from the crystal load capacitance which gives a voltage of VF
lagging the crystal current by 90°.
The RC network in the T1 collector causes I1 to lag the
collector current of T1 by 45°.
For SECAM operation, the currents I1 and I2 are added
together in a fixed ratio giving a frequency close to nominal.
When decoding PAL there are two departures from normal
chroma reference regeneration practice:
a) The loop is locked to the burst entering from the PAL
delay line matrix U channel and hence there is no
alternating component. A small improvement in signalnoise ratio is gained but more important is that the loop
filter is not compromised by the 7.8 kHz component
normally required at this point for PAL identification
b) The H/2 switching of the oscillator phase is carried out
before the phase detector. This implies any error signal
from the phase detector is a signal at 7.8 kHz and not dc.
A commutator at the phase detector output also driven
from the PAL bistable coverts this ac signal to a dc prior
to the loop filter. The purpose ot this is that constant
offsets in the phase detector are converted by the
commutator to a signal at 7.8 kHz which is integrated to
zero and does not give a phase error.
When used for decoding NTSC the bistable is inhibited, and
slightly less accurate phasing is achieved; however, as a hue
control is used on NTSC this cannot be considered to be a
serious disadvantage.
90° Reference Generation
To generate the U axis reference a variable all-pass network
is utilized in a servo loop. The output of the all-pass network
is compared with the oscillator output with a phase detector of
which the output is filtered and corrects the operating point of
the variable all»pass network .
As with the reference loop the oscillator signal is taken after
the H/2 phase switch and a commutator inserted before the
filter so that constant phase detector errors are cancelled.
For SECAM operation the loop filter is grounded causing
near zero phase shift so that the two synchronous detectors
work in phase and not in quadralure.
The use of a 4.4 MHz oscillator and a servo loop to generate
the required 90° reference signal allows the use of a standard,
high volume, low cost crystal and gives an extremely accurate90° which may be easily switched to 0° for decoding AM
SECAM generated by the TDA3030B adapter.
ACC and Identification Detectors
During burst gate time the output components of the U and
also the V demodulators are steered into PNP emitters. One
collector current of each PNP pair is mirrored and balanced
against its twin giving push-pull current sources for driving the
ACC and the identification filter capacitors.
The identification detector is given an internal offset by
making the NPN current mirror emitter resistors unequal. The
resistors are offset by 5% such that the identification detector
pulls up on its filter capacitor with zero signal.
Identification
See Figure 11 for definitions.
Monochrome I1 > I2
PAL ldent. OK I1 < lg
PAL ldent_ X l1 > I2
NTSC I3 > I2
Only for correctly identified PAL signal is the capacitor
voltage held low since I2 is then greater than I1.
For monochrome and incorrectly identified PAL signals l1>l2
hence voltage VC rises with each burst gate pulse.
When V,ef1 is exceeded by 0.7 V Latch 1 is made to conduct
which increases the rate of voltage rise on C. Maximum
current is limited by R1.
When Vref2 is exceeded by 0.7 V then Latch 2 is made to
conduct until C is completely discharged and the current drops
to a value insufficient to hold on Latch 2.
As Latch 2 turns on Latch 1 must turn off.
Latch 2 turning on gives extra trigger pulse to bistable to
correct identification.
The inhibit line on Latch 2 restricts its conduction to alternate
lines as controlled by the bistable. This function allows the
SECAM switching line to inhibit the bistable operation by firing
Latch 2 in the correct phase for SECAM. For NTSC, Latch 2
is fired by a current injected on Pin 6.
lf the voltage on C is greater than 1.4 V, then the saturation
is held down. Only for SECAM/NTSC with Latch 2 on, or
correctly identified PAL, can the saturation control be
anywhere but minimum.
NTSC Switch
NTSC operation is selected when current (I3) is injected into
Pin 6. On the TDA33O1 B this current must be derived
externally by connecting Pin 6 to +12 V via a 27 k resistor (as
on TDA33OOB). For normal PAL operation Pin 40 should be
connected to +12 V and Pin 6 to the filter capacitor.
4 Color Difference Matrixing, Color Killing,
and Chroma BlankingDuring picture time the two demodulators feed simple RC
filters with emitter follower outputs. Color killing and blanking
is performed by lifting these outputs to a voltage above the
maximum value that the color difference signal could supply.
The color difference matrixing is performed by two
differential amplifiers, each with one side split to give the
correct values of the -(B-Y) and -(Ft-Y) signals. These are
added to give the (G-Y) signal.
The three color difference signals are then taken to the
virtual grounds of the video output stages together with
luminance signal.
Sandcastle Selection
The TDA3301B may be used with a two level sandcastle
and a separate frame pulse to Pin 28, or with only a three level
(super) sandcastle. In the latter case, a resistor of 1.0 MQ is
necessary from + 12 V to Pin 28 and a 70 pF capacitor from
Pin 28 to ground.
Timing Counter for Sample Control
In order to control beam current sampling at the beginning
of each frame scan, two edge triggered flip-flops are used.
The output K ofthe first flip-flop A is used to clock the second
tlip-flop B. Clocking of A by the burst gate is inhibited by a count
of A.B.
The count sequence can only be initiated by the trailing
edge of the frame pulse. ln order to provide control signals for:
Luma/Chroma blanking
Beam current sampling
On-screen display blanking
Brilliance control
The appropriate flip-flop outputs ar matrixed with sandcastle
and frame signals by an emitter-follower matrix.Video Output Sections
Each video output stage consists of a feedback amplifier in A further drive current is used to control the DC operating
which the input signal is a current drive to the virtual earth from point; this is derived from the sample and hold stage which
the luminance, color difference and on-screen display stages. samples the beam current after frame flyback.
MOTOROLA TDA3303:TV COLOR PROCESSOR is a TV PAL/NTSC color processor.
In the Secam system, the colour information of a televised image is transmitted in the form of a frequency-modulated sub-carrier wave transmitted in superposition with the luminance signal Y which represents the black-and-white image. These two mixed signals give a signal which is known as the composite videofrequency signal.
In the television receiver, this videofrequency signal is obtained by the detection of the amplitude modulation of the intermediate-frequency signal of which the image carrier wave oscillates at 32.7 MHz. This intermediate-frequency signal is itself obtained after conversion of the high-frequency signal picked up by the antenna.
The Secam system is a sequential system, i.e. a signal (R-Y) representative of red is transmitted for the duration of one line (64 μs), after which a signal (B-Y) representative of blue is transmitted for the duration of the other line. The quiescent frequencies FoR and FoB of the sub-carriers are different for red and for blue: FoR =4.406 MHz for red and FoB =4.250 MHz for blue.
In order to identify the presence of a red line or blue line at the receiving end, a signal at the frequency FoR for a red line or a signal at the frequency FoB for a blue line is transmitted at the beginning of each line for 4.8 μs by the television transmitting station.
At the receiving end, it is best for the signal representing red and the signal representing blue to be simultaneously present. To this end, the information of one line is memorised for restoration at the following line, whence the use of a delay line which introduces a delay equivalent to one 64 μs line.
Since the first treatment which the composite videofrequency signal undergoes is to extract from it the colour identification frequencies and then to direct them to two demodulation channels, one of which is delayed by the duration of one line so that two signals FoR and FoB are available at the same time, the second operation consists precisely in identifying these signals, i.e. in measuring their frequencies so that they may be suitably directed to the "red" channel and to the "blue" channel, respectively.
However, these various operations are controlled and "authorised" by a so-called "keeper" circuit which performs a control function if the composite video signal contains a sub-carrier signal corresponding to the Secam system. In the absence of this sub-carrier, i.e. if the transmission is in black-and-white or if it emanates from a station transmitting by a system other than the Secam system, the keeper circuit inhibits certain stages of the decoding circuit and the image received on the television receiver is formed solely by its luminance components Y, i.e. in black-and-white.
In short, therefore, the decoding of the chrominance signals R-Y and B-Y from the composite video signal in the Secam system comprises three operations:
demodulation of the colour sub-carrier which is delayed by 64 μs on one channel so that a signal R-Y- and a signal B-Y- are simultaneously available;
identification of the quiescent frequencies transmitted at the beginning of a line, these frequencies being representative of the colours,
and, at the same time, authorisation to treat these signals if the transmission corresponds to the Secam system.
Decoding circuits of the type in question exist and are known in various forms, their main disadvantage being a lack of stability. The use for example of tuned circuits necessitates a delicate manual adjustment of the external components which will not prevent instability of the demodulated output voltages in the event of changes in temperature. In addition, on account of their already outdated design, these known circuits are not designed to lend themselves readily to monolithic integration on a semiconductor crystal, nor can they be modified to include new components such as, for example, video delay lines of the CCD (charge coupled device) type which respresent significant advances.
In a SECAM color television transmission, R-Y and B-Y color-difference signals frequency modulate respective subcarriers (4.40625 MHz. and 4.250 MHz.) which are provided alternately on a line-by-line basis. For recovery of color-difference information from the modulated SECAM subcarriers, some form of FM detection is required.
One form of FM detector that is attractive for realization in integrated circuit form is the so-called quadrature detector, wherein a signal multiplier is supplied with two inputs, one input comprising the output of a limiter applied directly to the multiplier and the other input comprising the output of said limiter applied via a phase shifter exhibiting a 90° phase shift at the resting frequency of the FM signal. Low pass filtering of the products of multiplication of the respective signal inputs recovers the modulation information.
The present invention relates generally to luminance channel circuitry for a color television receiver, and particularly to novel circuits providing controllable delay for a received luminance component, which may advantageously be employed, for example, in the luminance channel of a dual standard PAL/SECAM receiver.
In the copending U.S. patent application Ser. No. 001,166, now U.S. Pat. No. 4,233,622, a dual-standard PAL/SECAM color TV receiver arrangement is disclosed wherein standard PAL decoder apparatus is utilized (a) to decode, in conventional manner, a PAL-encoded signal, when such a transmission is received, and (b) to decode a quasi-PAL signal, developed by a SECAM-PAL transcoder operating in the general manner described in U.K. Pat. No. 1,358,551, when a SECAM transmission is received. By utilizing a suitable identification system, such as described, for example, in the copending U.S. patent application Ser. No. 020,942, now U.S. Pat. No. 4,240,102, the receiver may be automatically switched, in dependence on the SECAM or PAL nature of the transmission received, between a SECAM-reception mode of operation, in which the PAL decoder apparatus receives as its input the output of the SECAM-PAL transcoder, and a PAL-reception mode of operation, in which the PAL decoder apparatus receives as its input signals which bypass the transcoder and pass instead through an appropriate PAL chroma bandpass filter.
When a receiver of the above-described type is operating in the PAL-reception mode, the PAL signal's chrominance information is subject to a given amount of delay during its processing (e.g., by such elements as the aforementioned PAL chroma bandpass filter), prior to its delivery in the form of color-difference signals to matrix circuitry of the PAL decoder for combination with luminance signals. When such a receiver is operating in the SECAM-reception mode, however, the SECAM signal's chrominance information is subject to an amount of delay during its processing (e.g., by such elements as the SECAM-PAL transcoder, and the SECAM "cloche" bandpass filter at the transcoder input) which is significantly greater than the delay suffered by the PAL signal's chrominance signal information during operation in the PAL-reception mode. One solution to this delay difference problem is to provide the receiver's luminance signal path to the decoder's matrix circuits with a compensating delay of a fixed, compromise value (e.g., lying midway between the respective delay magnitudes appropriate to PAL-reception delay compensation and to SECAM-reception delay compensation). However, in an illustrative receiver arrangement involving realization of the transcoder circuits in integrated circuit form, the delay difference is sufficiently large (e.g., approximately 500 nanoseconds) that reliance on a compensating delay of a fixed, compromise value provides unsatisfactory results.
In the Secam system, the colour information of a televised image is transmitted in the form of a frequency-modulated sub-carrier wave transmitted in superposition with the luminance signal Y which represents the black-and-white image. These two mixed signals give a signal which is known as the composite videofrequency signal.
In the television receiver, this videofrequency signal is obtained by the detection of the amplitude modulation of the intermediate-frequency signal of which the image carrier wave oscillates at 32.7 MHz. This intermediate-frequency signal is itself obtained after conversion of the high-frequency signal picked up by the antenna.
The Secam system is a sequential system, i.e. a signal (R-Y) representative of red is transmitted for the duration of one line (64 μs), after which a signal (B-Y) representative of blue is transmitted for the duration of the other line. The quiescent frequencies FoR and FoB of the sub-carriers are different for red and for blue: FoR =4.406 MHz for red and FoB =4.250 MHz for blue.
In order to identify the presence of a red line or blue line at the receiving end, a signal at the frequency FoR for a red line or a signal at the frequency FoB for a blue line is transmitted at the beginning of each line for 4.8 μs by the television transmitting station.
At the receiving end, it is best for the signal representing red and the signal representing blue to be simultaneously present. To this end, the information of one line is memorised for restoration at the following line, whence the use of a delay line which introduces a delay equivalent to one 64 μs line.
Since the first treatment which the composite videofrequency signal undergoes is to extract from it the colour identification frequencies and then to direct them to two demodulation channels, one of which is delayed by the duration of one line so that two signals FoR and FoB are available at the same time, the second operation consists precisely in identifying these signals, i.e. in measuring their frequencies so that they may be suitably directed to the "red" channel and to the "blue" channel, respectively.
However, these various operations are controlled and "authorised" by a so-called "keeper" circuit which performs a control function if the composite video signal contains a sub-carrier signal corresponding to the Secam system. In the absence of this sub-carrier, i.e. if the transmission is in black-and-white or if it emanates from a station transmitting by a system other than the Secam system, the keeper circuit inhibits certain stages of the decoding circuit and the image received on the television receiver is formed solely by its luminance components Y, i.e. in black-and-white.
In short, therefore, the decoding of the chrominance signals R-Y and B-Y from the composite video signal in the Secam system comprises three operations:
demodulation of the colour sub-carrier which is delayed by 64 μs on one channel so that a signal R-Y- and a signal B-Y- are simultaneously available;
identification of the quiescent frequencies transmitted at the beginning of a line, these frequencies being representative of the colours,
and, at the same time, authorisation to treat these signals if the transmission corresponds to the Secam system.
Siemens TDA4940 FM IF AMPLIFIER WITH PILOT TONE DECODING FOR TV; TDA4940 STEREO SOUND IF:
The invention relates to a television receiver incorporating a processing section for processing stereo/dual sound signals having a first sound carrier which is modulated by a first sound signal and a second sound carrier modulated by a second sound signal and also by a pilot signal which is modulated by a stereo-dual sound identifying signal, said processing section comprising a synchronous demodulator in which the pilot signal is demodulated and to which an output signal of a Phase-Locked Loop circuit is applied, the phase-locked loop circuit comprising a frequency-controllable oscillator and a phase discriminator which compares a signal derived from the oscillator with a reference signal which, as regards frequency and phase, is in a fixed relationship to the pilot signal. Such a television receiver is obtained when the known integrated circuit TDA 4940 marketed by Siemens is used.
As is known, two frequency-modulated sound carriers are used, according to the German standard, for the transmission of stereo/dual sound television signals, the second, for instance weaker, sound carrier being frequency-modulated by a pilot carrier which, in the case of stereo or dual sound transmission, is amplitude-modulated by an identifying signal which characterizes the stereo or dual-sound transmission mode and which is required in the receiver to enable the required switching actions to be effected automatically. In a television receiver comprising the prior art circuit, the identifying signal is obtained in that the modulated pilot carrier is multiplied by the output signal of a PLL circuit whose oscillator oscillates at a frequency equal to 28-times the line frequency and whose frequency is controlled by a phase discriminator which compares the frequency-divided oscillator signal with the line frequency.
The fact that, in accordance with the relevant German standard, the line frequency is in a fixed frequency and phase-relationship to the pilot carrier frequency is utilized, and the pilot carrier frequency is precisely 3.5-times the line frequency. As a result thereof, a signal which is phase-locked onto the pilot carrier can be recovered from the ocscillator signal by means of a 1:8-frequency divider. Then only the modulation product of the pilot carrier, that is to say one of the two identifying signals, is then only present at the output of the multiplier circuit.
An advantage of this circuit is that it has a high identifying signal reliability and sensitivity. A disadvantage is that it always requires the presence of a signal of the line frequency which is phase-locked onto the pilot carrier frequency. This signal is, however, not always available. Novel receiving and display concepts provide, for example, the possibility to connect the receiving section of a television receiver to a video recorder and the display section to a video disc player. However, for recording with the video recorder, the identifying signal must already have been demodulated. The line-frequency signal required therefore is however only available in the display section of the television receiver and is derived from the video disc, and consequently has no fixed phase relationship with the pilot carrier. The prior art circuit is not suitable for such a receiver concept.
To recover the pilot signal, from the antenna signal it is necessary for the carriers contained in the antenna signal and on which the sound signals are frequency modulated, to be first converted into a frequency corresponding to the frequency spacing of the two carriers from the picture carrier on which the video signal is modulated. For the German standard, two sound carriers are obtained in this manner at 5.5 and 5.742 MHz, respectively. In a known television receiver published in Funkschau 2, 1982, pages 76 to 79, these two sound carriers are separated from each other by two filters and demodulated by two demodulators, which produce the two sound signals and also the modulated pilot signal.
As in the dual-sound mode, the two sound signals are independent from each other as regards their content, a very high cross-talk attenuation, for instance better than 60 dB is necessary between the two sound channels. For that reason and as the frequency spacing of the upper side band of the sound carriers to the lower frequency of the lower sideband of the sound carriers having the higher frequency--relative to the sound carrier frequencies--is very small, the filter arrangement must be formed from very expensive high-selection filters. For that purpose, the known arrangement utilizes ceramic filters. Also the FM-demodulators require resonant circuits which, in the known receiver, are also ceramic filters. All the filters and resonant circuits must be balanced. Consequently, the processing section for processing the dual-sound stereo signals is very expensive.
A further disadvantage is that with such a receiver, only signals in accordance with the German standard can be received. If signals in accordance with a different standard, that is to say with an other frequency of the sound carrier or a different frequency spacing between the carriers for the picture and the sound information, must be processed, additional filter, resonant circuits, etc. are required.
Siemens TDA4941 TV Stereo Matrix:
PHILIPS TDA1524A Stereo-tone/volume control circuitGENERAL DESCRIPTION The device is designed as an active stereo-tone/volume control for car radios, TV receivers and mains-fed equipment. It includes functions for bass and treble control, volume control with built-in contour (can be switched off) and balance. All these functions can be controlled by d.c. voltages or by single linear potentiometers. Features · Few external components necessary · Low noise due to internal gain · Bass emphasis can be increased by a double-pole low-pass filter · Wide power supply voltage range.
Various systems and apparatus have been proposed for the transmission of stereophonic sound together with a conventional television picture transmission. These systems normally utilize the radio broadcasting stereophonic transmission techniques discussed above but with, in most cases, different subcarrier frequencies selected for their compatibility with the transmitted video signal. One such prior art system is disclosed in U.S. Pat. No. 4,048,654 to Wegner. This patent discloses a transmission system in which a composite baseband signal identical to that employed in FM stereophonic radio broadcasting is employed to frequency modulate the main sound carrier of a television transmission signal. Thus, the proposed composite baseband signal includes an (L+R) main channel component, an amplitude modulated double-sideband suppressed-carrier 38 KHz subcarrier (L-R) component and a 19 KHz pilot component. In another embodiment, the use of a subcarrier signal having a frequency (fH) characterizing the transmitted video signal is proposed in lieu of the 38 KHz (L-R) channel subcarrier to reduce interference from the video component of the television signal.
Another system, which was proposed in U.S. Pat. No. 3,099,707 to R. B. Dome, also employed the conventional stereophonic radio broadcasting system but with an (L-R) channel subcarrier equal to 1.5fH and a pilot signal equal to 2.5fH. These frequencies were selected to minimize the effect of the video components of the television signal appearing in the recovered sidebands of the (L-R) channel signal.
U.S. Pat. No. 3,046,329 to Reesor discloses yet another similar system in which the composite baseband signal used to frequency modulate the main sound carrier includes only the main channel (L+R) component and the upper sidebands of the (L-R) channel signal amplitude modulated on a subcarrier having a frequency of 2fH. Other prior art system for stereophonic television sound transmission have proposed the use of frequency modulated subcarriers for the (L-R) stereo channel typically centered at 2fH, although a center frequency of 1.5fH has also been proposed.
As previously mentioned, in addition to transmitting stereophonic sound components on the main aural carrier of a transmitted television signal, it is also desirable to transmit additional information thereby more completely exercising the available audio bandwidth within a television channel. For example, the transmission of a second audio program ("SAP") signal would enable a viewer to selectively operate a television receiver for reproducing the audio signals associated with the transmitted stereophonic information, or alternatively, the audio signals associated with the transmitted second audio program which may comprise, e.g., a foreign language version of the television program.
One prior art proposal for providing a second language capability in connection with a transmitted television signal is disclosed in previously mentioned U.S. Pat. No. 4,048,654 to Wegner in which the two channels of a stereophonic-like signal are employed. In particular, the (L+R) main channel signal is used to transmit a first language audio signal and the (L-R) stereo channel signal is used to transmit a second language audio signal. U.S. Pat. No. 3,221,098 to Feldman discloses a transmission system allowing for the simultaneous broadcast of a single television program having up to four or more different language soundtracks by forming a composite baseband signal consisting of four or more different subcarrier signals each amplitude modulated with a different language audio signal, the composite baseband signal being used to frequency modulate the main RF audio carrier. Yet another proposed second language system uses a frequency modulated subcarrier baseband signal centered at 2fH for both stereophonic sound transmission and for second language transmission. A pilot signal, modulated with one of two different frequencies, is used to indicate which service is being broadcast.
BLAUPUNKT MONTANA IP 32 STEREO VT COLOR (7 664 880) CHASSIS FM 100-20 CKVS Television receiver including a teletext decoder circuit :
PHILIPS SAA5051, TELETEXT CHARACTER GENERATOR
(GERMANY)
The SAA5051 is an MOS N-channel integrated circuit which provides the video drive signals to the
television necessary to produce the teletext/v iewdata display.
The SAA5051 is a 28 pin device which incorporates a fast access character generator ROM (4.3 k bits),
the logic decoding for all the teletext control characters and decoding for some of the remote control
functions.
The circuit generates 96 alphanumeric and 64 graphic characters. In addition there are 32 control
characters which determine the nature of the display.
The SAA5051 is suitable for direct connection to the SAA5010, SAA5020 and SAA5040 integrated
circuits.
SPECIAL FEATURES
Flash oscillator
The circu it generates a 0.75 Hz signal with a 3:1 ON/OFF ratio to provide the flashing characterfacility.
Power-on-reset
When the supply voltage is switched on, the character generator will reset to TV, conceal and not
superimpose modes.Character rounding
The character rounding function is different for the small and double height characters. In both cases
the ROM is accessed twice during the character period of 1 I1S. The dot information of two rows is
then compared to detect the presence of any diagonal in the character matrix and to determine the
positioning of the character rounding half dots.
For small characters rounding is always referenced in the same direction (i.e. row before in even fields
and row after in odd fields as determined by the CRS signal).
For double height characters rounding is always referenced alternately up and down changing every·
line using an internally generated signal. (The CRS signal is '0' for the odd field and '1' for the even
field of an interlaced TV picture.)
Graphics decoder
The 64 graphics characters are decoded directly from the character data inputs and they appear on a
2 x 3 matrix.
The Mullard / philips SAA5050/51 is a character generator chip for implementing the Teletext character set.
Printed circuit board used in a Philips Viewdata unit, featuring a SAA5050/51 character generator.
The SAA5050/51 was used in teletext-equipped television sets, viewdata terminals, and microcomputers, most notably on computers like the Philips P2000 (1980), Acorn System 2 (1980), BBC Micro (1982),
This chip was also manufactured by Mullard for Philips.
Operation
The chip generated appropriate video output for a 7-bit input character code representing the current character on the text line, while keeping track of the effect of any of the various control characters defined by the teletext standard that had previously occurred in that text line, which could be used to change the foreground and background colour, switch to or from the alternate block graphics character set, or various other effects.
Level 1 teletext block characters and colours
Full-screen resolution generated by the SAA5050/51 was 480 × 500 pixels, corresponding to 40 × 25 characters. Each character position therefore corresponded to a 12 × 20 pixel space. Internally each character shape was defined on a 5 × 9 pixel grid that was loosely based on the Signetics 2513 character ROM chip. This was then interpolated by smoothing diagonals to give a 10×18 pixel character, with a characteristically angular shape, surrounded to the top and to the left by two pixels of blank space. This gave a particularly stable and flicker-free arrangement on interlaced displays.
The alternate set of 2 × 3 block graphic characters were created on the same 12 × 20 pixel grid, so that the top two blocks were each 6 × 6 pixels, the middle two blocks each 6×8 pixels, and the bottom two blocks again 6 × 6 pixels (or two fewer in each direction, if the "separated graphics" control character had been sent).
Compared to other alternative chips, the SAA5050/51 implemented the original World System Teletext teletext standard (Level 1), which had no provision to set black for the foreground text colour. Some alternative chips at the time did allow this, as became formalized in the 1981 CEPT videotex standard.
In addition to the UK version, several variants of the chip existed with slightly different character sets for particular localizations and/or languages. These had part numbers SAA5051 (German),[6] SAA5052 (Swedish),,
SAA5053 (Italian), SAA5054 (Belgian), SAA5055 (U.S. ASCII), SAA5056 (Hebrew) and SAA5057 (Cyrillic).
The SAA5050/51 was later superseded by the SAA5243 CCT chip, integrating a similar teletext character generator with all previously separately implemented functions such as decoding, timing and video generation. It was controlled through I2C.
PHILIPS SAA5030,TELETEXT VIDEO PROCESSOR
The SAA5030 is a monlithic bipolar integrated circuit used for teletext video processing. It is one of a
package of four circuits to be used in teletext TV data systems. The SAA5030 extracts data and data
clock information from the television composite video signal and feeds this to the Acquisition and
Control circuit SAA5040. A 6 MHz crystal controlled phase locked oscillator is incorporated which
drives the Timing Chain circuit SAA5020. An adaptive sync separator is also provided which derives
line and field sync pulses from the input video in order to synchronise the timing chain.
PHILIPS SAA5020,TELETEXT TIMING CHAIN CIRCUIT
The SAA5020 is an MaS N-channel integrated circuit which performs the timing functions for a teletext
system.
The SAA5020 is a 24-lead device which provides the necessary timing signals to the teletext page memory
and to the Character Generator (SAA5050). It works in conjunction with the Video Processor Circuit
(SAA5030) and the Teletext Acquisition and Control Circuit (SAA5040). The operation of the SAA5020
maiQtains the synchronisation between the teletext system and the incoming video signal.
PHILIPS SAA5041,TELETEXT ACQUISITION AND CONTROL CIRCUIT
The SAA5041 is an MOS N-channel integrated circuit which performs the control, data acquisition and
data routing functions of the teletext system.
The SAA5041 is a 28-lead device which receives serial teletext data from the SAA5030 video processor
and data from the remote control system e.g. SAA5010. The SAA5041 selects the required page
information and feeds it in parallel form to the teletext page memory.
The SAA5041 works in conjunction with the SAA5020 Timing Chain and the SAA5050 or SAA5052
Character Generator. It is similar to the SAA5040 but provides German on-screen displays and has a
different set of remote control commands.
The circuit is designed in accordance with the September 1976 Broadcast Teletext specification
published by BBC/IBA/BREMA.
The circuit consists of two main sections.
a)Data Acquisition
The basic input to this section is the serial teletext data 'stream (F7 Data) from the Video
Processor Circuit SAA5030. This is clocked by a 6.9375 MHz clock also from the SAA5030.
The incoming data stream is processed and sorted So that the page of data selected by the user
is written as 7 bit parallel words into the system memory. Hamming and parity checks are
performed on the incoming data to reduce errors. Provision is also made to process the control
bits in the page header.
b)Control Section
The basic input to this section is the 7 bit serial data from the Remote Control Decoder
(e.g. SAB3012 or SAA5010). This is clocked by the 0 LIM signal.
The remote control commands are decoded and the controlled functions· are stored.
See Table 1 for full details of the remote control commands used in the SAA5041. The control
section can also write data into the page memory independently of the data acquisition section.
This gives an on screen display of certain user-selected functions, e.g. page number and programme
name.
The data and address outputs to the system memory are set to high impedance state if certain
remote control commands are received (e.g. Viewdata mode). This is to allow another circuit to
access the memory using the same address and data lines. The address lines are also high impedance
while the SAA\5041 Is not writing into the memory.
In
a teletext decoder circuit the character generator supplies picture
elements at a rate of nominally approximately 6 MHz under the control of
display pulses occurring at the same rate. These display pulses are
derived from reference clock pulses which occur at a rate which is not a
rational multiple of 6 MHz. The character generator comprises a
generator circuit which receives the reference clock pulses and selects,
from each series of N reference clock pulses, as many pulses as
correspond to the number of horizontal picture elements constituting a
character, while the time interval of N reference clock pulses
corresponds to the desired width of the characters to be displayed. The
character generator supplies picture elements of distinct length,
while the length of a picture element is dependent on the ordinal
number of this picture element in the character.
1.
A receiver for television signal s including a teletext decoder
circuit for decoding teletext signals constituted by character codes
which are transmitted in the television signal, and comprising:
a video input circuit receiving the television signal and converting it into a serial data flow;
an
acquisition circuit for receiving the serial data flow supplied by
the video input circuit and selecting that part therefrom which
corresponds to the teletext page described by the viewer;
a character generator comprising:
a
memory medium addressed by the character codes which together
represent the teletext page desired by the user and which in response to
each character code successively supply m2 series of m1
simultaneously occurring character picture element codes each
indicating wether a corresponding picture element of the character must
be displayed in the foreground colour or in the background colour;
a generator circuit receiving a series of reference clock pulses and deriving display clock pulses therefrom;
a converter circuit receiving each series of m1 simultaneously occurring character picture element codes as well as the display clock pulses for supplying the m1 character picture element codes of a series one after the other and at the display clock pulse rate;
a
display control circuit receiving the serial character picture
element codes and converting each into an R, a G and a B signal for the
relevant picture element of the character to be displayed;
characterized in that
the
generator circuit is adapted to partition the series of reference
clock pulses applied thereto into groups of N reference clock pulses
each, in which N reference clock pulse periods correspond to the desired
width of a character to be displayed, and to select from each such
group m1 clock pulse to function as display clock pulses;
the
converter circuit is adapted to supply each character picture element
code during a period which is dependent on the ordinal number of the
character picture element code in the series of m1 character picture element codes.
2. A character generator for use in a receiver teletext claim 1, comprising:
a memory medium which is addressable by character codes and successively applies m2 series of m1
simultaneously occurring character picture element codes in response
to a character code applied as an address thereto, each character
picture element code indicating whether a corresponding picture element
of the character must be displayed in the foreground colour or in the
background colour;
a generator circuit receiving a series of reference clock pulses and deriving display clock pulses therefrom;
a converter circuit receiving each series of m1 simultaneously occurring character picture element codes and the display clock pulses for supplying the m1 character picture element codes of the series one after the other at the display clock pulse rate;
a
display control circuit receiving the serial character picture
element codes and converting each into an R, a G and a B signal for the
relevant picture element of the character to be displayed;
characterized in that
the generator circuit is adapted to
partition the series of reference clock pulses applied thereto into
groups of N reference clock pulses each, in which N reference clock
pulse periods correspond to the desired width of a character to be
displayed, and to select from each such group m1 clock pulses to function as display clock pulses
the
converter circuit is adapted to supply each character picture element
code during a period which is dependent on the ordinal number of the
character picture element code in the series of m1 character picture element codes.
BACKGROUND OF THE INVENTION 1. Field of the Invention
The invention generally relates to receivers for television signals and more particularly to receivers including teletext decoders for use in a teletext transmission system.
2. Description of the Prior Art
As is generally known, in a teletext transmission system, a number of pages is transmitted from a transmitter to the receiver in a predetermined cyclic sequence. Such a page comprises a plurality of lines and each line comprises a plurality of alphanumerical characters. A character code is assigned to each of these characters and all character codes are transmitted in those (or a number of those) television lines which are not used for the transmission of video signals. These television lines are usually referred to as data lines.
Nowadays the teletext transmission system is based on the standard known as "World System Teletext", abbreviates WST. According to this standard each page has 24 lines and each line comprises 40 characters. Furthermore each data line comprises, inter alia, a line number (in a binary form) and the 40 character codes of the 40 characters of that line.
A receiver which is suitable for use in such a teletext transmission system includes a teletext decoder enabling a user to select a predetermined page for display on a screen. As is indicated in, for example, Reference 1, a teletext decoder comprises, inter alia, a video input circuit (VIP) which receives the received television signal and converts it into a serial data flow. This flow is subsequently applied to an acquisition circuit which selects those data which are required for building up the page desired by the user. The 40 character codes of each teletext line are stored in a page memory which at a given moment thus comprises all character codes of the desired page. These character codes are subsequently applied one after the other and line by line to a character generator which supplies such output signals that the said characters become visible when signals are applied to a display.
For the purpose of display each character is considered as a matrix of m 1 ×m 2 picture elements which are displayed row by row on the screen. Each picture element corresponds to a line section having a predetermined length (measured with respect to time); for example, qμsec. Since each line of a page comprises 40 characters and each character has a width of m 1 qμsec, each line has a length of 40 m 1 μsec. In practice a length of approximately 36 to 44 μsec appears to be a good choice. In the teletext decoder described in Reference 1 line length of 40 μsec and a character width of 1 μsec at m 1 =6 have been chosen.
The central part of the character generator is constituted by a memory which is sub-divided into a number of submemories, for example, one for each character. Each sub-memory then comprises m 1 ×m 2 memory locations each corresponding to a picture element and the contents of each memory location define whether the relevant picture element must be displayed in the so-called foreground colour or in the so-called background colour. The contents of such a code memory location will be referred to as character picture element code. This memory is each time addressed by a character code and a row code. The character code selects the sub-memory and the row code selects the row of m 1 memory elements whose contents are desired. The memory thus supplies groups of m simultaneously occurring character picture element codes which are applied to a converter circuit. This converter circuit usually includes a buffer circuit for temporarily storing the m 1 substantially presented character picture element codes. It is controlled by display clock pulses occurring at a given rate and being supplied by a generator circuit. It also supplies the m 1 character picture element codes, which are stored in the buffer circuit, one after the other and at a rate of the display clock pulses. The serial character picture element codes thus obtained are applied to a display control circuit converting each character picture element code into an R, a G and a B signal value for the relevant picture element, which signal values are applied to the display device (for example, display tube).
The frequency f d at which the display clock pulses occur directly determines the length of a picture element and hence the character width. In the above-mentioned case in which m 1 =6 and in which a character width of 1 μsec is chosen, this means that f d =6 MHz. A change in the rate of the display clock pulses involve
s a
change in the length of a line of the page to be displayed (now 40
μsec). In practice a small deviation of, for example, not more than 5%
appears to be acceptable. For generating the display clock pulses the
generator circuit receives reference clock pulses. In the decoder
circuit described in Reference 1 these reference clock pulses are also
supplied at a rate of 6 MHz, more specifically by an oscillator
specially provided for this purpose. OBJECT AND SUMMARY OF THE INVENTION
A particular object of the invention is to provide a teletext decoder circuit which does not include a separate 6 MHz oscillator but in which for other reasons clock pulses, which are already present in the television receiver, can be used as reference clock pulses, which reference clock pulses generally do not occur at a rate which is a rational multiple of the rate at which the display clock pulses must occur.
According to the invention,
the generator circuit is adapted to partition the series of reference clock pulses applied thereto into groups of N reference clock pulses each, in which N clock pulse periods correspond to the desired width of a character to be displayed, and to select of each such group m 1 clockpulses to function as display clock pulses;
the converter circuit is adapted to supply each character picture element code during a period which is dependent on the ordinal number of the character picture element code in the series of m 1 character picture element codes.
The invention has resulted from research into teletext decoder circuits for use in the field of digital video signal processing in which a 13.5 MHz clock generator is provided for sampling the video signal. The 13.5 MHz clock pulses supplied by this clock generator are now used as reference clock pulses. The generator circuit partitions these reference clock pulses into groups of N clock pulses periods each. The width of such a group is equal to the desired character width. Since a character comprises rows of m 1 picture elements, m 1 reference clock pulses are selected from such a group which clock pulses are distributed over this group as regularly as possible. Since the mutual distance between the display clock pulses thus obtained is not constantly the same, further measures will have to be taken to prevent undesired gaps from occurring between successive picture elements when a character is displayed. Since the length of a picture element is determined by the period during which the converter circuit supplies a given character picture element code, this period has been rendered dependent on the ordinal number of the character picture element code in the series of m 1 character picture element codes.
REFERENCES
1. Computer-controlled teletext, J. R. Kinghorn; Electronic Components and Applications, Vol. 6, No. 1, 1984, pages 15-29.
2. Video and associated systems, Bipolar, MOS; Types MAB 8031 AH to TDA 1521: Philips' Data Handbook, Integrated circuits, Book ICO2a 1986, pages 374,375.
3. Bipolar IC's for video equipment; Philips' Data Handbook, Integrated Circuits Part 2, January 1983.
4. IC' for digital systems in radio, audio and video equipment, Philips' Data Handbook, Integrated Circuits Part 3, September 1982.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 shows the general structure of a television receiver including a teletext decoder circuit;
FIG. 2 shows different matrices of picture elements constituting a character;
FIG. 3 shows diagrammatically the general structure of a character generator;
FIG. 4 shows an embodiment of a converter circuit and a generator circuit for use in the character generator shown in FIG. 3, and
FIG. 5 shows some time diagrams to explain its operation;
FIG. 6 shows another embodiment of a converter circuit and a generator circuit for use in the character generator shown in FIG. 3, and
FIG. 7 shows some time diagrams to explain its operation;
FIG. 8 shows a modification of the converter circuit shown in FIG. 6, adapted to round the characters.
EXPLANATION OF THE INVENTION
General structure of a TV receiver
FIG. 1 shows diagra
mmatically
the general structure of a colour television receiver. It has an
antenna input 1 connected to an antenna 2 receiving a television signal
modulated on a high-frequency carrier, which signal is processed in a
plurality of processing circuits. More particularly, it is applied to
a tuning circuit 23 (tuner or channel selector). This circuit
receives a band selection voltage V B in order to enable
the receiver to be tuned to a frequency within one of the frequency
bands VHF1, VHF2, UHF, etc. The tuning circuit also receives a tuning
voltage V T with which the receiver is tuned to the desired frequency within the selected frequency band. This tuning circuit 3 supplies an oscillator signal having a frequency of f OSC on the one hand and an intermediate frequency video signal IF on the other hand. The latter signal is applied to an intermediate frequency amplification and demodulation circuit 4 supplying a baseband composite video signal CVBS. The Philips IC TDA 2540 described in Reference 3 can be used for this circuit 4.
The signal CVBS thus obtained is also applied to a colour decoder circuit 5. this circuit supplies the three primary colour signals R', G' and B' which in their turn are applied via an amplifier circuit 6 to a display device 7 in the form of a display tube for the display of broadcasts on a display screen 8. In the colour decoder circuit 5 colour saturation, contrast and brightness are influenced by means of control signals ANL. The circuit also receives an additional set of primary colour signals R, G and B and a switching signal BLK (blanking) with which the primary colour signals R', G' and B' can be replaced by the signals R, G and B of the additional set of primary colour signals. A Philips IC of the TDA 356X family described in Reference 3 can be used for this circuit 5.
The video signal CVBS is also applied to a teletext decoder circuit 9. This circuit comprises a video input circuit 91 which receives the video signal CVBS and converts it into a serial data flow. This flow is applied to a circuit 92 which will be referred to as teletext acquisition and control circuit (abbreviated TAC circuit). This circuit selects that part of the data applied thereto which corresponds to the teletext page desired by the viewer. The character codes defined by these data are stored in a memory 93 which is generally referred to as page memory and are applied from this memory to a character generator 94 supplying an R, a G and a B signal for each picture element of the screen 8. It is to be noted that this character generator 94 also supplies the switching signal BLK in this embodiment. As is shown in the Figure, the teletext acquisition and control circuit 92, the page memory 93 and the character generator 94 are controlled by a control circuit 95 which receives reference clock pulses with a frequency f o from a reference clock oscillator 10. The control circuit 95 has such a structure that it supplies the same reference clock pulses from its output 951 with a phase which may be slightly shifted with respect to the reference clock pulses supplied by the clock pulse oscillator 10 itself. The reference clock pulses occurring at this output 951 will be denoted by TR.
The
Philips IC SAA 5030 may be used as video input circuits 91, the
Philips IC SAA 5040 may be used as teletext acquisition and control
circuit, a 1K8 RAM may be used as page memory, a modified version of
the Philips IC SAA 5050 may be used as character generator 94 and a
modified version of the Philips IC SAA 5020 may be used as control
circuit 95, the obvious modification being a result of the fact that
this IC is originally intended to receive reference clock pulses at a
rate of 6 MHz for which 13.5 MHz has now been taken. The acquisition and control circuit 92 is also connected to a bus system 11. A control circuit 12 in the form of a microcomputer, an interface circuit 13 and a non-volatile memory medium 14 are also connected to this system. The interface circuit 13 supplies the said band selection voltage V B , the tuning voltage V T and the control signals ANL for controlling the analog functions of contrast, brightness and colour saturation. It receives an oscillator signal at the frequency f' OSC which is derived by means of a frequency divider 15, a dividing factor of which is 256, from the oscillator signal at the frequency f OSC which is supplied by the tuning circuit 3. Tuning circuit 3, frequency divider 15 and interface circuit 13 combined constitute a frequency synthesis circuit. The Philips IC SAB 3035 known under the name of CITAC (Computer Interface for Tuning and Analog Control) and described in Reference 4 can be used as interface circuit 13. A specimen from the MAB 84XX family, manufactured by Philips, can be used as a microcomputer.
The memory medium 14 is used, for example, for storing tuning data of a plurality of preselected transmitter stations (or programs). When such tuning data are applied to the interface circuit 13 under the control of the microcomputer 12, this circuit supplies a given band selection voltage V B and a given tuning voltage V T so that the receiver is tuned to the desired transmitter.
For operating this television receiver an operating system is provided in the form of a remote control system comprising a hand-held apparatus 16 and a local receiver 17. This receiver 17 has an output which is connected to an input (usually the "interrupt" input) of the microcomputer 12. It may be constituted by the Philips IC TDB 2033 described in Reference 4 and is then intended for receiving infrared signals which are transmitted by the hand-held apparatus 16.
The hand-held apparatus 16 comprises an operating panel 161 with a plurality of figure keys denoted by the FIGS. 0 to 9 inclusive, a colour saturation key SAT, a brightness key BRI, a volume key VOL, and a teletext key TXT. These keys are coupled to a transmitter circuit 162 for which, for example, the Philips IC SAA 3004, which has extensively been described in Reference 4, can be used. When a key is depressed, a code which is specific of that key is generated by the transmitter circuit 162, which code is transferred via an infrared carrier to the local receiver 17, demodulated in this receiver and subsequently presented to the microcomputer 12. This microcomputer thus receiv
es
operating instructions and activates, via the bus system 11, one of
the circuits connected thereto. It is to be noted that an operating
instruction may be a single instruction, that is to say, it is complete
after depressing only one key. It may also be multiple, that is to
say, it is not complete until two or more keys have been depressed.
This situation occurs, for example, when the receiver is operating in
the teletext mode. Operation of figure keys then only yields a
complete operating instruction when, for example, three figure keys
have been depressed. As is known, such a combination results in the
page number of the desired teletext page. The character generator
As already stated, a character is a matrix comprising m 2 rows of m 1 picture elements each. Each picture element corresponds to a line section of a predetermined length (measured with respect to time); for example, q/μsec. Such a matrix is indicated at A in FIG. 2 for m 1 =6 and m 2 =10. More particularly this is the matrix of a dummy character. The character for the letter A is indicated at B in the same FIG. 2. It is to be noted that the forty characters constituting a line of teletext page are contiguous to one another without any interspace. The sixth column of the matrix then ensures the required spacing between the successive letters and figures.
FIG. 3 shows diagrammatically the general structure of the character generator described in Reference 2 and adapted to supply a set of R, G and B signals for each picture element of the character. This character generator comprises a buffer 940 which receives the character codes from memory 93 (see FIG. 1). These character codes address a sub-memory in a memory medium 941, which sub-memory consists of m 1 ×m 2 memory elements each comprising a character picture element code. Each m 1 ×m 2 char
acter
picture element code corresponds to a picture element of the
character and defines, as already stated, whether the relevation
picture element must be displayed in the so-called foreground colour
or in the so-called background colour. Such a character picture
element code has the logic value "0" or "1". A "0" means that the
corresponding picture element must be displayed in the background
colour (for example, white). The "1" means that the corresponding
picture element must be displayed in the foreground colour (for
example, black or blue). At C in FIG. 2 there is indicated, the
contents of the sub-memory for the character shown at B in FIG. 2. The addressed sub-memory is read now by row under the control of a character row signal LOSE. More particularly, all first rows are read of the sub-memories of the forty characters of a teletext line, subsequently all second rows are read, then all third rows are read and so forth until finally all tenth rows are read.
The six character element codes of a row will hereinafter be referred to as CH(1), CH(2), . . . CH(6). They are made available in parallel by the memory medium 941 and are applied to a converter circuit 942 operating as a parallel-series converter. In addition to the six character picture element codes it receives display clock pulses DCL and applies these six character picture element codes one by one at the rate of the display clock pulses to a display control circuit 943 which converts each character picture element code into a set of R, G, B signals.
The display clock pulses DCL and the character row signal LOSE are supplied in known manner (see Reference 2, page 391) by a generator circuit 944 which receives the reference clock pulses TR from the control circuit 95 (see FIG. 1), which reference clock pulses have a rate f 0 . In the character generator described in Reference 2, page 391, f 0 is 6 MHz and the display clock pulses DCL occur at the same rate. The converter circuit thus supplies the separate character picture element codes at a rate of 6 MHz. The picture elements shown at A and B therefore have a length of 1/6 μsec each and a character thus has a width of 1 μsec.
When the rate of the reference clock pulses increases, the rate of the display clock pulses also increases and the character width decreases. Without changing the character width the above-described character generator can also be used without any essential changes if the rate of the reference clock pulses is an integral multiple of 6 MHz. In that case the desired display clock pulses can e derived from the reference clock pulses by means of a divider circuit with an integral dividing number. However, there is a complication if f 0 is not a rational multiple of 6 MHz, for example, if f 0 =13.5 MHz and each character nevertheless must have a width of substantially 1 μsec. Two generator circuits and a plurality of converter circuits suitable for use in the character generator shown in FIG. 3 and withstanding the above-mentioned complication will be described hereinafter.
FIG. 4 shows an embodiment of the generator circuit 944 and the converter circuit 942. The reference clock pulses TR are assumed to occur at a rate of 13.5 MHz. To derive the desired display clock pulses from these reference clock pulses, the generator circuit 944 comprises a modulo-N-counter circuit 9441 which receives the 13.5 MHz reference clock pulses TR indicated at A in FIG. 5. The quantity N is chosen to be such that N clock pulse periods of the reference clock pulses substantially correspond to the desired character width of, for example, 1 μsec. This is the case for N=14, which yields a character width of 1.04 μsec.
An encoding network 9442 comprising two output lines 9443 and 9444 is connected to this modulo-N-counter circuit 9441. This encoding netw
ork
9442 each time supplies a display clock pulse in response to the
first, the third, the sixth, the eighth, the eleventh and the
thirteenth reference clock pulse in a group of fourteen reference
clock pulses. More particularly the display clock pulse, which is
obtained each time in response to the first reference clock pulse of a
group, is applied to the output line 9443, whilst the other display
clock pulses are applied to the output line 9444. Thus, the pulse
series shown at B and C in FIG. 5 occur at these output lines 9443 and
9444, respectively. The converter circuit 942 is constituted by a shift register circuit 9420 comprising six shift register elements each being suitable for storing a character picture element code CH(.) which is supplied by the memory medium 941 (see FIG. 3). This shift register circuit 9420 has a load pulse input 9421 and a shift pulse input 9422. The load pulse input 9421 is connected to the output line 9443 of the encoding network 9442 and thus receives the display clock pulses indicated at B in FIG. 5. The shift pulse input 9422 is connected to the output line 9444 of the encoding network 9442 and thus receives the display clock pulses indicated at C in FIG. 5.
This converter circuit operates as follows. Whenever a display clock pulse occurs at the load pulse input 9421, the six character picture element codes CH(.) are loaded into the shift register circuit 9420. The first character picture element code CH(1) thereby becomes immediately available at the output. The contents of the shift register el
ements are shifted one position in the direction of the output by each display clock pulse at the shift pulse input 9422. Since the display clock pulses occur at mutually unequal distances, the time interval during which a character picture element code is available at the output of the shift register circuit is longer for the one character picture element code than for the other. This is shown in the time diagrams D of FIG. 5. More particularly the diagrams show for each character picture element code CH(.) during which reference clock pulse periods the code is available at the output of the shift register circuit. The result is that the picture elements from which the character is built up upon display also have unequal lengths as is indicated at D and E in FIG. 2.
The same character display is obtained by implementing the converter circuit 942 and the generator circuit 944 in the way shown in FIG. 6. The generator circuit 944 again comprises the modulo-N-counter circuit 9441 with N=14 which receives the 13.5 MHz reference clock pulses TR shown at A in FIG. 7. An encoding network 9445 is also connected to this counter circuit, which network now comprises six output lines 9446(.). This encoding network 9445 again supplies a display clock pulse in response to the first, the third, the sixth, the eighth, the eleventh and the thirteenth reference clock pulse of a group of fourteen reference clock pulses, which display clock pulses are applied to the respective output lines 9446(1), . . . , 9446(6). Thus, the pulse series indicated at B, C, D, E, F and G in FIG. 7 occur at these outputs.
The converter circuit 942 has six latches 9423(.) each adapted to store a character picture element code CH(.). The outputs of these latches are connected to inputs of respective AND gate circuits 9424(.). Their outputs are connected to inputs of an OR gate circuit 9425. The AND gate circuit is 9424(.) are controlled by the control signals S(1) to S(6), respectively, which are derived by means of a pulse widening circuit 9426 from the display clock pulses occurring at the output lines 9446(.) of the encoding network 9445 and which are also shown in FIG. 7. Such a control signal S(i) determines how long the character picture element code CH(i) is presented to the output of the OR gate circuit 9425 and hence determines the length of the different picture elements of the character on the display screen.
As is shown in FIG. 6, the pulse widening circuit 9426 may be constituted by a plurality of JK flip-flops 9426(.) which are connected to the output lines of the encoding network 944, in the manner shown in the Figure. It is to be noted that the function of the pulse widening circuit 9426 may also be included in the encoding network 9445. In that case this function may be realized in a different manner.
In the above-described embodiments of the converter circuit 942 and the generator circuit 944 the character generator supplies exactly contiguous picture elements on the display screen. This means that the one picture elements begins immediately after the previous picture element has ended. The result is that round and diagonal shapes become vague. It is therefore common practice to realize a rounding for such shapes. This rounding can be realized with the converter circuit shown in FIGS. 4 and 6
by ensuring that two consecutive picture elements partly overlap each
other. This is realized in the converter circuit shown in FIG. 4 by
means of a rounding circuit 9427 which receives the character picture
element codes occurring at the output of the shift register circuit
9420. This rounding circuit 9427 comprises an OR gate 9427(1) and a D
flip-flop 9427(2). The T input of this flip-flop receives the clock
pulses shown at E in FIG. 5, which pulses are derived from the
reference clock pulses TR by means of a delay circuit 9427(3). This
circuit has a delay time t 0 for which a value in the time
diagram indicated at E in FIG. 5 is chosen which corresponds to half a
clock pulse period of the reference cock pulses. The character
picture element codes supplied by the shift register circuit 9420 are
now applied directly and via the D flip-flop 9427(2) to the OR gate
which thereby supplies the six character picture element codes CH(.)
in the time intervals as indicated at F in FIG. 5. The result of this
measure for the display of the character with the letter A is shown at
F in FIG. 2. The same rounding effect can be realized by means of the converter circuit shown in FIG. 6, namely by providin
g it with a rounding circuit as well. This is shown in FIG. 8. In this FIG. 8 the elements corresponding to those in FIG. 6 h
ave
the same reference numerals. The converter circuit 942 shown in FIG. 8
differs from the circuit shown in FIG. 6 in that the said rounding
circuit denoted by the reference numeral 9428 is incorporated between
the pulse widening circuit 9426 and the AND gate circuits 9424(.). More
particularly this rounding circuit is a pluriform version of the
rounding circuit 9427 shown in FIG. 4 and is constituted by six D
flip-flops 9428(.) and six OR gates 9429(.). These OR gates receive the
respective control signals S(1) to S(6) directly and via the D
flip-flops. The T inputs of these D flip-flops again receive the version
of the reference clock pulses delayed over half a reference clock
pulse period by means of the delay circuit 94210. This rounding circuit
thus supplies the control signals S'(.) shown in FIG. 7. Philips Data Handbook, Electronic Components and Materials "Integrated Circuits: Part 3, Sep. 1982: ICs for Digital Systems in Radio, Audio, and Video Equipment: SAA5020 Series", pp. 1-10.
Philips Data Handbook, Electronic Components and Materials "Integrated Circuits: Book IC02a, 1986: Video and Associated Systems: Bipolar, MOS: Types MAB8031AH to TDA1521", pp. 374-375.
F. J. R. Kinghorn, "Computer Controlled Teletext"; Electronic Components and Applications; vol. 6, No. 1, 1984, pp. 15-29.
"World System Teletext Technical Specification", Revised Mar. 1985, pp. 1-10 and 38-41.
Philips Data Handbook, Electronic Components and Materials; "Integrated Circuits, Part 2: Jan. 1983: Bipola
r ICs for Video Equipment: TDA2540, TDA2540Q"; pp. 1-8. Philips Data Handbook, Electronic Components and Materials; "Integrated Circuits: Part 2: Jan. 1983: Bipolar ICs for Video Equipment: TDA 3562A"; pp. 1-16.
Philips Data Handbook, Electronic Components and Materials "Integrated Circuits: Part 3, Sep. 1982: IC's for Digital Systems in Radio, Audio, and Video Equipment: SAA3004"; pp. 1-10.
Philips Data Handbook, Electronic Components and Materials, "Integrated Circuits: Part 3, Sep. 1982: Ics for Digital Systems in Radio, Audio, and Video Equipment: SAB3035", pp. 1-4.
Philips Data Handbook, Electronic Components and Materials "Integrated Circuits: Part 3, Sep. 1982: ICs for Digital Systems in Radio, Audio and Video Equipment: TDB2033", pp. 1-9.
BLAUPUNKT MONTANA IP 32 STEREO VT COLOR (7 664 880) CHASSIS FM 100-20 CKVS Teletext / Videotext Error correction circuit using character probability :
An error correction circuit in a television receiver for receiving, for example, Teletext information, Viewdata information or information of comparable systems. The codes representing symbol information received by the receiver are classified into one out of two or more classes in dependence on the frequency of their occurrence, this classification being an indication of the extent to which it is probable that a received code is correctly received.
In
FIG. 1, a picture text television receiver has a receiving section,
audio and video amplifiers 4 and 9 and a picture tube 10, 11. A text
decoder 21 receives symbol information which is stored in a store 25
for display. An error detector circuit 40 including a comparison
circuit 43 and two parity circuits 41 and 42, and checks for parity
between newly received and already stored symbol information. A
reliability circuit 60 is also included.1. An error correction circuit for a receiving device for receiving digitally transmitted symbol information, the transmission of this information being repeated one or more times, the receiving device having a decoding circuit for decoding the received information, an information store coupled to said decoding circuit for storing the information, a circuit for generating synchronizing signals and a video converter circuit coupled to said information store and said generating circuit for converting information and synchronizing signals into a composite video signal for application to a standard television receiver, a symbol address in the information store corresponding with a symbol location on a television picture screen, a symbol location being a portion of a text line which is displayed with a number of video lines greater than one, the error correction circuit being coupled to said decoding circuit and said information store and including means coupled between said decoding circuit and said information store for checking newly received symbol information against symbol information stored in the information store for the corresponding symbol location, a write-switch having one input coupled to said decoding circuit and an output coupled to said information store, and a write-setting circuit, coupled to another input of said write-switch, which determines whether the newly received information is written or not written into the information store, said write-setting circit having an input coupled to said checking means whereby the results of said checking are a factor in the setting of said write-switch by said write-setting circuit, characterized in that the error correction circuit further comprises a classification circuit coupled to the output of said decoding circuit for classifying a newly received and decoded symbol in one of at least two classes on the basis of the probability of occurrence of the newly received symbol, the input of the classification circuit being coupled to another input of the write-setting circuit. 2. An error correction circuit for a receiving device as claimed in claim 1, characterized in that the write-setting circuit includes a reliability circuit and the information store comprises an additional storage element for each symbol address in the information store for storing a reliability bit associated with that symbol address, inputs of the reliability circuit being coupled to the classification circuit and to the information store for accessing the additional storage elements, for determining, from the additi
onal
storage element corresponding with the symbol address position of
newly received symbol information, a new reliability bit, an output of
the reliability circuit being coupled back to the information store
for writing this new reliability bit into the corresponding additional
storage element when the reliability bit for this symbol address
changes its value. 3. An error
correction circuit for a receiving device as claimed in claim 2,
characterized in that the checking means comprises a comparison circuit
for bit-wise comparing a newly received and decoded symbol with a
symbol read from an address of the information store, this address
corresponding with the symbol location, a comparison output of the
comparison circuit being coupled to a further input of the reliability
circuit. 4. An error correction
circuit for a receiving device as claimed in any one of the preceding
claims, characterized in that the classification circuit comprises a
parity circuit for classifying newly received symbols for respective
particular symbol locations into one of two classes which correspond to
an even and an odd parity respectively, of the newly received
information, and for classifying symbol information already stored in
the corresponding symbol addresses in the information store.
5. An error correction circuit for a
receiving device as claimed in claim 2, characterized in that the
reliability circuit comprises a reliability flipflop and a reliability
read circuit for this flipflop, an output of which also constitutes
the output of the reliability circuit.
6. An error correction circuit for a receiving device as claimed
in claim 1, characterized in that the error correction circuit
comprises a second classification circuit, coupled between said other
classification circuit and said write-setting circuit and having
inputs coupled to said information store, for classifying a symbol
read from the information store.
7. An error correction circuit for a receiving device as claimed in
claim 1 characterized in that the information store comprises, for
each symbol address in the information store, at least one further
storage element for storing the classification associated with the
symbol for that symbol address.
The invention relates to an error correction circuit of a type suitable for a receiving device for receiving digitally transmitted symbol information (picture and/or text), the transmission of this information being repeated one or more times, the receiving device comprising a deconding circuit for decoding the received information, an information store for storing the information, a circuit for generating synchronizing signals and a video converter circuit for converting information and synchronizing signals for applying a composite video signal to a standard television receiver, a symbol address in the information store corresponding with a symbol location on a television picture screen, a symbol location being a portion of a text line which is displayed with a number of videolines greater than one, the error correction circuit comprising means for checking newly received symbol information against symbol information stored in the information store for the corresponding symbol location, together with a write-switch having a write-setting circuit which determines whether the newly received information is written or not written into the information store, the position of the switch being determined on the basis of the result of said checking.
Error correction circuits of the above type are used in auxiliary apparatus for the reception of Teletext transmissions or comparable transmissions, these auxiliary apparatus being connected to a standard television receiver either by applying video signals to a so-called video input, or by applying these video signals, modulated on a carrier, to an aerial input of the television set. There are already television receivers with a built-in Teletext receiver already including an error correction circuit of the above-mentioned type.
The present Teletext system as it is already used rather widely in the UK, is based on an 8-bit symbol teletext code having 7 information bits and 1 parity bit; this parity bit is chosen so that each 8-bit symbol in the code has a so-called "odd" parity, that is to say there is an odd number of ones in a symbol, and, consequently, also an odd number of zeros. A display on the television picture screen comprises a "page" consisting of a number of rows (e.g. 24) of symbols.
Only symbols with the "odd" parity are stored in the information store. Each symbol represents either an alpha-numeric or a graphics character for display on the picture screen, or a control symbol.
If, in a subsequent transmission cycle for the same symbol location of the same page, a faulty symbol is detected, then, assuming that only a single error occurs within a symbol, this faulty symbol will have an even parity, that is to say a "one" changed into a "zero", or vice versa, as the result of the error. In this case the information store is not written into and the old information is retained in the relevant symbol address.
As the probability is very great that this old information is correct, the parity check does not only furnish an error detection, but also an error correction, partly because of the fact that some knowledge has already been gained from the previous history. Of course, this does not hold for the first transmission cycle. Should an "even" parity be found in a 8-bit symbol in the first transmission cycle, a space ("blank") is generally recorded in the relevant symbol address and, consequently, displayed as a space. The easiest way to do this is by filling the entire information store with space symbols when a new Teletext page is requested, so that also in the first cycle no information need be written into the information store on receipt of a symbol having an "even" parity.
For a poor transmission condition an error probability of 0.01 is assumed, that is to say one symbol out of a hundred symbols is received incorrectly. In a complete page having 960 Teletext symbol locations, (i.e. up to 24 rows of up to 40 symbols per row) the displayed page then shows, after the first cycle, 9 to 10 erroneous spaces on average. In the present system substantially all these erroneous spaces are likely to have been corrected in the second cycle.
When the receiving conditions are better, this situation is already correspondingly more favourable in the first cycle. Even in the poorest receiving conditions, it appears that the number of double errors is so small that they may be neglected. Double errors therefore are hardly ever taken into consideration hereafter. It will be apparent that in this system each symbol has a certain degree of redundancy in the form of the parity bit, but this is off-set by the drawback that the 8-bit code, which has 256 (=2 8 ) combinations, is utilized for only 50% of this capacity, i.e. only for the 128 symbols having "odd" parity.
Although, for the U.K. itself, such a code has a sufficient capacity to contain all desired symbols for control, graphics elements, letters, figures, punctuation marks, etc. as required for Teletext and also, for example, for Viewdata, it is not possible to allot a specific symbol to all of the special characters occurring in various other languages.
Several European la
nguages,
in so far they are written in latin characters, have all sorts of
"extra" characters, for example Umlaut letters, accent letters, etc.
When all these extra characters are totalled, including Icelandic,
Maltese and Turkish, then it appears that a total of approximately 220
symbols is required, namely the 128 known symbols plus further
symbols for these "extra" characters. Several solutions have been proposed to solve this, but so far none of these have been satisfactory as they are either very cumbersome or allow only one language within one page, so that it is impossible or very difficult e.g. to quote foreign names in a page of text.
Alternatively it has been proposed--and this is of course very obvious--to use the entire 8-bit code for symbols. As the redundancy in the code has now been reduced to zero, no correction can be effected in the second cycle. If two codes for one symbol location differ from one another in different transmission cycles, it is theoretically impossible to decide with certainty which one of the two codes is correct. An additional information store is required to enable a comparison between a newly received symbol in the third cycle and a symbol from the second and the first cycles, and to take the frequently used majority decision thereafter. This is possible, but three reading cycles are necessary before the number of errors is reduced to an acceptable level. As each transmission cycle of a completely full magazine (i.e. a plurality of pages) takes approximately 25 seconds, the correct text is not known until after approximately 75 seconds.
As the present system displays the text correctly after approximately 50 seconds already, such a solution would mean an increase in the so-called access time.
If a new parity bit were added to the 8-bit code, each symbol would require 8+1=9 bits so that it is no longer possible, as is done in the present system, to accommodate the s
ymbols for one text line of 40
characters in one video line, whereas on the other hand the average
transmission rate decreases if more video lines are needed for the
information transmission. This solution is generally considered to be
unacceptable, also because the compatibility with existing receivers
would be fully lost. 
Although any language to be displayed can be considered to contain redundancy both as regards text and graphics, so that a viewer may "overlook" many errors, in the sense that there is still an intelligible display, this does not offer a satisfactory solution.
SUMMARY OF THE INVENTION
It is the object of the invention to provide an error correction circuit of the type referred to for a receiving device for Teletext and comparable systems, which offers such a solution for the problem outlined above that also for an 8-bit code without a parity bit substantially all errors, if any, can be corrected in the second transmission cycle which is received.
According to the invention an error correction circuit of the type referred to is characterized in that it comprises at least one classification circuit for classifying a newly received and decoded symbol in one of at least two classes on the basis of the probability of occurrence of the newly received symbol, an output of the classification circuit being coupled to an input of the write-setting circuit.
The classification circuit utilizes the hitherto unrecognized fact that the "language" used for the Teletext system and for associated systems comprises a third form of redundancy, namely the frequency with which the different symbols occur in any random text.
From counts performed on longer texts in several languages, including texts that quote words or names from other languages, it is found that, on average, these texts did not contain more than approximately 5% "extra" symbols, in spite of the fact that the extra symbols constitute approximately 50% of the different code combinations. The remaining 95% are symbols from the original 50% of the different code combinations, that is to say control, graphics and text symbols which were already used in the existing system. For simplicity, these latter symbols are hereinafter denoted A-symbols, and the "extra" symbols are denoted B-symbols.
If now an A-symbol is received in the first cycle and a B-symbol in the second cycle, or vice versa, it is already possible to decide with a high degree of certainty which of the two is correct.
Let us assume that an identified A-symbol is transmitted from the transmitter end for the same symbol location in those first and second cycles, whereas the receiver receives an A-symbol in the first cycle and a B-symbol in the second cycle.
It can be seen that some form of A-symbol is obtained in the receiver when either a real A-symbol is properly received or a real B-symbol is erroneously received. Assuming there is an error probability of 0.01, the probability that the first-mentioned situation occurs is 0.95×0.99=0.9405 and the probability that the second situation occurs is 0.05×0.01=0.0005 so that the probability that an A-symbol is received totals 0.941. A B-symbol results from a real B-symbol (0.05×0.99=0.0495) or a faulty A-symbol (0.95×0.01=0.0095), adding up to a total probability of 0.059. Of course 0.941+0.059=1.000, based on the assumption that double errors do not occur, so that any A-symbol A x will never be received as another A-symbol A y from the same class. The probability that a received A-symbol is correct is 0.9405/0.941=0.9995. The probability that a received B-symbol is correct is 0.0495/0.059=0.839.
For the above mentioned case, it is correctly assumed that the A-symbol in the first cycle is correct, and that the B-symbol in the second cycle is incorrect.
Consequently, there is an A-symbol in the information store in both cycles. In the second cycle the B-symbol must not be stored, and the A-symbol obtained from the first cycle must be retained.
Should a B-symbol be received first, then a B-symbol is written into the information store, (the probability that this B-symbol is correct is still 84%) but it is not retained in the second cycle, and the A-symbol received in the second cycle must now be recorded in the information store.
At the end of the second cycle it is seen that in this manner the then remaining error is less than one in approximately 5 full pages, as applied to the Teletext system. Such a number of errors is so small that apparently they are not noticed by a viewer.
When an A-symbol is received in the first cycle and in the second cycle or a B-symbol is received in both cycles then there is no doubt, after symbol sequences A, B or B, A there is little doubt, but the symbol stored in the information store must be
considered to be somewhat suspect. This also applies to each B-symbol
recorded in the first cycle, which may lead to a further improvement
when a decision is taken. Another advantageous embodiment of an error correction circuit according to the invention is characterized in that the error correction circuit comprises a reliability circuit and the information store comprises an additional storage element for each symbol address in the information store for storing a reliability bit associated with that symbol address, inputs of the reliability circuit being coupled to the classification circuit and to a read circuit for the additional storage elements, for determining from the additional storage element corresponding with the symbol address of newly received symbol information a new reliability bit, this new reliability bit being written at least into the corresponding additional storage element when the reliability bit for this symbol address changes its value.
When the transmitter successively transmits an A-symbol for a certain symbol and location and symbols ABA are successively received, then the A-symbol may be recorded as being "non-suspect" after the first cycle, indicated by an R (reliable) hereinafter. An R' after the second (A), the brackets indicating that the information is retained (not written into the information store) indicates the assumed non-reliability of this retained (A)-symbol, and an A and an R in the third cycle indicates the reliability of the correctly received A-symbol. The A-symbol in the information store is now again assumed to be reliable for this symbol sequence.
In like manner, when the transmitter transmits a B for a certain symbol location, and the symbols B, A, B, B are successively received, symbols and reliability states B. R', A.R', B. R' and B.R are recorded.
All this depends on the decision logic opted for.
It is assumed here that the possibility of an error for the same symbol location in two consecutive cycles is also extremely small; when the transmitter transmits symbols A, A, A, A in successive cycles, the probability that the receiver would receive, for example, symbols A, B, B, A is assumed to be zero. From practical experiments it was seen that this form of a double error can be fully neglected.
This improvement makes it of course necessary for reliability state R or R' to be retained together with the related symbol in the information store and that it must be revised every cycle, if necessary. Each symbol address now has 9 bits instead of 8 in the Teletext receiver memory. This has hardly any consequences for the price as a standard RAM having a capacity of 1kx9 can be used.
As is apparent from the foregoing examples, it can be advantageous to make different decisions in the case a symbol sequence B-A is formed after the first cycle or after a further cycle.
A further advantageous embodiment of an error correction circuit is characterized in that the error correction circuit comprises a counting circuit for counting information transmission cycles following a new request for (always) a full picture of the requested symbol information, a counting output of this counting circuit being coupled at least to another input of the reliability circuit, this counting output being, for example, also coupled to a further input of the write-setting circuit.
As seen earlier in the history of data transmission and information processing equipment, the need was felt also for Teletext and comparable systems, to realise the extension with new symbols by doubling the number of symbols identified by an n-bit code, in such a way that the original symbols retain as far as possible their existing bit combustion.
This results inter alia in that transmission in a new, extended, code are also displayed reasonably well by existing receivers. A receiver for the original symbols only allots the correct symbol to approximately 95% or more of the symbol locations in the display. A limited compatability is therefore still possible, and even a full compatibility if a normal "English" text is transmitted.
In the example considered herein all the original symbols remain the same, and all the "extra" symbols have even parity.
This symbol set is now under discussion as an international standardization proposal.
It will be apparent that in the last-mentioned case no intricate classification circuit is required to decide for each symbol whether this symbol must be allocated to the A or to the B group.
A further advantageous embodiment of an error correction circuit according to the invention is therefore characterized in that the classification circuit comprises a parity circuit for classifying newly received symbols for respective particular symbol locations into one of two classes which correspond to an even and an odd parity, respectively, of the newly received information, and for classifying symbol information already stored in the corresponding symbol addresses in the information store.
This results, at first sight, in very strange circuit, as now a parity check is performed on a code which contains no parity bit at all.
It is, of course, alternatively possible to record the relevant classification of a symbol in the information store, but this requires at least a tenth bit for each symbol address and, for a classification in more than two groups, it requires even more. It is, however, more advantageous, when a newly received symbol for a particular symbol location is compared with the symbol already stored in the corresponding symbol address of the information store, to determine the classification of the symbol again when it is read from the address, as this requires less material and the advantage that a standard 1 Kx9 RAM can be used is retained.
A further advantageous embodiment is characterized in that the error correction circuit comprises a second classification circuit for classifying a symbol read from the information store.
In the most advantageous case, wherein all extra symbols are even parity codes, this means a second parity check circuit.
In the case that classification in two classes coincides with an even and an odd parity, respectively, of the symbols, it furthermore appears to be possible to enter the classification in the information store in such a way that the notation of the classification does not require an additional storage bit.
An embodiment of an error correction circuit according to the invention, which is advantageous for this case, is characterized in that the error correction circuit comprises a modification circuit which after having determined the "0" or "1" parity value of a newly received symbol means of the parity circuit replaces the content of a fixed bit position of the newly received symbol by this parity value.
Any random bit can be selected as the fixed bit position in the symbol, for example, the eight bit in the case of an 8-bit symbol, whereas a ninth bit is used as, for example, the reliability bit.
There are four distruct possibilities:
| TABLE I |
| ______________________________________ |
| Modified Class Symbol (n+1) Parity symbol (n+1) Parity |
| ______________________________________ |
A xxxxxxx 1 1 xxxxxxx 1 1 A xxxxxxx 0 1 xxxxxxx 1 0 B xxxxxxx 1 0 xxxxxxx 0 1 B xxxxxxx 0 0 xxxxxxx 0 0 |
| ______________________________________ |
It is of course alternatively possible to realize th
e second
classification circuit virtually by using the first classification
circuit twice on a time-sharing basis, first as the first and then as
the second classification circuit. This requires some additional control
logic and some additional time, so that the provision of a second
classification circuit will be preferred, especially in the case where a
simple parity check is performed. The above-mentioned solution with its possible extensions will furnish the best result if all these extensions are provided. This is at the same time the most expensive solution. Error correction circuits which do not have all the above-described extensions are cheaper and hardly less good.
DESCRIPTION OF THE DRAWINGS
One specific combination will now be discussed in greater detail by way of example with reference to the drawings. On the basis thereof, any other combination can be easily implemented by one skilled in the art.
In the drawings:
FIG. 1 shows a simplified block diagram of a television receiver comprising a Teletext receiving section including an error correction circuit according to the invention.
FIG. 2 shows a simplified time diagram in which a number of different error combinations is shown in an exaggerated burst of errors.
DESCRIPTION OF THE PREFERRED EMBODIMENT
The embodiment chosen for FIG. 1 is suitable for reception in accordance with the proposed new code and comprises two clasification circuits consisting of two parity circuits, a comparison circuit for the bit-wise comparison of two symbols, a reliability circuit comprising a reliability flipflop and, in addition, the elements already known for a television plus Teletext receiver.
FIG. 1 shows a television receiver by means of a simplified block diagram.
A
receiving section 1 having an aerial input 2 comprises the
high-frequency receiving section, the intermediate-frequency amplifier
section, the detection and the synchronizing circuits of the receiver.
An audio output 3 is coupled to one or more loudspeakers 5 via an
audio amplifier 4. Via control switches 7 and 8 a video output 6 is
coupled for normal television reception to a video amplifier 9 for a
picture tube 10 comprising the picture screen 11. Via a control switch
13 a synchronizing output 12 is coupled during normal television
reception to a time-base circuit 14 which supplies the deflection
voltages for the picture tube 10 via an output 15. However, the control switches 7, 8 and 13 are shown in the position for Teletext reception and display.
Via the switch 7 the video signal is applied to an input 20 of a Teletext decoder 21, a synchronizing input 22 of which is coupled to the synchronizing output 12 of the receiving section 1.
In the Teletext decoder 21, serially received Teletext symbols are successively entered in parallel into a buffer register 23 thereof. Depending on the action decided upon, the contents of the buffer register 23 can be transferred to a storage register 24 of an information store 25, and from the storage register 24, the consecutive symbol addresses each corresponding to a symbol location on the picture screen 11 are filled, until the entire information store 25 is filled with the symbol information which corresponds to the desired Teletext page.
This and also the further processing operations are fully in agreement with the existing Teletext system. Addressing, reading of the information store, etc. are therefore not further described.
An output 26 of the information store 25 is coupled to a video (Teletext) generator 27, an output 28 of which is connected to the video amplifier 9 via the switch 8. In addition, there is provided in known manner a signal generator 29 and a generator 30 for generating several timing signals required in the receiver, which are applied to several other elements via outputs 31 to 35, inclusive. Synchronizing signals which can be applied to the time-base circuit 14 via the switch 13 are produced at the output 32.
The decision whether the content of the buffer register 23 must be transferred or not transferred to the storage register 24 is taken by an error correction circuit, which would, in the known Teletext system, consist of a parity check circuit.
The error correction circuit according to the invention consists of an error detection circuit 40 and, in the specific embodiment being described, a reliability circuit 60. The error detection circuit 40 comprises a parity circuit 41 for the buffer register 23, a parity circuit 42 for the storage register 24, a comparison circuit 43 for comparing the contents of buffer and storage registers 23, 24 with one another, and a number of write switches 44-0 to 44-7 inclusive. In this example these write switches are represented as respective AND-gates each having t
wo
inputs and an output. An input 45-i of each of the write switches is
always connected to a corresponding output 46-i of the buffer register
23, these outputs also being connected respectively to inputs 47-1 to
47-8 inclusive, of the parity circuit 41 and to inputs 48-0 to 48-7
inclusive, of the comparison circuit 43. The other input 49-i of each of the write switches is connected to a common write command input 50 of the error detection circuit 40.
In addition, output 51-i of the storage register 24 are connected to respective inputs 52-1 to 52-8 inclusive, of the parity circuit 42 and to corresponding further inputs 53-i of the comparison circuit 43 and to outputs 54-i of the write switches 44-0 to 44-7.
An odd parity-output 55 ("1" for odd-parity) of the parity circuit 41, is connected to an input 52-9 of the additional parity circuit 42, which has an output 56 for even or odd parity at the inputs 52-1 to 52-9, inclusive.
A Signetics IC No. 54180 or No. 8262 may, for example, be used for the parity circuit 41. If the parity of the symbol in the buffer register 23 is odd or even, a "1" and "0", respectively, appears at the output 55.
A Signetics IC No. 8262 may also be used for the parity circuit 42. If the parity of the symbol in the storage register 24 is odd and a "1" has appeared at the output 55, then a "1" appears at the output 56 for the even parity of the parity circuit 42, that is to say both symbols had an odd parity. If both symbols have an even parity the input 52-9 receives a zero, so that the total number of ones is even again and the output 56 shows an "1" again. Should the parities of the buffer register 23 and the storge register 24 be unequal, then the output 56 shows "0".
Thus the output 56 (Even Parity) may be considered to be an output which indicates by means of the "1", that the investigated symbols have an equal parity (Equal Parity, EP).
The comparison circuit 43 has an output 57 which becomes a "1" as soon as all the bits of the compared symbols are mutually equal. The signal thus obtained will be denoted EB (Equal Bytes).
The reliability circuit 60 comprises a flipflop 61 having number of writing gates 62. A JK flipflop is chosen for the described example but this is not essential to the inventive idea. One half of a Signetics 54112 may, for example, be used as a JK flipflop. Descriptions, truth tables and time diagrams of the above-mentioned Signetics circuits are known from the Philips Signetics Data Handbook.
The reliability circit 60 satisfies the following equations:
CK R =CLK, obtained from the clock signal generator 29. J R =R/WR G +(R/W)'EP (I) K R =R/WR G +(R/W)'EB (II)
in which R G is the reliability status as stored in the memory 25,
The operation of the JK-flipflop can be explained as follows, reference also being made to the time diagram of FIG. 2. Within successive periods of approximately 25 seconds the symbols for 960 symbol locations (i.e. a page of text) are repeatedly received. The solid line sections 100 represent the symbol processing of the symbol S x in consecutive cycles 0 to 7, inclusive, indicated as S x ,0 to S x ,7 inclusive. The broken line sections represent in a very concise manner the processing of S 0 to S x -1, inclusive, and S x +1 to S 959 , inclusive, one processing period comprising, for example, two cycles of the clock signal 101 of the clock signal generator 29 and one read/write cycle consisting of the portions R/W and (R/W)', read and write respectively, controlled by the signal 102, obtained from the output 31 of time signal generator 30. During the read portion 103 of cycle 102 the contents of a symbol address which correspond with the signal combination entered in the buffer register 23 for a given symbol location, is entered into the storage register 24. As each symbol address has a ninth bit for a reliability bit, a status value R G appears simultaneously at an output 63 of the information store 25. On the first rising clock edge 104 only the first terms of the equations I and II are operative, as R/W="1" and consequently (R/W)'="0". This means that at the instant 104 the flipflop 61, R assumes the value "1" when R G ="1" and the value "0" when R G ="0", as shown in the line sections 105. At the next clock edge 106 only the second terms are operative, and the flipflop 61 can now retain the previously adjusted value or assume the other value. This final value at the output 64 of the flipflop 61 is applied to an input 65 of the information store for writing a next R G in the ninth bit of the corresponding storage address.
The output 66 (R') of the flipflop 61, which is connected to thewrite command signal input 50 of the error detection circuit 50, further determines whether the contents of the buffer register 23 can be transferred to the storage register 24 during the write cycle 107 (see FIG. 2).
Finally, the lines 108, 109 of FIG. 2 represent two bit contents of the storage register and 110, 111 represent two bit contents of the buffer register. For clarity's sake the remaining bits have been omitted.
The signal EP is denoted by 112, and the signal EB by 113.
In this example the following set of decision rules has been realised in the circuit.
| TABLE II |
| ______________________________________ |
| Decision Read Write SR EP EB R G 23➝24 Written S R K R |
| ______________________________________ |
1 0 0 0 1 0 0 x 2 1 0 0 1 1 1 x 3 1 1 0 1 1 1 x 5 1 1 1 0 1 x 1 6 1 0 1 0 0 x 0 7 0 0 1 0 0 x 0 (4) 1 0 0 1 0 0 x |
| ______________________________________ |
FIG.
2 shows the states and EP, EB and R in the line sections 112, 113 and
105, respectively, by means of an example which shows an unprobable
burst of received errors, such that each one of the decisions occurs at
least once. When the first cycle starts, the entire information store 25 is filled with space symbols. The space symbol is an A-symbol, denoted in FIG. 2 by A. It is assumed that the transmitter transmits a B-symbol and continues to do so. A faulty B-symbol has the same parity as A and is denoted by B'. On the basis of decision 1, EP=0, EB=0 and R G ="0" in the second half of the cycle a B' (erroneously received B with an even number of errors) is written into the storage register 24. The new R G remains "0" because J R =0, K R =x.
In the next cycle the buffer register 23 contains a correctly received B, which is transferred to the storage register 24 in accordance with decision 2.
The further cycles need no explanation. (B) indicates when there is no transfer to the store. The B already present in the relevant symbol address is not changed.
Throughout the example of the transmitter
transmitted: B B B B B B B B
received: B' B B' B B A B B
dislayed: B' B (B) B B (B) B B
The displayed error B' in the first cycle can of course not be avoided in this example, all following results are correct.
Any other possible received sequence can be followed in a similar manner.
Two of the decisions need some further explanation.
Decision 2 with EP="1" and EB="0", seems to indicate a multiple and, consequently, very rare error. As the information store 25 is initially filled with A's and the probability that an A will be received is high, this "error" will occur very frequently, especially in the first cycle.
Any double error occurring at a later instant will be treated likewise, in that very rare event.
Decision 6 deals with an equally rare event, but with R G ="1". It shortens the elimination of a multiple error, but will be rarely necessary. However, this decision 6 can be combined cheaply with decision 7.
In the embodiment explained on the basis of Table I the processing of EP in particular is simplified.
The following simple process can now, for example, be applied.
A newly received symbol is applied to the input of the parity circuit 41.
If the newly received symbol (n+1) is a symbol from the A group, then the parity circuit 41 indicates an odd parity that is to say a "1"
at the output "odd parity". This "1" is transferred to the eight bit of the buffer register 23.
By comparing a corresponding symbol (n) from the information store 25 with a modified symbol (n+1), EP can now be found by comparing the two eights bits of the buffer register 23 and the storage register 24. EB can be determined as previously to detect whether there is or there is not a difference between the two (modified) symbols.
In dependence on EP, EB and R, it is decided in a conventional manner whether the modified symbol will be written or not written into the information store 25. Thus the information store 25 comprises modified symbols only, so that in checking with the comparator 43, this check must be made against the also modified, newly received symbol.
During the display of the page, the parity circuit 41 is available for remodification, it only being necessary to invert the eighth bit if the eighth bit of the symbol to be displayed differs from the parity of this symbol, that is to say it is sufficient to replace the eighth bit of the storge register 24 by the parity now found..
A slight improvement can still be obtained by means of the additional decision (see at the bottom of the Table II). However, to enable the use of this additional decision, instead of decision 2 which can then only hold for the first cycle, a cycle counter must now be incorporated which forms with New Request="1" an additional condition for decision 2 and which, in all subsequent cycles with NR="0" results in decision 4 when EP=1, EB=0 and R G =0.
In view of what was described herefore such an extension can be easily realized by one normally skilled in the art of logic design.
In extremely rare cases this embodiment results in a further small improvement.
A simplified embodiment produces for all normal single errors an equally satisfactory result but it deals with the multiple errors in a less satisfactory way. However, the total result remains very satisfactory for the user.
The entire comparison circuit is omitted from this simplified embodiment. The decision table is now reduced to:
| TABLE III |
| ______________________________________ |
| Read Write Written Decision EP R G 23-24 R G |
| ______________________________________ |
1A 1 0 1 1 2A 1 1 1 1 3A 0 0 1 0 4A 0 1 0 0 |
| ______________________________________ |
The same applies if smll changes are desired in the decisions, and also when, for example, the circuit must be implemented in the form of one or more Large Scale Integrated circuits (LSI), or when it is realized wholly or partly by means of a micro-processor.
SFC318 OPERATIONAL AMPLIFIER THOMSON
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73. J. Geogopoulos, Fiber Optics and Optical Isolators.
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75. C. Hart and E. W. Malone, Lighting and Lighting Protection.
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78. Mardiguian, How to Control Electrical Noise.
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82. A. Smith, Coupling of External Electromagnetic Fields to Transmission Lines.
83. R. J. White and M. Mardiguian, E MI Control Methodolgy and Procedures.
84. R. J. White, E MI Control in the Design of Printed Circuit Boards and Backplanes, 248 Pages.
85. R. J. White, Shielding Design Methodlogy and Procedures.
86. R. J. White, Electrical Filter
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87. R. J. White, Electromagnetic Shielding Materials and Performance.
88. E MC E XPO, 1986 Symposium Record, 416 Pages.
89. E MC Library :
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vol. 3 E MI Control Methods and Techniques
vol. 4 E MI Test Instrumentation and Systems
vol. 5 E MI Prediction and Analysis Techniques
vol. 6 E MI Specifications, Standards, and Regulations
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VERTER, 17th Power Sources Conference proceedings, 1963, pp.
155-158
[3] van Velthooven, C., PROPERTIES OF DC-TO-DC CONVERT-
ERS FOR SWITCHED-MODE POWER SUPPLIES, Philips
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[4] G. Wolf, MAINS ISOLATING SWITCH-MODE POWER SUP-
PLY, Philips Electronic Applications Bulleting, Vol. 32, No. 1,
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[5] La Duca and Massey, IMPROVED SINGLE-ENDED REGU-
LATED DC/DC CONVERTER CIRCUIT, IEEE Power Electronics
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[6] Heinicke, Harald, APPARATUS FOR CONVERTING D.C.
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[7] Hamata and Katou, DC-TO-DC CONVERTER, U.S. patent
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[8] Peterson, W.A., A FREQUENCY-STABILIZED FREE-RUN-
NING DC-TO-DC CONVERTER CIRCUIT EMPLOYING
PULSE-WIDTH CONTROL REGULATION, IEEE PESC proceed-
ings, June 1976, pp. 200-205
[9] Vermolen, J.V., NON-SATURATING ASYMMETRIC DC/DC
CONVERTER, U.S. patent number 3,963,973, 15 June 1976 (1973
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[10] Lilienstein and Miller, THE BIASED TRANSFORMER DC-
TO-DC CONVERTER, IEEE PESC proceedings, June 1976, pp.
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[11] Carsten, B., HIGH POWER SMPS REQUIRE INTRINSIC
RELIABILITY, Power Conversion International (PCI) proceedings,
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[12] Kuwabara and Miyachika, A VERY WIDE INPUT RANGE
DC-DC CONVERTER, IEEE INTELEC proceedings, 1987, pp.
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[13] Wittenbreder, Martin and Baggerly, A DUTY CYCLE
EXTENSION TECHNIQUE FOR SINGLE ENDED FORWARD
CONVERTERS, IEEE Applied Power Electronics Conference
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More References:
Buhler H (1986) Sliding mode control (in French: Reglage ́
par mode de glissement). Presses
Polytechniques Romandes, Lausanne
Carpita M, Marchesoni M (1996) Experimental study of a power conditioning system using sliding
mode control. IEEE Trans Power Electron 11(5):731–742
Carrasco JM, Quero JM, Ridao FP, Perales MA, Franquelo LG (1997) Sliding mode control of a
DC/DC PWM converter with PFC implemented by neural networks. IEEE Trans Circuit Syst I
Fundam Theor Appl 44(8):743–749
DeBattista H, Mantz RJ, Christiansen CF (2000) Dynamical sliding mode power control of wind
driven induction generators. IEEE Trans Energy Convers 15(4):728–734
DeCarlo RA, Zak ̇
SH, Drakunov SV (2011) Variable structure, sliding mode controller design. In:
Levine WS (ed) The control handbook—control system advanced methods. CRC Press, Taylor
& Francis Group, Boca Raton, pp 50-1–50-22
Emelyanov SV (1967) Variable structure control systems. Nauka, Moscow (in Russian)
Filippov AF (1960) Differential equations with discontinuous right hand side. Am Math Soc
Transl 62:199–231
Guffon S (2000) Modelling and variable structure control for active power filters (in French:
“Modelisation ́
et commandes `
a structure variable de filtres actifs de puissance”). Ph.D. thesis,
Grenoble Institute of Technology, France
Guffon S, Toledo AS, Bacha S, Bornard G (1998) Indirect sliding mode control of a three-phase
active power filter. In: Proceedings of the 29th annual IEEE Power Electronics Specialists
Conference – PESC 1998. Kyushu Island, Japan, pp 1408–1414
Hung JY, Gao W, Hung JC (1993) Variable structure control: a survey. IEEE Trans Ind Electron
40(1):2–22
Itkis U (1976) Control systems of variable structure. Wiley, New York
Levant A (2007) Principles of 2-sliding mode design. Automatica 43(4):576–586
Levant A (2010) Chattering analysis. IEEE Trans Autom Control 55(6):1380–1389
Malesani L, Rossetto L, Spiazzi G, Tenti P (1995) Performance optimization of Cuk ́
converters by
sliding-mode control. IEEE Trans Power Electron 10(3):302–309
Malesani L, Rossetto L, Spiazzi G, Zuccato A (1996) An AC power supply with sliding mode
control. IEEE Ind Appl Mag 2(5):32–38
Martinez-Salamero L, Calvente J, Giral R, Poveda A, Fossas E (1998) Analysis of a bidirectional
coupled-inductor Cuk ́
converter operating in sliding mode. IEEE Trans Circuit Syst I Fundam
Theor Appl 45(4):355–363
Mattavelli P, Rossetto L, Spiazzi G (1997) Small-signal analysis of DC–DC converters with
sliding mode control. IEEE Trans Power Electron 12(1):96–102
ˇ
Sabanovic A (2011) Variable structure systems with sliding modes in motion control—a survey.
IEEE Trans Ind Inform 7(2):212–223
Sabanovic ˇ
A, Fridman L, Spurgeon S (2004) Variable structure systems: from principles to
implementation, IEE Control Engineering Series. The Institution of Engineering and Technol-
ogy, London
Sira-Ramırez ́ H (1987) Sliding motions in bilinear switched networks. IEEE Trans Circuit Syst 34
(8):919–933
Sira-Ramırez ́
H (1988) Sliding mode control on slow manifolds of DC to DC power converters. Int
J Control 47(5):1323–1340
Sira-Ramırez ́
H (1993) On the dynamical sliding mode control of nonlinear systems. Int J Control
57(5):1039–1061
Sira-Ramırez ́
H (2003) On the generalized PI sliding mode control of DC-to-DC power converters:
a tutorial. Int J Control 76(9/10):1018–1033
Sira-Ramırez ́
H, Silva-Ortigoza R (2006) Control design techniques in power electronics devices.
Springer, London
Slotine JJE, Sastry SS (1983) Tracking control of non-linear systems using sliding surface, with
application to robot manipulators. Int J Control 38(2):465–492
Spiazzi G, Mattavelli P, Rossetto L, Malesani L (1995) Application of sliding mode control to
switch-mode power supplies. J Circuit Syst Comput 5(3):337–354
Tan S-C, Lai YM, Cheung KHM, Tse C-K (2005) On the practical design of a sliding mode
voltage controlled buck converter. IEEE Trans Power Electron 20(2):425–437
Tan S-C, Lai Y-M, Tse C-K (2011) Sliding mode control of switching power converters:
techniques and implementation. CRC Press, Taylor & Francis Group, Boca Raton
Utkin VA (1972) Equations of sliding mode in discontinuous systems. Autom Remote Control 2
(2):211–219
Utkin VA (1977) Variable structure systems with sliding mode. IEEE Trans Autom Control 22
(2):212–222
Utkin V (1993) Sliding mode control design principles and applications to electric drives. IEEE
Trans Ind Electron 40(1):23–36
Venkataramanan R, Sabanovic ˇ
A, Cuk ́
S (1985) Sliding mode control of DC-to-DC converters. In:
Proceedings of IEEE Industrial Electronics Conference – IECON 1985. San Francisco,
California, USA, pp 251–258
Young KD, Utkin VI, Ozguner U (1999) A control engineer’s guide to sliding mode control. IEEE
Trans Control Syst Technol 7(3):328–342
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Other References
Buhler H (1986) Sliding mode control (in French: Reglage ́
par mode de glissement). Presses
Polytechniques Romandes, Lausanne
Carpita M, Marchesoni M (1996) Experimental study of a power conditioning system using sliding
mode control. IEEE Trans Power Electron 11(5):731–742
Carrasco JM, Quero JM, Ridao FP, Perales MA, Franquelo LG (1997) Sliding mode control of a
DC/DC PWM converter with PFC implemented by neural networks. IEEE Trans Circuit Syst I
Fundam Theor Appl 44(8):743–749
DeBattista H, Mantz RJ, Christiansen CF (2000) Dynamical sliding mode power control of wind
driven induction generators. IEEE Trans Energy Convers 15(4):728–734
DeCarlo RA, Zak ̇
SH, Drakunov SV (2011) Variable structure, sliding mode controller design. In:
Levine WS (ed) The control handbook—control system advanced methods. CRC Press, Taylor
& Francis Group, Boca Raton, pp 50-1–50-22
Emelyanov SV (1967) Variable structure control systems. Nauka, Moscow (in Russian)
Filippov AF (1960) Differential equations with discontinuous right hand side. Am Math Soc
Transl 62:199–231
Guffon S (2000) Modelling and variable structure control for active power filters (in French:
“Modelisation ́
et commandes `
a structure variable de filtres actifs de puissance”). Ph.D. thesis,
Grenoble Institute of Technology, France
Guffon S, Toledo AS, Bacha S, Bornard G (1998) Indirect sliding mode control of a three-phase
active power filter. In: Proceedings of the 29th annual IEEE Power Electronics Specialists
Conference – PESC 1998. Kyushu Island, Japan, pp 1408–1414
Hung JY, Gao W, Hung JC (1993) Variable structure control: a survey. IEEE Trans Ind Electron
40(1):2–22
Itkis U (1976) Control systems of variable structure. Wiley, New York
Levant A (2007) Principles of 2-sliding mode design. Automatica 43(4):576–586
Levant A (2010) Chattering analysis. IEEE Trans Autom Control 55(6):1380–1389
Malesani L, Rossetto L, Spiazzi G, Tenti P (1995) Performance optimization of Cuk ́
converters by
sliding-mode control. IEEE Trans Power Electron 10(3):302–309
Malesani L, Rossetto L, Spiazzi G, Zuccato A (1996) An AC power supply with sliding mode
control. IEEE Ind Appl Mag 2(5):32–38
Martinez-Salamero L, Calvente J, Giral R, Poveda A, Fossas E (1998) Analysis of a bidirectional
coupled-inductor Cuk ́
converter operating in sliding mode. IEEE Trans Circuit Syst I Fundam
Theor Appl 45(4):355–363
Mattavelli P, Rossetto L, Spiazzi G (1997) Small-signal analysis of DC–DC converters with
sliding mode control. IEEE Trans Power Electron 12(1):96–102
ˇ
Sabanovic A (2011) Variable structure systems with sliding modes in motion control—a survey.
IEEE Trans Ind Inform 7(2):212–223
Sabanovic ˇ
A, Fridman L, Spurgeon S (2004) Variable structure systems: from principles to
implementation, IEE Control Engineering Series. The Institution of Engineering and Technol-
ogy, London
References:
Sira-Ramırez ́
H (1987) Sliding motions in bilinear switched networks. IEEE Trans Circuit Syst 34
(8):919–933
Sira-Ramırez ́
H (1988) Sliding mode control on slow manifolds of DC to DC power converters. Int
J Control 47(5):1323–1340
Sira-Ramırez ́
H (1993) On the dynamical sliding mode control of nonlinear systems. Int J Control
57(5):1039–1061
Sira-Ramırez ́
H (2003) On the generalized PI sliding mode control of DC-to-DC power converters:
a tutorial. Int J Control 76(9/10):1018–1033
Sira-Ramırez ́
H, Silva-Ortigoza R (2006) Control design techniques in power electronics devices.
Springer, London
Slotine JJE, Sastry SS (1983) Tracking control of non-linear systems using sliding surface, with
application to robot manipulators. Int J Control 38(2):465–492
Spiazzi G, Mattavelli P, Rossetto L, Malesani L (1995) Application of sliding mode control to
switch-mode power supplies. J Circuit Syst Comput 5(3):337–354
Tan S-C, Lai YM, Cheung KHM, Tse C-K (2005) On the practical design of a sliding mode
voltage controlled buck converter. IEEE Trans Power Electron 20(2):425–437
Tan S-C, Lai Y-M, Tse C-K (2011) Sliding mode control of switching power converters:
techniques and implementation. CRC Press, Taylor & Francis Group, Boca Raton
Utkin VA (1972) Equations of sliding mode in discontinuous systems. Autom Remote Control 2
(2):211–219
Utkin VA (1977) Variable structure systems with sliding mode. IEEE Trans Autom Control 22
(2):212–222
Utkin V (1993) Sliding mode control design principles and applications to electric drives. IEEE
Trans Ind Electron 40(1):23–36
Venkataramanan R, Sabanovic ˇ
A, Cuk ́
S (1985) Sliding mode control of DC-to-DC converters. In:
Proceedings of IEEE Industrial Electronics Conference – IECON 1985. San Francisco,
California, USA, pp 251–258
Young KD, Utkin VI, Ozguner U (1999) A control engineer’s guide to sliding mode control. IEEE
Trans Control Syst Technol 7(3):328–342
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forward and Current-mode Control,” Proc. Powercon, 7, 1980.
Middlebrook,
R. D., Hsu, Shi-Ping, Brown, Art, and Rensink, Lowman, “Modelling and
AnalysisSwitching DC-DC Converters in Constant-Frequency
Current-Programmed Mode,” IEEE Power Elec-
tronics Specialists Conference, 1979.
Bloom, Gordon (Ed), and Severns, Rudy, “Magnetic Integration Methods for Transformers,” in Isolated
Buck and Boost DC-DC Converters, 1982.
Hetterscheid, W., “Base Circuit Design for High-Voltage Switching Transistors in Power Converters,”
Mullard Technical Note 6, 1974.
Gates, T. W., and Ballard, M. F., “Safe Operating Area for Power Transistors,” Mullard Technical
Communications, Vol. 13, No. 122, April 1974.
Dean-Venable, H., “The K Factor: A New Mathematical Tool for Stability Analysis and Synthesis,” Proc.
Powercon, 10, March 1983.
Dean-Venable, H., and Foster, Stephen R., “Practical Techniques for Analyzing, Measuring, and Stabi-
lizing Feedback Control Loops in Switching Regulators and Converters,” Proc. Powercon, 7, 1980.
Tuttle, Wayne H., “The Relationship of Output Impedance to Feedback Loop Parameters,” PCIM,
November 1986.
Dean-Venable, H., “Stability Analysis Made Simple,” Venable Industries, Torrance, Calif., 1982.
of
Tuttle, Wayne H., “Relating Converter Transient Response to Feedback Loop Design,” Proc. Powercon,
11, 1984.
Dean-Venable, H., “Optimum Feedback Amplifier Design Control Systems,” Proc. IECEC, August 1986.
Tuttle, Wayne H., “Why Conditionally Stable Systems Do Not Oscillate,” Proc. PCI, October 1985.
Jongsma, J., and Bracke, L. P. M., “Improved Method of Power-Coke Design,” Electronic Compo-
nents and Applications, vol. 4, no. 2, 1982.
Bracke, L. P. M., and Geerlings, F. C., “Switched-Mode Power Supply Magnetic Component Require-
ments,” Philips Electronic Components and Materials, 1982.
REFERENCES:
60. Carsten, Bruce, “High Frequency Conductor Losses in Switchmode Magnetics,” PCIM, November 1986.
61. Clarke, J. C., “The Design of Small Current Transformers,” Electrical Review, January 1985.
62. Houldsworth, J. A., “Purpose-Designed Ferrite Toroids for Isolated Current Measurements in Power
Electronic Equipment,” Mullard Technical Publication M81-0026, 1981.
63. Cox, Jim, “Powdered Iron Cores and a New Graphical Aid to Choke Design,” Powerconversion Interna-
tional, February 1980.
64. Cox, Jim, “Characteristics and Selection of Iron Powder Cores for Induction in Switchmode Convert-
ers,” Proc. Powercon, 8, 1981.
65. Cattermole, Patrick A., “Optimizing Flyback Transformer Design.” Proc. Powercon, 1979, PC 79-1-3.
66. Geerlings, F. C., and Bracke, L. P. M., “High-Frequency Ferrite Power Transformer and Choke Design,
Part 1,” Electronic Components and Applications, vol. 4, no. 2, 1982.
67. Jansson, L. E., “Power-handling Capability of Ferrite Transformers and Chokes for Switched-Mode
Power Supplies,” Mullard Technical Note 31, 1976.
68. Hirschmann, W., Macek, O., and Soylemez, A. I., “Switching Power Supplies 1 (General, Basic Circuits),”
Siemens Application Note.
69. Ackermann, W., and Hirschmann, W., “Switching Power Supplies 2, (Components and Their Selection
and Application Criteria),” Siemens Application Note.
70. Schaller, R., “Switching Power Supplies 3, (Radio Interference Suppression),” Siemens Application Note.
71. Macek, O., “Switching Power Supplies 4, (Basic Dimensioning), “Siemens Application Note.
72. Bulletin SFB, Buss Small Dimension Fuses, Bussmann Division, McGraw-Edison Co., Missouri.
73. Catalog #20, Littlefuse Circuit Protection Components, Littlefuse Tracor, Des Plaines, III.
74. Bulletin-B200, Brush HRC Current Limiting Fuses, Hawker Siddeley Electric Motors, Canada.
75. Bulletins PC-104E and PC109C, MPP and Iron Powder Cores, The Arnold Engineering Co., Marengo,
Illinois.
76. Publication TP-25-575, HCR Alloy, Telcon Metals Ltd., Sussex, England.
77. Catalog 4, Iron Powder Toridal Cores for EMI and Power Filters, Micrometals, Anaheim, Calif.
78. Bulletin 59–107, Soft Ferrites, Stackpole, St. Marys, Pa.
79. SOAR—The Basis for Reliable Power Circuit Design, Philips Product Information #68.
80. Bennett, Wilfred P., and Kurnbatovic, Robert A., “Power and Energy Limitations of Bipolar Transistors
Imposed by Thermal-Mode and Current-Mode Second-Breakdown Mechanisms,” IEEE Transactions
on Electron Devices, vol. ED28, no. 10, October 1981.
81. Roark, D. “Base Drive Considerations in High Power Switching Transistors,” TRW Applications Note
#120, 1975.
82. Gates, T. W., and Ballard, M. F., “Safe Operating Area for Power Transistors,” Mullard Technical Com-
munications, vol. 13, no. 122, April 1974.
83. Williams, P. E., “Mathematical Theory of Rectifier Circuits with Capacitor-Input Filters,” Power Con-
version International, October 1982.
84. “Guide for Surge Voltages in Low-Voltage AC Power Circuits,” IEC Publication 664, 1980.
85. Kit Sum, K., PCIM, February 1998.
86. Spangler, J., Proc. Sixth Annual Applied Power Electronics Conf., Dallas, March 10–15, 1991.
87. Neufeld, H., “Control IC for Near Unity Power Factor in SMPS,” Cherry Semiconductor Corp., October 1989.
88. Micro Linear application notes 16 and 33.
89. Micro Linear application note 34.
90. Micrometals’ “Power Conversion & Line Filter Applications” data book.
91. Pressman, Abraham I., Billings, Keith, Morey, Taylor, Switching Power Supply Design, McGraw-Hill,
2009. ISBN 978-0-07-148272-1.
92. Texas Instruments/Unitrode Data Sheet UCC3895 SLUS 157B & application notes U136A & U154.
93. Stanley, William D., Operational Amplifiers with Linear Integrated Circuits, 2d Ed., Merrill, Columbus,
Ohio, 1989. ISBN 067520660-X.
94. “LM13700 Dual Operational Transconductance Amplifiers with Linearizing Diodes and Buffers,”
National Semiconductor Corporation, 2004. http://www.national.com/ds/LM/LM13700.pdf.
Further References:
1. G. Aboud, Cathode Ray Tubes, 1997, 2nd ed., San Jose, CA, Stanford Resources, 1997.
2. G. Aboud, Cathode Ray Tubes, 1997, Internet excerpts, available http://www.stanfordresources.com/
sr/crt/crt.html, Stanford Resources, February 1998.
3. G. Shires, Ferdinand Braun and the Cathode Ray Tube, Sci. Am., 230 (3): 92–101, March 1974.
4. N. H. Lehrer, The challenge of the cathode-ray tube, in L. E. Tannas, Jr., Ed., Flat Panel Displays
and CRTs, New York: Van Nostrand Reinhold, 1985.
5. P. Keller, The Cathode-Ray Tube, Technology, History, and Applications, New York: Palisades Press,
1991.
6. D. C. Ketchum, CRT’s: the continuing evolution, Society for Information Display International
Symposium, Conference Seminar M-3, 1996.
7. L. R. Falce, CRT dispenser cathodes using molybdenum rhenium emitter surfaces, Society for
Information Display International Symposium Digest of Technical Papers, 23: 331–333, 1992.
8. J. H. Lee, J. I. Jang, B. D. Ko, G. Y. Jung, W. H. Kim, K. Takechi, and H. Nakanishi, Dispenser
cathodes for HDTV, Society for Information Display International Symposium Digest of Technical
Papers, 27: 445–448, 1996.
9. T. Nakadaira, T. Kodama, Y. Hara, and M. Santoku, Temperature and cutoff stabilization of
impregnated cathodes, Society for Information Display International Symposium Digest of Technical
Papers, 27: 811–814, 1996.
10. W. Kohl, Materials Technology for Electron Tubes, New York, Reinhold Publishing, 1951.
11. S. Sugawara, J. Kimiya, E. Kamohara, and K. Fukuda, A new dynamic-focus electron gun for color
CRTs with tri-quadrupole electron lens, Society for Information Display International Symposium
Digest of Technical Papers, 26: 103–106, 1995.
12. J. Kimiya, S. Sugawara, T. Hasegawa, and H. Mori, A 22.5 mm neck color CRT electron gun with
simplified dynamically activated quadrupole lens, Society for Information Display International
Symposium Digest of Technical Papers, 27: 795–798, 1996.
13. D. Imabayashi, M. Santoku, and J. Karasawa, New pre-focus system structure for the trinitron gun,
Society for Information Display International Symposium Digest of Technical Papers, 27: 807–810,
1996.
14. K. Kato, T. Sase, K. Sasaki, and M. Chiba, A high-resolution CRT monitor using built-in ultrasonic
motors for focus adjustment, Society for Information Display International Symposium Digest of
Technical Papers, 27: 63–66, 1996.
15. S. Sherr, Electronic Displays, 2nd ed., New York: John Wiley, 1993.
16. N. Azzi and O. Masson, Design of an NIS pin/coma-free 108° self-converging yoke for CRTs with
super-flat faceplates, Society for Information Display International Symposium Digest of Technical
Papers, 26: 183–186, 1995.
17. J. F. Fisher and R. G. Clapp, Waveforms and spectra of composite video signals, in K. Benson and
J. Whitaker, Television Engineering Handbook, Featuring HDTV Systems, New York: McGraw-Hill
Reinhold, 1992.
18. D. Pritchard, Standards and recommended practices, in K. Benson and J. Whitaker, Television
Engineering Handbook, Featuring HDTV Systems, New York: McGraw-Hill Reinhold, 1992.
19. A. Vecht, Phosphors for color emissive displays, Society for Information Display International Sym-
posium Conference Seminar Notes F-2, 1995.
20. Optical Characteristics of Cathode Ray Tube Screens, EIA publication TEP116-C, Feb., 1993.
21. G. Wyszecki and W. S. Stiles, Color Science: Concepts and Methods, Quantitative Data and Formulae,
2nd ed., New York: John Wiley & Sons, 1982.
© 1999 by CRC Press LLC
22. A. Robertson and J. Fisher, Color vision, representation, and reproduction, in K. Benson and J.
Whitaker, Television Engineering Handbook, Featuring HDTV Systems, New York: McGraw-Hill
Reinhold, 1992.
23. M. Maeda, Trinitron technology: current status and future trends, Society for Information Display
International Symposium Digest of Technical Papers, 27: 867–870, 1996.
24. C. Sherman, Field sequential color takes another step, Inf. Display, 11 (3): 12–15, March, 1995.
25. L. Ozawa, Helmet mounted 0.5 in. crt for SVGA images, Society for Information Display Interna-
tional Symposium Digest of Technical Papers, 26: 95–98, 1995.
26. C. Infante, CRT display measurements and quality, Society for Information Display International
Symposium Conference Seminar Notes M-3, 1995.
27. J. Whitaker, Electronic Displays, Technology, Design, and Applications, New York: McGraw-Hill, 1994.
28. P. Keller, Electronic Display Measurement, Concepts, Techniques, and Instrumentation, New York:
John Wiley & Sons, 1997.
Further Information
L. Ozawa, Cathodoluminescence: Theory and Applications, New York: Kodansha, 1990.
V. K. Zworykin and G. A. Morton, Television: The Electronics of Image Transmission in Color and Mono-
chrome, New York: John Wiley & Sons, 1954.
B. Wandell, The foundations of color measurement and color perception, Society for Information Display
International Symposium, Conference Seminar M-1, 1993. A nice brief introduction to color science
(31 pages).
Electronic Industries Association (EIA), 2500 Wilson Blvd., Arlington, VA 22201 (Internet: www.eia.org).
The Electronic Industries Association maintains a collection of over 1000 current engineering publi-
cations and standards. The EIA is an excellent source for information on CRT engineering, standards,
phosphors, safety, market information, and electronics in general.
The Society for Information Display (SID), 1526 Brookhollow Dr., Suite 82, Santa Ana, CA 92705-5421
(Internet: www.display.org). The Society for Information Display is a good source of engineering
research and development information on CRTs and information display technology in general.
Internet Resources:
The following is a brief list of places to begin looking on the World Wide Web for information on CRTs
and displays, standards, metrics, and current research. Also many of the manufacturers listed in Table
91.3 maintain Web sites with useful information.
The Society for Information Display
The Society of Motion Picture and Television Engineers
The Institute of Electrical and Electronics Engineers
The Electronic Industries Association
National Information Display Laboratory
The International Society for Optical Engineering
The Optical Society of America
Electronics & Electrical Engineering Laboratory
National Institute of Standards and Technology (NIST)
The Federal Communications Commission
www.display.org
www.smpte.org
www.ieee.org
www.eia.org
www.nta.org
www.spie.org
www.osa.org
www.eeel.nist.gov
www.nist.gov
www.fcc.gov
Philips Data Handbook, Electronic Components and Materials "Integrated Circuits: Part 3, Sep. 1982: ICs for Digital Systems in Radio, Audio, and Video Equipment: SAA5020 Series", pp. 1-10.
Philips Data Handbook, Electronic Components and Materials "Integrated Circuits: Book IC02a, 1986: Video and Associated Systems: Bipolar, MOS: Types MAB8031AH to TDA1521", pp. 374-375.
F. J. R. Kinghorn, "Computer Controlled Teletext"; Electronic Components and Applications; vol. 6, No. 1, 1984, pp. 15-29.
"World System Teletext Technical Specification", Revised Mar. 1985, pp. 1-10 and 38-41.
Philips Data Handbook, Electronic Components and Materials; "Integrated Circuits, Part 2: Jan. 1983: Bipolar ICs for Video Equipment: TDA2540, TDA2540Q"; pp. 1-8.
Philips Data Handbook, Electronic Components and Materials; "Integrated Circuits: Part 2: Jan. 1983: Bipolar ICs for Video Equipment: TDA 3562A"; pp. 1-16.
Philips Data Handbook, Electronic Components and Materials "Integrated Circuits: Part 3, Sep. 1982: IC's for Digital Systems in Radio, Audio, and Video Equipment: SAA3004"; pp. 1-10.
Philips Data Handbook, Electronic Components and Materials, "Integrated Circuits: Part 3, Sep. 1982: Ics for Digital Systems in Radio, Audio, and Video Equipment: SAB3035", pp. 1-4.
Philips Data Handbook, Electronic Components and Materials "Integrated Circuits: Part 3, Sep. 1982: ICs for Digital Systems in Radio, Audio and Video Equipment: TDB2033.
A data sheet for a teletext video processor SAA5030 produced by Mullard Co., dated Jun., 1981.
An article entitled, "Teletext Decoder" that appears in a publication entitled, LSI Circuits for Teletext and Viewdata, The Lucy Generation, pp. 15-20, dated Jun., 1981, published by Mullard Limited, London, England.
A data sheet for videotext data slicer and clock regenerator SL9100EXP published by Plessey Semiconductors, Ltd.
Mullard Dat Sheet SAA5040 Series Teletext
Acquisition and Control Circuit, Jun. 1981.
"Wireless World Teletext Decoder"; Daniels;
Wireless World, vol. 81, No. 1480, Dec. 1975, pp. 563-566.
"Teletext Data Decoding-The LSI Approach";
Norris et al., IEEE Transactions on Consumer Electronics, vol. CE-22,
No. 3, Aug. 1973, pp. 247-253.
"Broadcast Teletext Specification"; BBC, Sep. 1976.
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