THE SALORA 28M91 CHASSIS M CHASSIS SALORA STB253 110° M-CHASSIS DIGITAL Based completely on DIGIVISION ITT TECHNOLOGY and SALORA IPSALO (Power supply) and around a ITT CCU2000 As a main CPU.
THE
CHASSIS SALORA M-CHASSIS STB253 110° DIGITAL WAS FIRST SALORA DIGITAL
CHASSIS AND WAS USED EVEN IN HITACHI TV SETS AS SALORA WAS DEMANDED TO
DO SO.
It has a notable improvements and a high integration fashion which bring this chassis as an example of high engineering and complexity.
It's pretty unique for it's design engineering using for first time a 3 layers PCB and special circuitry development solutions I.E. the E/W modulator and other many parts.
DIGITIZATION OF "TV FUNCTIONS"
SALORA 28M91 CHASSIS M CHASSIS SALORA M-CHASSIS STB253 110° DIGITAL
The idea of digitization of TV functions is not new. The time some companies have started to work on it, silicon technology was not really adequate for the needed computing power so that the most effective solutions were full custom designs. This forced the block-oriented architecture where the digital functions introduced were the one to one replacement of an existing analog function. In Figure 2 there is a simplified representation of the general concept.
The natural separation of video and audio resulted in some incompatibilities and duplication of primary functions. The emitting principle is not changed, redundancy is a big handicap, for example the time a SECAM channel is running, the PAL functions are not in operation. New generations of digital TV systems should re-think the whole concept top down before VLSI system partitioning.
In today’s state-of-the-art solution one can recognize all the basic functions of the analog TV set with, however, a modularity in the concept, permitting additional features becomes possible, some special digital possibilities are exploited, e.g. storage and filtering techniques to improve signal reproduction (adaptive filtering, 100 Hz technology), to integrate special functions (picture-in-picture, zoom, still picture) or to receive digital broadcasting standards (MAC, NICAM). The Figure 3 shows the ITT Semiconductors solution which was the first on the market in 1983 !! !!
Fig.3: The DIGIT2000 TV receiver block diagram
Description:
This invention relates generally to digital television receivers and, particularly, to digital television receivers arranged for economical interfacing with a plurality of auxiliary devices.
With the proliferation of low cost microprocessors and microprocessor controlled devices, television (TV) receivers are being designed to utilize digitized signals and controls. There are many advantages associated with digital TV receivers, including uniformity of product, precise control of signal parameters and operating conditions, elimination of mechanical switches and a potential for reliability that has been heretofore unknown. Digital television receivers include a high speed communication bus for interconnecting a central control unit microprocessor (CCU) with various TV function modules for processing a TV signal. These modules include a deflection processing unit (DPU), a video processing unit (VPU), an automatic phase control (APC), a video codec unit (VCU), an audio analog to digital converter (ADC) and an audio processing unit (APU). The CCU has associated with it a non-volatile memory, a hardware-generated clock signal source and a suitable interface circuit for enabling the CCU to control processing of the TV signal throughout the various TV function modules. The received TV signal is in analog form and suitable analog to digital (A/D) converters and digital to analog (D/A) converters are provided for converting the digital and analog signals for signal processing and for reconverting them after processing for driving a cathode ray tube (CRT) and suitable speakers. The CCU microprocessor is heavily burdened because of the high speed timing required to control the various TV function modules.
To
further complicate matters, modern TV receivers are increasingly
being used with auxiliary devices for other than simple processing of
TV signals. For example, the video cassette recorder (VCR) has enabled
so-called "time-shifting" of program material by recording TV signals
for later, more convenient viewing. The VCR is also extensively used
with prerecorded material and with programs produced by users having
access to a video camera. Other auxiliary devices providing features
such as "Space Phone" whereby the user is enabled to make and receive
telephone calls through his TV receiver, are desirable options.
Additionally, a source selector auxiliary device enables a host of
different signal sources, such as cable, over-the-air antenna, video
disk, video games, etc. to be connected for use with the signal
processing circuitry of the TV. In addition, all of these many
auxiliary devices are preferably controllable from a remote position. A
great deal of flexibility is available since each of the above
auxiliary devices includes a microprocessor for internally controlling
functioning of the device.In the digital TV system described, the CCU microprocessor and the microprocessors in the auxiliary devices may be conventionally arranged to communicate over the main communication bus. Such a system would entail a specialized microprocessor with a hardware-generated clock signal in each auxiliary device in order to communicate at the high speeds used on the main communication bus. A specialized microprocessor, that is, one that is hardware configured, is significantly more expensive than an off-the-shelf microprocessor. Also, the auxiliary devices may not be required, or even desired, by all users and their low volume production cost becomes very important. It would therefore be desirable to provide a digital TV in which such auxiliary devices utilized off-the-shelf microprocessors for their control.
A digital TV system includes a CCU that is interconnected by a three-wire, high speed bus to a plurality of TV signal function modules for controlling operation thereof by means of a high speed hardware generated clock signal. A software generated clock signal in the CCU is supplied on a low speed two-wire auxiliary device bus which is connected to microprocessors in a plurality of auxiliary devices for performing functions ancillary to TV signal processing. The microprocessor in each auxiliary device is an off-the-shelf type that does not require any special hardware because the timing on the auxiliary device bus is sufficiently slow to enable software monitoring of the line and data transfer.
As
mentioned, the three-wire IM bus 21 is a high speed bidirectional bus
in which CCU 20 functions as the master and all of the interconnected
TV signal processing function modules are slaves that communicate
with the CCU in accordance with the protocol established for the
system. CCU 20 is also indicated as including a software generated
clock which supplies a two-wire auxiliary device bus 50. Two-wire bus
50 includes a clock lead 51 and a data lead 52 coupled to a plurality
of auxiliary devices. A VCR 54, including an off-the-shelf
microprocessor 55, is coupled to bus 50. A Source Selector 56,
including an off-the-shelf microprocessor 57, is also coupled to bus
50. Source Selector 56 has access to four RF inputs, two baseband
video and audio inputs and one separate baseband audio input. It will
be appreciated that Source Selector 56 may have a greater or lesser
number of signal sources to which it has access. Source Selector 56
outputs are coupled to VCR 54 and also to tuner 10 and supply, under
control of CCU 20 and keyboard 44, the signal from the signal source
selected by keyboard 44 or IR transmitter 46 for use with the digital
TV. Auxiliary device bus 50 is also coupled to a Space Phone 58 which
includes an off-the-shelf microprocessor 59 and a modem 60 that is
connectable to a conventional telephone terminal.
Two-wire auxiliary device bus 50 is a relatively low speed bus and there is no need for separate hardware generated clock signals to be developed by the auxiliary device microprocessors. As mentioned above, this feature involves a significant savings in the cost and complexity of the auxiliary devices.
The protocol used on the two-wire auxiliary device bus consists of a 16 bit sequence, the first eight bits of which are used for bus address commands for the auxiliary devices. Each auxiliary device may respond to 16 addresses which allows the CCU to write into or read from various storage registers in the devices which are used for control or data storage. Thus, with this low cost system, as many as 16 auxiliary devices may be connected to the auxiliary device bus. The second eight bits of the 16 bit sequence contain data which is either transferred from the CCU to the auxiliary device addressed, or transferred from the auxiliary device to the CCU, based upon the bus address used. Thus, the various bus addresses to which a given auxiliary device will respond determine whether the auxiliary device will receive data from the CCU or send data to the CCU. The clock line timing, generated by software in CCU 20, is slow enough to permit software monitoring of the line and data reception by simple auxiliary device microprocessors that are not equipped with an external interrupt feature. The timing on the auxiliary device bus is made sufficiently fast to avoid too many instruction steps or the need for special registers in CCU 20. In the system described, data is clocked every 82.5 microseconds, thus permitting a 16 bit word to be clocked in 1.32 milliseconds. A pause of 277.5 microseconds between the first 8 bits and the second 8 bits permits the slave auxiliary device to process the bus address data contained in the first 8 bits. This timing fits into the 2 millisecond timing block structure used for the CCU in controlling the DIGIT 2000 digital TV. Two-2 millisecond timing blocks have been established in the CCU, which has a 20 millisecond timing loop divided into ten-2 millisecond timing blocks. Thus, two control words may be sent to an auxiliary device every 20 milliseconds, or a request by the CCU to receive data and the actual receipt of that data may take place in that time period.
Referring to the drawing, a digital TV includes a tuner 10 coupled to an IF/Detector 12 which has a pair of outputs 13 and 14 supplying video and audio signals, respectively. Control signals for tuner 10 are supplied through an interface circuit 16 from a CCU microprocessor 20 which functions as a single master control unit for the system. Microprocessor 20 is interconnected by means of a bidirectional three-wire IM (Intermetal) bus 21 to a DPU 22, a VPU 26, an APC 30, a TTX (teletext processor) 38, an APU 36, an ADC 32 and a non-volatile memory 24. A serial control line 29 interconnects a hardware generated clock 28, VPU 26 and VCU 34. VPU 26 and VCU 34 are also interconnected by a seven wire cable and TTX 38 is interconnected with a DRAM 42. DRAM 42 is a dynamic RAM in which TTX information is stored for display. VCU 34 is supplied with video signal and supplies a digitized 7 bit grey coded video signal to VPU 24 for processing and RGB color signals to a Video Drive 40 which, in turn, supplies a cathode ray tube (not shown). A keyboard 44 is coupled to CCU 20 and includes an IR detector that is responsive to coded IR signals supplied from an IR transmitter (IRX) 46. A resident microprocessor in keyboard 44 decodes the received IR signals and generated control commands and supplies appropriate outputs to CCU 20. The diagram, as described, is substantially identical to that for a "DIGIT" 2000 VLSI Digital TV System developed by ITT Intermetal and published in Edition 1984/85 Order No. 6250-11-2E
Two-wire auxiliary device bus 50 is a relatively low speed bus and there is no need for separate hardware generated clock signals to be developed by the auxiliary device microprocessors. As mentioned above, this feature involves a significant savings in the cost and complexity of the auxiliary devices.
The protocol used on the two-wire auxiliary device bus consists of a 16 bit sequence, the first eight bits of which are used for bus address commands for the auxiliary devices. Each auxiliary device may respond to 16 addresses which allows the CCU to write into or read from various storage registers in the devices which are used for control or data storage. Thus, with this low cost system, as many as 16 auxiliary devices may be connected to the auxiliary device bus. The second eight bits of the 16 bit sequence contain data which is either transferred from the CCU to the auxiliary device addressed, or transferred from the auxiliary device to the CCU, based upon the bus address used. Thus, the various bus addresses to which a given auxiliary device will respond determine whether the auxiliary device will receive data from the CCU or send data to the CCU. The clock line timing, generated by software in CCU 20, is slow enough to permit software monitoring of the line and data reception by simple auxiliary device microprocessors that are not equipped with an external interrupt feature. The timing on the auxiliary device bus is made sufficiently fast to avoid too many instruction steps or the need for special registers in CCU 20. In the system described, data is clocked every 82.5 microseconds, thus permitting a 16 bit word to be clocked in 1.32 milliseconds. A pause of 277.5 microseconds between the first 8 bits and the second 8 bits permits the slave auxiliary device to process the bus address data contained in the first 8 bits. This timing fits into the 2 millisecond timing block structure used for the CCU in controlling the DIGIT 2000 digital TV. Two-2 millisecond timing blocks have been established in the CCU, which has a 20 millisecond timing loop divided into ten-2 millisecond timing blocks. Thus, two control words may be sent to an auxiliary device every 20 milliseconds, or a request by the CCU to receive data and the actual receipt of that data may take place in that time period.
Referring to the drawing, a digital TV includes a tuner 10 coupled to an IF/Detector 12 which has a pair of outputs 13 and 14 supplying video and audio signals, respectively. Control signals for tuner 10 are supplied through an interface circuit 16 from a CCU microprocessor 20 which functions as a single master control unit for the system. Microprocessor 20 is interconnected by means of a bidirectional three-wire IM (Intermetal) bus 21 to a DPU 22, a VPU 26, an APC 30, a TTX (teletext processor) 38, an APU 36, an ADC 32 and a non-volatile memory 24. A serial control line 29 interconnects a hardware generated clock 28, VPU 26 and VCU 34. VPU 26 and VCU 34 are also interconnected by a seven wire cable and TTX 38 is interconnected with a DRAM 42. DRAM 42 is a dynamic RAM in which TTX information is stored for display. VCU 34 is supplied with video signal and supplies a digitized 7 bit grey coded video signal to VPU 24 for processing and RGB color signals to a Video Drive 40 which, in turn, supplies a cathode ray tube (not shown). A keyboard 44 is coupled to CCU 20 and includes an IR detector that is responsive to coded IR signals supplied from an IR transmitter (IRX) 46. A resident microprocessor in keyboard 44 decodes the received IR signals and generated control commands and supplies appropriate outputs to CCU 20. The diagram, as described, is substantially identical to that for a "DIGIT" 2000 VLSI Digital TV System developed by ITT Intermetal and published in Edition 1984/85 Order No. 6250-11-2E
--------------------------
By its very nature, computer technology is digital, while consumer electronics are geared to the analog world. Starts have been made only recently to digitize TV and radio broadcasts at the transmitter end (in form of DAB, DSR, D2-MAC, NICAM etc). The most difficult technical tasks involved in the integration of different media are interface matching and data compression [5].
After this second step in the integration of multimedia signals, an attempt was made towards standardization, namely, the integration of 16 identical high speed processors with communication and programmability concepts comprised in the architecture !
The
concept is to provide generic architectures that can be applied to a
wide variety of systems taking into account that certain functions
have to be optimized and that some other complex algorithms have to be
ported to generic processors.
Compression
methods take advantage of both data redundancy and the non-linearity
of human vision. They exploit correlation in space for still images
and in both space and time for video signals. Compression in space is
known as intra-frame compression, while compression in time is called
inter-frame compression. Generally, methods that achieve high
compression ratios (10:1 to 50:1 for still images and 50:1 to 200:1 for
video) use data approximations which lead to a reconstructed image not
identical to the original.
Basics of current video coding standards
Methods that cause no loss of data do exist, but their compression ratios are lower (no better than 3:1). Such techniques are used only in sensitive applications such as medical imaging. For example, artifacts introduced by a lossy algorithm into a X-ray radiograph may cause an incorrect interpretation and alter the diagnosis of a medical condition. Conversely, for commercial, industrial and consumer applications, lossy algorithms are preferred because they save storage and communication bandwidth.
Lossy algorithms also generally exploit aspects of the human visual system. For instance, the eye is much more receptive to fine detail in the luminance (or brightness) signal than in the chrominance (or color) signals. Consequently, the luminance signal is usually sampled at a higher spatial resolution. Second, the encoded representation of the luminance signal is assigned more bits (a higher dynamic) than are the chrominance signals. The eye is less sensitive to energy with high spatial frequency than with low spatial frequency [7]. Indeed, if the images on a personal computer monitor were formed by an alternating spatial signal of black and white, the human viewer would see a uniform gray instead of the alternating checkerboard pattern. This deficiency is exploited by coding the high frequency coefficients with fewer bits and the low frequency coefficients with more bits.
All these techniques add up to powerful compression algorithms. In many subjective tests, reconstructed images that were encoded with a 20:1 compression ratio are hard to distinguish from the original. Video data, even after compression at ratios of 100:1, can be decompressed with close to analog videotape quality.
Lack of open standards could slow the growth of this technology and its applications. That is why several digital video standards have been proposed:
- JPEG (Joint Photographic Expert Group) for still pictures coding
- H.261 at p times 64 kbit/s was proposed by the CCITT (Consultative Committee on International Telephony and Telegraphy) for teleconferencing
- MPEG-1 (Motion Picture Expert Group) up to 1,5 Mbit/s was proposed for full motion compression on digital storage media
- MPEG-2 was proposed for digital TV compression, the bandwith depends on the chosen level and profile [33].
The needed technologies and methodologies were discussed to emphasize the main parameters influencing the design of VLSI chips for Digital TV Applications like parallelization, electrical constraints, power management, scalability and so on...............................
SALORA 28M91 CHASSIS M CHASSIS M-CHASSIS SALORA STB253 110° DIGITAL Sound Processing Overview Description
The stereo pilot carrier is selectively decoupled from soundchannel TV ll and fed separately to Pin 8 for recognition of the
station operating mode.
The digitized output signals are then available as pulse-rate-
modulated signals PDM I and PDM ll at Pins 10 and 11. Digital
signal processing is then performed completely in APU 2470,
the audio processor IC 3201, to which of course all control
functions controlled via the IM Bus belong. At IC outputs 22 and
23, the processed signals are outputted as pulse-width-
modulated information, so that they can be reconverted into
their original analog form by simple integration (RC element).
The downstream lC’s TDA 2040 H (3401/3501) supply power
amplification for feed to the loudspeakers. A second pair of
analog outputs, Pins 19, 20 ofthe APU, followed by an
integrated amplifier stage, IC 3301 , TDA 2822 M, serves for
connection of earphones or a stereo system via cinch sockets.
This output is likewise controllable, and also suitable for the
listening to the alternative sound channel in dual-channel sound
mode. Pins 21 and 24 at ADC 2310 E are available for coupling
a second dual-channel analog sound source. The signals
concerned come from the SCART socket (PPT), and in sets with
picture-in-picture function are passed via the PIP decoder. In
the opposite direction, the ADC 2310 E supplies at Pins 22 and
23 analog output signals to the SCART socket, e.g. as required
for recording audio signals. All switch-over functions necessary
in this area are executed inside the IC and controlled via the IM
Bus. Detection of the station transmission mode (mono, stereo,
dual-sound) is performed in the lC’s in exactly the same way as
the corresponding switch-over to the operating mode being
transmitted. A muting stage in each of the two audio channels
(T 3401 and T 3501) provides an audio muting function by short-
circuiting the signal input Pin 1 at the power output stage lC’s.
This function can be controlled in two different ways:
1. Via ST 33 at the moment when the set is switched on, in
order to suppress the switch-on click.
2. From Pin 16 of ADC 2310 E, e.g. for noise suppression,
when no TV signal is being received.
ln the first case, the L signal, which is passed as a switch-on
signal from Pin 5 of the CCU via R 1505 to ST 33 of Stereo
Module B, and thus via R 3511 to the base of T 3510, will switch
the transistor to on-state and thus connect the muting line to
12 V. Since in this case the two switching transistors T 4301 and
T 3501 also become conducting, the signal inputs to the audio
output stages are then short-circuited. The second muting
branch from Pin 16 of ADC 2310 E is software-controlled, and
receives the switch-off information from the CCU via the IM
Bus.
SALORA 28M91 CHASSIS M CHASSIS M-CHASSIS SALORA STB253 110° DIGITAL Digital Signal Processing Overview / Description:
The entire video signal processing function for PAL and
SECAM, the videotext decoder and the deflection signal
generator, are located together on one board.
This contains the VCU 2133 as an analog-digital converter for
the video signals, the PVPU 2203 and SPU 2220 for PAL and
SECAM signal processing respectively, the DTI 2222 for
improved reproduction of colour transitions, the TPU 2732 with
page buffer IC 645 for videotext decoding, the deflection
processor DPU 2543 and clock pulse generator MCU 2600 for
generating the working clock pulse for all processors.
After conversion of the FBAS (composite colour) signal selected
into digital form (7-bit gray code), this is passed from output
Pins 2-8 ofthe VCU to SPU 2220, IC 630, to TPU 2732, IC 640
and to DPU 2540.
The further path of the video signal leads first to the SECAM
processor SPU 2220. Here the signal standard is identified and
appropriately switched. In the case of a PAL signal, the input
information is passed unaltered to the video output (Pins 14-20),
and thus on to the input of PVPU 2203, Pins 5-11.
For further processing of the PAL signal, it is first split inside the
IC into luminance and chroma components. The conditioned
luminance signal, extended by 1 bit, appears on the output side
at Pins 32-39, and passes from here to DTI 2222, Pins 6-13.
The chroma signal component is demodulated, decoded and
converted into the colour difference signals in PVPU 2203;
these signals are then also passed (in multiplex mode, together
with picture tube beam current measured data), via output Pins
27-30 to DTI 2222, Pins 17-20.
At this point, the SECAM chroma signal path from SPU 2220,
output Pins 23-26, rejoins the main path. If the input signal is
identified as a SECAM signal in the SPU, the SECAM decoder
is activated, and the decoded signal appears at the output in the
same form as with the PAL processor.
In this case, the luminance signal component is passed through
an integrated delay circuit of 3.7 us, in order to compensate for
the corresponding travel time in the SECAM colour decoder,
and is then fed on the same path as the PAL signal (Pins 14-20,
SPU 2220, PVPU 2203) to DTI 2222, Pins 6-13. All adjustment
functions required for the signals, such as contrast, brightness,
colour intensity, etc. are of course controlled inside the IC via
the IM Bus.
Integrated circuit DTI 2222 serves solely to improve
reproduction of colour transitions on the screen. Since (owing to
the smaller transmission bandwidth with chroma) the signal
leading edges are very flat compared with Y-signals, a clear
improvement in the quality of colour reproduction can be
achieved by electronically increasing the steepness of the
edges. Since the signal manipulation involved increases travel
times in the chroma channel, this must be compensated by a
corresponding delay in the luminance channel. This function is
contained in DTI 2222, so that there are no differences in travel
time at the outputs of this circuit (Pins 27-34 for Y and Pins 22-25 for chroma).
VCU 2133 A (ITT VCU2133 A) (Video Codec Decodec Unit)
DPU 2543 (ITT DPU2543) (Digital Deflection Processor Unit)
PVPU 2203 (ITT PVPU2203) (PAL and Video Processor Unit)
DTI 2222 (ITT DTI2222) (Digital Transient Improvement [Chroma])
TPU 2732 (ITT TPU2732) (Teletext Processor Unit)
MCU 2600 (ITT MCU2600) (Main Clock Unit)
generator, are located together on one board.
This contains the VCU 2133 as an analog-digital converter for
the video signals, the PVPU 2203 and SPU 2220 for PAL and
SECAM signal processing respectively, the DTI 2222 for
improved reproduction of colour transitions, the TPU 2732 with
page buffer IC 645 for videotext decoding, the deflection
processor DPU 2543 and clock pulse generator MCU 2600 for
generating the working clock pulse for all processors.
After conversion of the FBAS (composite colour) signal selected
into digital form (7-bit gray code), this is passed from output
Pins 2-8 ofthe VCU to SPU 2220, IC 630, to TPU 2732, IC 640
and to DPU 2540.
The further path of the video signal leads first to the SECAM
processor SPU 2220. Here the signal standard is identified and
appropriately switched. In the case of a PAL signal, the input
information is passed unaltered to the video output (Pins 14-20),
and thus on to the input of PVPU 2203, Pins 5-11.
For further processing of the PAL signal, it is first split inside the
IC into luminance and chroma components. The conditioned
luminance signal, extended by 1 bit, appears on the output side
at Pins 32-39, and passes from here to DTI 2222, Pins 6-13.
The chroma signal component is demodulated, decoded and
converted into the colour difference signals in PVPU 2203;
these signals are then also passed (in multiplex mode, together
with picture tube beam current measured data), via output Pins
27-30 to DTI 2222, Pins 17-20.
At this point, the SECAM chroma signal path from SPU 2220,
output Pins 23-26, rejoins the main path. If the input signal is
identified as a SECAM signal in the SPU, the SECAM decoder
is activated, and the decoded signal appears at the output in the
same form as with the PAL processor.
In this case, the luminance signal component is passed through
an integrated delay circuit of 3.7 us, in order to compensate for
the corresponding travel time in the SECAM colour decoder,
and is then fed on the same path as the PAL signal (Pins 14-20,
SPU 2220, PVPU 2203) to DTI 2222, Pins 6-13. All adjustment
functions required for the signals, such as contrast, brightness,
colour intensity, etc. are of course controlled inside the IC via
the IM Bus.
Integrated circuit DTI 2222 serves solely to improve
reproduction of colour transitions on the screen. Since (owing to
the smaller transmission bandwidth with chroma) the signal
leading edges are very flat compared with Y-signals, a clear
improvement in the quality of colour reproduction can be
achieved by electronically increasing the steepness of the
edges. Since the signal manipulation involved increases travel
times in the chroma channel, this must be compensated by a
corresponding delay in the luminance channel. This function is
contained in DTI 2222, so that there are no differences in travel
time at the outputs of this circuit (Pins 27-34 for Y and Pins 22-25 for chroma).
DPU 2543 (ITT DPU2543) (Digital Deflection Processor Unit)
PVPU 2203 (ITT PVPU2203) (PAL and Video Processor Unit)
DTI 2222 (ITT DTI2222) (Digital Transient Improvement [Chroma])
TPU 2732 (ITT TPU2732) (Teletext Processor Unit)
MCU 2600 (ITT MCU2600) (Main Clock Unit)
VCU 2133 Video Codec UNIT
High-speed coder/decoder IC for analog-to-digital and di-
gital-to-analog conversion of the video signal in digital TV
receivers based on the DIGIT 2000 concept. The VCU 2133
is a VLSI circuit in Cl technology, housed in a 40-pin Dil
plastic package. One single silicon chip combines the fol-
lowing functions and circuit details (Fig. 1):
- two input video amplifiers
- one A/D converter for the composite video signal
- the noise inverter
- one D/A converter for the luminance signal
- two D/A converters for the color difference signals
- one RGB matrix for converting the color difference sig-
nals and the luminance signal into RGB signals
- three RGB output amplifiers
- programmable auxiliary circuits for blanking, brightness
adjustment and picture tube alignment
- additional clamped RGB inputs for text and other analog
RGB signals
- programmable beam current limiting
1. Functional Description
The VCU 2133 Video Codec is intended for converting the
analog composite video signal from the video demodulator
into a digital signal. The latter is further processed
digitally
in the VPU 2203 Video Processor and in the DPU 2553 De-
flection Processor. After processing in the VPU 2203 (color
demodulation, PAL compensation, etc.), the VPU‘s digital
output signals (luminance and color difference) are recon-
verted into analog signals in the VCU 2133. From these an-
alog signals are derived the RGB signals by means of the
RGB matrix, and, after amplification in the integrated RGB
amplifiers, the RGB signals drive the RGB output amplifiers
of the color T\/ set.
For TV receivers using the NTSC standard the VPU 2203
may be replaced by the CVPU 2233 Comb Filter Video Pro-
cessor which is pin-compatible with the VPU 2203, but of-
fers better video performance. In the case of SECAM, the
SPU 2220 SECAM Chroma Processor must be connected
in parallel to the VPU 2203 for chroma processing, while
the luma processing remains inthe VPU 2203.
In a more sophisticated CTV receiver according to the Dl-
GIT 2000 concept, after the VPU Video Processor may be
placed the DTI 2223 Digital Transient Improvement Proces-
sor which serves for sharpening color transients on the
screen. The output signals of the DTI are fed to the VCU’s
luma and chroma inputs. To achieve the desired transient
improvement, the R-Y and B-Y D/A converters of the VCU
must be stopped for a certain time which is done by the
hold pulse supplied by the DTI and fed to the Reset pin 23
of the VCU. The pulse detector following this pin seperates
the (capacitively-coupled) hold pulse from the reset signal.
In addition, the VCU 2133 carries out the functions:
- brightness adjustment
- automatic CRT spot-cutoff control (black level)
- white balance control and beam current limiting
Further, the VCU 2133 offers direct inputs for text or other
analog RGB signals including adjustment of brightness and
contrast for these signals.
The RGB matrix and RGB amplifier circuits integrated in
the VCU 2133 are analog. The CRT spot-cutoff control is
carried out via the RGB amplifiers’ bias, and the white bal-
ance control is accomplished by varying the gain of these
amplifiers. The VCU 2133 is clocked by a 17.7 or 14.3 MHz
clock signal supplied by the MCU 2632 Clock Generator IC.
1.1. The A/D Converter with Input Amplifiers and Bit
EnlargementThe video signal is input to the VCU 2133 via pins 35 and 37
which are intended for normal TV video signal (pin 35) and
for VCR or SCART video signal (pin 37) respectively. The
video amplifier whose action is required, is activated by the
CCU 2030, CCU 2050 or CCU 2070 via the IM bus by soft-
ware. The amplification of both video amplifiers is doubled
during the undelayed horizontal blanking pulse (at pin 36)
in order to obtain a higher digital resolution of the color
synchronization signal (burst). At D 2-MAC reception, the
doubled gain is switched off by means of bit p = 1 (Fig. 8).
The A/D converter is of the flash type, a circuit of 2" com-
parators connected in parallel. This means that the number
of comparators must be doubled if one additional bit is
needed. Thus it is important to have as few bits as possi-
ble. For a slowly varying video signal, 8 bits are required.
ln
order to achieve an 8-bit picture resolution using a 7-bit
converter, a trick is used: during every other line the refer-
ence voltage of the A/D converter is changed by an
amount corresponding to one half of the least significant
bit. ln this procedure, a grey value located between two 7-
bit steps is converted to the next lower value during one
line and to the next higher value during the next line. The
two grey values on the screen are averaged by the viewer’s
eye, thus producing the impression of grey values with
8-bit resolution. Synchronously to the changing reference
voltage of the A/D converter, to the output signal of the Y
D/A converter is added a half-bit step every second line.
The bit enlargement just described must be switched off in
the case of using the D2-MAC standard (q = 1 and r = 1
in Fig. 8). ln the case of using the comb filter CVPU instead
of the VPU, the half-bit adding in the Y D/A converter must
be switched off (r = 1 in Fig. 8).
The A/D converter’s sampling frequency is 17.7 MHZ for
PAL and 14.3 MHz for NTSC, the clock being supplied by
the MCU 2632 Clock Generator IC which is common to all
circuits for the digital T\/ system. The converter’s resolu-
tion is 1/2 LSB of 8 bits. Its output signal is Gray-coded to
eliminate spikes and glitches resulting from different com-
parator speeds or from the coder itself. The output is fed to
the VPU 2203 and to the DPU 2553 in parallel form.
1.2. The Noise Inverter
The digitized composite video signal passes the noise in-
verter circuit before it is put out to the VPU 2203 and to the
DPU 2553. The noise inverter serves for suppressing bright
spots on the screen which can be generated by noise
VCU 2133
pulses, p. ex. produced by ignition sparks of cars etc. The
function of the noise inverter can be seen in Fig. 2. The
maximum white level corresponds with step 126 of the A/D
converter’s output signal (that means a voltage of 7 V at
pin 35). lf, due to an unwanted pulse on the composite
video signal, the voltage reaches 7.5 V (what means step
127 in digital) or more, the signal level is reduced by such
an amount, that a medium grey is obtained on the screen
(about 40 lFiE). The noise inverter circuit can be switched
off by software (address 16 in the VPU 2203, see there).
1.3. The Luminance D/A Converter (Y)
After having been processed in the VPU 2203 (color de-
modulation, PAL compensation, etc.), the different parts of
the digitized video signal are fed back to the VCU 2133 for
further processing to drive the RGB output amplifiers. The
luminance signal (Y) is routed from the VPU’s contrast mul-
tiplier to the Y D/A converter in the VCU 2133 in the form of
a parallel 8-bit signal with a resolution of 1/2 LSB of 9
bits.
This bit range provides a sufficient signal range for contrast
as well as positive and negative overshoot caused by the
peaking filter (see Fig. 3 and Data Sheet VPU 2203).
The luminance D/A converter is designed as an R-2R lad-
der network. lt is clocked with the 17.7 or the 14.3 MHz
clock signal applied to pin 22. The cutoff frequency of the
luminance signal is determined by the clock frequency.
1.4. The D/A Converters for the Color Difference Signals
R-Y and B-Y
ln order to save output pins at the VPU 2203 and input pins
at the VCU 2133 as well as connection lines, the two digital
color difference signals R-Y and B-Y are transferred in time
multiplex operation. This is possible because these signals’
bandwidth is only 1 MHZ and the clock is a 17.7 or 14.3
MHz signal.
The two 8-bit D/A converters R-Y and B-Y are also built as
R-2R ladder networks. They are clocked with ‘A clock fre-
quency, but the clock for the multiplex data transfer is 17.7
or 14.3 MHz. Four times 4 bits are transferred sequentially,
giving a total of 16 bits. A sync signal coordinates the
multi-
plex operations in both the VCU 2133 and the VPU 2203.
Thus, only four lines are needed for 16 bits. Fig. 4 shows
the timing diagram of the data transfer described.
ln a CTV receiver with digital transient improvement (DTI
2223), the R-Y and B-Y D/A converters are stopped by the
hold pulse supplied by the DTI, and their output signal is
kept constant for the duration of the hold pulse. Thereafter,
the output signal jumps to the new value, as described in
the DTl’s data sheet.
Fig. 4:
Timing diagram of the multiplex data transfer of the chroma
channel between VPU 2203, VCU 2133 and SPU 2220
a) main clock signal QSM
b) valid data out of the VCU 2133’s video A/D converter.
AIAD is the delay time of this converter, about 40 ns.
c) valid data out of the VPU 2203.
d) MUX data transfer of the chroma signals from VPU 2203
to VCU 2133, upper line: sync pulse from pin 27 VPU to
pin 21 VCU during sync time in vertical blanking time,
see Fig. 8; lower line: valid data from pins 27 to 30
(VPU) to pins 18 to 21 (VCU)
1.5. The RGB Matrix and the RGB Output Amplifiers
ln the RGB matrix, the signals Y, R-Y and B-Y are dema-
trixed, the reduction coefficients of 0.88 and 0.49 being tak-
en into account. In addition, the matrix is supplied with a
signal produced by an 8-bit D/A converter for setting the
brightness of the picture. The brightness adjustment range
corresponds to 1/2 of the luminance signal range (see Fig.
3). It can be covered in 255 steps. The brightness is set by
commands fed from the CCU 2030, CCU 2050 or CCU 2070
Central Control Unit to the VPU 2203 via the IM bus.
There are available four different matrices: standard PAL,
matrix 2, 3 and 4, the latter for foreign markets. 'The re-
quired matrix must be mask-programmed during produc-
tion. The matrices are shown in Table 1, based on the for-
mulas:
R = r1~(R-Y)+ l'2~(B-Y) +Y
G = Q1-(Ft-Y)+ Q2 - (B-Y) +Y
B = b1-(Ft-Y)+ bg - (B-Y) +Y
The three RGB output amplifiers are impedance converters
having a low output impedance, an output voltage swing of
6 V (p-p), thereof 3 V for the video part and 3 V for bright-
ness and dark signal. The output current is 4 mA. Fig. 5
shows the recommended video output stage configuration.
For the purpose of white-balance control, the amplification
factor of each output amplifier can be varied stepwise in
127 steps (7 bits) by a factor of 1 to 2. Further, the CRT
spot-cutoff control is accomplished via these amplifiers’ bi-
as by adding the output signal of an 8-bit D/A converter to
the intelligence signal. The amplitude of the output signal
corresponds to one half of the luminance range. The eight
bits make it possible to adjust the dark voltage in 0.5 %
steps. By means of this circuit, the factory-set values for
the dark currents can be maintained and aging of the pic-
ture tube compensated.
1.6. The Beam Current and Peak Beam Current Limiter
The principle of this circuitry may be explained by means of
Fig. 6. Both facilities are carried out via pin 34 of the VCU
2133. For beam current limiting and peak beam current li-
miting, contrast and brightness are reduced by reducing
the reference voltages for the D/A converters Y, Ft-Y and
B-Y. At a voltage of more than +4 V at pin 34, contrast and
brightness are not affected. In the range of +4 V to +3 V,
the contrast is continuously reduced. At +3 V, the original
contrast is reduced to a programmable level, which is set
by the bits of address 16 of the VPU as shown in Table 2. A
further decrease of the voltage merely reduces brightness,
the contrast remains unchanged. At 2 V, the brightness is
reduced to zero. At voltages lower than 2 V, the output
goes to ultra black. This is provided for security purposes.
The beam current limiting is sensed at the ground end of
the EHT circuit, where the average value of the beam cur-
rent produces a certain voltage drop across a resistor in-
serted between EHT circuit and ground. The peak beam
current limiting can be provided additionally to avoid
“blooming” of white spots or letters on the screen. For
this, a fast peak current limitation is needed which is
sensed by three sensing transistors inserted between the
RGB amplifiers and the cathodes of the picture tube. One
of these three transistors is shown in Fig. 6. The sum of the
picture tube’s three cathode currents produces a voltage
drop across resistor R1. If this voltage exceeds that gen-
erated by the divider R2, B3 plus the base emitter voltage
of T2, this transistor will be turned on and the voltage at
pin
34 of the VCU 2133 sharply reduced. Time constants for
both beam current limiting and peak beam current limiting
can be set by the capacitors C1 and C2.
1.7. The Blanking Circuit
The blanking circuit coordinates blanking during vertical
and horizontal flyback. During the latter, the VCU 2133's
output amplifiers are switched to “ultra black”. Such
switching is different during vertical flyback, however, be-
cause at this time the measurements for picture tube align-
ment are Carried out. During vertical flyback, only the ca-
thode to be measured is switched to “black” during mea-
suring time, the other two are at ultra black so that only the
dark current of one cathode is measured at the same time.
For measuring the leakage current, all three cathodes are
switched to ultra black.
The sequence described is controlled by three code bits
contained in a train of 72 bits which is transferred from the
VPU 2203 to the VCU 2133 during each vertical blanking in-
terval. This transfer starts with the vertical blanking pulse.
During the transfer all three cathodes of the picture tube
are biased to ultra black. In the same manner, the white-
balance control is done.
The blanking circuit is controlled by two pulse combina-
tions supplied by the DPU 2553 Deflection Processor
(“sandcastle pulses"). Pin 39 of the VCU 2133 receives the
combined vertical blanking and delayed horizontal blanking
pulse from pin 22 of the DPU (Fig. 7 b), and pin 36 of the
VCU gets the combined undelayed horizontal blanking and
color key pulse from pin 19 of the DPU (Fig. 7 a). The two
outputs of the DPU are tristate-controlled, supplying the
output levels max. 0.4 V (low), min. 4.0 V (high), or high-im-
pedance, whereby the signal level in the high-impedance
mode is determined by the VCU’s input configuration, a
voltage divider of 3.6 KS! and 5 KQ between the +5 V sup-
ply and ground, to 2_8 V. The VCU’s input amplifier has two
thresholds of 2.0 V and 3.4 V for detecting the three levels
of the combined pulses. ln this way, two times two pulses
are transferred via only two lines.
1.8. The Circuitry for Picture Tube Alignment
During vertical flyback, a number of measurements are tak-
en and data is exchanged between the VCU 2133, the VPU
2203 and the CCU 2030 or CCU 2050. These measure-
ments deal with picture tube alignment, as white level and
dark current adjustment, and with the photo current sup-
plied by a photo resistor (Fig. 5) which serves for adapting
Fig. 8:
Data sequence during the transfer of test results from the
VPU 2203 to the VCU 2133. Nine Bytes are transferred, in
each case the LSB first. These 9 Bytes, 8 bits each, coin-
cide with the 72 pulses of 4.4 MHz that are transferred dur-
ing vertical flyback from pin 27 of the VPU 2203 to pin 21 of
the VCU 2133 (see Fig. 9).
l and mi beam current limiter range
l<: noise inverter on/off
n: video input switching bit
S: SECAM chroma sync bit; S = 1 means that the chroma
demultiplexer is synchronized every line. The switch-over
time from C0 to demux counter begins with the end of the
undelayed horizontal blanking pulse and remains valid for a
time of 12 Q M clock periods.
6
the contrast of the picture to the light in the room where
the TV set is operated. The circuitry for transferring the
pic-
ture tube alignment data, the sensed beam currents and
the photo current is clocked in compliance with the VPU
2203 by the vertical blanking pulse and the color key pulse.
To carry out the measurements, a quadruple cycle is pro-
vided (see Table 3). The timing of the data transfer during
the vertical flyback is shown in Fig. 9, and Fig. 8 shows the
data sequence during that data transfer.
Ft, G, B: code bits
p=1; no doubled gain in the input amplifier during horizon-
tal blanking (see section 1.1.)
q=1: no changing of the A/D converter’s reference vol-
tage during every other line (see section 1.1.)
r=1: when operating with the DMA D2-MAC decoder or
the CVPU comb filter video processor, the adding of
a step of ‘/2 LSB to the output signal of the Y D/A
converter is switched off (see section 1.1.).
s=1; the blankirig pulse in the analog video output signal
at pins 26 to 28 is switched off, as is required in
stand-alone applications.
1.9. The Additional RGB Inputs
The three additional analog RGB inputs are provided for
inputting text or other analog RGB signals. They are con-
nected to fast voltage-to-current converters whose output
current can be altered in 64 steps (6 bits) for contrast set-
ting between 100 % and 30 %. The three inputs are
clamped to a DC black level which corresponds to the level
of 31 steps in the luminance channel, by means of the color
key pulse. So, the same brightness level is achieved for
normal and for external RGB signals. The output currents
ofthe converters are then fed to the three RGB output am-
plifiers. Switchover to the external video signal is also
fast.
1.10. The Reset Circuit and Pulse Detector
The reset pulse produced by the external reset RC network
in common for the whole DIGIT 2000 system, switches the
RGB outputs to ultra black during the power-on routine of
the TV set. At other times, high level must be applied to the
reset input pin 23.
There is an additional facility with pin 23 which is used only
in conjunction with the DTl 2223 Digital Transient Improve-
ment Processor. The hold pulse produced by the latter
which serves for stopping the R-Y and B-Y D/A converters,
is also fed to pin 23, capacitively-coupled. The pulse detec-
tor responds on positive pulses which exceed the 5 V sup-
ply by about 1 V. The two DACs are stopped as long as the
hold pulse lasts, and supply a constant output signal of the
amplitude at the begin of the hold pulse.
5. Description of the Connections and the Signals
Pins 1, 9, and 25 - Supply Voltage, +5 V
The supply voltage is +5 V. Pins 1 and 25 supply the ana-
log part and must be filtered separately.
Pins 2 to 8 - Outputs V0 to V6
Via these pins the VCU 2133 supplies the digitized video
signal in a parallel 7-bit Gray code to the VPU 2203 and the
DPU 2553. The output configuration is shown in Fig. 16.
Pins 10 to 17 - Inputs L7 to L0
Fig. 17 shows these inputs’ configuration. Via these pins,
the VCU 2133 receives the digital luminance signal from the
VPU 2203 in a paraliel 8-bit code.
Pins 18 to 21 - Inputs C0 to C3
Via these inputs, whose circuitry and data correspond to
those of pins 10 to 17, the VCU 2133 is fed with the digi-
tized color difference signals R-Y and B-Y and with the
control and alignment signals described in section 1.8., in
multiplex operation. Pin 21 is additionally used for the
multi-
plex sync signal.
Pin 22 - QSM Main Clock Input
Via this pin, whose circuitry is shown in Fig. 18, the VCU
2133 is supplied with the clock signal QSM produced by the
MCU 2600 or MCU 2632 Clock Generator IC. The clock fre-
quency is 17.7 MHz for PAL and SECAM and 14.3 MHz for
NTSC. The clock signal must be DC-coupled.
Pin 23 - Reset and Hold Pulse Input (Fig. 19)
Via this pin, the VCU 2133 is supplied with the reset and
hold signals which are supplied by pin 21 of the DTI 2223
Digital Transient Improvement Processor for stopping the
R-Y and B-Y D/A converters, and for Reset.
Pins 24 and 29 - Analog Ground, 0
These pins serve as ground connections for the supply and
for the analog signals (GND pin 24 for RGB).
Pins 26 to 28 - RGB Outputs
These three analog outputs deliver an analog signal suit-
able for driving the RGB output transistors. Their diagram
is shown in Fig. 20. The output voltage swing is 6 V total,
3 V for the black-to-white signal and 3 V for adjusting
the brightness and the black level.
Pins 30 to 32 - Additional Analog Inputs R, G and B
Fig. 21 shows the configuration of these inputs. They serve
to feed analog RGB signals, for example for Teletext or si-
milar applications, and they are clamped during the color
key pulse. At a 1 V input, full brightness is reached. The
bandwidth extends from 0 to 8 MHz.
Pin 33 - Fast Switching Input
This input is connected as shown in Fig. 22. It ser\/es for
fast switchover of the video channel between an internally-
produced video signal and an externally-applied video sig-
nal via pins 30 to 32. With 0 V at pin 33, the RGB outputs
will supply the internal video signal, and at a 1 V input
level,
the RGB outputs are switched to the external video signal.
Bandwidth is 0 to 4 MHz, and input impedance 1 KQ mini-
mum.
Pin 34 - Beam Current Limiter Input
The diagram of pin 34 is shown in Fig. 25. The input voltage
may be between +5 V and 0 V. The input impedance is 100
kQ. The function of pin 34 is described in section 1.6.
Pin 35 - Composite Video Signal Input 1
To fully drive the video A/D converter the following ampli-
tudes are required at pin 35: +5 V = sync pulse top level,
all bits low; +7 V = peak white, all bits high. Fig. 24 shows
the configuration of pin 35.
Pin 36 - Undelayed Horizontal Blanking and Color Key
Pulse Input
The circuitry of this pin is shown in Fig. 23. Pin 36 receives
the combined undelayed horizontal blanking and color key
pulse which are “sandcastled” and are supplied by pin 19
of the DPU 2553 Deflection Processor. During the undelay-
ed horizontal blanking pulse, the input amplifiers’ gain is
doubled, and the bit enlargement circuit is also switched
by this pulse, and the counter for the data transmission
gap started. The color key pulse is used for clamping the
RGB inputs pins 30 to 32.
Pin 37 - Composite Video Signal Input 2
This pin has the same function and properties as pin 35,
except the gain of the input amplifier which is twice the
gain as that of the amplifier at pin 35. This means an input
voltage range of +5 V to +6 V.
Pin 38 - Supply Voltage, +12 V »
The 12 V supply is needed for certain circuit parts to obtain
the required input or output voltage range, as the video in-
put and the RGB outputs (see Figs. 20 and 24).
Pin 39 - Vertical Blanking and Delayed Horizontal Blanking
Input
This pin receives the combined vertical blanking and delay-
ed horizontal blanking. pulse from pin 22 of the DPU 2553
Deflection Processor. Both pulses are “sandcastled” so
that only one connection is needed for the transfer of two
pulses. These two pulses are separated in the input circui-
try of the VCU 2133, and are used for blanking the picture
during vertical and horizontal flyback. Fig. 23 shows the cir-
cuitry of pin 39.
Pin 40 - Digital Ground, O
This pin is used as GND connection in conjunction with the
pins 2 to 8 and 10 to 21 which carry digital signals.
DPU 2553, DPU 2554 Deflection Processors UNIT
Note: lf not otherwise designated, the pin numbers
mentioned refer to the 40-pin Dil package.
1. Introduction
These programmable VLSI circuits in n-channel mOS
technology carry out the deflection functions in digital
colorTV receivers based onthe DiGiT 2000 system and
are also suitable for text and D2~mAC application. The
three types are basically identical, but are modified ac-
cording to the intended application:
DPU 2553
normal-scan horizontal deflection, standard CTV re-
ceivers, also equipped with Teletext and D2-mAC fa-
cilityDPU 2554
double-scan horizontal deflection, for CTV receivers
equipped with double-frequency horizontal deflection
and double-~frequency vertical deflection for improved
picture quality. At power-up, this version starts with
double horizontal frequency.
1.1. General Description
The DPU 2553/54 Deflection Processors contain the fol-
lowing circuit functions on one single silicon chip:
- video clamping
- horizontal and vertical sync separation
~ horizontal synchronization
- normal horizontal deflection
-east-west correction, also for flat-screen picture
tubes
- vertical synchronization
- normal vertical deflection
~ sawtooth generation
-text display mode with increased deflection frequen-
cies (18.7 kHz horizontal and 60 Hz vertical)
- D2-mAC operation mode
and for DPU 2554 only:
- double-scan horizontal deflection
- normal and double-scan vertical deflection
ln this data sheet, all information given for double~scan
mode is available with the DPU 2554 only. Type DPU
2553 starts the horizontal deflection with 15.5 kHz ac-
cording to the normal TV standard, whereas type DPU
2554 starts with 31 kHz according to the double-scan
system.
The following characteristics are programmable:
~ selection ofthe TV standard (PAL, D2-mAC or NTSC)
- selection ofthe deflection standard (Teletext, horizon-
tal and vertical double-scan, and normal scan)
- filter time»constant for horizontal synchronization
- vertical amplitude, S correction, and vertical position
for in-line, flat-screen and Trinitron picture tubes
- east-west parabola, horizontal width, and trapezoidal
correction for in-line, flat-screen and Trinitron picture
tubes
- switchover characteristics between the different syn-
chronization modes
~characteristic of the synchronism detector for PLL
switching and muting
1.2. Environment
Fig. 1-1 showsthe simplified block diagram ofthe video
and deflection section of a digital TV receiver based on
the DIGIT 2000 system. The analog video signal derived
from the video detector is digitized in the VCU 2133,
VCU 2134 or VCU 2136 Video Codec and supplied in a
parallel 7 bit Gray code. This digital video signal is fed to
the video section (PVPU, CVPU, SPU and DmA) and to
the DPU 2553/54 Deflection Processorwhich carries out
all functions required in conjunction with deflection, from
sync separation to the control of the deflection power
stages, as described in this data sheet.
3. Functional Description
3.1. Block Diagram
The DPU 2553 and DPU 2554 Deflection Processors
perform all tasks associated with deflection in TV sets;
- sync separation
- generation and synchronization of the horizontal and
the vertical deflection frequencies
-the various eastevvest corrections
- vertical savvtooth generation including S correction
as described hereafter. The DPU communicates, viathe
bidirectional serial lm bus, with the CCU 2050 or CCU
2070 Central Control Unit and, via this bus, is supplied
with the picture-correction alignment information stored
in the mDA 2062 EEPROM during set production, vvhen
the set is turned on. The DPU is normally clocked with
a trapezoidal 17.734 mHz (PAL or SECAm), or 14.3 mhz
(NTSC) or 20.25 mHz (D2-mAC) clock signal supplied
by the mCU 2600 or mCU 2632 Clock Generator IC.
The functional diagram of the DPU is shovvn in Fig. 3-1.
3.2. The Video Clamping Circuit and the Sync Pulse
Separation Circuit
The digitized composite video signal delivered as a 7»bit
parallel signal by the VCU 2133, VCU 2134 or VCU 2136
Video Codec is first noise-filtered by a 1 mHz digital lovv-
pass filter and, to improve the noise immunity ofthe
clamping circuit, is additionally filtered by a 0.2 mHz low-
pass filter before being routed to the minimum and back
porch level detectors (Fig. 3-3).
The DPU has tvvo different clamping outputs, no. 1 and
No. 2, one of vvhich supplies the required clamping
pulses to the video input of the VCU as shovvn in Fig.
3-1. The following values forthe clamping circuit apply
for Video Amp. l. since the gain of Video Amp. ll istwice
th at of Video Amp l, all clamping and signal levels of Vid-
eo Amp ll are halt those of Video Amp l referred to +5 V.
Afterthe TV set is switched on,thevideo clamping circuit
first of all ensures by means of horizontal-frequency
current pulses from the clamping output of the DPU to
the coupling capacitor of the analog composite video
signal, that the video signal atthe VCU’s input is optimal-
ly biased for the operation range of the A/D converter of
5 to 7 V. For this, the sync top level is digitally measured
and set to a constant level of 5.125 V by these current
pulses. The horizontal and vertical sync pulses are novv
separated by a fixed separation level of 5.250 V so that
the horizontal synchronization can lock to the correct
phase (see section 3.3. and Figs. 3-2 and 3-3).
vvith the color key pulse which is now present in syn-
chronism with the composite video signal, the video
clamping circuit measures the DC voltage level of the
porch and by means of the pulses from pin 21 (or pin4),
sets the DC level ofthe porch at a constant 5.5 V (5.25 V
for Video Amp ll). This level is also the reference black
to Video Processorffeletext Processor, D2-MAC Processor tc.
level for the PVPU 2204 or CvPU 2270 Video Proces-
sors.
When horizontal synchronization is achieved, the slice
level for the sync pulses is set to 50 % of the sync pulse
amplitude by averaging sync top and black level. This
ensures optimum pulse separation, even with small
sync pulse amplitudes (see application notes, section
4).
3.3. Horizontal Synchronization
Two operating modes are provided for in horizontal syn-
chronization. The choice of mode depends on whether
or not the Tv station is transmitting a standard PAL or
NTSC signal, in which there is a fixed ratio between color
subcarrier frequency and horizontal frequency. ln the
first case we speak of “color-locked” operation and in
the second case of “non-color-locked” operation (e.g.
black-and-white programs). Switching between thetwo
modes is performed automatically by the standard sig-
nal detector.
3.3.1. Non-Color-Locked Operation
ln the non»locked mode,which is needed in the situation
where there is no standard fixed ratio between the color
subcarrier frequency and the horizontal frequency ofthe
transmitter, the horizontal frequency is produced by subdemding the clock frequency (1 7.7 mHz for PAL and SECAM, 14.3
mHz for NTSC) in the programmable fre-
quency dmder (Fig. 3-4) until the correct horizontal
frequency is obtained. The correct adjustment of fre-
quency and phase is ensured by phase comparator l.
This determines the frequency and phase deviation by
means of a digital phase comparison between the sepa-
rated horizontal sync pulses and the output signal of the
programmable dmder and corrects the dmder accordingly. For
optimum adjustment of phase iitter, capture
behavior and transient response of the horizontal PLL
circuit, the measured phase deviation is filtered in a digi-
lowpass filter (PLL phase filter). ln the case of non-
OZMH synchronized horizontal PLL, this filter is set to
wideband PLL response with a pull-in range of 1800 Hz. if the
- sync sync PLL circuit is locked, the PLL filter is
automatically switched to narrow-band response by an internal
synchronism detector in order to limit the phase jitter to a
minimum, even in the case of weak and noisy signals.
A calculator circuit in phase comparator , which analyzes the
edges of the horizontal sync pulses, increases
the resolution of the phase measurement from 56 ns at
Fig. 3-3: Principle ofvideo clamping and pulse separa- 17.7
mHz clock frequency to approx. 6 ns, or from 70 ns
NON at 14.3 MHz clock frequency to approx. 2.2 ns.
The various key and gating pulses such as the color key
pulse (tKe(,), the normal-scan (1 H) and double-scan
(2H) horizontal blanking pulse (tAZ(/) and the 1 H hori-
zontal undelayed gating pulse (t/(Z) are derived from the
output signals ofthe programmable dmder and an addi-
tional counter forthe2H signals and the 1 H and 2H skew
data output. These pulses retain a fixed phase position
with respect to the 1 H inputvideo signal andthe double-
scan output video signal from the CvPU 2270 Video Pro-
cessor
Forthe purpose of equalizing phase changes in the hori-
zontal output stage due to switching response toler-
ances or video influence, a second phase control loop
is used which generates the horizontal output pulse at
pin 31 to drivethe horizontal output stage. ln phase com-
parator li (Fig. 3~4), the phase difference between the
output signal of the programmable dmder and the lead-
ing edge (or the center) of the horizontal flyback pulse
(pin 23) is measured by means of a balanced gate delay
line. The deviation from the desired phase difference is
used as an input to an adder. ln this, the information on
the horizontal frequency derived from phase com-
parator l is added to the phase deviation originating form
phase comparator ll. The result of this addition controls
a digital on-chip sinewave generator (about 1 mHz)
which acts as a phase shifter with a phase resolution of
1/128 of one main clock period m_
By means of control loop ll the horizontal output pulse
(pin 31) is shifted such that the horizontal flyback pulse
(pin 23) acquiresthe desired phase position with respect
to the output signal of the programmable dmder which,
in turn, due to phase comparator l, retains a fixed phase
position with respect to the video signal. The horizontal
output pulse itself is generated by dmding the frequency
ofthe 1 mHz sinewave oscillator by a fixed ratio of 64 in
the case of norm al scan and of 32 in the case of double-
scan operation.
3.3.2. Color-Locked Operation
When in the color~locked operating mode, after the
phase position has been set in the non-color-locked
mode, the programmable dmder is set to the standard
dmsion ratio (1135:1 for PAL, 91O:1 for NTSC) and
phase comparator is disconnected so that interfering
pulses and noise cannot influence the horizontal deflec-
tion. Because phase comparator ll is still connected,
phase errors ofthe horizontal output stage are also cor-
rected in the color»locKed operating mode. The stan-
dard signal detector is so designed that it only switches
to color-locked operation when the ratio between color
subcarrier frequency and horizontal frequency deviates
no more than 1O'7 from the standard dmsion ratio. To
ascertain this requires about 8 s (NTSC). Switching off
color-locked operation takes place automatically, in the
_ case of a change of program for example, within approx-
imately 67 ms (e.g. two NTSC fields, 60 Hz).
3.3.3. Skew Data Output and Field Number Informa-
tion
with non-standard input signals, the TPU 2735 or TPU
2740 Teletext Processor produce a phase error vvith re-
spect to the deflection phase.
The DPU generates a digital data stream (skevv data,
pin 7 ofthe DPU), which informs the PSP and TPU on
the amount of phase delay (given in 2.2 ns increments)
used in the DPU for the 1H and 2h output pulse com-
pared With the Fm main clock signal of 17.7 mHz (PAL
or SECAm) or 14.3 mhz (NTSC), see also Figs. 3-6 to
3-8. The skew data is used by the PSP and by the TPU
to adjust the double-scan video signal to the 1 H and 2H
phase of the horizontal deflection to correct these phase
errors.
For the vmC processor the skew data contains three additional
bits for information about frame number, 1 V
sync and 2 V sync start.
3.3.4. Synchronism Detector for PLL and Muting
Signal
To evaluate locking ofthe horizontal PLL and condition
of the signal, the DPU’s HSP high-speed processor
(Fig. 3~1) receives two items of information from the hor-
izontal PLL circuit (see Fig. 3-11).
a) the overall pulsevvidth of the separated sync pulses
during a 6.7 us phase window centered to the horizontal
sync pulse (value A in Fig. 3-11).
b) the overall pulsevvidth of the separated sync pulse
during one horizontal line but outside the phase window
(value B in Fig. 3-11).
Based on a) and b) and using the selectable coefficients
KS1 and KS2 and a digital lovi/pass filter, the HSP pro-
cessor evaluates an 8-bit item of information “SD” (see
Fig. 3-12). By means of a comparator and a selectable
level SLP, the switching threshold for the PLL signal
“UN” is generated. UN indicates Whether the PLL is in
the synchronous or in the asynchronous state.
To produce a muting signal in the CCU, the data SD can
be read by the CCU. The range ot SD extends from O
(asynchronous) to +127 (synchronous). Typical values
torthe comparator levels and their hysteresis B1 = 30/20
and for muting 40/30 (see also HSP Bam address Table
5-6).
DPU 2553, DPU 2554
3.4. Start Oscillator and Protection Circuit
To protect the horizontal output stage of the TV set dur-
ing changing the standard and for using the DPU as a
low power start oscillator, an additional oscillator is pro-
vided on-chip (Fig. 3-4), with the output connected to
pin 31. This oscillator is controlled by a 4 mHz signalin-
dependent trom the Fm main clock produced by the
MCU 2600 or mCU 2632 Clock Generator IC and is pow-
ered by a separate supply connected to pin 35. Thefunc-
tion ofthis circuitry depends on the external standard se-
lection input pin 33 and on the start oscillator select input
pin 36, as described in Table 3-3. Using the protection
circuit as a start oscillator, the following operation modes
are available (see Table 3-3).
With pin 33 open-circuit, pin 36 at high potential (con-
nected to pin 35) and a 4 mHz clock applied to pin 34,
the protection circuit acts as a start oscillator. This pro-
duces a constant-frequency horizontal output pulse of
15.5 kHz in the case of DPU 2553, and of 31 khz in the
case of DPU 2554 while the Beset input pin 5 is at low
potential. The pulsewidth is 30 us with DPU 2553, and
16 us with DPU 2554. main clock at pin 2 or main power
supplies at pins 8, 32 and 40 are not required for this start
oscillator After the main power supply is stabilized and
the main clock generator has started, the reset input pin
5 must be switched to the high state. As long as the start
values from the CCU are invalid, the start oscillator will
continuously supply the output pulses of constant fre-
quency to pin 31 _ By means of the start values given by
the CCU via the lm bus, the register FL must be set to
zero to enable the stan oscillator to be triggered by the
horizontal PLL circuit. After that, the output frequency
and phase are controlled by the horizontal PLL only.
It the external standard selection input pin 33 is con-
nected to ground or to +5 V, the start oscillator is
switched off as soon as it ls in phase with PLL circuit. Pin
33to ground selects PAL or SECAm standard (17.7 mHz
main clock), and pin 33 to +5 V selects NTSC standard
(14.3 MHz main clock). After the main power supplies to
pins 8, 32 and 40 are stabilized, the start oscillator can
be used as a separate horizontal oscillator with a con-
stant frequency of 15.525 khz. For this option, pin 33
must be unconnected. By means ofthe lm bus register
SC the start oscillator can be switched on (SC = 0) or oft
(SC = 1). Setting SC =1 is recommended.
By means of pin 29 (horizontal output polarity selectin-
put and start oscillator pulsewidth select input), the out-
put pulsewidth and polarity ofthe start oscillator and pro-
tection circuit can be hardware-selected. Pin 29 at low
potential gives 30 us for DPU 2553 and 16 us for DPU
2554,with positive output pulses. Pin 29 at high potential
gives 36 us for DPU 2553 and 18 its for DPU 2554, with
negative output pulses. Both apply forthetime period in
which no start values are valid from the CCU. If pin 29
is intended to be in the high state, it must be connected
to pin 35 (standby power). Pin 29 must be connected to
ground or to +5 V in both cases.
Table 3-3: Operation modes ofthe start oscillator and
protection circuit
Operation Mode Pins
33 34 35 36
Horizontal output stage protected not connected 4 mHz Clock at
+5 V at ground
during main clock frequency changing
(for PAL and NTSC)
Horizontal output stage protected not connected 4 MHz Clock +5
V with connected to
and start oscillator function start oscilla- pin 35
(for PAL and NTSC) tor supply
Only start oscillator function with at +5 V 4 mHz Clock +5 V
with connected to
NTSC standard after Beset start oscilla- pin 35
tor supply
Only start oscillator function with at ground 4 mHz Clock +5 V
with connected to
PAL or SECAM standard after Beset start oscilla~ pin 35
5 tor supply
_ with 17.7 mHz clock at ground at ground at +5 V at ground
without protection.
3.5. Blanking and Color Key Pulses
Pin 19 supplies a combination ofthe color key pulse and
the undelayed horizontal blanking pulse in the form of a
three-level pulse as shown in Fig. 3-13. The high level
(4 V min.) and the low level (0.4 V max.) are controlled
by the DPU. During the low time of the undelayed hori-
zontal blanking pulse, pin 19 of the DPU i sin the high--
impedance mode and the output level at pin 19 is set to
2.8 V by the VCU.
At pin 22, the delayed horizontal blanking pulse in com-
bination with the vertical blanking pulse is available as
athree-level pulse as shown in Fig. 3-13. Output pin 22
is in high-impedance mode during the delayed horizon-
tal blanking pulse.
ln double-scan operation mode (DPU 2554), pin 22 sup-
plies the double-scan (2H) horizontal blanking pulse in-
stead ofthe 1H blanking pulse (DPU 2553). ln text dis-
play mode with increased deflection frequencies (see
section 1.), pin 22 ofthe respective DPU (DPU 2553, as
defined by register ZN) delivers the horizontal blanking
pulse with 18.7 kHz and the vertical blanking pulse with
60 Hz according to the display. At pin 24 the undelayed
horizontal blanking pulse is output.
normally,pin3suppliesthe samevertical blanking pulse
as pin 22. However, with“DVS” = 1, pin 3 will be in the
single-scan mode also with double-scan operation of
the system. The pulsewidth of the single-scan vertical
blanking pulse at pin 3 will be the same as.that of the
double-scan vertical blanking pulse at pin 22. The out-
put pulse of pin 3 is only valid if the COU register “VBE”
is set to 1 . The default value is set to 0 (high-impedance
state of pin 3).
Fig. 3-13: Shape of the output pulses at pins 19 and 22
*) The output level is externally defined
3.6. Output for Switching the Horizontal Power
Stage Between 15.6 kHz (PAL/NTSC) and 18 kHz
(Text Display)
This output (pin 37) is designed as a tristate output. High
levels (4 V mln.) and low levels (0.4 V max.) are con-
trolled bythe DPU. During high-impedance state an ex-
ternal resistor network defines the output level,
For changing the horizontal frequency from 15 kHz to
18 kHz, the following sequence of output levels is
derived at pin 37 (see Fig. 3-14).
After register ZN is set from ZN = 2 (15 kHz) to ZN = 0
(18 kHz) by the CCU, pin 37 is switched from High level
to high-impedance state synchronously with the fre-
quency change at pin 31. Following a delay of 20ms, pin
37 is set to Low level and remains in this state forthetime
the horizontal frequency remains 18 kHz (with ZN == 0).
This 20 ms delay is required for switching-over the hori-
zontal power stage.
To change the horizontal frequency in the opposite di-
rection, from 18 kHz to 15.6 kHz, the sequence de-
scribed is reversed.
3.7. Text Display Mode with Increased Deflection
Frequencies
As already mentioned, the DPU 2553 provides the fea-
ture of increased deflection frequencies for text display
for improved picture quality in this mode of operation. To
achieve this, the processor acting as deflection proces-
sor has its register Zn set to 0. The horizontal output fre-
quency at pin 31 is then switched to a frequency of
18746.802 Hz which is generated by dmding the Fm
main clock frequency by 946 i 46. The horizontal PLL is
then able to synchronize to an external composite sync
signal offH = 18.746 kHzi 46. The horizontal PLL isthen
able to synchronizeto an external composite sync signal
of fH = 18.746 kHzi 5 % and f\, = 60 Hz i 10 % and can
be set to an independent horizontal and vertical sync
generator by setting register VE = 1 and register VB = 0.
That means a constant dmder of 946 for horizontal fre-
quency and constant 312 lines per frame.
The DPU working in this mode supplies the TPU 2740
Teletext Processor or the respective Viewdata Proces-
sor with the 18.7 kHz horizontal blanking pulses form pin
24 and the 60 Hz vertical blanking pulses form pin 22
(see Fig. 3-8).
To be able to receive and store data from an IF video sig-
nal at the same time, the Teletext or Viewdata Processor
requires horizontal and vertical sync pulses from this IF
signal. Therefore, the second DPU provides video
clamping and sync separation forthe external signal and
supplies the horizontal sync pulses (pin 24) and the ver-
tical sync pulses (pin 22) to the Teletext or viewdata Pro-
cessor. For this, the second DPU is set to the PAL stan-
dard by register ZN = 2, and the clamping pulses of the
other DPU are disabled by CLD = 1.
To change the output frequency ofthe DPU acting as de-
flection processor from 18.7 kHz to 15.6 kHz, the control
switch output pin 37 prepares the horizontal output
stage for 15.6 khz operation (pin 37 is in the high-impe-
dance state) beforethe DPU changesthe horizontal out-
put frequencyto 15.6 kHz, after a minimum delay of one
vertical period. Switching the horizontal deflection fre-
quency from 15.6 kHzto 18.7 kHz is done in the reverse
sequence. Firstly, the horizontaloutput frequency of pin
31 is switched to 1 8.7 khz, and after a delay of one verti-
cal period, pin 37 is set low.
3.8. D2-MAC Operation Mode
When receiving Tv signals having the D2-mAC stan-
dard (direct satellite reception), register ZN is set to 3.
The programmable dmder is set to a dmsion ratio of
1296 i48 to generate a horizontal frequency of 15.625
khz with the clock rate of 20.25 mHz used in the
D2-mAC standard. ln this operation mode, pin 6 acts as
input forthe composite sync signal supplied by the DmA
2271 D2-mAC Decoder. The DPU is synchronized to
this sync signal, and after locking-in (status register
UN = 0), the CCU switches the DPU to a clock-locked
mode between clock signal and horizontal frequency
(fm main
clock by 1024, during the vertical sync signal separated
from the received video signal. To use an 8-bit register,
the result of the count is dmded by 2 and given to the
DPU status register. ln the CCU, the vertical frequency
can be evaluated using the following equation:
fv I __lL1’_l\
1024- vP- 2
with
fm), = 17.734475 mHz with PAL and SECAm
fq,M =14.31818 mHz with NTSC
rw = 2o_25 MHZ with D2-mAc
VP = status value, read from DPU.
The interlace control output pin 39 supplies a 25 Hz (for
PAL and SECAm) or 80 Hz (for NTSC) signal for control-
ling an external interlace-off switch, which is required
with A.C.-coupled vertical output stages, becausethese
are not able to handle the internal interlace-off proce-
dure using register “ZS”.
For operation with the vmC Processor the DPU 2554
hasthree interlace control modes in double vertical scan
mode (DVS = 1). These options can be selected with the
register “IOP” and can be used together with the control
output pin 39 only. This output has to be connected to the
vertical output stage, so that the vertical phase can be
shifted by 16 us (or 32 us with DPU 2553).
SALORA 28M91 CHASSIS M CHASSIS SALORA M-CHASSIS STB253 110° DIGITAL ITT DIGIT2000 CATHODE RAY TUBE (Kinescope) driver with kinescope current sensing circuit:
A television receiver includes a kinescope and a current sensing transistor for conveying amplified video signals to the kinescope, and for providing at a sensing output terminal an output signal related to the magnitude of kinescope current conducted during given sensing intervals. A clamping circuit clamps the sensing output terminal during normal image intervals, and unclamps the sensing output terminal during the sensing intervals. The clamping circuit facilitates interfacing the sensing transistor with utilization circuits which process the sensed output signal, and assists to maintain a proper operating condition for the sensing transistor.
1. In a video signal processing system including an image reproducing device for displaying video information in response to a video signal applied thereto, apparatus comprising:
a video output driver stage with a video signal input and a video signal output for providing an amplified video signal;
means for conveying said amplified video signal to said image reproducing display device, said conveying means having a sensing output for providing thereat a sensed signal representative of the current conducted by said image reproducing display device;
utilization means responsive to said sensed signal; and
cl
amping
means for selectively clamping said sensing output during normal
image intervals, and for unclamping said sensing output during
intervals when said sensed signal representative of current conducted
by said image reproducing display device is subject to processing by
said utilization means; wherein
said clamping means comprises clamping transistor means with an output first electrode coupled to said sensing output, a second electrode coupled to an operating potential, and an input third electrode coupled to said sensing output, the conduction of said clamping transistor means being controlled in accordance with the magnitude of said sensed signal as received by said third electrode; and
said clamping transistor means is self-keyed to exhibit clamping and non-clamping states in response to said sensed representative signal.
2. Apparatus according to claim 1, wherein:
said video output stage comprises a video amplifier with a video signal input and a video signal output for providing said amplified video signal; and
said conveying means comprises an active current conducting device with an input first terminal for receiving said amplified video signal, an output second terminal for conveying said amplified video signal to said image reproducing display device, and a third terminal for providing said sensed signal.
3. Apparatus according to claim 2, wherein
said active current conducting device is a transistor with a base input for receiving said amplified video signal, an emitter output for providing said amplified video signal to said image reproducing display device, and a collector output for providing said sensed signal.
4. Apparatus according to claim 1, wherein
said first and second electrodes define a main current conduction path of said clamping transistor means.
5. Apparatus according to claim 4, wherein
said clamping means includes resistive means coupled to said sensing output for providing a voltage in accordance with the magnitude of said sensed signal; and
said third electrode of said clamping transistor means is coupled to said resistive means.
6. Apparatus according to claim 1, and further comprising
filter means for bypassing high frequency signal components at said sensing output.
7. In a video signal processing system including an image reproducing device for displaying video information in response to a video signal applied thereto, apparatus comprising:
a video output driver stage coupled to said image reproducing display device for providing an amplified video signal thereto, and having a sensing output for providing thereat a sensed signal representative of the current conducted by said image reproducing display device;
control means responsive to said sensed signal for developing a control signal;
means for coupling said control signal to said image reproducing display device to maintain a desired conduction characteristic of said image reproducing display device; and
clamping means for selectively clamping said sensing output during normal image intervals, and for unclamping said sensing output during intervals when said control means operates to monitor said sensed signal; wherein
High-speed coder/decoder IC for analog-to-digital and di-
gital-to-analog conversion of the video signal in digital TV
receivers based on the DIGIT 2000 concept. The VCU 2133
is a VLSI circuit in Cl technology, housed in a 40-pin Dil
plastic package. One single silicon chip combines the fol-
lowing functions and circuit details (Fig. 1):
- two input video amplifiers
- one A/D converter for the composite video signal
- the noise inverter
- one D/A converter for the luminance signal
- two D/A converters for the color difference signals
- one RGB matrix for converting the color difference sig-
nals and the luminance signal into RGB signals
- three RGB output amplifiers
- programmable auxiliary circuits for blanking, brightness
adjustment and picture tube alignment
- additional clamped RGB inputs for text and other analog
RGB signals
- programmable beam current limiting
1. Functional Description
The VCU 2133 Video Codec is intended for converting the
analog composite video signal from the video demodulator
into a digital signal. The latter is further processed
digitally
in the VPU 2203 Video Processor and in the DPU 2553 De-
flection Processor. After processing in the VPU 2203 (color
demodulation, PAL compensation, etc.), the VPU‘s digital
output signals (luminance and color difference) are recon-
verted into analog signals in the VCU 2133. From these an-
alog signals are derived the RGB signals by means of the
RGB matrix, and, after amplification in the integrated RGB
amplifiers, the RGB signals drive the RGB output amplifiers
of the color T\/ set.
For TV receivers using the NTSC standard the VPU 2203
may be replaced by the CVPU 2233 Comb Filter Video Pro-
cessor which is pin-compatible with the VPU 2203, but of-
fers better video performance. In the case of SECAM, the
SPU 2220 SECAM Chroma Processor must be connected
in parallel to the VPU 2203 for chroma processing, while
the luma processing remains inthe VPU 2203.
In a more sophisticated CTV receiver according to the Dl-
GIT 2000 concept, after the VPU Video Processor may be
placed the DTI 2223 Digital Transient Improvement Proces-
sor which serves for sharpening color transients on the
screen. The output signals of the DTI are fed to the VCU’s
luma and chroma inputs. To achieve the desired transient
improvement, the R-Y and B-Y D/A converters of the VCU
must be stopped for a certain time which is done by the
hold pulse supplied by the DTI and fed to the Reset pin 23
of the VCU. The pulse detector following this pin seperates
the (capacitively-coupled) hold pulse from the reset signal.
In addition, the VCU 2133 carries out the functions:
- brightness adjustment
- automatic CRT spot-cutoff control (black level)
- white balance control and beam current limiting
Further, the VCU 2133 offers direct inputs for text or other
analog RGB signals including adjustment of brightness and
contrast for these signals.
The RGB matrix and RGB amplifier circuits integrated in
the VCU 2133 are analog. The CRT spot-cutoff control is
carried out via the RGB amplifiers’ bias, and the white bal-
ance control is accomplished by varying the gain of these
amplifiers. The VCU 2133 is clocked by a 17.7 or 14.3 MHz
clock signal supplied by the MCU 2632 Clock Generator IC.
1.1. The A/D Converter with Input Amplifiers and Bit
EnlargementThe video signal is input to the VCU 2133 via pins 35 and 37
which are intended for normal TV video signal (pin 35) and
for VCR or SCART video signal (pin 37) respectively. The
video amplifier whose action is required, is activated by the
CCU 2030, CCU 2050 or CCU 2070 via the IM bus by soft-
ware. The amplification of both video amplifiers is doubled
during the undelayed horizontal blanking pulse (at pin 36)
in order to obtain a higher digital resolution of the color
synchronization signal (burst). At D 2-MAC reception, the
doubled gain is switched off by means of bit p = 1 (Fig. 8).
The A/D converter is of the flash type, a circuit of 2" com-
parators connected in parallel. This means that the number
of comparators must be doubled if one additional bit is
needed. Thus it is important to have as few bits as possi-
ble. For a slowly varying video signal, 8 bits are required.
ln
order to achieve an 8-bit picture resolution using a 7-bit
converter, a trick is used: during every other line the refer-
ence voltage of the A/D converter is changed by an
amount corresponding to one half of the least significant
bit. ln this procedure, a grey value located between two 7-
bit steps is converted to the next lower value during one
line and to the next higher value during the next line. The
two grey values on the screen are averaged by the viewer’s
eye, thus producing the impression of grey values with
8-bit resolution. Synchronously to the changing reference
voltage of the A/D converter, to the output signal of the Y
D/A converter is added a half-bit step every second line.
The bit enlargement just described must be switched off in
the case of using the D2-MAC standard (q = 1 and r = 1
in Fig. 8). ln the case of using the comb filter CVPU instead
of the VPU, the half-bit adding in the Y D/A converter must
be switched off (r = 1 in Fig. 8).
The A/D converter’s sampling frequency is 17.7 MHZ for
PAL and 14.3 MHz for NTSC, the clock being supplied by
the MCU 2632 Clock Generator IC which is common to all
circuits for the digital T\/ system. The converter’s resolu-
tion is 1/2 LSB of 8 bits. Its output signal is Gray-coded to
eliminate spikes and glitches resulting from different com-
parator speeds or from the coder itself. The output is fed to
the VPU 2203 and to the DPU 2553 in parallel form.
1.2. The Noise Inverter
The digitized composite video signal passes the noise in-
verter circuit before it is put out to the VPU 2203 and to the
DPU 2553. The noise inverter serves for suppressing bright
spots on the screen which can be generated by noise
VCU 2133
pulses, p. ex. produced by ignition sparks of cars etc. The
function of the noise inverter can be seen in Fig. 2. The
maximum white level corresponds with step 126 of the A/D
converter’s output signal (that means a voltage of 7 V at
pin 35). lf, due to an unwanted pulse on the composite
video signal, the voltage reaches 7.5 V (what means step
127 in digital) or more, the signal level is reduced by such
an amount, that a medium grey is obtained on the screen
(about 40 lFiE). The noise inverter circuit can be switched
off by software (address 16 in the VPU 2203, see there).
1.3. The Luminance D/A Converter (Y)
After having been processed in the VPU 2203 (color de-
modulation, PAL compensation, etc.), the different parts of
the digitized video signal are fed back to the VCU 2133 for
further processing to drive the RGB output amplifiers. The
luminance signal (Y) is routed from the VPU’s contrast mul-
tiplier to the Y D/A converter in the VCU 2133 in the form of
a parallel 8-bit signal with a resolution of 1/2 LSB of 9
bits.
This bit range provides a sufficient signal range for contrast
as well as positive and negative overshoot caused by the
peaking filter (see Fig. 3 and Data Sheet VPU 2203).
The luminance D/A converter is designed as an R-2R lad-
der network. lt is clocked with the 17.7 or the 14.3 MHz
clock signal applied to pin 22. The cutoff frequency of the
luminance signal is determined by the clock frequency.
1.4. The D/A Converters for the Color Difference Signals
R-Y and B-Y
ln order to save output pins at the VPU 2203 and input pins
at the VCU 2133 as well as connection lines, the two digital
color difference signals R-Y and B-Y are transferred in time
multiplex operation. This is possible because these signals’
bandwidth is only 1 MHZ and the clock is a 17.7 or 14.3
MHz signal.
R-2R ladder networks. They are clocked with ‘A clock fre-
quency, but the clock for the multiplex data transfer is 17.7
or 14.3 MHz. Four times 4 bits are transferred sequentially,
giving a total of 16 bits. A sync signal coordinates the
multi-
plex operations in both the VCU 2133 and the VPU 2203.
Thus, only four lines are needed for 16 bits. Fig. 4 shows
the timing diagram of the data transfer described.
ln a CTV receiver with digital transient improvement (DTI
2223), the R-Y and B-Y D/A converters are stopped by the
hold pulse supplied by the DTI, and their output signal is
kept constant for the duration of the hold pulse. Thereafter,
the output signal jumps to the new value, as described in
the DTl’s data sheet.
Fig. 4:
Timing diagram of the multiplex data transfer of the chroma
channel between VPU 2203, VCU 2133 and SPU 2220
a) main clock signal QSM
b) valid data out of the VCU 2133’s video A/D converter.
AIAD is the delay time of this converter, about 40 ns.
c) valid data out of the VPU 2203.
d) MUX data transfer of the chroma signals from VPU 2203
to VCU 2133, upper line: sync pulse from pin 27 VPU to
pin 21 VCU during sync time in vertical blanking time,
see Fig. 8; lower line: valid data from pins 27 to 30
(VPU) to pins 18 to 21 (VCU)
1.5. The RGB Matrix and the RGB Output Amplifiers
ln the RGB matrix, the signals Y, R-Y and B-Y are dema-
trixed, the reduction coefficients of 0.88 and 0.49 being tak-
en into account. In addition, the matrix is supplied with a
signal produced by an 8-bit D/A converter for setting the
brightness of the picture. The brightness adjustment range
corresponds to 1/2 of the luminance signal range (see Fig.
3). It can be covered in 255 steps. The brightness is set by
commands fed from the CCU 2030, CCU 2050 or CCU 2070
Central Control Unit to the VPU 2203 via the IM bus.
There are available four different matrices: standard PAL,
matrix 2, 3 and 4, the latter for foreign markets. 'The re-
quired matrix must be mask-programmed during produc-
tion. The matrices are shown in Table 1, based on the for-
mulas:
R = r1~(R-Y)+ l'2~(B-Y) +Y
G = Q1-(Ft-Y)+ Q2 - (B-Y) +Y
B = b1-(Ft-Y)+ bg - (B-Y) +Y
The three RGB output amplifiers are impedance converters
having a low output impedance, an output voltage swing of
6 V (p-p), thereof 3 V for the video part and 3 V for bright-
ness and dark signal. The output current is 4 mA. Fig. 5
shows the recommended video output stage configuration.
F
or the purpose of white-balance control, the amplificationfactor of each output amplifier can be varied stepwise in
127 steps (7 bits) by a factor of 1 to 2. Further, the CRT
spot-cutoff control is accomplished via these amplifiers’ bi-
as by adding the output signal of an 8-bit D/A converter to
the intelligence signal. The amplitude of the output signal
corresponds to one half of the luminance range. The eight
bits make it possible to adjust the dark voltage in 0.5 %
steps. By means of this circuit, the factory-set values for
the dark currents can be maintained and aging of the pic-
ture tube compensated.
1.6. The Beam Current and Peak Beam Current Limiter
The principle of this circuitry may be explained by means of
Fig. 6. Both facilities are carried out via pin 34 of the VCU
2133. For beam current limiting and peak beam current li-
miting, contrast and brightness are reduced by reducing
the reference voltages for the D/A converters Y, Ft-Y and
B-Y. At a voltage of more than +4 V at pin 34, contrast and
brightness are not affected. In the range of +4 V to +3 V,
the contrast is continuously reduced. At +3 V, the original
contrast is reduced to a programmable level, which is set
by the bits of address 16 of the VPU as shown in Table 2. A
further decrease of the voltage merely reduces brightness,
the contrast remains unchanged. At 2 V, the brightness is
reduced to zero. At voltages lower than 2 V, the output
goes to ultra black. This is provided for security purposes.
The beam current limiting is sensed at the ground end of
the EHT circuit, where the average value of the beam cur-
rent produces a certain voltage drop across a resistor in-
serted between EHT circuit and ground. The peak beam
current limiting can be provided additionally to avoid
“blooming” of white spots or letters on the screen. For
this, a fast peak current limitation is needed which is
sensed by three sensing transistors inserted between the
RGB amplifiers and the cathodes of the picture tube. One
of these three transistors is shown in Fig. 6. The sum of the
picture tube’s three cathode currents produces a voltage
drop across resistor R1. If this voltage exceeds that gen-
erated by the divider R2, B3 plus the base emitter voltage
of T2, this transistor will be turned on and the voltage at
pin
34 of the VCU 2133 sharply reduced. Time constants for
both beam current limiting and peak beam current limiting
can be set by the capacitors C1 and C2.
1.7. The Blanking Circuit
The blanking circuit coordinates blanking during vertical
and horizontal flyback. During the latter, the VCU 2133's
output amplifiers are switched to “ultra black”. Such
switching is different during vertical flyback, however, be-
cause at this time the measurements for picture tube align-
ment are Carried out. During vertical flyback, only the ca-
thode to be measured is switched to “black” during mea-
suring time, the other two are at ultra black so that only the
dark current of one cathode is measured at the same time.
For measuring the leakage current, all three cathodes are
switched to ultra black.
The sequence described is controlled by three code bits
contained in a train of 72 bits which is transferred from the
VPU 2203 to the VCU 2133 during each vertical blanking in-
terval. This transfer starts with the vertical blanking pulse.
During the transfer all three cathodes of the picture tube
are biased to ultra black. In the same manner, the white-
balance control is done.
The blanking circuit is controlled by two pulse combina-
tions supplied by the DPU 2553 Deflection Processor
(“sandcastle pulses"). Pin 39 of the VCU 2133 receives the
combined vertical blanking and delayed horizontal blanking
pulse from pin 22 of the DPU (Fig. 7 b), and pin 36 of the
VCU gets the combined undelayed horizontal blanking and
color key pulse from pin 19 of the DPU (Fig. 7 a). The two
outputs of the DPU are tristate-controlled, supplying the
output levels max. 0.4 V (low), min. 4.0 V (high), or high-im-
pedance, whereby the signal level in the high-impedance
mode is determined by the VCU’s input configuration, a
voltage divider of 3.6 KS! and 5 KQ between the +5 V sup-
ply and ground, to 2_8 V. The VCU’s input amplifier has two
thresholds of 2.0 V and 3.4 V for detecting the three levels
of the combined pulses. ln this way, two times two pulses
are transferred via only two lines.
1.8. The Circuitry for Picture Tube Alignment
During vertical flyback, a number of measurements are tak-
en and data is exchanged between the VCU 2133, the VPU
2203 and the CCU 2030 or CCU 2050. These measure-
ments deal with picture tube alignment, as white level and
dark current adjustment, and with the photo current sup-
plied by a photo resistor (Fig. 5) which serves for adapting
Fig. 8:
Data sequence during the transfer of test results from the
VPU 2203 to the VCU 2133. Nine Bytes are transferred, in
each case the LSB first. These 9 Bytes, 8 bits each, coin-
cide with the 72 pulses of 4.4 MHz that are transferred dur-
ing vertical flyback from pin 27 of the VPU 2203 to pin 21 of
the VCU 2133 (see Fig. 9).
l and mi beam current limiter range
l<: noise inverter on/off
n: video input switching bit
S: SECAM chroma sync bit; S = 1 means that the chroma
demultiplexer is synchronized every line. The switch-over
time from C0 to demux counter begins with the end of the
undelayed horizontal blanking pulse and remains valid for a
time of 12 Q M clock periods.
6
the contrast of the picture to the light in the room where
the TV set is operated. The circuitry for transferring the
pic-
ture tube alignment data, the sensed beam currents and
the photo current is clocked in compliance with the VPU
2203 by the vertical blanking pulse and the color key pulse.
To carry out the measurements, a quadruple cycle is pro-
vided (see Table 3). The timing of the data transfer during
the vertical flyback is shown in Fig. 9, and Fig. 8 shows the
data sequence during that data transfer.
Ft, G, B: code bits
p=1; no doubled gain in the input amplifier during horizon-
tal blanking (see section 1.1.)
q=1: no changing of the A/D converter’s reference vol-
tage during every other line (see section 1.1.)
r=1: when operating with the DMA D2-MAC decoder or
the CVPU comb filter video processor, the adding of
a step of ‘/2 LSB to the output signal of the Y D/A
converter is switched off (see section 1.1.).
s=1; the blankirig pulse in the analog video output signal
at pins 26 to 28 is switched off, as is required in
stand-alone applications.
1.9. The Additional RGB Inputs
The three additional analog RGB inputs are provided for
inputting text or other analog RGB signals. They are con-
nected to fast voltage-to-current converters whose output
current can be altered in 64 steps (6 bits) for contrast set-
ting between 100 % and 30 %. The three inputs are
clamped to a DC black level which corresponds to the level
of 31 steps in the luminance channel, by means of the color
key pulse. So, the same brightness level is achieved for
normal and for external RGB signals. The output currents
ofthe converters are then fed to the three RGB output am-
plifiers. Switchover to the external video signal is also
fast.
1.10. The Reset Circuit and Pulse Detector
The reset pulse produced by the external reset RC network
in common for the whole DIGIT 2000 system, switches the
RGB outputs to ultra black during the power-on routine of
the TV set. At other times, high level must be applied to the
reset input pin 23.
There is an additional facility with pin 23 which is used only
in conjunction with the DTl 2223 Digital Transient Improve-
ment Processor. The hold pulse produced by the latter
which serves for stopping the R-Y and B-Y D/A converters,
is also fed to pin 23, capacitively-coupled. The pulse detec-
tor responds on positive pulses which exceed the 5 V sup-
ply by about 1 V. The two DACs are stopped as long as the
hold pulse lasts, and supply a constant output signal of the
amplitude at the begin of the hold pulse.
Pins 1, 9, and 25 - Supply Voltage, +5 V
The supply voltage is +5 V. Pins 1 and 25 supply the ana-
log part and must be filtered separately.
Pins 2 to 8 - Outputs V0 to V6
Via these pins the VCU 2133 supplies the digitized video
signal in a parallel 7-bit Gray code to the VPU 2203 and the
DPU 2553. The output configuration is shown in Fig. 16.
Pins 10 to 17 - Inputs L7 to L0
Fig. 17 shows these inputs’ configuration. Via these pins,
the VCU 2133 receives the digital luminance signal from the
VPU 2203 in a paraliel 8-bit code.
Pins 18 to 21 - Inputs C0 to C3
Via these inputs, whose circuitry and data correspond to
those of pins 10 to 17, the VCU 2133 is fed with the digi-
tized color difference signals R-Y and B-Y and with the
control and alignment signals described in section 1.8., in
multiplex operation. Pin 21 is additionally used for the
multi-
plex sync signal.
Pin 22 - QSM Main Clock Input
Via this pin, whose circuitry is shown in Fig. 18, the VCU
2133 is supplied with the clock signal QSM produced by the
MCU 2600 or MCU 2632 Clock Generator IC. The clock fre-
quency is 17.7 MHz for PAL and SECAM and 14.3 MHz for
NTSC. The clock signal must be DC-coupled.
Pin 23 - Reset and Hold Pulse Input (Fig. 19)
Via this pin, the VCU 2133 is supplied with the reset and
hold signals which are supplied by pin 21 of the DTI 2223
Digital Transient Improvement Processor for stopping the
R-Y and B-Y D/A converters, and for Reset.
Pins 24 and 29 - Analog Ground, 0
These pins serve as ground connections for the supply and
for the analog signals (GND pin 24 for RGB).
Pins 26 to 28 - RGB Outputs
These three analog outputs deliver an analog signal suit-
able for driving the RGB output transistors. Their diagram
is shown in Fig. 20. The output voltage swing is 6 V total,
3 V for the black-to-white signal and 3 V for adjusting
the brightness and the black level.
Pins 30 to 32 - Additional Analog Inputs R, G and B
Fig. 21 shows the configuration of these inputs. They serve
to feed analog RGB signals, for example for Teletext or si-
milar applications, and they are clamped during the color
key pulse. At a 1 V input, full brightness is reached. The
bandwidth extends from 0 to 8 MHz.
Pin 33 - Fast Switching Input
This input is connected as shown in Fig. 22. It ser\/es for
fast switchover of the video channel between an internally-
produced video signal and an externally-applied video sig-
nal via pins 30 to 32. With 0 V at pin 33, the RGB outputs
will supply the internal video signal, and at a 1 V input
level,
the RGB outputs are switched to the external video signal.
Bandwidth is 0 to 4 MHz, and input impedance 1 KQ mini-
mum.
Pin 34 - Beam Current Limiter Input
The diagram of pin 34 is shown in Fig. 25. The input voltage
may be between +5 V and 0 V. The input impedance is 100
kQ. The function of pin 34 is described in section 1.6.
Pin 35 - Composite Video Signal Input 1
To fully drive the video A/D converter the following ampli-
tudes are required at pin 35: +5 V = sync pulse top level,
all bits low; +7 V = peak white, all bits high. Fig. 24 shows
the configuration of pin 35.
Pin 36 - Undelayed Horizontal Blanking and Color Key
Pulse Input
The circuitry of this pin is shown in Fig. 23. Pin 36 receives
the combined undelayed horizontal blanking and color key
pulse which are “sandcastled” and are supplied by pin 19
of the DPU 2553 Deflection Processor. During the undelay-
ed horizontal blanking pulse, the input amplifiers’ gain is
doubled, and the bit enlargement circuit is also switched
by this pulse, and the counter for the data transmission
gap started. The color key pulse is used for clamping the
RGB inputs pins 30 to 32.
Pin 37 - Composite Video Signal Input 2
This pin has the same function and properties as pin 35,
except the gain of the input amplifier which is twice the
gain as that of the amplifier at pin 35. This means an input
voltage range of +5 V to +6 V.
Pin 38 - Supply Voltage, +12 V »
The 12 V supply is needed for certain circuit parts to obtain
the required input or output voltage range, as the video in-
put and the RGB outputs (see Figs. 20 and 24).
Pin 39 - Vertical Blanking and Delayed Horizontal Blanking
Input
This pin receives the combined vertical blanking and delay-
ed horizontal blanking. pulse from pin 22 of the DPU 2553
Deflection Processor. Both pulses are “sandcastled” so
that only one connection is needed for the transfer of two
pulses. These two pulses are separated in the input circui-
try of the VCU 2133, and are used for blanking the picture
during vertical and horizontal flyback. Fig. 23 shows the cir-
cuitry of pin 39.
Pin 40 - Digital Ground, O
This pin is used as GND connection in conjunction with the
pins 2 to 8 and 10 to 21 which carry digital signals.
Note: lf not otherwise designated, the pin numbers
mentioned refer to the 40-pin Dil package.
1. Introduction
These programmable VLSI circuits in n-channel mOS
technology carry out the deflection functions in digital
colorTV receivers based onthe DiGiT 2000 system and
are also suitable for text and D2~mAC application. The
three types are basically identical, but are modified ac-
cording to the intended application:
DPU 2553
normal-scan horizontal deflection, standard CTV re-
ceivers, also equipped with Teletext and D2-mAC fa-
cilityDPU 2554
double-scan horizontal deflection, for CTV receivers
equipped with double-frequency horizontal deflection
and double-~frequency vertical deflection for improved
picture quality. At power-up, this version starts with
double horizontal frequency.
1.1. General Description
The DPU 2553/54 Deflection Processors contain the fol-
lowing circuit functions on one single silicon chip:
- video clamping
- horizontal and vertical sync separation
~ horizontal synchronization
- normal horizontal deflection
-east-west correction, also for flat-screen picture
tubes
- vertical synchronization
- normal vertical deflection
~ sawtooth generation
-text display mode with increased deflection frequen-
cies (18.7 kHz horizontal and 60 Hz vertical)
- D2-mAC operation mode
and for DPU 2554 only:
- double-scan horizontal deflection
- normal and double-scan vertical deflection
ln this data sheet, all information given for double~scan
mode is available with the DPU 2554 only. Type DPU
2553 starts the horizontal deflection with 15.5 kHz ac-
cording to the normal TV standard, whereas type DPU
2554 starts with 31 kHz according to the double-scan
system.
The following characteristics are programmable:
~ selection ofthe TV standard (PAL, D2-mAC or NTSC)
- selection ofthe deflection standard (Teletext, horizon-
tal and vertical double-scan, and normal scan)
- filter time»constant for horizontal synchronization
- vertical amplitude, S correction, and vertical position
for in-line, flat-screen and Trinitron picture tubes
- east-west parabola, horizontal width, and trapezoidal
correction for in-line, flat-screen and Trinitron picture
tubes
- switchover characteristics between the different syn-
chronization modes
~characteristic of the synchronism detector for PLL
switching and muting
1.2. Environment
Fig. 1-1 showsthe simplified block diagram ofthe video
and deflection section of a digital TV receiver based on
the DIGIT 2000 system. The analog video signal derived
from the video detector is digitized in the VCU 2133,
VCU 2134 or VCU 2136 Video Codec and supplied in a
parallel 7 bit Gray code. This digital video signal is fed to
the video section (PVPU, CVPU, SPU and DmA) and to
the DPU 2553/54 Deflection Processorwhich carries out
all functions required in conjunction with deflection, from
sync separation to the control of the deflection power
stages, as described in this data sheet.
3. Functional Description
3.1. Block Diagram
The DPU 2553 and DPU 2554 Deflection Processors
perform all tasks associated with deflection in TV sets;
- sync separation
- generation and synchronization of the horizontal and
the vertical deflection frequencies
-the various eastevvest corrections
- vertical savvtooth generation including S correction
as described hereafter. The DPU communicates, viathe
bidirectional serial lm bus, with the CCU 2050 or CCU
2070 Central Control Unit and, via this bus, is supplied
with the picture-correction alignment information stored
in the mDA 2062 EEPROM during set production, vvhen
the set is turned on. The DPU is normally clocked with
a trapezoidal 17.734 mHz (PAL or SECAm), or 14.3 mhz
(NTSC) or 20.25 mHz (D2-mAC) clock signal supplied
by the mCU 2600 or mCU 2632 Clock Generator IC.
The functional diagram of the DPU is shovvn in Fig. 3-1.
3.2. The Video Clamping Circuit and the Sync Pulse
Separation Circuit
The digitized composite video signal delivered as a 7»bit
parallel signal by the VCU 2133, VCU 2134 or VCU 2136
Video Codec is first noise-filtered by a 1 mHz digital lovv-
pass filter and, to improve the noise immunity ofthe
clamping circuit, is additionally filtered by a 0.2 mHz low-
pass filter before being routed to the minimum and back
porch level detectors (Fig. 3-3).
The DPU has tvvo different clamping outputs, no. 1 and
No. 2, one of vvhich supplies the required clamping
pulses to the video input of the VCU as shovvn in Fig.
3-1. The following values forthe clamping circuit apply
for Video Amp. l. since the gain of Video Amp. ll istwice
th at of Video Amp l, all clamping and signal levels of Vid-
eo Amp ll are halt those of Video Amp l referred to +5 V.
Afterthe TV set is switched on,thevideo clamping circuit
first of all ensures by means of horizontal-frequency
current pulses from the clamping output of the DPU to
the coupling capacitor of the analog composite video
signal, that the video signal atthe VCU’s input is optimal-
ly biased for the operation range of the A/D converter of
5 to 7 V. For this, the sync top level is digitally measured
and set to a constant level of 5.125 V by these current
pulses. The horizontal and vertical sync pulses are novv
separated by a fixed separation level of 5.250 V so that
the horizontal synchronization can lock to the correct
phase (see section 3.3. and Figs. 3-2 and 3-3).
vvith the color key pulse which is now present in syn-
chronism with the composite video signal, the video
clamping circuit measures the DC voltage level of the
porch and by means of the pulses from pin 21 (or pin4),
sets the DC level ofthe porch at a constant 5.5 V (5.25 V
for Video Amp ll). This level is also the reference black
to Video Processorffeletext Processor, D2-MAC Processor tc.
level for the PVPU 2204 or CvPU 2270 Video Proces-
sors.
When horizontal synchronization is achieved, the slice
level for the sync pulses is set to 50 % of the sync pulse
amplitude by averaging sync top and black level. This
ensures optimum pulse separation, even with small
sync pulse amplitudes (see application notes, section
4).
3.3. Horizontal Synchronization
Two operating modes are provided for in horizontal syn-
chronization. The choice of mode depends on whether
or not the Tv station is transmitting a standard PAL or
NTSC signal, in which there is a fixed ratio between color
subcarrier frequency and horizontal frequency. ln the
first case we speak of “color-locked” operation and in
the second case of “non-color-locked” operation (e.g.
black-and-white programs). Switching between thetwo
modes is performed automatically by the standard sig-
nal detector.
3.3.1. Non-Color-Locked Operation
ln the non»locked mode,which is needed in the situation
where there is no standard fixed ratio between the color
subcarrier frequency and the horizontal frequency ofthe
transmitter, the horizontal frequency is produced by subdemding the clock frequency (1 7.7 mHz for PAL and SECAM, 14.3
mHz for NTSC) in the programmable fre-
quency dmder (Fig. 3-4) until the correct horizontal
frequency is obtained. The correct adjustment of fre-
quency and phase is ensured by phase comparator l.
This determines the frequency and phase deviation by
means of a digital phase comparison between the sepa-
rated horizontal sync pulses and the output signal of the
programmable dmder and corrects the dmder accordingly. For
optimum adjustment of phase iitter, capture
behavior and transient response of the horizontal PLL
circuit, the measured phase deviation is filtered in a digi-
lowpass filter (PLL phase filter). ln the case of non-
OZMH synchronized horizontal PLL, this filter is set to
wideband PLL response with a pull-in range of 1800 Hz. if the
- sync sync PLL circuit is locked, the PLL filter is
automatically switched to narrow-band response by an internal
synchronism detector in order to limit the phase jitter to a
minimum, even in the case of weak and noisy signals.
A calculator circuit in phase comparator , which analyzes the
edges of the horizontal sync pulses, increases
the resolution of the phase measurement from 56 ns at
Fig. 3-3: Principle ofvideo clamping and pulse separa- 17.7
mHz clock frequency to approx. 6 ns, or from 70 ns
NON at 14.3 MHz clock frequency to approx. 2.2 ns.
The various key and gating pulses such as the color key
pulse (tKe(,), the normal-scan (1 H) and double-scan
(2H) horizontal blanking pulse (tAZ(/) and the 1 H hori-
zontal undelayed gating pulse (t/(Z) are derived from the
output signals ofthe programmable dmder and an addi-
tional counter forthe2H signals and the 1 H and 2H skew
data output. These pulses retain a fixed phase position
with respect to the 1 H inputvideo signal andthe double-
scan output video signal from the CvPU 2270 Video Pro-
cessor
zontal output stage due to switching response toler-
ances or video influence, a second phase control loop
is used which generates the horizontal output pulse at
pin 31 to drivethe horizontal output stage. ln phase com-
parator li (Fig. 3~4), the phase difference between the
output signal of the programmable dmder and the lead-
ing edge (or the center) of the horizontal flyback pulse
(pin 23) is measured by means of a balanced gate delay
line. The deviation from the desired phase difference is
used as an input to an adder. ln this, the information on
the horizontal frequency derived from phase com-
parator l is added to the phase deviation originating form
phase comparator ll. The result of this addition controls
a digital on-chip sinewave generator (about 1 mHz)
which acts as a phase shifter with a phase resolution of
1/128 of one main clock period m_
By means of control loop ll the horizontal output pulse
(pin 31) is shifted such that the horizontal flyback pulse
(pin 23) acquiresthe desired phase position with respect
to the output signal of the programmable dmder which,
in turn, due to phase comparator l, retains a fixed phase
position with respect to the video signal. The horizontal
output pulse itself is generated by dmding the frequency
ofthe 1 mHz sinewave oscillator by a fixed ratio of 64 in
the case of norm al scan and of 32 in the case of double-
scan operation.
3.3.2. Color-Locked Operation
When in the color~locked operating mode, after the
phase position has been set in the non-color-locked
mode, the programmable dmder is set to the standard
dmsion ratio (1135:1 for PAL, 91O:1 for NTSC) and
phase comparator is disconnected so that interfering
pulses and noise cannot influence the horizontal deflec-
tion. Because phase comparator ll is still connected,
phase errors ofthe horizontal output stage are also cor-
rected in the color»locKed operating mode. The stan-
dard signal detector is so designed that it only switches
to color-locked operation when the ratio between color
subcarrier frequency and horizontal frequency deviates
no more than 1O'7 from the standard dmsion ratio. To
ascertain this requires about 8 s (NTSC). Switching off
color-locked operation takes place automatically, in the
_ case of a change of program for example, within approx-
imately 67 ms (e.g. two NTSC fields, 60 Hz).
3.3.3. Skew Data Output and Field Number Informa-tion
with non-standard input signals, the TPU 2735 or TPU
2740 Teletext Processor produce a phase error vvith re-
spect to the deflection phase.
The DPU generates a digital data stream (skevv data,
pin 7 ofthe DPU), which informs the PSP and TPU on
the amount of phase delay (given in 2.2 ns increments)
used in the DPU for the 1H and 2h output pulse com-
pared With the Fm main clock signal of 17.7 mHz (PAL
or SECAm) or 14.3 mhz (NTSC), see also Figs. 3-6 to
3-8. The skew data is used by the PSP and by the TPU
to adjust the double-scan video signal to the 1 H and 2H
phase of the horizontal deflection to correct these phase
errors.
For the vmC processor the skew data contains three additional
bits for information about frame number, 1 V
sync and 2 V sync start.
3.3.4. Synchronism Detector for PLL and Muting
Signal
To evaluate locking ofthe horizontal PLL and condition
of the signal, the DPU’s HSP high-speed processor
(Fig. 3~1) receives two items of information from the hor-
izontal PLL circuit (see Fig. 3-11).
a) the overall pulsevvidth of the separated sync pulses
during a 6.7 us phase window centered to the horizontal
sync pulse (value A in Fig. 3-11).
b) the overall pulsevvidth of the separated sync pulse
during one horizontal line but outside the phase window
(value B in Fig. 3-11).
Based on a) and b) and using the selectable coefficients
KS1 and KS2 and a digital lovi/pass filter, the HSP pro-
cessor evaluates an 8-bit item of information “SD” (see
Fig. 3-12). By means of a comparator and a selectable
level SLP, the switching threshold for the PLL signal
“UN” is generated. UN indicates Whether the PLL is in
the synchronous or in the asynchronous state.
To produce a muting signal in the CCU, the data SD can
be read by the CCU. The range ot SD extends from O
(asynchronous) to +127 (synchronous). Typical values
torthe comparator levels and their hysteresis B1 = 30/20
and for muting 40/30 (see also HSP Bam address Table
5-6).
DPU 2553, DPU 2554
3.4. Start Oscillator and Protection Circuit
To protect the horizontal output stage of the TV set dur-
ing changing the standard and for using the DPU as a
low power start oscillator, an additional oscillator is pro-
vided on-chip (Fig. 3-4), with the output connected to
pin 31. This oscillator is controlled by a 4 mHz signalin-
dependent trom the Fm main clock produced by the
MCU 2600 or mCU 2632 Clock Generator IC and is pow-
ered by a separate supply connected to pin 35. Thefunc-
tion ofthis circuitry depends on the external standard se-
lection input pin 33 and on the start oscillator select input
pin 36, as described in Table 3-3. Using the protection
circuit as a start oscillator, the following operation modes
are available (see Table 3-3).
With pin 33 open-circuit, pin 36 at high potential (con-
nected to pin 35) and a 4 mHz clock applied to pin 34,
the protection circuit acts as a start oscillator. This pro-
duces a constant-frequency horizontal output pulse of
15.5 kHz in the case of DPU 2553, and of 31 khz in the
case of DPU 2554 while the Beset input pin 5 is at low
potential. The pulsewidth is 30 us with DPU 2553, and
16 us with DPU 2554. main clock at pin 2 or main power
supplies at pins 8, 32 and 40 are not required for this start
oscillator After the main power supply is stabilized and
the main clock generator has started, the reset input pin
5 must be switched to the high state. As long as the start
values from the CCU are invalid, the start oscillator will
continuously supply the output pulses of constant fre-
quency to pin 31 _ By means of the start values given by
the CCU via the lm bus, the register FL must be set to
zero to enable the stan oscillator to be triggered by the
horizontal PLL circuit. After that, the output frequency
and phase are controlled by the horizontal PLL only.
It the external standard selection input pin 33 is con-
nected to ground or to +5 V, the start oscillator is
switched off as soon as it ls in phase with PLL circuit. Pin
33to ground selects PAL or SECAm standard (17.7 mHz
main clock), and pin 33 to +5 V selects NTSC standard
(14.3 MHz main clock). After the main power supplies to
pins 8, 32 and 40 are stabilized, the start oscillator can
be used as a separate horizontal oscillator with a con-
stant frequency of 15.525 khz. For this option, pin 33
must be unconnected. By means ofthe lm bus register
SC the start oscillator can be switched on (SC = 0) or oft
(SC = 1). Setting SC =1 is recommended.
By means of pin 29 (horizontal output polarity selectin-
put and start oscillator pulsewidth select input), the out-
put pulsewidth and polarity ofthe start oscillator and pro-
tection circuit can be hardware-selected. Pin 29 at low
potential gives 30 us for DPU 2553 and 16 us for DPU
2554,with positive output pulses. Pin 29 at high potential
gives 36 us for DPU 2553 and 18 its for DPU 2554, with
negative output pulses. Both apply forthetime period in
which no start values are valid from the CCU. If pin 29
is intended to be in the high state, it must be connected
to pin 35 (standby power). Pin 29 must be connected to
ground or to +5 V in both cases.
Table 3-3: Operation modes ofthe start oscillator and
protection circuit
Operation Mode Pins
33 34 35 36
Horizontal output stage protected not connected 4 mHz Clock at
+5 V at ground
during main clock frequency changing
(for PAL and NTSC)
Horizontal output stage protected not connected 4 MHz Clock +5
V with connected to
and start oscillator function start oscilla- pin 35
(for PAL and NTSC) tor supply
Only start oscillator function with at +5 V 4 mHz Clock +5 V
with connected to
NTSC standard after Beset start oscilla- pin 35
tor supply
Only start oscillator function with at ground 4 mHz Clock +5 V
with connected to
PAL or SECAM standard after Beset start oscilla~ pin 35
5 tor supply
_ with 17.7 mHz clock at ground at ground at +5 V at ground
without protection.
3.5. Blanking and Color Key Pulses
Pin 19 supplies a combination ofthe color key pulse and
the undelayed horizontal blanking pulse in the form of a
three-level pulse as shown in Fig. 3-13. The high level
(4 V min.) and the low level (0.4 V max.) are controlled
by the DPU. During the low time of the undelayed hori-
zontal blanking pulse, pin 19 of the DPU i sin the high--
impedance mode and the output level at pin 19 is set to
2.8 V by the VCU.
At pin 22, the delayed horizontal blanking pulse in com-
bination with the vertical blanking pulse is available as
athree-level pulse as shown in Fig. 3-13. Output pin 22
is in high-impedance mode during the delayed horizon-
tal blanking pulse.
ln double-scan operation mode (DPU 2554), pin 22 sup-
plies the double-scan (2H) horizontal blanking pulse in-
stead ofthe 1H blanking pulse (DPU 2553). ln text dis-
play mode with increased deflection frequencies (see
section 1.), pin 22 ofthe respective DPU (DPU 2553, as
defined by register ZN) delivers the horizontal blanking
pulse with 18.7 kHz and the vertical blanking pulse with
60 Hz according to the display. At pin 24 the undelayed
horizontal blanking pulse is output.
normally,pin3suppliesthe samevertical blanking pulse
as pin 22. However, with“DVS” = 1, pin 3 will be in the
single-scan mode also with double-scan operation of
the system. The pulsewidth of the single-scan vertical
blanking pulse at pin 3 will be the same as.that of the
double-scan vertical blanking pulse at pin 22. The out-
put pulse of pin 3 is only valid if the COU register “VBE”
is set to 1 . The default value is set to 0 (high-impedance
state of pin 3).
Fig. 3-13: Shape of the output pulses at pins 19 and 22
*) The output level is externally defined
3.6. Output for Switching the Horizontal Power
Stage Between 15.6 kHz (PAL/NTSC) and 18 kHz
(Text Display)
This output (pin 37) is designed as a tristate output. High
levels (4 V mln.) and low levels (0.4 V max.) are con-
trolled bythe DPU. During high-impedance state an ex-
ternal resistor network defines the output level,
For changing the horizontal frequency from 15 kHz to
18 kHz, the following sequence of output levels is
derived at pin 37 (see Fig. 3-14).
After register ZN is set from ZN = 2 (15 kHz) to ZN = 0
(18 kHz) by the CCU, pin 37 is switched from High level
to high-impedance state synchronously with the fre-
quency change at pin 31. Following a delay of 20ms, pin
37 is set to Low level and remains in this state forthetime
the horizontal frequency remains 18 kHz (with ZN == 0).
This 20 ms delay is required for switching-over the hori-
zontal power stage.
To change the horizontal frequency in the opposite di-
rection, from 18 kHz to 15.6 kHz, the sequence de-
scribed is reversed.
3.7. Text Display Mode with Increased Deflection
Frequencies
As already mentioned, the DPU 2553 provides the fea-
ture of increased deflection frequencies for text display
for improved picture quality in this mode of operation. To
achieve this, the processor acting as deflection proces-
sor has its register Zn set to 0. The horizontal output fre-
quency at pin 31 is then switched to a frequency of
18746.802 Hz which is generated by dmding the Fm
main clock frequency by 946 i 46. The horizontal PLL is
then able to synchronize to an external composite sync
signal offH = 18.746 kHzi 46. The horizontal PLL isthen
able to synchronizeto an external composite sync signal
of fH = 18.746 kHzi 5 % and f\, = 60 Hz i 10 % and can
be set to an independent horizontal and vertical sync
generator by setting register VE = 1 and register VB = 0.
That means a constant dmder of 946 for horizontal fre-
quency and constant 312 lines per frame.
The DPU working in this mode supplies the TPU 2740
Teletext Processor or the respective Viewdata Proces-
sor with the 18.7 kHz horizontal blanking pulses form pin
24 and the 60 Hz vertical blanking pulses form pin 22
(see Fig. 3-8).
To be able to receive and store data from an IF video sig-
nal at the same time, the Teletext or Viewdata Processor
requires horizontal and vertical sync pulses from this IF
signal. Therefore, the second DPU provides video
clamping and sync separation forthe external signal and
supplies the horizontal sync pulses (pin 24) and the ver-
tical sync pulses (pin 22) to the Teletext or viewdata Pro-
cessor. For this, the second DPU is set to the PAL stan-
dard by register ZN = 2, and the clamping pulses of the
other DPU are disabled by CLD = 1.
To change the output frequency ofthe DPU acting as de-
flection processor from 18.7 kHz to 15.6 kHz, the control
switch output pin 37 prepares the horizontal output
stage for 15.6 khz operation (pin 37 is in the high-impe-
dance state) beforethe DPU changesthe horizontal out-
put frequencyto 15.6 kHz, after a minimum delay of one
vertical period. Switching the horizontal deflection fre-
quency from 15.6 kHzto 18.7 kHz is done in the reverse
sequence. Firstly, the horizontaloutput frequency of pin
31 is switched to 1 8.7 khz, and after a delay of one verti-
cal period, pin 37 is set low.
3.8. D2-MAC Operation Mode
When receiving Tv signals having the D2-mAC stan-
dard (direct satellite reception), register ZN is set to 3.
The programmable dmder is set to a dmsion ratio of
1296 i48 to generate a horizontal frequency of 15.625
khz with the clock rate of 20.25 mHz used in the
D2-mAC standard. ln this operation mode, pin 6 acts as
input forthe composite sync signal supplied by the DmA
2271 D2-mAC Decoder. The DPU is synchronized to
this sync signal, and after locking-in (status register
UN = 0), the CCU switches the DPU to a clock-locked
mode between clock signal and horizontal frequency
(fm main
clock by 1024, during the vertical sync signal separated
from the received video signal. To use an 8-bit register,
the result of the count is dmded by 2 and given to the
DPU status register. ln the CCU, the vertical frequency
can be evaluated using the following equation:
fv I __lL1’_l\
1024- vP- 2
with
fm), = 17.734475 mHz with PAL and SECAm
fq,M =14.31818 mHz with NTSC
rw = 2o_25 MHZ with D2-mAc
VP = status value, read from DPU.
The interlace control output pin 39 supplies a 25 Hz (for
PAL and SECAm) or 80 Hz (for NTSC) signal for control-
ling an external interlace-off switch, which is required
with A.C.-coupled vertical output stages, becausethese
are not able to handle the internal interlace-off proce-
dure using register “ZS”.
For operation with the vmC Processor the DPU 2554
hasthree interlace control modes in double vertical scan
mode (DVS = 1). These options can be selected with the
register “IOP” and can be used together with the control
output pin 39 only. This output has to be connected to the
vertical output stage, so that the vertical phase can be
shifted by 16 us (or 32 us with DPU 2553).
SALORA 28M91 CHASSIS M CHASSIS SALORA M-CHASSIS STB253 110° DIGITAL ITT DIGIT2000 CATHODE RAY TUBE (Kinescope) driver with kinescope current sensing circuit:
A television receiver includes a kinescope and a current sensing transistor for conveying amplified video signals to the kinescope, and for providing at a sensing output terminal an output signal related to the magnitude of kinescope current conducted during given sensing intervals. A clamping circuit clamps the sensing output terminal during normal image intervals, and unclamps the sensing output terminal during the sensing intervals. The clamping circuit facilitates interfacing the sensing transistor with utilization circuits which process the sensed output signal, and assists to maintain a proper operating condition for the sensing transistor.
1. In a video signal processing system including an image reproducing device for displaying video information in response to a video signal applied thereto, apparatus comprising:
a video output driver stage with a video signal input and a video signal output for providing an amplified video signal;
means for conveying said amplified video signal to said image reproducing display device, said conveying means having a sensing output for providing thereat a sensed signal representative of the current conducted by said image reproducing display device;
utilization means responsive to said sensed signal; and
cl
amping
means for selectively clamping said sensing output during normal
image intervals, and for unclamping said sensing output during
intervals when said sensed signal representative of current conducted
by said image reproducing display device is subject to processing by
said utilization means; whereinsaid clamping means comprises clamping transistor means with an output first electrode coupled to said sensing output, a second electrode coupled to an operating potential, and an input third electrode coupled to said sensing output, the conduction of said clamping transistor means being controlled in accordance with the magnitude of said sensed signal as received by said third electrode; and
said clamping transistor means is self-keyed to exhibit clamping and non-clamping states in response to said sensed representative signal.
2. Apparatus according to claim 1, wherein:
said video output stage comprises a video amplifier with a video signal input and a video signal output for providing said amplified video signal; and
said conveying means comprises an active current conducting device with an input first terminal for receiving said amplified video signal, an output second terminal for conveying said amplified video signal to said image reproducing display device, and a third terminal for providing said sensed signal.
3. Apparatus according to claim 2, wherein
said active current conducting device is a transistor with a base input for receiving said amplified video signal, an emitter output for providing said amplified video signal to said image reproducing display device, and a collector output for providing said sensed signal.
4. Apparatus according to claim 1, wherein
said first and second electrodes define a main current conduction path of said clamping transistor means.
5. Apparatus according to claim 4, wherein
said clamping means includes resistive means coupled to said sensing output for providing a voltage in accordance with the magnitude of said sensed signal; and
said third electrode of said clamping transistor means is coupled to said resistive means.
6. Apparatus according to claim 1, and further comprising
filter means for bypassing high frequency signal components at said sensing output.
7. In a video signal processing system including an image reproducing device for displaying video information in response to a video signal applied thereto, apparatus comprising:
a video output driver stage coupled to said image reproducing display device for providing an amplified video signal thereto, and having a sensing output for providing thereat a sensed signal representative of the current conducted by said image reproducing display device;
control means responsive to said sensed signal for developing a control signal;
means for coupling said control signal to said image reproducing display device to maintain a desired conduction characteristic of said image reproducing display device; and
clamping means for selectively clamping said sensing output during normal image intervals, and for unclamping said sensing output during intervals when said control means operates to monitor said sensed signal; wherein
said
clamping means comprises clamping transistor means with an output
first electrode coupled to said sensing output, a second electrode
coupled to an operating potential, and an input third electrode coupled
to said sensing output, the conduction of said clamping transistor
means being controlled in accordance with the magnitude of said sensed
signal as received by said third electrode; and
said clamping transistor means is self-keyed to exhibit clamping and non-clamping states in response to said sensed signal.
8. Apparatus according to claim 7, wherein
said control means includes digital signal processing circuits; and
said control means includes an input analog-to-digital signal converter network.
9. In a video signal processing system including an image reproducing device for displaying video information in response to a video signal applied thereto, apparatus comprising:
a video amplifier with a video signal input for receiving video signals, and a video signal output for providing an amplified video signal;
a
signal
coupling transistor with an input first electrode for receiving said
amplified video signal from said video amplifier, an output second
electrode for providing a further amplified video signal to said image
reproducing display device, and a third electrode for providing a
sensed signal representative of the magnitude of the current
conducted by said image reproducing display device;
utilization means responsive to said sensed signal; and
clamping means for selectively clamping said third electrode of said coupling transistor during normal image intervals, and for unclamping said third electrode during interval when said sensed representative signal is subject to processing by said utilization means, said clamping means comprising clamping transistor means with an output first electrode coupled to said third electrode of said signal coupling transistor, a second electrode coupled to an operating potential, and an input third electrode coupled to said third electrode of said signal coupling transistor, the conduction of said clamping transistor means being controlled in accordance with the magnitude of said sensed signal as received by said input third electrode of said clamping transistor means.
10. Apparatus according to claim 9, wherein
said coupling transistor is an emitter follower transistor with a base input electrode, an emitter output electrode, and a collector output electrode corresponding to said third electrode.
said clamping transistor means is self-keyed to exhibit clamping and non-clamping states in response to said sensed signal.
8. Apparatus according to claim 7, wherein
said control means includes digital signal processing circuits; and
said control means includes an input analog-to-digital signal converter network.
9. In a video signal processing system including an image reproducing device for displaying video information in response to a video signal applied thereto, apparatus comprising:
a video amplifier with a video signal input for receiving video signals, and a video signal output for providing an amplified video signal;
a
utilization means responsive to said sensed signal; and
clamping means for selectively clamping said third electrode of said coupling transistor during normal image intervals, and for unclamping said third electrode during interval when said sensed representative signal is subject to processing by said utilization means, said clamping means comprising clamping transistor means with an output first electrode coupled to said third electrode of said signal coupling transistor, a second electrode coupled to an operating potential, and an input third electrode coupled to said third electrode of said signal coupling transistor, the conduction of said clamping transistor means being controlled in accordance with the magnitude of said sensed signal as received by said input third electrode of said clamping transistor means.
10. Apparatus according to claim 9, wherein
said coupling transistor is an emitter follower transistor with a base input electrode, an emitter output electrode, and a collector output electrode corresponding to said third electrode.
Description:
This
invention concerns a video output display driver amplifier for
supplying high level video output signals to an image display device
such as a kinescope in a television receiver. In particular, this
invention concerns a display driver stage associated with a sensing
circuit for providing a signal representative of the magnitude of
current conducted by the kinescope during prescribed intervals.
Video
signal processing and display systems such as television receivers
commonly include a video output display driver stage for supplying a
high level video signal to an intensity control electrode, e.g., a
cathode electrode, of an image display device such as a kinescope.
Television receivers sometimes employ an automatic black current (bias)
control system or an automatic white current (drive) control system
for maintaining desired kinescope operating current levels. Such
control systems typically operate during image blanking intervals, at
which time the kinescope is caused to conduct a black image or a white
image representative current. Such current is sensed by the control
system, which generates a correction signal representing the
difference between the magnitude of the sensed representative current
and a desired current level. The correction signal is applied to
video signal processing circuits for reducing the difference.
Various techniques are known for sensing the magnitude of the black or white kinescope current. One often used approach employs a PNP emitter follower current sensing transistor connected to the kinescope cathode signal coupling path. Such sensing transistor couples video signals to the kinescope via its base-to-emitter junction, and provides at a collector electrode a sensed current representative of the magnitude of the kinescope cathode current. The representative current from the collector electrode of the sensing transistor is conveyed to the control system and processed to develop a suitable correction signal.
In accordance with the principles of the present invention, there is disclosed a kinescope current sensing arrangement wherein a current sensing device is coupled to a kinescope for providing at an output terminal a signal representative of the magnitude of the kinescope current. A clamping circuit clamps the output terminal to a given voltage during normal image trace intervals. During prescribed kinescope current sensing intervals, however, the clamping circuit is inoperative and the sensed signal representative of the kinescope current is developed at the output terminal. The clamping circuit advantageously facilitates interfacing the current sensing device with control circuits for processing the sensed signal, and assists to maintain a proper operating condition for the current sensing device which, in a disclosed embodiment, also conveys video signals to the display device. In accordance with a feature of the invention, the clamping circuit is self-keyed between clamping and non-clamping states in response to the representative signal at the output terminal.
In the drawing:
FIG. 1 shows a circuit diagram of a kinescope driver stage with associated kinescope current sensing and clamping apparatus in accordance with the present invention; and
FIG. 2 depicts, in block diagram form, a portion of a color television receiver incorporating the current sensing and clamping apparatus of FIG. 1.
In FIG. 1, low level color image representative video signals r, g, b are provided by a source 10. The r,g
and b color signals are coupled to similar kinescope driver stages.
Only the red (r) color signal video driver stage is shown in
schematic circuit diagram form.
Red kinescope driver stage 15 comprises a driver amplifier including an input common emitter amplifier transistor 20 arranged in a cascode amplifier configuration with a common base amplifier transistor 21. Red color signal r is coupled to the base input of transistor 20 via a current determining resistor 22. Base bias for transistor 20 is provided by a resistor 24 in association with a source of negative DC voltage (-V). Base bias for transistor 21 is provided from a source of positive DC voltage (+V) through a resistor 25. Resistor 25 in the base circuit of transistor 21 assists to stabilize transistor 21 against oscillation.
The output circuit of driver stage 15 includes a load resistor 27 in the collector output circuit of transistor 21 and across which a high level amplified video signal is developed, and opposite conductivity type emitter follower transistors 30 and 31 with base inputs coupled to the collector of transistor 21. A high level amplified video signal R is developed at the emitter output of follower transistor 30 and is coupled to a cathode electrode of an image reproducing kinescope via a kinescope arc current limiting resistor 33. A resistor 34 in the collector circuit of transistor 31 also serves as a kinescope arc current limiting resistor. Degenerative feedback for driver stage 15 is provided by series resistors 36 and 38, coupled from the emitter of transistor 31 to the base of transistor 20.
A diode 39 connected between the emitters of transistors 30 and 31 as shown is normally reverse biased and therefore nonconductive by the voltage difference across it equalling the sum of the two base-emitter voltage drops of transistors 30 and 31, but is forward biased and therefore rendered conductive under certain conditions in response to positive-going transients at the emitter of transistor 30, corresponding to the output terminal of driver stage 15. The arrangement of transistor 31 prevents the amplifier feedback loop including transistors 20, 21 and 31 and resistors 36 and 38 from being disrupted, thereby preventing feedback transients and signal ringing from occurring. Additional details of the arrangement including transistors 30 and 31 and diode 39 are found in my copending U.S. patent application Ser. No. 758,954 titled "FEEDBACK DISPLAY DRIVER STAGE".
The emitter voltage of transistor 30 follows the voltage developed across load resistor 27, and transistor 30 conducts the kinescope cathode current. Substantially all of the kinescope cathode current flows as collector current of transistor 30, through a kinescope arc current limiting protection resistor 37a, to a clamping network 40. Transistor 30 acts as a current sensing device in conjunction with network 40 as will be explained. Clamping network 40 in this example is self-keyed to exhibit clamping and non-clamping states in response to the magnitude of the current conducted by transistor 30.
Clamping network 40 is common to all three driver stages of the receiver, as will be seen subsequently in connection with FIG. 2, and is coupled to the green and blue signal driver stages via protection resistors 37b and 37c. Network 40 includes clamping transistors 41 and 42 arranged in a Darlington configuration, and series voltage divider resistors 43 and 44 which bias clamp transistors 41 and 42. A high frequency bypass capacitor 46 filters signals in the collector circuit of transistor 30 in a manner to be described below. The series combination of a mode control switch 49 and a scaling resistor 48 is coupled across resistors 43 and 44. A voltage related to the magnitude of kinescope current is developed at a terminal A and, as will be explained with reference to FIG. 2, the voltage at terminal A can be used in conjunction with a feedback control loop to maintain a desired kinescope operating current condition which is otherwise subject to deterioration due to kinescope aging and temperature effects, for example.
Assuming switch 49, the function of which will be explained below, is open, the kinescope cathode current flowing in the collector of transistor 30 is conducted to ground via resistors 43 and 44. When this current causes a voltage drop across resistor 44 to sufficiently forward bias the base-emitter junctions of transistors 41 and 42, transistor 42 will conduct in a linear region, and will clamp terminal A to a voltage VA according to the following expression, where V BE41 and V BE42 are the base-emitter junction voltage drops of transistors 41 and 42: VA=(V BE41 +V BE42 ) (R43+R44)/R44
During
normal image intervals typically there are greater than
approximately 25 microamperes of current conducted by transistor 30,
which is sufficient to render transistors 41 and 42 conductive for
developing clamping voltage VA at terminal A. At other times, as will
be discussed, transistors 41 and 42 are rendered nonconductive
whereby clamping action is inhibited and a (variable) voltage is
developed at node A as a function of the magnitude of the kinescope
cathode current, for processing by succeeding control circuits.
Illustratively, the arrangement of FIG. 1 can be used in connection with digital signal processing and control circuits in a color television receiver employing digital signal processing techniques, as will be seen in FIG. 2. Such control circuits include an input analog-to-digital converter (ADC) for converting analog voltages developed at terminal A to digital form for processing.
When the control circuits are to operate in an automatic kinescope black current (bias) control mode, wherein during image
blanking intervals the kinescope conducts very small cathode
currents on the order of a few microamperes, approximating a kinescope
black image condition, clamp transistors 41 and 42 are rendered
nonconductive because such small currents flowing through resistors 43
and 44 from the collector of transistor 30 are unable to produce a
large enough voltage drop across resistor 44 to forward bias
transistors 41 and 42. Consequently terminal A exhibits voltage
variations, as developed across resistors 43 and 44, related to the
magnitude of kinescope black current. The voltage variations are
processed by the control circuits coupled to terminal A to develop a
correction signal, if necessary, to maintain a desired level of
kinescope black current conduction by feedback action. In this
operating mode switch 49, e.g., a controlled electronic switch, is
maintained in an open position as shown in response to a timing
signal VT developed by the control circuits.
When the control circuits are to operate in an automatic kinescope white current (drive) control mode wherein during image blanking intervals the kinescope conducts much larger currents representing a white image condition, switch 49 closes in response to timing signal VT, thereby shunting resistor 48 across resistors 43 and 44. The value of resistor 48 is chosen relative to the combined values of resistors 43 and 44 so that the larger current conducted via the collector of transistor 30 divides between series resistors 43, 44 and resistor 48 such that the magnitude of current conducted by resistors 43 and 44 is insufficient to produce a large enough voltage drop across resistor 44 to render clamping transistors 43 and 44 conductive. Unclamped terminal A therefore exhibits voltage variations related to the magnitude of kinescope white current, which voltage variations are processed by the control circuits to develop a correction signal as required. As used herein, the expression "white current" refers to a high level of individual red, green or blue color image current, or to combined high level red, green and blue currents associated with a white image.
With
the illustrated configuration of transistors 41 and 42 clamping
voltage VA is relatively low, approximately +2.0 volts. The clamping
voltage could be provided by a Zener diode rather than the disclosed
arrangement of Darlington-connected transistors 41 and 42, but the
disclosed clamping arrangement is preferred because Zener diodes with a
voltage rating less than about 4 volts usually do not exhibit a
predictable Zener threshold voltage characteristic, i.e., the "knee"
transition region of the Zener voltage-vs-current characteristic is
usually not very well defined. In addition, the disclosed transistor
clamp operates with better linearity than a Zener diode clamp and
radiates less radio frequency interference (RFI).
The relatively low clamping voltage is compatible with the analog input voltage requirements of the analog-to-digital converter (ADC) at the input of the control circuits which receive the sensed voltage at terminal A as will be explained in greater detail with respect to FIG. 2. In this example the ADC is intended to process analog voltages of from 0 volts to approximately +2.5 volts, and the clamping voltage assures that excessively high analog voltages are not presented to the ADC during normal video signal intervals.
The relatively low
clamping voltage also assists to prevent transistor 30 from
saturating, which is necessary since transistor 30 is intended to
operate in a linear region. To achieve this result and to maximize the
cathode current conduction capability of transistor 30, the clamping
voltage should be as low as possible to maintain a suitably low bias
voltage at the collector of transistor 30. On the other hand, the
value of arc current limiting resistor 37a should be large enough to
provide adequate arc protection without compromising the objective of
maintaining the collector bias voltage of transistor 30 as low as
possible. Operation of transistor 30 in a saturated state renders
transistor 30 ineffective for its intended purpose of properly
conveying video drive signals to the kinescope cathode, and for
conveying accurate representations of cathode current to clamping
network 40 particularly in the white current control mode when
relatively high cathode current levels are sensed. In addition,
undesirable radio frequency interference (RFI) can be generated by
transistor 30 switching into and out of saturation. Also, when
saturation occurs transistor base storage effects can result in video
image streaking due to the time required for a transistor to come out
of a saturated state.
Thus clamping network 40 advantageously limits the voltage at terminal A to a level tolerable by the analog-to-digital converter at the input of the control circuits coupled to terminal A, and protects the analog-to-digital converter input from damage due to signal overdrive. Network 40 also provides a collector reference bias for transistor 30 to prevent transistor 30 from saturating on large negative-going signal amplitude transitions at its emitter electrode. The clamping voltage level is readily adjusted simply by tailoring the values of resistors 43 and 44.
Capacitor 46 bypasses high frequency video signals to ground to prevent transistor 30 from saturating in response to such signals. Capacitor 46 also serves to smooth out undesirable high frequency variations at terminal A to prevent potentially troublesome signal components such as noise from interfering with the signal processing function of the input analog-to-digital converter of the control circuits, e.g., by smoothing the current sensed during the settling time of the analog-to-digital converter.
The latter noise reducing effect is particularly desirable, for example, when the input ADC of the control circuits coupled to terminal A is of the relatively inexpensive and uncomplicated "iterative approximation" type ADC, compared to a "flash" type ADC. The operation of an iterative ADC, wherein successive approximations are made from the most significant bit to the least significant bit, requires a relatively constant or slowly varying analog signal to be sampled during sampling intervals, uncontaminated by noise and similar effects.
The value of capacitor 46 should not be excessively large because a certain rate of current variation should be permitted at terminal A with respect to kinescope cathode currents being sensed. If the value of capacitor 46 is too small, excessive voltage variations, particularly high frequency video signal variations, will appear at terminal A, increasing the likelihood of transistor 30 saturating. The speed of operation of the clamp circuit itself is restricted by an RC low pass filter effect produced by the base capacitance of transistor 41 and the equivalent resistance of resistors 43 and 44.
FIG.
2 shows a portion of a color television receiver system employing
digital video signal processing techniques. The FIG. 2 system utilizes
kinescope driver amplifiers and a clamping network as disclosed in
FIG. 1, wherein similar elements are identified by the same reference
number. By way of example, the system of FIG. 2 includes a MAA 2100
VCU (Video Codec Unit) corresponding to video signal source 10 of FIG.
1, a MAA 2200 VPU (Video Processor Unit) 50, and a MAAA 2000 CCU
(Central Control Unit) 60. The latter three units are associated with a
digital television signal processing system offered by ITT
Corporation as described in a technical bulletin titled "DIGIT 2000
VLSI DIGITAL TV SYSTEM" published by the Intermetall Semiconductors
subsidiary of ITT Corporation.
In
unit 10, a luminance signal and color difference signals in digital
form are respectively converted to analog form by means of
digital-to-analog converters (DACs) 70 and 71. The analog luminance
signal (Y) and analog color difference signals r-y and b-y are
combined in a matrix amplifier 73 to produce r, g and b color image
representative signals which are processed by preamplifiers 75, 76 and
77, respectively, before being coupled to kinescope driver stages
15, 16 and 17 of the type shown in FIG. 1. A network 78 in unit 10
includes circuits associated with the automatic white current and black
current control functions.
The high level R, G and B color signals from driver stages 15, 16 and 17 are coupled via respective current limiting resistors (i.e., resistor 33) to cathode intensity control electrodes of a color kinescope 80. Currents conducted by the red, green and blue kinescope cathodes are conveyed to network 40 via resistors 37a-37c, for producing at terminal A a voltage representative of kinescope cathode current conducted during measuring intervals, as discussed previously.
VPU unit 50 includes input terminals 15 and 16 coupled to terminal A. Through terminal 15 the VPU receives the analog signal from terminal A and, via an internal multiplex switching network 51, the analog signal is supplied to an analog-to-digital-converter (ADC) 52. Terminal 16 is connected to an internal switching device (corresponding to switch 49 in FIG. 1) which, in conjunction with scaling resistor 48, controls the impedance and therefore the sensitivity at input terminal 15. High sensitivity for black current measurement is obtained with resistor 48 ungrounded by internal switch 49, and low sensitivity for white current measurement is obtained with resistor 48 grounded by internal switch 49.
The digital signal from ADC 52 is coupled to an IM BUS INTERFACE unit 53 which coacts with CCU unit 60and
provides signals to an output data multiplex (MPX) unit 55.
Multiplexed output signal data from unit 55 is conveyed to VCU unit 10,
and particularly to control network 78. Control network 78 provides
output signals for controlling the signal gain of preamplifiers 75,
76 and 77 to achieve a correct white current condition, and also
provides output signals for controlling the DC bias of the
preamplifiers to achieve a correct black current condition.
More specifically, during vertical image blanking intervals the three (red, green, blue) kinescope black currents subject to measurement and the three white currents subject to measurement are developed sequentially, sensed, and coupled to VPU 50 via terminal 15. The sensed values are sequenced, digitized and coupled to IM Bus Interface 53 which organizes the data communication with CCU 60. After being processed by CCU 60, control signals are routed back to interface 53 and from there to data multiplexer 55 which forwards the control signals to VCU 10.
Video
signal processing and display systems such as television receivers
commonly include a video output display driver stage for supplying a
high level video signal to an intensity control electrode, e.g., a
cathode electrode, of an image display device such as a kinescope.
Television receivers sometimes employ an automatic black current (bias)
control system or an automatic white current (drive) control system
for maintaining desired kinescope operating current levels. Such
control systems typically operate during image blanking intervals, at
which time the kinescope is caused to conduct a black image or a white
image representative current. Such current is sensed by the control
system, which generates a correction signal representing the
difference between the magnitude of the sensed representative current
and a desired current level. The correction signal is applied to
video signal processing circuits for reducing the difference.Various techniques are known for sensing the magnitude of the black or white kinescope current. One often used approach employs a PNP emitter follower current sensing transistor connected to the kinescope cathode signal coupling path. Such sensing transistor couples video signals to the kinescope via its base-to-emitter junction, and provides at a collector electrode a sensed current representative of the magnitude of the kinescope cathode current. The representative current from the collector electrode of the sensing transistor is conveyed to the control system and processed to develop a suitable correction signal.
In accordance with the principles of the present invention, there is disclosed a kinescope current sensing arrangement wherein a current sensing device is coupled to a kinescope for providing at an output terminal a signal representative of the magnitude of the kinescope current. A clamping circuit clamps the output terminal to a given voltage during normal image trace intervals. During prescribed kinescope current sensing intervals, however, the clamping circuit is inoperative and the sensed signal representative of the kinescope current is developed at the output terminal. The clamping circuit advantageously facilitates interfacing the current sensing device with control circuits for processing the sensed signal, and assists to maintain a proper operating condition for the current sensing device which, in a disclosed embodiment, also conveys video signals to the display device. In accordance with a feature of the invention, the clamping circuit is self-keyed between clamping and non-clamping states in response to the representative signal at the output terminal.
In the drawing:
FIG. 1 shows a circuit diagram of a kinescope driver stage with associated kinescope current sensing and clamping apparatus in accordance with the present invention; and
FIG. 2 depicts, in block diagram form, a portion of a color television receiver incorporating the current sensing and clamping apparatus of FIG. 1.
In FIG. 1, low level color image representative video signals r, g, b are provided by a source 10. The r,
g
and b color signals are coupled to similar kinescope driver stages.
Only the red (r) color signal video driver stage is shown in
schematic circuit diagram form.Red kinescope driver stage 15 comprises a driver amplifier including an input common emitter amplifier transistor 20 arranged in a cascode amplifier configuration with a common base amplifier transistor 21. Red color signal r is coupled to the base input of transistor 20 via a current determining resistor 22. Base bias for transistor 20 is provided by a resistor 24 in association with a source of negative DC voltage (-V). Base bias for transistor 21 is provided from a source of positive DC voltage (+V) through a resistor 25. Resistor 25 in the base circuit of transistor 21 assists to stabilize transistor 21 against oscillation.
The output circuit of driver stage 15 includes a load resistor 27 in the collector output circuit of transistor 21 and across which a high level amplified video signal is developed, and opposite conductivity type emitter follower transistors 30 and 31 with base inputs coupled to the collector of transistor 21. A high level amplified video signal R is developed at the emitter output of follower transistor 30 and is coupled to a cathode electrode of an image reproducing kinescope via a kinescope arc current limiting resistor 33. A resistor 34 in the collector circuit of transistor 31 also serves as a kinescope arc current limiting resistor. Degenerative feedback for driver stage 15 is provided by series resistors 36 and 38, coupled from the emitter of transistor 31 to the base of transistor 20.
A diode 39 connected between the emitters of transistors 30 and 31 as shown is normally reverse biased and therefore nonconductive by the voltage difference across it equalling the sum of the two base-emitter voltage drops of transistors 30 and 31, but is forward biased and therefore rendered conductive under certain conditions in response to positive-going transients at the emitter of transistor 30, corresponding to the output terminal of driver stage 15. The arrangement of transistor 31 prevents the amplifier feedback loop including transistors 20, 21 and 31 and resistors 36 and 38 from being disrupted, thereby preventing feedback transients and signal ringing from occurring. Additional details of the arrangement including transistors 30 and 31 and diode 39 are found in my copending U.S. patent application Ser. No. 758,954 titled "FEEDBACK DISPLAY DRIVER STAGE".
The emitter voltage of transistor 30 follows the voltage developed across load resistor 27, and transistor 30 conducts the kinescope cathode current. Substantially all of the kinescope cathode current flows as collector current of transistor 30, through a kinescope arc current limiting protection resistor 37a, to a clamping network 40. Transistor 30 acts as a current sensing device in conjunction with network 40 as will be explained. Clamping network 40 in this example is self-keyed to exhibit clamping and non-clamping states in response to the magnitude of the current conducted by transistor 30.
Clamping network 40 is common to all three driver stages of the receiver, as will be seen subsequently in connection with FIG. 2, and is coupled to the green and blue signal driver stages via protection resistors 37b and 37c. Network 40 includes clamping transistors 41 and 42 arranged in a Darlington configuration, and series voltage divider resistors 43 and 44 which bias clamp transistors 41 and 42. A high frequency bypass capacitor 46 filters signals in the collector circuit of transistor 30 in a manner to be described below. The series combination of a mode control switch 49 and a scaling resistor 48 is coupled across resistors 43 and 44. A voltage related to the magnitude of kinescope current is developed at a terminal A and, as will be explained with reference to FIG. 2, the voltage at terminal A can be used in conjunction with a feedback control loop to maintain a desired kinescope operating current condition which is otherwise subject to deterioration due to kinescope aging and temperature effects, for example.
Assuming switch 49, the function of which will be explained below, is open, the kinescope cathode current flowing in the collector of transistor 30 is conducted to ground via resistors 43 and 44. When this current causes a voltage drop across resistor 44 to sufficiently forward bias the base-emitter junctions of transistors 41 and 42, transistor 42 will conduct in a linear region, and will clamp terminal A to a voltage VA according to the following expression, where V BE41 and V BE42 are the base-emitter junction voltage drops of transistors 41 and 42: VA=(V BE41 +V BE42 ) (R43+R44)/R44
During
normal image intervals typically there are greater than
approximately 25 microamperes of current conducted by transistor 30,
which is sufficient to render transistors 41 and 42 conductive for
developing clamping voltage VA at terminal A. At other times, as will
be discussed, transistors 41 and 42 are rendered nonconductive
whereby clamping action is inhibited and a (variable) voltage is
developed at node A as a function of the magnitude of the kinescope
cathode current, for processing by succeeding control circuits.Illustratively, the arrangement of FIG. 1 can be used in connection with digital signal processing and control circuits in a color television receiver employing digital signal processing techniques, as will be seen in FIG. 2. Such control circuits include an input analog-to-digital converter (ADC) for converting analog voltages developed at terminal A to digital form for processing.
When the control circuits are to operate in an automatic kinescope black current (bias) control mode, wherein during i
mage
blanking intervals the kinescope conducts very small cathode
currents on the order of a few microamperes, approximating a kinescope
black image condition, clamp transistors 41 and 42 are rendered
nonconductive because such small currents flowing through resistors 43
and 44 from the collector of transistor 30 are unable to produce a
large enough voltage drop across resistor 44 to forward bias
transistors 41 and 42. Consequently terminal A exhibits voltage
variations, as developed across resistors 43 and 44, related to the
magnitude of kinescope black current. The voltage variations are
processed by the control circuits coupled to terminal A to develop a
correction signal, if necessary, to maintain a desired level of
kinescope black current conduction by feedback action. In this
operating mode switch 49, e.g., a controlled electronic switch, is
maintained in an open position as shown in response to a timing
signal VT developed by the control circuits.When the control circuits are to operate in an automatic kinescope white current (drive) control mode wherein during image blanking intervals the kinescope conducts much larger currents representing a white image condition, switch 49 closes in response to timing signal VT, thereby shunting resistor 48 across resistors 43 and 44. The value of resistor 48 is chosen relative to the combined values of resistors 43 and 44 so that the larger current conducted via the collector of transistor 30 divides between series resistors 43, 44 and resistor 48 such that the magnitude of current conducted by resistors 43 and 44 is insufficient to produce a large enough voltage drop across resistor 44 to render clamping transistors 43 and 44 conductive. Unclamped terminal A therefore exhibits voltage variations related to the magnitude of kinescope white current, which voltage variations are processed by the control circuits to develop a correction signal as required. As used herein, the expression "white current" refers to a high level of individual red, green or blue color image current, or to combined high level red, green and blue currents associated with a white image.
With
the illustrated configuration of transistors 41 and 42 clamping
voltage VA is relatively low, approximately +2.0 volts. The clamping
voltage could be provided by a Zener diode rather than the disclosed
arrangement of Darlington-connected transistors 41 and 42, but the
disclosed clamping arrangement is preferred because Zener diodes with a
voltage rating less than about 4 volts usually do not exhibit a
predictable Zener threshold voltage characteristic, i.e., the "knee"
transition region of the Zener voltage-vs-current characteristic is
usually not very well defined. In addition, the disclosed transistor
clamp operates with better linearity than a Zener diode clamp and
radiates less radio frequency interference (RFI).The relatively low clamping voltage is compatible with the analog input voltage requirements of the analog-to-digital converter (ADC) at the input of the control circuits which receive the sensed voltage at terminal A as will be explained in greater detail with respect to FIG. 2. In this example the ADC is intended to process analog voltages of from 0 volts to approximately +2.5 volts, and the clamping voltage assures that excessively high analog voltages are not presented to the ADC during normal video signal intervals.
The relatively l
ow
clamping voltage also assists to prevent transistor 30 from
saturating, which is necessary since transistor 30 is intended to
operate in a linear region. To achieve this result and to maximize the
cathode current conduction capability of transistor 30, the clamping
voltage should be as low as possible to maintain a suitably low bias
voltage at the collector of transistor 30. On the other hand, the
value of arc current limiting resistor 37a should be large enough to
provide adequate arc protection without compromising the objective of
maintaining the collector bias voltage of transistor 30 as low as
possible. Operation of transistor 30 in a saturated state renders
transistor 30 ineffective for its intended purpose of properly
conveying video drive signals to the kinescope cathode, and for
conveying accurate representations of cathode current to clamping
network 40 particularly in the white current control mode when
relatively high cathode current levels are sensed. In addition,
undesirable radio frequency interference (RFI) can be generated by
transistor 30 switching into and out of saturation. Also, when
saturation occurs transistor base storage effects can result in video
image streaking due to the time required for a transistor to come out
of a saturated state.Thus clamping network 40 advantageously limits the voltage at terminal A to a level tolerable by the analog-to-digital converter at the input of the control circuits coupled to terminal A, and protects the analog-to-digital converter input from damage due to signal overdrive. Network 40 also provides a collector reference bias for transistor 30 to prevent transistor 30 from saturating on large negative-going signal amplitude transitions at its emitter electrode. The clamping voltage level is readily adjusted simply by tailoring the values of resistors 43 and 44.
Capacitor 46 bypasses high frequency video signals to ground to prevent transistor 30 from saturating in response to such signals. Capacitor 46 also serves to smooth out undesirable high frequency variations at terminal A to prevent potentially troublesome signal components such as noise from interfering with the signal processing function of the input analog-to-digital converter of the control circuits, e.g., by smoothing the current sensed during the settling time of the analog-to-digital converter.
The latter noise reducing effect is particularly desirable, for example, when the input ADC of the control circuits coupled to terminal A is of the relatively inexpensive and uncomplicated "iterative approximation" type ADC, compared to a "flash" type ADC. The operation of an iterative ADC, wherein successive approximations are made from the most significant bit to the least significant bit, requires a relatively constant or slowly varying analog signal to be sampled during sampling intervals, uncontaminated by noise and similar effects.
The value of capacitor 46 should not be excessively large because a certain rate of current variation should be permitted at terminal A with respect to kinescope cathode currents being sensed. If the value of capacitor 46 is too small, excessive voltage variations, particularly high frequency video signal variations, will appear at terminal A, increasing the likelihood of transistor 30 saturating. The speed of operation of the clamp circuit itself is restricted by an RC low pass filter effect produced by the base capacitance of transistor 41 and the equivalent resistance of resistors 43 and 44.
F
IG.
2 shows a portion of a color television receiver system employing
digital video signal processing techniques. The FIG. 2 system utilizes
kinescope driver amplifiers and a clamping network as disclosed in
FIG. 1, wherein similar elements are identified by the same reference
number. By way of example, the system of FIG. 2 includes a MAA 2100
VCU (Video Codec Unit) corresponding to video signal source 10 of FIG.
1, a MAA 2200 VPU (Video Processor Unit) 50, and a MAAA 2000 CCU
(Central Control Unit) 60. The latter three units are associated with a
digital television signal processing system offered by ITT
Corporation as described in a technical bulletin titled "DIGIT 2000
VLSI DIGITAL TV SYSTEM" published by the Intermetall Semiconductors
subsidiary of ITT Corporation.In
unit 10, a luminance signal and color difference signals in digital
form are respectively converted to analog form by means of
digital-to-analog converters (DACs) 70 and 71. The analog luminance
signal (Y) and analog color difference signals r-y and b-y are
combined in a matrix amplifier 73 to produce r, g and b color image
representative signals which are processed by preamplifiers 75, 76 and
77, respectively, before being coupled to kinescope driver stages
15, 16 and 17 of the type shown in FIG. 1. A network 78 in unit 10
includes circuits associated with the automatic white current and black
current control functions.The high level R, G and B color signals from driver stages 15, 16 and 17 are coupled via respective current limiting resistors (i.e., resistor 33) to cathode intensity control electrodes of a color kinescope 80. Currents conducted by the red, green and blue kinescope cathodes are conveyed to network 40 via resistors 37a-37c, for producing at terminal A a voltage representative of kinescope cathode current conducted during measuring intervals, as discussed previously.
VPU unit 50 includes input terminals 15 and 16 coupled to terminal A. Through terminal 15 the VPU receives the analog signal from terminal A and, via an internal multiplex switching network 51, the analog signal is supplied to an analog-to-digital-converter (ADC) 52. Terminal 16 is connected to an internal switching device (corresponding to switch 49 in FIG. 1) which, in conjunction with scaling resistor 48, controls the impedance and therefore the sensitivity at input terminal 15. High sensitivity for black current measurement is obtained with resistor 48 ungrounded by internal switch 49, and low sensitivity for white current measurement is obtained with resistor 48 grounded by internal switch 49.
The digital signal from ADC 52 is coupled to an IM BUS INTERFACE unit 53 which coacts with CCU unit 60
and
provides signals to an output data multiplex (MPX) unit 55.
Multiplexed output signal data from unit 55 is conveyed to VCU unit 10,
and particularly to control network 78. Control network 78 provides
output signals for controlling the signal gain of preamplifiers 75,
76 and 77 to achieve a correct white current condition, and also
provides output signals for controlling the DC bias of the
preamplifiers to achieve a correct black current condition.More specifically, during vertical image blanking intervals the three (red, green, blue) kinescope black currents subject to measurement and the three white currents subject to measurement are developed sequentially, sensed, and coupled to VPU 50 via terminal 15. The sensed values are sequenced, digitized and coupled to IM Bus Interface 53 which organizes the data communication with CCU 60. After being processed by CCU 60, control signals are routed back to interface 53 and from there to data multiplexer 55 which forwards the control signals to VCU 10.
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Regulated power supply device for a line sweep circuit in a television receiver:SALORA 28M91 CHASSIS M CHASSIS SALORA M-CHASSIS STB253 110° DIGITAL POWER SUPPLY TECHNOLOGY BASIS THEORY .
1. A regulated power supply device, in particular for a line sweep circuit in a television receiver, whose output stage (30) contains a first electronic switch of the bidirectional type (36, 35), controlled periodically so as to be closed during the forward sweep and open during the fly-back, connected in parallel with a first series assembly containing line deviation coils (31) and a first capacitor (32), called the forward capacitor, which feeds these coils (31) during the closing of the first switch (36, 35), with a second capacitor (34), called the return capacitor, which forms a parallel resonant circuit with the inductance in particular of the coils (31) during the opening of the first switch (36, 35) and with a second series assembly containing a first winding (22) of a transformer (20), called the line transformer, and a third capacitor (33), called the power supply capacitor, which feeds the first winding (22) with D.C. voltage while the first switch (36, 35) is closed, the power supply device containing a chopper circuit (10)
connected between the terminals (6, 7) of a D.C. power supply voltage source (5) and containing an inductor, called the chopper inductor, (16) and a second electronic switch (15), which is controlled, mounted in series, this second switch (15) containing a chopper transistor (11) controlled on its base by means of a recurring control signal, which is produced by means of the line return pulses picked up on a secondary winding (25) of the line transformer (20), in order to be alternately conducting and cut off during each line period, this chopper inductor (16) containing a second winding (21), called the power supply winding, of this transformer (20), which is intended for the transfer of energy between the chopper circuit (10) and the line sweep output stage (30), and being characterized by the fact that, the second switch (15) being also of the bidirectional type and containing, apart from the chopper transistor (11),
2.
A power supply device as in claim 1, characterized by the fact that
the transistor (11) in the second switch (15) is controlled by means of
a regulation circuit (40) fed by an auxiliary winding (25) of the
transformer (20) which supplies it with a signal one of whose peak
amplitudes is proportional to the voltage at the terminals of the power
supply capacitor (33) in the output stage (30), which is recharged by
means of the chopper circuit (10), and whose peak to peak amplitude is
proportional to a very high voltage supplied by another winding (23)
of transformer (20), the regulation circuit (40) causing the delay in
the instant of cut off of transistor (11) to vary with respect to the
leading edge of the line return pulse produced by the opening of the
first switch (36, 35).3. A power supply device as in claim 2, characterized by the fact that the regulation by the phase shift between the respective cut off instants is obtained as a function either of the peak to peak amplitude or of the peak amplitude during the fly back or forward sweep of the signal at the terminals of one of the windings (21 or 25) of line transformer (20) by comparing this amplitude to a reference voltage and by controlling the delay as a function of the difference between the voltage corresponding to one of these amplitudes and the reference voltage, in order to stabilize either the sweep amplitude or the power supply voltage obtained by rectifying the line return pulse.
4.
A power supply device as in claim 2, characterized by the fact that
the regulation circuit (40) contains an unstable multivibrator (48)
whose output is coupled to the base of chopper transistor (11) by means
of a control stage (50) and which operates independantly on starting
up, a circuit generating a variable delay which contains a phase shift
stage (46) triggered by the line return pulses and supplying to the
multivibrator (48) triggering pulses which are delayed with respect to
the leading edges of the line return pulses, which cause the cutting
off of chopper transistor (11), and a regulator stage (47), which
supplies the phase shift stage (46) with a regulation signal that
makes it possible to vary the delay between the respective leading
edges of the line return pulses and the triggering pulses as a
function of one of the peak amplitudes or of the peak to peak
amplitude of the signal supplied by the auxiliary winding (25) of the
transformer (20).
5. A power supply device as in claim 4, of the type in which the power supply capacitor (33) feeds a D.C. voltage to the whole line sweep circuit, characterized by the fact that the regulation circuit (40) is fed by means of an independant power supply circuit (51) which enables the chopper circuit (10) to be started up by the independant operation of the unstable multivibrator (48) in order to start up the power supply of the line sweep circuit with the chopper voltage induced in the first winding (22) of the transformer (20) and rectified by the diode (35) which is part of the first bidirectional switch (36, 35) which charges the power supply capacitor (33).
6. A power supply device as in one of claims 4 and 5, characterized by the fact that the phase shift stage (46) contains a delay generator which supplies a voltage, in the shape of recurrent saw teeth (460, 463) which are triggered by the leading edges of the line return pulses, to an analog voltage comparator stage (469, 4600, 4601), which supplies at its output negative pulses to the base of the transistor (483) in multivibrator (48) whose cutting off controls the cut off of chopper transistor (11) at instants at which the instantaneous saw tooth amplitude exceeds a fixed threshold voltage (VZ 4601), and by the fact that the regulator stage (47) contains an assembly (470, 471) rectifying the signal supplied by the auxiliary winding (25) which feeds a signal generator (476, 475) supplying a signal which modifies, from a predetermined threshold, the saw tooth slope as a function of one of the peak amplitudes or peak to peak amplitudes of this signal (v25).
7. A power supply device as in claim 6, of the type in which the free running operating frequency of the unstable multivibrator (48) is less than the line frequency, characterized by the fact that the unstable multivibrator (48) is controlled solely by the negative pulses coming from the comparator stage (469), which are applied to one (483) of the transistors in the multivibrator (48), whose cut off controls that of chopper transistor (11).
8.
A power supply device as in one of claims 4 to 6, of the type in
which the free running operating frequency of the unstable
multivibrator (48) is greater than the line frequency in order to
limit the peak voltage (V19max) on the collector of the chopper
transistor (11), characterized by the fact that the transistor (480)
in the multivibrator (48), whose state is complementary to that of the
chopper transistor (11), is fed on its base through a diode (4803) by
a synchronizing stage (49), which supplies negative pulses whose
amplitude is equal to a predetermined fraction of that of the line
return pulses, in order to lengthen the cut off state of this
transistor (480) until the sum of these lengths is equal to the line
period.
Description:
The present invention concerns a regulated power supply device, in particular for a line sweep circuit in a television receiver, which can also provide D.C. supplies to other circuits in this receiver by splitting up a D.C. supply voltage which is usually obtained by the rectification and filtering of the A.C. mains voltage by means of a chopper.
Known chopper converters of this type contain, generally connected in series between the output terminals of a D.C. power supply source (filtered rectifier), an electronic switch such as a switching transistor operating in the saturated and cut off mode and an inductor which includes the primary winding of a transformer in which at least one secondary winding supplies the A.C. energy obtained by the chopping, which is then rectified to provide the D.C. supply voltages with a ground insulated from the mains. In most of the known chopper power supplies, one can vary the output voltages by action on the cyclic ratio, i.e. the length of the saturated (closed) state of the switch, for example, by controlling periodically the transistor-chopper by means of a monostable flip-flop of variable length as a function of a voltage which may be picked up at the output of a rectifier fed by a secondary winding of the transformer so as to form a regulation loop.
Chopper power supplies have frequently been used in television receivers to eliminate the bulky and heavy mains supply transformer and make possible a regulation of the D.C. power supply voltage for this receiver. They have often been combined in particular at the output stage of the horizontal sweep circuit which supplies them with a pulse signal at the line frequency that can be used to control the chopping. Various combinations of sweep circuits and chopper power supplies have described, for example, in the French patents or patent applications with publication Nos. 2.040.217, 2.060.495, 2.167.549, 2.232.147 or 2.269.257, in which the regulation is also done by means of the variation in the cyclic ratio of the saturated and cut off states of the chopper transistor which, in some cases, is also used as the active element of the (final) output stage of the line sweep circuit or of the feeder stage which controls this circuit.
5. A power supply device as in claim 4, of the type in which the power supply capacitor (33) feeds a D.C. voltage to the whole line sweep circuit, characterized by the fact that the regulation circuit (40) is fed by means of an independant power supply circuit (51) which enables the chopper circuit (10) to be started up by the independant operation of the unstable multivibrator (48) in order to start up the power supply of the line sweep circuit with the chopper voltage induced in the first winding (22) of the transformer (20) and rectified by the diode (35) which is part of the first bidirectional switch (36, 35) which charges the power supply capacitor (33).
6. A power supply device as in one of claims 4 and 5, characterized by the fact that the phase shift stage (46) contains a delay generator which supplies a voltage, in the shape of recurrent saw teeth (460, 463) which are triggered by the leading edges of the line return pulses, to an analog voltage comparator stage (469, 4600, 4601), which supplies at its output negative pulses to the base of the transistor (483) in multivibrator (48) whose cutting off controls the cut off of chopper transistor (11) at instants at which the instantaneous saw tooth amplitude exceeds a fixed threshold voltage (VZ 4601), and by the fact that the regulator stage (47) contains an assembly (470, 471) rectifying the signal supplied by the auxiliary winding (25) which feeds a signal generator (476, 475) supplying a signal which modifies, from a predetermined threshold, the saw tooth slope as a function of one of the peak amplitudes or peak to peak amplitudes of this signal (v25).
7. A power supply device as in claim 6, of the type in which the free running operating frequency of the unstable multivibrator (48) is less than the line frequency, characterized by the fact that the unstable multivibrator (48) is controlled solely by the negative pulses coming from the comparator stage (469), which are applied to one (483) of the transistors in the multivibrator (48), whose cut off controls that of chopper transistor (11).
8.
A power supply device as in one of claims 4 to 6, of the type in
which the free running operating frequency of the unstable
multivibrator (48) is greater than the line frequency in order to
limit the peak voltage (V19max) on the collector of the chopper
transistor (11), characterized by the fact that the transistor (480)
in the multivibrator (48), whose state is complementary to that of the
chopper transistor (11), is fed on its base through a diode (4803) by
a synchronizing stage (49), which supplies negative pulses whose
amplitude is equal to a predetermined fraction of that of the line
return pulses, in order to lengthen the cut off state of this
transistor (480) until the sum of these lengths is equal to the line
period.Description:
The present invention concerns a regulated power supply device, in particular for a line sweep circuit in a television receiver, which can also provide D.C. supplies to other circuits in this receiver by splitting up a D.C. supply voltage which is usually obtained by the rectification and filtering of the A.C. mains voltage by means of a chopper.
Known chopper converters of this type contain, generally connected in series between the output terminals of a D.C. power supply source (filtered rectifier), an electronic switch such as a switching transistor operating in the saturated and cut off mode and an inductor which includes the primary winding of a transformer in which at least one secondary winding supplies the A.C. energy obtained by the chopping, which is then rectified to provide the D.C. supply voltages with a ground insulated from the mains. In most of the known chopper power supplies, one can vary the output voltages by action on the cyclic ratio, i.e. the length of the saturated (closed) state of the switch, for example, by controlling periodically the transistor-chopper by means of a monostable flip-flop of variable length as a function of a voltage which may be picked up at the output of a rectifier fed by a secondary winding of the transformer so as to form a regulation loop.
Chopper power supplies have frequently been used in television receivers to eliminate the bulky and heavy mains supply transformer and make possible a regulation of the D.C. power supply voltage for this receiver. They have often been combined in particular at the output stage of the horizontal sweep circuit which supplies them with a pulse signal at the line frequency that can be used to control the chopping. Various combinations of sweep circuits and chopper power supplies have described, for example, in the French patents or patent applications with publication Nos. 2.040.217, 2.060.495, 2.167.549, 2.232.147 or 2.269.257, in which the regulation is also done by means of the variation in the cyclic ratio of the saturated and cut off states of the chopper transistor which, in some cases, is also used as the active element of the (final) output stage of the line sweep circuit or of the feeder stage which controls this circuit.
Chopper
power supplies of the so called "pump" type in which the chopper
transistor feeds one of the windings of the line transformer during the
line return periods and in which the regulation is done by means of
the variation of the internal resistance of this transistor or of a
"ballast" transistor in series with this transistor are known, for
example, from the French patents with publication Nos. 2.014.820,
2.025.365 or 2.116.335. A circuit of the "pump" type whose chopper
transistor has a winding of the line transformer in its collector
circuit and in which the sweep circuit is electrically insulated from
the mains has been described in the article by Peruth and Schrenk in the
German periodical, SIEMENS BAUTEILE REPORT Vol. 12 (1974), No. 4,
pages 96-98. Its structure corresponds to the contents of the
introduction to claim 1. In circuits of the "pump" type, the chopper
transistor or the "ballast" transistor in series with it dissipates an
amount of energy which is not negligable.
In the chopper device supplying power to the output stage of the line sweep circuit with which it is combined in accordance with the invention, one no longer uses regulation by variation of the internal resistance or of the length of the saturated state of the chopper transistor (or by variation of the cyclic ratio of the chopping with a constant periodicity) but one does the regulating by variation of the relative phase between the signals of the same frequency which are supplied respectively by the chopper circuit with a constant cyclic ratio and by the output stage of the line sweep, each of which is connected to one of the windings of a transformer called the line transformer through which the transfer of energy between the chopper circuit and the sweep output stage takes place as well as in the direction of the other secondary windings of the line tranformer such as the very high tension (V.H.T.) winding.
In accordance with the invention, a regulated power supply device, in particular for a line sweep circuit of a television receiver which contains an output stage fitted with a line transformer in which a first winding is connected in series with a supply capacitor, is connected in parallel with a first bidirectional switch controlled at the line frequency, the power supply device containing a chopper circuit with, connected in series between the terminals of a source of a D.C. power supply voltage, an inductor and a second electronic switch, which can also be controlled at the line frequency. The inductor in this circuit contains a second winding of the transformer which is intended for the transfer of energy between the chopper circuit and the output stage.
This
power supply device is in particular characterized by the fact that
the second switch, which is also bidirectional and mounted in parallel
with a tuning capacitor, is so controlled as to be alternately open
and closed during each line period with a constant cyclic ratio and by
the fact that the regulation of the power supplied and hence of the
voltage at the terminals of the supply capacitor is done by variation
of the phase delay between the respective opening instants of the
first and second switch as a function of the peak amplitude of the
line return pulse for example.
In accordance with a preferred way of making the invention, a power supply device in accordance with the preceding paragraph, in which the second bidirectional switch, which contains a switching transistor, is controlled on its base by a regulation circuit in which one input is fed by an auxiliary secondary winding of the line transformer supplying line return pulses, is remarkable in particular for the fact that the regulation circuit contains an unstable multivibrator controlling the base of the chopper transistor and operating independantly on starting up, a circuit generating a variable delay containing a phase shift stage, which is triggered by the line return pulses and supplies the multivibrator with triggering pulses that are delayed with respect to the leading edges of the line return pulses, which cause the cut off of the chopper transistor, and a regulator stage fed with the line return pulses and supplying to the phase shift stage a regulation signal which enables the delay in the triggering pulses to be varied with respect to the line return pulses as a function of one of the peak amplitudes or of the peak to peak amplitude of the line return pulses.
The invention will be better understood and others of its characteristics and advantages will appear from the description which follows, which is given as an example, and the drawings attached, which refer to it. Among them:
FIG. 1 represents part of a theoretical schematic diagram of a chopper power supply device combined with the output stage of the line sweep circuit in accordance with the invention;
FIGS.
2a-2f and 3a-3f are diagrams of the voltage wave forms and/or current
wave forms at various points in the circuit of FIG. 1 to explain the
operation of this circuit;
FIG. 4 represents part of a synoptic schematic diagram of a simple production model (without a starter device) of regulation circuit 40 in FIG. 1;
In the chopper device supplying power to the output stage of the line sweep circuit with which it is combined in accordance with the invention, one no longer uses regulation by variation of the internal resistance or of the length of the saturated state of the chopper transistor (or by variation of the cyclic ratio of the chopping with a constant periodicity) but one does the regulating by variation of the relative phase between the signals of the same frequency which are supplied respectively by the chopper circuit with a constant cyclic ratio and by the output stage of the line sweep, each of which is connected to one of the windings of a transformer called the line transformer through which the transfer of energy between the chopper circuit and the sweep output stage takes place as well as in the direction of the other secondary windings of the line tranformer such as the very high tension (V.H.T.) winding.
In accordance with the invention, a regulated power supply device, in particular for a line sweep circuit of a television receiver which contains an output stage fitted with a line transformer in which a first winding is connected in series with a supply capacitor, is connected in parallel with a first bidirectional switch controlled at the line frequency, the power supply device containing a chopper circuit with, connected in series between the terminals of a source of a D.C. power supply voltage, an inductor and a second electronic switch, which can also be controlled at the line frequency. The inductor in this circuit contains a second winding of the transformer which is intended for the transfer of energy between the chopper circuit and the output stage.
In accordance with a preferred way of making the invention, a power supply device in accordance with the preceding paragraph, in which the second bidirectional switch, which contains a switching transistor, is controlled on its base by a regulation circuit in which one input is fed by an auxiliary secondary winding of the line transformer supplying line return pulses, is remarkable in particular for the fact that the regulation circuit contains an unstable multivibrator controlling the base of the chopper transistor and operating independantly on starting up, a circuit generating a variable delay containing a phase shift stage, which is triggered by the line return pulses and supplies the multivibrator with triggering pulses that are delayed with respect to the leading edges of the line return pulses, which cause the cut off of the chopper transistor, and a regulator stage fed with the line return pulses and supplying to the phase shift stage a regulation signal which enables the delay in the triggering pulses to be varied with respect to the line return pulses as a function of one of the peak amplitudes or of the peak to peak amplitude of the line return pulses.
The invention will be better understood and others of its characteristics and advantages will appear from the description which follows, which is given as an example, and the drawings attached, which refer to it. Among them:
FIG. 1 represents part of a theoretical schematic diagram of a chopper power supply device combined with the output stage of the line sweep circuit in accordance with the invention;
FIGS.
2a-2f and 3a-3f are diagrams of the voltage wave forms and/or current
wave forms at various points in the circuit of FIG. 1 to explain the
operation of this circuit;FIG. 4 represents part of a synoptic schematic diagram of a simple production model (without a starter device) of regulation circuit 40 in FIG. 1;
FIG. 5 represents a block diagram of a preferred production model of regulation circuit 40 in FIG. 1 in accordance with the invention;
FIG. 6 represents a theoretical schematic diagram of the whole of the preferred production model of the regulation circuit in FIG. 5;
FIGS. 7a and 7b represent voltage wave forms illustrating the slaving of the frequency of the unstable multivibrator 48 to that of the line oscillator; and
FIGS. 8a-8c represent voltage wave forms illustrating the operation of the regulation by the variation in phase shift.
In FIG. 1 is shown schematically a chopper power supply device of line sweep output stage 30 in accordance with the invention which is electrically insulated from the A.C. mains which feed rectifier 5 whose output voltage is chopped. This power supply device has two terminals 1, 2 which are connected respectively to the two poles of the A.C. distribution mains (220 V, 50 Hz) and feed rectifier diode 3 and filter capacitor 4, whose capacity is high, which are connected in series and form together a rectifier assembly or a source of D.C. voltage 5. The output of rectifier assembly 5 formed by the two terminals 6 and 7 (plates) of the (electro-chemical) capacitor 4 is intended to supply a D.C. power supply voltage V A of the order of 300 V to chopper circuit 10. This chopper circuit 10 contains a controlled, bidirectional electronic switch 15, which consists of a switching transistor 11 of the NPN type connected with its emitter common and a junction semiconductor diode 12, which are connected in parallel in such a way as to conduct respectively in opposite directions (anti-parallel), and an inductor 16 consisting of a choke 14 and a winding 21 of a transformer 20, called a line transformer, connected in series. This winding 21 of line transformer 20 whose primary winding is normally connected in parallel with the coils of the horiziontal deviation circuit in the circuit of line sweep output stage 30 to the supply, through secondary windings, supply voltages in particular to the cathode ray tube will be called in what follows the supply voltage winding, because the transfer of energy between chopper circuit 10 and output stage 30 will be done through it. Switch 15 is mounted in parallel with a capacitor 13 and it is connected in series with inductor 16 (choke 14 and power supply winding 21 in series) between the output terminals 6 and 7 of D.C. voltage source 5. This capacitor 13 forms, because of its low capacity with respect to that of filter capacitor 4, with inductor 16 a parallel, resonant (oscillatory) circuit when electronic switch 15 is opened by the cutting off of switching transistor 11 by means of a control signal applied to its base.
Switching
transistor 11 is here connected by its collector to one of the
terminals of inductor 16, whose other terminal is connected to positive
terminal 6 of source 5 which supplies D.C. power supply voltage V A ,
by its emitter to negative terminal 7 of source 5, which forms a
ground, called the primary or hot ground, 8, which is connected to the
A.C. mains but is insulated from that 39 of the television set. The
base of transistor 11 is controlled by means of rectangular signals
supplied by a regulation circuit 40, which is described further on, in
such a way as to be alternately saturated and cut off. Regulation
circuit 40 is, for example, fed by a secondary winding 25 of
transformer 20, that supplies signals whose peak to peak amplitude is
proportional to the peak amplitude of the line return pulse. This peak
amplitude is a function of the energy transfer from chopper circuit 10
to the line sweep output stage 30 which is connected to another
winding 22 of transformer 20.One may note here that chopper circuit 10 resembles a classical, transistorized, line sweep output stage and that switching transistor 11 has been chosen to withstand high collector-emitter voltages (of the order of 1500 V), and that diode 12 has to withstand the same inverse voltage while switch 15 is open. One may also note that the inductance of choke 14 may be formed partly or wholly by the leakage inductance of power supply winding 21 in transformer 20.
The line sweep output stage 30, which is arranged in classical fashion, contains horizontal deviation coils 31 mounted in parallel and connected by one of their terminals to a first capacitor 32, called the "forward" or "S effect" capacitor, which feeds them during the forward sweep. The series mounting of coils 31 and forward capacitor 32 is connected in parallel, on the one hand, to a second controlled bidirectional switch containing a second switching transistor 36 and a second diode 35, called a "shunt" or "parallel" recuperation diode, which are connected in parallel to conduct in opposite directions, closed (conductor) during the forward sweep and open (cut off) during the return sweep, and, on the other hand, to a second capacitor 34, called the "return" capacitor, which forms, while the second switch is open, a parallel resonant circuit with the inductance of deviation coils 31. The common point of the collector of second transistor 36, of the NPN type, of the cathode of second diode 35 and return 34 and forward 32 capacitors is connected to one of the terminals 220 of winding 22 of transformer 20, which normally forms the primary winding of this transformer. The other terminal 221 of winding 22 is connected to one of the terminals of a third capacitor 33 of high capacity, whose other terminal is connected to the common point of deviation coils 31, return capacitor 34, the anode of second diode 35 and the emitter of second transistor 36, which is also connected to the ground 39 of the chassis of the television receiver, called the "cold" ground, because it is insulated from the A.C. power supply mains. It is at the terminals of this third capacitor 33 that one obtains the
In classical transistor line sweep circuits, a D.C. voltage source generally feeds either terminal 221 of winding 22 directly or an intermediate connection to this winding through a diode (see French Pat. Nos. 1.298.087 dated Aug. 11, 1961, 1.316.732 dated Feb. 15, 1962 or 1.361.201 dated June 27, 1963) which isolates the primary winding of the line transformer from the D.C. voltage source during the line return interval.
In
the circuit of FIG. 1, it is the A.C. electrical energy transmitted
by chopper circuit 10 through windings 21 and 22 of transformer 20
which charges capacitor 33 so that it supplies a regulated supply
voltage to output stage 30. During the line sweep forward periods,
when the second bidirectional switch 35, 36 of sweep output stage 30
is closed (conductor), the terminals of winding 22 of transformer 20
are directly connected to those of capacitor 33 which will then
receive the energy supplied of by chopper circuit 10.In FIG. 1, line transformer 20 also has a very high voltage winding 23, one terminal 230 of which may be connected to the ground 39 (or to terminal 220 of winding 22) and whose other terminal 231 is connected to the input of the very high voltage rectifier assembly or voltage multiplier (not shown) in classical fashion, and an auxiliary winding 24 which may be used to feed either a low voltage rectifier assembly or a load regulator assembly or the filament of the cathode ray tube (not shown). These secondary windings 23, 24 will receive their energy mainly from output stage 30 of the line sweep circuit through winding 22 of transformer 20, i.e. the line return pulses, the coupling between the windings will hence be as close as possible.
The operation of the power supply device in FIG. 1 will be explained below with that of output stage 30 of the line sweep circuit, with reference to FIGS. 2 and 3 of the drawing attached, representing diagrams of the voltage wave forms and/or current wave forms at various points in the schematic diagram of FIG. 1.
In
FIGS. 2 and 3, diagram (A) represents the saw tooth wave form of the
sweep current i 31 (t) in the coils 31 of the horizontal deviation
circuit. Diagram (B) represents the wave form of the voltage v 220 (t)
on terminal 220 of winding 22, which is also that at the terminals of
the second switch 35, 36. Diagram (C) is the wave form of the voltage v
21 (t) at the terminals of power supply winding 21 when its leakage
inductance is negligable. It is obtained by the transforming of the
A.C. component of voltage v 220 (t). Diagram (D) represents the wave
form of the voltage v 19 (t) at the terminals of first switch 15 in
chopper circuit 10, i.e. between the junction 19 of this chopper
circuit with inductor 16 and primary ground 8, and diagram (E)
represents as a dotted line the current i 16 (t) in inductor 16 when
output stage 30 is not controlled and as a full line the current i 21
(t) resulting from the superimposition in winding 21 to current i 16
(t) on that induced by winding 22 when output stage 30 is working.
Conversely, the current in winding 22 of transformer 20 results from
the superimposition of the current induced by winding 21 on the
current produced by the closing of the second switch 35, 36, which is
analogous to i 31 (t) in diagram (A).The wave forms of diagrams (D) and (E) in FIGS. 2 and 3 are out of phase respectively, one with respect to another, by a quarter of a line period T H /4 to allow the illustration of the regulation by the variation in the relative phase of the voltage v 21 and current i 21 waves in power supply winding 21.
The diagrams (F) represent the instantaneous energy E i transmitted by chopper circuit 10 to the output stage 30, which is equal to the product of the wave forms of current i 21 (t) and voltage v 21 (t) in winding 21, i.e. E i =-v 21 i 21 , for two different phase deviations between the voltage v 21 (t) and current i 21 (t) waves in power supply winding 21, which correspond respectively to a zero energy transfer in FIG. 2 and a maximum energy transfer in FIG. 3.
During the forward sweep intervals t A , when the switch 35, 36 is closed from instant t 1 to instant t 3 , the current i 31 (see A) in the deviator varies roughly linearly between its negative peak values (at t 1 ) and positive ones (at t 3 ) with a passage through zero at instant t 2 , when current i 31 passes from diode 35 to transistor 36, which has previously been polarized to conduct. This corresponds to a roughly zero voltage v 220 (see B) at the terminals of switch 35, 36.
The line return interval t R is started by the cutting off of transistor 36 at instant t 3 , and the inductance of deviator 31 then acts as a parallel resonant circuit with the return capacitor 34 by causing the voltage v 220 (t) to pass through a positive half-sinusoid and reach its peak value at the instant t 4 (or t=0), called the line return pulse, and the current i 31 (t) to pass through a half-cosinusoid between the positive and negative peak values cited, with a passage through zero at the instant t 4 (or t=0). The mean value of the voltage wave form v 220 (t) at terminal 220 is equal to the D.C. power supply voltage V 221 at the terminals of power supply capacitor 33 and forward or S effect capacitor 32.
The respective peak to peak amplitudes of current i 31 (t) (hence the width of the screen sweep beam excursion) and of voltage v 220 (t) (hence the very high voltage) depend on the value of the D.C. voltage V 221 which feeds the horizontal sweep output stage and which, in most of the chopper power supplies of preceding techniques, is regulated and stabilized by modulating the length of the saturated state (the cyclic ratio) of chopper transistor 11 as a function of the amplitude of the line return pulse picked up on an auxiliary winding of line transformer 20 (hence of the voltage at the terminals of capacitor 33) and later of the rectified and filtered voltage in the network.
I
n
accordance with the invention, the length t s of the saturated state
of chopper transistor 11 and of the conducting state of diode 12 and,
as a result, the ratio of this length to that of the complete cycle
(line period T H ) or to that t B of the cut off state is constant and
so chosen as to make the peak amplitude of voltage pulse v 19 , which
is applied to the collector of transistor 11 during the cut off
interval t B , considerably less than its collector-emitter D.C.
breakdown voltage in the cut off state (V CEX ) which may exceed 1500
Volts. Thus, for a rectified voltage of 300 V, it is possible to limit
the collector voltage V 19 to about 900 Volts by choosing a ratio t b
/T H of about 0.5.As a result, chopper circuit 10 must operate at the line frequency with conduction lengths t S (closed) and cut off lengths t B (open) of switch 15 preferably roughly equal (to a line half-period T H /2) and the regulation of the energy supplied to output stage 30 is done by causing the respective phases of the line return pulse v 220 (t) and the current i 21 (t) flowing through the power supply winding 21 of transformer 20 to vary as will be shown further on.
The operation of chopper circuit 10 (fed with D.C. voltage V A ) is in fact analogous to that of output stage 30, except as far as the form factor is concerned. This is determined mainly by the respective values of the inductance 16 (of choke 14 and the leakage inductance of winding 21 of transformer 20 connected in series) and of the capacity of tuning capacitor 13. The values L 16 and C 13 are chosen to obtain a half-period of oscillation slightly less than a line half-period, i.e.: ##EQU1## because the oscillation of the resonant circuit L 16 , C 13 occurs on one side and on the other of the D.C. voltage V A so that the cut off period of chopper switch 15 is greater than this half-period T D /2.
This operation of circuit 10 will first be explained with reference to diagrams D and E in FIG. 2. When, at the instant t=0, transistor 11 becomes saturated by a preliminary positive polarization of its base-emitter junction, it connects terminal 19 to ground 8 so that a current i 16 (t) (dotted on diagram E), which is increasing linearly, ##EQU2## passes through inductor 16 coming from positive terminal 6 of power supply 5.
When transistor 11 receives from regulation circuit 40 a cut off voltage at an instant preceding instant t 6
When oscillatory voltage v 19 (t) has exceeded the zero value slightly in the negative direction, diode 12 starts to conduct so as to connect terminal 19 to ground and produce in inductor 16 a current i 16 (t), which increases linearly from its maximum negative value i 16 (t 7 ) towards a zero value where transistor 11, which has already been polarized so as to be saturated, picks it up so that it reaches, at instant t 8 , its maximum positive value of instant t 6 again.
It is to be noted here that the mean value of the wave form of voltage v 19 at terminal 19 is equal to the D.C. power supply voltage V A between terminals 6 and 7 of filter capacitor 4 in rectifier assembly 5.
If one wishes to obtain an adequate energy transfer between chopper circuit 10 and line sweep output stage 30, it is advantageous to choose the value of inductor 16 in series with power supply winding 21, i.e. the sum of the leakage inductance of this winding and that of series choke 14, so that it is, for example, greater than or equal to three times the inductance L 31 of the horizontal deviation coils 31, multipled by the square of the transformation ratio between windings 22 and 21, i.e. L 16 ≥3l 31 (n 11 /n 21 ) 2 , and the value of this transformation ratio n 22 /n 21 so as to obtain at the terminals of winding 21, during the forward sweep and the closing of switch 15, an induced voltage v 21 (t) whose amplitude is between 100 and 150 Volts, i.e. between a third and a half the power supply voltage V A at terminals 6, 7 of filter capacitor 4.
The choice of these parameters is only given here as an example, because the criterion of this choice is a relative separation between chopper circuit 10 and, in particular, circuit 30 which it feeds, i.e. so that current i 21 (t) in winding 21 is only induced in winding 22 with peak amplitudes which do not exceed about one third those of sweep current i 31 (t) in order not to upset the operation of sweep circuit 30 during the conduction of recuperation diode 35. Also, the voltage pulses v 19 (t) of the diagrams (D) in FIGS. 2 and 3 should not appear at the terminals of winding 21 and should not be transmitted to winding 22 at least during the opening of sweep switch 36, 35 (line return interval) to winding 22 other than with amplitudes sufficiently small not to upset the operation of output stage 30 and the very high voltage rectifier fed by winding 23, while ensuring an energy transfer sufficient to obtain a regulated power supply voltage at the value required.
Transformer
20 may therefore be made in such a way as to have looser coupling
between windings 21 and 22, the self-inductance then consists of that (L
14 ) of choke coil 14 and the leakage inductance (L 21 ) of winding
21. Hence it is advantageous, when one uses a ferrite core (magnetic
circuit) of rectangular shape (in the form of a frame), to place
windings 22, 23 and 24 on one of the arms of this core and winding 21
and, later, winding 25 on the other. This will also help provide good
insulation between the primary and secondary grounds 8 and 39. The
dimension of the air gap in the magnetic circuit of transformer 20 or a
magnetic shunt, which fixes the leakage inductance L 21 , and the
inductance L 14 of the choke 14 are chosen with this result in view.One may consider then that, from the point of view of the energy transfer from chopper circuit 10 to output stage 30, winding 21 is passed through by current i 21 , which consists of triangular shaped current i 16 and the current in winding 22, which is induced in saw tooth form, superimposed one on the other and that voltage v 21 , which appears at its terminals and is shown in diagrams (C) of FIGS. 2 and 3, is roughly analgous to that, v 220 , at the terminals of sweep switch 35, 36 but with a mean value of zero.
The energy transmitted by transformer 20 will then be approximately equal to the product of voltage v 21 (t) and current i 21 (t) multiplied by the cosine of the phase angle if one considers the fundamental waves at the line frequency (15.625 Hz). This is also true for each of the harmonics of the current i 21 (t) and voltage v 21 (t) waves if one develops them in a Fourier series.
The energy ceded duuring each line period T H by chopper circuit 10 output stage 30 through transformer 20 may then be written: ##EQU3## In inductor 16, as a first approximation, current i 21 (t) in a sum of an A.C. component i A (t) and a D.C. component I c and, considering that the losses of chopper circuit 10 itself are negligable, that the mean value of voltage v 21 is zero and that the D.C. component I c of i 21 does not take part in the energy transfer, one may write that the energy supplied by the D.C. source during this period E s =V A I C T H and the A.C. energy supplied by chopper circuit 10, ##EQU4## are roughly equal, i.e. ##EQU5## from which it appears that there is a mean D.C. current ##EQU6## supplied by source 5 which is a consequence of the exchange of energy between winding 21 and winding 22 in particular. The A.C. energy ceded, E H , and, as a result, the D.C. current I c of source 5, varies as a function of the cosine of the phase angle α between each of the respective harmonics of the current i 21 (t) and voltage v 21 (t). Hence one can obtain regulation by causing the phase of the wave of current i 21 (t) to vary in power supply winding 21 with respect to that of voltage v 21 (t) at its terminals to stabilize the sweep (the peak to peak amplitude of current i 31 ) and/or the very high voltage by acting on the charge supplied to capacitor 33 during each cycle.
This
is illustrated respectively on the diagrams (F) in FIGS. 2 and 3
showing the instantaneous power E i =-v 21 (t)i 21 (t) corresponding to
two different phase angles between waves v 21 and i 21 , which
indicate respectively minimum (zero) energy transfers when the zeros of
current i 21 coincide with the maxima of voltage v 21 or when the
respective maxima of voltages v 21 and v 19 are out of phase by a half
period T H /2 and maximum energy transfers when the maxima of voltage v
21 and current i 21 coincide between circuit 10 and output stage 30.On the diagram (F) in FIG. 2, one can see that, when there is a phase difference between the corresponding (positive) maxima of v 21 (t) and i 21 (t) of a quarter of a line period (T H /4) roughly, the energy transfer is zero, because there is equality between the surfaces bounded by the curve and the abscissa, which are respectively above and below it and give a mean value of zero as far as the energy supplied is concerned.
On the other hand, on the diagram (F) in FIG. 3 in which the product-v 21 (t)i 21 (t) corresponds to a coincidence of phase between the respective maxima of voltage v 21 and i 21 , one can see that, when one subtracts from the surfaces above the abscissa the surfaces corresponding to the shaded triangles below it, three zones remain on the positive side whose surfaces correspond to the energy which is effectively transferred whose mean value ##EQU7## is positive and shows an effective transfer of energy to output stage 30. This translates into a D.C. voltage V 33 at the terminals of capacitor 33 which forms, during the forward sweep (closing of switch 35, 36), the sole load on winding 22 (terminal 220 being connected to the ground 39).
Hence, one has shown above that, by causing the phase difference between the corresponding maxima of waves v 21 (t) and i 21 (t) to vary between 0 and T H /4, one can cause the energy transmitted to vary and, as a result, the voltage V 221 at the terminals of capacitor 33 which feeds output stage 30.
When the relative phase difference between v 21 (t) and i 21 (t) exceeds a quarter of a line period, as, for example, when the negative peak amplitude of v 21 (t) coincides with the negative peak amplitude of i 21 (t), i.e. a phase difference equal to a line half period (T H /2), the term of the energy E H becomes negative which indicates that it is output stage 30 which feeds chopper circuit 10, or, more precisely, voltage source 5 (capacitor 4). This is not permanently possible unless it is output stage 30, and hence capacitor 33, which is fed by a rectifier assembly, thus showing the reversibility of the power supply device in accordance with the invention, which is contrary to classical chopper power supplies.
Hence, the regulation is done by causing the phase of the opening of switch 15 in chopper circuit 10 to be varied by the cutting off of transistor 11 with respect to the phase of the opening of sweep switch 36, 35, which is controlled by the line oscillator (not shown) and is generally slaved in frequency and phase to the line synchronizing pulses of the video complex signal.
which is proportional to the voltage V 33 (V 221 ) at the terminals of power supply capacitor 33 in output stage 30, or to the peak to peak amplitude of the line return pulse, which is proportional to the very high voltage, or to a combination of these two criteria. The other input of the differential amplifier receives a D.C. reference voltage, which may be adjusted, to allow the adjustment of the very high voltage and/or the horizontal sweep current amplitude.
It is to be noted here that power supply winding 21 may be connected between terminal 6 of capacitor 4 and choke 14 in two opposite directions so that the line return pulses can appear at its junction with choke 14 with opposite polarities. Two possibilities of the relative phase of voltage v 21 (t) respect to the current i 21 (t) in winding 21 result from this.
In FIG. 4, one has shown a partial block diagram (without a starting up device) of a simple way of making regulation circuit 40 which controls the cut off of transistor 11 in chopper circuit 10 with a delay which is variable with respect to the line return pulse as a function of the negative peak amplitude of the signal v 25 (t) supplied by auxiliary winding 25 of transformer 20.
Regulation circuit 40 in FIG. 4 is fed at its first input 401 with signal v 25 (t) supplied by one of the terminals 250 of auxiliary winding 25. This signal is roughly the reverse of signal v 21 (t) illustrated by the diagrams (C) respectively in FIGS. 2 and 3 in which one distinguishes, during each line period, a line return pulse of positive polarity and a negative plateau whose amplitude is proportional to D.C. voltage V 33 at the terminals of capacitor 30. This first input 401 feeds, through a first diode 410, the triggering input 411 of a first monostable flip-flop 41 of variable length, which produces at its output 413, in response to the leading edge of the return pulse, a rectangular signal whose length varies as a function of the D.C. voltage applied to its length control input 412.
Monostable flip-flops with a pulse length variable as a function of a D.C. voltage are known and a way of making them is described, for example, in French patent application No. 73.16116 made on May 4, 1973 by the present applicant.
This D.C. voltage controlling pulse length is obtained by means of a rectifier assembly 42, which is also fed by this first input 401 and contains a second diode 420 so connected as to conduct only while signal v 25 (t) is negative, a capacitor 421 in series with diode 420 which stores the negative peak values of v 25 (t), a resistive potentiometric divider assembly 422, 423 mounted in parallel with capacitor 421 and a polarity reverser 424 fed by the centre point of divider 422, 423 and supplying a positive voltage of the same level in reply to a negative input voltage, the respective terminals of capacitor 421 and divider 422, 423, which are not connected to diode 420, being connected together to primary ground 8.
The leading edges of the pulses supplied by output 413 of flip-flop 41 coincide roughly with those of the line return pulses and their rear or falling edges, which occur with variable delays with respect to the leading edges, are used to trigger, eventually through an inverter stage 450, a second monostable flip-flop 45 whose output feeds the base of chopper transistor 11 to cut it off. This second monostable flip-flop 45 supplies this base with negative rectangular signals at the line frequency, of constant length, which is greater than the half period of oscillation of resonant circuit 13, 15 and hence the half period (>T H /2) and less than three quarters of this same period (<3T H /4) so as to allow transistor 11 to accept the current i 16 (t) flowing through inductor 16 when the current in diode 12 disappears.
FIG. 5 is a block diagram of a preferred production model of a regulation circuit 40 (in FIG. 1) controlling transistor 11 of chopper circuit 10 in accordance with the invention.
In FIG. 5 regulation circuit 40 has an input 401 connected to one of the terminals of auxiliary winding 25 of line transformer 20 which feeds in parallel a first control input 461 of a phase shift stage 46, the input of a regulator stage 47 and, finally, the input of a synchronizing circuit 49. The output of regulator stage 47 feeds a second regulation input 462 of phase shift stage 46, these two stages 46, 47 forming together a variable delay generator. The output of phase shift stage 46 feeds a first triggering input 481 of an unstable multivibrator 48 whose second synchronizing input 482 is fed by the output of synchronizing circuit 49. This synchronizing circuit 49, whose operation will be described further on, is only necessary if the free running oscillation frequency of multivibrator 48 is greater than the line frequency. If this is not so, multivibrator 48 is synchronized in classical fashion by the triggering pulses applied to its input 481. The output of unstable multivibrator 48 feeds the input of a driver or control stage 50 formed by an amplifier. The output of control stage 50 (called a "driver" in anglo-american litterature), which is connected to output 402 of regulation circuit 40, feeds the base of transistor 11 in chopper circuit 10.
pply capacitor 33 (FIG. 1) in output stage 30. To obtain regulation of voltage V 33 , the phase shift must increase with the value of this voltage to regulate the transfer of energy between circuits 10 and 30. As a result, the slope of the saw tooth must decrease with the increase in amplitude of the return pulse. The comparator stage of phase shift circuit 46 feeds triggering input 481 of unstable multivibrator 48 to trigger it with a variable phase shift with respect to the leading edge of the return pulse, which corresponds to the energy transfer desired. Unstable multivibrator 48 is, preferably, synchronized in frequency with line sweep output stage 30 in a way which will be explained later by means of synchronizing circuit 49 which feeds its synchronizing input 482. The output of multivibrator 48 feeds the input of driver stage 50 for chopper transistor 11.
To enable the chopper circuit 10 to start up before the line sweep circuit is running and, in particular, its output stage 30, unstable multivibrator 48 must oscillate independantly and stage 50 must amplify the roughly square wave signal it supplies. For this purpose, an independant D.C. power supply voltage source 51 is connected to supply terminals 1, 2 of the A.C. mains and the voltage it supplies feed supply terminals 403, 404 and 405 of regulation circuit 40. When chopper circuit 10 starts operating independantly when the line sweep circuit containing in series a line oscillator, a driver stage and output stage 30 is not being fed, the chopper current i 16 (t) passing through power supply winding 21 is induced in winding 22 and it is rectified by the second diode 35 which charges positively power supply capacitor 33 which then also feeds the other stages of the sweep circuit with a D.C. voltage so that they start up. This starting up and the resulting regulation will be explained more in detail in what follows.
FIG. 6 is a theoretical schematic diagram of the preferred production model of regulation circuit 40 whose block diagram was shown in FIG. 5.
In
FIG. 6, power supply voltage source 51 of regulation circuit 40
contains a rectifier assembly 52 of the voltage doubler type operating
on a half wave with two diodes 521, 522 in series. The first diode 521
is connected by its anode to the second terminal 2 of the supply from
the mains, which is connected to the primary ground 8 and by its
cathode to the anode of the second diode 522 whose cathode is
connected to the positive plate of a first chemical filter capacitor
523. The negative plate of the first filter capacitor 523 is connected
to the anode of the first diode 521 and hence also to primary ground
8. The junction of the cathode of first diode 521 and the anode of
second diode 522 is coupled to the first terminal 1 of the power
supply from the mains through a coupling capacitor 520 which transmits
to the rectifier assembly 52 the mains voltage and whose capacity is
chosen as a function of the D.C. voltage desired (the voltage drop at
the terminals of this capacity 520 of the order of a few microfarads
makes it possible to obtain a rectified and filtered voltage of about
15 Volts). The junction of the positive plate of first filter
capacitor 523 is connected to the positive plate of a second filter
capacitor 524 through a resistor 525, the negative plate of this
second capacitor 524 being connected to primary ground 8. The positive
terminal of this second capacitor 524 supplies a first rectified and
filtered voltage V F , on the one hand, through the first output
terminal 510 of source 51 to the first positive power supply terminal
404 of regulation circuit 40 and, on the other hand, to a stabilizing
assembly 53 containing in series a resistor 531 and a Zener diode 530
whose anode is connected to primary ground 8. The junction of resistor
530 with the cathode of Zener diode 530 is connected to the second
output 511 of source 51, which supplies a second regulated voltage V R
that feeds the second power supply input 403 of regulation circuit
40.
The
first power supply input 404, which supplies a first voltage V F (15
V) that is higher than the second regulated voltage V R (5 V), only
feeds control stage 50 of chopper transistor 11. Control stage 50
contains in series a phase shift stage 500 (called a "phase splitter"
in anglo-american litterature) and an output stage 550 of the "series
push-pull" type often used in integrated logic circuits of the TTL
type. Phase splitter 500 contains a first NPN transistor 501 whose
collector is connected through a collector resistor 502 to the first
power supply input 404 and whose emitter is connected through an
emitter resistor 503 to primary ground 8 through the third power supply
terminal 405 of circuit 40. The base of transistor 501 is connected
to the output of unstable multivibrator 48 through a diode 504 and to
the second power supply input 403 through a polarizing resistor 505.
Output stage 550 contains a second and third NPN transistors 551 and
552. The collector of the second transistor 551 is connected through a
resistor 553 to the first power supply input 404, its base being
connected to the collector of the first transistor 501. The emitter of
the second transistor 551 is connected to the anode of a diode 554
whose cathode is connected to the collector of the third transistor
552. The base of the third transistor 552 is connected to the emitter
of the first 501 and its emitter, through the third power supply
terminal 405, to primary ground 8. The junction of the cathode of diode
554 with the collector of third transistor 552 is connected to the
cathode of a Zener diode 555 and to the positive plate of a chemical
capacitor 556, mounted in parallel to form a "battery" which
facilitates the cutting off of switching transistor 11. The other
terminal of the parallel assembly 555, 556 is connected, through an
inductor 557 (choke) to the output 402 of regulation circuit 40, which
feeds the base of switching transistor 11.
Control
stage 50 is controlled by an unstable multivibrator 48 of the
symmetrical type containing two NPN transistors 480, 483 mounted with
their emitters common, i.e. with their emitters connected through the
third power supply terminal 405 to primary ground 8. The collectors of
the two transistors 480, 483 are connected respectively to the second
power supply input 403, which receives the stabilized voltage V R ,
through two collector resistors 484, 485. The bases of the two
transistors 480, 483 are connected respectively by means of two
polarizing resistors 486, 487 also to the second power supply input
403. The base of first transistor 480 is also coupled to the collector
of second transistor 483 through a first capacitor 488 and the base
of second transistor 483 is coupled to the collector of the first 480
through a second capacitor 489. The respective values of the
polarizing resistors 486, 487 and of the mutual coupling capacitors
488, 489 (crossed) of the two stages mounted with their emitters
common determine, with the value of the stabilized power supply
voltage V R , the lengths of the half periods of relaxation of
multivibrator 48 whose sum (60 μsec) is chosen, preferably, less than
that of a line period (64 μsec).
In the absence of line return pulses coming from the line sweep output stage 30 through auxiliary winding 25, multivibrator 48 is fed neither at its triggering input 481, which is connected to the cathode of a first diode 4802 whose anode is connected to the base of the second transistor 483, nor at its synchronizing input 482 which is connected to the cathode of a second diode 4803 whose anode is connected to the base of the first transistor 480. It will operate independantly then as soon as voltage is applied to the mains power supply terminals 1, 2 which feed, on the one hand, rectifier assembly 5 and, on the other, independant power supply 51. The power supply then provides multivibrator 48 with a stabilized power supply voltage V R and the driver stage 50 with a rectified filtered voltage V F . When multivibrator 48 starts to oscillate, it supplies at its output formed by the collector of its second transistor 483 rectangular signals of two levels (V R and V CEsat ), the lowest of which, through coupling diode 504, causes the cut off of the first transistor 501 in control stage 50. When the first transistor 501 is cut off, the base of the second transistor 551 in output stage 50 is connected, through the collector resistor 502, to the first power supply input 404 in circuit 40 so as to saturate it. The emitter current of second transistor 551 then passes, through the diode 554, the Zener diode 555 and inductor 557 (which limits the rate of rise of the current di/dt), in resistor 19 connecting the base of chopper transistor 11 to primary ground 8 and in this base in order to allow the saturation of chopper transistor 11, the third transistor 552 then being cut off by the cut off of the first 501. The voltage drop at the terminals of Zener diode 555 enables the positive polarizing voltage of the base to be reduced and the capacitor 556 to be charged to the Zener voltage V Z during its periods of conduction.
When the second transistor 483 of multivibrator 48 has switched from its saturated to its cut off state, its collector voltage is equal to the stabilized voltage V R and diode 504 cuts off. The base of first transistor 501 in control stage 50 is then connected to the second power supply input 403 (+V R ) through resistor 505, which causes it to saturate. Then the emitter current of this first transistor 501 feeds the base of the third transistor 552 which also becomes saturated while the second transistor 551, whose base is at a voltage (V CEsat 501 +V BE 552), which is roughly equal to that of its emitter (V F 554 +V CEsat 552), cuts off. The saturation of the third transistor 552 first brings the base of chopper transistor 11 to a negative voltage with respect to its emitter V BE 11 =-V Z +V CEsat 552 so as to cut it off rapidly by a rapid evacuation of the minority carriers in its base, this voltage V BE 11 then tending asymptotically to zero because the capacitor 556 discharges through resistor 19 and the third transistor 552 saturated. Chopper transistor 11 will remain cut off during the whole half period of oscillation of the resonant circuit L 16 , C 13 and will only accept the current of diode 12 afterwards if it is already positively polarized on its base by the switching of multivibrator 48 to the state in which its second transistor 483 again becomes saturated so as to cut off first transistor 501 and again saturate second transistor 551 in control circuit 50.
The alternate cut off and conduction of bidirectional switch 15 causes the appearance at terminal 19 of recurrent half sinusoids of voltage, shown by the diagrams (D) in FIGS. 2 and 3, a fraction of which is also present at the terminals of power supply winding 21 of line transformer 20, from where they are transmitted with a phase inversion (polarity) but without a D.C. component to winding 22 of line sweep output stage 30. The negative half cycles of its wave forms on terminal 220 of the winding are then rectified by the parallel ("shunt") recovery diode 35 whose current charges power supply capacitor 33 until the voltage V 33 on terminal 221, which feeds the whole of the line sweep circuit, is sufficient for the line oscillator (which is not shown) to start oscillating independantly, so as to control, through the driver stage (not shown), switching transistor 36 in output stage 30. Line sweep output stage 30 then starts to supply, at the terminals of winding 22 of line transformer 20, line return pulses v 220 (t), which are illustrated by the diagrams (B) in FIGS. 2 and 3. These pulses are transmitted to auxiliary winding 25 without a D.C. component and with (negative) phase inversion so as to have a wave shape analogous to that of the diagrams (C) in FIGS. 2 and 3, which makes possible first the synchronization of multivibrator 48 with the line oscillator frequency using an original slaving device which will be described further on and then the regulation of voltage V 33 by varying the delay between the leading edges of the line return pulses and the instant when chopper transistor 11 in switch 15 is cut off.
When
multivibrator 48 and the line oscillator operate independantly and at
different frequencies, this produces a beat because there are random
phase variations between the line return pulses, v 220 (t) or v 21
(t), and the wave form of the chopper voltage v 19 (t), so that the
energy supplied (or consumed) by chopper circuit 10 to (or from)
output stage 30 varies from one cycle to another. This has as visible
result a more or less big fluctuation in the amplitude of the line
return pulses v 220 (t) which seem to be modulated in amplitude by a
sinusoidal signal whose frequency is equal to the difference between
that of multivibrator 48 and that of the line oscillator.
If one chooses to synchronize unstable multivibrator 48 in classical fashion soleby by means of periodic control pulses derived from the line return pulses through a variable delay circuit allowing regulation, it is sufficient for the independant oscillation frequency to be less than that of the line oscillator. One then obtains on starting up peak voltages V 19 , which are higher (overvoltages) on the collector of transistor 11 when it is cut off because, in the formula V 19max t B =V Amax T 48A , in which V 19max is the peak amplitude of the collector voltage (on terminal 19), t B the time during which switch 15 is cut off, V Amax the maximum supply voltage supplied by rectifier 5 and T 48A the free running period of multivibrator 48, T 48A being greater than T H . If one accepts this overvoltage V 19max and limits it by a choice of the saturation time t S slightly higher than the cut off time t B1 which is always equal to the half period of oscillation of L 16 and C 13 , it will not be necessary to slave multivibrator 48 before regulation and synchronizing circuit 49 can be omitted.
If, on the other hand, one wishes to avoid the excesses of the collector peak voltage V 19max on starting up, one chooses a free running period T 48A for multivibrator 48 less than the line period T H (64 μsec) and one synchronizes by acting only on the length of the cut off state of first transistor 480 in multivibrator 48 by lengthening it. During this same time interval, second transistor 483 of multivibrator 48 and second transistor 551 of driver stage 50 are saturated and the first 501 and third 552 transistors of this stage 50 are cut off so that the base of chopper transistor 11 is polarized to conduct.
This
lengthening is done by means of a network 49 containing a diode 490
whose cathode is connected to the input 401 of regulation circuit 40
which receives the line return pulses from winding 25 with negative
polarity and no D.C. component. The anode of diode 490 is connected to
that of a Zener diode 491 whose cathode is connected to one of the
terminals of a first resistor 492. The other terminal of this first
resistor 492 is connected, on the one hand through a second resistor
493, to the synchronizing input 482 of unstable multivibrator 48 and, on
the other hand through a third resistor 494, to the collector of the
second transistor 483 in the multivibrator so that the line return
pulse, negative and with its base cut off by Zener diode 491, cannot act
on the base of the first transistor 480 during its periods of
saturation so as to cut it off at the wrong time.
The process of slaving the frequency of multivibrator 48 by means of the line return pulses is shown by the diagrams of the wave forms in FIG. 7.
In FIG. 7, the diagram A represents the wave form at the terminals of auxiliary winding 25 of the line transformer 20 where line return pulses appear in the form of negative half sinusoids of amplitude V 25 at the line frequency (15.626 Hz). The diagram B shows the wave form of the voltage v BE 480 on the base of the first transistor 480. This wave form contains a first time interval t SA during which chopper switch 15 is conducting and transistor 480 is cut off. This time interval depends solely on the value of the components connected to this base, specifically the resistor 486 and the capacitor 488 and the supply voltage V R for this resistor 484. This wave form also contains a second time interval t B of fixed length during which chopper switch 15 is cut off and transistor 480 saturated. The sum of the intervals t SA and t B represents the period of independent operation T A of multivibrator 48 (of the order of 58 μsec for example).
In
FIG. 7 the first three periods of free running operation of
multivibrator 48 are not changed because either the line return pulse
occurs outside the cut off interval t SA of transistor 480 or its
amplitude, with its base cut off by Zener diode 491 and reduced by the
resistive voltage divider 492, 494, i.e. (V 25 -V Z 491)R 494 /(R 492
+R 494 ), is less in absolute value than the instantaneous
base-emitter voltage v BE 480 (t). From the instant at which the
cathode of the separator diode 4803 becomes more negative than its
anode, which is connected to the base of transistor 480, it begins to
conduct a current I 493 which discharges capacitor 488 through the
resistor 493 in series with the resistors 492 and 494 in parallel.
Current I 493 must be subtracted from the current I 486 , which is
charging the capacitor, during the whole of the time the amplitude of
the line return pulse exceeds the voltage v BE . The effect of this is
to shift in time a part of the charging wave form of capacitor 496
and thus lengthen the cut off time t SA of transistor 480 by a time Δt
S which will increase until the lengthened period of multivibrator 48
is equal to the line period T H . Because the conduction time of
switch 15 is lengthened, the energy stored in inductor 16 increases.
This increases the voltage V 33 and the amplitude of the line return
pulse.
The process of slaving multivibrator 48 in frequency must of necessity lead to equality of these periods because an inequality gives rise to a variation in the peak amplitude of the line return pulse in a direction which affects the length of cut off time t SA +Δt S of transistor 480 in the opposite direction.
After
the slaving of the frequency of unstable multivibrator 48 one can go
on to the regulation by varying the phase shift between the respective
cut off instants of the sweep transistor 36 and chopper transistor 11
by means of the phase shift 46 and regulator 47 stages in regulation
circuit 40, which together form the variable delay generator.
Phase shift stage 46 contains a saw tooth generator which includes a first capacitor 460, one of whose terminals is connected to primary ground 8 while the other terminal is connected to one of the terminals of a first resistor 463 whose other terminal is connected to the second power supply input 403 which receives the stabilized voltage +V R , and a switch, which is intended to short-circuit the first capacitor 460 periodically. This switch contains a first NPN switching transistor 464 whose collector is connected to the junction of first capacitor 460 and first resistor 463, its emitter being connected to primary ground 8 and its base, through a second resistor 465, to the second power supply input 403 and, through a third resistor 466, to the anode of a diode 467, whose cathode is connected to the control input 461 of phase shift stage 46 which receives negative line return pulses from input 401 of circuit 40. The base of first transistor 464 is also coupled to primary ground 8 through a second capacitor 468.
When input 401 of circuit 40 receives a negative line return pulse, diode 467 starts to conduct and its current causes voltage drops at the terminals of resistors 465, 466 in series which brings transistor 464 to cut off by polarizing it negatively. Second capacitor 468 then charges to a negative voltage which will extend the length of the cut off of transistor 464 beyond the disappearance of the line return pulse for a part of the forward sweep period in order to have a sufficient regulation range available.
When the negative return pulse ceases, diode 467 cuts off and second capacitor 468 is charged gradually through resistor 465 to a positive voltage V BE of about 0.7 Volts, at which transistor 464 becomes saturated and discharges first capacitor 460.
During the cut off period of first transistor 464, first capacitor 460 is charged almost linearly through resistor 463 and supplies a voltage of positive saw tooth shape to the base of a second NPN transistor 469, whose collector is connected,
through a fourth resistor 4600, to the second power supply terminal
403 (V R =+5 V). The emitter of second transistor 469 is connected, on
the one hand, to the cathode of a Zener diode 4601 whose anode is
connected to primary ground 8 and, on the other hand, to the second
power supply terminal 403 through a fifth resistor 4602 which makes it
possible to polarize the emitter of second transistor 469 at a fixed
voltage V Z (between 2 and about 3 Volts).
Second transistor 469 forms, with resistors 4600, 4602 and Zener diode 4601, an analog voltage comparator stage which is cut off until the voltage applied at its base exceeds a threshold voltage resulting from the addition of Zener voltage V Z of diode 4601 to the voltage V BEm of about 0.7 Volts at which second transistor 469 saturated.
When second transistor 469 passes from its cut off state to its saturated state, its collector voltage v C 469 changes from V R to V Z +V CEsat . This negative change is transmitted through a coupling capacitor 4603 to the triggering input 481 of unstable multivibrator 48 which is connected, on the one hand, to the cathode of the first diode 4802 whose anode is connected to the base of the second transistor 483 and, on the other hand, to the first terminals of two resistors 4800 and 4801 which form a resistive voltage divider and whose second terminals are respectively connected to primary ground 8 and to the second power supply terminal 403 of circuit 40. This negative change, when transmitted to the base of second transistor 483 in multivibrator 48, causes it to cut off and, in the manner already described, the coppice of chopper transistor 11 also.
The regulation of the power transmitted by chopper circuit 10 to line sweep output stage 30 is obtained by the variation of the phase shift between the respective cut off instants of the sweep 36 and chopper 11 transistors by means of the regulator stage 47 which causes the charging voltage slope of the capacitor 460 to vary as a function of one of the parameters contained in the line return pulse.
The combined operation of the phase shift 46 and regulator 47 stages will be explained by means of FIG. 8, which illustrates the voltage wave forms at three points of these circuits 46, 47.
Regulator stage 47 contains a diode 470 whose cathode is connected to the input 401 of circuit 40, which receives the negative polarity line return pulses and whose anode is connected to the negative plate of a filter capacitor 471 and to one of the terminals of a resistive voltage divider containing a potentiometer 472 between two resistors 473, 474 in series and to the anode of a Zener diode 475. The cathode of Zener diode 475 is connected, on the one hand, to one of the terminals of a third resistor 477 whose other terminal is connected to primary ground 8 and, on the other hand, to the emitter of an NPN transistor 476 whose base is connected to the slider arm of potentiometer 472 and whose collector is connected to the regulation input 462 of the phase shift stage 46, which is connected to the junction of its first capacitor 460 with its first resistor 463 and the collector of its first transistor 464.
Diode 470 forms with capacitor 471 a rectifier of the negative peaks of the line return pulses, capacitor 471 supplying at its terminals a voltage which is a function of the negative peak amplitude of the line return.
This rectified peak voltage is applied, on the one hand, to the resistive divider assembly, 472-474, so that the slider arm of potentiometer 472 supplies a voltage which is a predetermined adjustable fraction of that voltage and, on the other hand, to the series assembly of Zener diode 475 and resistor 477 which polarizes this diode 475. As soon as the amplitude of the line return pulses exceeds the Zener voltage V Z of diode 475, it is opened up so as to supply at its cathode a voltage equal to the difference between the rectified peak voltage and the Zener voltage V Z . The cathode voltage of Zener diode 475 polarizes the emitter of transistor 476 whose base is polarized by divider assembly 472-474 and which starts to conduct as soon as the fraction of the rectified voltage supplied by the slider arm of the potentiometer is greater than the Zener voltage V Z in absolute value. Transistor 476 then forms a source of constant current proportional to its base-emitter voltage V BE , i.e. to V B -V Z when the latter is positive. The collector current of transistor 476 is therefore a current which discharges capacitor 460 during the intervals when transistor 464 is cut off so as to reduce the slope of the saw tooth voltage at the terminals of capacitor 460. The bigger the negative peak voltage of the line return pulses, the more the collector current of transistor 476 reduces the slope so as to increase the delay time between the leading edge of the line return pulse and the instant of change of the comparator transistor 469 from its cut off to its saturated state.
This
is indicated in FIG. 8, in which the diagram (A) shows the voltage
wave form v 25 (t) at the terminals of auxiliary winding 25 whose line
return pulses are of three different amplitudes V 25B , V 25F and V
25N , the diagram (B) represents the voltage wave form at the
terminals of capacitor 460 corresponding to these three line return
pulses and the diagram (C) represents the collector voltage v 469 (t)
of comparator transistor 469.
In diagram (A) in FIG. 8, the first line return pulse is of a relatively small amplitude V 25B which does not cause the conduction of regulation transistor 476. To this corresponds in diagram (B) the steepest slope of the voltage wave v 460 (t) which starts at the instant t 1 of cut off of first transistor 464 in phase shift circuit 46 and the shortest length T B =t 2 -t 1 of this cut off because of the smaller negative charge of capacitor 468. At the instant t 2 , when voltage v 460 (t) becomes equal to V Z +V BEm , it no longer increases because the diode formed by the base-emitter junction of second transistor 469 limits the maximum level of this voltage and transistor 469 becomes saturated. This is illustrated by the diagram (C) in FIG. 8, in which one can see that the collector voltage v C 469 of second transistor 469 contains a negative square wave whose level is equal to V Z +V CEsat and which lasts until the instant t 3 of the opening up of the first transistor 464 which discharges capacitor 460 and, as a result, cuts off second transistor 469.
Because of the small phase delay t RB =t 2 -t 1 produced by the fast rise of the voltage v 460 (t), chopper circuit 10 supplies maximum energy to output stage 30 in the form of a high voltage V 33 at the terminals of the power supply capacitor 33. As a result, the next line return pulse will be of large amplitude V 25F . The comparator transistor 476 starts to conduct as soon as V BE becomes positive and the greater the amplitude V 25F to which the capacitor 471 charges, the greater the collector current. This collector current is to be subtracted from the charging current of capacitor 460 through the resistor 463. Hence, it causes a noticeable reduction in the slope of the rise in the voltage v 460 (t) which occurs between the instants t 4 and t 5 . The length of this rise, which corresponds to the phase delay t RF =t 5 -t 4 , will then be noticeably longer than before as well as the length of the cut off state T F of the first transistor 464. One can see then in the three diagrams that, when V 25F is large, the delay t RF is longer and the length of the negative pulse T F -t RF is slightly shorter.
This longer delay causes a reduction in the voltage V 33 compared with the preceding cycle in which it was too big and the next line return pulse (the third) will be of an amplitude V 25N greater than V 25B and less than V 25F . It will make it possible to obtain, by means of the corresponding collector current of the regulation transistor 476, a slope in which the rise from a voltage V CEsat near zero to a voltage V Z +V BEm is of a length equal to t RN =t 7 -t 6 . If the slider arm of potentiometer 472 has been so placed that the power supply voltage V 33 makes it possible to obtain a very high voltage for the cathode ray tube (which is not shown) and/or an amplitude of the horizontal sweep current saw tooth corresponding to their respective nominal values, the nominal amplitude V 25N of the line return pulse will be reproduced afterwards in recurrent fashion.
It is to be noted here that one can also use as a regulation criterion the positive amplitude of the signal v 25 (t), i.e. the positive plane whose level is proportional to the power supply voltage V 33 by using an analog phase inverter or another winding of line transformer 20 for example.
One will note also here that the main advantage of the regulation by the phase shift of a chopper circuit operating with a constant cyclic ratio and frequency, compared with that by the variation of one of them, is formed by the fact that the peak voltage applied to the collector of the chopper transistor, when it is cut off, is a function only of the mains voltage.
SALORA 28M91 CHASSIS M CHASSIS SALORA STB253 110° DIGITAL (SALORA M-CHASSIS ) Regulated power supply incorporating a power transformer having a tightly coupled supplemental power transfer winding :
A
regulated power supply for a television receiver includes a
transformer having a primary winding coupled to a source of unregulated
voltage. A transistor switch controls the interval during which the
unregulated voltage causes current to flow in the primary winding.
By transformer action, power is transferred to secondary windings
which are coupled to receiver load circuits. The secondary winding
voltages are regulated by control of the primary winding conduction
interval. A supplemental winding is layer wound over the primary
winding to transfer additional power to the load circuits. The
primary winding may be electrically isolated from the secondary
windings and from the supplemental winding.
1. A regulated power supply for a television receiver incorporating a plurality of load circuits comprising:
an unregulated voltage source electrically isolated from said load circuits;
a transformer core having first and second transformer core legs;
a first transformer winding, wound on said first transformer core leg and having first and second terminals, said first terminal coupled to and electrically nonisolated from said unregulated voltage source;
means, coupled to said first transformer winding second terminal for selectively energizing said first winding from said unregulated voltage source;
a second transformer winding, wound on said second transformer core leg, electrically isolated from said first transformer winding, for powering a given one of said load circuits in response to the energization of said first transformer winding;
means for controlling the operation of said energizing means to maintain a constant voltage supply for said load circuits; and
a third transformer winding electrically isolated from said first transformer winding and wound on said first transformer core leg to overlay said first transformer winding for powering at least one of said load circuits in response to the energization of said first transformer winding.
2.
The
arrangement defined in claim 1, wherein said means for selectively
energizing said first winding comprises a transistor switch.
3. The arrangement defined in claim 1,
wherein said means for controlling the operation of said energizing
means comprises a pulse width modulator.
4. The arrangement defined in claim 1, further comprising
a plurality of transformer load windings wound on said second
transformer core leg. 5. The
arrangement defined in claim 1, wherein said first transformer
winding is more closely coupled magnetically to said third
transformer winding than to said second transformer winding.
6. The arrangement defined in claim 1,
wherein said given one of said load circuits comprises a line
deflection circuit, said line deflection circuit developing a retrace
pulse across said second transformer winding.
7. The arrangement defined in claim 6, wherein said
energizing means causes said energization of said first transformer
winding to be terminated during the interval of said retrace pulse.
8. The arrangement defined in
claim 1, wherein energy stored in said transformer core, during the
time said first transformer winding is energized, is maintained in
said transformer core by energization of said third transformer
winding, when said first transformer winding is not energized, for
supplemental transfer to at least one of said load circuits by said
third transformer winding. 9.
The arrangement defined in claim 8, wherein substantially all of said
energy stored in said transformer core during energization of said
first transformer winding is removed before energization of said
first transformer winding reoccurs.
In the absence of line return pulses coming from the line sweep output stage 30 through auxiliary winding 25, multivibrator 48 is fed neither at its triggering input 481, which is connected to the cathode of a first diode 4802 whose anode is connected to the base of the second transistor 483, nor at its synchronizing input 482 which is connected to the cathode of a second diode 4803 whose anode is connected to the base of the first transistor 480. It will operate independantly then as soon as voltage is applied to the mains power supply terminals 1, 2 which feed, on the one hand, rectifier assembly 5 and, on the other, independant power supply 51. The power supply then provides multivibrator 48 with a stabilized power supply voltage V R and the driver stage 50 with a rectified filtered voltage V F . When multivibrator 48 starts to oscillate, it supplies at its output formed by the collector of its second transistor 483 rectangular signals of two levels (V R and V CEsat ), the lowest of which, through coupling diode 504, causes the cut off of the first transistor 501 in control stage 50. When the first transistor 501 is cut off, the base of the second transistor 551 in output stage 50 is connected, through the collector resistor 502, to the first power supply input 404 in circuit 40 so as to saturate it. The emitter current of second transistor 551 then passes, through the diode 554, the Zener diode 555 and inductor 557 (which limits the rate of rise of the current di/dt), in resistor 19 connecting the base of chopper transistor 11 to primary ground 8 and in this base in order to allow the saturation of chopper transistor 11, the third transistor 552 then being cut off by the cut off of the first 501. The voltage drop at the terminals of Zener diode 555 enables the positive polarizing voltage of the base to be reduced and the capacitor 556 to be charged to the Zener voltage V Z during its periods of conduction.
When the second transistor 483 of multivibrator 48 has switched from its saturated to its cut off state, its collector voltage is equal to the stabilized voltage V R and diode 504 cuts off. The base of first transistor 501 in control stage 50 is then connected to the second power supply input 403 (+V R ) through resistor 505, which causes it to saturate. Then the emitter current of this first transistor 501 feeds the base of the third transistor 552 which also becomes saturated while the second transistor 551, whose base is at a voltage (V CEsat 501 +V BE 552), which is roughly equal to that of its emitter (V F 554 +V CEsat 552), cuts off. The saturation of the third transistor 552 first brings the base of chopper transistor 11 to a negative voltage with respect to its emitter V BE 11 =-V Z +V CEsat 552 so as to cut it off rapidly by a rapid evacuation of the minority carriers in its base, this voltage V BE 11 then tending asymptotically to zero because the capacitor 556 discharges through resistor 19 and the third transistor 552 saturated. Chopper transistor 11 will remain cut off during the whole half period of oscillation of the resonant circuit L 16 , C 13 and will only accept the current of diode 12 afterwards if it is already positively polarized on its base by the switching of multivibrator 48 to the state in which its second transistor 483 again becomes saturated so as to cut off first transistor 501 and again saturate second transistor 551 in control circuit 50.
The alternate cut off and conduction of bidirectional switch 15 causes the appearance at terminal 19 of recurrent half sinusoids of voltage, shown by the diagrams (D) in FIGS. 2 and 3, a fraction of which is also present at the terminals of power supply winding 21 of line transformer 20, from where they are transmitted with a phase inversion (polarity) but without a D.C. component to winding 22 of line sweep output stage 30. The negative half cycles of its wave forms on terminal 220 of the winding are then rectified by the parallel ("shunt") recovery diode 35 whose current charges power supply capacitor 33 until the voltage V 33 on terminal 221, which feeds the whole of the line sweep circuit, is sufficient for the line oscillator (which is not shown) to start oscillating independantly, so as to control, through the driver stage (not shown), switching transistor 36 in output stage 30. Line sweep output stage 30 then starts to supply, at the terminals of winding 22 of line transformer 20, line return pulses v 220 (t), which are illustrated by the diagrams (B) in FIGS. 2 and 3. These pulses are transmitted to auxiliary winding 25 without a D.C. component and with (negative) phase inversion so as to have a wave shape analogous to that of the diagrams (C) in FIGS. 2 and 3, which makes possible first the synchronization of multivibrator 48 with the line oscillator frequency using an original slaving device which will be described further on and then the regulation of voltage V 33 by varying the delay between the leading edges of the line return pulses and the instant when chopper transistor 11 in switch 15 is cut off.
If one chooses to synchronize unstable multivibrator 48 in classical fashion soleby by means of periodic control pulses derived from the line return pulses through a variable delay circuit allowing regulation, it is sufficient for the independant oscillation frequency to be less than that of the line oscillator. One then obtains on starting up peak voltages V 19 , which are higher (overvoltages) on the collector of transistor 11 when it is cut off because, in the formula V 19max t B =V Amax T 48A , in which V 19max is the peak amplitude of the collector voltage (on terminal 19), t B the time during which switch 15 is cut off, V Amax the maximum supply voltage supplied by rectifier 5 and T 48A the free running period of multivibrator 48, T 48A being greater than T H . If one accepts this overvoltage V 19max and limits it by a choice of the saturation time t S slightly higher than the cut off time t B1 which is always equal to the half period of oscillation of L 16 and C 13 , it will not be necessary to slave multivibrator 48 before regulation and synchronizing circuit 49 can be omitted.
If, on the other hand, one wishes to avoid the excesses of the collector peak voltage V 19max on starting up, one chooses a free running period T 48A for multivibrator 48 less than the line period T H (64 μsec) and one synchronizes by acting only on the length of the cut off state of first transistor 480 in multivibrator 48 by lengthening it. During this same time interval, second transistor 483 of multivibrator 48 and second transistor 551 of driver stage 50 are saturated and the first 501 and third 552 transistors of this stage 50 are cut off so that the base of chopper transistor 11 is polarized to conduct.
This
lengthening is done by means of a network 49 containing a diode 490
whose cathode is connected to the input 401 of regulation circuit 40
which receives the line return pulses from winding 25 with negative
polarity and no D.C. component. The anode of diode 490 is connected to
that of a Zener diode 491 whose cathode is connected to one of the
terminals of a first resistor 492. The other terminal of this first
resistor 492 is connected, on the one hand through a second resistor
493, to the synchronizing input 482 of unstable multivibrator 48 and, on
the other hand through a third resistor 494, to the collector of the
second transistor 483 in the multivibrator so that the line return
pulse, negative and with its base cut off by Zener diode 491, cannot act
on the base of the first transistor 480 during its periods of
saturation so as to cut it off at the wrong time.The process of slaving the frequency of multivibrator 48 by means of the line return pulses is shown by the diagrams of the wave forms in FIG. 7.
In FIG. 7, the diagram A represents the wave form at the terminals of auxiliary winding 25 of the line transformer 20 where line return pulses appear in the form of negative half sinusoids of amplitude V 25 at the line frequency (15.626 Hz). The diagram B shows the wave form of the voltage v BE 480 on the base of the first transistor 480. This wave form contains a first time interval t SA during which chopper switch 15 is conducting and transistor 480 is cut off. This time interval depends solely on the value of the components connected to this base, specifically the resistor 486 and the capacitor 488 and the supply voltage V R for this resistor 484. This wave form also contains a second time interval t B of fixed length during which chopper switch 15 is cut off and transistor 480 saturated. The sum of the intervals t SA and t B represents the period of independent operation T A of multivibrator 48 (of the order of 58 μsec for example).
In
FIG. 7 the first three periods of free running operation of
multivibrator 48 are not changed because either the line return pulse
occurs outside the cut off interval t SA of transistor 480 or its
amplitude, with its base cut off by Zener diode 491 and reduced by the
resistive voltage divider 492, 494, i.e. (V 25 -V Z 491)R 494 /(R 492
+R 494 ), is less in absolute value than the instantaneous
base-emitter voltage v BE 480 (t). From the instant at which the
cathode of the separator diode 4803 becomes more negative than its
anode, which is connected to the base of transistor 480, it begins to
conduct a current I 493 which discharges capacitor 488 through the
resistor 493 in series with the resistors 492 and 494 in parallel.
Current I 493 must be subtracted from the current I 486 , which is
charging the capacitor, during the whole of the time the amplitude of
the line return pulse exceeds the voltage v BE . The effect of this is
to shift in time a part of the charging wave form of capacitor 496
and thus lengthen the cut off time t SA of transistor 480 by a time Δt
S which will increase until the lengthened period of multivibrator 48
is equal to the line period T H . Because the conduction time of
switch 15 is lengthened, the energy stored in inductor 16 increases.
This increases the voltage V 33 and the amplitude of the line return
pulse.The process of slaving multivibrator 48 in frequency must of necessity lead to equality of these periods because an inequality gives rise to a variation in the peak amplitude of the line return pulse in a direction which affects the length of cut off time t SA +Δt S of transistor 480 in the opposite direction.
Phase shift stage 46 contains a saw tooth generator which includes a first capacitor 460, one of whose terminals is connected to primary ground 8 while the other terminal is connected to one of the terminals of a first resistor 463 whose other terminal is connected to the second power supply input 403 which receives the stabilized voltage +V R , and a switch, which is intended to short-circuit the first capacitor 460 periodically. This switch contains a first NPN switching transistor 464 whose collector is connected to the junction of first capacitor 460 and first resistor 463, its emitter being connected to primary ground 8 and its base, through a second resistor 465, to the second power supply input 403 and, through a third resistor 466, to the anode of a diode 467, whose cathode is connected to the control input 461 of phase shift stage 46 which receives negative line return pulses from input 401 of circuit 40. The base of first transistor 464 is also coupled to primary ground 8 through a second capacitor 468.
When input 401 of circuit 40 receives a negative line return pulse, diode 467 starts to conduct and its current causes voltage drops at the terminals of resistors 465, 466 in series which brings transistor 464 to cut off by polarizing it negatively. Second capacitor 468 then charges to a negative voltage which will extend the length of the cut off of transistor 464 beyond the disappearance of the line return pulse for a part of the forward sweep period in order to have a sufficient regulation range available.
When the negative return pulse ceases, diode 467 cuts off and second capacitor 468 is charged gradually through resistor 465 to a positive voltage V BE of about 0.7 Volts, at which transistor 464 becomes saturated and discharges first capacitor 460.
During the cut off period of first transistor 464, first capacitor 460 is charged almost linearly through resistor 463 and supplies a voltage of positive saw tooth shape to the base of a second NPN transistor 469, whose collector is connec
ted,
through a fourth resistor 4600, to the second power supply terminal
403 (V R =+5 V). The emitter of second transistor 469 is connected, on
the one hand, to the cathode of a Zener diode 4601 whose anode is
connected to primary ground 8 and, on the other hand, to the second
power supply terminal 403 through a fifth resistor 4602 which makes it
possible to polarize the emitter of second transistor 469 at a fixed
voltage V Z (between 2 and about 3 Volts).Second transistor 469 forms, with resistors 4600, 4602 and Zener diode 4601, an analog voltage comparator stage which is cut off until the voltage applied at its base exceeds a threshold voltage resulting from the addition of Zener voltage V Z of diode 4601 to the voltage V BEm of about 0.7 Volts at which second transistor 469 saturated.
When second transistor 469 passes from its cut off state to its saturated state, its collector voltage v C 469 changes from V R to V Z +V CEsat . This negative change is transmitted through a coupling capacitor 4603 to the triggering input 481 of unstable multivibrator 48 which is connected, on the one hand, to the cathode of the first diode 4802 whose anode is connected to the base of the second transistor 483 and, on the other hand, to the first terminals of two resistors 4800 and 4801 which form a resistive voltage divider and whose second terminals are respectively connected to primary ground 8 and to the second power supply terminal 403 of circuit 40. This negative change, when transmitted to the base of second transistor 483 in multivibrator 48, causes it to cut off and, in the manner already described, the coppice of chopper transistor 11 also.
The regulation of the power transmitted by chopper circuit 10 to line sweep output stage 30 is obtained by the variation of the phase shift between the respective cut off instants of the sweep 36 and chopper 11 transistors by means of the regulator stage 47 which causes the charging voltage slope of the capacitor 460 to vary as a function of one of the parameters contained in the line return pulse.
The combined operation of the phase shift 46 and regulator 47 stages will be explained by means of FIG. 8, which illustrates the voltage wave forms at three points of these circuits 46, 47.
Regulator stage 47 contains a diode 470 whose cathode is connected to the input 401 of circuit 40, which receives the negative polarity line return pulses and whose anode is connected to the negative plate of a filter capacitor 471 and to one of the terminals of a resistive voltage divider containing a potentiometer 472 between two resistors 473, 474 in series and to the anode of a Zener diode 475. The cathode of Zener diode 475 is connected, on the one hand, to one of the terminals of a third resistor 477 whose other terminal is connected to primary ground 8 and, on the other hand, to the emitter of an NPN transistor 476 whose base is connected to the slider arm of potentiometer 472 and whose collector is connected to the regulation input 462 of the phase shift stage 46, which is connected to the junction of its first capacitor 460 with its first resistor 463 and the collector of its first transistor 464.
Diode 470 forms with capacitor 471 a rectifier of the negative peaks of the line return pulses, capacitor 471 supplying at its terminals a voltage which is a function of the negative peak amplitude of the line return.
This rectified peak voltage is applied, on the one hand, to the resistive divider assembly, 472-474, so that the slider arm of potentiometer 472 supplies a voltage which is a predetermined adjustable fraction of that voltage and, on the other hand, to the series assembly of Zener diode 475 and resistor 477 which polarizes this diode 475. As soon as the amplitude of the line return pulses exceeds the Zener voltage V Z of diode 475, it is opened up so as to supply at its cathode a voltage equal to the difference between the rectified peak voltage and the Zener voltage V Z . The cathode voltage of Zener diode 475 polarizes the emitter of transistor 476 whose base is polarized by divider assembly 472-474 and which starts to conduct as soon as the fraction of the rectified voltage supplied by the slider arm of the potentiometer is greater than the Zener voltage V Z in absolute value. Transistor 476 then forms a source of constant current proportional to its base-emitter voltage V BE , i.e. to V B -V Z when the latter is positive. The collector current of transistor 476 is therefore a current which discharges capacitor 460 during the intervals when transistor 464 is cut off so as to reduce the slope of the saw tooth voltage at the terminals of capacitor 460. The bigger the negative peak voltage of the line return pulses, the more the collector current of transistor 476 reduces the slope so as to increase the delay time between the leading edge of the line return pulse and the instant of change of the comparator transistor 469 from its cut off to its saturated state.
This
is indicated in FIG. 8, in which the diagram (A) shows the voltage
wave form v 25 (t) at the terminals of auxiliary winding 25 whose line
return pulses are of three different amplitudes V 25B , V 25F and V
25N , the diagram (B) represents the voltage wave form at the
terminals of capacitor 460 corresponding to these three line return
pulses and the diagram (C) represents the collector voltage v 469 (t)
of comparator transistor 469.In diagram (A) in FIG. 8, the first line return pulse is of a relatively small amplitude V 25B which does not cause the conduction of regulation transistor 476. To this corresponds in diagram (B) the steepest slope of the voltage wave v 460 (t) which starts at the instant t 1 of cut off of first transistor 464 in phase shift circuit 46 and the shortest length T B =t 2 -t 1 of this cut off because of the smaller negative charge of capacitor 468. At the instant t 2 , when voltage v 460 (t) becomes equal to V Z +V BEm , it no longer increases because the diode formed by the base-emitter junction of second transistor 469 limits the maximum level of this voltage and transistor 469 becomes saturated. This is illustrated by the diagram (C) in FIG. 8, in which one can see that the collector voltage v C 469 of second transistor 469 contains a negative square wave whose level is equal to V Z +V CEsat and which lasts until the instant t 3 of the opening up of the first transistor 464 which discharges capacitor 460 and, as a result, cuts off second transistor 469.
Because of the small phase delay t RB =t 2 -t 1 produced by the fast rise of the voltage v 460 (t), chopper circuit 10 supplies maximum energy to output stage 30 in the form of a high voltage V 33 at the terminals of the power supply capacitor 33. As a result, the next line return pulse will be of large amplitude V 25F . The comparator transistor 476 starts to conduct as soon as V BE becomes positive and the greater the amplitude V 25F to which the capacitor 471 charges, the greater the collector current. This collector current is to be subtracted from the charging current of capacitor 460 through the resistor 463. Hence, it causes a noticeable reduction in the slope of the rise in the voltage v 460 (t) which occurs between the instants t 4 and t 5 . The length of this rise, which corresponds to the phase delay t RF =t 5 -t 4 , will then be noticeably longer than before as well as the length of the cut off state T F of the first transistor 464. One can see then in the three diagrams that, when V 25F is large, the delay t RF is longer and the length of the negative pulse T F -t RF is slightly shorter.
This longer delay causes a reduction in the voltage V 33 compared with the preceding cycle in which it was too big and the next line return pulse (the third) will be of an amplitude V 25N greater than V 25B and less than V 25F . It will make it possible to obtain, by means of the corresponding collector current of the regulation transistor 476, a slope in which the rise from a voltage V CEsat near zero to a voltage V Z +V BEm is of a length equal to t RN =t 7 -t 6 . If the slider arm of potentiometer 472 has been so placed that the power supply voltage V 33 makes it possible to obtain a very high voltage for the cathode ray tube (which is not shown) and/or an amplitude of the horizontal sweep current saw tooth corresponding to their respective nominal values, the nominal amplitude V 25N of the line return pulse will be reproduced afterwards in recurrent fashion.
It is to be noted here that one can also use as a regulation criterion the positive amplitude of the signal v 25 (t), i.e. the positive plane whose level is proportional to the power supply voltage V 33 by using an analog phase inverter or another winding of line transformer 20 for example.
One will note also here that the main advantage of the regulation by the phase shift of a chopper circuit operating with a constant cyclic ratio and frequency, compared with that by the variation of one of them, is formed by the fact that the peak voltage applied to the collector of the chopper transistor, when it is cut off, is a function only of the mains voltage.
SALORA 28M91 CHASSIS M CHASSIS SALORA STB253 110° DIGITAL (SALORA M-CHASSIS ) Regulated power supply incorporating a power transformer having a tightly coupled supplemental power transfer winding :
A
regulated power supply for a television receiver includes a
transformer having a primary winding coupled to a source of unregulated
voltage. A transistor switch controls the interval during which the
unregulated voltage causes current to flow in the primary winding.
By transformer action, power is transferred to secondary windings
which are coupled to receiver load circuits. The secondary winding
voltages are regulated by control of the primary winding conduction
interval. A supplemental winding is layer wound over the primary
winding to transfer additional power to the load circuits. The
primary winding may be electrically isolated from the secondary
windings and from the supplemental winding.1. A regulated power supply for a television receiver incorporating a plurality of load circuits comprising:
an unregulated voltage source electrically isolated from said load circuits;
a transformer core having first and second transformer core legs;
a first transformer winding, wound on said first transformer core leg and having first and second terminals, said first terminal coupled to and electrically nonisolated from said unregulated voltage source;
means, coupled to said first transformer winding second terminal for selectively energizing said first winding from said unregulated voltage source;
a second transformer winding, wound on said second transformer core leg, electrically isolated from said first transformer winding, for powering a given one of said load circuits in response to the energization of said first transformer winding;
means for controlling the operation of said energizing means to maintain a constant voltage supply for said load circuits; and
a third transformer winding electrically isolated from said first transformer winding and wound on said first transformer core leg to overlay said first transformer winding for powering at least one of said load circuits in response to the energization of said first transformer winding.
2.
Description:
This
invention relates to regulated power supplies for television
receivers and in particular to switched mode power supplies having
transformers for regulating load circuit voltages.
Many of the circuits in television receivers require carefully regulated power supplies in order to operate properly. For example, if the horizontal and vertical deflection circuit supply voltages are permitted to vary in an uncontrolled manner, the size of the scanned raster may change, producing an undesirable visual effect. Additional receiver circuits may be subject to excessive electrical stresses or may be damaged if supply voltages are not held within acceptable limits.
One type of voltage regulating circuit utilizes a silicon controlled rectifier (SCR) coupled to an unregulated voltage source developed from the ac line. During conduction of the SCR, current flow from the unregulated supply charges a capacitor, establishing a regulated voltage level. The conduction time of the SCR is controlled to maintain a fixed regulated voltage level. Decreases in the ac line voltage or increased circuit loading will cause an increase in the SCR conduction time and an increase in line voltage will result in a decrease in SCR conduction time.
The
previously described SCR regulated power supply is not economically
incorporated in a receiver which provides input and output
terminals electrically isolated from the ac line. Such an
arrangement is required when it is desired to provide the receiver
with the capability to accept a direct video signal input, for
example, from a video tape recorder or a video disc player, or from a
home computer. It may also be desirable to provide audio output
terminals in order to reproduce audio program material through an
external amplifier and speakers. These input or output interface
terminals must be accessible by the user of the television receiver,
yet provide electrical isolation from the ac line to eliminate any
shock hazard. Providing this isolation may be difficult in a receiver
having an SCR regulated power supply, since the SCR is normally
connected directly to the unregulated supply. Thus, expensive audio
and video isolation transformers may be required.
An arrangement for electrically isolating the receiver load circuits from the ac line via the high voltage power transformer is disclosed in a copending application entitled "Regulated Power Supply Circuit", Ser. No. 426,360, filed on Sept. 29, 1982, in the name of D. H. Willis. The circuit described in that application includes a transistor switch which permits current from an unregulated voltage supply to energize a primary winding of the high voltage transformer. This in turn energizes the electrically isolated load circuit windings in order to power the associated load circuits. A supplemental transformer winding aids in transferring power to the load circuits. The conduction time of the transistor switch is controlled in order to regulate the magnitude of the voltages induced across the load circuit windings. The primary winding comprises one half of a bifilar-wound coil pair with the other half of the coil pair operable as a catch winding to return stored energy in the coil back at the unregulated supply when the transistor switch is turned off. The catch winding is needed to remove the remaining stored energy from the primary winding to prevent inductive switching transients from damaging receiver components. This arrangement requires the previously described bifilar primary coil, which increases transformer cost and complexity, and effectively limits the transistor switch conduction duty cycle to a maximum of approximately 50%. This insures that all of the stored energy in the primary winding can be transferred to the catch winding. Limiting the switch duty cycle also limits the amount of energy that may be transferred to the load windings which may limit the ability of the power supply to accurately regulate the load circuit voltages under extreme line voltage and circuit loading conditions.
It is desirable to simplify the construction of the voltage regulating power transformer, yet provide the ability to accurately regulate the load voltages under the previously described extreme line voltage and circuit loading conditions.
In accordance with the present invention, a regulated power supply for a television receiver which includes a number of load circuits comprises an unregulated voltage source coupled to a first terminal of a primary transformer winding. The unregulated voltage source is coupled to the primary winding second terminal and selectively energizes the winding. Means are provided which power the load circuits in response to the energization of the unitary winding. A control circuit is coupled between the load circuits and the energizing means for controlling the operation of the energizing means to maintain a substantially constant voltage supply for the load circuits. A supplemental transformer winding overlays the primary winding and powers at least one of the load circuits in response to energization of the primary winding.
In the accompanying drawing,
FIG. 1 is a schematic diagram of a television receiver regulated power supply constructed in accordance with the invention;
FIG. 2 illustrates waveforms associated with the circuit of FIG. 1; and
FIG. 3 is a diagramatic representation of a high voltage transformer constructed according to the invention.
Referring
to FIG. 1, an ac mains supply 10 is applied to a full-wave bridge
rectifier 11 and a filter capacitor 12 to develop a source of
unregulated voltage at a terminal 13. This unregulated voltage is
applied to one terminal of a primary winding 14 of a high voltage power
transformer 15. The other terminal of winding 14 is coupled to the
collector of a transistor 16 and through a protection network 17,
comprising a resistor 18, a diode 20 and a capacitor 21, to ground.
Transistor 16 is switched by signals from a regulator control circuit
22 via an isolation transformer 28 to control the conduction of
current from the unregulated voltage source through winding 14 in a
manner that will be explained later.
Transformer 15 also includes a number of secondary windings and a tertiary winding 23, which generates a high voltage of the order of 25 KV at an ultor terminal 24 to be applied to the anode of a kinescope (not shown).
Among the secondary windings shown as comprising transformer 15 are winding 25, which provides a voltage which is rectified and filtered to develop a direct voltage of the order of 185 volts at a terminal 26 that may be used, for example, to power the kinescope drive circuits (not shown). Another secondary winding 27 is coupled to a horizontal deflection circuit 30, which comprises a horizontal output transistor 31, a retrace capacitor 32, a damper diode 33, a deflection yoke winding 34, and a deflection waveform S-shaping capacitor 35. Horizontal output transistor 31 is switched at a horizontal rate by signals from a horizontal driver circuit 36, which is controlled by a horizontal oscillator 37 in order to develop horizontal deflection current in deflection yoke winding 34. Winding 27 also generates a voltage which forms a regulated B+ supply at a terminal 40 of the order of 127 volts.
The
voltage generated via the secondary and tertiary associated load
circuits are carefully regulated in the following manner, which will
be explained with reference to FIG. 2. Transistor 16 is rendered
conductive by a switching signal at a time t 1 from
regulator control circuit 22, for example Matsushita AN5900, being
applied to the base of transistor 16, thereby raising the base-emitter
voltage (V BE16 ), as shown in FIG. 2g. Current (I 14 )
flows in primary winding 14 of transformer 15, as shown in FIG. 2a,
from the unregulated voltage supply at terminal 13. Inductive
energy is stored in winding 14 and in the magnetically permeable
core of transformer 15. When transistor 16 is turned off, at time t 3 , the voltage across winding 14 (V 14 )
increases, as shown in FIG. 2b, and induces voltages across load
windings 23, 25 and 27 by transformer action in order to power the
previously described load circuits, such as horizontal deflection
circuit 30.
The amount of energy that may be transferred in this way is dependent on factors which include the conduction time of transistor 16 and the degree of magnetic coupling between the primary winding 14 and the load windings. As previously described, it may be desirable to provide the receiver with direct video and audio input and output capability in order to interface external components, such as video sources, home computers or separate audio equipment, with the receiver. This requires that the user accessible interface connectors or terminals on the receiver be electrically isolated from the ac line in order to prevent the possibility of a user receiving a shock. This isolation may be accomplished by electrically insulating the "hot" primary winding 14 from the load windings. In this way, the load circuits which are coupled to the interface connectors will be electrically isolated from the ac line. This is shown in FIG. 1 by the use of different ground symbols to illustrate the ac line "hot" ground as compared to the isolated "cold" ground.
In the interest of safety, guidelines and requirements may exist which define the amount of insulating material that is needed or the physical separation between windings, particularly between the high voltage ultor winding and the low voltage windings, that is required. These insulation and physical separation requirements may produce a transformer having a reduced primary to load winding magnetic coupling compared to a transformer that does not provide as great a degree of electrical isolation. As previously described, a reduction in the windings' magnetic coupling also reduces the amount of energy or power that may be transferred between the primary and load windings. Under certain severe receiver operating conditions, such as low ac line voltage, receiver start-up, or high load circuit power requirements, there may be insufficient power transferred between primary winding 14 and the load windings to maintain accurate regulation of the load circuit supply voltages.
To prevent a degradation of the voltage regulating capabilities of the receiver under these conditions, a supplemental winding 41 of transformer 14 is provided and operates in the following manner. Supplemental winding 41 is coupled to primary winding 14 more tightly than are the load windings 23, 25 and 27. When transistor 16 turns off, at time t 3 , this coupling causes the voltage across winding 41 (V 41 ) to increase, as shown in FIG. 2c. This voltage is rectified and filtered and provides the source of regulated B+ voltage at terminal 40 and also provides power to operate horizontal deflection circuit 30. An intermediate tap 42 on winding 41 provides a low voltage source of the order of 16 volts via a diode 43 and a capacitor 48 at a terminal 44. The 16 volt source is also applied to and provides operating power for horizontal oscillator 37 and for regulator control circuit 22. In FIG. 1, the level of the 127 volt source is shown as sampled by regulator control circuit 22 to control the switching of transistor 16, in order to maintain accurately regulated load circuit supply voltages. Sampling of the 127 volt supply is shown for example only. Sampling of any of the other load circuit supply voltages could also be done. Supplemental winding 41 is magnetically tightly coupled to primary winding 14 by constructing primary winding 14 and supplemental winding 41 as layer windings with supplemental winding
41
wound to overlay primary winding 14, as shown in FIG. 3. By winding
the transformer 15 in this way, it is possible for supplemental
winding 41 to transfer between 20% to 50% of the total power required
by the load circuits. Close magnetic coupling between the primary
winding 14 and supplemental winding 41 as a result of the layer
winding arrangement produces accurate regulation of the supplemental
winding voltage. This permits the supplemental winding 41 to be used
as a source of one or more regulated voltages for the receiver,
such as the +16 volt supply as shown in FIG. 1. The potential
difference between primary winding 14 and supplemental winding 41 is
relatively small, as contrasted to the potential difference between
primary winding 14 and high voltage winding 23, for example. This
permits windings 14 and 41 to be layer-wound as previously described
in order to provide tight magnetic coupling yet allows windings 14
and 41 to be electrically isolated through the use, for example, of
20 mils of Mylar between windings 14 and 41.
FIGS. 2d and 2e illustrate the waveforms of the current flow through windings 27 and 41, respectively. Current flow in winding 27 (I 27 ) will closely resemble the deflection current in deflection yoke winding 34. Current flow in supplemental winding 41 (I 41 ) decreases as the stored energy in the winding decreases. When this energy is depleted, current flow ceases. Current flow in winding 41 may also be terminated by the switching of transistor 16 terminating conduction of winding 14. The collector-emitter voltage of horizontal output transistor 31 (V BE31 ), illustrating the horizontal retrace pulse, is shown in FIG. 2f.
When transistor 16 is turned off, by action of the switching pulses from regulator control circuit 22, the stored inductive energy in winding 14 causes the collector-emitter voltage of transistor 16 to rise. If this energy is not rapidly removed from winding 14, the collector-emitter voltage of transistor 16 may increase to a point at which transistor 16 is damaged. The tight magnetic coupling between primary winding 14 and supplemental winding 41 causes winding 41 to act as a clamp winding which limits the extent to which the collector voltage of transistor 16 can increase. This occurs because winding 41 expeditiously removes much of the energy from winding 14, as previously described, so that a relatively small amount of energy remains. Protection network 17 is provided, however, to aid in removing this energy in order to protect transistor 16. During the time transistor 16 is conducting, capacitor 21 discharges through resistor 18 and the collector-emitter path of transistor 16 to ground to a level determined by the voltage drop across resistor 18. When transistor 16 turns off, its collector voltage rapidly rises, creating an inductive voltage spike as shown in FIG. 2b. When the collector voltage exceeds the combination of the voltage level on capacitor 21 and the conduction threshold voltage of diode 20, diode 20 is rendered conductive, permitting winding 14 energy to charge capacitor 21. The voltage represented by the spike in FIG. 2b is therefore dissipated by capacitor 21, rather than by transistor 16, thereby protecting transistor 16.
As
described, this excess charge on capacitor 21 is removed via
resistor 18 during conduction of transistor 16. Although some is
removed from primary winding 14 by protection network 17, most of
the energy in winding 14 is transferred to the loads by either the
load windings or by supplemental winding 41.
As the load circuit power requirements decrease or the ac line voltage increases, transistor 16 conducts for a shorter period of time each horizontal interval, as shown by the dashed lines in the waveforms of FIG. 2. Transistor 16 is switched on at a time t 2 and off at time t 4 , resulting in a decreased current flow in primary winding 14 and supplemental winding 41.
The regulator circuit of FIG. 1 therefore provides accurate load circuit supply voltage regulation even under severe receiver operating conditions with a relatively simple high voltage transformer, yet provides ac line isolation of the load circuits to permit interfacing with external video or audio components.
Many of the circuits in television receivers require carefully regulated power supplies in order to operate properly. For example, if the horizontal and vertical deflection circuit supply voltages are permitted to vary in an uncontrolled manner, the size of the scanned raster may change, producing an undesirable visual effect. Additional receiver circuits may be subject to excessive electrical stresses or may be damaged if supply voltages are not held within acceptable limits.
One type of voltage regulating circuit utilizes a silicon controlled rectifier (SCR) coupled to an unregulated voltage source developed from the ac line. During conduction of the SCR, current flow from the unregulated supply charges a capacitor, establishing a regulated voltage level. The conduction time of the SCR is controlled to maintain a fixed regulated voltage level. Decreases in the ac line voltage or increased circuit loading will cause an increase in the SCR conduction time and an increase in line voltage will result in a decrease in SCR conduction time.
The
previously described SCR regulated power supply is not economically
incorporated in a receiver which provides input and output
terminals electrically isolated from the ac line. Such an
arrangement is required when it is desired to provide the receiver
with the capability to accept a direct video signal input, for
example, from a video tape recorder or a video disc player, or from a
home computer. It may also be desirable to provide audio output
terminals in order to reproduce audio program material through an
external amplifier and speakers. These input or output interface
terminals must be accessible by the user of the television receiver,
yet provide electrical isolation from the ac line to eliminate any
shock hazard. Providing this isolation may be difficult in a receiver
having an SCR regulated power supply, since the SCR is normally
connected directly to the unregulated supply. Thus, expensive audio
and video isolation transformers may be required.An arrangement for electrically isolating the receiver load circuits from the ac line via the high voltage power transformer is disclosed in a copending application entitled "Regulated Power Supply Circuit", Ser. No. 426,360, filed on Sept. 29, 1982, in the name of D. H. Willis. The circuit described in that application includes a transistor switch which permits current from an unregulated voltage supply to energize a primary winding of the high voltage transformer. This in turn energizes the electrically isolated load circuit windings in order to power the associated load circuits. A supplemental transformer winding aids in transferring power to the load circuits. The conduction time of the transistor switch is controlled in order to regulate the magnitude of the voltages induced across the load circuit windings. The primary winding comprises one half of a bifilar-wound coil pair with the other half of the coil pair operable as a catch winding to return stored energy in the coil back at the unregulated supply when the transistor switch is turned off. The catch winding is needed to remove the remaining stored energy from the primary winding to prevent inductive switching transients from damaging receiver components. This arrangement requires the previously described bifilar primary coil, which increases transformer cost and complexity, and effectively limits the transistor switch conduction duty cycle to a maximum of approximately 50%. This insures that all of the stored energy in the primary winding can be transferred to the catch winding. Limiting the switch duty cycle also limits the amount of energy that may be transferred to the load windings which may limit the ability of the power supply to accurately regulate the load circuit voltages under extreme line voltage and circuit loading conditions.
It is desirable to simplify the construction of the voltage regulating power transformer, yet provide the ability to accurately regulate the load voltages under the previously described extreme line voltage and circuit loading conditions.
In accordance with the present invention, a regulated power supply for a television receiver which includes a number of load circuits comprises an unregulated voltage source coupled to a first terminal of a primary transformer winding. The unregulated voltage source is coupled to the primary winding second terminal and selectively energizes the winding. Means are provided which power the load circuits in response to the energization of the unitary winding. A control circuit is coupled between the load circuits and the energizing means for controlling the operation of the energizing means to maintain a substantially constant voltage supply for the load circuits. A supplemental transformer winding overlays the primary winding and powers at least one of the load circuits in response to energization of the primary winding.
In the accompanying drawing,
FIG. 1 is a schematic diagram of a television receiver regulated power supply constructed in accordance with the invention;
FIG. 2 illustrates waveforms associated with the circuit of FIG. 1; and
FIG. 3 is a diagramatic representation of a high voltage transformer constructed according to the invention.
Referring
to FIG. 1, an ac mains supply 10 is applied to a full-wave bridge
rectifier 11 and a filter capacitor 12 to develop a source of
unregulated voltage at a terminal 13. This unregulated voltage is
applied to one terminal of a primary winding 14 of a high voltage power
transformer 15. The other terminal of winding 14 is coupled to the
collector of a transistor 16 and through a protection network 17,
comprising a resistor 18, a diode 20 and a capacitor 21, to ground.
Transistor 16 is switched by signals from a regulator control circuit
22 via an isolation transformer 28 to control the conduction of
current from the unregulated voltage source through winding 14 in a
manner that will be explained later.Transformer 15 also includes a number of secondary windings and a tertiary winding 23, which generates a high voltage of the order of 25 KV at an ultor terminal 24 to be applied to the anode of a kinescope (not shown).
Among the secondary windings shown as comprising transformer 15 are winding 25, which provides a voltage which is rectified and filtered to develop a direct voltage of the order of 185 volts at a terminal 26 that may be used, for example, to power the kinescope drive circuits (not shown). Another secondary winding 27 is coupled to a horizontal deflection circuit 30, which comprises a horizontal output transistor 31, a retrace capacitor 32, a damper diode 33, a deflection yoke winding 34, and a deflection waveform S-shaping capacitor 35. Horizontal output transistor 31 is switched at a horizontal rate by signals from a horizontal driver circuit 36, which is controlled by a horizontal oscillator 37 in order to develop horizontal deflection current in deflection yoke winding 34. Winding 27 also generates a voltage which forms a regulated B+ supply at a terminal 40 of the order of 127 volts.
The
voltage generated via the secondary and tertiary associated load
circuits are carefully regulated in the following manner, which will
be explained with reference to FIG. 2. Transistor 16 is rendered
conductive by a switching signal at a time t 1 from
regulator control circuit 22, for example Matsushita AN5900, being
applied to the base of transistor 16, thereby raising the base-emitter
voltage (V BE16 ), as shown in FIG. 2g. Current (I 14 )
flows in primary winding 14 of transformer 15, as shown in FIG. 2a,
from the unregulated voltage supply at terminal 13. Inductive
energy is stored in winding 14 and in the magnetically permeable
core of transformer 15. When transistor 16 is turned off, at time t 3 , the voltage across winding 14 (V 14 )
increases, as shown in FIG. 2b, and induces voltages across load
windings 23, 25 and 27 by transformer action in order to power the
previously described load circuits, such as horizontal deflection
circuit 30.The amount of energy that may be transferred in this way is dependent on factors which include the conduction time of transistor 16 and the degree of magnetic coupling between the primary winding 14 and the load windings. As previously described, it may be desirable to provide the receiver with direct video and audio input and output capability in order to interface external components, such as video sources, home computers or separate audio equipment, with the receiver. This requires that the user accessible interface connectors or terminals on the receiver be electrically isolated from the ac line in order to prevent the possibility of a user receiving a shock. This isolation may be accomplished by electrically insulating the "hot" primary winding 14 from the load windings. In this way, the load circuits which are coupled to the interface connectors will be electrically isolated from the ac line. This is shown in FIG. 1 by the use of different ground symbols to illustrate the ac line "hot" ground as compared to the isolated "cold" ground.
In the interest of safety, guidelines and requirements may exist which define the amount of insulating material that is needed or the physical separation between windings, particularly between the high voltage ultor winding and the low voltage windings, that is required. These insulation and physical separation requirements may produce a transformer having a reduced primary to load winding magnetic coupling compared to a transformer that does not provide as great a degree of electrical isolation. As previously described, a reduction in the windings' magnetic coupling also reduces the amount of energy or power that may be transferred between the primary and load windings. Under certain severe receiver operating conditions, such as low ac line voltage, receiver start-up, or high load circuit power requirements, there may be insufficient power transferred between primary winding 14 and the load windings to maintain accurate regulation of the load circuit supply voltages.
To prevent a degradation of the voltage regulating capabilities of the receiver under these conditions, a supplemental winding 41 of transformer 14 is provided and operates in the following manner. Supplemental winding 41 is coupled to primary winding 14 more tightly than are the load windings 23, 25 and 27. When transistor 16 turns off, at time t 3 , this coupling causes the voltage across winding 41 (V 41 ) to increase, as shown in FIG. 2c. This voltage is rectified and filtered and provides the source of regulated B+ voltage at terminal 40 and also provides power to operate horizontal deflection circuit 30. An intermediate tap 42 on winding 41 provides a low voltage source of the order of 16 volts via a diode 43 and a capacitor 48 at a terminal 44. The 16 volt source is also applied to and provides operating power for horizontal oscillator 37 and for regulator control circuit 22. In FIG. 1, the level of the 127 volt source is shown as sampled by regulator control circuit 22 to control the switching of transistor 16, in order to maintain accurately regulated load circuit supply voltages. Sampling of the 127 volt supply is shown for example only. Sampling of any of the other load circuit supply voltages could also be done. Supplemental winding 41 is magnetically tightly coupled to primary winding 14 by constructing primary winding 14 and supplemental winding 41 as layer windings with supplemental winding
41
wound to overlay primary winding 14, as shown in FIG. 3. By winding
the transformer 15 in this way, it is possible for supplemental
winding 41 to transfer between 20% to 50% of the total power required
by the load circuits. Close magnetic coupling between the primary
winding 14 and supplemental winding 41 as a result of the layer
winding arrangement produces accurate regulation of the supplemental
winding voltage. This permits the supplemental winding 41 to be used
as a source of one or more regulated voltages for the receiver,
such as the +16 volt supply as shown in FIG. 1. The potential
difference between primary winding 14 and supplemental winding 41 is
relatively small, as contrasted to the potential difference between
primary winding 14 and high voltage winding 23, for example. This
permits windings 14 and 41 to be layer-wound as previously described
in order to provide tight magnetic coupling yet allows windings 14
and 41 to be electrically isolated through the use, for example, of
20 mils of Mylar between windings 14 and 41.FIGS. 2d and 2e illustrate the waveforms of the current flow through windings 27 and 41, respectively. Current flow in winding 27 (I 27 ) will closely resemble the deflection current in deflection yoke winding 34. Current flow in supplemental winding 41 (I 41 ) decreases as the stored energy in the winding decreases. When this energy is depleted, current flow ceases. Current flow in winding 41 may also be terminated by the switching of transistor 16 terminating conduction of winding 14. The collector-emitter voltage of horizontal output transistor 31 (V BE31 ), illustrating the horizontal retrace pulse, is shown in FIG. 2f.
When transistor 16 is turned off, by action of the switching pulses from regulator control circuit 22, the stored inductive energy in winding 14 causes the collector-emitter voltage of transistor 16 to rise. If this energy is not rapidly removed from winding 14, the collector-emitter voltage of transistor 16 may increase to a point at which transistor 16 is damaged. The tight magnetic coupling between primary winding 14 and supplemental winding 41 causes winding 41 to act as a clamp winding which limits the extent to which the collector voltage of transistor 16 can increase. This occurs because winding 41 expeditiously removes much of the energy from winding 14, as previously described, so that a relatively small amount of energy remains. Protection network 17 is provided, however, to aid in removing this energy in order to protect transistor 16. During the time transistor 16 is conducting, capacitor 21 discharges through resistor 18 and the collector-emitter path of transistor 16 to ground to a level determined by the voltage drop across resistor 18. When transistor 16 turns off, its collector voltage rapidly rises, creating an inductive voltage spike as shown in FIG. 2b. When the collector voltage exceeds the combination of the voltage level on capacitor 21 and the conduction threshold voltage of diode 20, diode 20 is rendered conductive, permitting winding 14 energy to charge capacitor 21. The voltage represented by the spike in FIG. 2b is therefore dissipated by capacitor 21, rather than by transistor 16, thereby protecting transistor 16.
As the load circuit power requirements decrease or the ac line voltage increases, transistor 16 conducts for a shorter period of time each horizontal interval, as shown by the dashed lines in the waveforms of FIG. 2. Transistor 16 is switched on at a time t 2 and off at time t 4 , resulting in a decreased current flow in primary winding 14 and supplemental winding 41.
The regulator circuit of FIG. 1 therefore provides accurate load circuit supply voltage regulation even under severe receiver operating conditions with a relatively simple high voltage transformer, yet provides ac line isolation of the load circuits to permit interfacing with external video or audio components.
Press CTRL/F to search this page within your browser:SALORA CHASSIS M TROUBLESHOOTING LIST:
M HITACHI CPT6608 LOPTR RB532,RB533,RB535,ALL 1R TB524 BC369 BS208 FET
M SERVICE MODE PRESS P THEN * THEN 0/AV THEN # THEN >M * AND #(CHANGE FUNCTION)
M AQUADAG B FIXING TO CRACK FALL OFF
M BLANK SCREEN WITH WHISTLE/HOWL TDA2040 AUDIO O/P CHIP
M CRT EARTH STRAP BROKEN+ BRIDGE RECT,+CHOPPER+LF0070
M DEAD-HOT LOPTR RB532,R533,R535 R536(1R)TB522 BC307,TB523 BC368 & TB524 BC369& BS208 FET IN EW CCT
M DEAD ; SWITCH ON AT MAINS WITH POWER ON IF STBY LIT POWER OK
M DEAD BRIDGE RECT,LF0070 HYBRID
M DEAD C523 C624
M DEAD C624 220UF 16V CHOPPER TRANSFORMER
M DEAD CAUSE AQUADAG BY133 BRIDGE RECT DIODES,LF0070 HYBRID CHIP & CHOPPER CHIP
M DEAD LOPTR CB622,CB623,CB624+DB523(BY448)+DB524/5(BYV95C)
M DEAD LOPTR TB523 BC368,TB524 BC369,TB522 BC307,458 OR 557 TB521 BC237. 532,535 & 533 1R)
M DEAD LOPTR(2SD1577)HF0070 HB701 C523,C624 220U 16V,C622 470U 16V,C707
M DEAD RB701 2R2 5W,CHOPTR TB701 BU603,12V ZENER DB709 CB705 680PF
M DEAD S2000AF LOP TR - ALONG WITH C523 470U 25V,C571 220U 40V,C622 & C624 220U 25V
M DEAD. SWITCH ON N PLUG IN SOCKET. IF STBY LED LITES,POWER SUPPLY IS USUALLY OK
M DEAD; LOPTR+C527(8N2)LOW CAP
M DEAD? - NOT GIVEN BY REPORTER C523 & C624 220U 16V
M EW RASTER BS208 FET TB526,CB527+CB531
M FIELD COLLAP TDA8172+2*470UF+D601(BY133)FROM LOPTX
M FIELD COLLAPSE CB571 100UF
M FIELD COLLAPSE FOP CHIP FAILURE DUE TO CB571 100U
M FIELD COLLAPSE TDA8172 TWO 470UF,D601 BY133
M FIELD COLLAPSE TDA8172+470UF*2+D601(BY133)
M FIELD O/P TDA8172+CB571+CB627+CB628,DB574 VIDEO CUT OFF
M FINLANDIA C66GZ7
M GREY SCALE POOR CCU-SALO-7
M HITACHI CPT6608 LOPTR SCRAP SET
M INT DEAD WITH WHINE LF0700 HYBRID IC
M INT OFF/FLASHING/E-W,ALL CAUSED BY S CH08 WHITE CAP
M LACK OF WIDTH WHEN HEATED(JUMPS IN 2")DPU2543 TBASE PROC CHIP IC8501
M LINE C0OLLAPSE,SCAN COUPLING CAPACITOR CB531 250NF,250V
M LINE COLLAPSE CB531(250NF250V)+DB525(BYV95C)
M LINE COLLAPSE R538 10K BURNT,C531 25U 250V
M LINE COLLAPSE SCAN COUPLING CAP CB531 250N OR 330N & CHECH SCAN COIL PLUG
M LINE COLLAPSE. SCAN COIL PLUG SOCKET
M LINE SYNC MISSING RB545 390K
M LO HEIGHT RB575 1R IN FOP STAGE HIGH RES
M LOPT TR SC TB525 HB701 DRY C523 C624 220UF C622 470UF USE 25V
M LOPTR CAUSE DB523/524/525+EW FET BS208
M LOPTR TB525,2SD1577.LF0070 HYBRID HB701 IN PSU C523,C624 220UF,16V C622 470UF,16V
M NARROW PIC & SQUEAL FROM LOPTX C624 220U 25V
M NO COL CHAN 3 TUNED ANOTHER CHAN TO CHAN 29 THEN TRANSFERRED IT TO CH3
M NO GREEN,R22(82K)
M NO PIC APART FROM 2" HORIZ BAND TB526 BS208 FET TR IN EW MOD DRIVE CCT
M NO PIC BS208 TB526 FET IN EW MODULATOR
M NO PIC CRT HEATERS ALIGHT FIELD COLLAPSE NO 12V & 17V SUPPLIES D601 BY133
M NO PIC GOOD EHT SOUND,BS208 EW MODULATOR DRIVER TB526 FET,PRONE TO BAD JOINTS
M NO PIC,SND & CRT HTRS OK TB526 BS208 EW DRIVER
M NO PIC,SND OK,BS208 EW FET MODULATOR TB526
M NO PICTURE SOMETIMES A TWO INCH BAND APPEARS TB526 BS208
M NO PICTURE,SND PRESENT AND THE TUBE'S HEATERS BS208 EW MODULATOR DRIVER TRANISTOR TB526,FET
TYPE. REPLACING IT RESTORED NORMAL OPERATION
M NO SND/PIC - DISPLAY BLANK HT(150V)WAS LOW AT 20V. DB525 BYV95C
M NO SND/PIC CRT HTRS OK,TDA8172 TWO 470UF,D601 BY133
M ON WITH HI VOLUME. X2404P MEMORY
M ONE COL MISSING OR INT R12,R22 & R32 82K ON CRT BASE
M RASPING,TRIPPING NOISE WHEN SW OUT OF DB521 1N4148 IN CCT - NEXT TO CRT HEATER CONN
M RUNNING COLORS PVPU2204
M SEE TV MAG AUG 1997
M SERVICE MODE VOL+ AND VOL-(CHANGE VALUE) >M(STORE CURRENT VALUE) TV(EXIT SERVICE MODE)
M SET COMES ON WITH HIGH VOLUME WHEN SET TURNED DOWN X2404P MEMORY IC
M SND LOW & DIST APU2470S CHIP - PROVED WITH FREEZER
M SND VOL VARIES & UNCONTROLLABLE X2404P MEMORY CHIP
M SPOTTY PIC VCU2133 ICB201
M SPOTTY PIC,VCU2133 VIDEO CODEC CHIP ICB201
M STBY DB525(BYV95C)
M STBY OK RASP/TRIP DB521(1N4148) NEAR HEATER PLUG
M STBY OK,BAD NOISE,DB521 1N4148
M STBY WHISTLE TD8172 ICB570
M STBY WHISTLE TDA8172 FIELD OUTPUT CHIP ICB570
M STBY. DB525 BYV95C,CB521 IS 330UF WITH 90-DEGREE
M STORE CHANS A,0,CHAN UP, STORE
M STORE CHANS P, 0, 10+, >M
M SWITCH OFF PLUG IN +-15V +5V -4.5V,LOPTR COLL 0.7V -
M SWITCH ON N PLUG IN IF STBY LIT POWER SUPPLY PROBABLY OK
M TO STORE CHANS A,0,CHAN UP,STORE
M TO STORE CHANS OPTION BYTE 1 - "1" SETS BITS 0 & 1 TO ON(SET COMES ON ON CHAN 1)
M TO STORE CHANS OPTION BYTE 2 - S BIT 4 FROM ON TO OFF AND ALLOWS YOU TO STORE CHANS 1 - 6
WITHOUT PASSWORD
M TO STORE CHANS P,0,10+,>M
M UNLOCKED COLORS PVPU(PAL VIDEO PROCESSOR UNIT) 2203
M WARM NOISES/PICTURE CLOGGINGHYBRID CHIP IN PSU LF0070
M WHINES WHEN COMES ON IN & INT LINE PAIRING BLANKET RESOLDER & C523 220U 25V,C571 100U 40V,C622
470U 16V,C642 220U 25V
M WHISTLES & PIC DISTURBANCE INT LF0070 S
M WHISTLING NOISE IN ICB570 TDA8172 HAS BETWEEN +/- 13V SUPPLY LINES
M WIDTH SUDDENLY INCREASES TB528 BF422
M(HITACHI 28") HOT WHISTLE LF0070 POWER MODULE
M1 DEAD - LOP TR WHEN PIC SHIFTED TO LEFT & TR OVERHEATS. DB528 BA157
M1 FIELD COLLAPSE,OUTPUT CHIP,E BOOST CAP CB571. 100UF
M1 FIELD O/P CHIP+CB571(100UF)
M1 LOPTR +DB528(BA157)
M1 LOPTR DB528 BA157
MSTBY 2SD1577 LOP TR - MAKE SURE YOU FIT CORRECT MENT C527 8N2
SALORA CHASSIS M SERVICING MANUAL PAGES:
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