LOEWE ARCADA 72-100 PIP (53471L39) CHASSIS Q2100 (110Q21) INTERNAL VIEW.

 

 

LOEWE ARCADA 72-100 PIP (53471L39)  CHASSIS Q2100  (110Q21) .

 

(Sit down, the post is............................................... long)

  This new CHASSIS Q2100  (110Q21)  was  intended for cover the high range of TVC, incorporating the most advanced technology available for obtain elevated benefits, both in terms of control and quality of image AND stereophonic sound . further allows the incorporation direct from different TVC standards and peripheral circuits through two scart connectors (SCART). 

The chassis is altough a Matsushita / Panasonic E2100. 

The signal is completely high speed computed in the digital domain in stages featuring improvements stage by stage adding further features and quality to reach the maximum performance and perfection dynamic UNTIL "going to the CRT". All functions are performed and controlled by 2 or more sophisticated Controllers with dedicated Firmware ,for high graphics menu and controls.

• These television LOEWE ARCADA 72-100 PIP (53471L39)  CHASSIS Q2100  (110Q21) sets are solated from the electric power mains by the power transformer. An additional isolation transformer is necessary for servicing work on the primary side of the power transformer.

• Components sensitive to electrostatic discharge must be handled at workstation with electrostatic shielding. An electrostatically shielded MOS workstation is fitted with discharge resistor which earth all conductive materials, including the technician working there. Dielectrics are discharged by air ionisation. The use of soldering irons and measuring equipment at shielded workstation is only possible in conjunction with isolating transformer in each of the devices used. Measuring equipment chassis are also earthed with discharge resistors.

• If there is any error on the signal board, please proceed as described:

1. - Remove the EAROM (| 1941) from the printed circuit board. The TV is able to keep running. (1 1941 and! 1946 are preprogrammed with different software and are not interchangeable. | 1946 is responsible for programs higher then 100).
   - If you get a static picture, the EAROM is out of order (possible geometry errors remain unconsidered).
   - If the error is still there, it's because of another component on the signal board.
   - If you want to change the signal board at the service head office in Kronach, insert the EAROM from the damaged signal board into the new one. So you don't need to make the alignment and the programming of the TV set.
   

  LOEWE ARCADA 72-100 PIP (53471L39)  CHASSIS Q2100  (110Q21)  Digital circuit system for television receivers with cathode ray picture tubes:
 
  A deflection processor generates deflection signals such that the video information of the received signal is visible on the picture tube screen during all movements of the cathode ray beam. The video signal, after being digitized by means of a clock signal, is written into a random-access memory and is read therefrom in such a way that the individual pixels occupy the correct positions on the screen. This is done under control of a memory controller. The digital signals of the memory are applied to a tube-error-compensating stage and to the picture tube via digital-to-analog converters. This arrangement eliminates the rigid dependence on sawtooth deflection signals and permits the waveforms of the deflection signals to be freely selected according to requirements.
 
 
 
1. A digital circuit system for a television receiver with a cathode-ray tube for converting a received video signal to images on the picture tube, comprising:

a deflection processor for generating deflection signals such that the video information of the received signal is displayed on the screen of the picture tube during both the sweep and retrace movements of the cathode-ray beam;

a random-access memory for storing either at least one line or at least one field of the video signal digitized to form digital signals by means of a clock signal, the randomaccess memory being under control of a memory controller, the digital signals being read from the random-access memory so that the individual pixels occupy the positions on the screen of the picture which are intended on the transmitter side; and

a compensating stage coupled to receive the digital signals from the random-access memory for correcting picture tube errors caused by the non-spherical curvature of the picture tube screen, the compensating stage driving the picture tube via a digital-to-analog converter.


2. A digital circuit system as claimed in claim 1, wherein the digital signals are read from the random-access memory in the order of write-in during the trace period and in reverse order during the retrace period.

3. A digital circuit system for a television receiver with a cathode-ray picture tube for converting a received video signal to images on the picture tube, comprising:

a deflection processor for generating deflection signals such that the video information of the received signal is displayed on the screen of the picture tube during both the sweep and retrace movements of the cathode-ray beam, wherein:

the deflection processor comprises a first phaselocked locked loop which synchronizes with the transmitted horizontal synchronizing signal and a second phase-locked loop which synchronizes with the flyback signal; and

the horizontal deflection signals are triangular signals whose frequency is equal to half the input horizontal frequency and the vertical deflection signals are sawtooth signals stepped line by line;

a random-access memory for storing either at least one line or at least one field of the video signal digitized to form digital signals by means of a clock signal, the randomaccess memory being under control of a memory controller, the digital signals being read from the random-access memory so that the individual pixels occupy the positions on the screen of the picture tube which are intended on the transmitter side, wherein:

the random-access memory has a first half and a second half, each half for the video signals of one of two successive lines;

during a horizontal trace period, the video signals stored inthe first half of the memory during the preceding horizontal retrace period are read out forward at the write-in rate;

during a horizontal retrace period, the video signals stored in the second half of the memory during the preceding horizontal trace period are read out backward at the write-in rate; and

the second phase-locked loop comprises first and second loop portions, said first loop portion being provided for horizontal sweep and said second loop portion being provided for horizontal retrace, the flyback signal for each of the first and second loop portions being a signal derived from the switching delay of a transistor to be cut off on the reversal of the direction of deflection; and

a compensating stage coupled to receive the digital signals from the random-access memor for correcting picture tube errors caused by the non-spherical curvature of the picture tube screen, the compensating stage driving the picture tube via a digital-to-analog converter.


4. A digital circuit system for a television receiver with a cathode-ray picture tube for converting a received video signal to images on the picture tube, comprising:

a deflection processor for generating deflection signals such that the video information of the received signal is displayed on the screen of the picture tube during both the sweep and retrace movements of the cathode-ray beam, wherein:

the deflection processor comprises a first phaselocked locked loop which synchronizes with the transmitted horizontal synchronizing signal and a second phase-locked loop which synchronizes with the flyback signal;

the horizontal deflection signals are triangular signals whose frequency is equal to the input horizontal frequency and the vertical deflection signals are sawtooth signals stepped line by line;

a random-access memory for storing either at least one line or at least one field of the video signal digitized to form digital signals by means of a clock signal, the randomaccess memory being under control of a memory controller, the digital signals being read from the random-access memory so that the individual pixels occupy the positions on the screen of the picture tube which are intended on the transmitter side, wherein:

the random-access memor has a first half and a second half, each half for the video signals of one of two successive lines;

during areceived odd line, the video signals stored in the first half of the memory during the preceding line are read out forward and subsequently backward at twice the write-in rate;

during a received even line, the video signals stored in the second half of the memory during the preceding line are read out forward and subsequently backward at twice the write-in rate; and

said second phase-locked loop comprises first and second loop portions, said first loop portion for horizontal sweep and said second loop portion for horizontal retrace, the flyback signal for each of the first and second loop portions being a signal derived from the switching delay of a transistor to be cut off on the reversal of the direction of deflection; and

a compensating stage coupled to receive the digital signals from the random-access memory for correcting picture tube errors caused by the non-spherical curvature of the picture tube screen, the compensating stage driving the picture tube via a digital-to-analog converter.


Description:

BACKGROUND OF THE INVENTION

During the past few years, digital circuit technology has come into se in television receivers, including color television receivers, for processing the received signal and for generating the deflection signal required to control the movement of the electron beam. During the research for and the development and implementation of these digital circuit systems, the course traced ou by conventional analog signal processing was followed, and the known individual problems were solved by means of digital rather than analog circuits.

By contrast, the present invention is predicated on the realization that, against the background of digital signal processing in television receivers, the constraints resulting from conventional analog technology, particularly with respect to predetermined signal waveforms, can be eliminated, thus making it possible to cope with difficult problems better than with conventional analog and/or digital technology. One of those difficult problems is still the geometric distortions introducted by the nonspherical curvature of the tube screen during reproduction. To eliminate these distortions, a considerable amount of circuitry is required both with conventional analog technology and more recent digital technology; an example is the great number of pincushion-correcting circuits.

SUMMARY OF THE INVENTION

The fundamental idea of the invention as claimed is to abandon the rigid dependence on the commonly used sawtooth signal for ohorizontal deflection and vertical deflection, which both have a very short retrace period in comparison with the trace period, and to make the individual pixels of the video signal visible on the screen when the two deflection signals have moved the electron beam to the point intended on the transmitter side.

In the present invention, therefore, the deflection signals are no longer generated by a sawtooth generator of long-known analog or more recent digital design, but a deflection processor is provided which generates horizontal and vertical deflection signals with freely selectable waveforms.

The video signal, after being digitized by means of a clock signal, is written into a random-access memory and is read ou in such a way that the individual pixels occupy the intended positions on the screen. The memory has a suitable controller associated therewith, of course. The digital signals read out of the memory must be applied to a compensating stage for correcting picture tube errors before they drive the picture tube via digital-to-analog converters.

BRIEF DESCRIPTION OF THE DRAWINGS

The invention will now be explained in greater detail with reference to the accompanying drawing, in which:

FIG. 1 is a highly schematic block diagram of an embodiment of the invention,

FIG. 2 shows a preferred embodiment of a portion of the circuit of FIG. 1.

FIG. 3 shows a preferred embodiment of a portion of the deflection processor of FIG. 1, showing the phase-locked loops therein, and

FIG. 4 illustrates graphs of exemplary signal waveforms associated with the deflection processor of FIG. 3.

DETAILED DESCRIPTION OF SEVERAL PREFERRED EMBODIMENTS

In the schematic circuit diagram of FIG. 1, the horizontal and vertical deflection systems of a picture tube 10 are fed, respectively, with the horizontal and vertical deflection signals generated by a deflection processor 12 in the above sense. To generate these signals, the deflection processor 12 needs horizontal and vertical synchronizing signals 14, 16, respectively, which are derived by a conventional sync separator, which may, of course, be implemented as a digital circuit, too, from the received and demodulated composite color signal in the usual manner. The video signal 18, after being digitized by means of a clock signal, is written into a random-access memory 20, which is capable of storing at least one line and/or at least one field. These stored video signals are then read out of the memory 20 in such a wah that the individual pixels occupy the intended positions on a picture tube screen 22, as mentioned above. Both the write-in and the read-out are performed under control of a memory controller 24, which, like the deflection processor 12, is fed with the horizontal and vertical synchronizing signals 14, 16.

The memory 20 is followed by a compensating stage 26 for correctign picture tube errors, and the picture tube 10 is driven with the correct video signals via digital-to-analog converters 28.

In a preferred embodiment of the invention, the signals are read from the memory 20 in the same order as that in which they were written in, i.e., forward, so to speak, during the trace period, and in reverse order, i.e. backward, so to speak, during the retrace period. This may apply to the individual lines of the screen picture, for example; then the memory 20 must have locations for at least two lines. It may also be the case for fields, however; then the memory 20 must be capable of storing at least two fields. As illustrated in FIGS. 3 and 4, when the embodiment just explained is used in television receivers, including color television receivers, with a deflection processor 12 (FIG. 3) which has two phase-locked loops (PLL) 40, 42 the first 40 of which synchronizes with the transmitted horizontal synchronizing signal 50 (FIG. 4) and the second 42 with the flyback signal, and if the horizontal deflection signals are triangular signals 52 whose frequency is half the input horizontal frequency, as shown in FIG. 4, with the vertical deflection signals 54 being sawtooth signals stepped line by line, in another preferred embodiment of the invention, the random-access memory 20 consists of two halves 30, 32, each for the video signals of one of two successive lines. During the horizontal trace interval, thte video signals stored in the first half 30 of the memory 20 during the preceding horizontal retrace interval are read out forward at the write-in rate, and during the horizontal retrace interval, the video signals stored in the second half 32 of the memory 20 during the preceding horizontal trace interval are read out backward at the write-in rate. This is indicated in FIG. 2 by means of the two switches to be operated by the memory controller 24 in a suitable manner.

In this preferred embodiment, the above-menttioned second phase-locked loop is duplicated, one loop 42A being provided for the deflection signal for horizontal sweep, and the other 42B for that for horizontal retrace. Each of these two second phase-locked loops is supplied with a separate flyback signal. These flyback signals are derived from the switching delays of two transistors 44, 46 to be cut off on the "right" and "left" reversals of the direction of deflection, respectively. These transistors 44, 46 are the usual output transistors 44, 46 of the deflection power output stage 48, which are operated in the base saturation region during the flow of current, as is well known, so that, on a change to the off state, they switch the input cut-off signal to the output not immediately, but only when the excess charge carriers stored in the base region during the saturated condition have been removed.

The preferred embodiment just mentioned can be modified so as to make the frequency of the triangular signals equal to the input horizontal frequency. Then, in a received odd line, the video signals stored in the first half 30 of the memory during the preceding line are read out first forward and immediately thereafter backward at twice the write-in rate. Furthermore, ina received even line, the video signals stored inthe second half 32 of the memory during the preceding line are read out first forward and immediately thereafter backward at twice the write-in rate. Here, too, the second phase-locked loop must be duplicated, and each of the two loops must be fed with a separate flyback signal as mentioned above.

The individual subcircuits of the invention are implemented with digital integrated circuits, of course, preferably with MOS circuits.
Inventors:Micic, Ljubomir (Freiburg, DE)  Deutsche ITT Industries, GmbH (Freiburg, DE)  

Mehrgardt, Soenke (March, DE)

 Other References:
Electronic Engineering 56 (1984) May, No. 689, London, G. Britain, pp. 77-80, "Deflection Processor Eliminating TV Hold Controls".
IEEE Transaction on Consumer Electronics, CE-31 (1985) Aug., No. 3, New York, pp. 255-261, "Symmetric Line Deflection for Color TV Receivers with Enhanced Picture Quality", Uwe E. Kraus.

 

LOEWE ARCADA 72-100 PIP (53471L39)  CHASSIS Q2100  (110Q21)   ITT DIGIT_2000 PART:

Color television receiver comprising at least one integrated circuit for the luminance signal and the chrominance signals: 

 Assignee:ITT Industries, Inc. (New York, NY)
A color television receiver is provided having a fully digital color demodulator wherein the luminance signal and the chrominance signals are separated and digitally processed prior to being converted to analog signals.

 1. A color-television receiver, comprising:

at least one integrated circuit for separating and conditioning the luminance signal and the chrominance signals from the composite color signal, said integrated circuit including a chrominance-subcarrier oscillator, a chrominance-subcarrier band-pass filter, a synchronous demodulator, a PAL switch, a color matrix and an R-G-B matrix, said chrominance-subcarrier oscillator is a square-wave clock generator providing four clock signals, the first of which

has four times the chrominance-subcarrier frequency, and the second to fourth of which have the chrominance-subcarrier frequency with the first and second clock signals having a mark-to-space ratio of 0.5, and the third and fourth clock signals each consisting of two consecutive, T/2-long pulses separated by T/2 within each 4T-long period (T=period of the first clock signal);

an analog-to-digital converter clocked by the first clock signal, whose analog input is presented with the composite color signal, and which forms as its output signal a parallel binary word from the amplitude of the composite color signal at those instants where the respective amplitudes of the undemodulated chrominance signal are equal to the amplitudes of the respective color-difference signal;

a first binary arithmetic stage which multiples the output signal of the analog-to-digital converter by a binary overall-contrast control signal;

a two-stage delay line which delays the output signal of the first binary arithmetic stage by T/2;

a second binary arithmetic stage which forms the arithmetic means of the delayed and undelayed output signals of the first binary arithmetic stage;

a third binary arithmetic stage which subtracts the output signal of the second binary arithmetic stage from the output signal of the first delay stage;

a buffer-memory arrangement which temporarily stores the output signal of the third binary arithmetic stage and whose enable input is fed with the third clock signal;

a shift-register arrangement consisting of n parallel shift registers (n=number of bits at the output of the third binary arithmetic stage) each of which provides a delay of one line period and whose serial inputs are connected to the parallel outputs of the buffer-memory arrangement while their clock inputs are fed with the fourth clock signal;

a fourth binary arithmetic stage which forms the arithmetic mean of the input and output signals of the shift-register arrangement;

a fifth binary arithmetic stage which subtracts the input signal of the shift-register arrangement from the output signal of this arrangement and then divides the difference obtained by two;

a sixth binary arithmetic stage which, controlled by the PAL switch, either leaves the output signal of the fifth binary arithmetic stage unchanged or forms its absolute value; and

a seventh binary arithmetic stage which forms the green color-difference signal from the output signals of the fourth and sixth binary arithmetic stages, the outputs of the second, fourth, sixth and seventh binary arithmetic stages are connected to the binary R-G-B matrix, each of whose outputs is coupled to one of three digital-to-analog converters for deriving the analog signals for controlling the R-G-B values of the picture tube.


2. A color-television receiver as claimed in claim 1, wherein the square-wave clock generator generates, in addition, a fifth and a sixth clock signal which are formed from the third clock signal and the fourth clock signal respectively, by eliminating every second pulse of each period, the buffer-memory arrangement consists of two buffer memories which are operated in parallel at their inputs, and whose enable inputs are fed with the fifth clock signal and the sixth clock signal, respectively, the shift-register arrangement consists of two shift-register subarrangements each of which has n parallel shift registers providing a delay of one line period, the series inputs of the first shift-register subarrangement are connected to the outputs of the first buffer memory, and the clock inputs of this subarrangement are fed with the sixth clock signal, the serial inputs of the second shift-register subarrangement are connected to the outputs of the second buffer memory, and the clock inputs of this subarrangement are fed with the fifth clock signal, the fourth binary arithmetic stage forms the means of the input signals and the output signals of the second shift-register subarrangement, and the fifth binary arithmetic stage subtracts the input signals of the first shift-register subarrangement from the output signals of this subarrangement.

3. A color-television receiver as claimed in claim 1 incorporating R-G-B control of the picture tube, wherein the three digital-to-analog converters associated with the binary R-G-B matrix are fed with a binary color-saturation control signal and the three digital-to-analog converters are fed with a binary brightness control signal.

4. A color-television receiver as claimed in claim 1 and incorporating color-difference control of the picture tube wherein the digital-to-analog converter associated with the second binary arithmetic stage is fed with a binary brightness control signal and the other three digital-to-analog converters are fed with a binary color-saturation control signal.

5. A color-television receiver as claimed in claim 1 and incorporating color-difference control of the picture tube wherein an eighth binary arithmetic stage multiplying the output signal of the third binary arithmetic stage by a binary color-saturation control signal is connected between the outputs of the third binary arithmetic stage and the parallel inputs of the buffer-memory arrangement.

6. A color-television receiver, comprising:

at least one integrated circuit for separating and conditioning the luminance signal and the chrominance signals from the composite color signal, said integrated circuit including a chrominance-subcarrier oscillator, a chrominance-subcarrier band-pass filter, a synchronous demodulator, a PAL switch, a color matrix, said chrominance-subcarrier oscillator is a square-wave clock generator providing four clock signals, the first of which has four times the chrominance-subcarrier frequency, and the second to fourth of which have the chrominance-subcarrier frequency, with the first and second clock signals having a mark-to-space ratio of 0.5, and the third and fourth clock signal each consisting of two consecutive, T/2 long pulses separated by T/2 within each 4T-long period (T=period of the first clock signal);

an analog-to-digital converter clocked by the first clock signal, whose analog input is presented with the composite color signal, and which forms as its output signal a parallel binary word from the amplitude of the composite color signal at those instants where the respective amplitudes of the undemodulated chrominance signal are equal to the amplitudes of the respective color-difference signal;

a first binary arithmetic stage which multiplies the output signal of the analog-to-digital converter by a binary overall-contrast control signal;

a two-state delay line which delays the output signal of the first binary arithmetic stage by T/2;

a second binary arithmetic stage which forms the arithmetic means of the delayed and undelayed output signals of the first binary arithmetic stage;

a third binary arithmetic stage which subtracts the output signal of the second binary arithmetic stage from the output signal of the first delay stage;

a buffer-memory arrangement which temporarily stores the output signal of the third binary arithmetic stage, and whose enable input is fed with the third clock signal;

a shift-register arrangement consisting of n parallel shift registers (n=number of bits at the output of the third binary arithmetic stage) each of which provides a delay of one line period and whose serial inputs are connected to the parallel outputs of the buffer-memory arrangement while their clock inputs are fed with the fourth clock signal;

a fourth binary arithmetic stage which forms the arithmetic mean of the input and the output signals of the shift-register arrangement;

a fifth binary arithmetic stage which subtracts the input signal of the shift-register arrangement from the output signal of this arrangement and then divides the difference obtained by two;

a sixth binary arithmetic stage which, controlled by the PAL switch, either leaves the output signal of the fifth binary arithmetic stage unchanged or forms its absolute value; and

a seventh binary arithmetic stage which forms the green color-difference signal from the output signals of the fourth and sixth binary arithmetic stages, the outputs of the second, fourth, sixth and seventh binary arithmetic stages are each connected to one of four digital-to-analog converters for deriving the analog signals for controlling the color-difference values of the picture tube.



7. A color-television receiver as claimed in claim 6, wherein the square-wave clock generator generates, an addition, a fifth and a sixth clock signal which are formed from the third clock signal and the fourth clock signal, respectively, by eliminating every second pulse of each period, the buffer-memory arrangement consists of two buffer memories which are operated in parallel at their inputs, and whose enable inputs are fed with the fifth clock signal and the sixth clock signal, respectively, the shift-register arrangement consists of two shift-register subarrangements each of which has n parallel shift registers providing a delay of one line period, the serial inputs of the first shift-register subarrangement are connected to the outputs of the first buffer memory, and the clock inputs of this subarrangement are fed with the sixth clock signal, the serial inputs of the second shift-register subarrangement are connected to the outputs of the second buffer memory, and the clock inputs of this subarrangement are fed with the fifth clock signal, the fourth binary arithmetic stage forms the mean of the input signals and the output signals of the second shift-register subarrangement, and the fifth binary arithmetic stage subtracts the input signals of the first shift-register subarrangement from the output signals of this subarrangement.

8. A color-television receiver as claimed in claim 6 incorporating R-G-B control of the picture tube, wherein an eighth binary arithmetic stage multiplying the output signal of the third binary arithmetic stage by a binary color-saturation control signal is connected between the outputs of the third binary arithmetic stage and the parallel inputs of the buffer-memory arrangement, and the three digital-to-analog converters are fed with a binary brightness control signal.

9. An arrangement for producing from a composite color analog signal, a plurality of color information digital signals, said arrangement comprising:

means responsive to said analog signal for generating first digital signals having a predetermined relationship carried by said composite color analog signals; and

means for processing said first digital signals to generate said color information digital signals, said processing means comprises: means responsive to control signals and to said first digital signals for generating intermediate digital signals; and first processing means for processing said intermediate digital signals to generate said color information digital signals, said first processing means comprises first means for generating first ones of said plurality of color information digital signals by acting on a first set of said intermediate digital signals and a second set of said intermediate digital signals in a predetermined manner, said first set and second successive set of said intermediate digital signals being successive sets of said intermediate digital signals.


10. An arrangement in accordance with claim 9, wherein said first means generates said first ones of said plurality of color information digital signals by forming the arithmetic means of said first and second sets of said intermediate digital signals.

11. An arrangement in accordance with claim 10, wherein said first ones of said plurality of color information digital signals represent luminance signal information.

12. An arrangement for producing from a composite color analog signal, a plurality of color information digital signals, said arrangement comprising:

means responsive to said analog signal for generating first digital signals having a predetermined relationship to information carried by said composite color analog signals; and

means for processing said first digital signals to generate said color information digital signals, said processing means comprising: first processing means for generating first ones of said color information digital signals in response to said first digital signals, and second processing means for generating other ones of said color information digital signals in response to said first digital signals and said first ones of said color information digital signals.


13. An arrangement in accordance with claim 12, wherein said first ones of said color information digital signals represent luminance signals and said other ones of said color information digital signals represent first and second chrominance signals.

14. An arrangement in accordance with claim 13, wherein said first digital signal generating means comprises means for generating said first digital signals at a predetermined rate relative to the chrominance subcarrier of said composite color analog signal.

15. An arrangement in accordance with claim 14, wherein said predetermined rate is at least twice the frequency of said chrominance subcarrier.

16. An arrangement in accordance with claim 15, wherein said first processing means generates said first ones of said color information signals in accordance with the means of the values represented by two successive sets of said first digital signals.

17. An arrangement in accordance with claim 16, wherein said second processing means generates said other ones of said color information digital signals by subtracting said first ones of said color information digital signals from said first digital signals.

18. An arrangement in accordance with claim 17, comprising means interposed between said digital signal generating means and said processing means for modifying said first digital signals in accordance with control signals.

19. A circuit arrangement for recovering video color signals from a composite color analog signal, said circuit arrangement comprising:

an analog to digital converter having inputs for receiving said composite color analog signal and for forming first digital signals representative of the amplitude of said composite color analog signal at predetermined time intervals at first outputs;

a delay circuit having inputs coupled to said analog to digital converter and first and second outputs;

a first digital circuit having first inputs coupled to said analog to digital converter first outputs and a second input coupled to said delay circuit second output and generating first color information digital signals at first outputs;

a second digital circuit having first inputs coupled to said first digital circuit first outputs and second inputs coupled to said delay circuit first outputs and generating first and second color difference digital signals at outputs.


20. A circuit arrangement in accordance with claim 19, comprising a third digital circuit coupled between said analog to digital converter and said delay circuit for receiving said first digital signals from said analog to digital converter, modifying said first digital signals in accordance with control signals and supplying said modified first digital signals to said delay circuit inputs.

21. A circuit arrangement in accordance with claim 20, comprising a third digital circuit coupled to the outputs of said second digital circuit, and responsive to said first and second color difference signals for generating a third color difference signal at outputs.

22. A circuit arrangement in accordance with claim 21, comprising: a binary R-G-B matrix having inputs coupled to said first digital circuit output, to said second digital circuit outputs, and to said third digital circuit outputs, for generating R, G and B digital outputs.

23. A circuit arrangement in accordance with claim 22, comprising:

digital to analog converter means coupled to said R, G and B digital outputs for generating R, G and B analog signals.


Description:

BACKGROUND OF THE INVENTION

1. Field of the Invention

This invention relates to color television receivers and, more particularly, to color television receivers having digital luminance and chrominance signals.

2. Description of the Prior Art

In a book by O. Limann, "Fernsehtechnik ohne Ballast", 12th edition, Munchen 1978, pages 189 to 263, the principle and the basic circuits of today's color-television receivers are described. This description includes an explanation of commercially available integrated circuits which can be used in the color portion of a color-television receiver. A characteristic feature of these integrated circuits is that they process the analog composite color signal in analog form. The integrated circuits described are, therefore, circuits implemented with conventional junction transistors, i.e., so-called bipolar integrated circuits.

On the other hand, the above-mentioned book describes, on pages 307 to 326, integrated remote-control arrangements for television receivers which operate essentially digitally and, thus, are implemented using mainly insulated-gate field-effect transistor technology, i.e., so-called MOS technology.

It should be noted that the term "MOS technology", once coined as an abbreviation for "metal oxide silicon" is no longer limited to insulated-gate field-effect transistors having a silicon-dioxide gate insulating layer, because today, use is also made of material other than silicon dioxide, such as silicon nitride or multilayer arrangements of different insulating materials.

Bipolar integrated circuits are mainly suited to analog signal processing, while integrated circuits for digital signal processing can be better implemented using MOS technology. With the development of ever larger integrated circuits, i.e. so-called VLSI (very-large-scale-integrated) circuits, a certain limit has now been reached with bipolar integrated circuits as far as the amount of circuitry capable of being accommodated on a single semiconductor chip is concerned is such circuits are to be fabricated at a warrantable expense (e.g., chip size, yield) by conventional mass-production techniques. In this respect, MOS integrated circuits are better suited for larger-scale integration.

SUMMARY OF THE INVENTION

The object of the invention as characterized in the claims is, in view of the preferred implementation using MOS technology, to provide a concept for a color-television receiver in which the luminance signal and the chrominance signals are separated and conditioned not in analog form as has been done so far, but in digital form.

DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram of a first embodiment of a digital luminance/chrominance portion of a color-television receiver according to the invention.

FIG. 2 shows a modification of the embodiment of FIG. 2.

FIG. 3 shows a second embodiment of a luminance/chrominance portion of a color-television receiver according to the invention.

FIG. 4 shows a modification of the second embodiment of FIG. 3 which corresponds to FIG. 2.

FIG. 5 shows a preferred form of the first embodiment of FIG. 1, which can also be used in the other embodiments of FIGS. 2 to 4.

FIG. 6 shows various waveforms in the arrangement of FIG. 1 and, in tabular form, signals occurring at given points at given times.

DESCRIPTION OF THE INVENTION

In the block diagrams shown in FIGS. 1 to 4, like parts are designated by like reference numerals. In addition to interconnections indicated by solid lines as is usual in circuit diagrams, these figures contain interconnections indicated by stripes. These stripes mark connections between digital parallel outputs of the delivering portion of the circuit and digital parallel inputs of the receiving portion. The interconnections indicated by stripes therefore consist of at least as many wires as there are bits in the binary word to be transferred. Thus, the signals transferred over the lines indicated by stripes in FIGS. 1 to 5 are all binary signals whose instantaneous binary value corresponds to the instantaneous analog value of the composite color signal and of other signals.

Like in conventional color-television receivers, the composite color signal F, derived in the usual manner, controls the chrominance-subcarrier oscillator, which, according to the invention, is designed as a square-wave clock generator 1. By means of the so-called burst contained in the composite colour signal F, the clock generator 1 is synchronized to the transmitted chrominance-subcarrier frequency. In the embodiments of FIGS. 1 to 5, the clock generator 1 generates the clock signal F1, whose frequency is four times the chrominance-subcarrier frequency, i.e. about 17.73 MHz (precisely 17.734475 MHz) in the case of the CCIR standard.

The clock generator 1 also generates the square-wave clock signal F2 having the frequency of the chrominance subcarrier. The first and second clock signals F1, F2 have a mark-to-space ratio of 0.5 (cf. FIGS. 6a and 6b). In addition, the clock generator 1 generates the third clock signal F3 and the fourth clock signal F4, each of which consists of two consecutive, T/2-long pulses separated by T/2 within each 4T-long period, where T is the period of the first clock signal F1. The third and fourth clock signals F3, F4 are shown in FIGS. 6b and 6g.

The individual clock signals are generated within the clock generator 1 in the usual manner using conventional digital techniques. The clock signal F1, for instance, may be generated by means of a suitable 17.37 MHz crystal, and the clock signals F2, F3, F4 may be derived therefrom by frequency division and suitable elimination of pulses. Like in conventional color-television receivers, the clock generator 1 is also fed with a pulse Z from the horizontal output stage during which the clock generator 1 is synchronized by the burst.

The composite color signal F is also applied to the analog input of the analog-to-digital converter 2, which is clocked by the first clock signal F1 and, at the beginning of each pulse of the first clock signal F1, forms from the amplitude of this pulse a parallel binary word and delivers it as an output signal. These leading edges of the pulses of the first clock signal F1 thus occur at the instants when the respective amplitudes of the undemodulated chrominance signal contained in the composite color signal are equal to the amplitudes of the respective color-difference signal. These parallel binary words then remain unchanged for the respective period T of the first clock signal F1, i.e., they are held like in a sample-and-hold circuit. The signals appearing at the output of the analog-to-digital converter 2 are given in tabular form in FIG. 6c, where the vertical lines symbolize the respective clock periods of the first clock signal F1. The letter c of FIG. 6 is also shown in FIG. 1 (encircled).

According to FIG. 6c, successive signals Y+V, Y-U, Y-V and Y+U are obtained in a line m during one period of the second clock signal F2, where U, V and Y have the formal meanings given in the abovementioned book, namely U=B-Y, V=R-Y, B=blue chrominance signal, R=red chrominance signal, and Y=luminance signal, but designate here the corresponding digitized signals, i.e., the corresponding binary words. The second line in the Table of FIG. 6c gives the corresponding binary signals in the line m+1, namely the signals Y-V, Y-U and Y+U occurring during that period of the clock signal F2 which is under consideration.

This output signal of the analog-to-digital converter 2 is applied to one of the two inputs of the first binary arithmetic stage 10, which multiplies this output signal by a binary overall-contrast control signal GK. This overall contrast control signal thus corresponds to the analog overall-contrast control signal present in conventional color-television receivers. In present-day color-television receivers, the binary overall-contrast control signal GK, just as the binary color-saturation control signal JF and the binary brightness control signal H to be explained below, is available in digital form, because remote-control units and digital controls are usually present which provide these signals. An advantage of the invention is therefore seen in the fact that these signals need no longer be conditioned in analog form in their place of action.

The output signal of the first binary arithmetic stage 10 is fed to the second binary arithmetic stage 20 and to the two-stage delay line 3, which delays this output signal by T/2. The second binary arithmetic stage 20 forms the arithmetic means of the delayed and undelayed signals. The underlying idea is that if a sinusoidal signal, namely the chrominance subcarrier, is sampled at double frequency, the mean of two successive sample values will always be zero. Thus, by forming the arithmetic means in the second binary arithmetic stage 20, the chrominance subcarrier is suppressed and the luminance signal Y is obtained in digital form.

The output signal of the first binary arithmetic stage 10, delayed in the first stage 31 of the delay line 3 by half the delay provided by this stage, i.e., by T/4, and the output signal of the second binary arithmetic stage 20 are then fed to the third binary arithmetic stage 30, which subtracts the latter signal, i.e., the Y signal, from the former signal. As a result, the output of the third binary arithmetic stage 30 provides the color-difference signal, made up of the successive components B-Y, R-Y, -(B-Y) and -(R-Y), as shown in FIG. 6d in tabular form for the lines m and m+1.

These signals are fed to the buffer-memory arrangement 4, whose enable input is fed with the third clock signal F3, which is shown in FIG. 6e. This buffer memory operates in such a manner that the binary word fed to the input at the beginning of each pulse of the third clock signal F3 appears at the output when the next clock pulse occurs. Thus, the instantaneous output signals given in FIG. 6f in tabular form for the lines m and m+1 are obtained. The individual stages of the buffer-memory arrangement may be so-called D flip-flops, for example.

The output signal of the buffer-memory arrangement 4 is applied to the shift-register arrangement 5, which consists of n parallel shift registers, where n is the number of bits at the output of the third binary arithmetic stage 30. The delay provided by the n parallel shift registers is equal to the duration of one line, i.e., 64 μs in the case of PAL television sets. The clock inputs of the parallel shift registers are fed with the fourth clock signal F4, which is shown in FIG. 6g. The output signal of the shift-register arrangement is given in tabular form in FIG. 6h for the lines m and m+1.

This output signal, together with the input signal of the shift-register arrangement 5, is fed to the fourth binary arithmetic stage 40, which forms the arithmetic mean of the two signals, so that its output provides the signal B-Y is digital form, which is given in tabular form in FIG. 6k. The input and output signals of the shift-register arrangement 5 are also fed to the fifth binary arithmetic stage 50, which subtracts the input signal from the output signal and divides the difference by two. By the division, a sort of averaging is performed as well.

The output signal of the fifth binary arithmetic stage 50 is given in tabular form in FIG. 6l, again for the lines m and m+1. This output signal is fed to the sixth binary arithmetic stage 60, which, in response to the output signal of the PAL switch 12, leaves it unchanged in one line and forms its absolute value in the other. "To form the absolute value" is used here first of all in the mathematical sense, i.e., the negative sign of a negative number is suppressed and only the positive value of this negative number is taken into account. Within the scope of the present invention, however, "absolute value" also means "value with respect to a constant number". By this it is meant that for a number A below the constant X, the "absolute value with respect to X" is 2X-A. Thus, for the number 30, the "absolute value with respect to 50" is 70. The output of the sixth binary arithmetic stage 60 thus provides the PAL-compensated signal R-Y in digital form, i.e., the red color-difference signal, which is given in tabular form in FIG. 6p for the lines m and m+1.

The output signals of the fourth binary arithmetic stage 40 and of the sixth binary arithmetic stage 60 are fed to the seventh binary arithmetic stage 70, which forms the green color-difference signal G-Y by the well-known formula Y=0.3R+0.59G+0.11B. The subcircuits 5, 40, 50, 60 and 70, together with the PAL switch 12, represent the portion for correcting the phase of the received signal by the PAL method.

The output signals of the second, fourth, sixth and seventh binary arithmetic stages 20, 40, 60, 70, i.e., the luminance signal Y and the color-difference signals B-Y, R-Y and G-Y, are then fed to the binary R-G-B matrix 6, which forms therefrom the binary chrominance signals R, G, B by the above formula. Each of these binary chrominance signals is then fed to one of the three digial-to-analog converters 7, 8, 9, which convert the binary chrominance signals to the analog chrominance signals R', G', B' necessary for R-G-B control of the picture tube.

In the embodiment of FIG. 1, each of these digital-to-analog converters is also fed with the color-saturation control signal FK and the brightness control signal H, both in binary form.

The PAL switch 12 is fed with the second clock signal F2, i.e., a signal having the chrominance-subcarrier frequency locked to the burst, with the composite color signal F, and with the reference pulse Z from the horizontal output stage.

The embodiment of FIG. 2 is a modification of the embodiment of FIG. 1 in which the binary color-saturation control signal FK is fed into the overall circuit at a different point. This point lies between the output of the third binary arithmetic stage 30 and the input of the buffer-memory arrangement 4, where the eighth binary arithmetic stage 80 is inserted, which multiplies the utput signal of the third binary arithmetic stage 30 by the binary color-saturation control signal FK. Thus, in the embodiment of FIG. 2, only the brighness control signal H is applied to the three digital-to-analog converters 7, 8, 9.

The embodiment of FIG. 3 shows the conditioning of the color-difference signals and of the luminance signal if the color-television receiver according to the invention contains colour difference control circuitry for the picture tube rather than R-G-B control circuitry as in the embodiments of FIGS. 1 and 2. In such case, the R-G-B matix 6 is not present, but the color-difference signals at the outputs of the fourth, sixth and seventh binary arithmetic stages 40, 60, 70 as well as the luminance signal Y at the output of the second binary arithmetic stage 20 are each fed to one of four digital-to-analog converters, the luminance signal Y being fed to the analog-to-digital converter 11, and the color-difference signals R-Y, G-Y and B-Y to the converters 7', 8' and 9', respectively. In the embodiment of FIG. 3, the brightness control signal H is fed to the digital-to-analog converter 11, which is associated with the luminance channel, while the color-saturation control signal FK is applied to the remaining three digital-to-analog converters 7', 8', 9'. The outputs of these digital-to-analog converters thus provide the analog luminance signal Y' and the analog color-difference signals (R-Y)', (G-Y)', (B-Y)'.

The embodiment of FIG. 4 shows that, in the arrangement of FIG. 1, in the same manner as in the embodiment of FIG. 2, the binary color-saturation control signal FK can be applied between the output of the third binary arithmetic stage 30 and the input of the buffer-memory arrangement 4 via the eighth binary arithmetic stage 80. Accordingly, each of the three digital-to-analog converters 7', 8', 9' has only one input for the respective color-difference signal.

FIG. 5 shows a preferred embodiment which can be used both with the R-G-B control of FIGS. 1 and 2 and with the color-difference control of FIGS. 3 and 4. The clock generator, designated here 1', generates two additional clock signals F5, F6. Both the buffer-memory arrangement and the shift-register arrangement are divided into two parts. The buffer-memory arrangement consists of the two buffer memories 41, 42, which are operated in parallel at the input ends, with the clock signal F5 applied to the first buffer memory 41, and the clock signal F6 to the second buffer memory 42. These two clock signals are shown in FIGS. 6s and 6t and are formed in the clock generator 1' by eliminating every second pulse of each period of the third and fourth clock signals F3, F4.

The output signal of the first buffer memory 41 is fed to the first shift-register subarrangement 51, which again consists of n parallel shift registers providing a delay of one line period. Similarly, the output signal of the second buffer memory 42 is applied to the input of the second shift-register subarrangement 52, which also consists of n parallel shift registers providing a delay of one line period. The clock inputs of the shift registers of the first shift-register subarrangement 51 are fed with the sixth clock signal F6, and those of the second shift-register subarrangement 52 with the fifth clock signal F5.

In the embodiment of FIG. 5, the fourth binary arithmetic stage 40 forms the arithmetic mean of the input and output signals of the second shift-register subarrangement 52, while the fifth binary arithmetic stage 50 subtracts the output signal of the shift-register subarrangement 51 from the input signal of this arrangement and divides the difference by two. The further signal processing then corresponds to that in the abovedescribed embodiments with the variants given there for the application of the color-saturation control signal FK and of the brightness control signal H.

While the invention has been described as applied to a PAL-standard color-television receiver, it is readily possible to apply the fundamental idea of the invention to NTSC-standard color-television receivers. To do this, in the embodiment of FIG. 5, for example, it is only necessary to omit the two shift-register subarrangements 51, 52, the fourth, fifth, and sixth arithmetic stages 40, 50, 60 and, of course, the PAL switch 12. The input signals of the seventh binary arithmetic stage 70 are then the two output signals of the two buffer memories 41, 42.

Because of the digital signal processing used in the invention, the sequence of steps in demodulating the composite color-signal differs considerably from that for analog signal processing. For example, part of the synchronous-demodulator function is already implemented by the analog-to-digital converter 2 and by the application thereto of the clock signal F1 having four times the chrominance-subcarrier frequency.

The binary arithmetic stages 10 . . . 80 are characterized by simple arithmetic operations, namely subtraction (in stages 30 and 50) multiplication (in stages 10 and 80), division by two (in stage 50), averaging (in stages 20 and 40), absolute-value formation (in stage 60), and calculation based on a given linear dependence (in stage 70). Implementation of these operations and subcircuits suitable therefor are known from data processing and computer systems and, therefore, need not be explained here in detail.

Other References:
"Digital Processing Amplifier and Color Encoder", SMPTE Journal Jan. 1978, vol. 87, pp. 15-19.
"An Integrated One-Chip Processor for Color TV Receivers," IEEE Trans. Cons., Electronics, Aug. 1977, pp. 300-310.
"A PAL/YUV Digital System . . . " BBC Research Report RD 1976/24 Sep. 1976.

DE2830825A1    1980-01-24           
FR2349250A1    1977-11-18           
GB1251767A    1971-10-27           
GB1457107A    1976-12-01           
GB1518126A    1978-07-19            

 Digital integrated circuit for the color matrix of a color-television set
 
  The circuit contains three multipliers/adders for the luminance signal (y) and the two color-difference signals (r-y, b-y). For the output signals of these stages, four parallel adders are provided. The multipliers for the factors -0.51 and -0.19, which would be required in accordance with the color-television-system formula y=0.3r+0.59g+0.11b are rendered unnecessary because, among other things, the input signals are provided with correction factors (k, L, m) and correction addends (d, e, f) in the multipliers/adders in view of a presettable color overload.
 
   1. Digital integrated circuit providing a color matrix for a color-television set with digital signal processing circuitry wherein the digital luminance signal (y) and the two digital color-difference signals (r-y, b-y) are applied to the color matrix and the color matrix provides the digital color signals (g, r, b), said circuit comprising:

a first multiplier/adder (ma1), having a parallel input for receiving the digital luminance signal (y), for adding a first addend (d) to the product of the digital luminance signal (y) and a first factor (k);

a second multiplier/adder (ma2), having a parallel input for receiving the red-minus-luminance signal (r-y), for adding a second addend (e) to the product of the red-minus-luminance signal (r-y) and a second factor (L);

a third multiplier/adder (ma3), having a parallel input for receiving the blue-minus-luminance signal (b-y), for adding a third addend (f) to the product of the blue-minus-luminance signal (b-y) and a third factor (m), the three factors (k, L, m) and the three addends (d, e, f) being determined by the following relationships in decimal notation, k=1/(0.89s+0/11) (1) L=1.4sk (2) m=2.514 sk (3) d=1-5/6 (4) e=5/6-0.7sk (5) f=11/6-1.257 sk (6)

where s is the maximum color overload set at the factory;

a first parallel adder (a1) having a first parallel input connected to a parallel output of the first multiplier/adder (ma1), and a second parallel input to which is applied an output signal of the second multiplier/adder (ma2) after it is inverted digit by digit and shifted one position to the right;

a second parallel adder (a2) having a first parallel input connected to the parallel output of the first parallel adder (a1), and a second parallel input to which is applied the blue-minus-luminance signal (b-y) after it is inverted digit by digit and shifted one position to the right:

a third parallel adder (a3) having first and second inputs connected to the output of the first multiplier/adder (ma1) and to the output of the second multiplier/adder (ma2), respectively; and

a fourth parallel adder (a4) having first and second parallel inputs connected to the first multiplier/adder (ma1) and to the output of the third multiplier/adder (ma3), each of said second, third and fourth parallel adders having a parallel output, whereby the parallel outputs of the second, third, and fourth parallel adders (a2, a3, a4) are the outputs for the digital green, red, and blue signals (g, r, b), respectively.


2. A digital integrated circuit as claimed in claim 1, wherein the multiplier/adder devices (ma1, ma2, ma3) comprise read-only memories.

3. A digital integrated circuit as claimed in claim 1, wherein the multiplier/adder devices (ma1, ma2, ma3) comprise reprogrammable read-only memories.

4. A digital color matrix comprising:

first means for adding a first terminal quantity to the product of a digital luminance signal and a first factor;

second means for adding a second predetermined quantity to the product of a first color difference signal and a second factor;

third means for adding a third determined quantity to the product of a second color difference signal and a third factor;

fourth means for adding the sum output of said first means to the sum output of said second means inverted digit by digit and shifted one position;

fifth means for adding the sum output of said first means to said second color difference signal inverted digit by digit and shifted one position

sixth means for adding the sum outputs of said first and second means; and

seventh means for adding the sum outputs of said first and third means;

wherein the outputs of said fifth, sixth and seventh means are digital color signals.


5. A digital color matrix in accordance with claim 4 wherein:

said first predetermined factor k is equal to 1/(0.89S+0.11);

said second predetermined factor L is equal to 1.4 sk;

said third predetermined factor m is equal to 2.514 sk; and

S is the maximum color overload.


6. A digital color matrix in accordance with claim 5 wherein:

said first predetermined quantity is equal to 1-5/6;

said second predetermined quantity is equal to 5/6-0.7 sk; and

said third predetermined quantity is equal to 11/6-1.257sk.


7. A digital color matrix in accordance with claim 4 wherein:

said first color difference signal is a red-minus-luminance signal and said second color difference signal is a blue-luminance-signal.


8. A digital color matrix in accordance with claim 4 wherein:

said first, second and third predetermined factors each has a predetermined relationship to the maximum color overload.


9. A digital color matrix comprising:

a first multiplier/adder for adding a first addend to the product of a digital luminance signal and a first factor;

a second multiplier/adder for adding a second addend to the product of a digital red-minus-luminance signal and a second factor;

a third multiplier/adder for adding a third addend to the product of a digital blue-minus-luminance signal and a third factor;

a first adder for adding the output of said first multiplier/adder and the output of said second multiplier/adder inverted digit-by-digit and shifted one position;

a second adder for adding the output of said first multiplier/adder and said blue-minus-luminance signal after it is inverted digit-by-digit and shifted one position;

a third adder for adding the outputs of said first and second multiplier adder; and

a fourth adder for adding the outputs of said first and third multiplier/adder;

the outputs of said second, third, and fourth parallel adders providing digital green, red, and blue signals respectively.


10. A digital color matrix in accordance with claim 9 wherein:

said first second and third factors each has a predetermined relationship to the maximum color overload.


11. A digital color matrix in accordance with claim 10 wherein: k=1/(0.895S+0.11); L=1.4 sk; and m=2.514 sk

where k is said first factor, L is said second factor, m is said third factor and S is a maximum color overload.


12. A digital color matrix in accordance with claim 9 wherein:

each of said first, second, and third multiplier/adders and each of said first, second, third and fourth adders has parallel inputs and outputs.


13. A digital color matrix in accordance with claim 9, wherein each of said first, second and third multiplier adders comprise a read only memory.

14. A digital color matrix in accordance with claim 9 wherein each of said first, second, third and fourth multiplier/adders comprises a reprogrammable read only memory.

Description:

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a digital integrated circuit for the color matrix of a color-television set with digital signal processing circuitry wherein the digital luminance signal and the two digital color-difference signals are applied to the three parallel inputs of the color matrix, whose three parallel outputs provide the digital color signals.

2. Description of the Prior Art

In present-day color-television systems (NTSC, PAL, SECAM), the luminance signal Y is composed of the three color signals R=red, G=green, and B=blue according to the following equation: Y=0.3R+0.59G+0.11B.

The color-television transmitter transmits the two color-difference signals R-Y and B-Y together with further signals using different modulation methods depending on the color-television system. After demodulation and separation, the color signals are regained by the color matrix in the color-television receiver according to the following equations: R=(R-Y)+Y G=-0.5(R-Y)-0.19 (B-Y)+Y B=(B-Y)+Y

For the color matrix commonly used in color-television sets, circuits consisting of suitable resistor networks are generally used which convert the analog color-difference signals into corresponding analog color signals.

In color-television sets with digital signal processing circuitry, as are disclosed, for example, in Offenlegungsschrift DE No. 28 54 236 A1 corresponding to U.S. Pat. No. 4,270,139, the color-difference signals and the luminance signal are present in digital form, and in such sets, too, a digital color matrix must satisfy the above three equations for the digital color signals. By means of parallel adders and parallel multipliers, the idealized digital color matrix can be readily implemented on the basis of these equations.

However, the use of such a color matrix would be greatly limited because such a matrix would not take into account the decimal reduction factor 0.88 for the red-minus-luminance signal and the decimal reduction factor 0.49 for the blue-minus-luminance signal and, in addition, would leave the manufacturer no choice in determining the color overload.

SUMMARY OF THE INVENTION

The object of the invention is to provide a digital color matrix which both takes into account the aforementioned reduction factors and permits a color overload up to a factor of 2. Furthermore, the design of the color matrix is to be such that the output signals of the matrix, i.e., the three digital color signals, are zero when the two digital color-difference signals and the digital luminance signal at the input of the matrix are zero. Finally, the maximum color overload intended by the manufacturer is to be possible at a predetermined number of digits of the digital color signals and a predetermined number of digits of the two digital color-difference signals and the digital luminance signal.

The solution of the various aspects of the problem offers the advantage that the multipliers required for the abovementioned factors of -0.51 and -0.19 can be dispensed with, and that only the three multipliers required to take into account the color overload and, of course, the four adders also required in the ideal color matrix are needed.

DESCRIPTION OF THE DRAWING

The drawing is a highly schematic diagram of an embodiment of the invention.

DESCRIPTION OF THE INVENTION

The
digital luminance signal y and the two color-differance signals r-y and b-y are generated by suitable stages of the digital color-television receiver. Such stages are described in the above-mentioned Offenlegungsschrift DE No. 28 54 236 A1 and will, therefore, be assumed to be known within the scope of the present invention. In the embodiment shown in the FIGURE, the digital luminance signal y is applied to the parallel input of the first multiplier/adder ma1, which adds the first addend d to the product of the luminance signal y and the first factor k. Similarly, the red-minus-luminance difference signal r-y is applied to the parallel input of the second multiplier/adder ma2, which adds the second addend e to the product of this color-difference signal and the second factor L. The blue-minus-liminance difference signal b-y is applied to the parallel input of the third multiplier/adder ma3, which adds the third addend f to the product of the b-y signal and the third factor m. The three factors k, L, m and the three addends d, e, f are determined by the following relationship in decimal notation; the numerical values in decimal notation are thus processed by the three multipliers/adders ma1, ma2, ma3 in the number system used in the concrete circuit; in the simplest case, the number system is the binary system. Thus, the following six equations hold: k=1/(0.89s+0.11) (1) L=1.4sk (2) m=2.514sk (3) d=1-5/6 (4) e=5/6-0.7sk (5) f=11/6-1.257sk (6)

where s is the maximum color overload set at the factory.

The parallel output of the first multiplier/adder ma1 is connected to the first parallel input of the first parallel adder a1, to whose second parallel input the output signal from the second multiplier/adder ma2 is applied after being inverted digit by digit and shifted one position to the right. The digit-by-digit inversion is advantageously accomplished by means of one inverter per digit, which is illustrated in the figure by the first multiple inverter i1.

The parallel output of the first parallel adder a1 is connected to the first parallel input of the second parallel adder a2, to whose second parallel input the blue-minus-luminance difference signal b-y is applied after being inverted digit by digit and shifted one position to the right. This inversion is advantageously accomplished by means of the multiple inverter i2.

The parallel output of the first multiplier/adder ma1 is also coupled to the first parallel input of the third parallel adder a3, which has its second parallel input connected to the parallel output of the second multiplier/adder ma2. Also coupled to the parallel output of the first multiplier/adder ma1 is the first parallel input of the fourth parallel adder a4, which has its second parallel input connected to the parallel output of the third multiplier/adder ma3.

The parallel outputs of the second parallel adder a2, the third parallel adder a3, and the fourth parallel adder a4 provide the green signal g, the red signal r, and the blue signal b, respectively, these three signals being the digital color signals, as mentioned previously.

As was also mentioned above, the digital color matrix according to the invention, contrary to expectation, contains no multipliers for the decimal factors -0.51 and -0.19, by which the r-y and b-y signals would have to be multiplied. This advantageous feature is obtained by taking the steps explained in the following, which led to the solution of the problem in accordance with the invention.

As considerations of the inventor show, it is advantageous to assign the maximum numerical value of the blue signal to the maximum output control range of the digital color matrix. For example, if the digital color signals are eight-digit signals, and the individual stages use the binary system, the eight-digit binary number 11111111 at the output of the fourth parallel adder a4 will be assigned to the full output control range, which means that the preset maximum color overload occurs at this numerical value. For an overload value of s=1, i.e., full saturation, the maximum value of the blue signal must be correspondingly reduced; a corresponding measure is the first factor k. From b-y=0.3r+0.58g+0.11b

it follows for r=g=0 that the maximum value (b-y)m =0.89. On the other hand, it follows from the condition r=g=0 that the maximum value ybm, which is a pure blue value in this case, is 0.11. The defining equation for the first factor k can thus be written as (ybm +(b-y)m s) k=1,

and rearranging terms gives k=1/(0.89s+0.11) (1)

As is well-known the color-difference signals are transmitted with different reduction factors, namely the red-minus-luminance signal with the reduction factor 0.88, and the blue-minus-luminance signal with the reduction factor 0.49. In addition to these factors, the color overload desired by the manufacturer must also be taken into account at the input end of the color matrix. Because of the lesser reduction of the red-minus-luminance signal r-y (factor 0.88), this signal is the determining signal. The possible range of values, i.e., the peak-to-peak value of the red-minus-luminance signal, so to speak, follows from a consideration of the following two cases: presence of pure red and presence of red=0. For pure red, g=b=0, so that (r-y)m =+0.7r. The minimum value (r-y)0 follows from the condition g=b=1, r=0 to -0.7. The red-minus-luminance signal thus lies in the range ±0.7, i.e., has the width 1.4, which, multiplied by reduction factor 0.88, is applied to the input of the color matrix.

The digital maximum value of the input signal of the color matrix must thus correspond to 1.40.88s.

Similar considerations for the blue-minus-luminance signal show that the maximum range of this signal is ±0.890.49. Thus, the maximum range to be processed in the case of the red-minus-luminance signal is greater than that in the case of the blue-minus-luminance signal, and the circuit of the color matrix must be so designed that the input-signal range satisfies the condition ±0.70.88.

As was just shown, a positive numerical value is obtained for the maximum of the red-minus-luminance signal, and a negative numerical value for the minimum. This must be taken into account in the matrix by allowing for the midranges of the two color-difference signals at the input end with the additional decimal numerical value ±0.5.

According to the inventor's above consideration, the second factor L and the third factor m are thus defined by ##EQU1##

The following table gives the numerical values for k, L, m, and s=1, 1.5,2:
TABLE 1
______________________________________
s 1.0 1.5 2.0 k 1 0.692 0.5291 L 1.4 1.453 1.481 m 2.513 2.61 2.661
______________________________________

It can be seen that the values of L and m vary only little between s=1 and s=2, so that it is advantageous to design the entire color matrix for a fixed average value of s=1.5.

It is also apparent that the factor m, by which the b-y signal is multiplied, and the factor -0.19 of the ideal matrix give approximately the common factor -0.5, which is satisfied particularly for s=1.5 to a very good approximation (the exact value is s=1.687). This leads to one essential feature of the invention, namely that a multiplier for the factor -0.89 can be dispensed with.

The considerations for determining the three addends d, e, f start from the fact that it is advantageous and advisable to make the output signals of the color matrix zero if the input signals y, r-y, and b-y disappear. Taking into account the additive value +0.5 necessary for the two color-difference signals r-y and b-y (see above), the following set of equations is thus obtained for determining the three addends d, e, f: ##EQU2##

Solving this set of equations for d, e, and f gives d=-5/6 e=5/6-0.7sk and f=11/6-1.257sk. The calculation of the numerical values in the range s=1 to s=2 shows that e, like d, becomes negative, so that two parallel subtractors would be necessary. However, this can be avoided in a simple manner in view of the fact that these negative numbers become positive numbers by addition of 1. The only result is that the color signals g and r are greater by decimal 1, while the color signal b is greater by decimal 2. However, since the number of digits of the output signals of the color matrix is too small to represent these additional additive quantities, i.e., the output signal of the color matrix would have to have one or two additional digits, respectively, which is not the case, the additive quantities have no effect in the output signal.

According to a further feature of the invention, the multiplier required for the factor -0.51 of the ideal matrix is not necessary, either, because the factor 0.51 is replaced by the factor 0.5=2-1. In the binary system, multiplication by powers of two is easily achieved by correspondingly shifting the digits of the signal to the left or to the right with respect to the digits to which it is to be applied. The minus operator is implemented by inverting the individual digits, so that the arrangement shown in the FIGURE is obtained.

If the three adders a2, a3, a4 have suitable capacities, the digits resulting from the above-mentioned additive 1 can be used to advantage for monitoring the color matrix. If the input signals of the color matrix do not lie within the predetermined or permissible ranges, signals indicating that the output signals have exceeded or fallen below the permissible range can occur in these additional positions, which lie above the actual most significant digit of the output signals. These signals can be used to activate digital limiters which clamp the respective output signal of the color matrix to the maximum value when it has exceeded the permissible range, and to the minimum value when it has fallen below this range. The following table shows the assignment of the signals in these additional positions for the respective operating conditions:
TABLE 2
______________________________________
Two digits above the most significant digit in the permis- above the permis- below the permis- sible range sible range sible range
______________________________________


r:a3 01 10 00

g:a2 01 10 00

b:a4 10 11 01

______________________________________

The three multipliers/adders ma1, ma2, ma3 are preferably implemented with read-only memories (ROMs) or reprogrammable read-only memories (e.g., EAROMs).

The digital color matrix according to the invention is preferably implemented using insulated-gate field-effect transistor integrated circuitry, which is ideally suited for implementing digital circuits.

 Digital signal processing circuitry for a color-television receiver
 

 
  Digital color signal processing circuitry includes a multiplier which multiplies two demodulated digital color-difference signals by a digital color-saturation signal to provide three time-division-multiplexed signal pairs, each of which is added to the digital luminance signal by an adder. The color-saturation-signal input of the multiplier is preceded by a second multiplier to which the color-saturation signal and multiplier factors stored in a memory (sp) are applied. These multiplier factors are permanently stored by the manufacture of the color-television receiver or can be varied or adjusted during the operation of the receiver. The three adders are followed by three digital-to-analog converters which provide the analog color signals.
 
 
 1. Digital signal processing circuitry comprising:

a multiplier circuit having first inputs for receiving two demodulated digital color difference signals, second inputs for receiving a color-saturation signal, and third inputs for receiving multiplier factors, and having outputs, said multiplier providing a first multiplied pair of signals at one output, a first one of said first pair of signals corresponding to the product of one of said color difference signals, said color-saturation signal and a first one of said multiplier factors, a second one of said first pair of signals corresponding to the product of the other of said color difference signals, said color-saturation signal and a second one of said multiplier factors, said multiplier providing a second multiplexed pair of signals at a second output, a first one of said second pair of signals corresponding to the product of said one of said color difference signals, said color-saturation signal and a third one of said multiplier factors, a second one of said second pair of signals corresponding to the product of said other of said color difference signals, said color-saturation signal and a fourth one of said multiplier factors;

a first adder having first inputs coupled to said multiplier and second inputs for receiving a digital luminance signal, said first adder adding said first pair of multiplexed signals and said digital luminance signal to provide signals at outputs;

a second adder having first inputs coupled to said multiplier and second inputs for receiving said digital luminance signal, said second adder adding said second pair of multiplexed signals and said digital luminance signal to provide signals at outputs.


2. A signal processing circuitry in accordance with claim 1 comprising:

a first digital to analog converter having digital inputs coupled to said first adder outputs and having analog outputs; and

a second digital to analog converter having digital inputs coupled to said second adder outputs and having analog outputs.


3. Signal processing circuitry in accordance with claim 2, wherein said multiplier circuit comprises

a first multiplier for receiving said color-saturation signal and said plurality of multiplier factors and providing first, second, third and fourth products of said color-saturation signal with said first, second, third and fourth multiplier factors, respectively; and

a second multiplier for multiplying said first color difference signal with each of said first and second products and said second color difference signal with each of said third and fourth products.


4. Signal processing circuitry in accordance with claim 1 comprising:

a memory for storing said first, second, third and fourth multiplier factors and having outputs coupled to said multiplier for supplying thereto said first, second, third and fourth multiplier factors.


5. Signal processing circuitry in accordance with claim 2 comprising:

a memory for storing said first, second, third and fourth multiplier factors and having outputs coupled to said multiplier for supplying thereto said first, second, third and fourth multiplier factor.


6. Signal processing circuitry in accordance with claim 3 comprising:

a memory for storing said first, second, third and fourth multiplier factors and having outputs coupled to said multiplier for supplying thereto said first, second, third and fourth multiplier factor.


7. Signal processing circuitry in accordance with claim 4, wherein said memory has an input whereby said first, second, third and fourth multiplier factors may be varied or adjusted.

8. Signal processing circuitry in accordance with claim 5, wherein said memory has an input whereby said first, second, third and fourth multiplier factors may be varied or adjusted.

9. Signal processing circuitry in accordance with claim 6, wherein said memory has an input whereby said first, second, third and fourth multiplier factors may be varied or adjusted.

10. Signal processing circuitry in accordance with claim 2 comprising:

a third digital to analog converter for converting said digital luminance signal to an analog signal; and

an R-G-B matrix having inputs coupled to said first, second, and third digital to analog converters.


11. Signal processing circuitry in accordance with claim 10, wherein said multiplier circuit comprises

a first multiplier for receiving said color-saturation signal and said plurality of multiplier factors and providing first, second, third and fourth products of said color-saturation signal with said first, second, third and fourth multiplier factors, respectively; and

a second multiplier for multiplying said first color difference signal with each of said first and second products and said second color difference signal with each of said third and fourth products.


12. Signal processing circuitry in accordance with claim 10 comprising:

a memory for storing said first, second, third and fourth multiplier factors and having outputs coupled to said multiplier for supplying thereto said first, second, third and fourth multiplier factor.


13. Signal processing circuitry in accordance with claim 11 comprising:

a memory for storing said first, second, third and fourth multiplier factors and having outputs coupled to said multiplier for supplying thereto said first, second, third and fourth multiplier factor.


14. Signal processing circuitry in accordance with claim 12, wherein said memory has an input whereby said first, second, third and fourth multiplier factors may be varied or adjusted.

15. Signal processing circuitry in accordance with claim 13, wherein said memory has an input whereby said first, second, third and fourth multiplier factors may be varied or adjusted.

16. Signal processing circuitry in accordance with claim 4, wherein said memory is a read only memory.

17. Signal processing circuitry in accordance with claim 5, wherein said memory is a read only memory.

18. Signal processing circuitry in accordance with claim 6, wherein said memory is a read only memory.

19. Signal processing circuitry in accordance with claim 12, wherein said memory is a read only memory.

20. Signal processing circuitry in accordance with claim 13, wherein said memory is a read only memory.

21. Signal processing circuitry in accordance with claim 1, wherein

said multiplier provides a third multiplexed pair of signals at a third output, a first one of said third pair of signals corresponding to the product of said one color difference signal, said color-saturation signal and a fifth multiplier factor, a second one of said third pair of signals corresponding to the product of said other of said color difference signals, said color-saturation signal and a sixth multiplier factor; and

said circuitry further comprises a third adder having first inputs coupled to said multiplier and second inputs for receiving said digital luminance signal, said third adder adding said third pair of multiplexed signals and said luminance signal to provide signals at outputs.


22. A signal processing circuitry in accordance with claim 21 comprising:

a first digital to analog converter having digital inputs coupled to said first adder outputs and having analog outputs;

a second digital to analog converter having digital inputs coupled to said second adder outputs and having analog outputs; and

a third digital to analog converter having digital inputs coupled to said third adder outputs and having analog outputs.


23. A digital integrated circuit for a color-television receiver with digital signal processing circuitry comprising:

a first multiplier having first inputs for receiving for multiplying a first demodulated digital color difference signal with second digital signals and a second demodulated digital color difference signal with said second digital signals to provide three multiplexed signal pair outputs;

a second multiplier for multiplying a color-saturation signal with each of a plurality of multiplier factors to provide said second digital signals;

a memory storing each of said plurality of multiplier factors and coupled to said second multiplier for supplying thereto said plurality of multiplier factors, said multiplier factors being defined as follows: b'=s(b-y)b1, b"=s(r-y)b2, g'=s(b-y)g1, g"=s(r-y)g2, r'=s(b-y)r1, and r"=s(r-y)r2

where s is the color-saturation signal, b-y is the first color difference signal, r-y is the second color difference signal b' and b" are a first pair of said three multiplexed signal pair outputs, g' and g" are a second pair of said three multiplexed signal pair outputs, r' and r" are a third pair of said multiplexed signal pair outputs, and b1, b2, g1, g2, r1 and r2 are said multiplier factors;

a first adder for adding said b' and b" signal pair with a digital luminance signal;

a first digital to analog converter having its digital input coupled to the output of said first adder for providing an analog blue signal;

a second adder for adding said g' and g" signal pair with said digital luminance signal;

a second digital to analog converter having its digital input coupled to the output of said second adder for providing an analog green signal;

a third adder for adding said r' and r" signal pair with said digital luminance signal; and

a third digital to analog converter having its digital input coupled to the output of said third adder for providing an analog red signal.


24. A digital integrated circuit in accordance with claim 23, wherein said multiplier factors are permanently stored in said memory.

25. A digital integrated circuit in accordance with claim 23, wherein said multiplier factors may be adjusted during operation of said receiver in accordance with a third digital signal.

26. A digital integrated circuit in accordance with claim 24, wherein said multiplier factors may be adjusted during operation of said receiver in accordance with a third digital signal.

27. A digital integrated circuit in accordance with claim 23, for driving a color picture tube with an analog luminance signal Y where Y=0.3R+0.5G+0.11B, wherein said multiplier factors have the following decimal numerical values: b1=1/b*, b2=0, r1=0, r2=1/r*, g1=-0.19b*, and g2=-0.51/r*

where b* and r* are factors by which the blue- and red-minus-luminance signals, respectively, are multiplied at the transmitting color signal source in accordance with a predetermined color television standard.


28. A digital integrated circuit in accordance with claim 27, wherein said standard is the PAL or NTSC standard and b*=0.493 and r*=0.877. .



29. A digital integrated circuit in accordance with claim 27, wherein said standard is the SECAM standard and b*=1.5 and r*=-1.9.

30. A digital integrated circuit in accordance with claim 23 for driving a color picture tube having a color loci different from that of a conventional color picture tube with an analog luminance signal Y where Y=0.3R'R+0.59G'G+0.11B'B, wherein said multiplier factors have the following decimal numerical values: b1=1/b*, b2=0, g1=-0.19B'/G'b*, g2=-0.51R'/G'r*, r1=0, and r2=1/r*

where b* and r* are factors by which the blue-minus-luminance and red-minus-luminance signals, respectively, are multiplied at the source of color signals in accordance with a predetermined color television standard.


31. A digital integrated circuit in accordance with claim 30, wherein said standard is the PAL or NTSC standard and b*=0.493 and r*=0.877. .



32. A digital integrated circuit in accordance with claim 30, wherein said standard is the SECAM standard and b*=1.5 and r*=-1.9.

33. A digital integrated circuit for a color-television receiver with digital signal processing circuitry comprising:

a first multiplier having first inputs for receiving for multiplying a first demodulated digital color difference signal with second digital signals and a second demodulated digital color difference signal with said second digital signals to provide two multiplexed signal pair outputs;

a second multiplier for multiplying a color-saturation signal with each of a plurality of multiplier factors to provide said second digital signals;

a memory storing each of said plurality of multiplier factors and coupled to said second multiplier for supplying thereto said plurality of multiplier factors, said multiplier factors being defined as follows: b'=s(b-y)b1, b"=s(r-y)b2, r'=s(b-y) r1, and r"=s(r-y)r2

where s is the color-saturation signal, b-y is the first color difference signal, r-y is the second color difference signal b' and b" are a first pair of said two multiplexed signal pair outputs, r' and r" are a second pair of said multiplexed signal pair outputs, and b1, b2, r1 and r2 are said multiplier factors;

a first adder for adding said b' and b" signal pair;

a first digital to analog converter having its digital input coupled to the output of said first adder for providing an analog B-Y signal;

a second digital to analog converter receiving a digital luminance signal at its digital input for providing an analog luminance signal;

a second adder for adding said r' and r" signal pair; and

a third digital to analog converter having its digital input coupled to the output of said second adder for providing an analog R-Y signal.


34. A digital integrated circuit in accordance with claim 33, wherein said multiplier factors have the following values: b1=cos α b2=sin α r1=-sin α r2=cos α

where α is the phase angle between the digital blue-minus-luminance signal and a color burst signal.


35. A digital integrated circuit in accordance with claim 34, wherein α can be set by the user of the receiver.

36. A digital integrated circuit in accordance with claim 34, wherein α is automatically adjusted.

37. A digital integrated circuit in accordance with claim 33, wherein said B-Y, R-Y and luminance signals are coupled to an analog R-G-B matrix.

38. Signal processing circuitry in accordance with claim 7, wherein said multiplier factor may be adjusted in accordance with a Vertical Interval Reference signal.

39. Signal processing circuitry in accordance with claim 8, wherein said multiplier factor may be adjusted in accordance with a Vertical Interval Reference signal.

40. Signal processing circuitry in accordance with claim 9, wherein said multiplier factor may be adjusted in accordance with a Vertical Interval Reference signal.

Description:

BACKGROUND OF THE INVENTION

The present invention relates to a digital integrated circuit for a color-television receiver with digital signal processing circuitry which contains a first multiplier which multiplies two demodulated digital color-difference signals with a digital color-saturation signal using time-division multiplexing.

A digital integrated circuit of this kind is disclosed in the publication "DIGIT 2000 VLSI-Digital-TV-System", March 1982, in the form of the description of the integrated circuits MAA 2100 and MAA 2200 on pages 4-3 to 4-5. In FIG. 4-2 on page 4-3, the above-mentioned multiplier is called a "color-saturation multiplier" because it is fed with the demodulated color-difference signals from the preceding stages and with the aforementioned digital color-saturation signal via a stage called "IM bus interface". For the two color-difference signals, time-division multiplexing is used; the same applies to the delivery of the corresponding output signals to the two following digital-to-analog converters for the two analog color-difference signals.

As also described in the publication mentioned above, the two integrated circuits MAA 2100 and MAA 2200 form part of an IC set with which digital color-television receivers can be implemented.

SUMMARY OF THE INVENTION

We have discovered that the color-saturation multiplier of the prior art, besides being usable for this special purpose, can be multiplexed so as to simplify the overall arrangement for digitally processing the received picture signal. Accordingly, an object of the invention is to improve the prior art digital circuit so that the multiplier can be multiplexed.

An advantage offered by the invention is that the analog R-G-B matrix used in the prior art arrangement to generate the analog color signals can be dispensed with because these analog color signals appear at the outputs of the digital-to-analog converters used in the invention. In a modified form, the invention offers the added advantage that the tint-control function required in NTSC color-television receivers can be realized with the color-saturation multiplier as well.

BRIEF DESCRIPTION OF THE DRAWINGS

The invention will now be explained in more detail with reference to the accompanying drawings, in which:

FIG. 1 is a block diagram of an embodiment of the invention;

FIG. 2 is a block diagram of another embodiment of the invention; and

FIG. 3 is a block diagram of an embodiment of the above-mentioned modification of the invention for NTSC color-television receivers.

DETAILED DESCRIPTION

In the figures, digital signals are designated by small letters, and analog signals by capital letters.

In the block diagram of FIG. 1, digital color-difference signals b-y, r-y, derived from the transmitted and received television signal in the known manner, are supplied to the multiplexer mx, whose output is connected to one of the two inputs of the first multiplier m1. Connected to the other input, to which the color-saturation signal is applied in the prior art arrangement mentioned above, is the output of the second multiplier m2, whose two inputs are, respectively, fed with the color-saturation signal s and connected to the output of the memory sp.

The first multiplier m1 provides three signal pairs b', b"; g', g"; r', r" on a time-division multiplex basis. The first signals of the pairs are applied to the first inputs of the first, second, and third adders a1, a2, a3, respectively, and the second signals are applied to the respective second inputs. Each adder has a third input to which the digital luminance signal y is applied, which was derived from the transmitted and received television signal in the known manner.

The memory sp contains multiplier factors b1, b2; g1, g2; r1, r2, which are defined as follows:

b'=s(b-y)b1, b"=s(r-y)b2

g'=s(b-y)g1, g"=s(r-y)g2,

r'=s(b-y)r1, r"=s(r-y)r2.

As can be seen, it is possible to influence with these six multiplier factors the composition of the signals provided at the outputs of the three adders a1, a2, a3 and, consequently, the analog signals provided at the outputs of the three digital-to-analog converters d1, d2, d3 following the adders.

The multiplier factors b1, b2; g1, g2; r1, r2, or their numerical values, are permanently stored in the memory sp by the manufacturer of the color-television receiver, or they may be variable or adjustable during operation of the color-television receiver by a corresponding signal fed to the memory. Such adjustability may be considered to be provided by the above-mentioned tint control feature in NTSC color-television receivers, as will be described below. The variability of the multiplier factors contained in the memory sp may also be used to produce color effects in the picture, e.g., by generating, with a suitable circuit, a periodically or temporarily variable signal with which the transmitted and received color combination can be changed, e.g., turned into the complementary colors. Such a variable signal may also originate directly from the transmitted and received color-television signal, as is the case, for example, in a recent variant of the NTSC system, the so-called vertical interval reference (VIR) system, in which on the nineteenth line of each transmitted field, a reference signal for the correct color is transmitted which is used for automatic color correction in the receiver.

If conventional color-picture tubes are to be driven with an analog luminance signal Y according to the known equation Y=0.3R+0.59G+0.11B, the multiplier factors have the following decimal numerical values:

b1=1/b*; b2=r=0; g1=-0.19b*, g2=-0.51/r*; r2=1/r*,

where b* and r* are factors by which the blue- and red-minus-luminance signals, respectively, are multiplied at the transmitting end in accordance with the transmitter's color-television standard. For the PAL and NTSC standards, the values of these factors are b*=0.493 and r*=0.877, while those for the SECAM standard are b*=1.5 and r*=-1.9, as is well known.

In the aforementioned special variant of driving conventional color-picture tubes, the numerical values are thus stored in the memory sp by the set manufacturer depending on the television standard for which the color-television receiver is designed. The memory is preferably a static memory, particularly a read-only memory or any of the various kinds of programmable and reprogrammable read-only memories.

The digital circuit in accordance with the invention not only can be used to drive conventional color-picture tubes but also is capable of driving color-picture tubes whose color loci differ from those of conventional color-picture tubes that are driven with an analog luminance signal Y according to the above equation. Such color-picture tubes are driven by the following equation: Y=0.3R'R+0.59G'G+0.77B'B

and the multiplier factors have the following decimal numerical values:

B1=1/b*; b2=r1=0; g1=-0.19B'/G'b*, g2=-0.51R'/G'r*; r2=1/r*,

where the factors b* and r* have the same meaning as above. The embodiment just described thus permits nonstandard color-picture tubes to be used for signals transmitted by the usual television standards without the need for significant extra circuitry.

FIG. 2 shows a block diagram of the above-outlined variant of the invention in which the values of the multiplier factors b1 . . . r2 contained in the memory sp can be changed by application of an external control signal u.

FIG. 3 shows the block diagram of a modification of the digital circuit according to the invention for color correction ("tint control") in NTSC color-television receivers. The memory sp contains numerical values for the two goniometric functions sin α and cos α and is controlled by a signal representing the corresponding argument α. The two multiplier factors g1 and g2 are zero, so that no values are stored for them, and the second adder a1 of FIGS. 1 and 2 is no longer necessary. The argument α is the phase angle between the digital blue-minus-luminance signal b-y and the color burst, which angle can be set by the user of the color-television receiver or adjusts itself automatically in the recent NTSC system mentioned above.

The remaining adders a1' and a3' in the modification of FIG. 3 are fed only with the signal pairs b', b" and r', r", respectively, but not with the digital luminance signal y; the latter is fed to the second digital-to-analog converter d2', which converts it into the analog luminance signal Y. The two other digital-to-analog converters d1 and d3 convert the output signals of the two adders a1' and a2' into the analog color-difference signals B-Y and R-Y, respectively.

The three analog signals just mentioned are fed to the usual analog R-G-B matrix mt, whose outputs provide the analog color signals B, G, and R.

It should be noted here that in the modification of FIG. 3, the factors b* and r* of the arrangements of FIGS. 1 and 2 do not belong the values stored in the memory sp, as can be seen; they are taken into account in the known manner by a suitable design of the R-G-B matrix mt.

In the arrangement of FIG. 3, the multiplier factors have the following values:

B1=r2=cos α; b2=sin α; r1=-sin α; g1=g2=0.

The negative sine function for the multiplier factor r1 can be realized either by storing the corresponding values in the memory sp in the binary two's complement, for example, or by making the third adder a3' switchable to "subtraction".

Other References:
"What is the Impact of Digital TV?", Thomas Fischer, IEEE Transactions on Consumer Electronics, vol. CE-28, No. 3, Aug. 82.

Assignee:ITT Industries, Inc. (New York, NY)

Other References:

Digital Signal Processing for the Marconi Line Array Telecine, R. Matchell, Marconi Communication Systems, Montreux Record, 1983.
U.S. patent application, Ser. No. 405,031, Reduced Data Rate Digital Comb Filter, H. G. Lewis, Jr. & T. V. Bolger, Filed 8/4/82.
The Marconi B3410 Line-Array Telecine, Communications & Broadcasting, Feb. 1982, vol. 7, No. 2, pp. 33-38.
The Marconi B3410 Line Array Telecine, SMPTE Journal, Nov. 1982, pp. 1066-1070.
Digital Video Processing for Telecine, A de M. Fremont, Communications & Broadcasting, vol. 8, No. 2, Feb. 1982, pp. 35-40. 

 

LOEWE ARCADA 72-100 PIP (53471L39)  CHASSIS Q2100  (110Q21) Digital integrated chrominance-channel circuit with gain control:

(Pal) Video Processing Unit (VPU - PVPU)An improved digital integrated chrominance-channel circuit having gain control for color-television receivers includes at least one integrated circuit for digitally processing the composite color signal. The circuit includes a first limiter inserted between a parallel multiplier and a burst-amplitude-measuring stage, and a control stage including a parallel subtracter whose minuend input is fed with a reference signal, and whose subtrahend input is connected to the output of the burst-amplitude-measuring stage. A digital accumulator whose enable input is presented with a signal derived from the trailing edge of a burst gating signal is used as an integrator.

1. A digital integrated chrominance-channel circuit with gain control for color-television receivers, comprising:
at least one integrated circuit for digitally processing the composite color signal, wherein a digital chrominance signal appearing at an output of a digital chroma filter is applied to a first input of a parallel multiplier, and a digital gain control signal is applied to a second input of the parallel multiplier, the output of the parallel multiplier is connected to an input of a digital chroma demodulator with a color killer stage and to an input of a burst-amplitude-measuring stage whose output signal is compared with a reference signal in a control stage, the output signal of the control stage passes through an integrator whose output signal is the gain control signal;
a square-wave clock generator used as a chrominance subcarrier oscillator generates at least a first clock signal, whose frequency is four times that of the chrominance subcarrier, and a second clock signal, whose frequency is equal to that of the chrominance subcarrier; and
a first limiter is inserted between the parallel multiplier and the burst-amplitude-measuring stage, the control stage is a parallel subtracter whose minuend input is presented with the reference signal, and whose subtrahend input is connected to the output of the burst-amplitude-measuring stage and the integrator is a digital accumulator whose enable input is fed with a signal derived from the trailing edge of a burst gating signal.
2. A chrominance-channel circuit as claimed in claim 1, wherein the output signal from the first limiter is applied to the input of a first buffer memory and, through a delay element which provides a delay equal to the period of the first clock signal, to the input of a second buffer memory, the second clock signal being applied to the enable inputs of the first and second buffer memories during the burst gating signal, the output signals from the first buffer memory and the second buffer memory are fed, respectively, to a first absolute-value former and a second absolute-value former which have their outputs connected to the first and the second input, respectively, of a first parallel adder, the output of the first parallel adder is connected via a second limiter to the input of a third buffer memory and to the minuend input of a parallel comparator whose minuend-greater-than-subtrahend output is coupled to the enable input of the third buffer memory through the first input-output path of an AND gate whose second input is fed with the second clock signal, and the output of the third buffer memory is coupled to the subtrahend input of the parallel comparator, the output of the third buffer memory is connected to the input of a fourth buffer memory whose output is coupled to the subtrahend input of the parallel subtracter, and whose enable input is fed with a signal derived from the leading edges of horizontal-frequency pulses not coinciding with the burst gating signal, and the clear input of the third buffer memory is fed with a signal derived from the trailing edges of the pulses not coinciding with the burst gating signal. 3. A chrominance-channel circuit as claimed in claim 1, wherein the output signal from the parallel subtracter is applied to the first input of a second parallel adder having its output connected via a third limiter to the input of a fifth buffer memory whose output is coupled to the second input of the second parallel adder, and which has normalizing-data inputs and the enable input of the accumulator. 4. A chrominance-channel circuit as claimed in claim 2, wherein the output signal from the parallel subtracter is applied to the first input of a second parallel adder having its output connected via a third limiter to the input of a fifth buffer memory whose output is coupled to the second input of the second parallel adder, and which has normalizing-data inputs and the enable input of the accumulator. 5. A chrominance-channel circuit as claimed in claim 1, additionally comprising:
a first bus switch having its path from the break-contact input to the output inserted between the output of the chroma filter and the associated input of the parallel multiplier and its make-contact input connected to the input of the chroma filter;
a second bus switch having its path from the break-contact input to the output inserted between the output of the first limiter and the input of the chroma demodulator and its make-contact input connected to the input of the chroma filter;
a first test enable signal and a second test enable signal, which does not overlap the first test enable signal, being applied to the control input of the first bus switch and to the control input of the second bus switch, respectively;
an actuating signal being applied to the input of the color killer stage during the second test enable signal;
a normalizing signal being applied to the enable input of the fifth buffer memory during a third test enable signal; and
in addition to the usual contact pads, there is a contact pad via which the test-result signals of the individual subcircuits are accessible.
6. A chrominance-channel circuit as claimed in claim 2, additionally comprising:
a first bus switch having its path from the break-contact input to the output inserted between the output of the chroma filter and the associated input of the parallel multiplier and its make-contact input connected to the input of the chroma filter;
a second bus switch having its path from the break-contact input to the output inserted between the output of the first limiter and the input of the chroma demodulator and its make-contact input connected to the input of the chroma filter;
a first test enable signal and a second test enable signal, which does not overlap the first test enable signal, being applied to the control input of the first bus switch and to the control input of the second bus switch, respectively;
an actuating signal being applied to the input of the color killer stage during the second test enable signal;
a normalizing signal being applied to the enable input of the fifth buffer memory during a third test enable signal; and
in addition to the usual contact pads, there is a contact pad via which the test-result signals of the individual subcircuits are accessible.
7. A chrominance-channel circuit as claimed in claim 3, additionally comprising:
a first bus switch having its path from the break-contact input to the output inserted between the output of the chroma filter and the associated input of the parallel multiplier and its make-contact input connected to the input of the chroma filter;
a second bus switch having its path from the break-contact input to the output inserted between the output of the first limiter and the input of the chroma demodulator and its make-contact input connected to the input of the chroma filter;
a first test enable signal and a second test enable signal, which does not overlap the first test enable signal, being applied to the control input of the first bus switch and to the control input of the second bus switch, respectively;
an actuating signal being applied to the input of the color killer stage during the second test enable signal;
a normalizing signal being applied to the enable input of the fifth buffer memory during a third test enable signal; and
in addition to the usual contact pads, there is a contact pad via which the test-result signals of the individual subcircuits are accessible.
8. A chrominance-channel circuit as claimed in claim 4, additionally comprising:
a first bus switch having its path from the break-contact input to the output inserted between the output of the chroma filter and the associated input of the parallel multiplier and its make-contact input connected to the input of the chroma filter;
a second bus switch having its path from the break-contact input to the output inserted between the output of the first limiter and the input of the chroma demodulator and its make-contact input connected to the input of the chroma filter;
a first test enable signal and a second test enable signal, which does not overlap the first test enable signal, being applied to the control input of the first bus switch, respectively;
an actuating signal being applied to the input of the color killer stage during the second test enable signal;
a normalizing signal being applied to the enable input of the fifth buffer memory during a third test enable signal; and
in addition to the usual contact pads, there is a contact pad via which the test-result signals of the individual subcircuits are accessible.
9. A method of testing a chrominance-channel circuit as claimed in claim 5, characterized by the following features:
in a first step, the chroma demodulator is tested by applying the second test enable signal to the control input of the second bus switch, the actuating signal to the input of the color killer stage, and a known data sequence to the input of the chroma filter;
in a second step, the parallel multiplier is tested by applying the first test enable signal to the control input of the first bus switch, the third test enable signal and the normalizing signal to the enable input of the accumulator, the normalizing data to the normalizing-data input of the accumulator, and a known data sequence to the input of the chroma filter;
in further steps, the absolute-value formers the first adder, and the parallel comparator are tested by applying the first test enable signal to the control input of the first bus switch, and known data sequences to the input of the chroma filter, and
in the last step, the accumulator is tested by applying the first test enable signal to the control input of the first bus switch, the third test enable signal and the normalizing signal to the enable input of the accumulator, the normalizing data to the normalizing data to the normalizing-data input of the accumulator, a trigger signal to the second limiter, and known data sequences to the minuend input of the parallel sub- tracter.
10. A method of testing a chrominance-channel circuit as claimed in claim 6, characterized by the following features:
in a first step, the chroma demodulator is tested by applying the second test enable signal to the control input of the second bus switch, the actuating signal to the input of the color killer stage, and a known data sequence to the input of the chroma filter;
in a second step, the parallel multiplier is tested by applying the first test enable signal to the control input of the first bus switch, the third test enable signal and the normalizing signal to the enable input of the accumulator, the normalizing data to the normalizing-data input of the accumulator, and a known data sequence to the input of the chroma filter;
in further steps, the absolute-value formers the first adder, and the parallel comparator are tested by applying the first test enable signal to the control input of the first bus switch, and known data sequences to the input of the chroma filter, and
in the last step, the accumulator is tested by applying the first test enable signal to the control input of the first bus switch, the third test enable signal and the normalizing signal to the enable input of the accumulator, the normalizing data to the normalizing-data input of the accumulator, a trigger signal to the second limiter, and known data sequences to the minuend input of the parallel subtracter.
11. A method of testing a chrominance-channel circuit as claimed in claim 7, characterized by the following features:
in a first step, the chroma demodulator is tested by applying the second test enable signal to the control input of the second bus switch, the actuating signal to the input of the color killer stage, and a known data sequence to the input of the chroma filter;

in a second step, the parallel multiplier is tested by applying the first test enable signal to the control input of the first bus switch, the third test enable signal and the normalizing signal to the enable input of the accumulator, the normalizing data to the normalizing-data input of the accumulator, and a known data sequence to the input of the chroma filter;
in further steps, the absolute-value formers the first adder, and the parallel comparator are tested by applying the first test enable signal to the control input of the first bus switch, and known data sequences to the input of the chroma filter, and
in the last step, the accumulator is tested by applying the first test enable signal to the control input of the first bus switch, the third test enable signal and the normalizing signal to the enable input of the accumulator, the normalizing data to the normalizing-data input of the accumulator, a trigger signal to the second limiter, and known data sequences to the minuend input of the parallel subtracter.
12. A method of testing a chrominance-channel circuit as claimed in claim 8, characterized by the following features:
in a first step, the chroma demodulator is tested by applying the second test enable signal to the control input of the second bus switch, the actuating signal to the input of the color killer stage, and a known data sequence to the input of the chroma filter;
in a second step, the parallel multiplier is tested by applying the first test enable signal to the control input of the first bus switch, the third test enable signal and the normalizing signal to the enable input of the accumulator, the normalizing data to the normalizing-data input of the accumulator, and a known data sequence to the input of the chroma filter;
in further steps, the absolute-value formers the first adder, and the parallel comparator are tested by applying the first test enable signal to the control input of the first bus switch, and known data sequences to the input of the chroma filter, and
in the last step, the accumulator is tested by applying the first test enable signal to the control input of the first bus switch, the third test enable signal and the normalizing signal to the enable input of the accumulator, the normalizing data to the normalizing-data input of the accumulator, a trigger signal to the second limiter, and known data sequences to the minuend input of the parallel subtracter.

Description:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a digital integrated chrominance-channel circuit with gain control for color-television receivers containing at least one integrated circuit for digitally processing the composite color signal.
2. Description of the Prior Art
A chrominance-channel circuit is disclosed in the published patent application EP 51075 Al. (U.S. application Ser. No. 311,218, Oct. 11, 1981).
Practical tests of color-television receivers with digital signal processing circuitry have shown that the prior art chrominance-channel circuit still has a few disadvantages. For example, the burst-amplitude-measuring circuit is not yet optimal because it is possible in the prior art arrangement that the burst signals are sampled, i.e., measured, near or at the zero crossing. As these measured values are small, so that the digitized values formed therefrom are small numbers, the measurement error is large.
Another disadvantage of the prior art arrangement is that it has two set points for the gain control, namely a lower and an upper threshold level in the form of corresponding numbers entered into two read-only memories. Finally, the integration of the control signal is implemented with two counters, so that the time constant of this "integrator" is determined only by the clock signals for the counters and by the count lengths of these counters. As to the prior art, reference is also made to the journal "Fernseh- und Kino-Technik", 1981, pages 317 to 323, particularly FIG. 9 on page 321. However, the digital chrominance-channel circuit shown there works on the principle of feed-forward control, while both the invention and the above-mentioned prior art use a feedback control system, so that the arrangement disclosed in that journal lies further away from the present invention, the more so since in that prior art arrangement, the set point is implemented only with the concrete circuit (hardware).
SUMMARY OF THE INVENTION
The invention as claimed eliminates the above disadvantages and, thus, has for its object to improve the prior art digital integrated chrominance-channel circuit with gain control in such a way that error-free burst amplitude measurement is ensured, that a single set point can be generated, and that the integration of the control signal is implemented in optimum fashion. Another object of the invention is to modify the chrominance-channel circuit so that the automatic control system can be opened for measuring purposes.
DESCRIPTION OF THE DRAWINGS
FIG. 1 is a block diagram of the chrominance channel in accordance with the invention.
FIG. 2 is a block diagram of a preferred embodiment of the burst-amplitude-measuring stage and the digital accumulator.
FIG. 3 is a block diagram of another embodiment of the invention with the aforementioned measuring facility.
DESCRIPTION OF THE INVENTION
The block diagram of FIG. 1 includes a digital chroma filter cf, which derives a digital chrominance signal cs from a digitized composite color signal. The digital chrominance signal cs is applied to a first input of a parallel multiplier m, whose second input is fed with a digital gain control signal st. The output of the parallel multiplier m is connected to an input of a first limiter b1, which limits the output signals from the parallel multiplier m to a predetermined value. This can be done by arranging, for example, that at least one of the high-order digits of the output signal from the parallel multiplier is indicated by the interconnecting lead between these two subcircuits in FIG. 1.
In the figures of the accompanying drawing, the lines interconnecting the signal inputs and outputs of the individual subcircuits are shown as stripelike connections (buses), while the solid lines commonly used to indicate interconnections in discrete-component circuits are used for interconnections over which only individual bits or clock and/or noise signals are transferred. The stripelike lines thus interconnect parallel inputs and parallel outputs, i.e., inputs to which complete binary words are applied, which are transferred in parallel into the subcircuit at a given time, and outputs which provide complete binary words.
An output signal bs of the first limiter b1 is applied to the input of a burst-amplitude-measuring stage bm, which has its output coupled to a subtrahend input (-) of a parallel subtracter sb, while its minuend input (+) is fed with the reference signal rs, i.e., the set point. The output of the parallel subtracter sb is connected to the input of a digital accumulator ak, which provides the digital gain control signal st, which is applied to the second input of the parallel multiplier m, as mentioned above. A signal rb derived from the trailing edge of the burst gating signal (keying pulse) is applied to an enable input eu of the accumulator ak.
It is also indicated in FIG. 1 that a square-wave clock generator os, used as a chrominance-subcarrier oscillator, forms part of the invention. It provides at least the first clock signal f1, whose frequency is four times that of the chrominance subcarrier, and a second clock signal f2, having the same frequency as the chrominance subcarrier.
FIG. 2 is a block diagram of a preferred embodiment of the burst-amplitude-measuring stage bm and the digital accumulator ak of FIG. 1. The burst-amplitude-measuring stage in FIG. 2 comprises all subcircuits ahead of the subtrahend input (-) of the parallel subtracter sb, while the accumulator consists of the subcircuits following the output of the parallel subtracter sb.
The output signal bs from the first limiter b1 of FIG. 1 is applied in FIG. 2 to the input of a first buffer memory p1 and, through a delay element v, which provides a delay equal to the period of the first clock signal f1, i.e., to one quarter or 90° of the chrominance-subcarrier frequency, to an input of a second buffer memory p2.
The second clock signal f2 is applied to the enable inputs eu of these two buffer memories p1, p2 during the burst gating signal ki, which is indicated in FIG. 2 by the logical term f2.ki. During the keying pulse ki, whose duration usually equals about 10 periods of the chrominance-subcarrier frequency, a corresponding number of digital values are thus transferred successively from the first limiter b1 into the two buffer memories p1, p2, the values transferred into the second buffer memory p2 differing in phase from those transferred into the first buffer memory p1 by the aforementioned 90°; thus, two zero-crossing values are never evaluated at the same time.
The outputs of the two buffer memories p1, p2 are connected to the inputs of a first absolute-value former bb1 and a second absolute-value former bb2, respectively, whose outputs are coupled to a first and a second input, respectively, of a first adder a1. The absolute-value formers bb1, bb2 provide digital values without the sign of the input value, i.e., without the sign bit, for example. They thus contain a subcircuit which converts negative numbers in one's or two's complement notation into the corresponding positive number, i.e., they include complement reconverters.
The first adder a1 is followed by the second limiter b2, whose limiting action is controlled by at least one of the high-order digits of the first adder a1.
The output signal from the second limiter b2 is applied to the input of a third buffer memory p3 and to a minuend input a of a parallel comparator k, which has its subtrahend input b connected to the output of the third buffer memory p3.
In the present description, the two inputs of the parallel comparator k, too, are referred to as "minuend input" and "subtrahend input", respectively, which is considered justifiable in view of the fact that, purely formally, the arithmetic operation performed by comparators is more closely related to subtraction than to addition by means of an adder, even though the internal circuit of a comparator resembles that of an adder more than that of a subtracter, cf. the corresponding mathematical operations a-b and a b as opposed to a+b.
The minuend-greater-than-subtrahend output a>b of the parallel comparator k is connected to the enable input eu of the third buffer memory p3 via the first input-output path of the AND gate u, while the second clock signal f2 is applied to the second input of the AND gate u. The output of the third buffer memory p3 is also connected to an input of a fourth buffer memory p4, which has its output coupled to the subtrahend input (-) of the parallel subtracter sb. The enable input eu of the fourth buffer memory p4 is presented with a signal vz derived from the trailing edges of horizontal-frequency pulses zf, which, however, do not coincide with the burst gating signal ki, while a signal rz derived from the trailing edges of the horizontal-frequency pulses zf not coinciding with the burst gating signal ki is applied to the clear input el of the third buffer memory p3.
The derivation of the two signals rz, vz from the horizontal-frequency pulses zf is indicated in FIG. 2 by a pulse-shaper stage if. The section consisting of the two buffer memories p3, p4, the parallel comparator k, the AND gate u, and the pulse shaper if determines, for each line of the television picture, the maximum value of the burst amplitude from the--possibly limited--output signal of the first adder a1, and feeds this maximum value to the subtrahend input (-) of the parallel subtracter sb. This is achieved essentially by transferring only those words of the output signal of the second limiter b2 into the third buffer memory p3 which are greater than any word already stored in the third buffer memory p3. This is done line by line during the keying pulse ki.
As mentioned, a preferred embodiment of the accumulator ak of FIG. 1 is shown in the lower portion of FIG. 2. The output signal from the parallel subtracter sb is applied to a first input of a second parallel adder a2, which has its output connected to an input of a fifth buffer memory p5 through the third limiter b3. To realize the adding function, the output of the fifth buffer memory p5 is connected to the second input of the second adder a2. The buffer memory p5 has, in addition to the enable input eu, which is the enable input of the accumulator ak of FIG. 1, the normalizing-data inputs ne, through which normalizing data nd, i.e., known data, can be entered if necessary. The enable input eu is presented with the signal rb derived from the trailing edge of the burst gating signal ki. With the trailing edge of the keying pulse, the output signal from the third limiter b3 is thus transferred into the fifth buffer memory p5 and simultaneously transferred to the output. With the trailing edge of each keying pulse, the sum of the value from the preceding line and the set-point deviation calculated in the measured line by the parallel subtracter sb is thus produced line by line as the control signal st.
Thus, the essential advantages of the invention follow directly from the solution of the problem, namely particularly the line-by-line subtraction of the maximum burst amplitude, which is integrated in the accumulator ak to form the control signal st for the automatic control system, from the reference signal rs.
FIG. 3, a block diagram like FIGS. 1 and 2, shows a preferred embodiment of the invention which makes it possible to test the digital automatic control system after the fabrication of the integrated circuit, and to make the test-result signals accessible. The testing is necessary because the automatic control system contains several subcircuits each of which may be faulty. The test procedure and the design of the overall circuit must therefore be adapted to one another in such a way that all subcircuits of the automatic control system can be tested with little additional circuitry.
To this end, the path from a break-contact input to an output of a first bus switch bu1, whose make-contact input is connected to the input of the chroma filter cf, is interposed between the output of this chroma filter and the associated input of the parallel multiplier m, as shown in the block diagram of FIG. 3. For the graphic representation of the bus switch bu1, the symbol of a mechanical transfer switch has been chosen, with the above mentioned stripelike interconnecting lines, i.e., buses, connected to the signal inputs and the output of the switch. It is thus clear that the bus switch consists of as many individual electronic switches as there are wires in the buses.
Inserted between the output of the first limiter b1 and the input of the chroma demodulator cd, which is also present in FIG. 1, where it "demodulates" the output signal bs of the first limiter b1 into the chroma signal cs, is a path from a break-contact input to an output of a second bus switch bu2, which has its make-contact input am connected to the input of the chroma filter cf. Viewed in the direction of signal flow, the second bus switch bu2 lies behind the junction point where the signal bs for the burst-amplitude-measuring circuit is taken off. What was said on the circuit design and the graphic representation of the first bus switch bu1 applies analogously to the second bus switch bu2.
The first test enable signal t1 and the second test enable signal t2, which does not overlap the first test enable signal t1, are applied to the control input of the first bus switch bu1 and to the control input of the second bus switch bu2, respectively. Thus, when the second bus switch bu2 is in its "make" position, the first bus switch bu2 is in its "break" position, and vice versa.
During the first test enable signal t1, an actuating signal db is applied to the input ec of the color killer stage ck of the chroma demodulator cd, so that the latter is active during the testing of the automatic control system although the circuit is not in its normal mode of operation but only in a test mode.

The enable input eu of the accumulator ak, i.e., the enable input eu of the fifth buffer memory p5 in FIG. 3, may be fed with a normalizing signal ns during the third test enable signal t3. During testing and measurement, instead of the signal rb, derived from the trailing edge of the keying pulse and applied in the normal mode of operation, the normalizing signal ns is applied to the enable input eu of the fifth buffer memory p5 and causes the normalizing data nd to be transferred into this buffer.
In addition to the usual contact pads of the integrated circuit, through part of which the output signal cs of the chroma demodulator cd is coupled out, a contact pad is provided via which test-result signals of individual subcircuits are accessible, i.e., transferred out of the integrated circuit. These test-result signals are advantageously coupled to this additional contact pad through transfer transistors which, in turn, are driven by the above-mentioned test enable signals or corresponding additional signals of this kind or by signals derived by performing simple logic operations on the signals just mentioned. In this manner, only the respective subcircuit to be tested is connected to the additional contact pad.
An advantageous method of testing the chrominance-channel circuit according to the invention consists in the following time sequence of test steps. In the first step, the chroma demodulator cd is tested. This is necessary because, throughout the testing of the chrominance-channel circuit, signals are transferred out through the chroma demodulator cd and must not be falsified by the latter.
This first test step is performed by applying the second test enable signal t2 to the control input of the second bus switch bu2, the actuating signal db to the input ec of the color killer stage ck, and a known data sequence, i.e., a test-data sequence, to the input of the chroma filter cf. The application of the actuating signal db to the input ec of the color killer stage ck is necessary because an actual actuating signal coming from other stages of the chrominance-channel circuit is applied to the color killer only during normal operation of the chrominance-channel circuit, cf. the above-mentioned printed publication EP 0 051 075 Al.
In response to the application of the second test enable signal t2 to the second bus switch bu2, the input signals of the chroma filter cf are transferred directly to the input of the chroma demodulator cd, so that, if a known test-data sequence is used, the performance of the chroma demodulator cd can be checked by means of the output signals.
In the second step, the parallel multiplier m is tested. This is done by applying the first test enable signal t1 to the control input of the first bus switch bu1, the third test enable signal t3 and the normalizing signal ns to the enable input of the accumulator ak, i.e., to the enable input of the fifth buffer memory p5, for example; the normalizing data nd are applied to the normalizing-data input ne of the fifth buffer memory p5, and a known data sequence, i.e., a test-data sequence, is applied to the input of the chroma filter cf.
As in the first test, the first test enable signal t1 causes the test-data sequence to bypass the chroma filter cf, so that the test data are applied directly to one input of the parallel multiplier m. This bypassing of the chroma filter cf is necessary because the chroma filter is generally a dynamic subcircuit, which is not suitable for being included in the individual tests for this reason alone.
As a result of the entry of normalizing data into the accumulator ak or into the fifth buffer memory p5 as a subcircuit of the accumulator, known data are also applied to the second input of the parallel multiplier m, so that the output signal of the latter is predeterminable, which makes it possible to check the correct functioning of the multiplier. Since the chroma demodulator cd was tested already in the first test step, the data appearing at its output during the second test step are the unchanged output data of the parallel multiplier m if the chroma demodulator cd was found to operate correctly.
Further tests may now be performed on the absolute-value formers bb1, bb2, the first adder a1, and the parallel comparator k. To do this, the first test enable signal t1 is applied to the control input of the first bus switch bu1, and known data sequences are applied to the input of the chroma filter cf, the individual test results being accessible via the above-mentioned additional contact pad and being generally present in the form of a go/no-go decision.
The last test to be performed is that of the accumulator ak. To this end, the first test enable signal t1 is applied to the control input of the first bus switch bu1; the third test enable signal t3 and the normalizing signal ns are applied to the enable input of the accumulator ak, i.e., to the corresponding input of the fifth buffer memory p5, for example; a trigger signal is applied to the second limiter b2, and known data sequences are fed to the minuend input (+) of the parallel subtracter sb. With the second limiter sb2 triggered, one of the input signals of the accumulator is predetermined and, thus, known because the output data of the subtracter sb are known as well. The accumulator ak can thus be tested by varying the reference data rs.
The reference data rs, the above-mentioned various test-data sequences, and the normalizing data nd may come from a microprocessor.

 LOEWE ARCADA 72-100 PIP (53471L39)  CHASSIS Q2100  (110Q21) Digital horizontal-deflection circuit:

Digital deflection Processor (DPU) Instead of fine-controlling the horizontal deflection signal in a digital television receiver by means of two phase-locked loops and gate-delay stages as is done in prior art arrangements, in the horizontal-deflection circuit according to the invention, a first digital word delivered by a first phase-locked loop and representative of the horizontal frequency is added in an adder to a suitably amplified third digital word delivered by a phase comparator of a second phase-locked loop. The output of the adder is fed to the control input of a digital sine-wave generator which drives a frequency divider. The latter delivers the horizontal deflection signal, which drives the horizontal output stage. The phase comparator is fed with the horizontal flyback signal, which is derived from the horizontal deflection signal, and a second digital word generated by the first phase-locked loop and representative of the desired phase position of the flyback signal.

What is claimed is: 1. A digital horizontal-deflection circuit for generating an analog horizontal deflection signal driving the horizontal output stage of a digital television receiver clocked with a system clock, comprising:
a first digital phase-locked loop which synchronizes the horizontal deflection signal with the horizontal synchronizing signal separated from the composite color signal and delivers for each line of video signal a first digital word representative of the horizontal frequency and a second digital word representative of the desired phase position of the horizontal flyback signal;
a second phase-locked loop which uses a digital phase comparator to generate a third digital word representative of the phase deviation of the horizontal flyback signal from the desired position and shifts the horizontal deflection signal in time so that the horizontal flyback signal takes up the desired phase position;
an adder having a first input to which said first digital word is fed and a second input to which said third digital word is fed via a multiplier serving as an amplifier;
a digital sine-wave generator having a control input to which the output of said adder is fed; and
a frequency divider to which the output of said digital sine-wave generator is supplied, the output of said frequency divider providing the horizontal deflection signal.
2. A horizontal-deflection circuit as defined in claim wherein said first digital word is representative of the period of the horizontal deflection signal, and additionally comprising a digital period-to-frequency converter connected between said first phase-locked loop and said first input of said adder. 3. A horizontal-deflection circuit as defined in claims 1 or 2, additionally comprising a protection circuit coupled between the output of said digital sine-wave generator and the input of said frequency divider, said protection circuit providing a sine-wave signal of a desired frequency if the frequency of said sine-wave generator departs from a desired-value range. 4. A horizontal-deflection circuit as defined in claim 3, wherein said protection circuit is an analog phase-locked loop.

Description:

BACKGROUND OF THE INVENTION
The present invention relates to a digital horizontal-deflection circuit for generating an analog horizontal deflection signal driving the horizontal output stage of a digital television receiver clocked with a system clock. A digital horizontal-deflection circuit of this kind is described in a data book of Intermetall, "DIGIT 2000 VLSI Digital TV System," 1984/5, pages 112 to 114, which deal with the integrated circuit DPU 2500.
In the prior art arrangement, the phase variation which is necessary for the digital generation of the horizontal deflection signal and must be stepped in fractions of the period of the system clock is achieved essentially by the use of gate-delay stages or chains as are described, for example, in the European Patent Applications EP-A Nos. 0,059,802; 0,080,970; and 0,116,669, which essentially utilize the inherent delay of inverters. It turned out, however, that with these arrangements, it is not possible to completely control all operating conditions which may occur.
SUMMARY OF THE INVENTION
It is, therefore, the object of the invention to modify and improve the digital horizontal-deflection circuit described in the above prior art in such a way that the gate-delay stages can be dispensed with.
DETAILED DESCRIPTION OF A PREFERRED EMBODIMENT
The invention will now be explained in more detail with reference to the single FIGURE of the accompanying drawing, which is a block diagram of an embodiment of the invention. The block diagram shows that portion of a digital television receiver, i.e., of a television receiver in which the analog signal received via the antenna is processed digitally, which is of interest in connection with the invention. Thus, all subcircuits for digital-to-analog conversion, sync separation, chrominance-signal and luminance-signal processing or sound-signal processing have been omitted; the overall circuit concept of digital television receivers has been well known for some time.
The first digital phase-locked loop (PLL) p1 is supplied with the (digital) horizontal synchronizing signal hs, which was separated from the composite color signal, and the system clock st, and derives therefrom, in the manner described in the prior art, the first digital word d1, which is representative of the horizontal frequency, and the second digital word d2, which is representative of the desired phase position of the horizontal flyback signal fy. The signal fy comes from the receiver's horizontal output stage ps, which supplies the necessary sawtooth current to the deflection coil 1. The phase position of the flyback signal fy relative to the horizontal deflection signal ps is dependent on the switching properties of the horizontal output stage ps and is also influenced by the video signal applied to the picture tube.
By means of the second PLL p2, indicated in the FIGURE by the large rectangle bounded by a broken line, these dependences are compensated in the manner described in the prior art. The phase comparator pv generates the third digital word d3, which is representative of the phase deviation of the flyback signal fy from its desired position, and the second PLL p2 shifts the horizontal deflection signal ds in time so that the flyback signal fy takes up the desired phase position.
The first digital word d1 is fed to the first input of the adder ad, and the third digital word d3 is fed to the second input of this adder via the multiplier m, which serves as an amplifier. The second input of the multiplier m is fed with the signal k determining the gain of the second PLL p2, so that the transient response of the latter can be optimally adjusted by the manufacturer of the television receiver.
The output of the adder ad is fed to the control input of the digital sine-wave generator s, which may be designed as an accumulator followed by a sine looker table (ROM). If an n-bit word d4 is applied to its control input, this arrangement, which is known in principle, delivers a sine-wave of frequency (d4)fs/2 ⁿ , where fs is the frequency of the system clock st.
The output of the digital sine-wave generator sg is fed to the frequency divider ft, which provides the horizontal deflection signal ds, a square-wave signal as usual. The frequency divider ft thus not only divides the frequency of the signal delivered by the sine-wave generator sg, but also converts the sine-wave signal into the above-mentioned square-wave signal; this can be done in a suitable sine-to-square wave converter stage at the input of the frequency divider ft.
Two stages which can be added to the arrangement singly or in combination are indicated in the FIGURE by rectangles bounded by broken lines. The period-to-frequency converter fw between the output of the first PLL pl for the first digital word d1 and the corresponding input of the adder ad is necessary if the first digital word d1, generated by the first PLL p1, represents the period of the horizontal deflection signal ds (if this word represents the frequency of the horizontal deflection signal, the stage fw is not necessary).
Between the output of the digital sine-wave generator sg and the input of the frequency divider ft, the protection circuit sc may be inserted. It is preferably an analog phase-locked loop which provides a sine-wave signal of the desired frequency if the frequency of the sine-wave generator sg departs from a predetermined desired-value range. This may be to advantage during the start-up phase after the turning on of the television receiver or may serve to afford protection in the event of a failure of one or both of the PLL's p1, p2.
In the FIGURE, the stripe-like connecting leads represent signal paths over which digital signals are transferred in parallel, i.e., on these buses, the individual (parallel) digital words follow one after the other at the pulse repetition rate of the system clock st. The fact that the individual stages of the second PLL p2--where necessary and appropriate--and the period-to-frequency converter fw are clocked with the system clock st, too, is indicated by the respective clock input lines.
The digital horizontal-deflection circuit in accordance with the invention is preferably realized using monolithic integrated circuit techniques, particularly MOS technology. It may form part of a larger integrated circuit but can also be implemented as a separate integrated circuit. 

 

 

 

 

 

LOEWE ARCADA 72-100 PIP (53471L39)  CHASSIS Q2100  (110Q21) Digital circuit for steepening color-signal transitions:

Digital Transient Improvement Processor (DTI)

This circuit arrangement is designed for use in digital color-television receivers or the like and contains for each of the two digital color-difference signals a slope detector to which both a digital signal defining an amplitude threshold value and a digital signal defining a time threshold value are applied. At least one intermediate value occurring during an edge to be steepened is stored, and at the same time value of the steepened edge, it is "inserted" into the latter. This is done by means of memories switches, output registers, and a sequence controller.

What is claimed is: 1. A circuit arrangement for steepening color-signal transitions, comprising:
first and second circuit branches, said first branch receiving a first color difference digital signal from a first color difference channel and said second branch receiving a second color difference digital signal from a second color difference channel, each of said branches comprising:
a digital slope detector for generating a control signal at an output when the respective one of said first or second color difference digital signals has a predetermined relationship to predetermined amplitude and time thresholds;
a first delay element receiving and delaying said respective one color difference digital signal by a time equal to the delay of said digital slope detector;
at least one memory having its input connected to the output of said first delay element;
a switch having first and second inputs connected to the outputs of said delay element and said at least one memory, respectively; and
an output register having its input connected to the output of said switch;
and
a sequence controller coupled to the outputs of said digital slope detectors in said first and second circuit branches, and receiving a clock signal having a predetermined frequency relationship to a chrominance subcarrier frequency, and receiving a digital signal determining the hold time equal to the known system rise time of said first and second color difference channels, said sequence controller providing sequence control signals for controlling said at least one memory, said switch and said output register in both of said first and second circuit branches such that:
a color difference signal value occurring at an intermediate value of said hold time is read into said memory, said color difference signal value stored in said memory is read via said switch into said output rergister at the corresponding intermediate value of the steepened leading edge of said color-signal, the input of said output register being connected to the output of said delay element at all times except at said intermediate value of said steepened leading edge.
2. A circuit arrangement in accordance with claim 1, wherein each said slope detector comprises:
a first digital differentiator receiving the respective color difference digital signal;
a digital absolute value stage coupled to said first digital differentiator output;
a first digital comparator having a minuend input coupled to said digital absolute value stage output, a subtrahend input supplied with a digital signal corresponding to said amplitude threshold value, and an output;
a second digital differentiator having an input coupled to said comparator output;
a counter for counting pulses of said clock signal, said counter having an enable input coupled to said comparator output, and having a reset input coupled to the output of said second digital differentiator;
a fifth memory having its inputs coupled to the count outputs of said counter and an enable input coupled to said second digital differentiator output;
a second digital comparator having a minuend input coupled to the output of said fifth memory, a subtrahend input supplied with a digital signal corresponding to said time threshold value; and
gate means for combining the output of said comparator and the output of said second digital differentiator to provide said control signal when the output of said comparator and the output of said second digital differentiator are both active.
3. A circuit arrangement in accordance with claim 2,
wherein each of said first and second circuit branches further comprises a second memory having its input connected to said first delay element output, said switch having a third input coupled to said second memory output; and
wherein said sequence controller comprises:
a counter for counting pulses of said clock signal; and
a decoder for decoding the count output of said counter to provide said sequence control signals, said sequence control signals also controlling each said second memory,
said sequence controller operating such that color difference signal values occurring at the end of the first third of said hold time are written into said at least one memory, and color difference signal values occurring at the end of the second third of said hold time are written into said second memory; and
wherein:
in said first circuit branch the contents of said at least one memory and said second memory are written via said switch into said output register at the end of the first third and at the end of the second third, respectively, of said steepened leading edge;
in said second circuit branch the contents of said at least one memory and said second memory are written via said switch into said output register at the end of the first third and the second third, respectively, of said steepened leading edge; and

the input of the respective output register of each of said first and second circuit branches is connected to the output of the respective first delay element at all times except at the end of said first third and said second third or said steepened leading edge.
4. A circuit arrangement in accordance with claim 1,
wherein each of said first and second circuit branches further comprises a second memory having its input connected to said first delay element output, said switch having a third input coupled to said second memory output;
wherein said sequence controller comprises:
a counter for counting pulses of said clock signal; and
a decoder for decoding the count output of said counter to provide said sequence control signals, said sequence control signals also controlling each said second memory,
said sequence controller operating such that color difference signal values occurring at the end of the first third of said hold time are written into said at least one memory, and color difference signal values occurring at the end of the second third of said hold time are written into said second memory; and
wherein:
in said first circuit branch the contents of said at least one memory and said second memory are written via said switch into said output register at the end of the first third and at the end of said second third, respectively, of said steepened leading edge;
in said second circuit branch the contents of said at least one memory and said second memory are written via said switch into said output register at the end of the first third and the second third, respectively, of said steepened leading edge; and
the input of the respective output register of each of said first and second circuit branches is connected to the output of the respective first delay element at all times except at the end of said first third and said second third of said steepened leading edge.

Description:

BACKGROUND OF THE INVENTION
The invention pertains to a circuit for steepening color-signal transitions in color television receivers or the like.
A circuit arrangement of this kind includes a slope detector which, when a predetermined amplitude threshold value is exceeded, delivers a switching signal which causes a substitute signal to appear at the respective output of the two color-difference channels for the duration of the system rise time of said channels. One circuit arrangement of this kind, which provides a chroma transient improvement, is described in a publication by VALVO entitled "Technische Information 840228 (Feb. 28, 1984): Versteilerung von Farbsignalsprungen and Leuchtdichtesignal-Verzogerung mit der Schaltung TDA 4560".
The bandwidth of the color-difference channel is very small compared with the bandwidth of the luminance channel, namely only about 1/5 that of the luminance channel in the television standards now in use. This narrow bandwidth leads to blurred color transitions ("color edging") in case of sudden color-signal changes, e.g., at the edges of the usual color-bar test signal, because, compared with the associated luminance-signal transition, an approximately fivefold duration of the color-signal transition results from the narrow transmission bandwidth.
In the prior circuit arrangement, the relatively slowly rising color-signal edges are steepened by suitably delaying the color-difference signals and the luminance signal and steepening the edges of the color-difference signals at the end of the delay by suitable analog circuits. The color-difference signals and the luminance signal are present and processed in analog form as usual.
The problem to be solved by the invention is to modify the principle of the prior art analog circuits in such a way that it can be used in known color-television receivers with digital signal-processing circuitry (cf. "Electronics", Aug. 11, 1981, pages 97 to 103), with the slope detector responding not only to one criterion, namely a predeterminable amplitude threshold value as in the prior art arrangement, but to an additional criterion.
SUMMARY OF THE INVENTION
In accordance with the invention a circuit arrangement provides a fully digital solution for chroma transient improvement. The circuit arrangement contains a slope detector, a memory, a switch-over switch and a timing control stage for the processing of each color difference signal. A time period threshold signal and an amplitude threshold signal are fed to the slope detector. If the amplitude threshold is exceeded and the time threshold is not being reached, the slope is improved.
This circuit arrangement is designed for use in digital color-television receivers or the like and contains for each of the two digital color-difference signals a slope detector to which both a digital signal defining an amplitude threshold value and a digital signal defining a time threshold value are applied. At least one intermediate value occurring during an edge to be steepened is stored, and at the same time value of the steepened edge, it is "inserted" into the latter. This is done by means of memories, switches, output registers, and a sequence controller.
BRIEF DESCRIPTION OF THE DRAWING
The invention will be better understood from a reading of the following detailed description in conjunction with the drawing in which:
FIG. 1 is a block diagram of a first embodiment of the invention;
FIG. 2 is a block diagram of a second form of the arrangement of FIG. 1;
FIG. 3 is a block diagram of an embodiment of the slope detectors of FIGS. 1 and 2;
FIGS. 4a-c shows various waveforms to explain the basic operation of the invention; and
FIGS. 5a and 5b shows waveforms to explain the operation of the improved arrangement of FIG. 2.
DETAILED DESCRIPTION
In the block diagram of FIG. 1, the digital color-difference signals yr, yb are present in the baseband at the frequency of the clock signal f, which is four times the chrominance-subcarrier frequency, i.e., the individual data words appear one after the other at this frequency. If a subharmonic of the clock signal f, i.e., the chrominance-subcarrier frequency itself, for example, is chosen for the color-difference-signal demodulation as may be the case in known digital color-television receivers, these digital signals must be brought to the aforementioned repetition frequency of the clock signal f by digital interpolation.
In FIG. 1, there are two branches for the two color-difference signal yr and yb, respectively. They are of the same design, with the branch z1 assigned to the red-minus-luminance channel, and the branch z2 to the blue-minus-luminance channel. In the branch z1, the red-minus-luminance signal yr is applied to the inputs of the first delay element v1 and the first digital slope detector fs1. The output of the first delay element v1 is fed to the input of the first memory s1 and to one of the inputs of the first switch us1, whereas the output of the first memory s1 is connected to the other input of the first switch us1, whose output is coupled to the input of the first output register r1.
The second branch z2, to which the blue-minus-luminance signals yb are applied, is of the same design as the first branch z1 as far as the individual circuits and their interconnections are concerned, and contains the second digital slope detector fs2, the second delay element v2, the second memory s2, the second switch us2, and the second output register r2.
The output signals of the two slope detectors fs1, fs2 are applied, respectively, to the first and second inputs of the OR gate og, whose output is connected to the first input of the sequence controller ab. The second input of the latter is presented with the clock signal f, and the third input with the digital signal hz, by which the hold time equal to the system rise time of the color-difference channels can be preset. The outputs of the sequence controller ab are connected to the enable inputs en of the first and second memories s1, s2 and of the first and second output registers r1, r2 and to the control inputs of the two switches us1, us2.
The sequence controller ab controls these subcircuits as follows. A red-minus-luminance signal value yr1 and a blue-minus-luminance signal value yb1 occurring at an intermediate value of the hold time are read into the memories s1 and s2, respectively. This intermediate value of the hold time lies preferably in the middle of the hold time. Furthermore, the sequence controller causes the contents of the memories s1 and s2 to be transferred via the associated switches us1 and us2 into the associated output registers r1 and r2, respectively, at the corresponding intermediate value, preferably one-half, of the steepened leading edge, while at all times other than the instant of the intermediate value of the steepened leading edge, the inputs of the associated output registers are connected to the outputs of the delay elements v1 and v2, respectively.
The block diagram of FIG. 2 shows an improved version of the arrangement of FIG. 1. The improvement is that the first and second memories s1 and s2 of FIG. 1 have been supplemented with the third and fourth memories s3 and s4, respectively, each of which is connected in parallel with the associated memory, and that the two switches us1 and us2 of FIG. 1 have been expanded into multiposition switches us1' and us2' each having one additional input connected to the output of the third memory s3 and the output of the fourth memory s4, respectively.
This improved portion of FIG. 2 concerns the sequence controller ab of FIG. 1. In FIG. 2, the latter consists of the counter c2, which counts the pulses of the clock signal s, the decoder dc, and the AND gate u2. The start input st of the counter c2 is connected to the output of the OR gate og, whereas the stop input sp is controlled by the decoder dc. The digital signal hz is fed to the decoder dc, cf. FIG. 1.
The counts of the counter c2 are decoded by reading the red- and blue-minus-luminance signal values occurring at the end of the first third of the hold time, i.e., the values yr1' and yb1', into the first memory s1 and the second memory s2, respectively, and the red- and blue-minus-luminance signal values occurring at the end of the second third of the hold time, i.e., the values yr2 and yb2, into the third memory s3 and the fourth memory s4, respectively. At the end of the first third and second third, respectively, of the steepened leading edge, the contents of the memories s1 and s3, respectively, are transferred through the switch us1' into the output register r1, and at the end of the first third and second third, respectively of that edge, the contents of the memories s2 and s4, respectively, are transferred through the switch us2' into the output register r2. The inputs of the two outputs registers are connected to the outputs of the first and second delay elements v1 and v2, respectively, except at the end of the first and second thirds, respectively, of the steepened leading edge.
The clock signal f is applied to one of the inputs of the AND gate u2, whose other input is connected to one of the outputs of the decoder dc, and whose output is coupled to the enable inputs en of the first and second output registers r1, r2.
The block diagram of FIG. 3 shows a preferred embodiment of the circuit of the slope detectors fs1, fs2. The input for the color-difference signal yr, yb is followed by the series combination of the first digital differentiator d1, the digital absolute-value stage bb, and the minuend input m of the first digital comparator k1. The subtrahend input s of the latter is presented with the digital signal corresponding to the amplitude threshold value, the signal ta.
The absolute-value stage bb delivers digital values which are unsigned, i.e., which have no sign bit, for example.
Accordingly, the absolute-value stage bb contains a subcircuit which changes negative binary numbers in, e.g., one's or two's complement representation into the corresponding positive binary number, i.e., a recomplementer.
The term "comparator" as used herein means a digital circuit which compares the two digital signals appearing at the two inputs to determine which of the two signals is greater. Since, purely formally, such a comparison is closer to the arithmetic operation of subtraction than to that of addition although the concrete internal circuitry of such comparators is more similar to that of adders than to that of subtracters, the two inputs of the comparator are called "minuend input" and "subtrahend input" as in the case of a subtracter. The three logic output signals are "minuend greater than subtrahend", "subtrahend greater than minuend", and "minuend equal to subtrahend". Thus, in positive logic, the more positive logic level will appear at the minuend-greater-than-subtrahend output of a comparator if and as long as the minuend is greater than the subtrahend. If needed, the more negative logic level appearing at this output may serve to signal the "minuend-smaller-than-subtrahend" function, i.e., it is also possible to use negative logic.
In the slope detector of FIG. 3, the enable input eb of the first clock-pulse counter c1 and one of the inputs of the second digital differentiator d2 are connected to the minuend-greater-than-subtrahend output ms of the first comparator k1. The count outputs of the first counter c1 are coupled to the input of the fifth memory s5, which has its output connected to the minuend input m of the second digital comparator k2. The subtrahend input s of the latter is presented with a digital signal corresponding to the time threshold value, the signal tt.
The reset input re of the first counter c1, the enable input en of the fifth memory s5, and the first input of the first AND gate u1 are connected to the output of the second differentiator d2. The subtrahend-greater-than-minuend output sm of the second comparator k2 is connected to the second input of the second AND gate u2, whose output is fed to the OR gate of FIGS. 1 or 2. The subcircuits d1, bb, k1, d2, and, as mentioned above, c1 are clocked by the clock signal f.
FIGS. 4a-c and 5a and b serve to illustrate the operation of the circuit arrangement in accordance with the invention. FIG. 4a shows the assumed shape of one of the two color-difference signals yr, yb; it should be noted that, in those figures, the representation commonly used for analog signals has been chosen for simplicity.
FIG. 4b shows the output signal of the absolute-value stage bb and the amplitude threshold value corresponding to the digital signal ta. Also shown is the time threshold value corresponding to the digital signal tt. FIG. 4c shows the shape of the assumed color-difference signal of FIG. 4a as it appears at the output of the output register r1, r2 of FIG. 1 or FIG. 2. A comparison between FIGS. 4a and 4c shows that the last edge on the right has been steepened since, during this edge, both the amplitude threshold value is exceeded and the time threshold value is not reached (cf. the use of the subtrahend-greater-than-minuend output sm of the second comparator k2), the steepening function becomes effective. The first comparator k1 provides a signal at the minuend-greater-than-subtrahend output ms as long as the output signal of the absolute-value stage bb is greater than the amplitude threshold value. During that time, the first counter c1 can count the clock pulses until it is reset by a signal derived by the second differentiator d2 from the trailing edge of the output signal of the first comparator k1. The previous count of the counter c1 is transferred into the fifth memory s5 and compared with the time threshold value by the second comparator k2. If the time threshold value is greater than the period measured by the counter c1, the above-mentioned function will be initiated.
FIGS. 5a and 5b serve to explain how the steepened edge is formed. Curve a of FIG. 5a shows a slowly rising edge used for the explanation. The distances between the points in curves a and b of FIG. 5a are to illustrate the period of the clock signal f. FIG. 5b shows the waveform at the enable inputs en of the output registers r1, r2. At the arrow shown on the left between curves a and b of FIG. 5a, the signal periodically applied to these inputs at the repetition rate of the clock signal f is stopped, so to speak, so that no signals are transferred to the output registers r1, r2 over several clock periods, but the signal read in at the "clocking" of the enable inputs en is retained in those registers. After the "clocking" of the enable inputs of the output registers r1, r2 has resumed at the beginning of the edge to be steepened, the signal values yr1', yb1' and yr2, yb2 read into the memories s1, s2 and s3, s4 at the end of the first third and the second third, respectively, of the slowly rising edge of curve a of FIG. 5a are transferred into the output registers r1, r2 at the end of the first third and the second third, respectively, of this edge. The arrow shown on the right between curves a and b of FIG. 5a is to indicate that, at the end of the slowly rising edge of curve a, the steepened edge of curve b has reached the desired signal value.
The period for which the "clocking" of the enable inputs en of the output registers r1, r2 is "interrupted" is equal to the duration of the digital signal hz fed to the sequence controller ab of FIG. 1 or to the decoder dc of FIG. 2.
The circuit arrangement in accordance with the invention can be readily implemented in monolithic integrated form. As it uses exclusively digital circuits, it is especially suited for integration using insulated-gate field-effect transistors, i.e., MOS technology.

 

NOTES: 

Article, Electronic, Aug. 11, 1981, "Digital VLSI Breeds Next-Generation TV Receivers", by T. Fischer, pp. 97-103.
Pamphlet by Intermetall Semiconductors ITT, "A New Dimension--VLSI Digital TV System", Publically Available Prior to Filing Date of Subject U.S. patent application of H. G. Lewis, Jr.
Data Sheet from Analogic Corporation, "MP8308, MP8318, Ultrafast 8-Bit Video D/A Converters", copyright 1979. 

Paper "Colour Demodulation of an NTSC Television Signal Using Digital Filtering Techniques" by A. G. Deczky, 1975 IEEE Int'l. Conf. on Comm., vol. II, pp. 23-6 through 23-11.
U.S. patent application filed Aug. 31, 1981 in the name of H. G. Lewis, Jr., Digital Color Television Signal Demodulator, Ser. No.: 297,556.
An Approach to the Implementation of Digital Filters by L. R. Jackson, reprinted from IEEE Trans. Audio Electroacoust., vol. AU-16, pp. 413-421, Sep. 1968.
W. Weltersbach et al., "Digitale Videosignalverarbeitung im Farbfernsehempfanger", Fernseh und Kino-Technik, 35 Jahrgang, Nr. 9, Sep. 1981, pp. 317-323, (with translation).
T. Fischer, "Digital VLSI Breeds Next-Generation TV Receivers", Electronics, Aug. 11, 1981, pp. 97-103.
T. Fischer, "Fernsehen Wird Digital", Elektronik, No. 16, 1981, pp. 27-35, (with translation of pp. 30-31).
ITT Intermetall, A New Dimension-VLSI Digital TV System, Sep. 1981, pp. 1-23.  

Pages 57 through 63 of the ITT "Digit 2000 VLSI Digital TV System" Product Description published by the Intermettal Division of ITT in Sep. 1983. 

E. Lerner, "Digital TV: Makers Bet on VLSI", IEEE Spectrum, 2/83, pp. 39-43.
TRW LSI Product Data Sheet--Model TDC1016J, Monolithic Video D/A Converters, 6/79.
B. Amazeen et al., "Monolithic d-a Converter Operates on Single Supply," Electronics, Feb. 28, 1980, pp. 125-131.  

"Digital VLSI Breeds Next-Generation TV Receivers", Electronics, Aug. 11, 1981, pp. 97-103.
Selected pages from a technical bulletin of the Semiconductor Division of ITT Corporation, titled "Digit 2000 VLSI Digital TV System".

ACVP2205 (Adaptive Combifilter Video Processing)
In a chroma control circuit for a digital television receiver, the system clock lies in the range of four-times the chrominance-subcarrier frequency. The originally received color-burst signal is locked in frequency and phase to the system clock by means of an all-digital phase-locked loop. The phase-difference angle between the color-burst signal and the system clock appears as a sine or cosine value in the two standard color-difference signals of the chrominance demodulator during the reception of the color-burst signal. One of the standard color-difference signals, the B-Y signal, is fed through a horizontal-frequency-suppressing loop filter to a digital oscillator. The latter determines the speed of rotation of a hue adjustment angle rotating at approximately constant angular speed. The respective sine and cosine values of the hue adjustment angle are read as data values from first and second read-only memories, respectively, and are fed to the sine and cosine inputs of a hue adjuster in a calculating stage which derives the color-burst signal and the chrominance signal.The ACVP 2205 is a digital real–time signal processor for multistandard color TV sets based on the DIGIT2000
system. It handles composite video signals as well as
S–VHS signals. For PAL and NTSC a 2H adaptive
combfilter is implemented. It considerably improves the
picture quality by a sophisticated luminance and chrominance
separation. A single silicon chip contains the following
functions:
– selectable 7 or 8 bit video input
– code converter and a data demultiplexer for composite
and S–VHS input signals
– 2H adaptive combfilter for PAL and NTSC composite
video signals
– adjustable horizontal and vertical peaking filter for luminance
– selectable luminance filter for enhanced frequency response
– black–level–expander for improving the picture contrast
and the gamma correction
– contrast multiplier with limiter for the luminance signal
– adjustable chrominance filter
– all color signal processing circuits such as automatic
color control (ACC), color killer, PAL identification, decoder
with PAL compensation, hue correction
– color saturation multiplier with multiplexer for the color
difference signals
– IM bus interface for communication with the CCU 2070
or CCU 3000 Central Control Unit
– circuitry for measuring dark current (CRT spot–cutoff),
white level and photo current, and for transferring this
data to the CCU.
The ACVP 2205 is pin compatible to the PVPU 2204 . It
is designed in N–MOS technology and is available in a
40 pin Dil plastic package.
2. Functional Description
Supplied by one of the DIGIT2000 A/D converters (VCU
2136 or SAD 2140), the ACVP 2205 separates the video
signal into luminance and chrominance. These two signals
are processed in different circuits, which will be described
in the following. The output signals are reconverted
to analog signals in the VCU 2136 or VDU 2146.
Their RGB output amplifiers are used to drive the cathodes
of the CRT (see Fig. 2–4). Additionally, the ACVP
2205 performs a number of measurements and control
operations (in conjunction with the VCU 2136 or VDU
2146)relating to picture tube alignment such as spot–
cutoff current adjustment, white level control, beam current
limiting, etc.
For a multistandard application including SECAM, the
SPU 2243 SECAM Chroma Processor must be connected
in parallel to the ACVP 2205 for chroma processing.
The different processing delays Dt can be equalized
in the DTI 2223.

A comb filter arrangement operating at a reduced data rate is provided, which requires comparably fewer storage locations than previous arrangements. A digitized composite video signal of a given codeword rate is applied to a bandpass filter, which produces a filtered signal restricted to a portion of the passband of the composite video signal. The filtered signal is then subsampled at a rate which satisfies the Nyquist criterion for information of the restricted passband. Codewords, now at a reduced data rate, are applied to a one-H delay line, and delayed and undelayed signals are combined to produce a first comb-filtered signal. The first comb-filtered signal is then applied to an interpolator, which provides a sequence of codewords at the codeword rate of the original digitized composite video signal. This sequence of codewords is then combined with the codewords of the composite video signal to produce a second comb-filtered signal.
This invention relates to signal separation systems and, in particular, to a comb filter arrangement for separating the luminance and chrominance components of a digitized video signal at a reduced data rate.

Conventional television broadcast systems are arranged so that much of the brightness (luminance) information contained in an image is represented by signal frequencies which are concentrated about integer multiples of the horizontal linescanning frequency. Color (chrominance) information is encoded and inserted in a portion of the luminance signal spectrum around frequencies which lie halfway between the multiples of the line scanning frequency (i.e., at odd multiples of one-half theline scanning frequency).

Chrominance and luminance information can be separated by appropriately combing the composite signal spectrum. Known combing arrangements take advantage of the fact that the odd multiple relationship between chrominance signal components andhalf the line scanning frequency causes the chrominance signal components for corresponding image areas on successive lines to be 180.degree. out of phase with each other. Luminance signal components for corresponding image areas on successive linesare substantially in phase with each other.

In a comb filter system, one or more replicas of the composite image-representative signal are produced which are time delayed from each other by at least one line scanning interval (a so-called one-H delay). The signals from one line are addedto signals from a preceding line, resulting in the cancellation of the chrominance components, while reinforcing the luminance components. By subtracting the signals of two successive lines (e.g., by inverting the signals of one line and then combiningthe two), the luminance components are cancelled while the chrominance components are reinforced. Thus, the luminance and chrominance signals may be mutually combed and thereby may be separated advantageously.

The composite video signal may be comb filtered in an analog form, a sampled data form, or a digital form. Comb filters using analog signal glass delay lines for the (approximately) one-H delay lines are commonly employed in PAL-type receiversto separate the red and blue color difference signals, taking advantage of the one-quarter line frequency offset of the interlacing of the two signals. An example of a comb filter system for a sampled data signal is shown in U.S. Pat. No. 4,096,516,in which the delay line comprises a 6821/2 stage charge-coupled device (CCD) delay line which shifts signal samples from stage to stage at a 10.7 MHz rate to achieve a one-H delay. The article "Digital Television Image Enhancement" by John P. Rossi,published in Volume 84 of the Journal of the Society of Motion Picture and Television Engineers (1974) beginning at page 37 shows a digital comb filter in which the one-H delay is provided by a digital storage medium for 682 codewords which is accessedat a 10.7 MHz rate.

In the CCD delay line described in the above-referenced U.S. patent, 6821/2 stages are needed to transfer charge packets related to the analog video signal. But in the digital delay line described in the Rossi article, the video signal is inthe form of eight-bit digital codewords. This arrangement requires the use of eight storage locations for each of the 682 codewords in a horizontal line, or a storage medium for 5,456 bits. Moreover, this delay line is only of sufficient size for asystem in which an NTSC color video signal is sampled at a rate of three times per subcarrier cycle (i.e., using a 10.738635 MHz sampling signal). A frequently discussed sampling frequency for digitizing the analog video signal is 14.3181818 MHz, orfour times the color subcarrier frequency. A one-H digital delay line operating at this frequency requires storage for 910 codewords which, at eight bits per codeword, requires a total of 7280 storage locations. Since a storage medium of this capacityis difficult to fabricate economically, it is desirable to provide a digital comb filter system which requires fewer storage locations.

In accordance with the principles of the present invention, a comb filter arrangement operating at a reduced data rate is provided, which requires comparably fewer storage locations than previous arrangements. A digitized composite video signalof a given codeword rate is applied to a bandpass filter, which produces a filtered signal restricted to a portion of the passband of the composite video signal. The filtered signal is then subsampled at a rate which satisfies the Nyquist criterion forinformation of the restricted passband. Codewords, now at a reduced data rate, are applied to a one-H delay line, and delayed and undelayed signals are combined to produce a first comb-filtered signal. The first comb-filtered signal is then applied toan interpolator, which provides a sequence of codewords at the codeword rate of the original digitized composite video signal. This sequence of codewords is then combined with the codewords of the composite video signal to produce a second comb-filteredsignal.

The invention pertains to a chroma control circuit for a digital television receiver.
A chroma control circuit of this kind is described in an INTERMETALL Data Book entitled "Digit 2000 VLSI Digital TV System", Freiburg/Br., June 1985, pages 163 to 174, which explain the CVPU 2210 NTSC comb-filter video processor. The chroma control circuit according to the aforementioned preambles is contained especially in FIG. 10-2 on page 165, which is described in Section 10.1.4 on page 167 and in Section 10.1.6 on page 168.
In the NTSC and PAL television standards, the hue of a picture element can be represented as an angle-coded signal with respect to a transmitter reference system. The different phase angles from 0° to 360° correspond to hues assigned thereto, the zero reference phase being the zero phase of one of the two standard color-difference signals, namely the B-Y signal. The transmitter reference system is the unmodulated chrominance subcarrier, which is suppressed during the horizontal trace period but is transmitted for a short time as a burst signal during the horizontal retrace period, the phase of the burst signal, referred to the B-Y color-difference signal, being
-180° in the case of the NTSC television standard, and
+/-135° in the case of the PAL television standard.
In the prior art chroma circuit, the receiver reference system is the system clock, which has four times the frequency of, and is locked in frequency and phase to, the unmodulated chrominance subcarrier; four successive system-clock pulses, beginning with the zero phase of the B-Y color-difference signal, correspond to the phase angles of 0°, 90°, 180° and 270° of the unmodulated chrominance subcarrier. The latter, which is included in the composite color signal as mentioned above, is fed to the chroma control circuit after the chrominance and luminance components have been separated from the composite color signal by means of the chrominance filter.
In the NTSC and PAL television standards, the zero reference phase of the receiver reference system is the zero phase of the B-Y color-difference signal during the reception of the color burst. In that case, the R-Y color-difference signal is zero, and the phase comparison in the phase-locked loop is very simple.
If this chroma control circuit is to operate correctly, the chrominance subcarrier and the system clock, which has four times the chrominance-subcarrier frequency, must be locked together in frequency and phase. This is accomplished with a phase-locked loop, which causes the system clock to lock with the unmodulated chrominance subcarrier.
During the further development and improvement of this integrated chroma control circuit, the inventors discovered that the action of the phase-locked loop on the frequency and phase of the system clock is disadvantageous. For example, the phase-locked loop requires a voltage-controlled oscillator for the system clock whose deviation from the reference phase during a line period must not exceed 3°. This corresponds to a permissible deviation of the system-clock frequency of only 0.03 per mill from its nominal value if the phase difference at the beginning of the scanned line is zero. Otherwise, the permissible frequency deviation is even smaller. The necessary frequency stability and control accuracy are thus very high, so that tunable crystal oscillators are used for generating the system clock.
In addition, the data resulting from the phase comparison must be fed to the voltage-controlled oscillator, which is a tunable crystal oscillator forming part of a separate monolithic integrated circuit, so that additional terminals and interconnecting leads are required for both integrated circuits.
Another problem arises if such chroma control circuits are used in television receivers with two or more receiving units which present the information from two or more signal sources or television channels on the screen simultaneously. Each of those receiving units requires a separate clock system whose frequency must be synchronized with the frequency of the respective color-burst signal. With the small differences in the frequencies of the various received color-burst signals, interaction of the associated voltage-controlled oscillators is hardly avoidable, which results in interferences on the screen. The greater the lock-in range of the tunable crystal oscillators, the stronger the interaction will be, because the frequency stability of the oscillators decreases with increasing lock-in range.
SUMMARY OF THE INVENTION
Accordingly, one object of the invention is to improve the prior art chroma control circuit in such a way that the system clock need not be locked to four times the frequency of the originally received chrominance subcarrier, so that it can be locked to other system-related signals, such as a fixed-frequency signal, and that the phase-locked loop is an all-digital circuit.
The fundamental idea of the invention is to achieve the correct adjustment of the frequency and phase between the system clock, which forms the receiver reference system, and the color-burst signal not by locking the system clock to four times the frequency and four times the phase of the color-burst signal by means of a voltage-controlled oscillator, i.e., by analog means, as has been done so far, but by leaving the frequency and phase of the system clock unchanged and taking the necessary locking measures on the received color-burst and chrominance signals. The phase of the digitalized burst signal is, therefore, rotated with respect to the zero phase of the receiver reference system purely digitally by means of a phase-locked loop until it is -180° or +/-135° in accordance with the NTSC or PAL television standard, respectively; at the same time, frequency equality is established between the rotated burst signal and the system clock. The necessary correction angle is then applied to the chrominance signal too. In case of large frequency differences between the original received color-burst signal and the system clock, the correction of the chrominance signals during the scanning line must be interpolated.
A special advantage of the invention that one or more chroma control circuits in accordance with the invention can be added to the prior art chroma control circuit to produce a television receiver for multipicture reproduction that has only a single system clock for all receiving systems.
Another important advantage is that the system clock can be synchronized with signals which are locked to the horizontal frequency or a multiple thereof. This offers advantages during operation of a video recorder and in signal processing for picture enhancement as is performed, for example, to obtain a flicker-free television picture.
Finally, the necessary interpolation of the chroma correction during the scanning line is achieved by the invention in an advantageous manner even in case of large frequency differences between the originally received color-burst signal and the system clock.

CCU 3000, CCU 3000-I Main System Processor
CCU 3001, CCU 3001-I
MICRONAS INTERMETALL

1. Introduction
The CCU 3000, CCU 3000-I, CCU 3001, CCU 3001-I
are integrated circuits designed in 1.2 mm CMOS
technology, with the exception of CCU 3000, TC18 and
TC19, which is designed in 1 mm CMOS technology. The
CPU contained on the chips is a functionally unchanged
65C02-core, which means that for program development,
systems can be used which are on the market; including
high level language compilers.
The pin numbers mentioned in this data sheet refer to
the 68-pin PLCC package unless otherwise designated.
The CCU 3000-I is described separately in an addendum
on page 66.
1.1. Features of the CCU 3000, CCU 3000-I,
CCU 3001, CCU 3001-I
– CCU 3000 = ROM-less version of the CCU 3001
– 65C02 CPU with max. 8 MHz clock
– 32 kByte internal ROM (CCU 3001 only)
– 1344 internal Bytes RAM with stand-by option
– 51 I/O lines (CCU 3001)
– 26 I/O lines (CCU 3000)
– clock generator with programmable clock frequency
– 8 level interrupt controller
– CCU 3000, CCU 3001:
2 Multimaster IM bus interfaces
– CCU 3000-I, CCU 3001-I: 1I2C/IM bus and
1 Multimaster IM bus interface (see addendum)
– IR-input for software-decoded IR-systems
– on-chip power on, stand-by and clock supervision
logic
– on-chip watchdog
– 3 multifunctional timers
– supports memory banking (external 2MBytes)
– power down signal for external memory
– mask option: EMU mode
– programs can be written in Assembler or in “C”
– CCU 3000 TC 18/19: 1.0 mm CMOS technology, (see
addendum)
– application software available.

Functional Description
2.1. ROM
The chip is equipped with 32 kByte mask-programmable
ROM. The ROM uses up the address space from 8000H
to FFFFH. This ROM can be supplemented or replaced
externally. Only the CCU 3001 has an internal ROM.
2.2. RAM
The RAM area is split into three parts:
– page 0 (address 0 to FFH)
– page 1 (address 100H to 1FFH)
– page 3, 4, 5, 6 (address 300H to 63FH)
Page 0 offers a particularly fast access to the 65C02 and
is therefore very valuable for fast, compact programs.
Page 1 contains the stack and must therefore also have
RAM. The remaining RAM-memory follows in pages 3,
4, 5, 6, as page 2 is reserved as I/O address space. The
RAM can be kept in the stand-by mode via stand-by pin.
2.3. CPU
The CPU core is fully compatible with the 65C02 microprocessor.
However, not all the pins of the 65C02 processor
are accessible for the user outside the chip. One
switch in the control register allows the CPU to be
switched off, so that an external processor can take over
its tasks. This external processor can of course also be
an in-circuit emulator, which makes near-hardware
emulation possible, even though the status and control
lines of the internal CPU are not accessible. If an external
processor is used, all hardware blocks of the chip are
as accessible to it as if it were the internal CPU.
2.4. Clock Generator
An integrated two-pin oscillator generates the clock for
the microcontroller. The frequency created by the oscillator
can be programmed to be reduced with a divider
by the factor 1 ... 255. This enables the user to decrease
the current consumption by the controller by reducing
the working frequency as well as to increase the access
time for the (slower) external memory. This divider contains
the value 4 after a reset, so that the system can also
start with a slow external memory. If the mask-option
OSC is set (EMU version), a switch in the control register
makes it possible to receive the internal clock F2 at
XTAL2. In this case the oscillator must be external and
the clock must be fed to the pin XTAL1. In this way, the
user gets a time reference for internal operations in the
microcomputer. This is especially important with the interrupt
controller. The production version of the CCU
does not have this function!
2.5. PORT 1 to PORT 3, PORT 6 to PORT 8
8 ports belong to the system, of which 5 are 8 bits wide,
one 6 bit, one 4 bit and one 1 bit wide. All port lines of
PORTS 1 to 3 and 6 to 8 can be used as inputs or outputs
independently from each other. One register per port
defines the direction. PORT1 to PORT3 have push-pull
outputs and PORT6 to PORT8 have open drain outputs.
Even a line defined as output can be read, the pin level
being important. This property makes it possible for the
software to find desired and undesired short circuits.
Each port reserves a byte for the direction register and
the data in the I/O page. If the corresponding bit in the
direction register is set to 0, the output mode is switched
on. After a reset, all bits of a direction register are set
to 1. The falling edge of bit 7 of PORT 8 generates interrupts
if the priority of the corresponding interrupt controller
source (7) is not set to 0.
2.6. PORT 4
PORT 4 consists of only one line (LSB, P40). After a reset,
PORT 4 operates as an input only. As soon as PORT
4 is written for the first time, it is switched to output mode
(push-pull). Later read accesses read the actual level at
port 4. If bit 3 in the control word is active, P4 is used as
an R/W-line. If the internal CPU is active, R/W is an output
line, otherwise it is an input. But P4 has another, very
important function during RESET. The level at P4 during
RESET decides whether the control word is read from
the internal ROM (FFF9H) or from the external memory.
It is therefore important that the desired level during RESET
is set at P4. An internal pull-down resistor of approx.
100 kW is integrated in the CCU 3001, which ensures
that the control word is read by the internal ROM. The
external control word access is obtained via an external
pull-up resistor of approx. 5 kW. The CCU 3000 has an
internal pull-up resistor at P4 (external ROM access).
The further mode of operation of the CCU 3000, CCU
3001 depends only on the control word though.
Please note that this mode is always necessary for
the CCU 3000 since this device does not have internal
ROM!
2.7. I/O-Lines P50 to P55
The 6 additional I/O-lines have a two-fold function:
– input or output line (open drain output) or
– fully decoded I/O-select lines (push-pull outputs)
As a rule these lines can be used as input or output lines.
As soon as ports 1 to 4 are used as system bus, they are
lost as I/O-channels. However, a total of 48 port lines (24
inputs and outputs each) can be reconstructed without
difficulties (1 housing for 8 lines), if the additional 6 I/Olines
of the CCU 3000, CCU 3001 are switched into the
port select mode. They then represent the select lines of
the original ports 1 to 3. Each line can be defined as I/O
or port select line separately. In the I/O-page three bytes
are needed. 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 DPU 2553, DPU 2554 Deflection Processors UNIT

Note: lf not otherwise designated, the pin numbers mentioned refer to the 40-pin Dil package.

1. Introduction
These programmable VLSI circuits in n-channel mOS technology carry out the deflection functions in digital color TV receivers based on the DiGiT 2000 system and are also suitable for text and D2~mAC application. The three types are basically identical, but are modified ac- cording to the intended application:

DPU 2553
normal-scan horizontal deflection, standard CTV receivers, also equipped with Teletext and D2-mAC facility

DPU 2554
double-scan horizontal deflection, for CTV receivers equipped with double-frequency horizontal deflection and double-~frequency vertical deflection for improved picture quality. At power-up, this version starts with double horizontal frequency.

1.1. General Description
The DPU 2553/54 Deflection Processors contain the fol- lowing circuit functions on one single silicon chip:
- video clamping
- horizontal and vertical sync separation
~ horizontal synchronization
- normal horizontal deflection
-east-west correction, also for flat-screen picture tubes
- vertical synchronization
- normal vertical deflection
~ sawtooth generation
-text display mode with increased deflection frequencies (18.7 kHz horizontal and 60 Hz vertical)
- D2-mAC operation mode and for DPU 2554 only:
- double-scan horizontal deflection
- normal and double-scan vertical deflection

ln this data sheet, all information given for double~scan mode is available with the DPU 2554 only. Type DPU 2553 starts the horizontal deflection with 15.5 kHz ac- cording to the normal TV standard, whereas type DPU 2554 starts with 31 kHz according to the double-scan system.

The following characteristics are programmable:
~ selection of the TV standard (PAL, D2-mAC or NTSC)
- selection of the deflection standard (Teletext, horizontal and vertical double-scan, and normal scan)
- filter time»constant for horizontal synchronization
- vertical amplitude, S correction, and vertical position for in-line, flat-screen and Trinitron picture tubes
- east-west parabola, horizontal width, and trapezoidal correction for in-line, flat-screen and Trinitron picture tubes
- switchover characteristics between the different synchronization modes
~characteristic of the synchronism detector for PLL switching and muting

1.2. Environment
Fig. 1-1 shows the simplified block diagram of the video and deflection section of a digital TV receiver based on the DIGIT 2000 system. The analog video signal derived from the video detector is digitized in the VCU 2133, VCU 2134 or VCU 2136 Video Codec and supplied in a parallel 7 bit Gray code. This digital video signal is fed to the video section (PVPU, CVPU, SPU and DmA) and to the DPU 2553/54 Deflection Processor which carries out all functions required in conjunction with deflection, from sync separation to the control of the deflection power stages, as described in this data sheet.

3. Functional Description
3.1. Block Diagram
The DPU 2553 and DPU 2554 Deflection Processors perform all tasks associated with deflection in TV sets;
- sync separation
- generation and synchronization of the horizontal and the vertical deflection frequencies
-the various east OWest corrections

- vertical savvtooth generation including S correction as described hereafter. The DPU communicates, via the
bidirectional serial lm bus, with the CCU 2050 or CCU 2070 Central Control Unit and, via this bus, is supplied with the picture-correction alignment information stored in the mDA 2062 EEPROM during set production, When the set is turned on. The DPU is normally clocked with a trapezoidal 17.734 mHz (PAL or SECAM), or 14.3 mhz (NTSC) or 20.25 mHz (D2-mAC) clock signal supplied by the mCU 2600 or mCU 2632 Clock Generator IC.
 
The functional diagram of the DPU is shown in Fig. 3-1.
3.2. The Video Clamping Circuit and the Sync Pulse

Separation Circuit
The digitized composite video signal delivered as a 7»bit parallel signal by the VCU 2133, VCU 2134 or VCU 2136 Video Codec is first noise-filtered by a 1 mHz digital lovv- pass filter and, to improve the noise immunity of the clamping circuit, is additionally filtered by a 0.2 mHz low - pass filter before being routed to the minimum and back porch level detectors (Fig. 3-3).

The DPU has two different clamping outputs, no. 1 and
No. 2, one of which supplies the required clamping
pulses to the video input of the VCU as shown in Fig.
3-1.

The following values for the clamping circuit apply for Video Amp. l. since the gain of Video Amp. ll is twice th at of Video Amp l, all clamping and signal levels of Video Amp ll are halt those of Video Amp l referred to +5 V. After the TV set is switched on,the video clamping circuit first of all ensures by means of horizontal-frequency current pulses from the clamping output of the DPU to the coupling capacitor of the analog composite video signal, that the video signal at the VCU’s input is optimally biased for the operation range of the A/D converter of 5 to 7 V. For this, the sync top level is digitally measured and set to a constant level of 5.125 V by these current pulses. The horizontal and vertical sync pulses are now separated by a fixed separation level of 5.250 V so that the horizontal synchronization can lock to the correct phase (see section 3.3. and Figs. 3-2 and 3-3). with the color key pulse which is now present in synchronism with the composite video signal, the video clamping circuit measures the DC voltage level of the porch and by means of the pulses from pin 21 (or pin4), sets the DC level ofthe porch at a constant 5.5 V (5.25 V for Video Amp ll). This level is also the reference black to Video Processor teletext Processor, D2-MAC Processor tc.

level for the PVPU 2204 or PVPU 2270 Video Processors. When horizontal synchronization is achieved, the slice level for the sync pulses is set to 50 % of the sync pulse amplitude by averaging sync top and black level. This ensures optimum pulse separation, even with small sync pulse amplitudes (see application notes, section 4).

3.3. Horizontal Synchronization
Two operating modes are provided for in horizontal synchronization. The choice of mode depends on whether or not the Tv station is transmitting a standard PAL or NTSC signal, in which there is a fixed ratio between color sub carrier frequency and horizontal frequency. ln the first case we speak of “color-locked” operation and in the second case of “non-color-locked” operation (e.g. black-and-white programs). Switching between the two modes is performed automatically by the standard signal detector.

3.3.1. Non-Color-Locked Operation
ln the non»locked mode,which is needed in the situation where there is no standard fixed ratio between the color sub carrier frequency and the horizontal frequency of the transmitter, the horizontal frequency is produced by sub sampling the clock frequency (1 7.7 mHz for PAL and SECAM, 14.3 mHz for NTSC) in the programmable frequency divider (Fig. 3-4) until the correct horizontal frequency is obtained. The correct adjustment of frequency and phase is ensured by phase comparator l. This determines the frequency and phase deviation by means of a digital phase comparison between the separated horizontal sync pulses and the output signal of the programmable divider and corrects the divider accordingly. For optimum adjustment of phase jitter, capture behavior and transient response of the horizontal PLL circuit, the measured phase deviation is filtered in a digital low pass filter (PLL phase filter). ln the case of non - horizontal  synchronized horizontal PLL, this filter is set to wide band PLL response with a pull-in range of 1800 Hz. if the -  sync sync PLL circuit is locked, the PLL filter is automatically switched to narrow-band response by an internal synchronism detector in order to limit the phase jitter to a minimum, even in the case of weak and noisy signals. A calculator circuit in phase comparator , which analyzes the edges of the horizontal sync pulses, increases the resolution of the phase measurement from 56 ns at

Fig. 3-3: Principle of video clamping and pulse separated 17.7 mHz clock frequency to approx. 6 ns, or from 70 ns NON at 14.3 MHz clock frequency to approx. 2.2 ns.

The various key and gating pulses such as the color key pulse (tKe(,), the normal-scan (1 H) and double-scan (2H) horizontal blanking pulse (tAZ(/) and the 1 H horizontal un delayed gating pulse (t/(Z) are derived from the output signals of the programmable divider and an additional counter for the 2H signals and the 1 H and 2H skew data output. These pulses retain a fixed phase position with respect to the 1 H input video signal and the double- scan output video signal from the pvPU 2270 Video Processor For the purpose of equalizing phase changes in the horizontal output stage due to switching response tolerances or video influence, a second phase control loop is used which generates the horizontal output pulse at pin 31 to drive the horizontal output stage. ln phase comparator li (Fig. 3~4), the phase difference between the output signal of the programmable divider and the leading edge (or the center) of the horizontal fly back pulse (pin 23) is measured by means of a balanced gate delay line. The deviation from the desired phase difference is used as an input to an adder. ln this, the information on the horizontal frequency derived from phase comparator l is added to the phase deviation originating form phase comparator ll. The result of this addition controls a digital on-chip sine wave generator (about 1 mHz) which acts as a phase shifter with a phase resolution of 1/128 of one main clock period <f> m _ By means of control loop ll the horizontal output pulse (pin 31) is shifted such that the horizontal fly back pulse (pin 23) acquires the desired phase position with respect to the output signal of the programmable divider which, in turn, due to phase comparator l, retains a fixed phase position with respect to the video signal. The horizontal output pulse itself is generated by dividing the frequency of the 1 mHz sine wave oscillator by a fixed ratio of 64 in the case of normal scan and of 32 in the case of double- scan operation.

3.3.2. Color-Locked Operation
When in the color~locked operating mode, after the phase position has been set in the non-color-locked mode, the programmable divider is set to the standard dimension ratio (1135:1 for PAL, 91O:1 for NTSC) and phase comparator  is disconnected so that interfering pulses and noise cannot influence the horizontal deflection. Because phase comparator ll is still connected, phase errors oft he horizontal output stage are also corrected in the color » locked operating mode. The standard signal detector is so designed that it only switches to color-locked operation when the ratio between color sub carrier frequency and horizontal frequency deviates no more than 1O'7 from the standard dimension ratio. To ascertain this requires about 8 s (NTSC). Switching off color-locked operation takes place automatically, in the _ case of a change of program for example, within approximately 67 ms (e.g. two NTSC fields, 60 Hz).


3.3.3. Skew Data Output and Field Number Information with non-standard input signals, the TPU 2735 or TPU 2740 Teletext Processor produce a phase error with respect to the deflection phase. The DPU generates a digital data stream (skew data, pin 7 of the DPU), which informs the PSP and TPU on the amount of phase delay (given in 2.2 ns increments) used in the DPU for the 1H and 2h output pulse compared With the Fm main clock signal of 17.7 mHz (PAL or SECAM) or 14.3 mhz (NTSC), see also Figs. 3-6 to 3-8. The skew data is used by the PSP and by the TPU to adjust the double-scan video signal to the 1 H and 2H phase of the horizontal deflection to correct these phase errors. For  the vmC processor the skew data contains three additional bits for information about frame number, 1 V sync and 2 V sync start.

3.3.4. Synchronism Detector for PLL and Muting
Signal
To evaluate locking ofthe horizontal PLL and condition of the signal, the DPU’s HSP high-speed processor (Fig. 3~1) receives two items of information from the horizontal PLL circuit (see Fig. 3-11). a) the overall pulse width of the separated sync pulses during a 6.7 us phase window centered to the horizontal sync pulse (value A in Fig. 3-11). b) the overall pulse width of the separated sync pulse during one horizontal line but outside the phase window (value B in Fig. 3-11). Based on a) and b) and using the selectable coefficients KS1 and KS2 and a digital low /pass filter, the HSP processor evaluates an 8-bit item of information “SD” (see Fig. 3-12). By means of a comparator and a selectable level SLP, the switching threshold for the PLL signal “UN” is generated. UN indicates Whether the PLL is in the synchronous or in the asynchronous state. To produce a muting signal in the CCU, the data SD can be read by the CCU. The range ot SD extends from O (asynchronous) to +127 (synchronous). Typical values for the comparator levels and their hysteresis B1 = 30/20 and for muting 40/30 (see also HSP Bam address Table 5-6).

DPU 2553, DPU 2554

3.4. Start Oscillator and Protection Circuit To protect the horizontal output stage of the TV set during changing the standard and for using the DPU as a low power start oscillator, an additional oscillator is provided on-chip (Fig. 3-4), with the output connected to pin 31. This oscillator is controlled by a 4 mHz signaling dependent from the Fm main clock produced by the MCU 2600 or mCU 2632 Clock Generator IC and is powered by a separate supply connected to pin 35. The function of this circuitry depends on the external standard selection input pin 33 and on the start oscillator select input pin 36, as described in Table 3-3. Using the protection circuit as a start oscillator, the following operation modes are available (see Table 3-3). With pin 33 open-circuit, pin 36 at high potential (connected to pin 35) and a 4 mHz clock applied to pin 34, the protection circuit acts as a start oscillator. This produces a constant-frequency horizontal output pulse of 15.5 kHz in the case of DPU 2553, and of 31 khz in the case of DPU 2554 while the Beset input pin 5 is at low potential. The pulse width is 30 us with DPU 2553, and 16 us with DPU 2554. main clock at pin 2 or main power supplies at pins 8, 32 and 40 are not required for this start oscillator After the main power supply is stabilized and the main clock generator has started, the reset input pin 5 must be switched to the high state. As long as the start values from the CCU are invalid, the start oscillator will continuously supply the output pulses of constant frequency to pin 31 _ By means of the start values given by the CCU via the lm bus, the register FL must be set to zero to enable the start oscillator to be triggered by the horizontal PLL circuit. After that, the output frequency and phase are controlled by the horizontal PLL only. It the external standard selection input pin 33 is connected to ground or to +5 V, the start oscillator is switched off as soon as it ls in phase with PLL circuit. Pin 33 to ground selects PAL or SECAM standard (17.7 mHz main clock), and pin 33 to +5 V selects NTSC standard (14.3 MHz main clock). After the main power supplies to pins 8, 32 and 40 are stabilized, the start oscillator can be used as a separate horizontal oscillator with a constant frequency of 15.525 khz. For this option, pin 33 must be unconnected. By means of the lm bus register SC the start oscillator can be switched on (SC = 0) or oft (SC = 1). Setting SC =1 is recommended. By means of pin 29 (horizontal output polarity selecting - input and start oscillator pulse width select input), the out- put pulse width and polarity of the start oscillator and protection circuit can be hardware-selected. Pin 29 at low potential gives 30 us for DPU 2553 and 16 us for DPU 2554,with positive output pulses. Pin 29 at high potential gives 36 us for DPU 2553 and 18 its for DPU 2554, with negative output pulses. Both apply for the time period in which no start values are valid from the CCU. If pin 29 is intended to be in the high state, it must be connected to pin 35 (standby power). Pin 29 must be connected to ground or to +5 V in both cases. Table 3-3: Operation modes of the start oscillator and protection circuit Operation Mode Pins 33 34 35 36 Horizontal output stage protected not connected 4 mHz Clock at +5 V at ground during main clock frequency changing (for PAL and NTSC) Horizontal output stage protected not connected 4 MHz Clock +5 V with connected to and start oscillator function start oscillator pin 35 (for PAL and NTSC) tor supply Only start oscillator function with at +5 V 4 mHz Clock +5 V with connected to NTSC standard after Beset start oscillator pin 35 tor supply Only start oscillator function with at ground 4 mHz Clock +5 V with connected to PAL or SECAM standard after Beset start oscillating pin 35 5 tor supply _ with 17.7 mHz clock at ground at ground at +5 V at ground without protection.


3.5. Blanking and Color Key Pulses

Pin 19 supplies a combination of the color key pulse and the un delayed horizontal blanking pulse in the form of a three-level pulse as shown in Fig. 3-13. The high level (4 V min.) and the low level (0.4 V max.) are controlled by the DPU. During the low time of the un delayed horizontal blanking pulse, pin 19 of the DPU i sin the high-- impedance mode and the output level at pin 19 is set to 2.8 V by the VCU. At pin 22, the delayed horizontal blanking pulse in combination with the vertical blanking pulse is available as a three-level pulse as shown in Fig. 3-13. Output pin 22 is in high-impedance mode during the delayed horizontal blanking pulse. ln double-scan operation mode (DPU 2554), pin 22 sup- plies the double-scan (2H) horizontal blanking pulse in- stead of the 1H blanking pulse (DPU 2553). ln text display mode with increased deflection frequencies (see section 1.), pin 22 of the respective DPU (DPU 2553, as defined by register ZN) delivers the horizontal blanking pulse with 18.7 kHz and the vertical blanking pulse with 60 Hz according to the display. At pin 24 the un delayed horizontal blanking pulse is output. normally, pin3  supplies the same vertical blanking pulse as pin 22. However, with“DVS” = 1, pin 3 will be in the single-scan mode also with double-scan operation of the system. The pulse width of the single-scan vertical blanking pulse at pin 3 will be the same as.that of the double-scan vertical blanking pulse at pin 22. The out- put pulse of pin 3 is only valid if the COU register “VBE” is set to 1 . The default value is set to 0 (high-impedance state of pin 3). Fig. 3-13: Shape of the output pulses at pins 19 and 22 *) The output level is externally defined 3.6. Output for Switching the Horizontal Power Stage Between 15.6 kHz (PAL/NTSC) and 18 kHz (Text Display) This output (pin 37) is designed as a tristate output. High levels (4 V mln.) and low levels (0.4 V max.) are con- trolled by the DPU. During high-impedance state an external resistor network defines the output level, For changing the horizontal frequency from 15 kHz to 18 kHz, the following sequence of output levels is derived at pin 37 (see Fig. 3-14). After register ZN is set from ZN = 2 (15 kHz) to ZN = 0 (18 kHz) by the CCU, pin 37 is switched from High level to high-impedance state synchronously with the frequency change at pin 31. Following a delay of 20ms, pin 37 is set to Low level and remains in this state for the time the horizontal frequency remains 18 kHz (with ZN == 0). This 20 ms delay is required for switching - over the horizontal power stage. To change the horizontal frequency in the opposite direction, from 18 kHz to 15.6 kHz, the sequence described is reversed.

3.7. Text Display Mode with Increased Deflection Frequencies
As already mentioned, the DPU 2553 provides the feature of increased deflection frequencies for text display for improved picture quality in this mode of operation. To achieve this, the processor acting as deflection processor has its register Zn set to 0. The horizontal output frequency at pin 31 is then switched to a frequency of 18746.802 Hz which is generated by dividing the Fm main clock frequency by 946 i 46. The horizontal PLL is then able to synchronize to an external composite sync signal of fH = 18.746 kHz
46. The horizontal PLL is then able to synchronize to an external composite sync signal of fH = 18.746 kHzi 5 % and f\, = 60 Hz i 10 % and can be set to an independent horizontal and vertical sync generator by setting register VE = 1 and register VB = 0. That means a constant divider of 946 for horizontal frequency and constant 312 lines per frame. The DPU working in this mode supplies the TPU 2740 Teletext Processor or the respective View data Processor with the 18.7 kHz horizontal blanking pulses form pin 24 and the 60 Hz vertical blanking pulses form pin 22 (see Fig. 3-8). To be able to receive and store data from an IF video signal at the same time, the Teletext or View data Processor requires horizontal and vertical sync pulses from this IF signal. Therefore, the second DPU provides video clamping and sync separation for the external signal and supplies the horizontal sync pulses (pin 24) and the vertical sync pulses (pin 22) to the Teletext or view data Processor. For this, the second DPU is set to the PAL standard by register ZN = 2, and the clamping pulses of the other DPU are disabled by CLD = 1. To change the output frequency of the DPU acting as deflection processor from 18.7 kHz to 15.6 kHz, the control switch output pin 37 prepares the horizontal output stage for 15.6 khz operation (pin 37 is in the high -impedance state) before the DPU changes the horizontal out- put frequency  to 15.6 kHz, after a minimum delay of one vertical period. Switching the horizontal deflection frequency from 15.6 kHz to 18.7 kHz is done in the reverse sequence. Firstly, the horizontal output frequency of pin 31 is switched to 1 8.7 khz, and after a delay of one vertical period, pin 37 is set low. 3.8. D2-MAC Operation Mode When receiving Tv signals having the D2-mAC standard (direct satellite reception), register ZN is set to 3. The programmable divider is set to a dimension ratio of 1296 i 48 to generate a horizontal frequency of 15.625 khz with the clock rate of 20.25 mHz used in the D2-mAC standard. ln this operation mode, pin 6 acts as input for the composite sync signal supplied by the DmA 2271 D2-mAC Decoder. The DPU is synchronized to this sync signal, and after locking-in (status register UN = 0), the CCU switches the DPU to a clock-locked mode between clock signal and horizontal frequency (f<pM/fH = 1296). ln  D2-mAC operation mode (ZN = 3), the clamping pulse outputs (pins 4 and 21) are set to the high- impedance state by the CCU (with CLD = 1) to enable the video clamping function of the DMA 2270 at the same pin of the vCU. Further, pin 24 must be set to the high- impedance state by means of register “UHD”, because the DmA 2271 uses this pin. 3.8.1. Vertical Synchronization The vertical sync pulse is derived by means of digital integration from the separated composite sync signal (Fig. 3-15). Then, the trigger pulse for the high-speed processor and the vertical deflection is produced in the working counter which divides the double horizontal frequency (31 kHz) by (625 i64) for PAL and SECAM, and by (525 i64) for NTSC. The working counter can be set to three different operating modes (see Fig. 3-16): 1. Non-locked operation using a wide trigger window. The working counter can be reset by the vertical sync pulse at a counter position of 561 to 689 (for PAL and SECAM) or of 461 to 589 (for NTSC), which means that it can be synchronized by vertical frequencies in the range from 45 to 55 Hz for PAL and SECAM or 54 to 66 Hz for NTSC. 2. Non-locked operation using a narrow trigger window In this mode, the working counter reset range is restricted to between 618 to 632 for PAL and SECAM or 51 8 to 532 for NTSC. This ensures that improved noise immunity is also obtained with non-standard signals or in the case of video recorder operation. 3. Locked operation. ln this mode, the standard dimension ratio, e.g. 625 : 1 for PAL and SECAM or 525 : 1 for NTSC, is fixed. This ensures optimum noise immunity for all standard signals. The three operating modes described are defined by the following test circuitry. A standard signal detector, com- prising measuring counter, measuring window, coincidence detector and frequency detector, checks whether the ratio of the vertical frequency received to double the horizontal frequency is in accordance with the specified standard. For this purpose, the measuring counter which can be triggered first of all by the vertical sync pulses supplied by the transmitter in the counter range of 625 i64 for NTSC, is used to produce a constant measuring window representing the counts 620 to 630 (PAL and SECAM) or 520 to 530 (NTSC). A subsequent up/down counter establishes whether five consecutive sync pulses appear in the measuring window. If this rough coincidence test has a positive result, the measuring counter is set to the standard divider ratio, and the frequency detector starts to count the vertical sync pulses lying inside the measuring window. When the count reaches 64 (in about 1.3 s for PAL and SECAM or about 1.7 s for NTSC), the frequency detector signals that locking is present between horizontal frequency and vertical frequency. Following this, the working counter is then also set to the standard dimension ratio. The switch-on delay for the locked operation can be ex- tended to 128 (corresponding to about 2.5 s for PAL and SECAM or3.3 s for NTSC) by means of the CCU register “FF”. The time needed for canceling the locked mode, in the case of a program change for example, is defined by the maximum counter reading of the up/down counter which can be selected. This counter counts down the sync pulses which do not appear in the measuring window. in the case of a reading of less than 2, the measuring counter is switched back to window operation and the frequency detector is reset to “0”. The switch~off delay can be selected in four steps (from 80 to 320 ms for PAL and SECAM or from 67 to 270 ms for NTSC) by means of the CCU register “CiH”. With the aid of a further measuring window of 625 i5 for PAL and SECAM or 525 i5 for NTSC, which is derived from the working counter, a phase test circuit is used, synchronously with the frequency detector, to as certain whether more than 128 consecutive sync pulses are found within the phase window of the synchronized working counter. It there have been, and the standard test has not yet resulted in locking of the vertical synchronization, the working counter is switched to the narrow window. lf the phase positions of the measuring counter and the working counter do not coincide, then the working counter is set to the phase position of the measuring counter if the sync pulse does not appear more than tour times in succession in the measuring window of the working counter. This is done without directly influencing the other test circuitry. To achieve additional noise suppression, the vertical sync pulse passes through a gating circuit derived from the measuring counter which corresponds to a count of 561 to 689 for PAL and SECAM or 461 to 589 for NTSC. ln order to ensure vertical synchronization even when the vertical sync pulses in the composite sync signal are suppressed (in the case of reflections for example), all the test results remain unchanged if no vertical sync pulse from the transmitter is received during the entire vertical cycle, i.e. a locked operating mode, once switched on, is retained. The vertical frequency fv is evaluated in the HSP high speed processor by counting the cycles of the HSP calculation clock, which is derived by dividing the <I>m main clock by 1024, during the vertical sync signal separated from the received video signal. To use an 8-bit register, the result of the count is divided by 2 and given to the DPU status register. ln the CCU, the vertical frequency can be evaluated using the following equation:
fv I __lL1’_l\
1024- vP- 2
with
fm), = 17.734475 mHz with PAL and SECAM
fq,M =14.31818 mHz with NTSC
rw = 2o_25 MHZ with D2-mAc
VP = status value, read from DPU.

The interlace control output pin 39 supplies a 25 Hz (for PAL and SECAM) or 80 Hz (for NTSC) signal for control- ling an external interlace-off switch, which is required with A.C.-coupled vertical output stages, because  these are not able to handle the internal interlace-off procedure using register “ZS”. For operation with the vmC Processor the DPU 2554 has three interlace control modes in double vertical scan mode (DVS = 1). These options can be selected with the register “IOP” and can be used together with the control output pin 39 only. This output has to be connected to the vertical output stage, so that the vertical phase can be shifted by 16 us (or 32 us with DPU 2553).

 

 

 

 TEA6415C Bus-Controlled Video Matrix Switch
Main Features
20 MHz Bandwidth
Cascadable with another TEA6415C (Internal
Address can be changed by Pin 7 Voltage)
8 Inputs (CVBS, RGB, Chroma, ...)
6 Outputs
Possibility of Chroma Signal for each Input
by switching off the Clamp with an external
Resistor Bridge
Bus Controlled
6.5 dB Gain between any Input and Output
-55 dB Crosstalk at 5 MHz
Full ESD Protection

Description
The main function of the TEA6415C is to switch 8
video input sources on the 6 outputs.
Each output can be switched to only one of the
inputs, whereas any single input may be connected
to several outputs.
All switching possibilities are controlled through the
I2C bus.

Driving a 75 W load requires an external transistor.
The switches configuration is defined by words of 16 bits: one word of 16 bits for each output
channel.
So, 6 words of 16 bits are necessary to determine the starting configuration upon power-on (power supply: 0 to 10V). But a new configuration needs only the words of the changed output channels.

Using a Second TEA6415C
The programming input pin (PROG) allows two TEA6415C circuits to operate in parallel and to select them independently through the I²C bus by modifying the address byte. Consequently, the switching capabilities are doubled, or IC1 and IC2 can be cascaded.



TEA6420 BUS-CONTROLLED AUDIO MATRIX SWITCH


5 Stereo Inputs
4 Stereo Ouputs
Gain Control 0/2/4/6dB/Mute for each Output cascadable (2 different addresses) Serial Bus Controlled Very low Noise
Very low Distorsion
DESCRIPTION The TEA6420 switches 5 stereo audio inputs on 4stereo outputs. All the switching possibilities are changed through the I2C bus.  

 

LOEWE ARCADA 72-100 PIP (53471L39)  CHASSIS Q2100  (110Q21) Display device using scan velocity modulation:

To improve pictures to be displayed on a display screen of a display device, it is known to use scan velocity modulation. In scan velocity modulation the (horizontal) deflection rate of the electron beam(s) is modulated with the luminance component of the video signal. As a result of scan velocity modulation, the information of the video signal will no longer be displayed at the correct position on the display screen. By using the modulation signal applied to the scan velocity modulator also for modulating the (read) clock rate of the video signal from the memory, it can be ensured that the video signal and the (modulated) deflection signal are always in synchronism with each other.

  1. A display device for displaying a video signal on a display screen of a display tube comprising at least one control electrode and deflection coils for deflecting at least one electron beam current, said display device further having an input for receiving the video signal, means for determining a derivative of a luminance component of the video signal, a scan velocity modulator for modulating the deflection rate of the electron beam current in the display tube in dependence upon the determined derivative, a position error correction circuit for correcting the video signal in dependence upon the derivative of the luminance component of the video signal, and means for applying the corrected video signal to the control electrode of the display tube, characterized in that the position error correction circuit comprises a frequency-modulatable clock (16) which is coupled to the means for determining the derivative of the luminance component of the video signal, said frequency-modulatable clock thereby generating a read clock signal; and a memory into which said video signal is written, said memory having a read clock signal input to which said read clock signal is applied, whereby the video signal stored in said memory is read at a frequency-modulated clock rate in dependence on said derivative of the luminance component.

2. A display device as claimed in claim 1, characterized in that the means for determining the derivative of the luminance component of the video signal comprise a clock signal generator, a further memory and a differentiator, the luminance Component of the video signal being written into said further memory under the control of said clock signal generator, and the luminance component stored in said further memory being applied to the differentiator.

3. A display device as claimed in claim 2, characterized in that the output of the differentiator is coupled to the scan velocity modulator for supplying a modulation signal.

4. A display device as claimed in claim 2, characterized in that the memory includes a write clock signal input coupled to the output of said clock signal generator so that the video signal is written into said memory at a fixed write clock rate under control of the clock generator.

5. A display device as claimed in claim 1, characterized in that the means for applying the corrected video signal comprises a display tube control circuit for receiving the modulated video signal read from the memory and for applying the video signal suitable for display to the control electrode(s) of the display tube.

6. A display device as claimed in claim 1, characterized in that the display device further comprises a beam current modulator coupled to an output of said means for determining a derivative for modulating the electron beam current in dependence upon the determined derivative of the luminance component in the video signal.

7. A display device as claimed in claim 6, characterized in that the beam current modulator has an output coupled to the means for applying the corrected video signal to the control electrode of the display tube for adapting the video signal in the applying means in dependence upon the output signal of the beam current modulator.

8. A display device as claimed in claim 1, characterized in that the display device also comprises an aperture correction circuit for correcting the luminance component of the video signal in dependence upon the derivative of the luminance component, the display device comprising a comparator for comparing the luminance component with a reference value and for aperture-correcting said component in dependence upon the output signal of the comparator.

Description:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to a display device for displaying a video signal on a display screen of a display tube comprising at least one control electrode and deflection coils for deflecting at least one electron beam current, said display device further having an input for receiving the video signal, means for determining a derivative of a luminance component of the video signal, a scan velocity modulator for modulating the deflection rate of the electron beam current in the display tube in dependence upon the determined derivative, a position error correction circuit for correcting the video signal in dependence upon the derivative of the luminance component of the video signal, and means for applying the corrected video signal to the control electrode of the display tube.
2. Description of the Related Art
A display device of this type is known from U.S. Pat. No. 4,183,064. In this known display device, the position error is corrected by enlarging the portion of a display line having a higher luminance with respect to a portion having a smaller luminance and by subsequently applying scan velocity modulation (so as to obtain an improved definition) at which the dark/light transition is delayed and the light/dark transition is brought forward. As a result, the picture to be displayed is displayed with the original picture contents (the same quantity of light and dark portions as in the original video signal). In this solution, a second error (enlarging the light portions) is deliberately introduced to correct the first error (reducing the light portions as a result of scan velocity modulation). This is not an ideal solution because the two errors must compensate each other in this case. Correcting a non-linear error by means of a linear system is not very well possible. The drawback is that the position error cannot be satisfactorily corrected in this way. At a less sharp transition from light to dark (or conversely), the second error will be too large so that it will overcompensate the first error, whereas with a very sharp transition, the second error is too small so that the first error is not fully compensated. A further drawback is that it is not easy to enlarge the portions of the video signal having a higher luminance/brightness. Moreover, by enlarging the light portion, the beam current is increased so that the definition is adversely influenced due to spot growth.
To give pictures a better (impression of) sharpness, manufacturers focus on improvements of the display tube, inter alia by providing an improved phosphor layer and by improving the electron gun/guns. Moreover, scan velocity modulation of the electron beam deflection is used in a display tube (as is described, for example in the above-mentioned U.S. Patent). In this method the scan velocity (deflection rate) is adapted to the picture contents, notably to brightness variations. In scan velocity modulation, the derivative of the luminance component of the video signal is determined. Generally, the second derivative of the luminance component is used, which second derivative is applied to a voltage amplifier, an output of which applies a voltage to, for example, a scan velocity modulation coil. If a voltage-controlled current source is used instead of the voltage amplifier, the first derivative of the luminance component is taken. Actually, the scan velocity modulation coil is then the second differentiator. The scan velocity modulation is proportional to the second derivative of the voltage across the coil. By using scan velocity modulation, a position error is produced on the display screen (the video information rate is no longer synchronous with the scan velocity) at which a dark/light transition of the video signal is shifted to the right and a light/dark transition of the video signal is shifted to the left on the display screen. Consequently, portions of the video signal having a higher brightness/luminance are reduced with respect to portions of the video signal having a smaller light intensity. For example, when a plurality of successive squares (for example, a chessboard) is displayed, this effect can be clearly observed: larger (darker) and smaller (lighter) squares instead of squares all having the same size.
SUMMARY OF THE INVENTION
It is, inter alia an object of the invention to eliminate the above-mentioned drawbacks. To this end, the display device according to the invention is characterized in that the position error correction circuit comprises a frequency-modulatable clock which is coupled to the means for determining the derivative of the luminance component of the video signal for frequency-modulating the read clock rate of the video signal stored in a memory.

By modulating (varying) the clock rate at which the video information is written or read, the position error caused by scan velocity modulation can be corrected. The video signal is applied to the display tube at the same information rate as the scan velocity. Here, a (position) error which would arise due to scan velocity modulation is thus corrected instead of making two errors which hopefully counteract each other and are equally large as described in said U.S. patent.
Literature describes all kinds of examples in which higher derivatives or combinations of different derivatives for correcting the position error are used instead of the first and second derivatives of the video signal for use in scan velocity modulation. However, this results in a full correction of the position error at most for given slopes of transitions from light to dark and vice versa, whereas the picture will only degrade in the case of other slopes. Moreover, this renders the scan velocity modulation circuit much more complicated and hence more expensive. The display device according to the invention provides a solution which is completely different. This solution is that it is not attempted to correct the position error by means of the scan velocity modulation method (or by introducing a second error) but by modulating the clock with which the video information and the deflection is maintained synchronous at all times, thus principally precluding a position error.
The clock modulator is controlled by the same signal or by a corresponding signal with which the scan velocity modulator is controlled.
An embodiment of a display device according to the invention is characterized in that the display device further comprises a beam current modulator for modulating the electron beam current in dependence upon the determined derivative of the video signal. By using beam current modulation, brightness modulations occurring as undershoots and overshoots which may be produced by scan velocity modulation can be prevented or in any case reduced. This provides the possibility of using scan velocity modulation at a larger amplitude without this being a hindrance to the user of the display device, while a better picture sharpness is obtained. A larger amplitude of the scan velocity modulation results in a larger position error, which position error can be simply corrected again by means of the clock modulation.
A further embodiment of a display device according to the invention is characterized in that the display device also comprises an aperture correction circuit for correcting the luminance component of the video signal. By combining the scan velocity modulation with an aperture correction, a picture which is even sharper is obtained. At small or less steep jumps in the beam currents, the scan velocity modulation does not yield considerable improvements of the picture sharpness, whereas the opposite is true for aperture correction. By combining scan velocity modulation with an aperture correction, the sharpness of the picture can also be improved at these beam currents. 

PHILIPS 100hz digital processing part :

The invention relates to an arrangement for converting an original picture signal representing a sequence of frames, each of which is composed of two interlaced fields, into a converted picture signal which has a double field frequency with respect to the original picture signal.
When converting a picture signal into such a converted picture signal which, with respect to the original picture signal, has a double field frequency, there is the problem that every second field of the converted picture signal must be newly generated, because no corresponding field of the original picture signal is available with respect to time and also with respect to the picture information.
In simple arrangements for doubling the field frequency, every field is doubled. A moving object in the fields of the converted picture signal is imaged twice in the same position before it jumps to the next position in the two subsequent fields. Since the human eye cannot follow these jumps, it is incident on the average speed of motion and observes a moving object from field to field at different positions. This leads to a double structure and motion blurr.

In other arrangements for field doubling of a picture signal a motion compensation is therefore provided by means of which the motion between two fields of the original picture signal is determined so that the motion can be taken into account in fields of the converted picture signal to be generated therebetween as a function of time and a corresponding interpolation can be performed. However, such arrangements have the further problem that possibly present noise is also to be reduced and that the line flicker, which still occurs in spite of the doubling of the field frequency in picture signals generated by way of interlaced scanning, is to be reduced. In the state of the art arrangements are only known in which a motion compensation is combined either with a noise reduction or with a line flicker reduction.

  100HZ DIGITAL TELEVISION PICTURE SCAN TECHNOLOGY OVERVIEW


 In an arrangement for converting an original picture signal representing a sequence of frames, each of which is composed of two interlaced fields, into a converted picture signal which has a double field frequency with respect to the original picture signal, is for doubling the field frequency, for the purpose of noise reduction, motion compensation and line flicker reduction, a memory arrangement (1, 2) provided for doubling the field frequency, which memory arrangement precedes a motion compensation arrangement (5) whose output signal is applied to a noise reduction arrangement (6), and a line flicker reduction arrangement (7) is provided which receives the output signals from the noise reduction arrangement (6) and the motion compensation arrangement (5), while the converted picture signal is obtained from the output signal of the noise reduction arrangement (6), the line flicker reduction arrangement (7) or the motion compensation arrangement (5), dependent on the position with respect to time of a field to be generated of the converted picture signal. ( U.S. Philips Corporation)

Other References:

 PHILIPS INTELLECTUAL PROPERTY & STANDARDS (Stamford, CT, US)

 U.S. Philips Corporation (New York, NY)

A. Ibenthal et al., "Motion compensated 100 Hz Conversion", Philips Components, Internal Laboratory Report.  

1. A system for converting an original picture signal representing a sequence of frames, each of which is composed of two interlaced fields, into a converted picture signal which has a double field frequency with respect to the original picture signal, comprising: a memory for doubling each field of the original picture signal, a motion compensation circuit receiving an output signal from the memory, a noise reduction circuit receiving an output signal from the motion compensation circuit, a line flicker reduction circuit receiving output signals from the noise reduction circuit and the motion compensation circuit and a multiplexer for generating a converted picture signal that is obtained from the output signals of the noise reduction circuit, the line flicker reduction circuit or the motion compensation circuit, dependent on position with respect to time of each field to be generated of the converted picture signal with respect to the original picture signal.

2. The system as claimed in claim 1, wherein said memory comprises a first field memory, the original picture signal being written into the first field memory and read from the first field memory at a double field frequency, each field being consecutively read twice, and wherein said system comprises a second field memory into which each field read for the second time from the first field memory is written after said each field read for the second time has passed through the noise reduction circuit.

3. The system as claimed in claim 2, wherein the first and second field memories precede a line memory which buffers a picture line of one of the output signals of the first and second field memories.

4. The system as claimed in claim 1, wherein the line flicker reduction circuit comprises a median filter receiving three input signals each having an amplitude values, one of the input signals having an amplitude value between the other two amplitude values, the median filter supplying as an output signal the one input signal.

5. The system as claimed in claim 3, wherein the motion compensation circuit receives the output signals of the first and second field memories and the line memory, and in that the motion compensation circuit determines a motion vector from two consecutive fields of the original picture signal read from the field memories, said motion vector indicating motion between the two fields for a group of pixels of these fields.

6. The system as claimed in claim 2, wherein the line flicker reduction circuit is a median filter receiving three input signals each having an amplitude values, one of the input signals having an amplitude value between the other two amplitude values, the median filter supplying as an output signal the one input signal.

7. The system as claimed in claim 3, wherein the line flicker reduction circuit is a median filter receiving three input signals each having an amplitude values, one of the input signals having an amplitude value between the other two amplitude values, the median filter supplying as an output signal the one input signal.

8. The system as claimed in claim 5, wherein the multiplexer generates a sequence of four fields of the converted picture signal corresponding to two fields of a frame of the original picture signal, a first field of the sequence being obtained from the output signal of the noise reduction circuit, a second and a third field of the sequence being obtained from the output signal of the line flicker reduction circuit, and a fourth field of the sequence being obtained from the output signal of the motion compensation circuit.

9. A system for converting an original picture signal representing a sequence of frames, each of which is composed of two interlaced fields, into a converted picture signal which has a double field frequency with respect to the original picture signal, comprising: a memory for doubling each field of the original picture signal,a motion compensation circuit receiving an output signal from the memory, a noise reduction circuit receiving an output signal from the motion compensation circuit, a line flicker reduction circuit receiving output signals from the noise reduction circuit and the motion compensation circuit and a multiplexer for generating a converted picture signal that is obtained from the output signals of the noise reduction circuit, the line flicker reduction circuit or the motion compensation circuit, dependent on position with respect to time of each field to be generated of the converted picture signal with respect to the original picture signal,
wherein the multiplexer generates a sequence of four fields of the converted picture signal corresponding to two fields of a frame of the original picture signal, a first field of the sequence being obtained from the output signal of the noise reduction circuit, a second and a third field of the sequence being obtained from the output signal of the line flicker reduction circuit, and a fourth field of the sequence being obtained from the output signal of the motion compensation circuit.


10. The system as claimed in claim 9, wherein in generating the first field of the sequence, the multiplexer obtains a value of each pixel of a line position x in a picture line y by addition of a value, multiplied by a factor k, of a pixel of a line position x-v_x in a line y+1 of a last field of the original picture signal transmitted before a corresponding frame of the original picture signal,
and a value, multiplied by a factor 1-k, of a pixel of the line position x of the picture line y of a first field of the corresponding frame of the original picture signal, the value v_x being a motion vector supplied by the motion compensation circuit and the value k determining a measure of noise reduction.


11. The system as claimed in claim 9, wherein in generating the second field of the sequence, the multiplexer obtains a value of each pixel of a line position x in a picture line y by median filtering from a value of a pixel of a line position x+(v_x.1/2) in a line y+1 of a first field of a corresponding frame of the original picture signal,
a value of a pixel of the line position x+(v_x.1/2) in a line y+1 of the first field of the corresponding frame of the original picture signal, and a value of a sum of
a value, multiplied by a factor k, of a pixel of the line position x+(v_x.1/2) in the line y-1 of the first field of the corresponding frame of the original picture signal
and a value, multiplied by a factor 1-k, of a pixel of a line position x-(v_x.1/2) in the line y of a second field of the corresponding frame of the original picture signal,
the value v_x being a motion vector supplied by the motion compensation circuit and the value k indicating a measure of noise reduction.


12. The system as claimed in claim 9, wherein in generating the third field of the sequence, the multiplexer obtains a value of each pixel of a line position x in a picture line y by median filtering from a value of a pixel of a line position x+v_x in the line y of a first field of the corresponding frame of the original picture signal,
a value of a pixel of the line position x in a line y-1 of a second field of the corresponding frame of the original picture signal,
and a value of a sum of
a value, multiplied by a factor k, of pixel of the line position x+v_x in the line y of the first field of the corresponding frame
and a value, multiplied by a factor 1-k, of a pixel of the line position x in a line y+1 of the second field of the corresponding frame of the original picture signal,
the value v_x being a motion vector supplied by the motion compensation circuit and the value k determining a measure of noise reduction.


13. The system as claimed in claim 9, wherein in generating the fourth field of the sequence, the multiplexer obtains a value of each pixel of a line position x in a picture line y from a value of a pixel of a line position x+(v_x.1/2) of the line y of a second field of a corresponding frame of the original picture signal, the value v_x being a motion vector supplied by the motion compensation circuit.

Description:

BACKGROUND OF THE INVENTION
The invention relates to an arrangement for converting an original picture signal representing a sequence of frames, each of which is composed of two interlaced fields, into a converted picture signal which has a double field frequency with respect to the original picture signal.
When converting a picture signal into such a converted picture signal which, with respect to the original picture signal, has a double field frequency, there is the problem that every second field of the converted picture signal must be newly generated, because no corresponding field of the original picture signal is available with respect to time and also with respect to the picture information.
In simple arrangements for doubling the field frequency, every field is doubled. A moving object in the fields of the converted picture signal is imaged twice in the same position before it jumps to the next position in the two subsequent fields. Since the human eye cannot follow these jumps, it is incident on the average speed of motion and observes a moving object from field to field at different positions. This leads to a double structure and motion blurr.
In other arrangements for field doubling of a picture signal a motion compensation is therefore provided by means of which the motion between two fields of the original picture signal is determined so that the motion can be taken into account in fields of the converted picture signal to be generated therebetween as a function of time and a corresponding interpolation can be performed. However, such arrangements have the further problem that possibly present noise is also to be reduced and that the line flicker, which still occurs in spite of the doubling of the field frequency in picture signals generated by way of interlaced scanning, is to be reduced. In the state of the art arrangements are only known in which a motion compensation is combined either with a noise reduction or with a line flicker reduction.

SUMMARY OF THE INVENTION
It is an object of the invention to provide an arrangement in which the motion of the picture contents during generation of the compensated fields is taken into account when converting the picture signal into a converted picture signal at the double field frequency, and which moreover allows a noise reduction of the picture signal and a line flicker reduction.
According to the invention this object is solved in that for doubling the field frequency a memory arrangement is provided which precedes an arrangement for motion compensation whose output signal is applied to an arrangement for noise reduction, in that an arrangement for line flicker reduction is provided which receives the output signals from the noise reduction arrangement and the motion compensation arrangement and in that the converted picture signal is obtained from the output signal of the noise reduction arrangement, the line flicker reduction arrangement or the motion compensation arrangement, dependent on the position with respect to time of a field to be generated of the converted picture signal.
The actual the field frequency doubling is obtained by means of a memory arrangement. Consequently, the fields of the original picture signal are repeated at the double frequency so that a double field frequency is realised. However, this signal still has the above-mentioned errors.
An arrangement for motion compensation is therefore provided, which arrangement determines motions in the original picture signal and, with reference to the known motions, allows a compensation of this motion in the new fields to be generated of the compensated signal.
The arrangement for motion compensation precedes an arrangement for noise reduction which combines the data of two consecutive fields for the purpose of noise reduction.
Furthermore, an arrangement for line flicker reduction is provided which receives the output signals from the motion compensation arrangement and the output signals from the noise reduction arrangement.
The output signal of the arrangement, i.e. the converted picture signal of the double field frequency, is obtained from the output signal of one of said three arrangements in dependence upon the position with respect to time of a field to be generated of the converted picture signal. This alternation between the output signals of the arrangements is advantageous because different errors occur, dependent on the position with respect to time of the fields of the converted picture signal. In some fields a motion compensation is required because these fields occur with respect to time between two fields of the original picture signal. This is not required for those fields which coincide with pictures of the original picture signal. The line flicker reduction is in its turn only required for those fields which as a consequence of the interlaced scanning method do not have the correct vertical position as compared with the fields of the original picture signal from which they are generated.
The arrangement according to the invention thus offers a combination of motion compensation with line flicker reduction and noise reduction.
An embodiment of the arrangement is characterized in that the original picture signal is written into a first field memory from which it is read at the double frequency, each field being consecutively read twice, and in that a second field memory is provided into which each field read for the second time from the first field memory is written after it has passed through the noise reduction arrangement.
The first field memory is thus used for doubling the field frequency. Each field written into this memory is read twice consecutively. A second field memory already operates at this double field frequency at the input side, because each field, which was read from the first field memory for the second time and has passed through the noise reduction arrangement, is written into this second field memory. After this noise-reduced field has been written into the memory, it is available at the output of the second field memory.
Consequently, two fields of the original picture signal, however, with a doubled field frequency are available at the outputs of the two field memories for the motion compensation arrangement. One of these fields is already noise-reduced, which simplifies the determination of motion by the motion compensation arrangement.
A further embodiment of the invention is characterized in that the two field memories precede a line memory which buffers a picture line of one of the output signals of the two fields. For one of the fields information of two consecutive picture lines is thus time-parallel available, which is advantageous for the subsequent line flicker reduction.
In a further embodiment of the invention the arrangement for line flicker reduction may advantageously be a median filter whose output supplies that input signal which has the middle amplitude value of the input signals.
In accordance with a further embodiment of the invention the arrangement for motion compensation receives the output signals of the two field memories and the line memory, which motion compensation arrangement determines a motion vector from the two consecutive fields of the original picture signal read from the field memories, which motion vector indicates the motion between the two fields for a group of pixels of these fields.
This motion vector may be used for motion compensation in those fields of the converted field signal which occur with respect to time between two fields of the original picture signal.
A further embodiment of the invention is characterized in that the arrangement generates a sequence of four fields (A1₁₀₀,B1^-₁₀₀,B1*₁₀₀,B1⁺₁₀₀) of the converted picture signal corresponding to two fields of a frame of the original picture signal, the first field (A1₁₀₀) of the sequence being obtained from the output signal of the noise reduction arrangement, the second and third fields (B1^-₁₀₀,B1*₁₀₀) of the sequence being obtained from the output signal of the line flicker reduction arrangement and the fourth field (B1⁺₁₀₀) of the sequence being obtained from the motion compensation arrangement.

As a consequence of the doubled field frequency of the converted picture signal, four fields of the converted picture signal must be generated in a time range in which two fields of the original picture signal are present. These two fields of the original picture signal and the four fields of the corresponding sequence of the converted picture signal will hereinafter be referred to as corresponding fields and corresponding sequence, respectively.
The first field of the sequence is obtained from the output signal of the noise reduction arrangement. This is possible because this first field of the sequence has the right position with respect to time and location as compared with the first corresponding field of the original picture signal and because only a noise reduction is to be performed.
The second and third fields of the sequence are obtained from the output signal of the line flicker reduction arrangement, because the two fields of the original picture signal must be utilized for these two fields, at least one of which does not have the correct position with respect to time and neither has the correct vertical position due to the interlaced scanning method used.
The signal for the fourth field of the sequence is obtained from the motion compensation arrangement, because this signal can only be obtained from the second corresponding field of the original picture signal due to use of motion compensation.
The further sub-claims state how the arrangement advantageously generates the four fields for the sequence of converted picture signals from the corresponding two fields of the original picture signal.
These and other aspects of the invention will be apparent from and elucidated with reference to the embodiments described hereinafter.


BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 shows a block diagram of the arrangement according to the invention for converting an original picture signal into a converted picture signal of the double field frequency,
FIG. 2 shows a Table of the fields written into and read from the memory arrangement according to FIG. 1,
FIG. 3 shows a diagram in accordance with which the arrangement of FIG. 1 generates the first field of a sequence of the converted picture signal,
FIG. 4 is a representation, corresponding to FIG. 3, of the second field of the sequence,
FIG. 5 is a representation, corresponding to FIG. 3, of the third field of the sequence, and
FIG. 6 is a representation, corresponding to FIG. 3, of the fourth field of the sequence.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS OF THE INVENTION
FIG. 1 shows a block diagram of the arrangement according to the invention, which arrangement allows the field frequency of an original picture signal to be doubled and thus generates a converted picture signal, which generated picture signal is noise-reduced, and which performs, if necessary, a motion compensation and a line flicker reduction for the fields.
The arrangement of FIG. 1 is divided into two blocks, the first block processing the received luminance signal component Y₅₀ of the original picture signal and the second block processing the received chrominance signal component C₅₀ of the original picture signal. In the embodiment shown in FIG. 1 the chrominance signal is doubled only with respect to its frequency. The special procedures of noise reduction and line flicker reduction are performed only for the luminance signal in the embodiment shown in FIG. 1. However, it is alternatively possible to take these measures both for the luminance signal and for the chrominance signal.
In the arrangement shown in FIG. 1 the luminance signal component Y₅₀ of the original picture signal is applied to a first field memory 1 by means of which the field frequency of this signal is doubled. Each field of the original picture signal written into the field memory 1 is subsequently read twice. This reading process is performed at the double frequency. A simple doubling of the field frequency is thus already performed. However, the output signal of this field memory is only suitable for display if motion disturbances and line flicker are accepted. Furthermore, a second field memory 2 is provided whose input receives field signals to be described hereinafter, which signals already have the double field frequency. The signals of two consecutive fields of the original picture signal are parallel available at the outputs of the two field memories 1 and 2, which fields have already been doubled in field frequency.
The two field memories 1 and 2 are followed by a multiplexer 3 allowing one of the output signals of the field memories 1 and 2 to be alternatively applied to a line memory 4. The output signals of the two field memories 1 and 2 are applied to a motion compensation arrangement 5 via the multiplexer 3. The arrangement 5 thus receives the signals of the two field memories 1 and 2 and hence two consecutive fields of the original picture signal whose field frequencies have already been doubled. By using the line memory 4, the values of two pixels of the same line position of consecutive picture lines are simultaneously available for one of the two field signals.
The motion compensation arrangement 5 determines, from the two fields apply thereto, a motion which is present in the picture contents between these two fields. Advantageously, a motion vector indicating the motion between the two fields for a group of pixels is obtained from this determined motion for a group of pixels. The motion compensation arrangement 5 can determine this motion both in the horizontal direction and in the vertical direction, i.e. in the line direction as well as in the direction perpendicular to the lines. However, the motion may exclusively be determined in the line direction, which is much easier to realise in the circuit construction and also yields good results.
The arrangement shown in FIG. 1 also includes a noise reduction arrangement 6. This arrangement 6 may operate in known manner in which it combines the signals of pixels of the same location in consecutive fields. These signals are applied from the arrangement 5 to the arrangement 6. Since the arrangement 5 has already determined the corresponding motion vector, the noise reduction in the arrangement 6 can already be performed with motion-compensated signals.
The output signal of the noise reduction arrangement 6 is applied to the input of the second field memory 2, to an input of a line flicker reduction arrangement 7 and to a first input of a multiplexer 8. A signal which is already noise-reduced is thus written into the field memory 2 at the input side, which signal corresponds to that field which is read from the first field memory 1 for the second time already.
The line flicker reduction arrangement 7 which may be, for example a median filter and which selects, from the signals applied thereto, the signal with the middle instantaneous amplitude value, not only receives the output signal from the arrangement 6 but also the output signal from the motion compensation arrangement 5, because this output signal also contains the motion-compensated output signal of the line memory 4. This is necessary because a vertical interpolation must be performed for the line flicker reduction and consequently the pixels corresponding to the signals of two lines should be available, i.e. pixels of the same location in their line.
The line flicker reduction arrangement 7 not only receives these signals of two successive picture lines of a field from the arrangement 6 but also the signal of another field. In a manner to be described hereinafter a median filtering of these signals is performed, which leads to a line flicker reduction.
The output signal of the line flicker reduction arrangement 7 is applied to a second input of the multiplexer 8. A third input of the multiplexer 8 receives the output signal from the noise reduction arrangement 5.
At the output, the multiplexer 8 supplies the luminance signal Y₁₀₀ which represents the converted picture signal and which has a doubled field frequency as compared with the input signal Y₅₀. In a manner to be described hereinafter, the multiplexer 8 is switched between its three inputs dependent on the field to be generated.
FIG. 1 further shows a circuit block 9 in which the field frequency of the chrominance signal component C₅₀ of the original picture signal is doubled. This can be effected in the same way as for the luminance signal but alternatively, the field frequency may be doubled only. At the output, the unit 9 supplies the chrominance signal component of the converted picture signal.
FIG. 2 shows a Table indicating diagrammatically which fields are written into or read from the field memories 1 and 2 shown in FIG. 1.
Two consecutive fields of the original picture signal are denoted by A1, B1 and A2, B2, etc. in an unchanged form. Two fields having the same cipher form part of a frame. The two fields are generated in accordance with the interlaced scanning method.
As is shown in the Table of FIG. 2, for example two fields A1 and B1 of a frame of the original picture signal are written into the field memory 1 of FIG. 1, which field memory is denoted by FM1 in FIG. 2. Each of these two fields is subsequently read twice from the

field memory 1, which reading is effected at the double frequency so that the field frequency of these pictures is already doubled.
If a field is read from the first field memory 1 for the second time, this signal reaches the input of the field memory 2 denoted by FM2 in the Table of FIG. 2, after it has passed through the arrangement 5 and the arrangement 6 of FIG. 1. At the next reading step of the field memories 1 and 2, two fields whose field frequencies have already been doubled are available at their outputs. As one of the fields, viz. the field written into the field memory 2 has already passed through the noise reduction arrangement, this field is already noise-reduced which is denoted by NR in the Table of FIG. 2.
The result is that two fields from the original picture signal having an already doubled field frequency are available at the outputs of the field memories 1 and 2 in FIG. 1.
It will now be explained with reference to FIGS. 3 to 6 how the four fields A1₁₀₀,B1^-₁₀₀,B1*₁₀₀ and B1⁺₁₀₀ of the output signal Y₁₀₀ as shown in the Table of FIG. 2, which are the signals of the multiplexer 8 as shown in FIG. 1, are obtained. These four fields are hereinafter assumed to be associated with a sequence. A frame of the original picture signal or two fields of this signal, viz. the fields A1 and B1 correspond to this sequence. The four fields of the sequence will hereinafter be assumed to correspond to these two fields of the original picture signal.
FIG. 3 shows diagrammatically, above a broken line, two fields B0_NR and A1 of the original picture signal read from the two field memories 1 and 2 of FIG. 1. Below the broken line, a field A1₁₀₀ is shown which represents the first field of a sequence of the converted picture signal. This signal of the field A1₁₀₀ is to be generated by the arrangement of FIG. 1.
To this end the output signal of the first field memory 1 is used, from which field memory the field A1 of the original picture signal (at the doubled field frequency) is read. The field B0 of the original picture signal was already previously written in a noise-reduced form into the field memory 2. At the output, this signal is now available as signal B0_NR at the output of the second field memory simultaneously with the signal A1. The first field A1₁₀₀ of the sequence is obtained from these two output signals of the field memories 1 and 2 in accordance with the diagrammatic representation in FIG. 3.
This field A1₁₀₀ to be generated has the correct position vertically and with respect to time as compared with the field A1 of the original picture signal. Therefore, only a noise reduction should be carried out, and a line flicker reduction in particular is not necessary.
The output signals of the field memories 1 and 2 are utilized for the noise reduction, while it is advantageous to submit the field read from the field memory 2 and not having the correct position with respect to time as compared with the field A1₁₀₀ to be generated to a motion compensation of its picture contents. The motion vector determined by the motion compensation arrangement 5 in accordance with FIG. 1 is utilized for this purpose. This motion vector is denoted by v_x in FIG. 3.
For a pixel marked in picture line 3 of the field A1₁₀₀ in FIG. 3, th₁₀₀, as read from the field memory 1, is utilized. Moreover, the pixel of the field B0_NR as read from the second field memory and offset by the motion vector v_x is used. This pixel is taken from line 4. A noise-reduced signal is obtained from these two pixels of the two fields. A factor k is provided for this purpose, indicating the degree of noise reduction. The pixel from the field A1 is multiplied by a factor 1-k and the pixel from the field B0_NR is multiplied by a factor k. These two multiplied values are added and constitute the value of the marked pixel of the field A1₁₀₀.
e pixel of the same line position and the same line number of the field A1
If k is chosen to be small, only a small or no noise reduction is to be performed and this pixel is essentially obtained from the corresponding pixel of the field A1. With a larger factor k, the value of the pixel is increasingly being taken from the field B0_NR.
The generated field A1₁₀₀ thus corresponds to the field A1 of the original picture signal, but for the performed noise reduction. It is written into the second field memory 2 of FIG. 1 and is available as A1_NR for subsequent fields to be generated.
During the generation of the first field A1₁₀₀ the multiplexer 8 is switched to its first input in accordance with FIG. 1, because the output signals for the noise reduction are used as output signals in accordance with the diagrammatic representation in FIG. 3 and hence as signals for the field A1₁₀₀.

FIG. 4 is a representation, corresponding to FIG. 3, for obtaining the second field B1^-₁₀₀ of the sequence.
As compared with the two fields of the original picture signal, this second field of the sequence neither has a vertically correct position nor a correct position as regards time. Therefore, a motion compensation and a line flicker reduction are performed.
At the instant of generating this second field, the field B1 of the original picture signal is read from the first field memory and the field A1 of the original picture signal is read in a noise-reduced form from the second field memory.
In the representation in FIG. 4 a pixel of the picture line 2 is marked for the field B1^-₁₀₀. The value of this pixel is generated from three values by means of median filtering, which values are obtained from the fields A1_NR and B1.
The first of these values is obtained from the picture line 3 for that pixel which, after being offset by half the motion vector (v_x.1/2) has the same position as the pixel to be generated in the field B1^-₁₀₀. The second input signal of the median filter is obtained from the pixel of the same line position of line 1 of the field A1_NR. The value of this pixel is also multiplied by a factor k. Moreover, that pixel of the picture line 2 of the field B1 which, after use of half the negative motion vector (-v_x.1/2) has the same picture line position as the pixel to be generated of the field B1^-₁₀₀ is multiplied by a factor 1-k. These two values are added and the sum constitutes the third input signal for the median filtering. Due to the median filtering, the input signal having the middle instantaneous amplitude value is selected from these three input signals. This signal is constituted by the value of the marked pixel of the second field B1^-₁₀₀ of the sequence.
As already shown in the representation according to FIG. 4, a motion compensation for all signals is required for this field. Moreover, a line flicker reduction is to be performed. Consequently, the multiplexer 8 is switched to its second input for generating the value of the field B1^-₁₀₀ in accordance with the representation in FIG. 1, which input receives the output signal from the line flicker reduction arrangement 7.

FIG. 5 is a representation corresponding to FIGS. 3 and 4, but in the representation according to FIG. 5 the third field B1*₁₀₀ of the sequence is to be generated.
The two corresponding fields A1 and B1 of the original picture signal are used again for generating this field. The field B1 is read from the field memory 1 of FIG. 1. The field A1, which is already noise-reduced, is read from the field memory 2 of FIG. 1.
A median filtering is performed again, because the output field B1 has the incorrect vertical position. The output field A1_NR additionally has the incorrect position with respect to time so that also a motion compensation has to be performed for this field.
A median filtering of three input signals is carried out for generating one of the pixels marked in FIG. 5, of the picture line 3 of the field B1*₁₀₀.
The first of these input signals represents the value of the pixel of the picture line 2 of the field B1, which has the same picture line position in its picture line as the pixel to be generated in its picture line. Moreover, from the field A1, as read from the second field memory, that pixel is used which after correction by the motion vector v_x has the same line position as the pixel to be generated. This motion-compensated pixel represents the second input signal of the median filter. The third input signal is formed by the sum of the value of the same line position of the pixel of the picture line 4 of the field B1, multiplied by a factor 1-k, and the value of the second input signal of the median filter, multiplied by a factor k. This sum represents the third input signal of the median filter and is simultaneously written as input signal into the second field memory from which it can be read again for fields to be subsequently generated.
The multiplexer 8 of the block diagram in FIG. 1 is switched to its second input for generating the third field B1*₁₀₀ of the sequence, because a line flicker reduction as well as a motion compensation have to be performed.
In FIG. 6, corresponding to the representations in FIGS. 3 to 5, the values of the fourth field B1⁺₁₀₀ of the sequence are to be obtained.
Since the field B1 used for this purpose (in a noise-reduced form) of the original picture signal has the correct vertical position,⁺₁₀₀, a line flicker reduction is not necessary in this case. The field B1_NR has, however, the incorrect position with respect to time so that a motion compensation is necessary.

i.e. the same position as the field B1
Consequently, for a pixel as marked by way of example in FIG. 6 in picture line 2 in a given position, that pixel of the field B1_NR as read from the field memory 2 is used which has the same line position as the pixel to be generated in its picture line after correction by half the motion vector (v_x.1/2).
Since only a motion compensation (in addition to noise reduction) is necessary in this case, the multiplexer 8 of FIG. 1 is switched to its third input.
The way of generating a sequence of four fields in accordance with FIGS. 3 to 6 is continuously repeated, with four corresponding fields of the converted picture signal being obtained for two output fields of the original picture signal. 

 

 

 

 

PHILIPS SAA4940H NOise Reduction IC (NORIC)

FEATURES - Constant and motion adaptive noise reduction - Cross colour and cross luminance reduction 0 Colour generation for side panels. box or border o Possibility for cross fade between two synchronized video inputs 0 Prepared for Mu|ti—P|P applications - Split screen noise reduction inside or outside box o Solarization - Internal bypass for 4:4:-1 format
 
GENERAL DESCRIPTION The NOise Reduction IC (NORIC) is intended ior noise reduction purposes. Together with the BENDIC (SAA7158WP) it is designed to operate in an 100/120 Hz environment. However, an application with 50/60 Hz environment is possible. The NORIC is designed to co-operate with an 8051 type of microprocessor, the BENDIC and Texas Instruments lield memories plus memory/sync controller, but other configurations may be applicable,
 
 
FUNCTIONAL DESCRIPTION The main function of the NORIC is shown in Fig.1. The video A and B busses are split into Y data and UV data, which will each have its own processing. Combination of the data from video A and B is carried out by the subtractor/multiplier/adder sections. Video C will therefore be a linear combination of video A and B data, where video D is mainly a copy of video B. but with appropriate processing delay. Grey/colourized, pixel repetition and sawtooth insert are operated on the video B sources. With K set to 1 both video C and D will be affected by these functions. For noise reduction, K may be fixed for constant noise level reduction or dependent on movement detection for motion adaptive noise reduction.
 


Implementation The noise reduction function is based upon the control of the K-factor that interpolates between the direct input video A and the field delayed (already noise reduced) input video 8. The setting of the K-factor is dependent on the operating mode: a) K is a constant, which can be set to 0. ‘/32. ‘/16. ‘/8, 3/8. 3/E. 4/a, 5/ti. 5/is. 7/8 and 8/is. b) K is dependent on (an eventually filtered version of) the absolute difference in luminance between the output of the field memory and the input. This dependency is staircase-like, of which the start of each step can be programmed. An example is shown in Fig.6, where the edges of the steps are programmed as: K_step0 = 3 K_step1 = 7 K_step2 = 16 K_step3 = 28 K_step4 = 44 K,_,step5 = 64 K_step6 = 88 K_step7 = 120 c) K can be switched from fixed (situation a) to adaptive (situation b) inside or outside a rectangular box. This enables the possibility for a split screen of the noise reduction function. d) K is 0 during ‘recirculate', which may be inside or outside a rectangular box. This enables selective updating of the field memory contents, to be used e. g. for multi-PIP. (step from K = 1/is to K = 1/5; 3 x weight of 1) (step from K = ‘A3 to K = $8; 7 x weight of 1) (step from K = Z1; to K = 3/8; 8 x weight of 2) (step from K = 3/a to K = 4/e; 14 x weight of 2) (step from K = ‘/8 to K = 5/8; 11 x weight of 4) (step from K = 5/9 to K = 64;: 16 x weight of 4) (step from K = 5/is to K = 7/a; 11 x weight of 8) (step from K = 741 to K = 5/B: 15 x weight of 8) In the adaptive mode, the circuit of Fig.5 is used for the determination of the K value for each pixel in the video. The (horizontal) low pass filters are useful to discriminate better between noise and movement. Also curves can be implemented that will pass cross-luminance patterns as noise, which will then get reduced. In chapter ’NORIC control’ the various transfer functions of TF1 and TF2 are listed. DJ! 05 0.25 n o {r‘ 0 23 so 75 too us ucozn Fig.6 K curve example.

 
Cross colour and cross luminance reduction As a side effect of the noise reduction algorithm, disturbances of cross colour and cross luminance will also be reduced. Cross colour is reduced because the movement detection (that operates on luminance only) will not detect any movement in the cross colour pattern and therefore averages the colour contents over many fields of video. As the colour vector in the cross colour patterns is in various phases (0, 90, 180 and 270 degrees) in successive fields, the average of many fields of video will have significantly less of the cross colour pattern, Cross luminance is reduced if the cross luminance pattern is not detected as movement by the movement detection algorithm. This can be implemented by using a (horizontal) filter characteristic that has a zero in the frequency area of the luminance pattern. As the cross luminance pattern is in various phases (0. 90, 180 and 270 degrees) in successive fields, the average of many fields of video will have significantly less of the cross pattern. Colour and pixel repetition generation for side panels, box or border A constant colour value can be generated and led to the outputs video C and video D. The colour value is set by the microprocessor, by coding the luminance value in 8 bits and the U and V values in their most significant 4 bits each. The least significant U and V bits remain 0. The number of colours to be generated is therefore 64 k. Side panels are generated where the memory outputs are inactive (RE LOW). The side panels can use the colour generation as described above or maintain the last active video data from the memory on each video line (pixel repetition). A rectangular box can be generated. in which colour, pixel repetition or a recirculate function can be performed. This rectangular box is defined by the coordinates of the left-upper edge (hor_start_box, vert_start_box) and the right_lower edge (hor__stop_box, vert_stop_box).

 
Cross-fade between two video Inputs If video A and video B are (synchronized) video sources, an interpolation to the video C output is made with a K setting between 0 and 1. Cross fading is therefore a matter of varying K from 0 to 1 or from 1 to 0 by the microprocessor. Use of NORIC for Multl-PIP Mu|ti—PlP operation consists of selective updating the memory contents, for the size of a PIP picture. The NORIC can help this process by having recirculated all the memory contents, except a part within a rectangular box. Implementation of noise reduction split screen To demonstrate the result of the noise reduction it is easier to show part of the picture with, and the rest of the picture without noise reduction. The rectangular box (not border) can therefore be used to switch between NR on and off, The box may e. g. cover the right half of the picture. Horizontal sawtooth generation For easy testing of the board. the luminance part of the video C bus can be applied with a horizontal synchronous sawtooth, that has an increment in every 4 pixels. This mode can be set by either the microprocessor or by applying a LOW level on the SAWN input. This input has an internal pull-up, thus short—circuiting this pinto ground for testing is sufficient, it overrules all other modes in the NORIC. Solarlzatlon This function reduces the internal signal quantization from 8 to 4 bits. Of the luminance signal Y the lower four bits are constantly kept at 1 which gives a slight positive offset in brightness. The four lower bits of U and V are made equal to the sign-bit which gives a slight decrease in saturation. Bypass of YUV 4:4:4 data Although the data from the video A bus undergoes reformatting and formatting operations, normally used to operate on encoded UV data, the NORIC can be controlled to have a transparent throughput from video A to video C and from video B to video D. The data will remain having a delay of 12 clock cycles. All other features in the NORlC are excluded in this mode.
 

 

LOEWE ARCADA 72-100 PIP (53471L39)  CHASSIS Q2100  (110Q21)   SAA7158 Back END IC


GENERAL DESCRIPTION
Application Environment
The Back END IC (abbreviated as BENDIC) is designed to cooperate with an 8051 type of microprocessor, the ECO3
(SAA4951) memory controller and Texas Instruments TMS4C2970 memories, but other configurations may be
applicable. Fig.1 shows the block diagram of the feature box. The nominal clock frequency of the IC is 27 MHz or 32 MHz,
with a maximum of 36 MHz.
The system supports the digital Y/U/V bus for selection of different video signal sources. The Y/U/V bus and the BENDIC
data input are fully synchronous with respect to the clock signal. A line reference signal BLN for timing control purposes
has to be provided by external elements which always controls the system timing, independent of active signal sources
or desired functions.
Analog Characteristics
The BENDIC contains 3 independent, high speed digital to analog converters for luminance and colour difference signal
processing and conversion. The resolution of the two DA converters for the colour difference signals is 8 bit. The
luminance peaking up to 6 dB at high frequencies widens the resolution of the luminance channel. To avoid aliasing
effects due to time discrete amplitude limiting the resolution of 9-bit is offered for the luminance conversion. All output
stages provide high performance output stages for driving lines with low impedance line termination.

FEATURES
· Line Flicker Reduction (LFR) by means of MEDIAN filtering
· Vertical zoom
· Digital colour transient improvement
· Digital luminance peaking
· Movie phase detection
· 4:4:4 YUV data throughput selectable, standard is 4:1:1 Y/U/V
· D/A conversion
· UART interface.

FUNCTIONAL DESCRIPTION
Block Diagram
The BENDIC will be produced in a CMOS double metal process. It is possible to feed the BENDIC with 8-bit wide
luminance and chrominance signals Y/U/V in 4:1:1 mode from the digital Y/U/V bus and to run it in a bypass mode with
Y/U/V in 4:4:4 mode without any bandwidth reduction.
The BENDIC contains the processing functions as depicted in Fig.3.
Following functions are available:
Datapath:
· 1H - 4:1:1 line memory, 852 words by 8-bits luminance + 4-bits multiplexed chrominance
· REFORMATTER to get 8-bit wide UV from the Y/U/V bus format
· MIX UV and MIX Y to interpolate between actual and 1H-delayed input signals, programmable for realization of vertical
zoom
· MEDIAN filter in luminance processing path for line flicker reduction
· MOVIE PHASE DETECT for supporting line flicker reduction control
· PEAKING for luminance channel
· UPSAMPLING and DCTI for chrominance transient improvement
· HOLD/GREY/BLANK blocks for blanking and grey level insertion
· RE PROCESSING controls read enable for first and second memory, outputs are programmable for different
applications
· Data switches for field select, mix/median select, 4:1:1/4:4:4 select
· DAC blocks for digital to analog conversion of Y, U, V video signals
· REGISTER with 3-state control for direct output of Y/U/V 1 input to memories.
Control:
· mP INTERFACE for the control of BENDIC functions, including zoom control
· TIMING CONTROL and TEST as support blocks.
All video data signal processing inside the BENDIC is phaselinear and nonrecursive (except line delay in recirculation
mode).

Data Path Signal processing
· 1H - 4:1:1 line memory, 852 words by 8-bits luminance
+ 4-bits multiplexed chrominance
The Y/U/V line memory is organized as 852 x 12 bits. It
works as a shift register with recirculation mode if desired.
The line start is synchronized to RE, and if there are more
than 852 words to be stored it will stop and hold.
· REFORMATTER to get 8-bit wide UV from the Y/U/V
bus format
The reformatter changes the 4:1:1 format of UV signals
into a sequential 8-bit U and V data stream with a sampling
rate of half the master clock.
· MIX UV and MIX Y to interpolate between actual and
1H-delayed input signals, programmable for realization
of vertical zoom
The function of the MIX-blocks is to interpolate between
two input sources A and B (original signal and 1H-delayed
signal). Possible interpolation coefficients
are
· MEDIAN filter in luminance processing path for line
flicker reduction
The median filter consists of two different median filters
working in parallel with full clock rate. Filters for up and
downsampling are implemented with an 8-bit output.
· MOVIE PHASE DETECT for supporting line flicker
reduction control
A pixel by pixel luminance level comparison is made on the
active video of two consecutive fields from the memory.
The absolute difference of the 4 most significant bits of
each pixel from the two fields is added to the accumulated
value of the current field in a register. The highest
significant two bytes thereof are transferred during field
blanking period with rising edge of RSTR signal into a
register that can be read via the mP interface. After reading
the register will be cleared.
· PEAKING for luminance channel
The H-peaking of the luminance channel compensates the
bandwidth reduction caused by various components of the
TV signal processing chain. Because of the possibility to
convert over and undershoots it is even possible to
precompensate the si-amplitude attenuation of the D/A
converter by 6 dB. The absolutely phaselinear filters can
be programmed: frequency response, amplitude of the
high frequency signals and degree of coring is controlled
via the mP interface. Frequency responses c. f. separate
application sheet.
1 or 3
4
--- or 1
2
----- or 1
4
----- or 0 } A B – ( ) ´ B. + {
· UPSAMPLING and DCTI for chrominance transient
improvement
After upsampling of U and V, in the DCTI block the U and
V signals are processed with a
look-backwards/look-forwards device. The chrominance
signal values are stored in a 26 tap pixel delay line.
Controlled by a multiplexer select signal K the values are
read from the pixel delay line into the output registers of
DCTI. The calculation of the K signal is done within this
block. To determine the number of steps to look back and
forwards the following relation is used:
U and V are processed serially with the same circuitry. The
final upsampling towards the master clock for D/A
conversion is part of the algorithm and done by linear
interpolation between two adjacent taps of choice. It is
controlled by the K signal too.
· HOLD/GREY/BLANK blocks for blanking and grey level
insertion
The function of these blocks is to insert desired levels for
Y, U and V, where no active video is present. BLANKing is
performed during line and field blanking period indicated
by BLN. GREY is performed where RE indicates that the
memory is not read out, and pixel repetition is switched off
by the mP interface; the grey value comes via the mP
interface. HOLD is performed if pixel repetition is selected
by the mP interface; the last value of Y, U and V is kept until
RE is active again.
· RE PROCESSING controls read enable for first and
second memory
Here the output signals RE1 and RE2 are shifted by
adding a programmable delay of 5, 6, 7 or 8 clock pulses
with respect to the input signals. In addition RE1 will be
influenced in case of zoom.
· data switches for field select, mix/median select,
4:1:1/4:4:4 select
The switches shown in the block diagram Fig.3 are
controlled via the mP interface and allow control of the data
streams inside the BENDIC.
· DAC blocks for digital to analog conversion of Y, U, V
video signals
The D/A conversion is performed in the DAC blocks. The
converters consist of the resistor strings to be connected
externally and three buffers with a 25 W serial resistor at
the output built in. To get 75 W impedance externally three
50 W resistors have to be used near the pins. The
capacitive load at the outputs should not exceed 30 pF.



· REGISTER with 3-state control for direct output of Y/U/V
1 input to memories
The 3-state switch with internal register is supplied for the
feedback data to the second memory. The feedback bus is
a copy of the field 1 bus, but with 4 clockpulses delay.
3-state control is done via mP interface.
The control signals
CLK
Line locked clock of maximal 36 MHz.
This is the system clock. Within the BENDIC the CLK
signal is distributed to the different blocks.
BLN
Blanking NOT signal.
This signal marks the horizontal and vertical blanking and
defines with its rising edge the start phase of the UV 4:1:1
format. A programmable delay of 0, 1, 2 or 3 clock pulses
shifts the internal pulse with respect to the input.
RE1_in
Read enable memory 1 signal.
This signal is generated by the memory controller and its
HIGH state determines the read enable on the first
memory bank, after it is processed by BENDIC for the
ZOOM mode and fine shift of the edges.
RE2_in
Read enable memory 2 signal.
This signal is generated by the memory controller and its
HIGH state determines the read enable on the second
memory bank, including a fine shift of the edges.
note:
RE1_in and RE2_in are processed in the BENDIC to:
· external signals: RE1_out and RE2_out
· RE with correct internal delay to match datapath delays,
is used to define the edges between video and side
panels (grey insertion or pixel repetition).
RSTR
Reset signal
This signal is transferred (asynchronous with CLK) by e. g.
a microprocessor to reset the communication between the
microprocessor and the BENDIC. CLK has to be present
in this case. In a typical application, RSTR is an active
HIGH pulse, issued only in the vertical blanking period.
During RSTR HIGH-state, the ‘feedback_data’ lines are
switched to 3-state, temporarily overruling the mode that
has been set by the microprocessor. By this provision,
RSTR can be used to prevent data collision on the 3-state
databus, e. g. during a power on sequence. Also, this
signal is used to transfer the ‘movie phase detect’ data to
a register that can be read by the microprocessor.
mPCL
Microprocessor interface clock signal
This signal is transferred (asynchronous with CLK) by a
microprocessor (8051, UART mode 0) as communication
clock signal at 1 MHz.
mPDA
Microprocessor interface data signal
This signal is transferred or received (asynchronous with
CLK) by a microprocessor (8051, UART mode 0) as
communication data signal at 1 MBaud, related to mPCL.
Data is valid the rising edge of mPCL.
The external control
The mP interface has the following functions:
· Receive settings from the mP
· Transmit movie phase detect data to the mP
The interface is based on a two wire interface, one for
clock, the other for bidirectional data form. It is compatible
with the 8051 family UART mode 0 interface. The mP is the
master of the communication, it generates the clock
(nominal 12 MHz/12 = 1 MHz), only active when transfer is
done.
The protocol for the communication is:
8 addressbits are sent by the mP (LSB first), if the address
is a write address then 8 databits (LSB first) are sent by the
mP, else (if the address is a read address) 8 databits are
sent by BENDIC.
RSTR is used to reset the phase of the address/data
transfer. The negative going edge of RSTR clears the
address register. After reset the first transmitted bit is to be
taken as the first (LSB) bit of an address.
For field1/field2 selection and for mix/median selection, 4
addresses are used to select each of the four
combinations. A databyte is not obligatory after each of
these four addresses, but a dummy databyte is needed if
the transmission is to be followed by a further one.

APPLICATION NOTE FOR THE ANALOG PART OF BENDIC
The digital to analog conversion is done in parallel for the three channels. The DA converters (8-bit for U and V; 9-bit
for Y) are based on resistor strings with low impedance output buffers. They are designed for 2 Vp-p unloaded output
swing. To avoid integral nonlinearity errors, the minimum output voltage is 200 mV; so the DC range for unloaded output
is between 0.2 and 2.2 V.
A serial resistor of 25 W is integrated at the outputs of the buffers. With 50 W in series - close to the output pins - the
nominal output voltage for 75 W line termination is 1 Vp-p with a DC range of 0.1 to 1.1 V. Amplitude matching to external
requirements has to be done with external dividers. Capacitance load should not exceed 30 pF.
The DAC’s require three separate analog supply voltages VDDA1-3 and analog ground lines VSSA1-3 for the output buffers.
The accuracy of an external voltage reference input VDDA4 directly influences the output amplitude of the video signals.
The current input CUR supplies the output buffers with a current of about 0.3 mA at VDDA = 5 V, if a resistor of 15 kW is
connected to this pin.
A larger current improves the output bandwidth but makes the integral nonlinearity worse.

 

 

LOEWE ARCADA 72-100 PIP (53471L39)  CHASSIS Q2100  (110Q21)  Video signal scan conversion

Abstract:

In a scan conversion method of generating an output video signal from an interlaced input signal, including the steps of furnishing (1) a first signal having first lines (F_i (x-(0, 1)^T, n)) corresponding to original lines of the interlaced input signal, and second lines (F_i (x, n)) in addition to the first lines (F_i (x-(0, 1)^T, n)); and providing (5, 11, 7, 13) a second signal which is delayed or advanced with respect to the first signal, the second signal having first processed lines (F_out (x-(0, 1)^T -D, n-1)) corresponding to the original lines, and second processed lines (F_out (x-D, n-1)) corresponding to the second lines (F_i (x, n)); output lines (F_out (x, n)) of the output video signal are obtained in dependence upon a first difference between the first processed lines (F_out (x-(0, 1)^T -D, n-1)) and the first lines (F_i (x-(0, 1)^T, n)), and a second difference between the second processed lines (F_out (x-D, n-1)) and the second lines (F_i (x, n)).


1. A scan conversion method of generating an output video signal from an interlaced input signal, comprising the steps of:
furnishing a first signal having first lines (F_i (x-(0, 1)^T, n)) corresponding to original lines of said interlaced input signal, and second separate lines (F_i (x, n)) in addition to said first lines (F_i (x-(0, 1)^T, n)); and
providing a second signal which is delayed or advanced with respect to said first signal, said second signal having first processed lines (F_out (x-(0, 1)^T -D, n-1)) corresponding to said original lines, and second processed lines (F_out (x-D, n-1)) corresponding to said second lines (F_i (x, n));
characterized in that output lines (F_out (x, n)) of said output video signal are obtained in dependence upon
a first mixer-generated difference between said first processed lines (F_out (x-(0, 1)^T -D, n-1)) and said first lines (F_i (x-(0, 1)^T, n)), and
a second mixer-generated difference between said second processed lines (F_out (x-D, n-1)) and said second lines (F_i (x, n)).


2. A method as claimed in claim 1, wherein said output video signal is a sequentially scanned video signal, and wherein the method comprises the further step of combining said first signal and said second signal to obtain an output sequentially scanned video signal having first output lines (F_out (x-(0, 1)^T, n)) corresponding to said original lines, and said output lines (F_out (x, n)) between said first output lines (F_out (x-(0, 1)^T, n)).

3. A method as claimed in claim 2, wherein said output lines (F_out (x, n)) of said output video signal are obtained further in dependence upon a relation (k₂) between said first lines (F_i (x-(0, 1)^T, n)) and said first output lines (F_out (x-(0, 1)^T, n)).

4. A method as claimed in claim 1, wherein said first processed lines (F_out (x-(0, 1)^T -D, n-1)) and said second processed lines (F_out (x-D, n-1)) are obtained by means of a motion-compensated interpolation.

5. A method as claimed in claim 2, wherein said output lines are obtained in dependence upon said second difference and a third difference between said first output lines (F_out (x-(0, 1)^T, n)) and said first processed lines (F_out (x-(0, 1)^T -D, n-1)).

6. A method as claimed in claim 2, wherein said combining step is controlled such that a difference between said output lines (F_out (x, n)) and said second processed lines (F_out (x-D, n-1)) corresponds to a difference between said first output lines (F_out (x-(0, 1)^T, n)) and said first processed lines (F_out (x-(0, 1)^T -D, n-1)).

7. A method as claimed in claim 1, wherein said first and second differences are absolute differences.

8. A scan conversion apparatus for generating an output video signal from an interlaced input signal, comprising:
means for furnishing a first signal having first lines (F_i (x-(0, 1)^T, n)) corresponding to original lines of said interlaced input signal, and separate second lines (F_i (x, n)) in addition to said first lines (F_i (x-(0, 1)^T, n)); and
means for providing a second signal which is delayed or advanced with respect to said first signal, said second signal having first processed lines (F_out (x-(0, 1)^T -D, n-1)) corresponding to said original lines, and second processed lines (F_out (x-D, n-1)) corresponding to said second lines (F_i (x, n));
characterized in that said scan conversion apparatus further comprises means for generating output lines (F_out (x, n)) of said output video signal in dependence upon
a first mixer-generated difference between said first processed lines (F_out (x-(0, 1)^T -D, n-1)) and said first lines (F_i (x-(0, 1)^T, n)), and
a second mixer-generated difference between said second processed lines (F_out (x-D, n-1)) and said second lines (F_i (x, n)).


9. An apparatus as claimed in claim 8, wherein said output video signal is a sequentially scanned video signal, and wherein the apparatus further comprises means for combining said first signal and said second signal to obtain an output sequentially scanned video signal having first output lines (F_out (x-(0, 1)^T, n)) corresponding to said original lines, and said output lines (F_out (x, n)) between said first output lines (F_out (x-(0, 1)^T, n)).

10. An apparatus as claimed in claim 9, wherein said output lines (F_out (x, n)) of said output video signal are obtained further in dependence upon a relation (k₂) between said first lines (F_i (x-(0, 1)^T, n)) and said first output lines (F_out (x-(0, 1)^T, n)).

11. An apparatus as claimed in claim 9, wherein said output lines are obtained in dependence upon said second difference and a third difference between said first output lines (F_out (x-(0, 1)^T, n)) and said first processed lines (F_out (x-(0, 1)^T -D, n-1)).

12. An apparatus as claimed in claim 9, wherein said combining means are controlled such that a difference between said output lines (F_out (x, n)) and said second processed lines (F_out (x-D, n-1)) corresponds to a difference between said first output lines (F_out (x-(0, 1)^T, n)) and said first processed lines (F_out (x-(0, 1)^T -D, n-1)).

13. A video signal display apparatus comprising:
means for supplying an interlaced input signal;
a scan conversion apparatus for generating an output video signal from said interlaced input signal, as claimed in claim 8; and
means for displaying (16) said output video signal.

Description:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to a method and apparatus for video signal scan conversion, and to a video signal display apparatus comprising such a conversion apparatus.
2. Description of the Related Art
WO-A-95/27362, corresponding to U.S. Pat. No. 5,532,750 (Attorney's reference PHN 14,794), discloses a method of converting an interlaced video signal into an output sequentially scanned video signal. A first sequentially scanned video signal is furnished in dependence upon the interlaced video signal. Subsequently, a motion-compensated sequentially scanned signal is furnished in dependence upon the first sequentially scanned video signal. All video lines of the output sequentially scanned video signal are generated in dependence upon both the first sequentially scanned video signal and the motion-compensated sequentially scanned signal to prevent inaccuracies in motion vectors used in the motion-compensated processing operation from resulting in visible distortions. The first sequentially scanned video signal and the motion-compensated sequentially scanned signal are combined to furnish the output sequentially scanned video signal by means of a first mixer for first lines positionally corresponding to original lines of a present field of the interlaced video signal, a second mixer for second lines positionally corresponding to interpolated lines between the original lines, and a multiplexer for line-alternately selecting an output of the first mixer or an output of the second mixer.
SUMMARY OF THE INVENTION
It is, inter alia, an object of the invention to provide an improved video signal scan conversion.
Accordingly, a first aspect of the invention provides a method of generating an output video signal from an interlaced input signal, comprising the steps of:
furnishing a first signal having first lines (F _i (x-(0, 1) ^T , n)) corresponding to original lines of the interlaced input signal, and second lines (F _i (x, n)) in addition to the first lines (F _i (x-(0, 1) ^T , n)); and
providing a second signal which is delayed or advanced with respect to the first signal, the second signal having first processed lines (F _out (x-(0, 1) ^T -D, n-1)) corresponding to the original lines, and second processed lines (F _out (x-D, n-1)) corresponding to the second lines (F _i (x, n));
in which output lines (F _out (x, n)) of the output video signal are obtained in dependence upon
a first difference between the first processed lines (F _out (x-(0, 1) ^T -D, n-1)) and the first lines (F _i (x-(0, 1) ^T , n)), and
a second difference between the second processed lines (F _out (x-D, n-1)) and the second lines (F _i (x, n)).
Preferably, the output video signal is a sequentially scanned video signal, and the method comprises the further step of combining the first signal and said second signal to obtain the output sequentially scanned video signal having first output lines (F _out (x-(0, 1) ^T , n)) corresponding to the original lines, and the output lines (F _out (x, n)) between the first output lines (F _out (x-(0, 1) ^T , n)). Advantageously, the output lines (F _out (x, n)) of the output video signal are obtained further in dependence upon a relation between the first lines (F _i (x-(0, 1) ^T , n)) and the first output lines (F _out (x-(0, 1) ^T , n)).
A refinement of the first aspect of the invention provides that the output lines are obtained in dependence upon the second difference and a third difference between the first output lines (F _out (x-(0, 1) ^T , n)) and the first processed lines (F _out (x-(0, 1) ^T -D, n-1)), in which the first difference as well as the relation between the first lines and the first output lines are replaced by a third difference which is equivalent thereto in a preferred embodiment of the invention.
Another refinement of the first aspect of the invention provides that the combining step is controlled such that a difference between the output lines (F _out (x, n)) and the second processed lines (F _out (x-D, n-1)) corresponds to a difference between the first output lines (F _out (x-(0, 1) ^T , n)) and the first processed lines (F _out (x-(0, 1) ^T -D, n-1)). The above-mentioned aspects of the invention improve the consistency along the motion trajectory or, put in other words, a smoother picture is obtained for moving objects.
A second aspect of the invention provides a scan conversion apparatus for generating an output video signal from an interlaced input signal, comprising means for furnishing a first signal having first lines (F _i (x-(0, 1) ^T , n)) corresponding to original lines of said interlaced input signal, and second lines (F _i (x, n)) in addition to said first lines (F _i (x-(0, 1) ^T , n)); and means for providing a second signal which is delayed or advanced with respect to said first signal, said second signal having first processed lines (F _out (x-(0, 1) ^T -D, n-1)) corresponding to said original lines, and second processed lines (F _out (x-D, n-1)) corresponding to said second lines (F _i (x, n)); characterized in that said apparatus further comprises means for generating output lines (F _out (x, n)) of said output video signal in dependence upon a first difference between said first processed lines (F _out (x-(0, 1) ^T -D, n-1)) and said first lines (F _i (x-(0, 1) ^T , n)), and a second difference between said second processed lines (F _out (x-D, n-1)) and said second lines (F _i (x, n)).
A third aspect of the invention provides a video signal display apparatus incorporating such a scan conversion apparatus as described.
BRIEF DESCRIPTION OF THE DRAWINGS
In the drawings:
FIG. 1 illustrates an embodiment of a television receiver comprising a sequential scan converter in accordance with the present invention;
FIG. 2 shows an embodiment of a device for calculating mixer coefficients k1 and k2 for use in the embodiment of FIG. 1; and
FIG. 3 shows an embodiment of a device for calculating the mixer coefficient k1 for use in the embodiment of FIG. 1.
DESCRIPTION OF THE PREFERRED EMBODIMENTS
1. Introduction
De-interlacing is a basic operation required for most video scanning format conversions. Vertical and temporal interpolation of image data cause practical and fundamental difficulties, as the conditions of the sampling theorem are generally not met in video signals. Linear methods, based on sampling rate conversion theory, therefore negatively influence the resolution and/or the motion portrayal. The more advanced algorithms can be characterized by their common attempt to interpolate the 3-D image data in the direction with the highest correlation. To this end, they either have an explicit or implicit detector to find this direction. In case of 1-D temporal interpolation the explicit detector is usually called a motion detector, for 2-D spatial interpolation it is called an edge detector, while the most advanced device estimating the optimal spatio-temporal 3-D interpolation direction is a motion estimator. The interpolation filter can either be recursive or transversal, but the number of taps in the temporal direction is preferably small.
Recently, some papers have been published proposing a recursive scheme for motion compensated sequential scan conversion (References [1] and [2]). Experiments indicate that the recursiveness yields a significant improvement of the motion-compensated median (Reference [3]), on which these algorithms are based, if good quality motion vectors are available. Furthermore, recursiveness is expected to allow an improved performance on critical velocities, compared to recently published methods applying generalized sampling theory (Reference [4]), if the velocities are accelerating. In this application an improved recursive sequential scan conversion algorithm is introduced that suppresses remaining artifacts of the prior art further. The invention provides the algorithms and a novel evaluation method that shows the improvement in an objective score. For high quality, sub-pixel accurate motion estimation the algorithm of (Reference [5]) is used.
2. De-interlacing techniques
In general, the samples required for the motion compensated de-interlacing do not exist in the time discrete input signal, e.g. due to non-integer velocities. In the horizontal domain this problem can be solved with linear Sampling Rate Conversion (SRC) theory, e.g. (Reference [6]), but not in the vertical domain, as the constraints of the sampling theorem are not met. Three different solutions for this problem have been proposed recently in the literature:
(1) A straight extension of the motion vector into earlier pictures until it points (almost) to an existing pixel (Reference [7]).
(2) The application of a generalized sampling theory (GST) (Reference [4]).
(3) Recursive de-interlacing of the signal (Reference [1] and [2]).
Solution (1) is valid only if we assume the velocity constant over a larger temporal instance. This is a rather severe limitation which makes the method practically useless.
The implication of GST is that it is possible to perfectly reconstruct a signal sampled at 1/n times the Nyquist rate with n independent sets of samples that describe the signal. For the de-interlacing problem n=2, and the required two sets are the current field and the motion compensated previous field. If the two do not coincide, i.e., the object does not have an odd vertical motion vector component, the independency constraint is fulfilled, and the problem can theoretically be solved. Practical problems are:
a) The velocity can have an odd vertical component.
b) A perfect reconstruction requires the use of pixels from many lines, for which the velocity needs not be constant.
c) For velocities near the vertical odds, noise may be enhanced.
Solution (3) is based on the assumption that it is possible at some time to have a perfectly de-interlaced picture in a memory. Once this is true, the picture is used to de-interlace the next input field. With motion compensation, this solution can be perfect as the de-interlaced picture in the memory allows the use of SRC-theory also in the vertical domain. If this new de-interlaced field is written in the memory, it can be used to de-interlace the next incoming field etc. Limitations of this method are:
(I) Propagation of errors due to motion vector inaccuracy and interpolation defects
(II) Even a perfectly de-interlaced picture can contain alias in the vertical frequency domain, assuming the common case of a camera without optical pre-filter.
In practice problem (I) is the more serious, particularly for nearly odd vertical velocities and/or noisy input signals.
We concluded that recursive de-interlacing and de-interlacing based on GST are the best methods presently known. However, even these best methods are imperfect. It is our target to present an improvement that can be applied in combination with both methods to suppress the remaining artifacts in the de-interlaced output signal. In fact, our proposal can be used to improve any de-interlacing algorithm.
3. Description of the Applied Algorithms
In Reference [1] a time-recursive de-interlacing algorithm is proposed in which the lines that need to be interpolated are found by motion compensating the previously found de-interlaced output frame: ##EQU1## where F(x, t) is the interlaced input signal, F _out (x, n) the sequential output, n the field number, and x is the spatial position.
To prevent errors from propagating, in Reference [1] several additional measures are described to protect the interpolated lines. Particularly, the median filter is proposed to realize this protection:
Although further alternatives are suggested in Reference [1], we will use this algorithm as the basis for our comparison. ##EQU2##
As we expect the quality of Reference the resulting algorithm to depend heavily on the performance of the motion estimator, we applied the motion estimation method of [5]. This high quality algorithm yields a quarter pixel accuracy, and a close to true-motion vector field which is considered very important for scan rate conversion. Rather than calculating all possible candidate vectors, this recursive search block-matcher takes spatial and/or temporal "prediction vectors" from a 3-D neighborhood, and a single updated prediction vector. This implicitly assumes spatial and/or temporal consistency. The updating process involves update vectors added to either of the spatial prediction vectors. We applied a candidate set CS(X, n), from which the block-matcher selects its result vector, defined by: ##EQU3## where the update vectors U _a (X, n) and U _b (X, n) are alternatingly (on block basis) available, and are taken from a limited fixed integer update set, in our case: ##EQU4## To realize sub-pixel accuracy, the update set of equation (4) is extended with fractional update values. We realized a quarter pixel resolution by adding the following fractional update vectors to the update set: ##EQU5## Because of the small number of candidate vectors, the method is very efficient and realizes, due to the inherent smoothness constraint, very coherent and close to true-motion vector fields, most suitable for scanning format conversion.
4. Recursive de-interlacing algorithm
The main imperfection of the recursive de-interlacing algorithm is remaining alias in the output signal. Although this imperfection is usually worse for alternative methods, further improvement seems attractive. Difficulty with this defect is that it is hardly visible in single images but mainly in moving sequences. This makes it difficult to illustrate, while also quantitative measures to show the improvement seem to lack.
A common method for evaluating the de-interlacing quality is comparing an original sequentially scanned image with a de-interlaced result using a, what we will call here, MSEs-criterion: ##EQU6##
This criterion is not exclusively sensitive for remaining alias, as it sums all differences without discriminating for different backgrounds, e.g., due to resolution losses, noise, vector errors, etc. An additional inconvenience of this criterion is that it cannot be applied to check the performance of the algorithm on original interlaced source signals.
In a perfectly de-interlaced picture (without residual alias), a characteristic is that the sequence is stationary along the motion trajectory, in picture parts for which the motion model is valid. Based upon this characteristic, an alternative was suggested in where we measured how well the current interlaced input field n was predicted by the motion compensated previously de-interlaced field: ##EQU7## This method has the advantage that it can be applied to judge the performance in absence of an original sequentially scanned sequence. However, the measure has limited value in case of critical velocities, as in that case the quality of the interpolated lines is not reflected in the figure.
In an attempt to improve on this aspect, it is possible to measure a "Motion Trajectory Inconsistency" (MTI(n)) for all output lines in field n, which we will define as: ##EQU8## A problem with this measure is that a good score on this criterion is a necessary but not sufficient constraint in the processing. It is possible, e.g. applying a strong temporal filtering, to force this MTI to very low values, while obviously the picture quality is degraded. However, a lower score on the MTI criterion coupled to a hardly varying MSE score is a strong indication for quality improvement. There is a clear analogy with the motion vector smoothness constraint (see Reference [8]), where motion estimation techniques have been improved by adding a smoothness term in the match criterion which yields a significant consistency improvement accepting a slight MSE degradation. Quite similarly, it is possible here to introduce a de-interlacing cost figure defmed as: ##EQU9## The parameter α allows tuning of the cost function to match the subjective impression.
After quantifying "remaining alias" applying equation (9), an improvement of the MTI figure could be realized by suppressing non-stationarities along the motion trajectory. As long as this does not seriously degrades the MSE-score, it brings an improved Cost-score and, with α tuned correctly, also an improved subjective performance.
As non-stationarities can reside on interpolated lines as well as on original lines, the implication would be that both have to be temporally filtered. That filtering of original lines, which is somewhat contra-intuitive, helps to suppress remaining alias can also be understood from the vertical frequency spectrum of the signal on original and interpolated lines respectively. In the original recursive de-interlacing algorithm, the lines existing in the input field are always directly transferred to the output and never modified. As the first repeat spectrum of the interpolated lines will almost always suffer from inaccuracies in the motion vector estimates and the protection features, this spectrum cannot fully compensate for the (anti-phase) repeat spectrum resulting from the original lines.
As a consequence of the above, the recursive de-interlacing method that we propose interpolates not only the new lines, but, in an attempt to maximize the motion trajectory consistency on both type of lines equally strong, also the lines existing in the interlaced signal: F _out (x, n)=k(R).(F _out (x-D(x, n), n-1)+(1-k(R)).(F _i (x, n))(10)
where k(R) is a control parameter that reflects the reliability R of the motion vectors. F _i (x, n) can be calculated according to equation (2) but also, with little disadvantage as we will show later, using a simpler intra-field interpolation: ##EQU10## In the literature, sometimes the match error, or the match error corrected for the local picture contrast is used. When applying the 3-D Recursive Search block-matcher described in Reference [5], another indication for motion vector reliability is available. This recursive estimator, due to the use of spatial and temporal predictions, implicitly assumes consistent motion vector fields. If the output vector field is not smooth than the implicit assumption may be false, and therefore the motion vectors unreliable.
For this smoothness, any sum of absolute (or squared) differences of the current vector with its spatial and temporal neighbors can be applied, but using the 3-D RS block-matcher, we obtained good results using the following definition for the vector smoothness S: ##EQU11## where p=(x, y, t) ^T is the spatio-temporal position, α is a constant selected experimentally, while the neighborhood N in which the neighboring vectors are found defined as: ##EQU12## In this definition X and Y denote the horizontal and vertical block dimensions as used in the motion estimator respectively.
5. Refinements of the Algorithm
The severest drawbacks that were found with the above-described algorithm were:
(1) Large homogeneously moving picture parts occasionally break up into several areas with slightly different velocities (earthquakes).
(2) In areas where large displacement discontinuities occurred, blocking artifacts were sometimes visible. These are due to the reliability indicator being available on block base only.
The first of these difficulties is directly related to the fundament of the proposed method and, therefore, most difficult to cure: by recursively filtering both the original and the interpolated lines, the output becomes more and more "isolated from the input" if the reliability of the motion vectors is considered to be good. In this section, therefore, we introduce a solution to prevent the output pictures from drifting too far from the input material.
The basis for the refinement is to detect directly how far the filtered information on an original line differs from the unfiltered information and to reduce the filtering in case the deviation becomes to large. As this adaptation of the filtering can easily be realized on a pixel base, it further provides a means to cope with the drawback mentioned under number (2). The same difference is used to reduce the filtering of the interpolated lines, albeit that much larger differences turned out to be tolerable.
In the refined algorithm (modification of equation (2) the output luminance is found as: ##EQU13## and using a limiter function "clip" defined as: ##EQU14## k ₂ is calculated as: ##EQU15## Consequently, k ₂ is a function of the vector smoothness S, defined in equation (4), and of the (pixel-) difference, Diff, in the motion compensated recursive loop measured on original lines of the interlaced grid only: ##EQU16## where W is a window containing the six pixels nearest to the currently interpolated pixel on the lines directly above and below the interpolated pixel. As Diff is related to the MSE _i (n) of equation (7), it is possible by appropriately choosing C ₁ , to tune the relative importance of MSE _i (n) and MTI(n).
Although this tuning seems rather straightforward for the original lines, it is more complicated for the interpolated lines. For these lines, an MTI(n) figure can be calculated, but a significant MSE _i (n) cannot be found, as the quality of the input lines to this temporal filter depends on the quality of the initial sequential scan conversion algorithm. To escape from this fundamental problem, we propose here to tune k ₁ such that the contribution of original lines and interpolated lines to the MTI(n) figure is identical per pixel, disregarding the energy over the temporal filter for the interpolated lines. The assumption leads to: ##EQU17## while at the same time: F _out (x, n)=k ₁ F _i (x, n)+(1-k ₁ )F _out (x-D, n-1)(19)
where F _i (x, n) is the output of the initial de-interlacing algorithm, e.g., using equation (2) or (11). Combination of equations (18) and (19), results in a calculation of k ₁ according to: ##EQU18## Combining this result with the lower part of equation (14) results in: ##EQU19## As an implication, the temporal recursive filtering on the interpolated lines depends on the quality of the initial de-interlacing method. A simple line averaging algorithm will cause stronger temporal filtering, of the interpolated lines, than e.g. a motion compensated median filter. Experimentally, we could show that the difference in resulting de-interlacing performance was small.
The assumption of equation (18) leads to an adaptation of temporal recursive filtering on the interpolated line applying differences measured on the upper neighboring original line. Rather than using the upper original line as a reference, the lower neighboring line can be used equally well. For symmetry considerations, the average effect on the two neighboring original lines seems advantageous. Elaborating this results in a symmetrical alternative for equation (20): ##EQU20## with: ##EQU21##
Rather than averaging the absolute differences, it is possible to take the absolute value of the average, the maximum of the two averages, or apply (2-D) spatial filters before and/or after the rectifier (abs). The choices resemble those commonly applied in motion detectors. It is furthermore possible to apply the above control of the temporal filter on the interpolated lines, while fixing the value of k ₂ to no filtering on the original lines (k ₂ =1). Generally, this will lead to somewhat lower MSE _i (n) figures, but a significantly higher MTI(n) score.
In an alternative embodiment, k ₂ is calculated as: ##EQU22## with: Diff(x, n)=abs(F _out (x-D(x, n), n-1)-(F _i (x, n)) (25)
Consequently, k ₂ is a function of the prediction error, Diff, in the motion compensated recursive loop. As Diff is related to the MSE(n) of equation (7), it is possible by appropriately choosing C ₂ , to tune the relative importance of MSE _i (n) and MTI(n).
As the quality of the interpolated pixels, as resulting from the initial de-interlacing method, is obviously less than that of the original pixels, the filtering of these pixels should be stronger. As, furthermore, Diff(x, n), at the position of the interpolated lines, has little value to determine the quality of the motion compensated prediction, we propose to control k ₁ using: ##EQU23## where C ₁ is smaller than C ₂ , and the control of the recursive filter for interpolated pixels is derived from the quality of the motion compensated prediction at the vertically neighboring existing pixels.
There is a risk in filtering alternate lines differently, as it potentially introduces visible line structures. Although the advantage of high quality de-interlacing will be apparent in areas with vertical detail, there is no advantage in regions that lack such high vertical frequency components. Therefore, in order to prevent the introduction of line structure in image parts that never profit from individual filtering, k ₁ is made equal to k ₂ if: ##EQU24##
To evaluate the proposals resulting from the previous section, we selected a set of 4 critical sequences. The sequences contain vertical detail, and motion with various sub-pixel values in many directions. Using the algorithm of Reference [1], in the version described in section 2 as a above reference, we calculated MSEs and MTIs for another two algorithms, illustrating the proposals of this paper. The first algorithm is the one illustrated in FIG. 1, in which the control of the recursive loop is according to equations (24,26). The second algorithm has k ₂ fixed at 1, i.e., no recursive filtering of the original pixels, and is further identical. Compared to the reference algorithm, both proposed new algorithms yield a slightly improved MSE _i figure, which is expected to be mainly due to the elimination of median defects in the high spatial frequencies. The MTI figures, however, have been improved dramatically, particularly for the first algorithm, i.e., the algorithm that performs recursive filtering even on the original lines. MSE _i figures of both algorithm differ only little. The additional recursive filtering of the original pixels mainly improves the MTI figure (with little or no disadvantage for the MSE _i figure).
FIG. 1 shows the resulting architecture of the proposed de-interlacing algorithm. In FIG. 1, an interlaced input signal is applied from an input I to an initial sequential scan converter 1 which supplies original lines at its lower output and interpolated lines at its upper output. The original lines are applied to a motion compensation stage 7 thru a mixer 3 and a field memory 5. Similarly, the interpolated lines are applied to the motion compensation stage 7 thru a mixer 9 and a field memory 11. Motion vectors D for the motion compensation stage 7 are determined by a motion estimator 13 on the basis of the original lines supplied by the initial sequential scan converter 1 (or on the basis of the lines supplied by the mixer 3), and shifted lines supplied by the motion compensation stage 7. Motion compensated shifted lines are supplied by the motion compensation stage 7 to the mixers 3 and 9. The mixer 3 mixes the original lines and the motion compensated shifted lines in the ratio k2: (1-k2). The mixer 9 mixes the interpolated lines from the initial sequential scan converter 1 and the motion compensated shifted lines in the ratio k1:(1-k1). Output signals from the mixers 3 and 9 are applied to a compress and multiplex stage 15 to generate a de-interlaced output signal, which is displayed on a display unit 16.
While this embodiment largely corresponds to that described in WO-A-95/27362 (Attorney's reference PHN 14,794), the present invention is mainly concerned with providing optimal values for k1 (and k2). To this end, FIG. 2 shows an embodiment of a device for calculating the mixer coefficients k1 and k2 for use in the embodiment of FIG. 1. The mixer coefficients calculating device of FIG. 2 contains a first calculation circuit 17 for calculating a vector smoothness S in response to the motion vectors D in accordance with equations 12, 13, and a second calculation circuit 19 for calculating the mixing factors k1 and k2 in dependence upon the four signals applied to the mixers 3 and 9 in accordance with equations 14 thru 23.
FIG. 3 shows an embodiment of a device for calculating the mixer coefficient k1 for use in the embodiment of FIG. 1. The mixer coefficient k2 has a fixed value of 1. The mixer coefficient k1 is calculated in accordance with equation 20 by a calculating device 20.
6. Conclusion
A generally applicable improvement to existing de-interlacing algorithms and a new evaluation measure for such algorithms have been proposed in this application. A motion-compensated temporal recursive filtering is used. A typical feature of the proposal is that this filtering is not limited to the interpolated pixels only, but is extended to the filtering of the pixels existing in the interlaced input signal. This somewhat contra-intuitive action followed from the assumption that in order to have the repeat spectra of original lines compensated by that of the interpolated ones, it is essential that the two have identical frequency response. As it cannot be prevented that of the interpolated pixels may be distorted by the limited accuracy of the applied motion vectors, a similar distortion can best be applied to that of the original pixels in order to maximally suppress alias. The application of the improvement to time-recursive de-interlacing was elaborated and the improved performance was verified. The verification has to be understood in a sense that the classical MSE _i performance measure had not suffered (in fact, even showed some improvement), whereas the new proposed "consistency along the motion trajectory" (MTI) had greatly improved.
In a preferred embodiment, the invention provides a method of sequential scan conversion which uses a recursive temporal filtering of at least the interpolated lines, in which the filter is controlled by locally giving a resulting consistency along the motion trajectory a fixed relation (e.g. 1), to the values determined for adjacent lines.
It should be noted that the above-mentioned embodiments illustrate rather than limit the invention, and that those skilled in the art will be able to design many alternative embodiments without departing from the scope of the appended claims. While absolute differences are described, in some embodiments, normal differences are used to preserve the sign of the difference. FIG. 1 shows a recursive embodiment, in which the outputs of the mixers 3, 9 are applied to the motion-compensation stage 7 thru the field memories 5, 11; of course, a non-recursive embodiment in which the inputs of the field memories 5, 11 are directly connected to the outputs of the initial sequential scan convertor 1 is also possible. In FIG. 1, the interpolated lines supplied by the initial sequential scan convertor 1 may be just white, black or grey lines; if an interpolation algorithm is used to obtain the interpolated lines, any algorithm will do. In the claims, any reference signs placed between parentheses shall not be construed as limiting the claim. The invention can be implemented by means of hardware comprising several distinct elements, and by means of a suitably programmed computer.
Accordingly, a preferred embodiment of the invention provides a method of generating a sequentially scanned video signal from an interlaced input signal, comprising the steps of: furnishing a first signal having first lines (F _i (x-(0, 1) ^T , n)) corresponding to original lines of the interlaced input signal, and second lines (F _i (x, n)) in addition to the first lines (F _i (x-(0, 1) ^T , n)); and
providing a second signal having first motion-compensated lines (F _out (x-(0, 1) ^T -D, n-1)) corresponding to the original lines, and second motion-compensated lines (F _out (x-D, n-1)) corresponding to the second lines (F _i (x, n));
combining the first signal and the motion-compensated signal to obtain an output sequentially scanned video signal having first output lines (F _out (x-(0, 1) ^T , n)) corresponding to the original lines, and second output lines (F _out (x, n)) between the first output lines (F _out (x-(0, 1) ^T , n));
wherein the second output lines (F _out (x, n)) are obtained in dependence upon (see equations 21 and 27):
a first difference between the first motion-compensated lines (F _out (x-(0, 1) ^T -D, n-1)) and the first lines (F _i (x-(0, 1) ^T , n)),
a second difference between the second motion-compensated lines (F _out (x-D, n-1)) and the second lines (F _i (x, n)), and
a relation (k ₂ ) between the first lines (F _i (x-(0, 1) ^T , n)) and the first output lines (F _out (x-(0, 1) ^T , n)).
However, it is not necessary that the output video signal is a sequentially scanned video signal, as the invention can advantageously be used to derive an output interlaced signal having its output lines vertically positioned between the lines of the input interlaced signal. Such an interlaced-to-interlaced conversion is needed in 100 Hz conversion, where the lines one of the input interlaced fields need to be vertically shifted towards the positions of the lines of the other input interlaced field. The combining step is advantageous in a sequential scan conversion, but not necessary in other scan conversions.
Also, while the second signal is preferably obtained by means of a motion-compensated interpolation, satisfactory results can already be obtained when a less complex method is used to obtain a second signal which is delayed or advanced with respect to the first signal, like one which uses a median filter.
Finally, the dependence on the relation (k ₂ ) between the first lines and the first output lines appeared to contribute to an improved result, while good results were already obtained when the output lines were dependent only on the first and second differences.
The invention can advantageously be applied in a video signal display apparatus like a television receiver or a personal computer.
7. References
[1] F. M. Wang, D. Anastassiou, and A. N. Netravali, `Time-Recursive Deinterlacing for IDTV and Pyramid Coding`, Signal processing: Image Communication 2, Elsevier 1990, pp. 365-374.
[2] Kwon, Seo, Kim, and Kim, `A Motion Adaptive De-Interlacing Method`, IEEE Transactions on Consumer Electronics, Vol. 38, No.3, 1992.
[3] G. de Haan and G. F. M. De Poortere, `Method and apparatus for processing a picture signal`, EP-A-0,474,287.
[4] P. Delogne, L. Cuverlier, B. Maison, B. Van Caillie, and L. Vandendorpe, "Improved Interpolation, Motion Estimation, and Compensation for Interlaced Pictures", IEEE Transactions on Image Processing, Vol. 3, No. 5, September 1994.
[5] G. de Haan, and P. W. A. C. Biezen, `Sub-pixel motion estimation with 3-D recursive search block-matching`, Signal Processing: Image Communication 6 (1994), pp. 229-239.
[6] A. W. M. van den Enden and N. A. M. Verhoeckx, Discrete-time signal processing, Prentice Hall (ISBN 0-13-216763-8), pp. 233-.
[7] J. W. Woods and S. C. Han, "Hierarchical Motion Compensated De-interlacing", Proc. SPIE Visual Communication and Image Processing VI, Boston, November 1991.
[8] G. de Haan, P. W. A. C Biezen, H. Huijgen, and O. A. Ojo, "True Motion Estimation with 3-D Recursive Search Block-Matching", IEEE Transactions on Circuits & Systems for Video Technology, Vol. 3, October 1993, pp. 368-388.

PHILIPS TDA4780 RGB video processor with automatic cut-off control and gamma adjust

 GENERAL DESCRIPTION The TDA4780 is a monolithic integrated circuit with a luminance and a colour difference interface for video processing in TV receivers. Its primary function is to process the luminance and colour difference signals from a colour decoder which is equipped e.g. with the multistandard decoder TDA4655 or TDA9160 plus delay line TDA4661 or TDA4665 and the Picture Signal Improvement (PSI) IC TDA467X or from a feature module. The required input signals are: · Luminance and negative colour difference signals · 2 or 3-level sandcastle pulse for internal timing pulse generation · I2C-bus data and clock signals. Two sets of analog RGB colour signals can also be inserted, e.g. one from a peritelevision connector (SCART plug) and the other one from an On-Screen Display (OSD) generator. The TDA4780 has I2C-bus control of all parameters and functions with automatic cut-off control of the picture tube cathode currents. It provides RGB output signals for the video output stages. In clamped output mode it can also be used as an RGB source. The main differences with the sister type TDA4680 are: · Additional features, namely gamma adjust, adaptive black, blue stretch and two different peak drive limiters · The measurement lines are triggered by the trailing edge of the vertical component of the sandcastle pulse · I2C-bus receiver only. Automatic white level control is not provided; the white levels are determined directly by the I2C-bus data. · The TDA4780 is pin compatible (except pin 18) with the TDA4680. The I2C-bus slave address can be used for both ICs. When a function of the TDA4780 is not included in the TDA4680, the I2C-bus command is not executed. Special commands (except control bit FSWL) for the TDA4680 will be ignored by the TDA4780. FEATURES · Gamma adjust · Dynamic black control (adaptive black) · All input signals clamped on black-levels · Automatic cut-off control, alternative: output clamping on fixed levels · Three adjustable reference voltage levels via I2C-bus for automatic cut-off control · Luminance/colour difference interface · Two luminance input levels allowed · Two RGB interfaces controlled by either fast switches or by I2C-bus · Two peak drive limiters, selection via I2C-bus · Blue stretch, selection via I2C-bus · Luminance output for scan velocity modulation (SCAVEM) · Extra luminance output; same pin can be used as hue control output e.g. for the TDA4650 and TDA4655 · Non standard operations like 50 Hz/32 kHz are also possible · Either 2 or 3 level sandcastle pulse applicable · High bandwidth for 32 kHz application · White point adjusts via I2C-bus · Average beam current and improved peak drive limiting · Two switch-on delays to prevent discoloration during start-up · All functions and features programmable via I2C-bus · PAL/SECAM or NTSC matrix selection. Automatic cut-off control During leakage measurement time the leakage current is compensated in order to get a reference voltage at the cut-off measurement info pin. This compensation value is stored in an external capacitor. During cut-off current measurement times for the R, G and B channels, the voltage at this pin is compared with the reference voltage, which is individually adjustable via I2C-bus for each colour channel. The control voltages that are derived in this way are stored in the external feedback capacitors. Shift stages add these voltages to the corresponding output signals. The automatic cut-off control may be disabled via the I2C-bus. In this mode the output voltage is clamped to 2.5 V. Clamping periods are the same as the cut-off measurement periods. 

 

Signal limiting The TDA4780 provides two kinds of signal limiting. First, an average beam limiting, that reduces signal level if a certain average is exceeded. Second, a peak drive limiting, that is activated if one of the RGB signals even shortly exceeds a via I2C-bus adjusted threshold. 

 

The latter can be either referred to the cut-off measurement level of the outputs or to ground. When signal limiting occurs, contrast is reduced, and at minimum contrast brightness is reduced additionally. Sandcastle decoder and timer A 3-level detector separates the sandcastle pulse into combined line and field pulses, line pulses, and clamping pulses. 

The timer contains a line counter and controls the cut-off control measurement. Application with a 2-level 5 V sandcastle pulse is possible. 

 

Switch on delay circuit After switch on all signals are blanked and a warm up test pulse is fed to the outputs during the cut-off measurement lines. If the voltage at the cut-off measurement input exceeds an internal level the cut-off control is enabled but the signal remains still blanked. In the event of output clamping, the cut-off control is disabled and the switch on procedure will be skipped. Y output and hue adjust 

 

 

The TDA4780 contains a D/A converter for hue adjust. The analog information can be fed, e.g. to the multistandard decoder TDA4650 or TDA4655. This output pin may be switched to a Y output signal, which can be used for scan velocity modulation (SCAVEM). The Y output is the Y input signal or the matrixed (RGB) input signal according to the switch position of the fast switch. I2C-bus The TDA4780 contains an I2C-bus receiver for control function.

 

 ESD protection The Pins are provided with protection diodes against ground and supply voltage (see Chapter “Internal pin configurations”). I2C-bus input pins do not shunt the I2C-bus signals in the event of missing supply voltage. Notes to the characteristics 1. RGB signals controlled by saturation, adaptive black, contrast and brightness. Gamma affects the Y component of the internal RGB signals. 2. Adaptive black control acts on Y signal, which is either Y input or Y output from RGB matrix. Negative set-up is not affected. The level shift value is determined by the peak dark detector, operation selected by control bit ADBL. The peak dark detector is inactive during blanking. Peak dark detector activated by internal line counter, which starts after the end of the vertical blank of the sandcastle. 

 

Active from line 16 (after end of vertical sandcastle) to line 224 (NTSC mode, NMEN = 1) or line 272 (PAL mode, NMEN = 0). It is recommended to increase the contrast value (subaddress 02H) by 15% if ADBL = 1. The line numbers are doubled if control bit HDTV = 1. 3. At minimum gamma (3FH) any differences in black level steps are amplified by 6 dB. 4. For nominal saturation the range of values is: a) 1FH is the minimum value that can be used b) 20H is the typical value that can be used c) 21H is the maximum value that can be used. 5. For nominal contrast the range of values is: a) 20H is the minimum value that can be used b) 22H is the typical value that can be used c) 24H is the maximum value that can be used. 6. . For meaning of actual nominal signal see chapter “Characteristics”. 7. Series resistor in supply voltage should be less than 0.3 W. 8. At 1.0 V cut-off measurement level the function of the cut-off control loop is not guaranteed because the blanking level is limited to the minimum output voltage.

 

 For proper working a guide number for the minimum cut-off measurement level is 1.3 V. 9. 

For nominal AC gain settings the range of values is: a) 21H is the minimum value that can be used b) 22H is the typical value that can be used c) 23H is the maximum value that can be used. 10. . For meaning of actual nominal signal see chapter “Characteristics”. 11. Sandcastle pulse detector (pin 14) The sandcastle pulse is compared with 3 (control bit SC5 = 0) or 2 (SC5 = 1) internal threshold levels to separate the various pulses; the internal pulses are generated while the input is higher than the thresholds. The thresholds are independent of supply voltage and temperature. 12. 

Blanking to ultra black level occurs during time DG except MR in R-channel, MG in G-channel, MB in B-channel (see Fig.10). a) Leakage current measuring time: LM will start after the end of vertical sandcastle (see Fig.10). b) Vertical blanking period and cut-off measurement lines (see Fig.10): The vertical component will be identified if it contains 2 or more burst key pulses in the event of SC5 = 1 or two or more line pulses (H) in the event of SC5 = 0. The line counter is triggered by the leading edge. The blanking time is valid for a vertical pulse detected by the sandcastle decoder.

 The internal blank pulse is OR gated with the sandcastle vertical pulse and the end of the measurement pulses. c) Insertion time: full line period. d) Measurement time: line period minus horizontal period (50/60 Hz). e) Line sequence of measuring lines (see Fig.10): First line after end of horizontal pulse which followed the end of vertical pulse: leakage measurement LM First line after leakage measurement pulse: red measurement MR Second line after leakage measurement pulse: green measurement MG Third line after leakage measurement pulse: blue measurement MB. 13. Y output can be switched to hue adjust output via I2C-bus control bit YEXH. Output without sync pulse. Recommendation: Hue adjust DAC set to 3FH. Black level adjustable via hue adjust DAC. 14. Output can be switched to Y output via I2C-bus control bit YEXH (via I2C-bus, resolution 6-bit, bus subaddress 03H).

 

PHILIPS  TDA9141 PAL/NTSC/SECAM processor decoder/sync

GENERAL DESCRIPTION
The TDA9141 is an I2C-bus controlled, alignment-free PAL/NTSC/SECAM decoder/sync processor. The TDA9141 has been designed for use with baseband chrominance delay lines, and has a combined subcarrier frequency/comb filter enable signal for communication with a PAL comb filter. The IC can process CVBS signals and Y/C input signals. The input signal is available on an output pin, in the event of a Y/C signal, it is added into a CVBS signal. The sync processor provides a two-level sandcastle, a horizontal pulse (CLP or HA pulse, bus selectable) and a vertical (VA) pulse. When the HA pulse is selected a line-locked clock (LLC) signal is available at the output port pin. A fast switch can select either the internal Y signal with the UV input signals, or YUV signals made of the RGB input signals. The RGB input signals can be clamped with either the internal or an external clamping signal (search tuning mode). Two pins with an input/output port and an output port of the I2C-bus are available. The I2C-bus address of the TDA9141 is hardware programmable.

FEATURES
• Multistandard PAL, NTSC and SECAM
• I2C-bus controlled
• I2C-bus addresses can be selected by hardware
• Alignment free
• Few external components
• Designed for use with baseband delay lines
• Integrated video filters
• CVBS or YC input with automatic detection
• CVBS output
• Vertical divider system
• Two-level sandcastle signal
• VA synchronization pulse (3-state)
• HA synchronization pulse or clamping pulse CLP
input/output
• Line-locked clock output or stand-alone I2C-bus output
port
• Stand-alone I2C-bus input/output port
• Colour matrix and fast YUV switch
• Comb filter enable input/output with subcarrier
frequency.


FUNCTIONAL DESCRIPTION
General
The TDA9141 is an I2C-bus controlled, alignment-free PAL/NTSC/SECAM colour decoder/sync processor which has been designed for use with baseband chrominance delay lines. In the standard operating mode the I2C-bus address is 8A. If the address input is connected to the positive rail the address will change to 8E. Input switch WARNING: THE VOLTAGE ON THE CHROMINANCE PIN MUST NEVER EXCEED 5.5 V. IF IT DOES THE IC ENTERS A TEST MODE. The TDA9141 has a two pin input for CVBS or YC signals which can be selected via the I2C-bus. The input selector also has a position in which it automatically detects whether a CVBS or YC signal is on the input. In this input selector position, standard identification first takes place on an added Y/CVBS and C input signal. After that, both chrominance signal input amplitudes are checked once and the input with the strongest chrominance burst signal is selected. The input switch status is read out by the I2C-bus via output bit YC. CVBS output In the standard operating mode with the I2C-bus address 8A, a CVBS output signal is available on the address pin, which represents either the CVBS input signal or the Y/C input signal, added into a CVBS signal RGB colour matrix WARNING: THE VOLTAGE ON THE UIN PIN MUST NEVER EXCEED 5.5 V. IF IT DOES THE IC ENTERS A TEST MODE. The TDA9141 has a colour matrix to convert RGB input signals into YUV signals. A fast switch, controlled by the signal on pin F and enabled by the I2C-bus via EFS (enable fast switch), can select between these YUV signals and the YUV signals of the decoder. The Y signal is internally connected to the switch. The −(R−Y) and −(B−Y) output signals of the decoder have to first be delayed in external baseband chrominance delay lines. The outputs of the delay lines must be connected to the UV input pins. If the RGB signals are not synchronous with the selected decoder input signal, clamping of the RGB input signals is possible by I2C-bus selection of STM (search tuning mode), EFS and by feeding an external clamping signal to the CLP pin. Also in search tuning mode the VA output will be in a high impedance OFF-state. Standard identification The standards which the TDA9141 can decode are dependent on the choice of external crystals. If a 4.4 MHz and a 3.6 MHz crystal are used then SECAM, PAL 4.4/3.6 and NTSC 4.4/3.6 can be decoded. If two 3.6 MHz crystals are used then only PAL 3.6 and NTSC 3.6 can be decoded. Which 3.6 MHz standards can be decoded is dependent on the exact frequencies of the 3.6 MHz crystals. In an application where not all standards are required only one crystal is sufficient (in this instance the crystal must be connected to the reference crystal input (pin 30)). If a 4.4 MHz crystal is used it must always be connected to pin 30. Both crystals are used to provide a reference for the filters and the horizontal PLL, however, only the reference crystal is used to provide a reference for the SECAM demodulator. To enable the calibrating circuits to be adjusted exactly two bits from I2C-bus sub address 00 are used to indicate which crystals are connected to the IC. The standard identification circuit is a digital circuit without external components; the search loop is illustrated in Fig.3. The decoder (via the I2C-bus) can be forced to decode either SECAM or PAL/NTSC (but not PAL or NTSC). Crystal selection can also be forced. Information concerning which standard and which crystal have been selected and whether the colour killer is ON or OFF is provided by the read out. Using the forced-mode does not affect the search loop, it does, however, prevent the decoder from reaching or staying in an unwanted state. The identification circuit skips impossible standards (e.g. SECAM when no 4.4 MHz crystal is fitted) and illegal standards (e.g. is forced mode). To reduce the risk of wrong identification PAL has priority over SECAM (only line identification is used for SECAM). Integrated filters All filters, including the luminance delay line, are an integral part of the IC. The filters are gyrator-capacitor type filters. The resonant frequency of the filters is controlled by a circuit that uses the active crystal to tune the SECAM Cloche filter during the vertical flyback time. The remaining filters and the luminance delay line are matched to this filter. The filters can be switched to either 4.43 MHz, 4.28 MHz or 3.58 MHz irrespective of the frequency of the active crystal. The switching is controlled by the identification circuit. In YC mode the chrominance notch filter is bypassed, to preserve full signal bandwidth. For a CVBS signal the chrominance notch filter can be bypassed by I2C-bus selection of TB (trap bypass). The luminance delay line delivers the Y signal to the output 60 ns after the −(R−Y) and −(B−Y) signals have arrived at their outputs.

This compensates for the delay of the external chrominance delay lines. Colour decoder The PAL/NTSC demodulator employs an oscillator that can operate with either crystal (3.6 or 4.4 MHz). If the I2C-bus indicates that only one crystal is connected it will always connect to the crystal on the reference crystal input (pin 30). The Hue signal, which is adjustable via the I2C-bus, is gated during the burst for NTSC signals. The SECAM demodulator is an auto-calibrating PLL demodulator which has two references. The reference crystal, to force the PLL to the desired free-running frequency and the bandgap reference, to obtain the correct absolute value of the output signal. The VCO of the PLL is calibrated during each vertical blanking period, when the IC is in search mode or SECAM mode. If the reference crystal is not 4.4 MHz the decoder will not produce the correct SECAM signals. The frequency of the active crystal is fed to the Fscomb output, which can be connected to an external comb filter IC. The DC value on this pin contains the comb enable information. Comb enable is true when bus bit ECMB is HIGH. If ECMB is LOW, the subcarrier frequency is suppressed. The external comb filter can force the DC value of Fscomb LOW, as pin Fscomb also acts as input pin. In this event the subcarrier frequency is still present. If the DC value of Fscomb is HIGH, the input switch is always forced in Y/C mode, indicated by bus bit YC. Sync processor (φ1 loop) The main part of the sync circuit is a 432 × fH (6.75 MHz) oscillator the frequency of which is divided by 432 to lock the Phase 1 loop to the incoming signal. The time constant of the loop can be forced by the I2C-bus (fast or slow). If required the IC can select the time constant, depending on the noise content of the input signal and whether the loop is phase-locked or not (medium or slow). The free-running frequency of the oscillator is determined by a digital control circuit that is locked to the active crystal. When a power-on-reset pulse is detected the frequency of the oscillator is switched to a frequency greater than 6.75 MHz to protect the horizontal output transistor. The oscillator frequency is reset to 6.75 MHz when the crystal indication bits have been loaded into the IC. To ensure that this procedure does not fail it is absolutely necessary to send subaddress 00 before subaddress 01. Subaddress 00 contains the crystal indication bits and when subaddress 01 is received the line oscillator calibration will be initiated (for the start-up procedure after power-on reset detection see the I2C-bus protocol. The calibration is terminated when the oscillator frequency reaches 6.75 MHz. The oscillator is again calibrated when an out-of-lock condition with the input signal is detected by the coincidence detector. Again the calibration will be terminated when the oscillator frequency reaches 6.75 MHz. The Phase 1 loop can be opened using the I2C-bus. This is to facilitate On Screen Display (OSD) information. If there is no input signal or a very noisy input signal the phase 1 loop can be opened to provide a stable line frequency and thus a stable picture. The sync part also delivers a two-level sandcastle signal, which provides a combined horizontal and vertical blanking signal and a clamping pulse for the display section of the TV. Vertical divider system The vertical divider system has a fully integrated vertical sync separator. The divider can accommodate both 50 and 60 Hz systems; it can either locate the field frequency automatically or it can be forced to the desired system via the I2C-bus. A block diagram of the vertical divider system is illustrated in Fig.4. The divider system operates at twice the horizontal line frequency. The line counter receives enable pulses at this line frequency, thereby counting two pulses per line. A state diagram of the controller is illustrated in Fig.5. Because it is symmetrical only the right hand part will be described. Depending on the previously found field frequency, the controller will be in one of the COUNT states. When the line counter has counted 488 pulses (i.e. 244 lines of the video input signal) the controller will move to the next state depending on the output of the norm counter. This can be either NORM, NEAR_NORM or NO_NORM depending on the position of the vertical sync pulse in the previous fields. When the controller is in the NORM state it generates the vertical sync pulse (VSP) automatically and then, when the line counter is at LC = 626, moves to the WAIT state. In this condition it waits for the next pulse of the double line frequency signal and then moves to the COUNT state of the current field frequency. When the controller returns to the COUNT state the line counter will be reset half a line after the start of the vertical sync pulse of the video input signal.

When the controller is in the NEAR_NORM state it will move to the COUNT state if it detects the vertical sync pulse within the NEAR_NORM window (i.e. 622 < LC < 628). If no vertical sync pulse is detected, the controller will move back to the COUNT state when the line counter reaches LC = 628. The line counter will then be reset. When the controller is in the NO_NORM state it will move to the COUNT state when it detects a vertical sync pulse and reset the line counter. If a vertical sync pulse is not detected before LC = 722 (if the Phase 1 loop is locked in forced mode) it will move to the COUNT state and reset the line counter. If the Phase 1 loop is not locked the controller will move back to the COUNT state when LC = 628. The forced mode option keeps the controller in either the left-hand side (60 Hz) or the right-hand side (50 Hz) of the state diagram. Figure 6 illustrates the state diagram of the norm counter which is an up/down counter that counts up if it finds a vertical sync pulse within the selected window. In the NEAR_NORM and NORM states the first correct vertical sync pulse after one or more incorrect vertical sync pulses is processed as an incorrect pulse. This procedure prevents the system from staying in the NEAR_NORM or NORM state if the vertical sync pulse is correct in the first field and incorrect in the second field. If no vertical sync pulse is found in the selected window this will always result in a down pulse for the norm counter. Output port and input/output port Two stand-alone ports are available for external use. These ports are I2C-bus controlled, the output port by bus bit OPB and the input/output port by bus bit OPA. Bus bit OPA is an open-drain output, to enable input port functioning. The pin status is read out by bus via output bit IP. Sandcastle Figure 7 illustrates the timing of the acquisition sandcastle (ASC) and the VA pulse with respect to the input signal. The sandcastle signal is in accordance with the 2-level 5 V sandcastle format. An external vertical guard current can overrule the sink current to enable blanking purposes.

 

 

PHILIPS TDA4661 Baseband delay line

FEATURES
· Two comb filters, using the switched-capacitor
technique, for one line delay time (64 ms)
· Adjustment-free application
· No crosstalk between SECAM colour carriers (diaphoty)
· Handles negative or positive colour-difference input
signals
· Clamping of AC-coupled input signals (±(R-Y) and
±(B-Y))
· VCO without external components
· 3 MHz internal clock signal derived from a 6 MHz CCO,
line-locked by the sandcastle pulse (64 ms line)
· Sample-and-hold circuits and low-pass filters to
suppress the 3 MHz clock signal
· Addition of delayed and non-delayed output signals
· Output buffer amplifiers
· Comb filtering functions for NTSC colour-difference
signals to suppress cross-colour.

GENERAL DESCRIPTION
The TDA4661 is an integrated baseband delay line circuit
with one line delay. It is suitable for decoders with
colour-difference signal outputs ±(R-Y) and ±(B-Y).

 

 

 

LOEWE ARCADA 72-100 PIP (53471L39)  CHASSIS Q2100  (110Q21) Switched-mode power supply control circuit: Siemens Function and Application of the Switch Mode Powersupply IC TDA4605;

 A controller for a switch mode power supply includes an undervoltage protection circuit responsive to an input supply voltage indicative signal. The input supply voltage indicative signal is also coupled to a foldback point correction circuit. The correction circuit causes a decrease in a maximum duty cycle of a control signal when the input supply voltage increases and is still smaller than a predetermined magnitude. A zener diode limits the input supply voltage indicative signal in a manner to prevent a further decrease in the duty cycle when the input supply voltage exceeds the predetermined magnitude.

 1. A switch mode power supply, comprising: a source of an input supply voltage;
a switch responsive to a first control signal having a controllable duty cycle and coupled to said source of input supply voltage for generating an output supply voltage, in accordance with said duty cycle of said first control signal;
a duty cycle modulator responsive to a second control signal for generating said first control signal and for controlling said duty cycle of said first control signal in accordance therewith, said modulator being responsive to a signal that is indicative of said input supply voltage for decreasing said duty cycle when said input supply voltage increases; and
a limiter coupled to said modulator for limiting the decrease in duty cycle, for a given increase in said input supply voltage, when said input supply voltage exceeds a first magnitude.


2. A power supply according to claim 1, wherein said duty cycle of said first control signal varies within a control range, in accordance with said second control signal, and wherein said limiter limits a decrease of said duty cycle when said duty cycle is at an end of said control range.

3. A power supply according to claim 1, wherein said limiter comprises a clamper coupled in a signal path of said input supply voltage indicative signal for clamping said input voltage indicative signal, when said input supply voltage exceeds said first magnitude, and for disabling the clamping thereof, when said input supply voltage does not exceed said first magnitude.

4. A power supply according to claim 3, wherein said voltage clamper comprises a diode.

5. A power supply according to claim 3, further comprising a disabling circuit responsive to said input supply voltage indicative signal for disabling said output supply voltage, when said input supply voltage is smaller than a second magnitude and wherein said voltage clamper is coupled in a common signal path of said input supply voltage indicative signal with respect to each of an input of said disabling circuit and an input of said limiter.

6. A power supply according to claim 1, wherein said modulator comprises a foldback point corrector for decreasing said duty cycle, when said input supply voltage increases and wherein said limiter is coupled to said corrector.

7. A power supply according to claim 1, wherein said second control signal is produced in a feedback path for regulating said output supply voltage.

8. A power supply according to claim 1, wherein said input supply voltage indicative signal is coupled to said modulator from said source of input supply voltage via a signal path that bypasses said switch.

9. A power supply according to claim 8, wherein said limiter comprises a clamp coupled in said signal path for clamping said input supply voltage indicative signal, when said input supply voltage exceeds said first magnitude, and for disabling the clamping operation, when said input supply voltage does not exceed said first magnitude.

10. A power supply, comprising: an input supply voltage, a transformer and a switch coupled for switch mode generation of a regulated output supply voltage, said switch being responsive to a first control signal having a controllable duty cycle;
a duty cycle modulator for generating said first control signal responsive to a second control signal for limiting a duty cycle of said switch, said modulator operating in a first mode when said second control signal is in a predetermined range of voltage levels and operating in a second mode when said second control signal is outside of said range; and
a voltage monitor circuit for generating said second control signal, said second control signal representing a first proportion of said input supply voltage in a first range of input supply voltage values and a second proportion of said input supply voltage in a second range of input supply voltage values.


11. A power supply according to claim 10 wherein said voltage monitor circuit comprises a clamp coupled in a signal path of said second control signal.

12. A power supply according to claim 11, wherein said second signal is coupled to said modulator from said input supply voltage via a signal path that bypasses said switch.

13. A power supply, comprising: an input supply voltage, a transformer and a switch coupled for switch mode generation of a regulated output supply voltage, said switch being responsive to a first control signal having a controllable duty cycle;
a duty cycle modulator for generating said first control signal responsive to a second control signal, said modulator operating in a first mode when said second control signal is in a predetermined range of voltage levels and operating in a second mode when said second control signal is outside of said range; and
a voltage monitor circuit for generating said second control signal, said second control signal representing a first proportion of said input supply voltage in a first range of input supply voltage values and a second proportion of said input supply voltage in a second range of input supply voltage values, such that as long as said input supply voltage is in said first range of input supply voltage values, said second control signal varies when said input supply voltage varies and said modulator operates in said first mode of operation.


14. A power supply, comprising: an input supply voltage, a transformer and a switch coupled for switch mode generation of a regulated output supply voltage, said switch being responsive to a first control signal having a controllable duty cycle;
a duty cycle modulator for generating said first control signal responsive to a second control signal, said modulator operating in a first mode when said second control signal is in a predetermined range of voltage levels and operating in a second mode when said second control signal is outside of said range; and
a nonlinear voltage divider circuit coupled to said input supply voltage for generating said second control signal, said second control signal representing a first proportion of said input supply voltage in a first range of input supply voltage values and a second proportion of said input supply voltage in a second range of input supply voltage values.

Description:

The invention relates to a switch mode power supply control circuit.
Switched-mode power supplies efficiently generate a variety of regulated voltages from a single line voltage level (e.g., 220 volts AC). One important use of these power supplies is within a television signal receiver where they are used to produce a regulated B+ voltage for the horizontal deflection circuit as well as other regulated voltages for powering various digital and analog circuits.
Typically, a switched-mode power supply contains a full-wave rectifier, a power supply controller, a switch, and an output transformer. The switch is typically a high-power transistor such as a MOSFET. To regulate the output voltages, the controller activates and deactivates (e.g., pulse width modulates) the gate of the transistor in response to power supply loading and other control parameters. The switched voltage from the transistor drives a primary winding of the transformer, while various power supply loads are connected to one or more secondary windings. As such, the power supply converts an AC input voltage into one or more DC voltages.
One particular controller is an integrated circuit available from Siemens as Model TDA 4605. This power supply controller is typically used to drive the MOSFET transistor, which in turn drives the primary coil of the transformer. This specific integrated circuit, as well as others used in the art, typically contain a control mechanism that disables the power supply when the input voltage drops below a pre-defined voltage level. Such protection is necessary because, to produce regulated output voltages, the switched-mode power supply increases the duty cycle of the control signal driving the transistor as the input voltage decreases. At some point, the input voltage decreases to a level where the output of the power supply is unregulated (e.g., the maximum pulse length is used to drive the transistor). Such unregulated operation can damage the power supply electronics, but is more likely to damage the load electronics.

For the integrated circuit (IC) TDA4605, as defined in the TDA4605 Technical Manual available from Siemens AG, dated Jul. 27, 1989, pin 3 of the integrated circuit is used for sensing or monitoring the primary input voltage (vp) for the power supply (e.g., the rectified AC voltage). The threshold voltage for disabling or deactivating the integrated circuit, and thus the power supply, is pre-established by the controller at one volt. As such, the primary input voltage (vp) is reduced using a voltage divider at the input of pin 3. By selecting appropriate resistor values within the voltage divider, a nominal value of monitoring voltage is applied to pin 3. Typically, this voltage is approximately 2.0 volts for a primary input voltage of 120 volts. When the primary input voltage falls to a level that causes the monitoring voltage at pin 3 to fall below one volt, the power supply is deactivated to avoid unregulated operation.
As stated above, this form of switched-mode power supply has been finding use within television signal receivers. However, television receivers, in particular, present peculiar loading characteristics to a power supply. Specifically, a television receiver power supply is called upon to produce a regulated B+ voltage, typically of approximately 140 volts, as well as a low voltage DC level of 16 volts for powering all of the digital and analog circuitry within the receiver. When the television receiver is switched from stand-by to run mode, a heavy load is produced by the in-rush of current into filter capacitors connected to the regulated B+ voltage. This heavy load causes the power supply to temporarily operate in an unregulated (maximum pulse width) mode, and may cause the primary input voltage to drop to a low level. Furthermore, when the degaussing circuit is activated to degauss the cathode ray tube (CRT), the main AC supply voltage is depressed due to the substantial load presented by the degaussing circuit. Consequently, the drop in line voltage could typically cause the monitoring voltage to drop below the 1 volt, first threshold level, and as such, to disable the power supply.
Therefore, there it is desirable to produce a monitoring voltage indicative of the primary input voltage, but to insure that the power supply will not be deactivated for the expected heavy loads found in a television receiver.

The IC TDA 4605 includes a foldback point correction circuit that reduces the maximum duty cycle of the MOSFET control signal, when the monitoring voltage exceeds a second threshold level of approximately 1.7 V. The monitoring voltage is applied to the correction circuit also via pin 3.
In a circuit embodying an inventive feature, a resistive voltage divider that produces the monitoring input or sense signal from the primary input voltage is designed such that the first threshold level is not attained during the expected temporary loading of the primary input voltage. However, such a voltage divider results in a higher voltage being applied to the monitoring voltage input of the controller during normal operation of the power supply. As such, an increase of the primary input voltage to a higher level, which is still within the acceptable tolerance range of the AC line voltage, can cause the monitoring voltage to rise to a level that exceeds the second threshold level at which the integrated circuit begins to limit the maximum duty cycle of the control signal that controls the MOSFET, i.e., the controller applies a foldback correction technique. When the second threshold level is exceeded, the power supply automatically limits the output power of the power supply for an increase in the primary voltage. As a result of the voltage divider design that provides sufficient headroom to overcome loading generated drop outs in the primary input voltage, the maximum power supply output could be, undesirably, significantly reduced at high primary input voltage.
In carrying out an inventive feature, to insure that such inconsequential increase in the primary input voltage does not cause the power supply to significantly reduce the maximum duty cycle of the control signal and thereby, the power output of the power supply, a zener diode is coupled to the voltage divider. The zener diode limits the magnitude of the monitoring voltage to a level that avoids further maximum duty cycle limiting when the primary input voltage further increases. Consequently, when the power supply is used in a television signal receiver, the voltage divider provides enough head room for the primary voltage to drop substantially due to degaussing circuit activation or other loading conditions, while the zener diode insures that the primary voltage can rise above its nominal voltage without causing a significant power limitation of the power supply output.
A switch mode power supply, embodying an aspect of the invention, includes a source of an input supply voltage. A switch is responsive to a first control signal having a controllable duty cycle and coupled to the source of input supply voltage for generating an output supply voltage, in accordance with the duty cycle of the first control signal. A duty cycle modulator is responsive to a second control signal for generating the first control signal and for controlling the duty cycle of the first control signal in accordance therewith in a manner to control the current pulses. An increase in the duty cycle produces an increase in a magnitude of the current pulses. The modulator is responsive to a signal that is indicative of the input supply voltage for decreasing the duty cycle when the input supply voltage increases. A limiter is coupled to the modulator for limiting the decrease in duty cycle, for a given increase in said input supply voltage, when the input supply voltage exceeds a first magnitude.

FIG. 1 depicts a schematic diagram of a switched-mode power supply incorporating the teachings of the present invention.

FIG. 1 depicts a schematic diagram of a switched-mode power supply 100 incorporating the present invention. The embodiment shown is designed for use as a power supply for a television signal receiver, wherein the power supply generates a regulated B+ voltage (e.g., 140 volts) and a low voltage (e.g., 16 volts). The regulated B+ voltage is used to power a horizontal deflection circuit and the regulated low voltage is used to power the digital and analog electronics (continuous load 118). Other applications for the power supply may require slight variation in the depicted components and their interconnections; however, such variations are well within the scope of the present invention.
The power supply contains a number of major components, including a full-wave rectifier 102, the power supply controller 106, a MOSFET transistor Q1, a monitor voltage generator 110, an output transformer 112, and a plurality of circuit components used to complete the power supply electronics. Illustratively, the input to the power supply is a 110-volt AC, 60 hertz voltage.
Rectifier 102 is a conventional full-wave bridge rectifier coupled to an AC input voltage source 101. The output of the bridge rectifier 102 is coupled to capacitor C1 approximately 680 μF). A voltage RAW B+ forms raw (unregulated) B+ voltage (also referred to herein as the primary input voltage vp) having a nominal value of approximately 150 volts. Capacitor C1, connected from the output of the rectifier to ground, smoothes the voltage from the bridge rectifier such that a DC voltage, i.e., the primary input voltage vp, is available at the upper terminal of the transformer's primary winding W₁.
The primary input voltage forms an input to the monitor voltage generator 110 which produces a monitor voltage VZ1 for the controller 106. The monitor voltage generator is discussed in detail below.
The controller is illustratively a TDA 4605 power supply controller available from Siemens AG of Munich, Germany. The eight pins of the controller are connected to signals and voltages that enable the controller to produce a pulse width or duty cycle modulated signal at pin five for controlling the duty cycle of the transistor Q1. Specifically, pin 4 of controller 106 is grounded. Pin 3 is coupled to the monitor voltage.
Pin 2 is supplied information concerning the primary current. A primary current increase in the primary winding W₁ is simulated as a voltage rise of a periodical, ramp voltage VC2 at pin 2 using an external RC element formed by resistor R3, capacitor C2, and resistor R4 (where R3 is approximately 360 kΩ, C2 is approximately 6,800 pF; and R4 is approximately 220 Ω). These elements are connected in series from the primary input voltage to ground. Pin 2 of the controller 106 is coupled to the junction of R3 and C2. A pulse width modulator 106c of the controller 106 controls the duration of the forward phase, and thus, the primary peak current, using ramp voltage VC2 that is proportional to the drain current of the transistor Q1. As indicated before, the ramp voltage is derived from the primary input voltage using the RC elements connected to pin 2, i.e., the ramp voltage simulates the primary current. Controller pin 1 is supplied secondary voltage information which internally compares the control voltage sampled from the regulating winding W3 of the transformer 112 and compares that sample voltage with an internal reference voltage.
Pin 5 generates a duty cycle modulated control signal or voltage VOUT via a push-pull output driver for rapid charge and discharge of the input capacitance of a MOSFET power transistor Q1 (Model IRF740).
Pin 6 is coupled to the supply voltage for the controller. Pin 7 forms a soft start input terminal. Capacitor C5 (0.1 μF) is connected from pin 7 to ground to reduce the pulse duration during start-up. Lastly, pin 8 is the input pin for the oscillator feedback.
In operation, the transistor Q1 is used as a power switch controlled by the controller 106. A snubber circuit is connected to the drain of the transistor Q1. The snubber circuit contains a combination of diode D3, resistor R16 and capacitor C12, which together limit the voltage overshoot when the transistor is turned off. D3 is a MUR450 diode, C12 is a 1000 pF capacitor, and R16 is a 2-watt, 30 kΩ resistor.
Together with the stray capacitance of the transformer, capacitor C7 (470 pF connected from drain terminal to ground) determines the no-load frequency, and consequently, the maximum slew rate of the drain voltage for a transistor Q1.
Transistor Q1 is driven with pulse width modulated signal VOUT produced at pin 5 of controller 106 and coupled to the gate terminal of the transistor via resistor R11 (35 Ω). Furthermore, a capacitor C6 (4700 pF) is coupled from the source terminal to the drain terminal. The source terminal is coupled to ground through resistor R13 (0.27 KΩ). Resistor R12 (10 kΩ) is optionally connected between the source terminal and gate terminal to ensure that the transistor will not be activated if power is applied to the power supply without the controller 106 being installed. The drain terminal is coupled to one terminal of the primary winding W1 of transformer 112. Consequently, the transistor Q1 controls the current flow from the primary input voltage through the primary winding.
The secondary circuit of the transformer 112 consists of several windings, each of which has a different number of turns, polarity, and load capacity. Specifically, winding W2 forms the output voltage for the regulated B+, while winding W4 forms the output winding for the regulated 16-volt low voltage output, and winding W3 generates the feedback voltage for the controller 106.
The load circuitry includes, connected to winding W2, an output diode D4 and capacitor C13 that couple power to the horizontal deflection circuit 116. Additionally, the center tap of the output secondary winding is connected to ground, and winding W4 is coupled to diode D5 and capacitor C14. This output is the 16 volts that powers the continuous load 118 of the television receiver, e.g., all of the electronics and integrated circuits. This circuit 118 also controls the timing of when the degaussing circuit 114 is activated using degaussing control line 120. The control line for the continuous load is the run/standby control signal that essentially turns the television receiver on and off. The continuous load circuitry 118 is also coupled to the horizontal deflection circuit 116 to provide control signals therefor.
The controller 106 is started up using resistor R17 (100 KΩ) as a start resistor. As such, capacitor C11 (100 μF) is charged with half-wave currents at the voltage supply pin of the controller 106, e.g., pin 6. These half-wave currents are supplied from the primary input voltage through resistor R17 (100 KΩ) to ground through series connected resistor R14 (202 Ω), diode D2 (148 Ω) and regulating winding W3. When the voltage at C11 reaches the switch-on threshold, the switched-mode power supply begins to function and supplies the feedback voltage, via winding W3, resistor R14 and diode D2. This feedback voltage, when rectified by diode D2 and smoothed by capacitor C11, forms the supply voltage (v_cc) for the controller 106 via pin 6.
A control signal or voltage VCT for pin 1 is generated in a circuit parallel to the controller supply voltage circuit. The control voltage is produced by diode D1 (ERB43) charging capacitor C3 (1.5 μF) through resistor R8 (10 Ω). The RC element, consisting of series connected R15 (30 Ω) and C10 (0.01 μF), prevents peak value rectification of high frequency components of the feedback signal.
More specifically, regulating winding W3 is coupled to one terminal of resistor R15. The other terminal of resistor R15 is coupled to capacitor C10 to ground. Diode D1 is connected at the junction of resistor R15 and capacitor C10. Capacitor C9 (1000 pF) is connected in parallel with diode D1. Diode D1 has an output voltage that is coupled to series connected R8 and C3 which couples the output of the diode to ground. The output of the diode is also coupled through resistive divider network R6 and R7 which are respectively connected in series to ground. The voltage at the junction of R6 and R7 forms control voltage VCT and is coupled to pin 1 of the controller 106. These resistors define the no-load frequency of oscillation of the controller 106. Therefore, they are typically 0.1% accurate resistors having R6 being 5.49 KΩ, and R7 being 174 Ω. Control voltage VCT is coupled to a pulse-width modulator 106c within controller 106 that controls the duty cycle modulation of voltage VOUT for regulating, for example, voltage REGB+.
During the power supply start-up, capacitor C5 at the soft-start pin (e.g., pin 7), influences the duration of the forward phase by controlling the error voltage of the pulse width modulator. The controller detects the end of the transformer discharge phase via resistor R10 (20 KΩ) that is coupled at one end to controller pin 8 and at the other end to resistor R14, and ultimately to the regulating winding W3. Additionally, capacitor C8 (0.022 μF) is coupled from the junction of R10 and R14 to ground. At this point, the voltage changes polarity from positive to negative, i.e., the voltage represents zero crossings.
A voltage VZ1, embodying an inventive feature, is generated by the monitor voltage generator 110 and is coupled to pin 3 of the controller 106. Voltage VZ1 is used both for determining the minimum line voltage that will allow the power supply to operate and for controlling a foldback point correction circuit 106b within the controller 106.
The monitor voltage generator 110 contains resistor R1 (270 kΩ) coupled in series with resistor R2 (5100 Ω) to form a resistive voltage divider network with respect to primary input voltage RAW B+. The junction of the two resistors is coupled to the pin 3 of controller 106. Furthermore, a zener diode Z1 (B2X55/C3VO), embodying an inventive feature, is connected in parallel with resistor R2 from the junction point to ground. Zener diode Z1 forms a limiter for limiting the maximum voltage across R2 to the breakdown voltage of the zener diode Z1. Consequently, the voltage at the output of the monitor voltage generator 110 tracks the primary input voltage RAW B+ up to the threshold point where the zener diode Z1 begins to conduct.
The controller 106 includes an under-voltage detector 106a that uses a fixed, internal voltage threshold that causes the controller to disable the power supply whenever the monitor voltage VZ1 drops below a first threshold voltage. For the TDA 4605 integrated circuit, this first threshold voltage is one volt. As such, the divider network of R1 and R2 defines a voltage at the output that under typical operation would not cause the controller to deactivate the power supply.
In one particular application, e.g., a television signal receiver, a degaussing circuit 114 for a television signal receiver is typically connected directly across the input AC power. Consequently, when the degaussing circuit is activated, it will typically cause a drop in the AC voltage that is applied to the input of the voltage rectifier 102. Consequently, the primary input voltage RAW B+ will drop significantly during the degaussing period. Since this is a normal behavior of a conventional television receiver circuit, it is desirable that the monitor voltage generator 110 be designed such that the controller 106 will not deactivate the power supply during the degaussing period.
For a primary input voltage of 120 volts and using a resistive divider of 270 KΩ for R1 and 5100 Ω for R2, the nominal voltage VZ1 at the voltage monitor input pin is 2 volts. Such a value for the voltage monitor voltage will avoid power supply deactivation during the degaussing period or other heavy load period.
When the duty cycle of voltage VOUT is at the maximum as a result of an overload condition, an increase in voltage RAW B+, produced by an increase in the AC line voltage, causes the voltage across primary winding w₁ to increase. As the primary input voltage RAW B+ rises, the available input power to the power supply increases which could damage the power supply when the power supply is overloaded. During a period of overloaded, unregulated output, the modulator 106c generates the voltage VOUT having a maximum duty cycle for driving transistor Q1. As a result, a primary current IP in winding W₁ of transformer 112 has also a maximum duty cycle. Therefore, undesirably an increase in voltage RAW B+ can produce a large voltage across the transistor that could damage the transistor or other circuitry.
To maintain the power supply within a safe operation range, the controller 106 includes what is known as a foldback or overload point correction circuit 106b. This foldback point correction circuit reduces the maximum duty cycle of voltage VOUT when the primary input voltage exceeds a predetermined magnitude. An increase above the predetermined magnitude causes the foldback point correction circuit 106b to decrease the maximum duty cycle of signal VOUT as voltage RAW B+ increases. The decrease is done by generating a correction current ICOR that is coupled to capacitor C2 causing an increase in the rate of change of voltage VC2 at pin 2 of controller 106 when voltage VZ1 exceeds a second threshold voltage.
When voltage RAW B+ increases and causes voltage VZ1 to further increase above the second threshold voltage an increase in current ICOR produces a decrease in the maximum duty cycle of signal VOUT, in a well know manner. The second threshold voltage occurs when voltage VZ1 is above a voltage level of approximately 1.7 V. The result is that, when voltage RAW B+ further increases the maximum duty cycle decreases proportionally. The decrease in the maximum duty cycle tends to stabilize the maximum power produced in the power supply against an increase of voltage RAW B+. On the other hand, an increase of voltage VZ1 when voltage VZ1 is below the 1.7 V level, does not affect current ICOR and the duty cycle of voltage VOUT.
Because the divider network (R1 and R2) establishes a sufficiently large monitor voltage VZ1 that provides sufficient headroom for preventing power supply shutdown when the degaussing circuit is activated, primary input voltage RAW B+ may be at a level that causes voltage VZ1 to exceed the second threshold voltage of circuit 106b by an excessive amount even when voltage RAW B+ is within the normal tolerance range. Therefore, disadvantageously, the maximum duty cycle may further decrease by a significant amount in a manner to lower the maximum power that can be derived. Such significant reduction in power capability can occur even though primary input voltage is not truly at such a high level that could damage the power supply.
In accordance with an inventive feature, to prevent current ICOR from further reducing the maximum duty cycle of voltage VOUT when voltage RAW B+ increases above a threshold magnitude that corresponds to voltage VZ1 being equal to 3 V, the monitor voltage generator 110 contains the zener diode Z1 operating as a limiter which limits the primary input voltage indicative voltage VZ1 to 3 V. Consequently, the monitor voltage VZ1 can never rise above a pre-defined level (e.g., 3 volts) that would otherwise cause the foldback point correction circuit 106b within the controller 106 to further decrease the maximum duty cycle. In this way, advantageously, the decrease in the maximum duty cycle as a function of an increase in voltage RAW B+ is limited.
The decrease in the duty cycle of voltage VOUT produced by current ICOR, for a given increase in voltage RAW B+, is limited when voltage RAW B+ is greater than a threshold magnitude that corresponds to voltage VZ1 equal to 3 V. In contrast, the decrease in the duty cycle produced by current ICOR is not limited but varies proportionally to voltage RAW B+ when voltage VZ1 is between 1.7 V and 3 V. Thus, zener diode Z1 operates as a limiter for limiting the decrease in the duty cycle when the voltage RAW B+ exceeds the threshold magnitude relative to when voltage RAW B+ does not exceed the threshold magnitude. An increase in voltage RAW B+ that produces voltage VZ1 below the second threshold voltage of 1.7 V, does not affect current ICOR.
Specifically, for the TDA 4605 integrated circuit control, the zener diode has a value of three volts. Consequently, the input signal to the monitor voltage generator cannot rise above the three volt level before the zener diode will begin to conduct current to ground. As such, the monitor voltage generator establishes a range of voltages that pre-defines a range of primary input voltages at which the controller 106 operates in a normal manner that avoids both an undervoltage power supply deactivation and a further decrease in the maximum duty cycle. The input voltage dynamic range is thereby extended.

siemens TDA4605-3Control IC for Switched-Mode Power Supplies using MOS-Transistor


The IC TDA 4605-3 controls the MOS-power transistor and performs all necessary control and
protection functions in free running flyback converters. Because of the fact that a wide load range
is achieved, this IC is applicable for consumer as well as industrial power supplies.
The serial circuit and primary winding of the flyback transformer are connected in series to the input
voltage. During the switch-on period of the transistor, energy is stored in the transformer. During the
switch-off period the energy is fed to the load via the secondary winding. By varying switch-on time
of the power transistor, the IC controls each portion of energy transferred to the secondary side
such that the output voltage remains nearly independent of load variations. The required control
information is taken from the input voltage during the switch-on period and from a regulation winding
during the switch-off period. A new cycle will start if the transformer has transferred the stored
energy completely into the load.

Features
- Fold-back characteristics provides overload protection for
external components
- Burst operation under secondary short-circuit condition
implemented
- Protection against open or a short of the control loop Switch-off if line voltage is too low (undervoltage switch-off)
- Line voltage depending compensation of fold-back point
- Soft-start for quiet start-up without noise generated by the
transformer
- Chip-over temperature protection implemented (thermal
shutdown)
- On-chip ringing suppression circuit against parasitic
oscillations of the transformer
- AGC-voltage reduction at low load.

In the different load ranges the switched-mode power supply (SMPS) behaves as follows:
No load operation
The power supply is operating in the burst mode at typical 20 to 40 kHz. The output voltage can be
a little bit higher or lower than the nominal value depending of the design of the transformer and the
resistors of the control voltage divider.
Nominal operation
The switching frequency is reduced with increasing load and decreasing AC-voltage.
The output voltage is only dependent on the load.
Overload point
Maximal output power is available at this point of the output characteristic.
Overload
The energy transferred per operation cycle is limited at the top. Therefore the output voltages
declines by secondary overloading.

Application Circuit
The application circuit shows a flyback converter for video recorders with an output power rating of
70 W. The circuit is designed as a wide-range power supply for AC-line voltages of 180 to 264 V.
The AC-input voltage is rectified by the bridge rectifier GR1 and smoothed by C1 . The NTC limits
the rush-in current.
In the period before the switch-on threshold is reached the IC is suppled via resistor R 1 ; during the
start-up phase it uses the energy stored in C2 , under steady state conditions the IC receives its
supply voltage from transformer winding n1 via diode D1. The switching transistor T1 is a BUZ 90.
The parallel connected capacitor C3 and the inductance of primary winding n 2 determine the
system resonance frequency. The R 2-C4-D2 circuitry limits overshoot peaks, and R 3 protects the
gate of T1 against static charges.
During the conductive phase of the power transistor T1 the current rise in the primary winding
depends on the winding inductance and the mains voltage. The network consisting of R 4-C5 is used
to create a model of the sawtooth shaped rise of the collector current. The resulting control voltage
is fed into pin 2 of the IC. The RC-time constant given by R 4-C5 must be designed that way that
driving the transistor core into saturation is avoided.
The ratio of the voltage divider R 10/R 11 is fixing a voltage level threshold. Below this threshold the
switching power supply shall stop operation because of the low mains voltage. The control voltage
present at pin 3 also determines the correction current for the fold-back point. This current added to
the current flowing through R 4 and represents an additional charge to C5 in order to reduce the turnon
phase of T1. This is done to stabilize the fold-back point even under higher mains voltages.
Regulation of the switched-mode power supplies via pin 1. The control voltage of winding n1 during
the off period of T1 is rectified by D3, smoothed by C6 and stepped down at an adjustable ratio by
R 5 , R 6 and R 7 . The R 8-C7 network suppresses parasitic overshoots (transformer oscillation). The
peak voltage at pin 2, and thus the primary peak current, is adjusted by the IC so that the voltage
applied across the control winding, and hence the output voltages, are at the desired level.
When the transformer has supplied its energy to the load, the control voltage passes through zero.
The IC detects the zero crossing via series resistors R 9 connected to pin 8. But zero crossings are
also produced by transformer oscillation after T1 has turned off if output is short-circuited. Therefore
the IC ignores zero crossings occurring within a specified period of time after T1 turn-off.
The capacitor C8 connected to pin 7 causes the power supply to be started with shorter pulses to
keep the operating frequency outside the audible range during start-up.
On the secondary side, five output voltages are produced across winding n3 to n7 rectified by D4 to
D8 and smoothed by C9 to C13 . Resistors R 12 , R 14 and R 19 to R 21 are used as bleeder resistors.
Fusable resistors R 15 to R 18 protect the rectifiers against short circuits in the output circuits, which
are designed to supply only small loads.

Pin 1
The regulating voltage forwarded to this pin is compared with a stable internal reference voltage VR
in the regulating and overload amplifier. The output of this stage is fed to the stop comparator. If
the control voltage is rather small at pin 1 an additional current is added by means of current source
which is controlled according the level at pin 7. This additional current is virtually reducing the
control voltage present at pin 1.
Pin 2
A voltage proportional to the drain current of the switching transistor is generated there by the
external RC-combination in conjunction with the primary current transducer. The output of this
transducer is controlled by the logic and referenced to the internal stable voltage V2B . If the voltage
V2 exceeds the output voltage of the regulations amplifier, the logic is reset by the stop comparator
and consequently the output of pin 5 is switched to low potential. Further inputs for the logic stage
are the output for the start impulse generator with the stable reference potential VST and the
supply voltage motor.
Pin 3
The down divided primary voltage applied there stabilizes the overload point. In addition the logic is
disabled in the event of low voltage by comparison with the internal stable voltage VV in the primary
voltage monitor block.
Pin 4
Ground
Pin 5
In the output stage the output signals produced by the logic are shifted to a level suitable for MOSpower
transistors.
Pin 6
From the supply voltage V6 are derived a stable internal references VREF and the switching
threshold V6A , V6E , V6 max and V6 min for the supply voltage monitor. All references values (VR ,
V2B , VST) are derived from VREF . If V6 > VVE , the VREF is switched on and switched off when V6 <
V 6A . In addition, the logic is released only for V6 min < V6 < V6 max .
Pin 7
The output of the overload amplifier is connected to pin 7. A load on this output causes a reduction
in maximal impulse duration. This function can be used to implement a soft start, when pin 7 is
connected to ground by a capacitor.


Pin 8
The zero detector controlling the logic block recognizes the transformer being discharged by
positive to negative zero crossing of pin 8 voltage and enables the logic for a new pulse. Parasitic
oscillations occurring at the end of a pulse cannot lead to a new pulse (double pulsing), because an
internal circuit inhibits the zero detector for a finite time tUL after the end of each pulse.
Start-Up Behaviour
The start-up behaviour of the application circuit per sheet 88 is represented an sheet 90 for a line
voltage barely above the lower acceptable limit time t0 the following voltages built up:
– V6 corresponding to the half-wave charge current over R1
– V2 to V2 max (typically 6.6 V)
– V3 to the value determined by the divider R 10/R 11 .
The current drawn by the IC in this case is less than 1.6 mA.
If V6 reaches the threshold V6E (time point t1), the IC switches on the internal reference voltage. The
current draw max. rises to 12 mA. The primary current- voltage reproducer regulates V2 down to V2B
and the starting impulse generator generates the starting impulses from time point t5 to t6 . The
feedback to pin 8 starts the next impulse and so on. All impulses including the starting impulse are
controlled in width by regulating voltage of pin 1. When switching on this corresponds to a shortcircuit
event, i.e. V1 = 0. Hence the IC starts up with "short-circuit impulses" to assume a width
depending on the regulating voltage feedback (the IC operates in the overload range). The IC
operates at the overload point. Thereafter the peak values of V2 decrease rapidly, as the starting
attempt is aborted (pin 5 is switched to low). As the IC remains switched on, V6 further decreases
to V6 . The IC switches off; V6 can rise again (time point t4) and a new start-up attempt begins at
time point t1 . If the rectified alternating Iine voltage (primary voltage) collapses during load, V3 can
fall below V3A , as is happening at time point t3 (switch-on attempt when voltage is too low). The
primary voltage monitor then clamps V3 to V3S until the IC switches off (V6 < V6A). Then a new startup
attempt begins at time point t1 .

Regulation, Overload and No-Load Behaviour
When the IC has started up, it is operating in the regulation range. The potential at pin 1 typically is
400 mV. If the output is loaded, the regulation amplifier allows broader impulses (V5 = H). The peak
voltage value at pin 2 increases up to V2S max . If the secondary load is further increased, the
overload amplifier begins to regulate the pulse width downward. This point is referred to as the
overload point of the power supply. As the IC-supply voltage V6 is directly proportional to the
secondary voltage, it goes down in accordance with the overload regulation behaviour. If V6 falls
below the value V6 min , the IC goes into burst operation. As the time constant of the half-wave
charge-up is relatively large, the short-circuit power remains small. The overload amplifier cuts back
to the pulse width tpk . This pulse width must remain possible, in order to permit the IC to start-up
without problems from the virtual short-circuit, which every switching on with V1 = 0 represents. If
the secondary side is unloaded, the loading impulses (V5 = H) become shorter. The frequency
increases up to the resonance frequency of the system. If the load is further reduced, the secondary
voltages and V6 increase. When V6 = V6 max the logic is blocked. The IC converts to burst
operation.This renders the circuit absolutely safe under no-load conditions.
Behaviour when Temperature Exceeds Limit
An integrated temperature protection disables the logic when the chip temperature becomes too
high. The IC automatically interrogates the temperature and starts as soon as the temperature
decreases to permissible values.

Pin Definitions and Functions
Pin No. Function
1 Information Input Concerning Secondary Voltage. By comparing the
regulating voltage - obtained trom the regulating winding of the transformer - with
the internal reference voltage, the output impulse width on pin 5 is adjusted to the
load of the secondary side (normal, overload, short-circuit, no load).
2 Information Input Regarding the Primary Current. The primary current rise in
the primary winding is simulated at pin 2 as a voltage rise by means of external
RC-element. When a voltage level is reached thats derived from the regulating
voltage at pin 1, the output impulse at pin 5 is terminated. The RC-element serves
to set the maximum power at the overload point set.
3 Input for Primary Voltage Monitoring: In the normal operation V3 is moving
between the thresholds V3H and V3L (V3H > V3 > V3L).
V3 < V3L: SMPS is switched OFF (line voltage too low).
V3 > V3H : Compensation of the overload point regulation (controlled by pin 2)
starts at V3H : V3L = 1.7.
4 Ground
5 Output: Push-pull output provides ± 1 A for rapid charge and discharge of the
gate capacitance of the power MOS-transistor.
6 Supply Voltage Input: A stable internal reference voltage VREF is derived from
the supply voltage also the switching thresholds V6A , V6E , V6 max and V6 min for
the supply voltage detector. If V6 > V6E then VREF is switched on and swiched off
when V6 < V6A . In addition the logic is only enable for V6 min < V6 < V6 max.
7 Input for Soft-Start. Start-up will begin with short pulses by connecting a
capacitor from pin 7 to ground.
8 Input for the Oscillation Feedback. After starting oscillation, every zero
transition of the feedback voltage (falling edge) through zero (falling edge)
triggers an output pulse at pin 5. The trigger threshold is at + 50 mV typical.

PHILIPS TDA6111 :

Video output amplifier
GENERAL DESCRIPTION
The TDA6111Q is a video output amplifier with 16 MHz
bandwidth. The device is contained in a single in-line 9-pin
medium power (DBS9MPF) package, using high-voltage
DMOS technology, intended to drive the cathode of a
colour CRT.




 FEATURES
• High bandwidth and high slew rate
• Black-current measurement output for Automatic
Black-current Stabilization (ABS)
• Two cathode outputs; one for DC currents, and one for
transient currents
• A feedback output separated from the cathode outputs
• Internal protection against positive appearing
Cathode-Ray Tube (CRT) flashover discharges
• ESD protection
• Simple application with a variety of colour decoders
• Differential input with a designed maximum common
mode input capacitance of 3 pF, a maximum differential
mode input capacitance of 0.5 pF and a differential input
voltage temperature drift of 50 μV/K
• Defined switch-off behaviour.

 The cathode output is protected against peak currents (caused by positive voltage peaks during high-resistance flash) of 5 A maximum with a charge content of 100 μC. The cathode is also protected against peak currents (caused by positive voltage peaks during low-resistance flash) of 10 A maximum with a charge content of 100 nC. Flashover protection The TDA6111Q incorporates protection diodes against CRT flashover discharges that clamp the cathode output pin to the VDDH pin. The DC supply voltage at the VDDH pin has to be within the operating range of 180 to 210 V to ensure that the Absolute Maximum Rating for VDDH of 250 V will not be exceeded during flashover. To limit the diode current, an external 680 Ω carbon high-voltage resistor in series with the cathode output and a 2 kV spark gap are needed (for this resistor-value, the CRT has to be connected to the main PCB). This addition produces an increase in the rise and fall times of approximately 5 ns and a decrease in the overshoot of approximately 4%.

CCU 3000, CCU 3000-I Main System Processor
CCU 3001, CCU 3001-I
MICRONAS INTERMETALL

1. Introduction
The CCU 3000, CCU 3000-I, CCU 3001, CCU 3001-I
are integrated circuits designed in 1.2 mm CMOS
technology, with the exception of CCU 3000, TC18 and
TC19, which is designed in 1 mm CMOS technology. The
CPU contained on the chips is a functionally unchanged
65C02-core, which means that for program development,
systems can be used which are on the market; including
high level language compilers.
The pin numbers mentioned in this data sheet refer to
the 68-pin PLCC package unless otherwise designated.
The CCU 3000-I is described separately in an addendum
on page 66.
1.1. Features of the CCU 3000, CCU 3000-I,
CCU 3001, CCU 3001-I
– CCU 3000 = ROM-less version of the CCU 3001
– 65C02 CPU with max. 8 MHz clock
– 32 kByte internal ROM (CCU 3001 only)
– 1344 internal Bytes RAM with stand-by option
– 51 I/O lines (CCU 3001)
– 26 I/O lines (CCU 3000)
– clock generator with programmable clock frequency
– 8 level interrupt controller
– CCU 3000, CCU 3001:
2 Multimaster IM bus interfaces
– CCU 3000-I, CCU 3001-I: 1I2C/IM bus and
1 Multimaster IM bus interface (see addendum)
– IR-input for software-decoded IR-systems
– on-chip power on, stand-by and clock supervision
logic
– on-chip watchdog
– 3 multifunctional timers
– supports memory banking (external 2MBytes)
– power down signal for external memory
– mask option: EMU mode
– programs can be written in Assembler or in “C”
– CCU 3000 TC 18/19: 1.0 mm CMOS technology, (see
addendum)
– application software available.

Functional Description
2.1. ROM
The chip is equipped with 32 kByte mask-programmable
ROM. The ROM uses up the address space from 8000H
to FFFFH. This ROM can be supplemented or replaced
externally. Only the CCU 3001 has an internal ROM.
2.2. RAM
The RAM area is split into three parts:
– page 0 (address 0 to FFH)
– page 1 (address 100H to 1FFH)
– page 3, 4, 5, 6 (address 300H to 63FH)
Page 0 offers a particularly fast access to the 65C02 and
is therefore very valuable for fast, compact programs.
Page 1 contains the stack and must therefore also have
RAM. The remaining RAM-memory follows in pages 3,
4, 5, 6, as page 2 is reserved as I/O address space. The
RAM can be kept in the stand-by mode via stand-by pin.
2.3. CPU
The CPU core is fully compatible with the 65C02 microprocessor.
However, not all the pins of the 65C02 processor
are accessible for the user outside the chip. One
switch in the control register allows the CPU to be
switched off, so that an external processor can take over
its tasks. This external processor can of course also be
an in-circuit emulator, which makes near-hardware
emulation possible, even though the status and control
lines of the internal CPU are not accessible. If an external
processor is used, all hardware blocks of the chip are
as accessible to it as if it were the internal CPU.
2.4. Clock Generator
An integrated two-pin oscillator generates the clock for
the microcontroller. The frequency created by the oscillator
can be programmed to be reduced with a divider
by the factor 1 ... 255. This enables the user to decrease
the current consumption by the controller by reducing
the working frequency as well as to increase the access
time for the (slower) external memory. This divider contains
the value 4 after a reset, so that the system can also
start with a slow external memory. If the mask-option
OSC is set (EMU version), a switch in the control register
makes it possible to receive the internal clock F2 at
XTAL2. In this case the oscillator must be external and
the clock must be fed to the pin XTAL1. In this way, the
user gets a time reference for internal operations in the
microcomputer. This is especially important with the interrupt
controller. The production version of the CCU
does not have this function!
2.5. PORT 1 to PORT 3, PORT 6 to PORT 8
8 ports belong to the system, of which 5 are 8 bits wide,
one 6 bit, one 4 bit and one 1 bit wide. All port lines of
PORTS 1 to 3 and 6 to 8 can be used as inputs or outputs
independently from each other. One register per port
defines the direction. PORT1 to PORT3 have push-pull
outputs and PORT6 to PORT8 have open drain outputs.
Even a line defined as output can be read, the pin level
being important. This property makes it possible for the
software to find desired and undesired short circuits.
Each port reserves a byte for the direction register and
the data in the I/O page. If the corresponding bit in the
direction register is set to 0, the output mode is switched
on. After a reset, all bits of a direction register are set
to 1. The falling edge of bit 7 of PORT 8 generates interrupts
if the priority of the corresponding interrupt controller
source (7) is not set to 0.
2.6. PORT 4
PORT 4 consists of only one line (LSB, P40). After a reset,
PORT 4 operates as an input only. As soon as PORT
4 is written for the first time, it is switched to output mode
(push-pull). Later read accesses read the actual level at
port 4. If bit 3 in the control word is active, P4 is used as
an R/W-line. If the internal CPU is active, R/W is an output
line, otherwise it is an input. But P4 has another, very
important function during RESET. The level at P4 during
RESET decides whether the control word is read from
the internal ROM (FFF9H) or from the external memory.
It is therefore important that the desired level during RESET
is set at P4. An internal pull-down resistor of approx.
100 kW is integrated in the CCU 3001, which ensures
that the control word is read by the internal ROM. The
external control word access is obtained via an external
pull-up resistor of approx. 5 kW. The CCU 3000 has an
internal pull-up resistor at P4 (external ROM access).
The further mode of operation of the CCU 3000, CCU
3001 depends only on the control word though.
Please note that this mode is always necessary for
the CCU 3000 since this device does not have internal
ROM!
2.7. I/O-Lines P50 to P55
The 6 additional I/O-lines have a two-fold function:
– input or output line (open drain output) or
– fully decoded I/O-select lines (push-pull outputs)
As a rule these lines can be used as input or output lines.
As soon as ports 1 to 4 are used as system bus, they are
lost as I/O-channels. However, a total of 48 port lines (24
inputs and outputs each) can be reconstructed without
difficulties (1 housing for 8 lines), if the additional 6 I/Olines
of the CCU 3000, CCU 3001 are switched into the
port select mode. They then represent the select lines of
the original ports 1 to 3. Each line can be defined as I/O
or port select line separately. In the I/O-page three bytes
are needed.



TEA6415C Bus-Controlled Video Matrix Switch
Main Features
20 MHz Bandwidth
Cascadable with another TEA6415C (Internal
Address can be changed by Pin 7 Voltage)
8 Inputs (CVBS, RGB, Chroma, ...)
6 Outputs
Possibility of Chroma Signal for each Input
by switching off the Clamp with an external
Resistor Bridge
Bus Controlled
6.5 dB Gain between any Input and Output
-55 dB Crosstalk at 5 MHz
Full ESD Protection

Description
The main function of the TEA6415C is to switch 8
video input sources on the 6 outputs.
Each output can be switched to only one of the
inputs, whereas any single input may be connected
to several outputs.
All switching possibilities are controlled through the
I2C bus.

Driving a 75 W load requires an external transistor.
The switches configuration is defined by words of 16 bits: one word of 16 bits for each output
channel.
So, 6 words of 16 bits are necessary to determine the starting configuration upon power-on (power supply: 0 to 10V). But a new configuration needs only the words of the changed output channels.

Using a Second TEA6415C
The programming input pin (PROG) allows two TEA6415C circuits to operate in parallel and to select them independently through the I²C bus by modifying the address byte. Consequently, the switching capabilities are doubled, or IC1 and IC2 can be cascaded.




TEA6420 BUS-CONTROLLED AUDIO MATRIX SWITCH


5 Stereo Inputs
4 Stereo Ouputs
Gain Control 0/2/4/6dB/Mute for each Output cascadable (2 different addresses) Serial Bus Controlled Very low Noise
Very low Distorsion
DESCRIPTION The TEA6420 switches 5 stereo audio inputs on 4stereo outputs. All the switching possibilities are changed through the I2C bus.

ACP2371 Audio Control Processing:

 

 

 

 Note:
If not otherwise designated, the pin numbers men-
tioned refer to the 44-pin PLCC package.
1. Introduction
The Audio Processor ACP2371NI comprises two components – an A/D converter (ADC) and an Audio Proces- sor Unit (APU) implemented in CMOS (ADC) and NMOS (APU) technology. Together with the MSP2410, the ACP2371NI is a true two-chip solution for terrestrial multistandard sound processing including NICAM and tone control for TV-Sets. One D/A converter pair represents the tone controlled output (DAC1) for speakers, the second D/A converter pair performs the conversion of digital sources (NICAM or FM from MSP) for the scart output (AUXOUT). There- fore DAC2 is routed to TVIN. Herewith it is possible to have an independent input selection for Speaker-Out and Scart-Out (e.g. NICAM to Speakers, FM to Scart). The Audio Processor ACP2371NI has analog and digital inputs:

– Three analog stereo signal pairs are connected via analog switches with the analog output (AUXOUT) and the pulse-density modulators (PDM). Apart from the amplifiers at the inputs, there are also automatic level controls so that even overmodulated signals can be processed. The analog signals that are fed to the DSP unit are then passed to two pulse-density modulators which work on the sigma delta principle (PDM followed by conversion filters). The pulse train density at the PDM outputs is proportional to the signal amplitude; the PDM data rate is about 5 MHz. This high frequency means that anti-aliasing filters are not re- quired. In the second step of the A/D conversion, in the digital decimation filters, the two PDM pulse trains are transformed into 16-bit words and the data rate to ap- prox. 32 kHz, i.e. to values that are more favorable for subsequent processing. In terms of its signal-to-noise ratio, this combined converter system is more or less comparable to a conventional 16-bit A/D converter.

– The digital data bus, the S-Bus, was designed for the transmission of audio data from digital sources. Via the S-Bus Interface any digital source such as MSP 2410 IF-Processor or any DMA MAC-Decoder/Des- crambler can be connected to the ACP2371NI. How- ever, the ACP2371NI is prepared to work together with the MSP2410 as FM-Demodulator and NICAM-De- coder. The activities of the various signal processors in the DIGIT 2000 System are coordinated via the Intermetall control bus (IM-Bus for short). A Central Control Unit (CCU) is used for this purpose. The CCU receives tuning instructions from the user and adjusts the corresponding registers of the signal processors to the required values. The CCU acts as a master, while the ACP and the other signal processors have purely slave status. The DSP block consists of a mask-programmable digital signal processor with 256 x 14 bit ROM whose software can be controlled via the IM-Bus; in this way, various parameters (e.g. filter coefficients) can be altered during operation. The heart of the processor is a fast 16 x 8 multiplier, the basic instruction being the addition of prod- ucts; this is performed in less than 250 ns. Other instructions (in particular, MOVE) can be executed simultaneously by the use of the pipelining technique so that the flow of arithmetic operations does not have to be interrupted. The clock frequency of the system of just 18 MHz means that a maximum of 5 million “product sums” can be calculated per second, which is adequate for real-time signal processing in the audio frequency range. All typical audio functions are carried out in the DSP block:
– Input selection between S-Bus and PDM data (NICAM from MSP, FM from MSP, Scart or AM via PDM)
– Dematrixing of the digital signals (necessary for two channel or stereo sound and mono modes)
– Adjustment of volume, balance, loudness, treble, bass, basewidth enlargement
– Independent input selection for Speaker-Out and Scart-Out (e.g. NICAM to Speakers, FM to Scart)
– Decoding of the identification signal of German 2-tone system for automatic switching between stereo, mono and bilingual sound modes. The three modes are identified by a characteristic frequency peak whichtransmitted modulated upon a carrier of 54.6875 kHz (= three and a half times the horizontal frequency); These tuning functions are controlled by the CCU via suitable filter coefficients and switches.

2. Functional Description of the A/D Part
The analog sound signals selected for conversion by the analog switches are fed to the first processing stage, the pulse density modulators PDM1 and PDM2. The output signals of these are 1-bit data streams at a rate of about 5 MHz. Due to the high sampling rate of the pulse density modulators no steep anti-aliasing filters are needed.

2.1. Analog Switches
The analog switches S1 to S7 are controlled via the IM bus (see section 2.6.). S1 is used to select between signals from – the FM-sound-demodulator of the TV set (inputs TVIN1, TVIN2)

– external sources, for example a video recorder (inputs AUXIN1, AUXIN2)
– additional audio sources, for example the output of the AM-sound-demodulator (inputs AUXDIN1, AUXDIN2) S2 defines whether dematrixing is done or not, according to the German Zweiton TV stereo sound system (see Table 2–1). In addition, S2 is used to control a mute function for the SCART outputs (AUXOUT1, AUX- OUT2). S3 selects between signals from TVIN, AUXIN and an additional analog source fed to the inputs AUXDIN. By means of switches S4 and S5, one single input signal can be connected to both AUXOUT outputs, e.g. if only one TVIN pin is supplied by a signal, as is the case when- ever a non-stereo station is being received. In the case of a bilingual input, it is possible to cross the connections from language A and B to the outputs AUXOUT1 and AUXOUT2. Controlled by the switch S6, the digital inputs/outputs 1 and 2 (PDM1, PDM2) either receive the pulse-density modulated output signals of another ADC or ACP, or serve as monitoring outputs of the pulse-density modulators PDM1 and PDM2. Their output signals can be fed, for example, to another ACP, APU or AMU.

2.2. Dematrix
When switched on via the IM bus (switch S2, (see Table 2–2), the dematrix provides the 2R and 2L stereo signals at the outputs AUXOUT. These signals are extracted from the L + R and 2R input signals (inputs TVIN) ac- cording to the German TV stereo sound system (see Table 2–1). If the MSP 2410 is used for FM-Demodulation, this is not necessary, because the dematrixing is done before D/A conversion in DAC2.

2.3. Pulse-Density Modulators
The two pulse-density modulators PDM1 and PDM2 are sigma-delta modulators equipped with two feedback loops each. At the outputs, they supply pulse trains whose pulse density is proportional to the amplitude of the input signal. The maximum sampling rate, and therefore, the maximum pulse rate is ΦM clock divided by 4.

2.4. Level Control
In former systems a certain signal level headroom had to be left free in order to avoid clipping and distortion in case of input levels beyond the nominal maximum. So some SNR was wasted. Using the internal level control in the ACP 2371NI, the input signal can be scaled up separately in each path. No external components are needed. Whenever the input signal tends to exceed the PDM clip- ping level, a variable gain in the signal path is decreased in 16 steps, 1 step/ms until the modulation of the PDM is again well matched to the input level. If overload has disappeared the circuitry tries to increase the gain in 1 step/s until the internal signal level is at the optimum. There is an additional gain adjustment for the input TVIN2 (±3 dB in steps of 0.2 dB) controlled by the IM bus, so that the channel separation can be optimized during production of the set (see Table 2–2). In the standard configuration (see Fig. 1–1), this feature is not used. Be- cause matrixing is done digitally, no adjustments have to be made.
2.5. Preemphasis and Deemphasis or additional in- put for Scart-Out. TV signals are always preemphasized with 50 μs ac- cording to the standard, AUXIN and AUXDIN signals normally are not. If the FM-Demodulation is not done in the MSP 2410, the deemphasis is realized as follows:
– apply deemphasis DE1 for AUXOUT path
– apply deemphasis at ACP outputs whenever S1 selects TVIN Deemphasis DE1 is done by internal resistors and external capacitors. DE11, DE12 could also be used as inputs for additional audio sources, selected by switch S7 and connected via S3 to AUXOUT. In this case, the Mute control Mu1, Mu2 has to be activated (Bit 3 of addr. 96), so that no other signal connected to AUXOUT. Then, the maximum input voltage is 260 mV RMS (with gain = 3.9 from DE1 to AUXOUT).

2.6. Pilot Input
The pilot signal of the German Zweiton TV stereo sound system is transmitted on the second sound channel. This signal must be supplied separately to the input PI- LOTIN. There is a separate A/D converter (PDM3 and digital decimation filter) for the input PILOTIN to avoid interac- tion between audio and pilot signals. If the input PILOTIN is not used, it should be connected to ground.
2.7. IM Bus Interface This circuit section is provided for controlling the A/D part by the CCU Central Control Unit.

3. Architecture and Functional Description of the Audio Processor Part The audio processor architecture combines two main parts: the I/O blocks and the DSP core. Fig. 3–1 shows a block diagram of the audio processor architecture.

3.1. I/O Blocks
3.1.1. Digital Decimation Filters
The digital decimation filters are cascades of transversal and recursive lowpass filters. They are necessary to convert the two 1-bit PDM-data streams by stepwise re- duction of bandwidth and word rate (sampling rate) into two PCM data streams with 16 bit word length and a sampling rate of 32 kHz, which in the following are called PDM-Data 1 and 2. They are temporarily stored in the corresponding locations of the ACP Data RAM. The two PDM-Data streams at the input of the decima- tion filters have no separate clock signal. Therefore, the decimation filters are equipped with a synchronization facility. This feature also supplies the ACP software with the sampling clock (32 kHz), which is called “I/O Sync”.
.
3.1.2. S Bus Interface
Digital audio information provided by any digital source (for example DMA 2271, MSP 2410 or AMU 2481) is transmitted serially via the S bus to the S bus interface. The S bus consists of four pins: S-Data In: Four channels per sampling cycle (= 4
16 bits) are received from external circuits. S-Data Out: Four channels per sampling cycle (= 4
16 bits) are transmitted to external circuits S-Clock In/Out: gives the timing for the transmission of S-Data S-Ident In/Out:after 64 S-Clock cycles the S-Ident determines the end of one sampling cycle A precise timing diagram of the S bus is shown in Fig. 3–2. The S bus interface mainly consists of an input and output register, each having 64 bits. The timing to write or read out bit by bit is supplied by the S-Clock. In the case of an S-Ident pulse the contents of the input register are transferred to the Data RAM and the contents of the output register are written to the S-Data out line. The S-Ident is also used as the sampling rate reference for the DSP software in the case of digital source mode. In this mode, the I/O-Sync, generated by the decimation filters is locked to the S-Ident. This allows a mixed mode, i.e. S-Data and PDM-Data can be processed simultaneously. However, this feature is not supported by the actual ACP 2371 NI software. By means of coefficient k33 (see section 4.12.), the ACP 2371 NI can be switched to an S bus slave mode (bit 4=0) or to an S bus master mode (bit 4=1). The slave mode is required in an application as shown in Fig. 2–1, where the MSP 2410 NICAM Demodulator/Decoder acts as master on the S bus, i.e. the MSP supplies the S-Clock and S-Ident signals, as well as the S-Data input signal. In an application where two or more Audio Processors of the APU/ACP family are intended to work in one system without a DMA or MSP being present, one of the audio processors must act as master on the S bus (Table 4–22, notes).

3.1.3. IM Bus Interface and IM Bus
3.1.3.1. Description of the IM Bus The INTERMETALL Bus (IM Bus for short) has been de- signed to control the DIGIT 2000 ICs by the CCU Central Control Unit. Via this bus the CCU can write data to the ICs or read data from them. This means the CCU acts as a master whereas all controlled ICs are slaves. The IM bus consists of three lines for the signals Ident (ID), Clock (CL), and Data (D). The clock frequency range is 50 Hz to 170 kHz. Ident and clock are unidirectional from the CCU to the slave ICs, Data is bidirectional. Bidirectionality is achieved by using open-drain out- puts with on-resistances of 150 Ohm maximum. The 2.5 kOhm pull-up resistor common to all outputs is incorporated in the CCU. The timing of a complete IM bus transaction is shown in Fig. 3–3 and under “Recommended Operating Conditions”. In the non-operative state the signals of all three bus lines are High. To start a transaction, the CCU sets the ID signal to Low level, indicating an address trans- mission, and sets the CL signal to Low level as well to switch the first bit on the Data line. Thereafter, eight ad- dress bits are transmitted, beginning with the LSB. Data takeover in the slave ICs occurs at the positive edge of the clock signal. At the end of the address byte the ID signal goes High, initiating the address comparison in the slave circuits. In the addressed slave, the IM bus inter- face switches over to Data read or write, because these functions are correlated to the address. Also controlled by the address, the CCU now transmits eight or sixteen clock pulses, and accordingly, one or two bytes of data are written into the addressed IC or read out from it, beginning with the LSB. The completion of the bus transaction is signalled by a short Low state pulse of the ID signal. This initiates the storing of the transferred data. It is permissible to interrupt a bus transaction for up to 10 ms. For future software compatibility, the CCU must write a zero into all bits not used at present. When reading undefined or unused bits, the CCU must adopt “don’t care” behavior.

 TPU3040 Teletext Processor Unit :

Multistandard Teletext Processor for Level 1 and 2


The TPU 3040 is a single chip World System Teletext (WST) decoder for applications in analog and digital TV sets. Based on a 65C02 core with RAM and ROM on chip, an adaptive data slicer, a display controller and a number of interfaces, the TPU 3040 offers acquisition and display of various teletext and data services such as WST, PDC, VPS and WSS.
1.1. Features
The TPU 3040 is an integrated circuit designed in CMOS technology. As a stand-alone system or in combi- nation with the DIGIT 3000 system, the TPU 3040 offers a wide range of new and interesting features, some of them unique in comparison with other products on the market. The TPU 3035 is a stripped-down version of TPU 3040, designed for low-cost applications. The basic chip archi- tecture remains unchanged, whereas some of the more sophisticated features are removed (see Tab 1–1). In the following description only the TPU 3040 is mentioned.

2. Functional Description
2.1. Conceptional Overview
The basic idea behind the TPU 3040 concept is the re- placement of random logic by software. The still existing hardware supports the on-chip CPU in tasks with high data rates and ineffective software solutions. Typical tasks of a teletext decoder are listed below (realization on TPU 3040 in brackets):
– teletext data acquisition
– teletext data decoding
– page generation
– page memory management
– page display
– user interface
(hardware)
(software)
(software)
(software)
(hardware)
(software)
Fig. 2–1 shows the functional block diagram of the
TPU 3040. The software approach is realized using a 65C02 core with RAM and program ROM on chip. Via I/O the CPU is connected to a DRAM interface. The DRAM contains an acquisition scratch buffer which is filled automatically by the teletext slicer circuit. After processing this scratch buffer, the CPU stores reorganized teletext lines into the page memory which takes up the greatest space in the DRAM capacity. A third part of the DRAM holds WST level 2 display data, which are read out by the WST layer. The CPU has to generate the dis- play data by decoding teletext information from the page memory. Apart from the WST layer, there is also one additional on-chip OSD layer. The OSD layer accesses the on-chip memory to read text and character font information. The RGB outputs of the OSD layer can have higher priority than the WST layer outputs. Thus it is possible to overlay the teletext display with an additional layer for user guidance. The CPU memory contains RAM, program ROM and character ROM. The character ROM holds the font data and is separated from the program ROM to save CPU time. The CPU can still access the character ROM via a DMA interface including wait cycles. The WST layer and the additional OSD layer can also access the CPU memory via the same DMA interface. The CPU is supported by some glue logic such as timer, watchdog and interrupt controller and communicates with the outside world via the I2C-Bus.

2.2. Teletext Acquisition
The only task of the slicer circuit is to extract teletext lines from the incoming composite video signal and to store them into the acquisition scratch buffer of the external DRAM. No page selection is done at this hardware level. Two analog sources can be connected, thus it is possible to receive text from one channel while watching another on the screen. After clamping and AGC amplifer the analog video signal is converted into binary data. Sync separation is done by a sync slicer and a horizontal PLL, which generate the horizontal and vertical timing. By these means no external sync signals are needed and any available signal source can be used for teletext reception. The teletext information itself is acquired using adaptive slicers on bit and byte level with soft error detection to decrease the bit error rate under bad reception conditions. The slicer can be programmed to different bit rates for reception of PAL, NTSC or MAC world system tele- text as well as VPS,WSS or CAPTION signals.

2.3. Teletext Page Management
As a state-of-the-art teletext decoder the TPU3040 is able to store and manage a sufficient number of teletext pages to absorb the annoying transmission cycle times. The number of available pages is only limited by the memory size. With an intelligent software and a 16 Mbit DRAM it is possible to store and to control more than 2000 teletext pages. The management of such a data base is a typical soft- ware task and is therefore performed by the 65C02. Using a fixed length page table with one entry for every possible page, the software distributes the content of the acquisition scratch buffer among the page memory. The page size is fixed to 1 KByte, only ghost rows are chained in 128-byte segments to avoid unused memory space.

2.4. Display Page Generation
A stored teletext page cannot be displayed directly, because of the row-adaptive transmission and the level 2 enhancements (row 26–29). Therefore the CPU has to generate a display page buffer, separated into level 1 data such as character codes and spacing attributes and into level 2 data, such as character set extension and non-spacing attributes. This is done by using a slightly modified stack model, in which one pointer bit for every character location indicates the presence of additional parallel attributes. Fig. 2–2 shows the organization of the stack row buffer. In this stack model the number of non- spacing attributes per row is limited to 40, which agrees with the WST and CEPT specification.

2.5. WST Display Controller
The display controller includes two row buffers. The first row buffer holds a copy of a teletext row from the display page buffer. This decreases the data rate through the DRAM interface by a factor of 10 or 8, because new teletext row data is needed only after 10 lines in PAL or 8 lines in NTSC mode. The second row buffer stores all display attributes in parallel, to allow level 2 display with- out additional decoding. To present a WST level 2 display, the teletext display controller has to evaluate the following attributes in parallel, that is for every character location:
– 10-bit character code
– 5-bit foreground color
– 5-bit background color
– 2-bit size
– 5-bit flash
– 1-bit invert
– 1-bit separated
– 1-bit conceal
– 1-bit underline
– 1-bit boxing/window
Additional attributes are defined to improve the display
of CAPTION and OSD text:
– 1-bit italics
– 1-bit shadow
The display controller delivers 5-bit digital color information, a shadow signal for contrast reduction and a fast blank signal. The color bus can be used to address external color-look-up-tables (CLUT) which are part of modern digital TV systems, such as the DIGIT 3000. By this means, the full level 2 color spectrum can be dis- played. For simple level 1 applications only 3 bits of the color bus are converted into analog RGB signals on chip.
2.6. Character Generator
Characters are displayed with a 10x10 pixel resolution in PAL and 10x8 pixel resolution in NTSC mode. Pixel clock is 10.125 MHz, derived from the main clock of 20.25 MHz. To get 10-bit pixel information two memory cycles are needed. The character font is part of the mask-programmable ROM, but supplied with its own bus structure (see Fig. 4–1). By this means the data transfer between character ROM and teletext display controller does not stop the CPU, which is important in the case of doubled line frequency. Both bus structures are connected via a memory inter- face which allows cross-connections using DMA or wait cycles. As the number of addressable characters is 1024, the maximum character font size is 12800 byte. In this case part of the character font can be shifted into the program ROM which causes DMA cycles. Therefore only less frequently used characters should be placed into the program ROM. Vice versa seldom used CPU code can be put into the character ROM. The WST specification defines a number of 7-bit code tables, which are filled with 96 characters only. In the G0 code table some characters have several language de- pendent variations. Additionally characters from the G0 code table can be combined with diacritical marks from the G2 code table (row 26). Thus it is not possible to simply transform the code tables into a continuous font ROM without getting unused ROM space and multiple defined character fonts. The character ROM is optimized by reorganizing the code table structure of the WST specification. The whole character font is subdivided into blocks of 32 characters which are mapped to the WST character sets via a mask programmable mapping ROM (see Fig. 4–5). The character set selection is done via software.

2.7. OSD Layer
Apart from the WST layer, there is also one additional OSD layer on chip. The OSD layer accesses the CPU memory via DMA to read text and character font information. The RGB outputs of the OSD layer can have higher priority than the WST layer outputs. Thus it is possible to overlay the teletext display with an additional lay- er for user guidance. time faster than 120 ns. The data rate calculation already takes into account the required refresh cycles. The DRAM interface has to handle 3 asynchronous data streams. The CPU needs access to every memory location of the DRAM. During VBI the slicer writes up to 22 teletext lines of 43 bytes into the acquisition scratch memory. Alternatively the slicer can store MAC packets of 90 bytes into the acquisition scratch. During text display the display controller copies teletext rows from display memory into its internal row buffer. The lower data rate of the slow mode makes some restrictions necessary. With 6.1 Mbit/s it is no longer possible to run slicer and display in parallel. Only MAC packet teletext can still be acquired asynchronously because of the lower bit rate. VBI teletext can only be acquired while the display controller is inactive (synchronous acquisition and display).

2.9. Applications
The field of applications covers analog and digital TV sets, set-top satellite decoders, video recorders and home computers. For example,  Two analog sources are connected and the output is analog RGB, synchronized with an external sync signal or self-timed. Page selection and other user actions are sent to the TPU 3040 via I2C-Bus using a high level command language.

SIEMENS SDA9187-2X  Analog-Digital-Converter for Picture in Picture

Features
 3 separate A/D-converters

 Resolution: 6 bit  Sampling rate: 13.5 MHz, 3.375 MHz

 Clamping circuit for the input signals

 Adjustable delay for the luminance signal (8 steps)

 Color difference signals Y and V can be inverted

 Internal clock synchronization by sandcastle signal

 System clock generation for picture insertion processor
 

 The 9187-2X converts the analog output signals Y, U, V of any color decorder into the digital input signals of the PIP PLUS Processor SDA 9188-3X. A clock generator which is synchronized to the sync signals of the insert channel is integrated on this chip. At the input for the channel of the inset picture an analog CVBS signal is required. An analog operating chroma decoder as well as a sync processor are generating the analog luminance- and chrominance signals Y, U, V and the horizontal and vertical sync signals of the inset picture. Y, U and V are digitized by 6-bit flash converters and output in a format that matches the interface of the PIP-processor SDA 9188-3X. Furthermore, with the aid of PLL, the SDA 9187-2X generates the line locked clock LL3 (nominal 13.5 MHz) and the blanking signal BLN.
 
 The luminance signal Y and the chrominance signals U, V are fed to the SDA 9187-2X by means of coupling capacitors. The color subcarrier must be filtered out of Y. The sampling rate of the three 6-bit A/D-flash converters is the LL3 clock. The dynamic range of the converter is the range between VREFH and VREFL. The black level of Y is clamped to VREFL. The luminance information is generated as a 6-bit binary offset code. The digitized luminance signal Y can be delayed to compensate the different signal propagation times of the preceding decoder. This delay can be set in increments of two LL3 cycles in a range of 0 through 15 LL3 cycles (nominally 0 to 1.11) on pins YD0, YD1 and YD2. The white level of U and V is clamped to 0.5 × (VREFH + VREFL). U, V are then converted into a 6-bit two’s complement code. The digitized U-, V-signals can be inverted via the CNEG-control input. A multiplexer selects every fourth U-, V-sample and applies this 10-bit information in four clock cycles in a nibble format to pins UV (0:3).
 
 The horizontal PLL, consisting of a horizontal timer, phase comparator and VCO, generates the line-locked picture-in-picture system clock LL3 and the internal chip timing. The horizontal timer divides the LL3-clock by 864 (the same for PAL and NTSC) and applies this signal as a horizontal reference signal to the phase comparator. The external horizontal signal is decoded from the sandcastle signal and matched in its pulse width (= 345 LL3-cycles) to the reference signal. The digital phase comparator is frequency- and phase-sensitive and produces current pulses at its output. The up/down pulses of the phase comparator are filtered on pin RC. The filtered signal is the control voltage of the VCO. The horizontal timer also determines the start time and the width of the clamping pulse as well as the location of the blanking signal BLN, which in turn defines the horizontal duration of the picture information on the Y output and should be synchronous with it. BLN is consequently delayed to the same degree as Y.
 
Clamping An internal clamping circuit is provided in each of the three analog channels. The external clamping capacitance is loaded by on chip current sources during clamping (typ. 100 μA). So the loading time depends on the values of the ext. clamping capacitor.

SIEMENS SDA9188-3X Picture-in-Picture Processor with On-Chip PLL


 
On-chip PLL
Full frame display for 50/60 Hz in order to increase the vertical resolution and to suppress moving artifacts.

Compatibility to the 16:9 display format by means of independent setting of the vertical and horizontal decimation factors and the width of the border frame

Decimation of the Y, U, V data for pictures sizes 1/9 and 1/16 with 6 bits width of the input word without rounding error

Intermediate storage of the inset picture (on-chip-memory) RGB- or Y-, U-, V-signal generation

100% pin- and software compatible with SDA 9188X if external PLL is used Increased bandwidth of analog outputs due to higher output currents New select function for multi-PIP feature

Functional Description
The SDA 9188-3X Picture-in-Picture (PIP) processor with on-chip PLL combines two asynchronous picture sources so that a small moving picture (the inset picture) can be superimposed in a moving picture of normal size (the parent picture). The components of the video signal of the inset source have to be fed in a digitized form to the SDA 9188-3X (figure 1). Amplitude resolution of the signal components is 6 bit at a sampling rate of 13.5 MHz for the luminance signal and 3.375 MHz for the crominance signals.

The PIP processor SDA 9188-3X handles picture reduction (decimation with horizontally and vertically acting filters), intermediate data storage in an integrated image memory (169.812 bits) as well as the output of the decimated picture. The picture can be set 1/9 or 1/16 of its original size. In order to indicate the border between parent picture and inset picture the inset picture can be surrounded with a frame: its width is adjustable in 2 stages and its brightness in 16 stages. Different signal sources can be identified by using different framing colors. The four corners of the parent picture are possible positions for the inset picture. The inset picture can also be inserted as a still picture, independently of the parent picture. The output signals of the SDA 9188-3X are analog. Either RGB or Y, U, V signals can be output, whereby a 6-bit broadband conversion is obtained for all components. Clamping for RGB output signal is performed in an RGB processor (e.g. TDA 4685). Only a few additional devices are required for a complete picture-in-picture system. Application circuits 1a and 1b illustrate the use of the PIP device. If the CVBS input signal is to be decoded using an analog color decoder for the PIP, the analog/ digital interface for the inset picture (3 A/D Converter, SDA 9187-2X) performs the conversion of the Y, U, V components into digital signals as well as the generation of the inset clocks BLNI and LL3I. The SDA 9188-3X processes both 50 Hz/625 and 60 Hz/525 line signals. The field frequency can be 50/60 Hz or 100/120 Hz. For systems with Siemens Dig TV Feature box a field frequency of 100 Hz or 120 Hz is also possible by doubling the clock frequency LL3P (LL1.5P). Frame mode display with 50 Hz or 60 Hz can also be set via the I2C bus. Adaptation to the number of lines occurs automatically. If the field frequency in the parent and inset channels are different, artifacts may result in the picture. Synchronization with the parent channel is performed via the horizontal and vertical sync signals HSP/SAND and VSP. The clock frequency is 13.5 MHz (LL3P) without standard conversion and 27 MHz (LL1.5P) with standard conversion (100/120 Hz). The display clock is generated on chip. Optionally the external clock generator SDA 9086-3 can be used in the same way as with the SDA 9188X. The horizontal and vertical sync signals BLNI and VSI plus the LL3I clock (13.5 MHz) are used for synchronization with the inset source. The interface between inset and parent channel is done by the on-chip memory. The memory write access is controlled by the inset clock and the read access is controlled by the parent clock. The SELECT output signal inserts the inset picture into the parent picture driving an external analog switch, e.g. the TDA 4685. All operation modes of the SDA 9188-3X can be controlled via the I2C bus. Nine registers can be used.

Circuit Description
Data Transfer
The digital data are transferred under the control of LL3I, BLNI and VSI on pins YS0-YS5 and UVS0-UVS3. The decimated data are stored automatically. Either R, G, B, or Y, -U, -V analog signals are available at the outputs OUT1-OUT3. The validity of the signals is identified by SELECT = 1. In a digital system environment the input is controlled by LL3P, HSP and VSP. Inset Data Reduction The data rate at the inputs YS0-YS5, UVS0-UVS3 is 13.5 MHz in multiplexed format, see figure 1. In order to reduce the quantity of data which have to be stored and to prevent artifacts in the inset picture, nine pixels are processed into one inset pixel for a 1/9 picture. For the 1/16 picture 16 pixels are processed into one inset pixel. This is done by horizontal and vertical averaging of pixels: The characteristic of decimation for the luminance signal is 1-1-1 for 1/9- and 1-1-1-1 for 1/16 picture. Crominance signal: 1-2-1 for 1/9 and 1-1-1-1 for 1/16 picture.

During the decimation process the following parts of the original picture are processed:
1.
2.
DECHOR/DECVER = 0(1/9-Picture)
during 625 line mode:
during 525 line mode:
SIZE = 1(1/16-Picture):
during 625 line mode:
during 525 line mode:
Line 36 ... 302; Pixel 13 ... 636
Line 26 ... 256; Pixel 13 ... 636
Line 36 ... 303; Pixel 17 ... 640
Line 26 ... 257; Pixel 17 ... 640
Temporary Storage of Inset Picture
The PIP memory has a capacity of 169.812 bits. The memory organization is 89 × 212 × 9 bits. Data are written in with the inset and read out with the parent clock frequency. For standard video signals with 50 or 60 Hz a full frame display is possible. To assure a correct display of the two fields, the control of the memory is done dependently of the field and the phase relation of the Inset and Parent channel. Frame mode display is only possible for standard 50 Hz/ 60 Hz video signals. Certain VCR-functions (e.g. fast forward-mode), non interlaced signals and 50 Hz/60 Hz mixed-mode would cause inacceptable picture distortions. Under these conditions the SDA 9188-3X switches automatically into field mode display. Also freezed pictures can only be displayed in the field-mode. Output of Data in Parent Window The four corners of the parent picture are foreseen as positions for inserting the inset picture. To enable compatibility to different system configurations, readout from memory can be shifted horizontally in 63 steps by max. 252 LL3P cycles and vertically in 15 steps by max. 30 lines in the parent field setting the control bits RDH and RDV in control register 2 and 3. The coordinates BRP, BRL of the normal location of all four insertion positions are given in table 3 for RDH = RDV = 8.
The SELECT signal goes high during the display of the inset picture. Outside of the inset picture SELECT signal is low and the analog outputs OUT1-OUT3 provide the black level. The external wiring can produce a delay between the SELECT signal and the analog outputs. This delay can be compensated by bits SD0-SD2 in register 2 via the I2C bus. A frame with one of eight colors can be inserted using control bits FRON, COL0-2. The width of the frame is fixed by FRWV at three or two lines and by FRWH at six or four pixels. The brightness can be adjusted in 16 stages.

TDA8175 TV VERTICAL DEFLECTION OUTPUT CIRCUIT:

 DESCRIPTION
The TDA8175 is a monolithic integrated circuit in
HEPTAWATT package. It is a high efficiency power
booster for direct driving of vertical windings of TV
yokes. It is intended for use in Color and B & W
television sets as well as in monitors and displays.

 .POWER AMPLIFIER
 .FLYBACK GENERATOR 
.AUTOMATIC PUMPING COMPENSATION 
.THERMAL PROTECTION .
.REFERENCE VOLTAGE

ABSOLUTE MAXIMUMRATINGS
Symbol Parameter Value Unit
VS Supply Voltage (PIn 2) 35 V
V5, V6 Flyback Peak Voltage 60 V
V3 Voltage at PIn 3 +VS
V1, V7 Amplifier Input Voltage +VS
IO Output Peak Current (non-repetitive, t = 2ms) 2.5 A
IO Output Peak Current at :
f = 50 or 60Hz, t 3 10ms
f = 50 or 60Hz, t > 10ms
32
AA
I3 Pin 3 DC Current at V5 < V2 100 mA
I3 Pin 3 Peak-to-peak Flyback Current at f = 50 or 60Hz, tfly 3 1.5ms 3 A
Ptot Total Power Dissipation at Tcase = 70oC 20 W
Tj, Tstg Storage and Junction Temperature -40, +150 oC.

THERMAL PROTECTION
The thermal protection circuit intervenes when the
odie temperatures reaches 150 C and turns-off the
output power device.
PUMPING COMPENSATION
The device incorporates a special preampliflier, the
gain of which varies with changes in supply voltage.
This functionallows perfect compensationof height
variations caused by changes in brightness.

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Further References:
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Further Information
L. Ozawa, Cathodoluminescence: Theory and Applications, New York: Kodansha, 1990.
V. K. Zworykin and G. A. Morton, Television: The Electronics of Image Transmission in Color and Mono-
chrome, New York: John Wiley & Sons, 1954.
B. Wandell, The foundations of color measurement and color perception, Society for Information Display
International Symposium, Conference Seminar M-1, 1993. A nice brief introduction to color science
(31 pages).
Electronic Industries Association (EIA), 2500 Wilson Blvd., Arlington, VA 22201 (Internet: www.eia.org).
The Electronic Industries Association maintains a collection of over 1000 current engineering publi-
cations and standards. The EIA is an excellent source for information on CRT engineering, standards,
phosphors, safety, market information, and electronics in general.
The Society for Information Display (SID), 1526 Brookhollow Dr., Suite 82, Santa Ana, CA 92705-5421
(Internet: www.display.org). The Society for Information Display is a good source of engineering
research and development information on CRTs and information display technology in general.

Internet Resources:
The following is a brief list of places to begin looking on the World Wide Web for information on CRTs
and displays, standards, metrics, and current research. Also many of the manufacturers listed in Table
91.3 maintain Web sites with useful information.
The Society for Information Display
The Society of Motion Picture and Television Engineers
The Institute of Electrical and Electronics Engineers
The Electronic Industries Association
National Information Display Laboratory
The International Society for Optical Engineering
The Optical Society of America
Electronics & Electrical Engineering Laboratory
National Institute of Standards and Technology (NIST)
The Federal Communications Commission

www.display.org
www.smpte.org
www.ieee.org
www.eia.org
www.nta.org
www.spie.org
www.osa.org
www.eeel.nist.gov
www.nist.gov
www.fcc.gov


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