JVC AV-32WP2EN CHASSIS MB POWER AND DEFLECTION + EHT PANEL BOARD SMB-2001-U2

The supply is based on MOTOROLA MC44603p which is a MIXED FREQUENCY MODE GREENLINE PWM CONTROLLER:Fixed Frequency, Variable Frequency,
Standby Mode.

The MC44603 is an enhanced high performance controller that is
specifically designed for off–line and dc–to–dc converter applications. This
device has the unique ability of automatically changing operating modes if
the converter output is overloaded, unloaded, or shorted, offering the
designer additional protection for increased system reliability. The MC44603
has several distinguishing features when compared to conventional SMPS
controllers. These features consist of a foldback facility for overload
protection, a standby mode when the converter output is slightly loaded, a
demagnetization detection for reduced switching stresses on transistor and
diodes, and a high current totem pole output ideally suited for driving a power
MOSFET. It can also be used for driving a bipolar transistor in low power
converters (< 150 W). It is optimized to operate in discontinuous mode but
can also operate in continuous mode. Its advanced design allows use in
current mode or voltage mode control applications.

Current or Voltage Mode Controller
• Operation up to 250 kHz Output Switching Frequency
• Inherent Feed Forward Compensation
• Latching PWM for Cycle–by–Cycle Current Limiting
• Oscillator with Precise Frequency Control
High Flexibility
• Externally Programmable Reference Current
• Secondary or Primary Sensing
• Synchronization Facility
• High Current Totem Pole Output
• Undervoltage Lockout with Hysteresis
Safety/Protection Features
• Overvoltage Protection Against Open Current and Open Voltage Loop
• Protection Against Short Circuit on Oscillator Pin
• Fully Programmable Foldback
• Soft–Start Feature
• Accurate Maximum Duty Cycle Setting
• Demagnetization (Zero Current Detection) Protection
• Internally Trimmed Reference
GreenLine Controller: Low Power Consumption in Standby Mode
• Low Startup and Operating Current
• Fully Programmable Standby Mode
• Controlled Frequency Reduction in Standby Mode
• Low dV/dT for Low EMI Radiation.

A Pulse Width Modulation (PWM) control circuit is used in a switched-mode power supply (SMPS) having a normal mode and a standby mode, for controlling and regulating the SMPS. An input of the PWM control circuit is arranged to receive a signal indicating an amount of current supplied by the supply. An over-current determining arrangement provides an over-current signal in the event of there being an over-current condition in the signal indicating the amount of current supplied by the supply. A further input of the PWM control circuit receives a regulation signal in the event of there being a regulation output from circuitry coupled to receive power from the SMPS. A logic circuit within the PWM control circuit compares the over-current signal and the regulation signal in order to detennine whether the switched-mode power supply is in standby mode or normal mode, thus avoiding the need for a dedicated control pin to indicate standby and normal modes.
This invention relates to a pulse-width modulated controller, and particularly for such a controller when used to control a switched-mode power supply. Background of the Invention
Switched-Mode Power Supplies (SMPS) are being increasingly used in many domestic and industrial applications. In applications such as television or computer monitor, the application may require a number of states or modes of operation. A first 'off' mode occurs when there is no power supplied to a device (or when a master switch is off); a second 'on' mode occurs when the device is switched on an operating normally; and a third mode (referred to as a standby mode) occurs when the device is to remain powered, but with reduced functions and reduced power consumption.
 Such a switched-mode power supply circuit (further referred to as power supply) is known from Motorola Semiconductor technical data "high flexibility green SMPS controller", in which an integrated circuit for controlling the power supply (further referred to as control circuit), having type number MC44603, is described. In the normal on-state (further referred to as operating mode), this known power supply generates a plurality of operating-output DC voltages (further referred to as operating voltages) applying a voltage to those circuits in an electronic apparatus which should be active in the operating mode. The known power supply further generates a standby output DC voltage (further referred to as standby voltage), both in the operating mode and in a standby mode for applying a voltage to those circuits which should be active in the standby mode.

The known power supply is provided with a transformer having a primary winding and a plurality of secondary windings. A first secondary winding supplies the standby voltage, both in the operating mode and in the standby mode. In the operating mode, an operating voltage from a second secondary winding is fed back to the control circuit via a feedback circuit. The control circuit controls on and off-times of a repetitive switching transistor which is arranged in series with the primary winding for stabilizing the operating voltage generated by the second secondary winding. The feedback circuit includes an optocoupler for transferring feedback information from the secondary side of the power supply to the primary side via a DC separation.

The control circuit brings the power supply to the standby mode if the peak current through the switching transistor has fallen below a given value, which is the case if the power consumption at the secondary side decreases considerably. The power consumption at the secondary side decreases considerably if the current taken from the operating voltage is reduced considerably by inactivating the circuit connected to the operating voltage or by decoupling this circuit from the operating voltage. The standby voltage is stabilized indirectly in the standby mode by stabilizing the operating voltage. To improve the efficiency of the power supply in the standby mode, in which the power supply supplies a small power, the switching transistor is switched at a lower frequency than in the operating mode.

A standby mode may be encountered in a television via an 'off' switch of a remote control, which typically does not switch the television fully off, but allows certain circuitry within the television to remain powered, so that if the 'on' button of the remote control is pressed, the television will return to the 'on' mode.
There is a need to reduce the power consumed by the SMPS during standby mode, so that use of mains electricity is reduced. At present there is a goal to reduce the power consumption to a value of the order of 1 Watt.
Burst mode SMPS are known, which have an efficient power consumption in standby mode. However, there is a problem with SMPS operating in a burst mode which is that the periodicity of the bursts (or the frequency of bursting) will typically lie within the audible frequency range. Thus tends to generate audible noise for reasons which are not well understood and are certainly not predictable in advance of a finished prototype. Altering the frequency of bursting can help to reduce the noise as can altering the peak current generated by the SMPS during each burst (note this may be achieved if the frequency of bursting - or at any rate the duty rate of bursting - is increased without reducing the averaged power supplied to the microprocessor on the secondary side of the SMPS).
Typically, however, there is no way to alter the frequency of bursting meaning that designers must simply hope that the finished product is not too noisy in standby mode.
-------------------------------------------------------------------------------


TDA9151B Programmable deflection controller

GENERAL DESCRIPTION The TDA9151B is a programmable deflection controller contained in a 20-pin DIP package and constructed using BIMOS technology. This high performance synchronization and DC deflection processor has been especially designed for use in both digital and analog based TV receivers and monitors, and serves horizontal and vertical deflection functions for all TV standards. The TDA9151B uses a line-locked clock at 6.75, 13.5 or 27 MHz, depending on the line frequency and application, and requires only a few external components. The device can be programmed in a self-adaptive mode or in a programmable fixed slope mode. Selection of these modes and a large number of other functions is fully programmable via the I2C-bus. FEATURES
General
· 6.75, 13.5 and 27 MHz clock frequency
· Few external components
· Synchronous logic
· I2C-bus controlled
· Easy interfacing
· Low power

· ESD protection
· Flash detection with restart
· Two-level sandcastle pulse.
Vertical deflection
· 16-bit precision vertical scan
· Self adaptive or programmable fixed slope mode
· DC coupled deflection to prevent picture bounce
· Programmable fixed compression to 75%
· Programmable vertical expansion in the fixed slope
mode
· S-correction can be preset
· S-correction setting independent of the field frequency
· Differential output for high DC stability
· Current source outputs for high EMC immunity
· Programmable de-interlace phase.
East-West correction
· DC coupled EW correction to prevent picture bounce
· 2nd and 4th order geometry correction can be preset
· Trapezium correction
· Geometry correction settings are independent of field
frequency
· Self adaptive Bult generator prevents ringing of the
horizontal deflection
· Current source output for high EMC immunity.
Horizontal deflection
· Phase 2 loop with low jitter

· Internal loop filter
· Dual slicer horizontal flyback input
· Soft start by I2C-bus
· Over voltage protection/detection with selection and
status bit.
EHT correction
· Input selection between aquadag or EHT bleeder
· Internal filter.

FUNCTIONAL DESCRIPTION
Input signals (pins 12, 13, 14, 17 and 18)
The TDA9151B requires three signals for minimum
operation (apart from the supply). These signals are the
line-locked clock (LLC) and the two I2C-bus signals (SDA
and SCL). Without the LLC the device will not operate
because the internal synchronous logic uses the LLC as
the system clock.
I2C-bus transmissions are required to enable the device to
perform its required tasks. Once started the IC will use the
HA and/or VA inputs for synchronization. If the LLC is not
present the outputs will be switched off and all operations
discarded (if the LLC is not present the line drive will be
inhibited within 2 ms, the EW output current will drop to
zero and the vertical output current will drop to 20% of the
adjusted value within 100 ms). The SDA and SCL inputs
meet the I2C-bus specification, the other three inputs are
TTL compatible.
The LLC frequency can be divided-by-two internally by
connecting LLCS (pin 5) to ground thereby enabling the
prescaler.

Horizontal part (pins 1, 2, 13, 19 and 20
SYNCHRONIZATION PULSE
The HA input (pin 13) is a TTL-compatible CMOS input.
Pulses on this input have to fulfil the timing requirements
as illustrated in Fig.6. For correct detection the minimum
pulse width for both the HIGH and LOW periods is 2
internal clock periods.
FLYBACK INPUT PULSE
The HFB input (pin 1) is a CMOS input. The delay of the
centre of the flyback pulse to the leading edge of the HA
pulse can be set via the I2C-bus with the horizontal phase
byte (subaddress 08), as illustrated in Fig.7.
The resolution is 6-bit.
OUTPUT PULSE
The HOUT pulse (pin 20) is an open-drain NMOS output.
The duty factor for this output is typically 52¤48
(conducting/non-conducting) during normal operation. A
soft start causes the duty factor to increase linearly from 5
to 52% over a minimum period of 2000 lines in 2000 steps.
OFF-CENTRE SHIFT
The OFCS output (pin 19) is a push-pull CMOS output
which is driven by a pulse-width modulated DAC.
By using a suitable interface, the output signal can be used
for off-centre shift correction in the horizontal output stage.
This correction is required for HDTV tubes with a 16 ´ 9
aspect ratio and is useful for high performance flat square
tubes to obtain the required horizontal linearity. For
applications where off-centre correction is not required,
the output can be used as an auxiliary DAC. The OFCS
signal is phase-locked with the line frequency. The
off-centre shift can be set via the I2C-bus, subaddress 09,
with a 6-bit resolution as illustrated in Fig.8.
SANDCASTLE
The DSC input/output (pin 2) acts as a sandcastle
generating output and a guard sensing input. As an output
it provides 2 levels (apart from the base level), one for the
horizontal and vertical blanking and the other for the video
clamping. As an input it acts as a current sensor during the
vertical blanking interval for guard detection.
CLAMPING PULSE
The clamping pulse width is 21 internal clock periods. The
shift, with respect to HA can be varied from 35 to 49 clock
periods in 7 steps via the I2C-bus, clamp shift byte
subaddress 0A, as illustrated in Fig.9. It is possible to
suppress the clamping pulse during wait, stop and
protection modes with control bit CSU. This will avoid
unwanted reset of the TDA4680/81 (only used in those
circuits).
HORIZONTAL BLANKING
The start of the horizontal blanking pulse is minimum 38
and maximum 41 clock periods before the centre of the
flyback pulse, depending on the fclk/fH ratio K in
accordance with 41 - (432 - K).
Stop of the horizontal blanking pulse is determined by the
trailing edge of the HFB pulse at the horizontal blanking
slicing level crossing as illustrated in Fig.10.
VERTICAL BLANKING
The vertical blanking pulse starts two internal clock pulses
after the rising edge of the VA pulse. During this interval a
small guard pulse, generated during flyback by the vertical
power output stage, must be inserted. Stop vertical
blanking is effected at the end of the blanking interval only
when the guard pulse is present (see Section “Vertical
guard”).
The start scan setting determines the end of vertical
blanking with a 6-bit resolution in steps of one line via the
I2C-bus subaddress 02 (see Figs 11, 12 and 13).
VERTICAL GUARD
In the vertical blanking interval a small unblanking pulse is
inserted. This pulse must be filled-in by a blanking pulse or
guard pulse from the vertical power output stage which
was generated during the flyback period. In this condition
the sandcastle output acts as guard detection input and
requires a minimum 800 mA input current. This current is
sensed during the unblanking period. Vertical blanking is
only stopped at the end of the blanking interval when the
inserted pulse is present. In this way the picture tube is
protected against damage in the event of missing or
malfunctioning vertical deflection.


VERTICAL GEOMETRY PROCESSING
The vertical geometry processing is DC-coupled and
therefore independent of field frequency. The external
resistive conversion (RCONV) at pin 8 sets the reference
current for both the vertical and EW geometry processing.
A useful range is 100 to 150 mA, the recommended value
is 120 mA.
VERTICAL OUTPUTS
The vertical outputs VOUTA and VOUTB on pins 10 and 11
together form a differential current output. The vertical
amplitude can be varied over the range 80 to 120% in
63 steps via the I2C-bus (subaddress 00). Vertical
S-correction is also applied to these outputs and can be
set from 0 to 16% by subaddress 01 with a 6-bit resolution.
The vertical off-centre shift (OFCS) shifts the vertical
deflection current zero crossing with respect to the EW
parabola bottom. The control range is -1.5 to +1.5%
(±1¤8 ´ I8) in 7 steps set by the least significant nibble at
subaddress 03.
EW GEOMETRY PROCESSING
The EW geometry processing is DC coupled and therefore
independent of field frequency. RCONV sets the reference
current for both the vertical and EW geometry processing.
The EW output is an ESD-protected single-ended current
output.
The EW width/width ratio can be set from 100 to 80% in
63 steps via subaddress 04 and the EW parabola/width
ratio from 0 to 20% via subaddress 05. The EW
corner/EW parabola ratio has a control range of -40 to 0%
in 63 steps via subaddress 06.
The EW trapezium correction can be set from
-1.5 to +1.5% in 7 steps via the most significant nibble at
subaddress 03.
BULT GENERATOR
The Bult generator makes the EW waveform continuous
(see Fig.21).
Protection input (pin 3)
The protection input (PROT) is a CMOS input.
The input voltage must be EHT scaled and has the
following characteristics:
Two modes of protection are available with the aid of
control bit PRD.
· With PRD = logic 1 the protection mode is selected,
HOUT will be defeated and the PROT bit in the status
word is set if the input voltage is above 3.9 V. Thus the
deflection stops and EW output current is zero, while the
vertical output current is reduced to 20% of the adjusted
value. A new start of the circuit is I2C-bus controlled with
the user software.
· With PRD = logic 0 the detection mode is selected,
HOUT will not be defeated and the over voltage
information is only written in the PROT status bit and can
be read by the I2C-bus.
All further actions, such as a write of the LFSS bit, are
achieved by the I2C-bus. They depend on the
configuration used and are defined by user software.
Flash detection/protection input (pin 9)
The FLASH input is a CMOS input with an internal pull-up
current of approximately 8 mA.
When a negative-going edge crosses the 0.75 V level a
restart will be executed with a soft start of approximately
2000 lines, such as in the soft-start mode. When the
function is not used pin 9 can be connected to ground, VCC
or left open-circuit, the internal pull-up current source will
prevent any problems. However a hard wired connection
to VCC or ground is recommended when the function is not
used.

EHT compensation (pin 7)
The EHT input is a CMOS input.
The EHT compensation input permits scan amplitude
modulation should the EHT supply not be perfect. For
correct tracking of the vertical and horizontal deflection the
gain of the EW output stage, provided by the ratio
RCONV-EW/RCONV, must be 1¤16Vscan ´ Vref (see Fig.15).
The input for EHT compensation can be derived from an
EHT bleeder or from the picture tubes aquadag
(subaddress 0B, bit BLDS).
EHT compensation can be set via subaddress 07 in
63 steps allowing a scan modulation range from
-10 to +9.7%.

Other References:

 

 MOTOROLA: "GreenLine PWM Controller" DATA SHEET MC44603, 28 February 1995 (1995-02-28), pages 1-24, XP009057599
PHILIPS SEMICONDUCTORS: "200W SMPS with TEA1504" APPLICATION NOTE AN98011, 1998, pages 1-22, XP001236144
PHILIPS SEMICONDUCTORS: "GreenChip SMPS control IC TEA1504" DATA SHEET, 7 December 1999 (1999-12-07), pages 1-20, XP001236145

 

Motorola, Inc. Hogh Performance Current Mode Controllers,Motorola Analog IC Device Data for type UC3842, pp. 1-15 1996. No Month.
Motorola Inc. TV Horizontal ProcessorMC1391 pp. 1-6 MC1391/D 1996. No Month.
Mitsubishi Synchronization Deflection System Control PWM ICdata sheet for M62500P pp.1-77 undated.
Mitsubishi Sync Signal ProcessorIC data sheet for M52347SP pp. 1-16 updated.
NEC Bipolar Analog Integrated Circuit .mu.PC1883 pp. 1-32 1995, with English translation pp. 1-23. No Month.
Goldstar, Goldstar Color Monitor Service Manual,Jun. 1994, cover sheet, pp. 34-37.
Panasonic Multi-Scan Color CRT Displaymodel TX-D2162 Service Manual pp. 1-81 dated 1996. No Month.
U.S. Patent Application No. 09/130,953, D.R. jackson, High-Voltage Power Supply For Video Display Apparatus,Filed Aug. 7, 1998.