The METZ 7096 CLASSIC COLOR (CH679G) CHASSIS 679G has a completely modular approach, see pictures, and it's quite complex expecially in the power supply / horizontal deflection parts.
Was even first METZ TV COLOR CHASSIS ground isolated from mains and featuring PHILIPS 30AX CRT TUBE.
TDA2541 IF AMPLIFIER WITH DEMODULATOR AND AFC
DESCRIPTION
The TDA2540 and 2541 are IF amplifier and A.M.
demodulator circuits for colour and black and white
televisionreceiversusingPNPorNPNtuners. They
are intended for reception of negative or positive
modulation CCIR standard.
They
incorporate the following functions : .Gain controlled amplifier
.Synchronous demodulator .White spot inverter .Video preamplifier with
noise protection .Switchable AFC .AGC with noise gating .Tuner AGC
output (NPN tuner for 2540)-(PNP
tuner for 2541) .VCR switch for video output inhibition (VCR
play back).
SGS-THOMSON TDA2030 14W Hi-Fi AUDIO AMPLIFIER
DESCRIPTION
The TDA2030 is a monolithic integrated circuit in
Pentawatt package, intended for use as a low
frequency class AB amplifier. Typically it provides
14W output power (d = 0.5%) at 14V/4Ω;at ± 14V
the guaranteedoutput poweris 12W on a 4Ω load
and 8Won a 8Ω (DIN45500).
TheTDA2030provideshighoutputcurrentandhas
very lowharmonic and cross-over distortion.
Further the device incorporates an original (and
patented) short circuit protection system compris-
ing an arrangement for automatically limiting the
dissipated power so as to keep the working point
of the outputtransistorswithin their safe operating
area.A conventionalthermal shut-downsystem is
also included.
SHORT CIRCUIT PROTECTION
The TDA2030 has an originalc ircuitwhichlimitsthe
current of the output transistors.Fig.18 showsthat
the maximum output current is a function of the
collector emitter voltage; hence the output transis-
tors work within their safe operating area (Fig. 2).
This functioncan thereforebe consideredas being
peak power limiting rather than simple current lim-
iting.
It reducesthe possibility that the devicegetsdam-
aged during an accidental short circuit from AC
output to ground.
THERMAL SHUT-DOWN
The presenceof a thermallimiting circuit offersthe
following advantages:
1. An overload on the output (even if it is perma-
nent),oranabovelimitambienttemperaturecan
be easily supported since the Tj cannot be
higher than 150°C.
2. The heatsinkcan havea smaller factorof safety
compared with that of a conventional circuit.
There is no possibility of devicedamage due to
high junctiontemperature.If for any reason,the
junctiontemperatureincreasesup to 150°C, the
thermal shut-down simply reduces the power
dissipationat the current consumption.
The maximum allowable power dissipation de-
pendsuponthe sizeof the externalheatsink(i.e.its
thermal resistance); fig. 22 shows this dissipable
power as a function of ambient temperature for
differentthermalresistance.
METZ 7096 CLASSIC COLOR (CH679G) CHASSIS 679G AMBIENT LIGHT RESPONSIVE CONTROL OF BRIGHTNESS, CONTRAST AND COLOR SATURATION
1.
In a color television apparatus, a circuit for varying color display
characteristics in accordance with variations in ambient light
comprising: 2. In a color picture
display system having a display device comprising:
3. The display system of claim 2 with kinescope means
having a first set of electrodes and a second set of electrodes,
4. The display system of claim 2
with said light sensing means being responsive to the intensity of the
ambient light and said parameter varying in accordance with the
intensity of ambient light. 5.
The display system of claim 4 with said modifying means increasing the
gain of said luminance amplifying means at a greater rate than the
gain of said chroma amplifying means as said ambient light intensity
is increased. 6. A color
television apparatus comprising:
7. In a color television receiver:
8. The receiver of claim 7 with said modifying means comprising a
light dependent resistor means,
9. The receiver of claim 8 with second impedance means coupling said
light dependent resistor means to said luminance gain means to control
the gain of said luminance gain means.
10. The receiver of claim 9 with said second impedance means
comprising a parallel combination of capacitance and resistance.
11. The receiver of claim 7 with said
modifying means varying the gain of the luminance gain means at a
greater rate than the gain of the chroma gain means as ambient light is
varied. 12. The receiver of
claim 7 with said modifying means being responsive to the intensity of
ambient light and said parameter being varied as the intensity of the
ambient light is varied. 13. The
receiver of claim 7 with said modifying means attenuating the gain of
said luminance amplifying means approximately fifty percent more than
the gain of said chroma amplifying means, when the attenuation is
measured in decibels, as said ambient light intensity is decreased.
14. In a color television receiver:
Description:
BACKGROUND OF THE INVENTION
The
present invention relates generally to a television receiver control
system and more particularly to a control system for maintaining
proper balance between room lighting conditions and the level of
picture tube excitation in a color television receiver. More
especially the present invention functions to increase contrast,
intensity and chroma signal strength when the room lighting level
increases to diminish these parameters when the level of room lighting
decreases.
Conventional
television receivers, of course, have manually operable controls by
means of which a viewer may set the level of contrast, intensity, and
chroma signal strength to what he feels to be an optimum level for
given room lighting conditions. Under changed room lighting conditions,
the viewer will obtain the optimum viewing situation by changing
these manual controls to a new preferred level.
It is
also known in the prior art to automate this process for a black and
white television receiver, for example, as taught in the U.S. Pat. No.
3,165,582 to Korda, issued Jan. 12, 1965, and the French patent
1,223,058 issued in June of 1960.
It is accordingly
an object of the present invention to provide an automatic color
saturation control for a color television receiver by providing
separate, predetermined gains for the luminance and chroma for a given
change in ambient light. In the disclosed preferred embodiment, the
luminance signal is attenuated 3.3 dB and the chroma signal is
attenuated 2.1 dB for a change in ambient light from 100 footcandles to
0.1 footcandles, measured at the display face.
SUMMARY OF THE INVENTION
The
foregoing as well as numerous other objects and advantages of the
present invention are achieved by providing a light sensitive element in
a television receiver exposed to ambient light in the vicinity of the
receiver for separately controlling brightness, contrast and chroma
signal strength of the displayed picture in accordance with the level
of ambient light. The circuit of a preferred embodiment of the present
invention, in response to an increase of ambient light level,
functions to increase the gain of the luminance amplifier in a
relatively greater ratio than the increase in the gain of the
chrominance amplifier whereas when the ambient light level decreases
the respective gains of these two amplifiers are decreased, again,
with the change in the luminance signal being in a greater proportion
than the change in the chroma signal strength signal. By using the
teaching of this invention, other gain relationships between the
luminance components and chroma signal, for a given change in ambient
light, may be automatically attained to achieve a desired result of
luminance and color saturation.
BRIEF DESCRIPTION OF THE DRAWINGS
The
aforementioned and other objects, features and advantages of the
present invention will become more apparent from the following detailed
description thereof when considered in conjunction with the drawings
wherein:
FIG. 1 is a partial block diagram of a color television receiver employing the present invention;
FIG. 2 is a detailed schematic diagram of those portions of FIG. 1 embodying the present invention;
FIG. 3 illustrates chroma gain control characteristic curves for the circuit of FIG. 2; and
FIG. 4 is a graph showing changes in luminance and chroma signal strength according to changes in ambient light.
DESCRIPTION OF THE PREFERRED EMBODIMENT
Considering first FIG. 1 which
illustrates
generally in block diagram form a color television receiver embodying
the present invention, this receiver is seen to comprise a tuner and
radio frequency amplifier 11 for detecting and amplifying incoming
signals received on the antenna 13 and supplying those signals through
an appropriate heterodyning process to an intermediate frequency
amplifier 15. After detection in the detector 17, the luminance signals
are passed through a delay 19 which compensates for the delays
experienced by the chroma signal strength signals and then to the
luminance amplifier 21, which, of course, corresponds to the video
amplifier of a black and white receiver, to then be supplied to the
cathode ray tube 23. The luminance or video amplifier may also be
provided with gain control circuitry 25. An appropriate band pass
amplifier 27 may be employed to separate out the chroma signal strength
signals which are demodulated by the demodulator 29 in well known
fashion to provide the three color difference signals to grids in the
color cathode ray tube 23. While the present invention will be described
with respect to such color difference signals, it is equally
applicable to direct RGB color separation systems. An ambient light
level detector 31 such as a light dependent resistor of the cadmium
sulphide variety is physically located on the front of the television
receiver in such a position as to be exposed to the light levels in the
vicinity of the receiver so that its resistance varies inversely in
accordance with variations in the ambient light levels around the
receiver. These resistance variations are then employed to control the
gain of the luminance amplifier 21 by way of gain control 25 and to
control the gain of the chroma signal strength amplifier circuitry.
The
entire color demodulation process is only generally depicted in the
block diagram of FIG. 1 and is illustrated as a closed loop burst gain
controlled chroma amplifier system with auxiliary chroma gain control
introduced by way of the detector 33 from the ambient light level
detector 31. A burst gain controlled chroma amplifier circuit is
somewhat analogous to a black and white keyed AGC circuit and functions
to set the gain level of the amplifier 27 in accordance with the color
sync burst rather than the chroma signal level associated with a
particular picture. While the present invention is being described with
respect to this preferred type of gain control, it would, of course,
be possible, in television circuits employing DC gain controls for
chroma and/or contrast, to connect the ambient light tracking means to
these direct current control circuits. The gain controlled chroma
band pass amplifier, of course, supplies an output to a burst
amplifier 35 which in turn drives an automatic phase control system 37
for synchronizing the 3.58 megacycle oscillator 39 the output of
which is used in the color demodulation process.
Considering
now FIG. 2 which illustrates schematically in detail those portions
of the receiver of FIG. 1 necessary for a complete understanding of
the present invention, the light dependent resistor 41 is mounted near
the front of the television receiver in such a position as to
adequately receive the ambient lighting conditions in the vicinity of
the receiver. The resistance of this device is inversely proportional
to the intensity of light incident thereon. If the room ambient light
experiences an increase in level, the resistance of light dependent
resistor 41 will decrease which decrease in turn lowers the voltage at
the base of transistor 43 which in turn lowers the voltage at the
emitter due to increased conduction through that transistor. T
his in
turn increases the gain of the chroma amplifier transistor stage 45.
More precisely the lowering the voltage at the emitter of transistor 43
raises a threshold in the automatic chroma control detector 33 so
that the chroma signal
strength signal, and hence the color saturation
level, to the picture tube is increased. In the absence of a chroma
signal with its synchronizing burst, the gain of the chroma amplifier
is set at a maximum by the voltage divider comprising resistors 47 and
49. At this time there is no output from the automatic chroma control
detector to the base of transistor 51 and that transistor is
non-conducting.
When a color signal is received, the
detector provides an output signal proportional to the color sync
burst level which turns on the transistor 51 to control the gain of
the chroma amplifier stage 45 so as to maintain the desired output
level. The turn on level of transistor 51 represents a fairly well
defined knee in the chroma gain control characteristic curves
illustrated in FIG. 3. Operation beyond the knee or threshold of such a
curve operates to maintain a nearly constant chroma output level
while operation below the knee of the curve and its extension as the
almost vertical dotted line represents the open loop characteristic
wherein there is no automatic gain control to the chroma amplifier.
Since transistor 51 is non-conducting below the knee of this curve,
gain control is delayed until the output signal reaches this threshold
point. Since variations in the potential at the emitter of transistor
43 cause corresponding variations in the potential at the base of
transistor 51, it is clear that a variation in the resistance of the
light dependent resistor 41 will, for example, cause the gain control
characteristic curve to shift from that depicted by curve A to that
depicted by curve B and that for a given burst level input as
represented by the vertical dotted line, two different levels of chroma
output which, in turn, cause two different levels of color saturation
will be achieved by a change in the light intensity incident on the
resistor 41.
To better understand the operation of
detector 33, assume that the burst voltage induced across the top half
of the secondary of transformer 34 is in phase with the 3.58
megacycle reference signal and that the burst voltage induced across
the bo
ttom half of the secondary of transformer 34 is 180° out of
phase with this reference signal. Assuming further that the diodes 36
and 38 have equal characteristics, that the resistors 40 and 42 are
equal, that the capacitors 44 and 46 are equal, and that the two
portions of the secondary winding on transformer 34 are equal when no
burst is being received, diodes 36 and 38 will conduct equally but
during opposite portions of a cycle. Diode 36 conducts during negative
excursions of the reference signal whereas diode 38 conducts during
positive portions of that reference wave form. Thus during the
negative portions of the reference wave form diode 36 conducts to
charge capacitor 44 so that its right hand plate is negative and its
left hand plate is positive. During the positive excursions, diode 38
conducts to charge capacitor 46 with its right hand plate positive and
its left hand plate negative. Under this assumed no burst input
condition the net charge on these capacitors yields a voltage on line
48 which is zero. If noise is introduced into the system, it will be
of equal amplitude but opposite phase across the two diodes and both
diodes will
be affected to an equal extent resulting in no change in
the voltage on line 48. When during a color telecast a burst signal is
present, we may assume that the burst voltage induced across the two
portions of the secondary of transformer 34 are of equal amplitude to
the 3.58 megacycle reference signal. With this situation the diode 36
will not conduct since the burst voltage is equal in phase and
amplitude to the reference signal and its anode and cathode remain at
the same potential. The diode 38 will, however, conduct readily since
the burst and reference signals have an additive rather than a
cancelling effect on it resulting in the diode 38 conducting twice as
much as in the previous no burst example and resulting in the
capacitor 46 charging to about twice its previous voltage which
voltage is presented on line 48 as a control signal.
Suppose
now that the burst signal amplitude is reduced to one half that of
the foregoing example. With this new assumption the phase
relationships remain as before but now diode 36 will conduct about one
half its previous amount while diode 38 conducts about one and one
half times its previous amount resulting in a voltage on line 48 which
is about one half the previous voltage.
The voltage
on line 48 which is approximately proportional to the burst voltage is
applied to the base of transistor 51 which biases the base of the
chroma amplifier transistor 45 thereby controlling the gain of that
chroma amplifier stage.
A variation in threshold can
be achieved by altering the conduction points of the diodes 36 and 38.
This is accomplished by applying a bias voltage to the junction of
these two diodes to alter their respective points of conduction
thereby changing the output voltage on line 48. For example, if a
positive 2-volt direct current bias is applied to the junc
tion of the
two diodes, under a no burst input condition, diode 38 will conduct
sooner and turn off later than with no bias applied, while diode 36
will turn on later and off sooner than under the no bias condition.
This results in a control voltage on line 48 under the no burst
condition. In other words, a bias voltage applied to the junction of
the two diodes acts as an additional bias on the chroma amplifier
stage thereby affecting its gain.
The control of
brightness (intensity) and contrast is achieved in the present
invention by a second light dependent resistor 53 which is optically
coupled to a light emitting diode 55. LIght emitting diode 55 and
light dependent resistor 53 are encapsulated in a light impervious
housing illustrated by the dotted line 57. As the room ambient light
changes, the change in the resistance of light dependent resistor 41
causes a change in the current through light emitting diode 55.
Variations in the current through the light emitting diode cause
corresponding variations in the light emitted thereby which in turn
cause variations in the resistance of the light dependent resistor 53.
The luminance or video amplifier is here illustrated as a three
transistor amplifier with the output of the first amplifier stage being
across resistor 59. A diminution in the resistance of light dependent
resistor 53 causes a lowering of this output impedance and thus a
diminution in the gain of the luminance amplifier. In other words, if
the light intensity in the room increases, the resistance of resistor 41
will decrease causing a decrease in the current through light
emitting diode 55 and, therefore, a decrease in its light output level
and this decreased light will cause an increase in the resistance of
light dependent resistor 53 thus increasing the effective output load
resistor for the transistor 61 thus increasing the gain of the video
amplifier as desired.
Variable resistor 63 being
effectively in series with the light dependent resistor 41 may be
varied to compensate for differences in specific light dependent
resistors so as to establish a desired level of picture brightness,
contrast and color saturation for a given level of ambient light.
Variable resistance 65 which is in parallel with the light dependent
resistor 41 may be varied so as to effectively change the range of
variation in brightness, contrast and color saturation for a specific
range of variations in the ambient light conditions. The entire
automatic control circuit of the present invention may be bypassed by
closing the defeat switch 67.
Looking now at FIGS. 2 and
4, the relative attenuation of the chroma channel and luminance
channel will become apparent. Looking first at FIG. 4, the abscissa is
the measure of ambient illumination in foot candles on a log scale,
and the ordinate is the measure of attenuation of signal amplitude in
dB. At 100 footcandles there is 0 dB attenuation of luminance and
chroma signals and as the ambient illumination decreases to 0.1 foot
candles, it is seen that the chroma signal line 72 is down 2.1 dB
while the luminance signal line 72 is down 3.3 dB. This ratio has been
found to be a highly satisfactory ratio giving a very pleasing
picture at all ambient light levels between 0.1 footcandles and 100
footcandles of ambient light.
The manner in which this
variation in luminance attenuation is achieved may be seen by looking
at FIG. 2. As mentioned, the chroma channel signal is varied by the
conduction level of transistor 43. As light dependent resistor 41
changes in resistance, the conduction level of transistor 43 will also
change with the degree of change being determined by divider
resistances 75 and 76. Further the luminance channel gain is
determined by resistor 77 since it is this resistor which will control
the signal level of light emitting diode 55 which in turn will
control the gain to luminance transistor 61. It is these resistors
which determine the relative amount of attenuation of gain in the
chroma and luminance channels as the ambient light is changed. In this
embodiment, resistance 75 is 5.6 k ohms, resistance 76 is 4.3 k ohms,
resistance 77 is 3.9 k ohms, resistance 78 is 7.5 k ohms, the voltage
applied to the upper terminal of resistance 78 is 35 volts,
resistance 63 is 500 ohms, resistance 65 is 25 k ohms, resistance 69
is 4.7 k ohms, capacitance 71 is 47 microfarads, resistance 59 is 1 k
ohm, resistance 59a is 6.8 k ohms, resistance 62a is 1 k ohms,
resistance 64a is 100 ohms, resistance 64b is 6.8 k ohms. Light
dependent resistor 41 is a Clariex CL-11360, photocoupler unit 57 is
Magnavox Part Number 701482. Transistors 43, 61, 62, and 64 are
2N3962, 2N4916, MPSA20 and 25C685A, respectively. This invention has
been incorporated in a Magnavox Company T979 color television chassis.
The
effective load resistance for the transistor 61 under direct current
conditions is the parallel combination of the resistor 59 and the
series pair of resistors 53 and 69 whereas due to the presence of
capacitor 71 this effective load resistance under alternating current
conditions is the parallel combination of resistors 59 and 53. Thus
the ratio of AC to DC gain for this video amplifier stage may be
selected by proper selection of these parameters so as to maintain the
black level of the picture essentially constant.
Thus
while the present invention has been described with respect to a
specific embodiment, numerous modifications will suggest themselves to
those of ordinary skill in the art. Since the luminance and chroma
gains are individually controlled for a given change in ambient light,
the gain ratios between the luminance and chroma channels may be
selected as desired to achieve a desired effect for a given change in
ambient light. Also, while the present invention has been described in
the environment of a television receiver, the invention could equally
well be used in television monitors as well as many other types of
display devices. Accordingly the scope of the present invention is to
be measured only by that of the appended claims.
METZ 7096 CLASSIC COLOR (CH679G) CHASSIS 679G AMBIENT LIGHT RESPONSIVE CONTROL OF BRIGHTNESS, CONTRAST AND COLOR SATURATION Gain control arrangement useful in a television signal processing system
In
a color television receiver, first and second amplifiers are
respectively included in the luminance and chrominance channels to
permit control of contrast and saturation. The amplifiers have gain
versus control voltage characteristics including linear portions
extrapolated to cut off at predetermined voltages which may or may not
be the same. A first potentiometer is coupled between a source of fixed
voltage equal to the extrapolated cut off voltage of the first
amplifier and a gain controlling voltage source. The gain controlling
voltage may be produced by a circuit including an element responsive to
ambient light. The wiper of the first potentiometer is coupled to the
first amplifier to couple a voltage developed at a predetermined
point of the first potentiometer to the first amplifier to control its
gain. A second potentiometer is coupled between a source of voltage
equal to the extrapolated cut off voltage of the second amplifier and
the gain controlling voltage source to receive a portion of the gain
controlling voltage in accordance with the ratio of the extrapolated
cut off voltages of the first and second amplifiers. The wiper of the
second po
tentiometer is coupled to the second amplifier to couple a
voltage developed at a predetermined point of the second potentiometer
to the second amplifier to control its gain. In this manner, the
contrast of the receiver may be varied over a relatively wide range
while saturation is maintained substantially constant.
1.
In a color television signal processing system of the type including
luminance and chrominance signal processing channels, apparatus
comprising:
first and second amplifiers respectively included in
said luminance and chrominance channels, said amplifiers having gain
versus control voltage characteristics including linear portions
extrapolated to cut-off at predetermined voltages which may or may not
be the same voltage;
a gain controlling voltage source;
means for coupling said gain controlling voltage to said first amplifier to control its gain;
potentiometer
means coupled between a fixed voltage substantially equal to the
extrapolated cut-off voltage of said second amplifier and to said gain
controlling voltage source to recieve a portion of said gain
controlling voltage in accordance with the ratio of the extrapolated
cut-off voltages of said first and second amplifiers; and
means
for coupling a voltage developed at a predetermined point on said
potentiometer means to said second amplifier to control its gain.
2.
The apparatus recited in claim 1 wherein said means for coupling said
gain controlling voltage to said first amp
lifier includes another
potentiometer coupled between a source of fixed voltage substantially
equal to the extrapolated cut-off voltage of said first amplifier and
said gain controlling voltage source.
3. In a color television signal processing system of the type
including luminance and chrominance signal processing channels,
apparatus comprising:
first and second amplifiers respectively
included in said luminance and chrominance channels, said amplifiers
having gain control voltage characteristics including linear portions
extrapolated to cut-off at substantially the same predetermined voltage;
a source of gain controlling voltage; and
means for coupling said gain controlling voltage to said first and second amplifiers.
4. Apparatus comprising:
first
variable gain amplifying means for
amplifying a first signal in
response to a first DC control signal, said first amplifying means
having a first gain versus DC control voltage characteristic including a
linear region, said linear region having a gain substantially equal
to 0 at a DC control voltage equal to V
O ;
second
variable gain amplifying means for amplifying a second signal in
response to a second DC control signal, said second amplifying means
having a second gain versus DC control voltage characteristic including
a linear region, said linear region having a gain substantially equal
to 0 at a DC control voltage equal to AV
O, where A is a number greater than 0;
a first source of fixed voltage substantially equal to V
O ;
a second source of fixed voltage substantially equal to AV
O ;
means for developing a third DC control voltage v;
means for developing a portion Av of said third control voltage v;
first
means for deriving said first control voltage including means for
providing the difference between said third control voltage v and said
fixed voltage V
O and means for adding a predetermined portion of the difference between said third control voltage v and said fixed voltage V
O to said DC control voltage v; and
second
means for deriving said second control voltage including means for
providing the difference between a portion Av of said third control
voltage v and said fixed voltage AV
O and means for adding a predetermined portion of the difference between said portion Av and said fixed voltage AV
O to said DC control voltage v.
5.
The apparatus recited in claim 4 wherein A is equal to 1.
6. The apparatus recited in claim 4 wherein
said first amplifying means is included in a luminance channel of a
televeision signal processing system and said second amplifying means
is included in a chrominance channel of said television signal
processing system. 7. The
apparatus recited in claim 6 wherein means for developing said third
control voltage includes means responsive to ambient light.
8. The apparatus recited in claim 4 wherein
said first means includes first voltage divider means coupled bet
ween
said fixed voltage V
O and said third DC control voltage v;
and wherein said second means includes second voltage divider means
coupled between said fixed voltage AV
O and said portion Av.
9. The apparatus recited in claim
8 wherein said first voltage divider means includes a first
potentiometer, said first potentiometer having a wiper coupled to said
first amplifying means; and wherein said second voltage divider means
includes a second potentiometer, said second potentiometer having a
wiper coupled to said amplifying means.
10. The apparatus recited in claim 4 wherein said second gain
versus DC control voltage characteristic includes a region between said
voltage AV
O and a voltage V
B where the gain is greater than 0, said voltage V
B
being substantially equal to the voltage at which said second
amplifying means has a gain substantially equal to 0; and wherein said
second source of fixed voltage includes means for coupling said voltage
V
B to said second amplifying means.
11. The apparatus recited in claim 10 wherein said
second source of said voltage AV
O includes a third source of fixed voltage V
B ; potentiometer means coupled between said third source of fixed voltage V
B
and said means for developing said third DC control voltage; and
means coupled to said potentiometer means for developing said voltage
AV
O at a point along said potentiometer means; said
potentiometer means including a wiper coupled to said second amplifier
means, said wiper being adjustable to couple a DC voltage V
FB and said third control voltage to said second amplifying means.
Description:
The
present invention pertains to gain controlling apparatus and
particularly to apparatus for controlling the gains of amplifiers
included in the luminance and chrominance channels of a television
signal processing system.
Recently, the maximum brightness
available from television receivers has increased sufficiently so that a
pleasing image may be repro
duced under conditions of high ambient
light as well as under conditions of low ambient light. Apparatus is
known for automatically controlling the contrast and brightness
properties of a television receiver in response to ambient light to
provide a pleasing image over a range of ambient light conditions. Such
apparatus is described in U.S. Pat. Nos. 3,027,421, entitled "Circuit
Arrangements For Automatically Adjusting The Brightness And The
Contrast In A Television Receiver," issued to H. Heijligers on Mar.
27, 1962 and 3,025,345, entitled "Circuit Arrangement For Automatic
Readjustment Of The Background Brightness And The Contrast In A
Television Receiver," issued to R. Suhrmann on Mar. 13, 1962.
Apparatus
is also known for automatically controlling the contrast and
saturation properties of a color television receiver by controlling the
gains of luminance and chrominance channel amplifiers, respectively,
in response to ambient light. Such apparatus is described in U.S. Pat.
Nos. 3,813,686 entitled "Ambient Light Responsive Control Of
Brightness, Contrast And Color Saturation," issued to Eugene Peter
Mierzwinski, on May 28, 1974 and 3,814,852 entitled "Ambient Light
Responsive Control Of Brightness, Contrast and Color Saturation,"
issued to Eugene P. Mierzwinski on June 4, 1974.
Also of interest
is apparatus for manually controlling the gains of luminance and
chrominance channel amplifiers. Such apparatus is described in U.S.
Pat. Nos. 3,374,310, entitled "Color Television Receiver with
Simultaneous Brightness and Color Saturation Controls," issued to G.L.
Beers on Mar. 19, 1968; 3,467,770, entitled "Dual Channel Automatic
Control Circuit," issued to DuMonte O. Voigt on June 7, 1966; and
3,715,463, entitled "Tracking Control Circuits Using a Common
Potentiometer," issued to Lester Tucker Matzek, on Feb. 6, 1973.
When
the gain of luminance channel is adjusted to control the contrast of
an image, either manually or automatically, in response to ambient
light, it is desirable to simultaneously control the gain of the
chrominance channel in such a manner that the ratio of the gains of the
luminance and chrominance channels is substantially constant over a
wide range of contrast control to maintain constant saturation. If the
proper ratio between the amplitudes of the chrominance and luminance
signals is not maintained incorrect color reproduction may result. For
instance, if the amplitude of the luminance signals are increased
without correspondingly increasing the amplitude of the chrominance
signals, colors may become desaturated, i.e., they will appear washed
out or pastel in shade. Furthermore, it may be desirable to provide
controls for presetting the gains of the luminance and chrominance
channels to compensate for tolerance variations in other portions of the
television signal processing apparatus.
In accordance with the
present invention, apparatus is provided which may be utilized in a
color television receiver to control contrast over a relatively wide
range while maintaining constant saturation. The apparatus includes
first and second amplifiers having gain versus control voltage
characteristics including linear portions extrapolated to cut off at
predetermined voltages which may or may not be the same. Means couple a
gain controlling voltage source to the first amplifier to control its
gain. Potentiometer means are coupled between a source of fixed
voltage substantially equal to the extrapolated cut off voltage of the
second amplifier and the source of gain controlling voltage to
receive a portion of said gain controlling voltage in accordance with
the ratio of the extrapolated cut off voltages of the amplifiers. A
voltage developed at a predetermined point along the potentiometer
means is coupled to the second amplifier to control its gain.
In
accordance with another feature of the present invention, the means
for coupling said gain controlling voltage to said first amplifier
includes another potentiometer coupled between a source of fixed
voltage substantially equal to the extrapolated cut off voltage of
said first amplifier and said gain controlling voltage source.
In
accordance with still another feature of the present invention the
gain controlling voltage source includes an element responsive to
ambient light .
These and other aspects of the present invention
may best be understood by references to the following detailed
description and accompanying drawing in which:
FIG. 1 shows the
general arrangement, partly in block diagram form and partly in
schematic diagram form, of a color television receiver employing an
embodiment of the present invention;
FIG. 1A shows, in schematic form, a modification to the embodiment shown in FIG. 1;
FIG.
2 shows graphical representation of gain versus control voltage
characteristics of amplifiers utilized in the embodiment shown in FIG.
1;
FIG. 3 shows graphical representations of gain versus control
voltage characteristics of amplifiers which may be utilized in the
receiver shown in FIG. 1;
FIG. 4 shows, in schematic form,
another embodiment of the present invention which may be utilized to
control the amplifiers whose gain versus control voltage
characteristics are shown in FIG. 3;
FIG. 5 shows, in schematic form, an amplifier which may be utilized in the receiver shown in FIG. 1; and
FIG. 6 shows, in schematic form, another amplifier which may be utilized in the receiver shown in FIG. 1.
Referring now
to
FIG. 1, the general arrangement of a color television receiver
employing the present invention includes a video signal processing unit
112 responsive to radio frequency (RF) television signals for
generating, by means of suitable intermediate frequency (IF) circuits
(not shown) and detection circuits (not shown), a composite video signal
comprising chrominance, luminance, sound and synchronizing signals.
The output of signal processing unit 112 is coupled to chrominance
channel 114, luminance channel 116, a channel 118 for processing the
synchronizing signals and a channel (not shown) for processing sound
signals.
Chrominance
processing channel 114 includes chrominance processing unit 120 which
serves to remove chrominance signals from the composite video signal
and otherwise process chrominance signals. Chrominance signal
processing unit 120 may include, for example, automatic color control
(ACC) circuits for adjusting the amplitude of the chrominance channels
in response to amplitude variations of a reference signals, such as a
color burst signal, included in the commposite video signal.
Chrominance signal processing circuits of the type described in the
U.S. Pat. No. 3,740,462, entitled "Automatic Chroma Gain Control
System," issued to L.A. Harwood, on June 19, 1973 and assigned to the
same assignee as the present invention are suitable for use as
chrominance processing unit 120.
The output of the chrominance
signal processing unit 120 is coupled to chrominance amplifier 122
which serves to amplify chrominance signals in response to a DC signal v
C
generated by gain control network 142. As illustrated, chrominance
amplifier 122 provides chrominance signals to a chroma demodulator 124.
An amplifier suitable for use as chrominance amplifier 122 will
subsequently be described with reference to FIG. 6.
Chroma
demodulator 124 derives color difference signals representing, for
example, R-Y, B-Y and G-Y information from the chrominance signals.
Demodulator circuits of the general type illustrated by the chrominance
amplifier CA 3067 integrated circuit manufactured by RCA Corporation
are suitable for use as chrominance demodulator 124.
The color
difference signals are applied to a video driver 126 where they are
combined with the output signals -Y of luminance channel 116 to produce
color signals of the appropriate polarity, representing for example,
red (R), green (G) and blue (B) information. The color signals are
coupled to kinescope 128.
Luminance channel 116 includes a first
luminance signal processing unit 129 which relatively attenuates
undesirable signals, such as chrominance or sound signals or both,
present in luminance channel 116 and otherwise processes the luminance
signals. The output of first luminance processing unit 129 is coupled
to luminance amplifier 130 which serves to amplify the luminance
signals in response to a DC control signal v
L generated by
gain control unit 142 to thereby determine the contrast of a
reproduced image. An amplifier suitable for use as luminance amplifier
130 will subsequently be described with reference to FIG. 5. The
output of luminance amplifier 130 is coupled to second luminance
signal processing unit 132 which serves to further process luminance
signals. A brightness control unit 131 is coupled to luminance signal
processing unit 132 to control the DC content of the luminance
signals. The output -Y of luminance processing unit 132 is coupled to
kinescope driver 126.
Channel 118 includes a sync separator 134
which separates horizontal and vertical synchronizing pulses from the
composite video signal. The synchronizing pulses are coupled to
horizontal deflection circuit 136 and vertical deflection cir
cuit 138.
Horizontal deflection circuit 136 and vertical deflection circuit 138
are coupled to kinescope 128 and to a high voltage unit 140 to
control the generation and deflection of one or more electron beams
generated by kinescope 128 in the conventional manner. Deflection
circuits 136 and 138 also generate horizontal and vertical blanking
signals which are coupled to luminance signal processing unit 132 to
inhibit its operation during the horizontal and vertical retrace
intervals.
Gain control unit 142 is coupled to luminance
amplifier 130 and to chrominance amplifier 122 to control their gains.
Gain control unit 142 includes a PN
P transistor 152 arranged as an
emitter-follower amplifier. The collector of transistor 152 is coupled
to ground while its emitter is coupled through a series connection of
a potentiometer 156 and fixed resistor 154 to a source of positive
supply voltage V
O. The wiper of potentiometer 156 is
coupled to luminance amplifier 130. The series connection of a
potentiometer 158 and a variable resistor 159 is coupled between the
source of positive supply voltage V
O and the emitter of transistor 152. The wiper of potentiometer 158 is coupled to chrominance amplifier 122.
The
base of transistor 152 is coupled to the wiper of a potentiometer
146. One end of potentiometer 146 is coupled to the source of positive
supply voltage V
O through a fixed resistor 144. The other
end of potentionmeter 146 is coupled to ground through a light
dependent resistor (LDR) 148. LDR 148 is a resistance element whose
impedance varies in inverse relationship with light which impinges on
it. LDR 148 may comprise a simple cadmium sulfide type of light
dependent element or other suitable light dependent device. LDR 148 is
desirably mounted to receive ambient light in the vicinity of the
screen of kinescope 128.
A single pole double-throw switch 150
has a pole coupled to the junction of potentiometer 146 and LDR 148. A
resistor 151 is coupled between the wiper of potentiometer 146 and
the other pole of switch 150. The arm of switch 150 is coupled to
ground.
The general arrangement shown in FIG. 1 is suitable for
use in a color television receiver of the type shown, for example, in
RCA Color Television Service Data 1973 No. C -8 for a CTC-68 type
receiver, published by RCA Corporation, Indianapolis, Indiana.
In
operation, gain control circuit 142 maintains the ratio of the gain
of chrominance amplifier 122 to the gain of amplifier 130 constant in
order to maintain constant saturation while providing for contrast
adjustment either manually by means of potentiometer 146 or
automatically by means of LDR 148. If the gain of luminance were
adjusted to control the contrast of an image without a corresponding
change in the gain of chrominance amplifier 122, the amplitudes of
luminance signals -Y and color difference signals R-Y, B-Y and G-Y
would not, in general, be in the correct ratio when combined by
divider 126 to provide the desired color.
When switch 140 is in
the MANUAL position, the gains of chrominance amplifier 122 and
luminance amplifier 130 are controlled by adjustment of the position
of potentiometer 146. When switch 150 is in the AUTO position the gain
of the chrominance amplifier 122 and luminance amplifier is
automatically controlled by the response of LDR 148 to ambient light
conditions. The voltage developed at the wiper of potentiometer 146
(base of transistor 152) when switch 150 is in the AUTO position is
inversely related to the ambient light recieved by LDR 148. It is
noted that the values of resistors 114, potentiometer 146, LDR 148 and
resistor 151 are desirably selected such that the adjustment of the
wiper arm of potentiometer 146 when switch 150 is in the MANUAL
position does not substantially affect the voltage developed at the
base of transister 152 when switch 150 is placed in the AUTO position.
The
control voltage v developed at the wiper arm of potentiometer 146 is
coupled through emitter-follower transistor 152 to the common junction
of potentiometer 156 and variable resistor 159. A control voltage v
L comprising v plus a predetermined portion of the difference V
O
-v developed across the series connection of fixed resistor 154 and
potentiometer 156, depending on the setting of potentiometer 156, is
coupled to luminance amplifier 130 to control its gain. Similarly, a
control voltage v
C comprising v plus a predetermined portion of the difference voltage V
O
-v developed across the series connection of potentiometer resistor
158 and variable resistor 159, depending on the setting of the wiper of
potentiometer 158, is coupled to chrominance amplifier 122 to control
its gain.
The gain of luminance amplifier 130 may be pre-set to
a desired value by the factory adjustment of potentiometer 156.
Similarly, variable resistor 159 is provided to allow factory pre-set of
the gain of the chrominance amplifier 122. Potentiometer 158 is
provided to allow customer control of saturation.
R
eferring to FIG. 2, the gain versus voltage characteristics of chroma amplifier 122 (g
C) and luminance amplifier 130 (g
L) are shown. The characteristic g
C has a reversed S-shape including a linear portion 214. Extrapolated linear portion 214 of g
C intersects the GAIN axis at G
C and intersects the CONTROL VOLTAGE axis at V
O. Similarly, the characteristics g
L has a reverse S-shape characteristic including a linear portion 212. Extrapolated linear portion 214 of g
L intersects the GAIN axis at G
L and intersects the CONTROL VOLTAGE axis at V
O.
From FIG. 2, the expression for linear portion 212 of g
L is ##EQU1## The expression for linear portion 214 of g
C is ##EQU2## From FIG. 1, the expression for v
L is v
L = v + (V
O -v) K
1 [3]
where K
1
is determined by the voltage division of fixed resistor 154 and
potentiometer 156 at the wiper of potentiometer 156. When the wiper of
potentiometer 156 is at the emitter of transistor 152, K
1 =0. The expression for v
C is v
C = v + (V
O -v)K
2 [4]
where K
2
is determined by the voltage division of potentiometer 158 and fixed
resistor 159 at the wiper of potentiometer 158. By combining equations
[1] and [3], the equation for g
L becomes ##EQU3## By combining equations [2] and [4], the equation for g
C becomes ##EQU4## The ratio of g
L to g
C
is thus ##EQU5## It is noted that this ratio is independent of DC
control voltage v. Thus, although DC control voltage v may be varied
either manually or in response to ambient light to control the contrast
of an image reproduced by kinescope 128, the saturation remains
constant.
With re
ference to FIG. 2, it is noted that although the linear portion 214 of g
C has an extrapolated gain equal to 0 at a control voltage equal to V
O, the non-linear portion of g
C does not attain a gain equal to 0 until a control voltage equal to V
B. That is, a control voltage of V
O will not cut-off chrominance amplifier 122.
In
FIG. 1A there is shown, in schematic form, a modification to the
arrangement of gain control network 142 of FIG. 1 with provisions which
allow a viewer to cut off chrominance amplifier 122 to produce a more
pleasing image under conditions of poor color reception due, for
example, to noise or interference. The modifications to gain control
unit 142 shown in FIG. 1A include coupling potentiometer resistor 158
between a source of positive supply voltage V
B, the value of V
B being greater than the value of V
O,
and coupling a resistor 160 from a tap-off point 162 along
potentiometer 158 to ground. The value of potentiometer 158 and resistor
160 and the location of tap 162 are selected so that voltage V
O is developed at tap 162.
The
arrangement shown in FIG. 1A allows for the adjustment of contrast
while constant saturation is maintained and additionally allows a
viewer, by adjusting the wiper of potentiometer 158 to voltage V
B, to cut off chrominance amplifier 122.
Referring
to FIG. 3 there are shown gain versus DC control voltage
characteristics of chrominance and luminance amplifiers which do not
have the same extrapolated linear cut off control voltage. The gain
versus control voltage characteristic g
L ' of the luminance
amplifier has a reverse S-shape characteristic including a linear
portion 312. Extrapolated linear portion 312 of g
L ' intersects the GAIN axis at a gain G
L ' and intersects the CONTROL VOLTAGE axis at a voltage V
O '. The gain versus control voltage characteristic g
C
' of the chrominance amplifier has a reverse S-shape characteristic
having a linear portion 314. Extrapolated linear portion 314 of g
C ' intersects the GAIN axis at a gain G
C ' and intersects the CONTROL VOLTAGE axis at a voltage AV
O ', where A is a number greater than zero.
From FIG. 3, the expression for linear portion 312 of g
L ' is ##EQU6## where v
L ' is the DC conrol voltage coupled to the luminance amplifier. The expression for linear portion 314 of g
C ' is ##EQU7## where v
C ' is the DC control voltage coupled to the chrominance amplifier.
A
modified form of the control network 142 of FIG. 1 suitable for
controlling the gain of a chrominance and a luminance amplifier having
characteristics such as shown in FIG. 3 is shown in FIG. 4. Similar
portions of FIGS. 1 and 4 are identified by reference numbers having the
same last two significant digits and primed (') designations. The
modified portions of FIG. 1 shown in FIG. 4 include the series
connection resistors 460 and 462 coupled between the emitter of
transistor 452 to ground. The values of resistors 460 and 462 are
selected so that a portion Av' of the DC control voltage v' developed at
the emitter of transistor 452 is developed at the junction of
resistors 460 and 462. Furthermore, the series connection of
potentiometer 458 and variable resistor 459 is coupled between the
junction of resistor 460 and 462 and a source of positive supply
voltage AV
O '.
From FIG. 4, the expression for control voltage v
L ' developed at the wiper of potentiometer 456 is v
L ' = v' + (v
O '-v')K
1 ' [10]
where K
1 ' is determined by the voltage division at the wiper of potentiometer 456. The expression for control voltage v
C ' developed at the wiper of potentiometer 458 is V
C ' = Av' + (AV
O ' - Av')K
2 ' [11]
where K
2
' is determined by the voltage division at the wiper of potentiometer
458. By combining equations [8] and [10], ##EQU8## By combining
equations [9] and [11], ##EQU9## The ratio of g
L ' to g
C
' is given by the expression ##EQU10## It is noted that this ratio is
independent of DC control voltage v'. Therefore, gain control network
442 of FIG. 4 also allows for the adjustment of contrast while
maintaining constant saturation.
It is noted that if A were made
equal to 1, the arrangement gain control unit 442 would be suitable to
control the gains of chrominance and luminance amplifiers having the
characteristics shown in FIG. 2.
In FIG. 5, there is shown an
amplifier suitable for use as luminance amplifier 130 of FIG. 1. The
amplifier includes a differential amplifier comprising NPN transistors
532 and 534. The commonly coupled emitters of transistors 532 and 534
are coupled to the collector of an NPN transistor 528. The emitter of
transistor 528 is coupled via a resistor 530 to ground. The collector
of transistor 532 and the collector of transistor 534, via load
resistor 536, is coupled to a bias voltage provided by bias supply
546, illustrated as a series connection of batteries. The bases of
transistors 532 and 534 are respectively coupled to a lower bias voltage
through resistors 533 and 535 respectively.
An input signal,
such as, for example, the output signal provided by first luminance
processing circuit 129 of FIG. 1 is coupled to the base of transistor
532 via terminal 542. The output signal of the amplifier is developed at
the collector of transistor 534 and coupled to output terminal 544.
A DC control voltage, such as v
L
provided by gain control unit 142 of FIG. 1, is coupled to the base
of an NPN transistor 514, arranged as an emitt
er-follower, via
terminal 512. The collector of transistor 514 is coupled to bias
supply 546. The emitter of transistor 514 is coupled to ground through
the series connection of resistor 516, a diode connected transistor
518 and resistor 520.
The anode of diode 520 is coupled to the
base of an NPN transistor 538. The collector of transistor 538 is
coupled to the collector of transistor 534 while its emitter is
coupled to ground through resistor 540. Transistor 538, resistor 540,
diode 518 and resistor 520 are arranged in a current mirror
configuration.
The emitter of transistor 514 is coupled to the
base of a PNP transistor 522. The emitter of transistor 522 is coupled
to bias supply 546 while its collector is coupled to the base of
transistor 528 and to ground through the series connection of a diode
connected transistor 524 and resistor 526. Transistor 528, resistor
530, diode 524 and resistor 526 are arranged in a current mirror
configuration
In operation, the DC control voltage coupled to
terminal 512 is coupled in inverted fashion to the anode of diode 524
by transistor 522. As a result, current directly related to the
voltage developed at the anode of diode 524 flows through diode 524
and resistor 526. Due to the operation of the current mirror
arrangement of diode 524, resistor 526, transistor 528 and resistor
530, a similar current flows through the emitter circuit of transistor
528. The gain of the differential amplifier comprising transistors
532 and 534 is directly related to this current flowing in the emitter
circuit of transistor 528, and therefore is inversely related to the
DC control voltage at terminal 512. The gain versus DC control voltage
characteristics of the differential is similar to g
L shown in FIG. 2.
Further,
a current is developed through the series connection of resistor 516,
diode 518 and resistor 520 in direct relationship to the DC control
coupled to terminal 512. A similar current is developed through
resistor 540 due to the operation of the current mirror comprising
diode 518, resistor 520, transistor 538 and resistor 540. This current
is of the opposite sense to that provided by the current mirror
arrangement of diode 524, resistor 526, transistor 528 and resistor 530
and is coupled to the collector of transistor 534 so that the DC
voltage at output terminal 544 does not substantially vary with the DC
control voltage.
In FIG. 6, ther
e
is shown an amplifier suitable for use as chroma amplifier 120 of
FIG. 1. The amplifier shown in FIG. 6 is of the type described in U.S.
patent application Ser. No. 530,405 entitled "Controllable Gain
Signal Amplifier," fled by L.A. Harwood et al. on Dec. 6, 1974.
The
amplifier comprises a differential amplifier including NPN
transistors 624 and 625 having their bases coupled to terminal 603 via
a resistor 626. Chrominance signals, provided by a source of
chrominance signals such as chrominance processing unit 120 of FIG. 1,
are coupled to terminal 603. The current conduction paths between the
collectors and emitters of transistors 624 and 625 are respectively
coupled to ground via resistors 628, 629 and 630.
A current
splitter circuit comprising an NPN transistor 632 and a diode 634 is
coupled to the collector of transistor 624. Diode 634 and the
base-emitter junction of transistor 632 are poled in the same
direction with respect to the flow of collector current in transistor
624. It desirable that conduction characteristics of transistor 632
and diode 635 be substantially matched. Similarly, the collector of
transistor 625 is coupled to a second current splitter comprising a
transistor 633 and a diode 635.
An output load circuit
comprising series connected resistors 636 and 638 is coupled between
the collector of transistor 632 and a source of operating voltage
provided by bias supply 610. Amplified chrominance signals are
provided at output terminal 640 for coupling, for example, to a chroma
demodulator such as chroma demodulator 124 of FIG. 1. Similarly,
series connected load resistors 637 and 639 are coupled between the
collector of transistor 633 and bias supply 610. An output terminal
641 at the junction of resistors 637 ad 639 provides oppositely phased
chrominance signals to those provided at terminal 640. The gain
associated with the cascode combination of transistors 624 and 632 is
controlled in response to a DC control voltage, such as, for example, v
C
provided by gain control unit 142 of FIG. 1, coupled to the base of
an NPN transistor 646 via terminal 602. Direct control current is
supplied from the emitter of transistor 646 to diode 634 and 635 via a
series resistor 652. A signal by-pass circuit comprising a series
resonant combination 654 of inductance and capacitance is coupled from
the anode of diode 634 to ground. Resonant circuit 654 is tuned, for
example, to 3.58 MHz to provide a low impedance path to ground for
color subcarrier signals.
Bias voltages and currents are supplied
to the amplifier arrangement by bias supply 610, illustrated as a
series connection of batterys. A voltage B+ is coupled to the collector
of transistor 646. A lower bias voltage is coupled to the load
circuits of transistors 632 and 633. The bases of transistors 632 and
633 are coupled in common to a still lower bias voltage. The bases of
transistors 624 and 625 are coupled to a still lower bias voltage via
substantially equal in value resistors 658 and 659. A resistor 694 is
coupled from the common junction of resistors 658 and 659 to ground.
I
n
operation, a quiescent operating current is provided through resistor
630. In the absence of an input signal at terminal 603, this current
will divide substantially equally between the similarly biased
transistors 624 and 625. If the DC control voltage at terminal 602 is
near ground potential, transistor 646 will be effectively cut off and
no current will flow in resistor 652 and diodes 634 and 635. In that
case, neglecting the normally small difference betweeen collector and
emitter currents of NPN transistors, the collector currents of
transistors 624 and 625 will flow, respectively, in transistors 632 and
633. The transistors 632 and 633 are operated in common base mode and
form cascode signal amplifiers with respective transistors 624 and
625. With the DC control voltage near ground potential, one-half of
the quiescent current from resistor 630 flows in each of the load
circuits and maximum gain for chrominance signals supplied from
terminal 603 is provided.
Transistor 646 will conduct when the
DC control voltage approaches the bias voltage supplied to the bases
of transistors 632 and 633 of the current splitters. By selection of
the circuit parameters, diodes 634 and 635 may be arranged to operate
in a range between cut off to the conduction of all of the quiescent
operating current supplied via resistor 630, thereby cutting off
transistors 632 and 633 to provide no output signals at terminals 640
and 641.
At a DC control voltage intermediate to that
corresponding to cut off of transistors 632 and 633 on the one hand
and cut off of diodes 634 and 635 on the other hand, the voltage gain
of the illustrated amplifier will vary in a substantially linear
manner with the DC control voltage.
It
is noted that although the characteristics shown in FIGS. 2 and 3
were reversed S-shaped characteristics, the characteristics could have
other shapes including linear portions. For example, the
characteristics could be substantially linear. Furthermore, with
reference to FIG. 3, although g
C ' was shown as having a
linear portion that had a cut off control voltage lower than the cut
off control voltage of the linear portion of g
L ', the cut off control voltage of the linear portion of g
C ' could be greater than the cut off voltage for the linear region of g
L
'. In addition, the gain control units and associate amplifiers could
be arranged to utilize voltages opposite in polarity to those shown.
These and other modifications are intended to be within the scope of
the invention.
PHILIPS TDA2593 SYNCHRO AND HORIZONTAL DEFLECTION CONTROL FOR COLOR TV SET:
DESCRIPTION
The TDA2593 isacircuitintendedforthehorizontal
deflectionofcolorTVsets,suppliedwithtransistors
or SCR’S.
LINE OSCILLATOR(two levels switching)
.PHASE
COMPARISON
BETWEEN
SYN-
CHRO-PULSE AND OSCILLATOR VOLTAGE
Ø 1, ENABLED BY AN INTERNAL PULSE,
(better parasitic immunity)
.PHASE COMPARISON BETWEEN THE FLY-
BACK PULSESAND THE OSCILLATORVOL-
TAGE Ø2
.COINCIDENCE DETECTOR PROVIDING A
LARGE HOLD-IN-RANGE
.FILTER
CHARACTERISTICS
AND
GATE
SWITCHING FOR VIDEO RECORDER AP-
PLICATION
.NOISE GATED SYNCHRO SEPARATOR
.FRAME PULSE SEPARATOR
.BLANKING AND SAND CASTLE OUTPUT
PULSES
.HORIZONTAL POWER STAGE PHASE LAG-
GING CIRCUIT
.SWITCHING OF CONTROL OUTPUT PULSE
WIDTH
.SEPARATED SUPPLY VOLTAGE OUTPUT
STAGE
ALLOWING
DIRECT
DRIVE
OF
SCR’S CIRCUIT
.SECURITY CIRCUIT MAKES THE OUTPUT
PULSE SUPPRESSED WHEN LOW SUPPLY
VOLTAGE.
METZ 7096 CLASSIC COLOR (CH679G) CHASSIS 679G Supply circuit for a television receiver:In one prior art arrangement utilizing a transformerless power supply,
the electrical components in the receiver and the chassis carrying the
same are directly grounded. To avoid the danger of the user being
subjected to electric shock on touching the grounded chassis should the
receiver power line plug be inserted in a domestic power source in a
position to apply the "hot" high voltage side of the source to the
chassis, it has been the practice to insulate the chassis from the
cabinet of the receiver set. Externally located knobs, their associated
controls, and antenna circuits also had to be electrically insulated
from the grounded chassis to avoid serious injury to the user. When
record player and channel converter components are used in association
with such television receivers, these components also had to be
electrically insulated from the grounded receiver chassis.
A supply circuit for television receivers in which power source
isolation is effected via a backward transformer. For the sake of
achieving an insusceptibility to interferences, the operating frequency
is equal to the line frequency. According to the invention, the supplied
energy is controlled by varying the switch-on time during one period of
the line frequency, in that the disconnecting time position is changed
with the aid of a thyristor switching stage.
1. A supply circuit for a television receiver having a horizontal output
stage including means for controlling line sweep and commutation, the
energy required by said horizontal output stage being provided by a
power source through a controllable supply circuit that isolates the
power source from the horizontal output stage, said controllable supply
circuit comprising:
an input transformer having a secondary winding
connected to the horizontal output stage for providing the energy
required thereby and a primary winding adapted for connection to the
power source and being electrically isolated from the secondary winding
and the horizontal output stage;
electronic switch means connected in series with the primary winding of the transformer;
first switching control means for switching on the electronic switch means as a function of line frequency; and
second switching control means for switching off the electronic switch
means as a function of the energy required by the horizontal output
stage, whereby the supply circuit provides the horizontal output stage
with the required energy from the power source while also electrically
isolating the horizontal output stage from the power source.The term "power transformer" as used herein refers to a transformer used
in a commercial power supply network for supplying power to the
deflection circuits from a commercial power supply, and should not be
confused with transformers in other portions of the receiver designated
by different terms. Thus, the expression "television receiver of a power
transformerless type" refers to a television receiver which does not
use the defined power transformer.
It is an object of the
invention to provide in conjunction with a transformerless power supply a
transformer coupling means effective to isolate, d.c. wise, deflection
circuits of the receiver from grounded receiver circuit components while
at the same time enabling a.c. coupling between components to be
coupled to one another.
It is another object of the invention to
provide a transformerless power supply and a transformer coupling means
which co-operate to permit operation of the deflection circuits without
need for connecting the deflection circuits to chassis ground for a.c.
by means of a small coupling condenser or otherwise.
It is a
further object of the invention to provide transformerless coupling
means having a turns ratio between the primary and secondary windings
thereof effective to couple in a forward direction a sync signal
amplifier output to the ungrounded horizontal and vertical deflection
circuits while substantially attenuating in the reverse direction
transients and external noise prevalent in the ungrounded deflection
circuits.
The present invention relates to a supply circuit for a television
receiver in which, for effecting isolation of the power source , an
input transformer serving the horizontal or line output stage, is
operated as a backward transformer and in which, within the horizontal
(line) output stage, there are taken off further voltages required for
operating the television receiver.
Owing to the various
attachments which are capable of being operated in connection with a
television receiver, it has increasingly become necessary, for safety
reasons, to provide for isolation of the power source the television
receiver.
In conventional types of circuits employing backward
transformers for effecting the source isolation, it is customary to
control the energy supply by way of inserting a transistorized control
stage.
A switching regulator for a television receiver, wherein a non-stable dc
voltage is periodically interrupted at the horizontal frequency by a
chopper and the dc voltage obtained as the output of the chopper is
applied to the horizontal output circuit. Flyback pulses generated by
the horizontal output circuit are integrated to generate a saw-tooth
waveform, and the dc component of the saw-tooth waveform is varied in
accordance with the variation of the dc voltage delivered by the
chopper. The duty ratio of the chopper is changed according to the
variation of the dc component of the saw-tooth waveform.
1. A switching regulator for use in a television receiver, comprising:
(a) a d.c. power source for generating a non-stabilized d.c. voltage;
(b) chopper means including a switching element, said chopper means
being operatively turned on and off alternately for periodically
interrupting said non-stabilized d.c. voltage in accordance with the
turn-on and turn-off of said switching element to produce an interrupted
voltage;
(c) rectifying means for converting the interrupted voltage from said chopper means into a d.c. output voltage;
This invention relates to a switching regulator for a television
receiver and more particularly to a switching regulator in which the
switching operation is performed at the horizontal frequency.
In
the U.S. Pat. No. 3,819,986, a switching regulator for a television
receiver is disclosed wherein a non-stabilized dc voltage is passed
through a chopper and then rectified to be applied to a load circuit
such as a horizontal oscillation circuit, and wherein an oscillator is
incorporated in a control circuit for controlling the chopper, to which
trigger pulses obtained by differentiating an output signal of the
horizontal oscillation circuit are applied. According to this switching
regulator, at the time when a power switch is closed, i.e., at the
starting time, a non-stable dc voltage is applied through a capacitor to
load circuits such as a horizontal oscillation circuit, a horizontal
exciting circuit and a control circuit so that these circuits are
temporarily actuated to cause the chopper to operate. The above circuits
are then operated continuously by a dc voltage obtained at the output
of the chopper due to the temporary actuation of the circuits. Such a
type of regulator is advantageous in comparison with a regulator wherein
the control circuit is always operated by a non-stabilized dc voltage,
in that the load circuit such as the horizontal oscillation circuit, the
horizontal exciting circuit and the control circuit are operated by a
stabilized voltage after the starting of operation and that when the
load is short-circuited the control circuit stops its operation and in
turn the operation of the chopper is stopped.
According to this invention, for attaining the above objects,
utilization is made of the horizontal flyback pulses generated by the
horizontal output circuit. The control circuit receives as a control
signal a signal in accordance with the output voltage of the chopper,
and is also controlled by the flyback pulses, so that the duty ratio of
the chopper is so controlled as to cause the chopper to deliver a
constant output voltage. Moreover, the control circuit is supplied with a
non-stable dc voltage applied to the chopper at the time of starting
and with a stable dc voltage obtained at the output of the chopper after
the starting.
According to this invention, there is provided a
switching regulator for use in a television receiver, comprising: a dc
power source for generating a non-stable dc voltage; a chopper which
includes therein a switching element turned on and off alternately and
which periodically interrupts the non-stable dc voltage in accordance
with the turn-on and turn-off of the switching element; a rectifying
means for reconverting a voltage obtained at an output of the chopper
into a dc output voltage; a horizontal deflection circuit receiving the
dc output voltage of the rectifying means; and a control circuit which
receives a signal having the horizontal frequency from the horizontal
deflection circuit, turns the switching element on and off at the
horizontal frequency and controls the increase and decrease in the
conduction period of the switching element in accordance with the
decrease or increase in the dc output voltage, wherein the control
circuit has means for responding to the horizontal flyback pulses
generated by the horizontal output circuit in the horizontal deflection
circuit.
In a switch mode power supply, a first switching transistor is coupled to a primary winding of an isolation transformer.
A
second switching transistor periodically applies a low impedance
across a second winding of the transformer that is coupled to an
oscillator for synchronizing the oscillator to the horizontal
frequency. A third winding of the transformer is coupled via a
switching diode to a capacitor of a control circuit for developing a
DC control voltage in the capacitor that varies in accordance with a
supply voltage B+. The control voltage is applied via the
transformer to a pulse width modulator that is responsive to the
oscillator output signal for producing a pulse-width modulated
control signal. The control signal is applied to a mains coupled
chopper transistor for generating and regulating the supply voltage
B+ in accordance with the pulse width modulation of the control
signal.
Description:
The invention relates to switch-mode power supplies.
Some
television receivers have signal terminals for receiving, for
example, external video input signals such as R, G and B input
signals, that are to be developed relative to the common conductor of
the receiver. Such signal terminals and the receiver common
conductor may be coupled to corresponding signal terminals and
common conductors of external devices, such as, for example, a VCR
or a teletext decoder.
To simplify the coupling of signals
between the external devices and the television receiver, the common
conductors of the re
ceiver and of the external devices are connected
together so that all are at the same potential. The signal lines of
each external device are coupled to the corresponding signal
terminals of the receiver. In such an arrangement, the common
conductor of each device, such as of the television receiver, may be
held "floating", or conductively isolated, relative to the
corresponding AC mains supply source that energizes the device. When
the common conductor is held floating, a user touching a terminal
that is at the potential of the common conductor will not suffer an
electrical shock.
Therefore, it may be desirable to isolate
the common conductor, or ground, of, for example, the television
receiver from the potentials of the terminals of the AC mains supply
source that provide power to the television receiver. Such isolation
is typically achieved by a transformer. The isolated common
conductor is sometimes referred to as a "cold" ground conductor.
In
a typical switch mode power supply (SMPS) of a television receiver
the AC mains supply voltage is coupled, for example, directly, and
without using transformer coupling, to a bridge rectifier. An
unregulated direct current (DC) input supply voltage is produced
that is, for example, referenced to a common conductor, referred to
as "hot" ground, and that is conductively isolated from the cold
ground conductor. A pulse width modulator controls the duty cycle of
a chopper transistor switch that applies the unregulated supply
voltage across a primary winding of an isolating flyback
transformer. A flyback voltage at a frequency that is determined by
the modulator is developed at a secondary winding of the transformer
and is rectified to produce a DC output supply voltage such as a
voltage B+ that energizes a horizontal deflection circuit of the
televi
sion
receiver. The primary winding of the flyback transformer is, for
example, conductively coupled to the hot ground conductor. The
secondary winding of the flyback transformer and voltage B+ may be
conductively isolated from the hot ground conductor by the hot-cold
barrier formed by the transformer.
It may be desirable to
synchronize the operation of the chopper transistor to horizontal
scanning frequency for preventing the occurrence of an objectionable
visual pattern in an image displayed in a display of the television
receiver.
It may be further desirable to couple a horizontal
synchronizing signal that is referenced to the cold ground to the
pulse-width modulator that is referenced to the hot ground such that
isolation is maintained.
A synchronized switch mode power supply, embodying an aspect of
the invention, includes a transfromer having first and second
windings. A first switching arrangement is coupled to the first
winding for generating a first switching current in the first winding
to periodically energize the second winding. A source of a
synchronizing input signal at a frequency that is related to a
deflection frequency is provided. A second switching arrangement
responsive to the input signal and coupled to the second winding
periodically applies a low impedance across the energized second
winding that by transformer action produces a substantial increase in
the first switching current. A periodic first control signal is
generated. The increase in the first switching current is sensed to
synchronize the first control signal to the input signal. An output
supply voltage is generated from an input supply voltage in accordance
with the first control signal.
METZ 7096 CLASSIC COLOR (CH679G) CHASSIS 679G Synchronized and regulated power supply:
A switching regulator adapted to be coupled to a source of alternating current potential produces a direct current potential having an amplitude proportional to the duration of a first drive signal condition relative to the duration of a second drive signal condition. A modulator coupled to a synchronized oscillator produces a synchronized control signal having an amplitude proportional to the amplitude of the direct current potential. A drive signal generator coupled to the modulator and the switching regulator produces a first drive signal condition having a duration relative to the duration of the second drive signal condition which is proportional to the amplitude of the control signal, thereby providing for regulation of the direct current potential.
1. A synchronized and regulated power supply comprising;switching regulator means adapted to be coupled to a source of alternating current potential for producing a direct current potential having an amplitude proportional to the duration of a first drive signal condition relative to the duration of a second drive signal condition;
oscillating means adapted to be coupled to a source of synchronizing signals for producing a switching signal having a first predetermined phase offset relationship with respect to said synchronizing signals;
modulating means coupled to said switching regulator means and said oscillating means for producing a control signal having a second predetermined phase offset relationship with respect to said switching signal and having an amplitude which is proportional to the amplitude of said direct current potential; and
means including a drive signal generator coupled to said modulating means and said switching regulator means for initiating the production of said first drive signal condition in response to the initiation of said control signal and for controlling the duration of said first drive signal condition relative to the duration of said second drive signal condition in response to the amplitude of said control signal.
2. A synchronized and regulated power supply according to claim 1 wherein said modulating means includes:
means coupled to said oscillating means for producing said control signal for a first predetermined duration, said control signal having said second predetermined phase relationship with respect to said switching signal; and
amplifying means coupled to said means for producing said control signal and said switching regulator for controlling the amplitude of said control signal for said first duration in response to said direct current potential.
3. A synchronized and regulated power supply according to claim 2 wherein said means including a drive signal generator includes:
first peak detecting means coupled to said modulating means for producing a control voltage proportional to the peak amplitude of said control signal;
a reference voltage source;
voltage comparing means coupled to said first peak detecting means and said reference source for producing a charging voltage proportional to said control voltage; and
monostable means coupled to said voltage comparing means, said modulating means and said switching regulator for initiating the production of said first drive signal condition in response to the initiation of said control signal and for initiating the production of said second drive signal condition when a voltage produced by said charging voltage equals a predetermined voltage.
4. A synchronized and regulated power supply according to claim 2 wherein said means including a drive signal generator includes:
first peak detecting means coupled to said modulating means for producing a control voltage equal to the peak amplitude of said control signal during said first duration and providing for a reduction of said control voltage at a predetermined rate subsequent to said first duration;
a reference voltage source;
voltage comparing means coupled to said first peak detecting means and said reference source for producing a first charging voltage when said control voltage is greater than said reference voltage and a second charging voltage when said control voltage is less than said reference voltage; and
monostable means coupled to said voltage comparing means, said modulating means and said switching regulator for initiating the production of said first drive signal conditin in response to the initiation of said control signal and for initiating the production of said second drive signal condition when a voltage produced by said first and second charging voltages equals a predetermined voltage.
5. A synchronized and regulated power supply comprising:
switching regulator means adapted to be coupled to a source of alternating current potential for producing a direct current potential having an amplitude proportional to the duration of a first drive signal condition relative to the duration of a second drive signal condition;
oscillating means adapted to be coupled to a source of synchronizing signals for producing a switching signal having a first predetermined phase relationship with respect to said synchronizing signals;
modulating means coupled to said switching regulator means and said oscillating means, said modulating means including:
means coupled to said oscillating means for producing a control signal for a first predetermined duration, said control signal having said second predetermined phase relationship with respect to said switching signal; and
amplifing means coupled to said means for producing said control signal and said switching regulator for controlling the amplitude of said control signal for said first duration in response to said direct current potential;
means including a drive signal generator coupled to said modulating means and said switching regulator means, including:
first peak detecting means coupled to said modulating means for producing a control voltage proportional to the peak amplitude of said control signal;
a reference voltage source;
voltage comparing means coupled to said first peak detecting means and said reference source for producing a charging voltage proportional to said control voltage; and
monostable means coupled to said voltage comparing means, said modulating means and said switching regulator for initiating the production of said first drive signal condition in response to the initiation of said control signal and for initiating the production of said second drive signal condition when a voltage produced by said charging voltage equals a predetermined voltage; and
an auxiliary oscillator means coupled to said monostable means for repetitively initiating said first drive signal condition when said direct current potential is less than a predetermined amplitude.
6. A synchronized and regulated power supply according to claim 5 wherein said means includes an isolation transformer for providing isolated coupling between said modulating means and said means including a drive signal generator.
7. A synchronized and regulated power supply comprising:
switching regulator means adapted to be coupled to a source of alternating current potential for producing a direct current potential having an amplitude proportional to the duration of a first drive signal condition relative to the duration of a second drive signal condition;
oscillating means adapted to be coupled to a source of synchronizing signals for producing a switching signal having a first predetermined phase relationship with respect to said synchronizing signals;
modulating means coupled to said switching regulator means and said oscillator means, said modulating means including:
means coupled to said oscillating means for producing a control signal for a first predetermined duration, said control signal having said second predetermined phase relationship with respect to said switching signal; and
amplifying means coupled to said means for producing said control signal and said switching regulator for controlling the amplitude of said control signal for said first duration in response to said direct current potential;
means including a drive signal generator coupled to said modulating means and said switching regulator means,
first peak detecting means coupled to said modulating means for producing a control voltage equal to the peak amplitude of said control signal during said first duration and providing for a reduction of said control voltage at a predetermined rate subsequent to said first duration;
a reference voltage source;
voltage comparing means coupled to said first peak detecting means and said reference source for producing a first charging voltage when said control voltage is greater than said reference voltage and a second charging voltage when said control voltage is less than said reference voltage; and
monostable means coupled to said voltage comparing means, said modulating means and said switching regulator for initiating the production of said first drive signal condition in response to the initiation of said control signal and for initiating the production of said second drive signal condition when a voltage produced by said first and second charging voltages equals a predetermined voltage; and
an auxiliary oscillator means coupled to said monostable means for repetitively initiating said first drive signal condition when said direct current potential is less than a predetermined amplitude.
8. A synchronized and regulated power supply according to claim 7 wherein said means including a drive signal generator further includes an isolation transformer for providing isolated coupling between said modulating means and said means including a drive signal generator.
9. A synchronized and regulated power supply, comprising:
switching regulator means adapted to be coupled to a source of alternating current potential for producing a direct current potential and a pulsating direct current having amplitudes proportional to the duration of a first drive signal condition relative to the duration of a second drive signal condition;
oscillating means adapted to be coupled to a source of synchronizing signal for producing a switching signal having a first predetermined phase offset relationship with respect to said synchronizing signals;
modulating means coupled to said switching regulator means and said oscillating means for producing a control signal having a second predetermined phase offset relationship with respect to said switching signal and having an amplitude which is proportional to the amplitude of said direct current potential;
means including a drive signal generator coupled to said modulating means and said switching regulator means for initiating the production of said first drive signal condition in response to the initiation of said control signal and for controlling the duration of said first drive signal condition relative to the duration of said second drive signal condition in response to the amplitude of said control signal;
delay means coupled to said oscillating means for producing a delayed switching signal; and
deflection means coupled to said switching regulator means, said delay means, and said oscillating means for producing repetitive deflection cycles having a third predetermined phase relationship with respect to said synchronizing signals such that the current only flows between said switching regulator means and said deflection means during an energy replenishing period of said deflection cycle.
Description:
BACKGROUND OF THE INVENTION
The invention relates to a synchronized and regulated power supply.
In order to maintain optimum performance of the television receiver, it is desirable to provide a regulated direct current potential (B+) to the various circuits of the receiver. Numerous types of regulated power supply circuits have been used to provide the desired regulation. One such type is a switching regulator power supply.
A switching regulator power supply is a very efficient type of regulated power supply since the switching device is alternately turned off and on and the regulation is accomplished by controlling the relative durations of the off condition and the on condition of the switching device.
In order to minimize the interference produced by switching of the switching regulator power supply, it is desirable to synchronize the switching with the synchronizing signals utilized to synchronize the deflection circuits. In addition to the synchronizing signals, the B+ level must be coupled to the switching device to provide feedback to control the B+ level.
In television receivers, where it is desirable to isolate the chassis from the alternating current potential source having an earthen ground reference to prevent electrical shock to the operator, the coupling of B+ and synchronizing signals to the switching device requires numerous components or complicated construction of an isolation transformer.
Also, television receivers utilizing line rate deflection systems of the type disclosed in U.S. Pat. No. 3,452,244 employing two bidirectional conducting switches require an input reactor between the source of B+ and the commutating bidirectional conducting switch to prevent short circuiting of the B+ during the commutating interval (i.e., when the commutating switch is turned on).
SUMMARY OF THE INVENTION
In accordance with the invention, a synchronized and regulated power supply for a television receiver comprises a switching regulator means adapted to be coupled to a source of alternating current potential for producing a direct current potential having an amplitude proportional to the duration of a first drive signal condition relative to the duration of a second drive signal condition. Oscillating means adapted to be coupled to a source of synchronizing signals produces a switching signal having a first predetermined phase relationship with respect to the synchronizing signals. Modulating means coupled to the switching regulator means and the oscillating means produces a control signal having a second predetermined phase relationship with respect to the switching signal and having an amplitude which is proportional to the amplitude of the direct current potential. Means including a drive signal generator coupled to the modulating means and the switching regulator means initiates the production of the first drive signal condition in response to the initiation of the control signal and controls the duration of the first drive signal condition relative to the duration of the second drive signal condition in response to the amplitude of said control signal.
A more detailed description of the preferred embodiment of the invention is given in the following detailed description and the accompanying drawings of which:
FIG. 1 is a schematic diagram, partially in block form, of a non-isolated portion of a synchronized and regulated power supply of a television receiver;
FIG. 2 is a schematic diagram, partially in block form, of a preferred embodiment of an isolated portion of the synchronized and regulated power supply of the television receiver;
FIGS. 3A-3J illustrate normalized waveforms obtained at various points in the diagram of a first embodiment of FIG. 1 and the diagram of FIG. 2; and
FIG. 4A-4J illustrate normalized waveforms obtained at various points in the diagram of a second embodiment of FIG. 1 and the diagram of FIG. 2.
DESCRIPTION OF THE INVENTION
FIG. 1 is a schematic 
diagram, partially in block form, of the non-isolated portion 42 of the television receiver of FIGS. 1 and 2. A source of alternating current (not shown), having an earthen ground reference, is coupled through a diode 16 to a filter capacitor 18 thereby providing for the development of a positive direct current potential at terminal 20 with respect to earthen ground. Terminal 20 is coupled through a winding 22a of an isolation transformer 22 to the collector electrode, designated as terminal I, of switching transistor 24. Winding 22a is magnetically coupled to and polarized as indicated by the polarizing dots with windings 22b and 22c of isolation transformer 22. A first terminal of winding 22b is designated as terminal J and another terminal of winding 22b is designated as terminal K. A first terminal of winding 22c is coupled to terminal K and another terminal of winding 22c is designated as terminal L. The emitter electrode of transistor 24 is coupled to earthen ground.
Terminal 20 is also coupled through a resistor 104 to the cathode of a zener diode 106. The anode of zener diode 106 is coupled to earthen ground. A filter capacitor 108 is coupled in parallel with zener diode 106. Zener diode 106 provides for a regulated potential at the cathode electrode with respect to earthen ground. The cathode of zener diode 106 is coupled through a collector resistor 110 to the collector electrode of transistor 112. The emitter electrode of transistor 112 is coupled to earthen ground. The collector electrode of transistor 112 is also coupled through a resistor 113 to the base electrode of a transistor 114 and a terminal 3 of a monostable 32. The emitter electrode of transistor 114 is coupled to the cathode electrode of zener diode 106. The collector electrode of transistor 114 is coupled through an integrating network comprising a capacitor 116 and a resistor 118 in parallel combination to earthen ground. The collector electrode of transistor 114 is also coupled to the base electrode of transistor 120 by means of a resistor 122. The emitter electrode of transistor 120 is coupled to earthen ground. The collector electrode of transistor 120 is coupled to the cathode of zener diode 106 by means of a resistor 124, to the base electrode of a transistor 126 by means of a resistor 128, and to a first gate 130 of a dual input NAND gate 132. The emitter electrode of transistor 126 is coupled to earthen ground and the collector electrode is coupled to the cathode of zener diode 106 by means of a resistor 134 and to a terminal 4 of monostable 32. Transistors 112, 114, 120 and 126, in conjunction with their associated circuitry, form a shaper and peak detector 28.
A second gate 136 of dual input NAND gate 132 is coupled through a capacitor 138 to earthen ground and to the output terminal of dual input NAND gate 132 by means of a resistor 140. Capacitor 138, resistor 140 and dual input NAND gate 132 form an auxiliary oscillator 26. The output terminal of dual input NAND gate 132 is coupled to terminal 5 of monostable 32.
The cathode of zener diode 106 is also coupled to pin 14 of monostable 32 and the collector electrode of a transistor 142. A terminal D of a winding 40a of an isolation transformer 40 is coupled through a resistor 144 to the base electrode of transistor 142, through a resistor 146 to the base electrode of transistor 112, and through a parallel combination of a protective and clamping diode 148 and a resistor 150 to earthen ground. Another terminal of winding 40a is coupled to earthen ground. Winding 40a of transformer 40 is magnetically coupled to and polarized as indicated by the polarizing dots with a winding 40b. A first terminal of winding 40b is designated as terminal M and another terminal is designated as terminal N.
The emitter electrode of transistor 142 is coupled to earthen ground by means of an integrating network comprising the parallel combination of a capacitor 152 and the series combination of a resistor 154, the resistive element of a potentiometer 156 and a resistor 158. The transistor 142 and the integrator form a peak detector 30.
The wiper terminal of potentiometer 156, designated as terminal F, is coupled to the base electrode of a transistor 160. The potentiometer provides for adjustment of the voltage at the base electrode of transistor 160 relative to the peak voltage at the base electrode of transistor 142. Transistor 160 operates in conjunction with a transistor 162 and associated circuitry to form a voltage comparator and differential amplifier 34. The emitter electrodes of transistors 160 and 162 are coupled to earthen ground by means of a resistor 164. The collector electrode of transistor 160 is coupled through a resistor 166 to the cathode electrode of zener diode 106, and the collector electrode of transistor 162 is coupled through a resistor 168 to the cathode electrode of zener diode 106. Connected in this manner, the voltage at the collector electrode of transistor 162 increases as the voltage at terminal F increases within a predetermined range of voltage determined by a reference voltage on the base electrode of transistor 162.
The collector electrode of transistor 162 is also coupled through a series combination of a resistor 170 and a capacitor 172 to terminal 10 of monostable 32. The resistor 170, the capacitor and the voltage at the collector of transistor 162 determine the width of the logic 0 portion of the drive pulse produced by monostable 32 at terminal 1. The junction of resistor 170 and capacitor 172, designated as terminal G, is coupled to terminal 11 of monostable 32. The base electrode of transistor 162 is coupled to the cathode of a zener diode 174 and coupled to the cathode of zener diode 106 by means of a resistor 176. The anode of zener diode 174 is coupled to earthen ground. The zener diode 174 and the resistor 176 form a reference source 38 and provide a relatively constant voltage at the base electrode of transistor 162 and thereby serves as a reference for the voltage comparator and differential amplifi
er 34.
The output terminal 1 of monostable 32, designated as terminal H, is coupled through a parallel combination of a resistor 178 and a capacitor 180 to the base electrode of a transistor 182. The base electrode of transistor 182 is also coupled through a resistor 184 to earthen ground. The emitter electrode of transistor 182 is coupled to earthen ground, and the collector electrode is coupled to a first terminal of a winding 186a of a driver transformer 186 and to earthen ground by means of a high frequency suppression network comprising a series combination of a resistor 188 and a capacitor 190 to earthen ground. The other terminal of winding 186a is coupled through a resistor 192 to terminal 20 and through a capacitor 194 to earthen ground.
Another winding 186b of driver transformer 186, polarized with respect to winding 186a as indicated by polarizing dots, has a first terminal coupled to earthen ground and another terminal coupled by means of a parallel combination of a capacitor 196 and a resistor 198 to the base electrode of transistor 24. The base electrode of transistor 24 is also coupled through a parallel combination of a resistor 200 and a protection diode 202 to earthen ground. The emitter electrode of transistor 24 is coupled to earthen ground and the collector electrode, designated as terminal I, is coupled to earthen ground by means of a high frequency suppression network comprising a series combination of a resistor 204 and a capacitor 206. The transistor 182 and associated circuitry comprises a driver network 36 which provides for power gain and polarity inversion of the signal developed at terminal H of monostable 32.
FIG. 2 is a schematic diagram, partially in block form, of a preferred embodiment of the isolated portion 44 of the synchronized and regulated power supply of the television receiver of FIGS. 1 and 2.
Terminal J of winding 22b is coupled to the anode electrode of a diode 52. The cathode electrode of diode 52, designated as terminal C, provides a pulsating direct current voltage to a deflection system 53 and is coupled to the anode electrode of an SCR 54 and to the cathode electrode of a damper diode 56. The SCR 54 and the damper diode 56 comprise a commutating switch 58. The cathode electrode of SCR 54 and the anode electrode of damper diode 56 are coupled to reference potential. Terminal C is also coupled to the anode of SCR 60 by means of a commutating network 62 comprising a series combination of a commutating inductor 64, a first commutating capacitor 66, and a second commutating capacitor 68. An auxiliary capacitor 70 is coupled between the junction of commutating capacitors 66 and 68 and reference potential. A damper diode 72 is coupled in anti-parallel combination with SCR 60 to form a trace switch 73. The anode of SCR 60 is coupled through a series combination of a set of yoke windings 74 and an S-shaping capacitor 76 to reference potential. The anode of SCR 60 is also coupled through a series combination of a winding 78a of a high voltage transformer 78 and a DC blocking capacitor 80 to reference potential. A trace SCR gating network 98 comprising a resistor 278, a capacitor 280, a capacitor 282, a resistor 284, and an inductor 286 coupled between the anode electrode of SCR 54 and the gate electrode of SCR 60 provides for gating of the trace SCR 60 at the proper point in the deflection interval (t0 - t0 ' of FIGS. 3 and 4).
A winding 78b of high voltage transformer 78 has a first terminal coupled to reference potential and another terminal coupled to a high voltage multiplier and rectifier 82. An output terminal 84 of high voltage multiplier and rectifier 82 is coupled to a kinescope tube (not shown). Pulses produced by winding 78b are rectified and added in high voltage multiplier and rectifier 82 to produce a high voltage direct current potential at terminal 84 required to provide the necessary beam current in the kinescope tube. A first terminal of a winding 78c is coupled to reference potential and another terminal is coupled to a horizontal oscillator and automatic phase control (APC) network 96.
Terminal K is coupled to the anode electrode of diode 86 and the cathode electrode of diode 86 is coupled through the capacitor 88 to reference potential. The cathode of diode 86 which provides a source of B+ is also coupled through a resistor 208 to terminal M. Terminal M is coupled through a parallel combination of a resistor 210 and a filter capacitor 212 to reference potential. The cathode of diode 86 is also coupled through a resistor 214 to the cathode electrode of a zener diode 216. The anode electrode of zener diode 216 is coupled to reference potential. A filter capacitor 218 is coupled in parallel with zener diode 216. The cathode electrode of zener diode 216 is coupled through a series combination of a resistor 220 and a parallel combination of a zener diode 224 and a capacitor 226 to reference potential, the cathode electrode of diode 224 being coupled to terminal 14 of a monostable 222 and the anode electrode of diode 224 being coupled to reference potential. Terminal 14 of monostable 222 is coupled through a series combination of a resistor 228 and a capacitor 230 to terminal 10 of monostable 222. The junction of resistor 238 and capacitor 230 is coupled to terminal 11 of monostable 222. An output terminal 6 of monostable 222 is coupled through a resistor 232 to the base electrode of a switching transistor 234 and through a fast discharge diode 236 to reference potential. The emitter electrode of transistor 234 is coupled through a level shifting diode 238 to reference potential. Resistor 228, capacitor 230 and the voltage at terminal 14 of monostable 222 determined the width of the logic 1 portion of the signal produced by monostable 222 at terminal 6.
The collector electrode of transistor 234, which provides a control signal which has an amplitude proportional to B+, is coupled to terminal N and through a high frequency suppression network comprising a series combination of a resistor 240 and a capacitor 242 to reference potential. Terminals 3 and 7 of monostable 222 are coupled to reference potential. Monostable 222, transistor 234 and associated circuitry comprise a modulator 90.
The cathode electrode of zener diode 216 is also coupled through a resistor 244 to terminal 1 of a horizontal oscillator and APC 96 and through a parallel combination of a high frequency bypass capacitor 246 and a low frequency filter capacitor 248 to reference potential. Terminal 16 of oscillator and APC 96 is coupled to reference potential. A sync source 92 which provides a switching signal at line deflection rate is also coupled to oscillator and APC 96 to provide for proper phasing of the signal developed at output terminal A of oscillator and APC 96 to synchronize the pulse developed by winding 78c with the synchronizing signal produced by the synchronizing source 92. Output terminal A is coupled through a series combination of an RF choke 250 and a resistor 252 to terminal 5 of monostable 222. The junction of choke 250 and resistor 252 is coupled through a resistor 254 to reference potential and through a series combination of a resistor 256 and a capacitor 258 to the base electrode of a transistor 260. The junction of resistor 256 and capacitor 258 is coupled through a capacitor 262 to reference potential. The resistor 256 and the capacitor 262 provide delay of the signal between terminal A of oscillator and APC 96 and the base electrode of transistor 260. The base electrode of transistor 260 is coupled though a resistor 264 to reference potential. The emitter electrode of transistor 260 is coupled to reference potential and the collector electrode of transistor 260 is coupled through a resistor 266 to the cathode electrode of zener diode 216 and to the base electrode of a transistor 268 by means of a resistor 270. The base electrode of transistor 268 is coupled to reference potential by means of a capacitor 272. The resistor 270 and the capacitor 272 form a pulse stretcher and give some additional delay. The emitter electrode of transistor 268 is coupled to the cathode electrode of zener diode 216 and the collector electrode of transistor 268 is coupled to reference potential by means of a resistor 274 and to the gate electrode of SCR 54 by means of a capacitor 276. Transistors 260 and 268 and associated circuitry comprise a pulse shaper and delay network 94.
The transistor 24 operating in conjunction with diode 16, capacitor 18, isolation transformer 22, diode 52, diode 86 nd capacitor 88 comprise a switching regulator. The switching regulator produces B+ which has an amplitude proportional to the duration that transistor 24 is turned on relative to the duration transistor 24 is turned off by drive signals.
Since the non-isolated portion 42 (FIG. 1) operates in conjunction with the isolated portion 44 (FIG. 2), the explanation of the operation will simultaneously consider both FIG. 1 and FIG. 2. Also, the operation will be first explained by referring to the solid curves of FIGS. 3A-3J and 4A-4J and then the dotted curves.
An alternating current source (not shown) provides an alternating current voltage which is rectified by the diode 16 and filtered by means of the capacitor 18 to develop a direct current voltage at terminal 20 with respect to earthen ground. The direct current voltage at terminal 20 provides for energization of the non-isolated portion 42 of the television receiver of FIGS. 1 and 2.
Before energy can be transferred from winding 22a to windings 22b and 22c, which provides for energization of the isolated portion 44 of the television receiver of FIGS. 1 and 2, the transistor 24 must alternately be switched off and on thereby creating an alternating flux in the core of isolation transformer 22. In the absence of such switching of transistor 24, no B+ is developed at the cathode of diode 86 and, therefore, no signal appears at terminal D of winding 40a of isolation transformer 40.
With no signal at terminal D, transistor 112 is cut off, thereby providing a logic 1 at terminal E. The logic 1 level at terminal E provides for cutoff of transistor 114. It will be assumed that the non-isolated portion 42 has previously been de-energized for a relatively long period of time; therefore, the collector electrode of transistor 114 is at earthen ground (logic 0). With the collector electrode of transistor 114 at a logic 0, the base electrode of transistor 120 is at a logic 0; therefore, transistor 120 is cut off. With the transistor 120 cut off, the collector electrode of transistor 120, the base electrode of transistor 126 and terminal 130 of dual input NAND gate 132 are at logic 1. With a logic 1 at the base electrode of transistor 126, the collector electrode is at a logic 0.
With the logic 1 at terminal E and a logic 0 at the collector electrode of transistor 126, monostable 32 is responsive; to positive transitions at terminal 5. With a logic 1 on terminal 130 of dual input NAND gate 132, terminal 5 of monostable 32 will be alternately pulsed from a logic 1 to a logic 0 at a rate determined by capacitor 138 and resistor 140.
Also, in the absence of signal on te
rminal D of winding 40a, the transistor 142 will be cut off; therefore, the voltage at terminal F will be at a logic 0 thereby placing transistor 160 in cutoff and transistor 162 in maximum conduction. With transistor 162 in maximum conduction, the voltage at the collector electrode of transistor 162 will be at a minimum voltage determined by the zener voltage of zener diode 174 and resistors 164 and 168. Since the voltage at the collector of transistor 162 is less than the zener voltage of zener diode 106, the charge rate of the capacitor 172 will be slower than when the transistor 162 is cut off. This slow charging rate of the capacitor 172 provides for a minimum duration logic 1 pulse (maximum monostable period) being produced by the monostable 32 at output terminal H when no signal is present at terminal D.
Transitions from a logic 0 to a logic 1 at terminal 5 of monostable 32 provided by the auxiliary oscillator 26 produce a transition from logic 1 to a logic 0 at terminal H and a negative transition at terminal G. As the capacitor 172 charges through resistor 168, the voltage at terminal G begins to become more positive. When the voltage at terminal G reaches a threshold voltage level established by the characteristics of monostable 32, a transition from a logic 0 to a logic 1 occurs at terminal H.
Transitions from a logic 1 to a logic 0 at terminal H, as shown at T0 in FIG. 3H, provide for a cutoff of the transistor 182 and the production of a positive voltage at the base electrode of transistor 24 with respect to earthen ground. With a positive voltage at the base electrode of transistor 24, current flows from terminal 20 through winding 22a of isolation transformer 22 and transistor 24 to earthen ground. The current flowing through winding 22a during the saturation of transistor 24 produces a logic 0 at terminal I as shown in FIG. 3I and a negative potential at terminal J and terminal K with respect to terminal L of windings 22b and 22c similar to that shown in FIG. 3J.
When the signal at terminal H of monostable 32 makes a transition from a logic 0 to a logic 1, as shown at t6 in FIG. 3H, transistor 182 is placed in saturation, thereby producing a negative potential at the base electrode of transistor 24 with respect to earthen ground. With a negative potential at the base electrode of transistor 24, transistor 24 is cut off, thereby providing for a collapse of the field developed in isolation transformer 22 during saturation of transistor 24. The collapse of field in isolation transformer 22 produces a positive voltage at terminals J and K with respect to terminal L of winding 22b and 22c similar to that shown in FIG. 3J.
With a signal similar to that shown in FIG. 3J being produced at terminal J and K of windings 22b and 22c, a pulsating direct current voltage is developed at terminal C and B+ is developed at the cathode of diode 86. With B+ being developed at the cathode of diode 86, oscillator and APC 96 starts producing a signal similar to that shown in FIG. 3A at terminal A. The signal at output terminal A of oscillator and APC 96 provides for triggering of the monostable 222, thereby providing a signal at terminal 6 of monostable 222 similar to that shown in FIG. 3D but of constant amplitude. The signal at terminal 6 of monostable 222 provides for switching of transistor 234 and the production of a waveform at terminal D as shown in FIG. 3D. The amplitude of the signal at terminal D is directly proportional to the amplitude of the B+ produced at the cathode of diode 86. The signal at terminal A of oscillator and APC 96 is shaped and delayed by shaper and delay network 94, thereby providing a gating signal at terminal B as shown in FIG. 3B. In addition, due to choice of components in pulse shaper and delay network 94 and modulator 90, pulses are developed at terminal D of transformer 40 before p
ulses are produced at terminal B during initial start-up of the power supply (i.e., prior to t0).
The transition from a logic 0 to a logic 1 at output terminal B of pulse shaper and delay 94 occurs at t1 as shown in FIG. 3B, thereby providing for assurance that the commutating switch 58 is not turned on until after the voltage at terminal J goes negative. The voltage at terminal J remains negative for an interval t0 -t6. Since the commutating switch 58 ceases conduction at t4 as shown in FIG. 3C, no significant current flows through the diode 52 during conduction of commutating switch 58. The deflection system 53 operates similar to that described in U.S. Pat. No. 3,452,244 and thereby produces pulses across winding 78c which, when coupled to the oscillator and APC 96 and compared to signals produced by the sync source 92, produce a signal at output terminal A which maintains synchronization of the signals produced by the sync source 92 and the pulses across winding 78c.
At t0 a positive pulse is initiated at terminal D of winding 40a. The initiation of the positive pulse provides for saturation of transistor 112 by way of resistor 146, thereby providing a logic 0 at terminal E. The logic 0 at terminal E provides for base-emitter current in the transistor 114 by way of resistor 113, resulting in saturation of transistor 114. With transistor 114 in saturation, the voltage at the collector of transistor 114 is at a logic 1. With a logic 1 at the collector electrode of transistor 114, the transistor 120 is placed in saturation by means of base-emitter current flow produced by resistor 122. With transistor 120 in saturation, the voltage at terminal 130 of dual input NAND gate 132 is at a logic 0 and the base electrode of transistor 126 is at a logic 0. With a logic 0 at terminal 130 of dual input NAND gate 132, the auxiliary oscillator 26 is disabled, thereby maintaining a logic 1 at the output of dual input NAND gate 132. With the logic 0 at the base electrode of transistor 126, the collector electrode of transistor 126 at a logic 1 and the output of dual input NAND gate 132 at a logic 1, the monostable 32 produces a transition from a logic 1 to a logic 0 at output terminal H, as shown in FIG. 3H, when a transition from a logic 0 to a logic 1 occurs at terminal D of winding 40a, as shown at t0 in FIG. 3D.
By altering the time constant of the integrator of the peak detector 30, two different modes of operation can be obtained. Each of these modes of operation will be considered as a separate embodiment of a non-isolated portion 42 of the television receiver.
A first embodiment utilizes an integrator having a time constant very much longer than the pulse repetition rate (t0 -t0 ') of the oscillator and APC 96. With the long time constant, the positive pulses at terminal D of winding 40a produce a voltage across capacitor 152 which is nearly constant and is approximately equal to the maximum amplitude of the positive pulses at terminal D. A voltage proportional to the voltage across capacitor 152 is therefore produced at terminal F and is as shown in FIG. 3F.
Assuming that the amplitude of the positive pulse at terminal D is within the predetermined range to which voltage comparator 34 is responsive, the voltage at the collector of transistor 162 is proportional to the voltage at terminal F.
At t0 the voltge at terminal G of monostable 32 goes negative as shown in FIG. 3G. After t0 the voltage at terminal G begins to increase at an exponential rate determined by the voltage at the collector of transistor 162. When the voltage at terminal G reaches the threshold level established by the characteristics of the monostable 32, the output terminal H of monostable 32 makes a transition from a logic 0 to a logic 1 as shown in FIG. 3H at t6.
Transitions at terminal H produce corresponding transitions at terminals I, J and K as described above under conditions whereby the auxiliary oscillator 26 is operational. The transitions at terminals I, J and K provide for operation of the deflection system 53 and production of B+ at the cathode of diode 86, thereby maintaining operation of the isolated portion 44.
Components of modulator 90 and pulse shaper and delay 94 are chosen to delay the production of gating pulses at terminal B during the transient period until positive pulses at terminal C have a proper phase relationship with respect to the signals produced by the sync source to prevent current flow through diode 52 during conduction of the commutating switch 58. The aforementioned delay prevents excessive current flow through diode 52 during the start-up of power supply.
When B+ increases, the pulse amplitude at terminal D increases as shown by the dotted curve of FIG. 3D, a larger voltage is produced at terminal F as shown in FIG. 3F, and the voltage at terminal G reaches the threshold level at t5 rather than t6. With the voltage at terminal G reaching the threshold level faster, the time duration during which the voltage at terminals H, I, J and K are at a logic 0 is less during each deflection interval. This change at terminals J and K results in a drop of the peak voltage at terminal J and the B+ to the levels produced by the solid curves of FIG. J even though the peak-to-peak voltage at terminals J and K is greater than under the original conditions. By maintaining a relatively constant peak voltage at terminal J and a relatively constant B+, the operation of the isolated portion 44 is maintained relatively uniform.
A second embodiment utilizes an integrator having a time constant which is shorter than the pulse repetition rate of the oscillator and APC 96. With the short time constant, the positive pulse at terminal D of winding 40a produces a voltage at the emitter electrode of transistor 142 which is approximately equal to the maximum amplitude of the positive pulse produced at terminal D during the interval t0 -t1 . A voltage proportional to the voltage at the emitter electrode of transistor 142 is produced at terminal F. At t0 a voltage is developed at terminal F which is in excess of the zener voltage of the zener diode 174. This condition produces maximum conduction of transistor 160 and cutoff of transistor 162. With transistor 162 in cutoff, the collector electrode of transistor 162 is at a potential approximately equal to the zener voltage of zener diode 106, thereby providing for a relatively fast charging of capacitor 172 from the level at t0 as shown in FIG. 4G.
The point at which the voltage at terminal G reaches the threshold level as shown in FIG. 4G determines when the signal at output terminal H of monostable 32 makes a transition from a logic 0 to a logic 1.
At t1 the voltage at terminal D goes negative, providing for cutoff of transistor 112 and a logic 1 at terminal E. With a logic 1 at terminal E, transistor 114 is placed in cutoff and capacitor 116 begins to discharge through the resistor 118 and through the series combination of resistor 122 and the base-emitter junction of transistor 120. Due to the repetition rate of the pulses produced at terminal D of winding 40a of isolation transformer 40 relative to the time constant of the capacitor 116, resistor 118 and resistor 122, the voltage at the collector electrode of transistor 114 will not drop below a level which will sustain saturation of transistor 120 between pulses produced at terminal D. Therefore, terminal 130 of dual input NAND gate 132 will remain at a logic 0 and the output of NAND gate 132 will remain at a logic 1.
With the negative voltage at terminal D of winding 40a, the transistor 142 will be cut off and the capacitor 152 will begin to discharge through the resistors 154, 156 and 158 as shown in FIG. 4F between t1 and t0 '. At t2, the voltage at terminal F is equal to the zener voltage of zener diode 174. When the voltage at terminal F drops just below this level, transistor 160 cuts off and transistor 162 is placed in maximum conduction. During the interval t2 - t6, the transistor 162 remains in maximum conduction and the rate of charging of capacitor 172 is less than the rate of charging of capacitor 172 with transistor 162 in cutoff, as shown in FIG. 4G. At t6 the signal at output terminal H makes a transition from logic 0 to logic 1 as shown in FIG. 4H as a result of the voltage at terminal G reaching the threshold level as shown in FIG. 4G.
Positive and negative transitions at output terminal H of monostable 32 produce positive and negative transitions at termial I and terminal J as described above under conditions whereby the auxiliary oscillator 26 is operational.
When the pulse amplitude at the terminal D of winding 40a increases as shown in dotted curve of FIG. 4D, the maximum amplitude of the voltage at terminal F increases as shown in FIG. 4F. This change of maximum voltage at terminal F increases the time during which capacitor 172 is charged at the faster rate as shown in FIG. 4G and decreases the total time for charging capacitor 172 to the threshold level. This decrease in total time for charging the capacitor 172 to the threshold level decreases the duration during which terminal H of monostable 32 is at a logic 0 as shown in FIG. 4H and decreases the duration of saturation of the transistor 24 which provides for compensation for an increase of direct current voltage at terminal 20 which initially produced an increase of the pulse amplitude at terminal D as shown in FIG. 4D. This compensation can be seen by referring to FIG. 4J where it can be seen that the positive peak voltage remains approximately the same due to the change of saturation period of the transistor 24 in response to an increase of the pulse amplitude at terminal D of winding 40a.
The power supply of the television receiver as described above provides for regulation of B+, synchronization of the switching transistor 24 at the line rate to reduce interference, isolation of the alternating current source from operator accessible components coupled to reference potential and elimination of the input reactor of the deflection system 53 by providing synchronization of B+ with conduction of the commutating switch 58.
One particular configuration corresponding to that illustrated in FIGS. 1 and 2 is set forth below in terms of component types.
______________________________________
Monostable 32 SN74121 Texas Instruments Oscillator and APC 96 TBA920 Philips Monostable 222 SN74121 Texas Instruments
______________________________________
METZ 7096 CLASSIC COLOR (CH679G) CHASSIS 679G CIRCUIT ARRANGEMENT IN A PICTURE DISPLAY DEVICE UTILIZING A STABILIZED SUPPLY VOLTAGE CIRCUIT:
A stabilized supply voltage circuit for a picture display device
comprising a chopper wherein the switching signal has the line
frequency and is duration-modulated. The coil of the chopper
constitutes the primary winding of a transformer a secondary winding
of which drives the line output transistor so that the switching
transistor of the chopper also functions as a driver for the line
output stage. The oscillator generating the switching signal may be
the line oscillator. In a special embodiment the driver and line
output transistor conduct simultaneously and in order to limit the
base current of the line output transistor a coil shunted by a diode
is incorporated in the drive line of the line output transistor.
Other secondary windings of the transformer drive diodes which
conduct simultaneously with the efficiency diode of the chopper so
as to generate further stabilized supply voltages.
1.
An electrical circuit arrangement for a picture display device
operating at a given line scanning frequency, comprising a source of
unidirectional voltage, an inductor, first switching transistor means
for periodically energizing said inductor at said scanning frequency
with current from said source, an electrical load circui
coupled to
said inductor and having applied thereto a voltage as determined by
the ratio of the ON and OFF periods of said transistor, means for
maintaining the voltage across said load circuit at a given value
comprising means for comparing the voltage of said load circuit with a
reference voltage, means responsive to departures of the value of
the load circuit voltage from the value of said reference voltage
for varying the conduction ratio of the ON and OFF periods of said
transistor thereby to stabilize said load circuit voltage at the
given value, a line deflection coil system for said picture display
device, means for energizing said line deflection coil system from
said load voltage circuit means, means for periodically interrupting
the energization of said line deflection coil comprising second
switching means and means coupled to said inductor for deriving
therefrom a switching current in synchronism with the energization
periods of said transistor and applying said switching current to
said switching means thereby to actuate the same, and means coupled
to said switching means and to said load voltage circuit for
producing a voltage for energizing said 2. A circuit as claimed in
claim 1 wherein the duty cycle of said switching 3.
A circuit as claimed in claim 1 further comprising an efficiency
first 4. A circuit as claimed in claim 3 further comprising at least
a second diode coupled to said deriving means and to ground, and
being poled to 5. A circuit as claimed in claim 1 wherein said
second switching means comprises a second transistor coupled to said
deriving means to conduct simultaneously with said first transistor,
and further comprising a coil coupled between said driving means and
said second transistor and a third diode shunt coupled to said coil
and being poled to conduct when said 6. A circuit as claimed in
claim 1 further comprising a horizontal oscillator coupled to said
first transistor, said oscillator being the 7. A circuit as claimed
in claim 1 further comprising means coupled to said inductor for
deriving filament voltage for said display device.
Description:
The
invention relates to a circuit arrangement in a picture display
device wherein the input direct voltage between two input terminals,
which is obtained be rectifying the mains alternating voltage, is
converted into a stabilized output direct voltage by means of a
switching transistor and a coil and wherein the transistor is connected
to a first input terminal and an efficiency diode is connected to th
e
junction of the transistor and the coil. The switching transistor
is driven by a pulsatory voltage of line frequency which pulses are
duration-modulated in order to saturate the switching transistor
during part of the period dependent on the direct voltage to be
stabilized and to cut off this transistor during the remaining part
of the period. The pulse duration modulation is effected by means of
a comparison circuit which compares the direct voltage to be
stabilized with a substantially constant voltage, the coil
constituting the primary winding of a transformer.
Such
a circuit arrangemen
t is known from German "Auslegeschrift"
1.293.304. wherein a circuit arrangement is described which has for
its object to convert an input direct voltage which is generated
between two terminals into a different direct voltage. The circuit
employs a switch connected to the first terminal of the input
voltage and periodically opens and closes so that the input voltage
is converted into a pulsatory voltage. This pulsatory voltage is
then applied to a coil. A diode is arranged between the junction of
the switch and the coil and the second terminal of the input voltage
whilst a load and a charge capacitor in parallel thereto are
arranged between the other end of the coil and the second terminal
of the input voltage. The assembly operates in accordance with the
known efficiency principle i.e., the current supplied to the load
flows alternately through the switch and through the diode. The
function of the switch is performed by a switching transistor which
is driven by a periodical pulsatory voltage which saturates this
transistor for a given part of the period. Such a configuration is
known under different names in the literature; it will be referred to
herein as a "chopper."
A
known advantage thereof, is that the switching transistor must be
able to stand a high voltage or provide a great current but it need
not dissipate a great power. The output voltage of the chopper is
compared with a constant reference voltage. If the output voltage
attempts to vary because the input voltage and/or the load varies, a
voltage causing a duration modulation of the pulses is produced at
the output of the comparison arrangement. As a result the quantity
of the energy stored in the coil varies and the output voltage is
maintained constant. In the German "Auslegeschrift" referred to it
is therefore an object to provide a stabilized supply voltage device.
In
the circuit arrangement according to the mentioned German
"Auslegeschrift" the frequency of the load variations or a harmonic
thereof is chosen as the frequency for the switching voltage.
Particularly when the load fed by the chopper is the line deflection
circuit of a picture display device, wherein thus the impedance of
the load varies in the rhythm of the line frequency, the frequency
of the switching voltage is equal to or is a multiple of the line
frequency.
It
is to be noted that the chopper need not necessarily be formed as
that in the mentioned German "Auslegeschrift." In fact, it is known
from literature that the efficiency diode and the coil may be
exchanged. It is alternatively possible for the coil to be provided at
the first terminal of the input voltage whilst the switching
transistor is arranged between the other end and the second terminal
of the input voltage. The efficiency diode is then provided between
the junction of said end and the switching transistor and the load.
It may be recognized that for all these modifications a voltage is
present across the connections of the coil which voltage has the same
frequency and the same shape as the pulsatory switching voltage.
The control voltage of a line deflection circuit is a pulsatory
voltage which causes the line output transistor to be saturates and
cut off alternately. The invention is based on the recognition that
the voltage present across the connections of the coil is suitable
to function as such a control voltage and that the coil constitutes
the primary of a transformer. To this end the circuit arrangement
according to the invention is characterized in that a secondary
winding of the transformer drives the switching element which applies a
line deflection current to line deflection coils and by which the
voltage for the final anode of a picture display tube which forms
part of the picture display device is generated, and that the ratio
between the period during which the switching transistor is
saturated and the entire period, i.e., the switching transistor duty
cycle is between 0.3 and 0.7 during normal operation.
The
invention is also based on the recognition that the duration
modulation which is necessary to stabilize the supply voltage with
the switching transistor does not exert influence on the driving of
the line output transistor. This resides in the fact that in case of
a longer or shorter cut-off period of the line output transistor
the current flowing through the line deflection coils thereof is not
influenced because of the efficiency diode current and transistor
current are taken over or, in case of a special kind of transistor,
the collector-emitter current is taken over by the base collector
current and conversely. However, in that case the above-mentioned
ratios of 0.3 : 0.7 should be taken into account since otherwise
this take-over principle is jeopardized.
As will be fu
rther
explained the use of the switching transistor as a driver for the
line output transistor in an embodiment to be especially described
hereinafter has the further advantage that the line output transistor
automatically becomes non-conductive when this switching transistor
is short circuited so that the deflection and the EHT for the
display tube drop out and thus avoid damage thereof.
Due
to the step according to the invention the switching transistor in
the stabilized supply functions as a driver for the line deflection
circuit. The circuit arrangement according to the invention may in
addition be equipped with a very efficient safety circuit so that
the reliability is considerably enhanced, which is described in the
U.S. Pat. No. 3,629,686. The invention is furthermore based on the
recognition of the fact that the pulsatory voltage present across
the connections of the coil is furthermore used and to this end the
circuit arrangement according to the invention is characterized in
that secondary windings of the transformer drive diodes which
conduct simultaneously with the efficiency diode so as to generate
further stabilized direct voltages, one end of said diodes being
connected to ground.
In
order that the invention may be readily carried into effect, a few
embodiments thereof will now be described in detail by way of
example with reference to the accompanying diagrammatic drawings in
which:
FIG. 1 shows a principle circuit diagram
wherein the chopper and the line deflection circuit are further
shown but other circuits are not further shown.
FIGS.
2a, 2b and 2c show the variation as a function of time of two
currents and of a voltage occurring in the circuit arrangement
according to FIG. 1.
FIGS. 3a 3b, 3c and 3d show other embodiments of the chopper.
FIGS. 4a and 4b show modifications of part of the circuit arrangement of FIG. 1.
In
FIG. 1 the reference numeral 1 denotes a rectifier circuit which
converts the mains voltage supplied thereto into a non-stabilized
direct voltage. The collector of a switching transistor 2 is
connected to one of the two terminals between which this direct
voltage is obtained, said transistor being of the npn-type in this
embodiment and the base of which receives a pulsatory voltage which
originates through a control stage 4 from a modulator 5 and causes
transistor 2 to be saturated and cut off alternately. The voltage
waveform 3 is produced at the emitter of transistor 2. In order to
maintain the output voltage of the circuit arrangement constant, the
duration of the pulses provided is varied in modulator 5. A pulse
oscillator 6 supplies the pulsatory voltage to modulator 5 and is
synchronized by a signal of line frequency which originates from the
line oscillator 6' present in the picture display device. This line
oscillator 6' is in turn directly synchronized in known manner by
pulses 7' of line frequency which are present in the device and
originate for example from a received television signal if the
picture display device is a television receiver. Pulse oscillator 6
thus generates a pulsatory voltage the repetition frequency of which
is the line frequency.
The
emitter of switching transistor 2 is connected at one end to the
cathode of an efficiency diode 7 whose other end is connected to the
second input voltage terminal and at the other end to primary winding
8 of a transformer 9. Pulsatory voltage 3 which is produced at the
cathode of efficiency diode 7 is clamped against the potential of
said second terminal during the intervals when this diode conducts.
During the other intervals the pulsatory voltage 3 assumes the value
V
i .
A
charge capacitor 10 and a load 11 are arranged between the other end
of winding 8 and the second input voltage terminal. The elements
2,7,8,10 and 11 constitute a so-called chopper producing a direct
voltage across charge capacitor 10, provided that capacitor 10 has a
sufficiently great value for the line frequency and the current
applied to load 11 flowing alternately through switching transistor 2
or through efficiency diode 7. The output voltage V
o
which is the direct voltage produced across charge capacitor 10 is
applied to a comparison circuit 12 which compares the voltage V
o
with a reference voltage. Comparison circuit 12 generates a direct
voltage which is applied to modulator 5 so that the duration of the
effective period δ T of switching transistor 2 relative to the
period T of pulses 3 varies as a function of the variations of
output voltage V
0 . In fact, it is readily evident that output voltage V
o is proportional to the ratio δ :
V
o = V
i . δ
Load 11 of the chopper consists in the consumption of parts of the picture display device which are fed by output voltage V
0 .
In a practical embodiment of the circuit arrangement according to
FIG. 1 wherein the mains alternating voltage has a nominal effective
value of 220 V and the rectified voltage V
i is approximately 270 V, output voltage V
o
for δ = 0.5 is approximately 135 V. This makes it also possible,
for example, to feed a line deflection circuit as is shown in FIG. 1
wherein load 11 then represents different parts which are fed by
the chopper. Since voltage V
o is maintained constant
due to pulse duration modulation, the supply voltage of this line
deflection circuit remains constant with the favorable result that
the line amplitude(= the width of the picture displayed on the
screen of the picture display tube) likewise remains constant as
well as the EHT required for the final anode of the picture display
tube in the same circuit arrangement independent of the variations
in the mains voltage and the load on the EHT generator (= variations
in brightness).
However,
variations in the line amplitude and the EHT may occur as a result
of an insufficiently small internal impedance of the EHT generator.
Compensation means are known for this purpose. A possibility within
the scope of the present invention is to use comparison circuit 12
for this purpose. In fact, if the beam current passes through an
element having a substantially quadratic characteristic, for example,
a voltage-dependent resistor, then a variation for voltage V
o
may be obtained through comparison circuit 12 which variation is
proportional to the root of the variation in the EHT which is a known
condition for the line amplitude to remain constant.
In addition this facilitates smoothing of voltage V
o
since the repetition frequency of pulsatory voltage 3 is many times
higher than that of the mains and a comparatively small value may
be sufficient for charge capacitor 10. If charge capacitor 10 has a
sufficiently high value for the line frequency, voltage V
o
is indeed a direct voltage so that a voltage having the same form
as pulsatory voltage 3 is produced across the terminals of primary
winding 8. Thus voltages which have the same shape as pulsatory
voltage 3 but have a greater or smaller amplitude are produced across
secondary windings 13, 14 of transformer 9 (FIG. 1 shows only 2
secondary windings but there may be more). The invention is based on
the recognition that one end of each secondary winding is connected
to earth while the other end thereof drives a diode, the winding
sense of each winding and the direction of conductance of each diode
being chosen to be such that these diodes conduct during the
same
period as does efficiency diode 7.
After smoothing, stabilized supply voltages, for example, at
terminal 15 are generated in this manner at the amplitudes and
polarities required for the circuit arrangements present in the
picture display device. In FIG. 1 the voltage generated at terminal
15 is, for example, positive relative to earth. It is to be noted
that the load currents of the supply voltages obtained in this
manner cause a reduction of the switching power which is economized
by efficiency diode 7. The sum of all diode currents including that
of diode 7 is in fact equal to the current which would flow through
diode 7 if no secondary winding were wound on transformer 9 and if
no simultaneous diode were used. This reduction may be considered an
additional advantage of the circuit arrangement according to the
invention, for a diode suitable for smaller powers may then be used.
However, it will be evident that the overall secondary load must
not exceed the primary load since otherwise there is the risk of
efficiency diode 7 being blocked so that stabilization of the
secondary supply voltages would be out of the question.
I
t
is to be noted that a parabola voltage of line frequency as shown
at 28 is produced across the charge capacitor 10 if this capacitor
is given a smaller capacitance so that consequently the so-called
S-correction is established.
In FIG. 1 charge
capacitors are arranged between terminals 15 etc. and earth so as to
ensure that the voltages on these points are stabilized direct
voltages. If in addition the mean value of the voltage on one of
these terminals has been made equal to the effective value of the
alternating voltage which is required for heating the filament of
the picture display tube present in the picture display device, this
voltage is suitable for this heating. This is a further advantage
of the invention since the cheap generation of a stabilized filament
voltage for the picture display tube has always been a difficult
problem in transistorized arrangements.
A further
advantage of the picture display device according to the invention is
that transformer 9 can function as a separation transformer so that
the different secondary windings can be separated from the mains
and their lower ends can be connected to ground of the picture
display device. The latter step makes it possible to connect a
different apparatus such as, for example, a magnetic recording
and/or playback apparatus to the picture display device without
earth connection problems occurring.
In
FIG. 1 the reference numeral 14 denotes a secondary winding of
transformer 9 which in accordance with the previously mentioned
recognition of the invention can drive line output transistor 16 of the
line deflection circuit 17. Line deflection circuit 17 which is
shown in a simplified form in FIG. 1 includes inter alia line
deflection coils 18 and an EHT transformer 19 a secondary winding 20
of which serves for generating the EHT required for the acceleration
anode of the picture display tube. Line deflection circuit 17 is
fed by the output voltage V
o of the chopper which
voltage is stabilized due to the pulse duration modulation with all
previously mentioned advantages. Line deflection circuit 17
corresponds, for example, to similar arrangements which have been
described in U.S. Pat. No. 3,504,224 issued Mar. 31, 1970 to J.J.
Reichgelt et al., U.S. patent application Ser. No. 737,009 filed June
14, 1968 by W. H. Hetterscheid and U.S. application Ser. No. 26,497
filed April 8, 1970 by W. Hetterscheid et al. It will be evident
that differently formed lined deflection circuits are alternatively
possible.
It will now be shown that secondary
winding 14 can indeed drive a line deflection circuit so that
switching transistor 2 can function as a driver for the line
deflection. FIGS. 2a and b show the variation as a function of time
of the current i
C which flows in the collector of transistor 16 and of the drive voltage v
14 across the terminals of secondary winding 14. During the flyback period (0, t
1 ) transistor 16 must be fully cut off because a high voltage peak is then produced at its collector; voltage v
14 must then be absolutely negative. During the scan period (t
1 , t
4 ) a sawtooth current i
C
flows through the collector electrode of transistor 16 which
current is first negative and then changes its direction. As the
circuit arrangement is not free from loss, the instant t
3 when current i
C becomes zero lies, as is known, before the middle of the scan period. At the end t
4
of the scan period transistor 16 must be switched off again.
However, since transistor 16 is saturated during the scan period and
since this transistor must be suitable for high voltages and great
powers so that its collector layer is thick, this transistor has a
very great excess of charge carriers in both its base and collector
layers. The removal of these charge carriers takes a period t
s
which is not negligible whereafter the transistor is indeed
switched off. Thus the fraction δ T of the line period T at which v
14 is positive must end at the latest at the instant (t
4 - t
s ) located after the commencement (t = 0) of the previous flyback.
The time δ T may be initiated at any instant t
2 which is located between the end t
1 of the flyback period and the instant t
3 when collector current i
C reverses its direction. It is true that emitter current flows through transistor 16 at the instant t
2 , but collector current i
C is not influenced thereby, at least not when the supply voltage (= V
o )
for line deflection circuit 17 is high enough. All this has been
described in the U.S. Pat. No. 3,504,224. The same applies to line
deflection
circuits
wherein the collector base diode does not function as an efficiency
diode as is the case in the described circuit 17, but wherein an
efficiency diode is arranged between collector and emitter of the
line output transistor. In such a case the negative part of the
current i
C of FIG. 2a represents the current flowing through the said efficiency diode.
After the instant t
3 voltage v
14 must be positive. In other words, the minimum duration of the period T when voltage v
14 must be positive is (t
4 - t
s ) - t
3 whilst the maximum duration thereof is (t
4 - t
s ) - t
1 . In a television system employing 625 lines per raster the line period t
4 is approximately 64 μus and the flyback period is approximately 12 μus. Without losses in the circuit arrangement instant t
3 would be located approximately 26 μus after the instant t
1 ,
and with losses a reasonable value is 22 μus which is 34 μus after
the commencement of the period. If for safety's sake it is assumed
that t
s lasts approximately 10 μus, the extreme values
of δ T are approximately 20 and 42 μus and consequently the values
for δ are approximately 0.31 and 0.66 at a mean value which is equal
to approximately 0.49. It was previously stated that a mean value
of δ = 0.5 was suitable. Line deflection circuit 17 can therefore
indeed be used in combination with the chopper in the manner
described, and the relative variation of δ may be (0.66 - 0.31) :
0.49 = 71.5 percent. This is more than necessary to obviate the
variations in the mains voltage or in the various loads and to
establish the East-West modulation and ripple compensation to be
described hereinafter.
In
fact, if it is assumed that the mains voltage varies between -15
and +10 percent of the nominal value of 220 V, while the 50 Hz
ripple voltage which is superimposed on the input voltage V
i has a peak-to-peak value of 40 V and V
i is nominally 270 V, then the lowest occurring V
i is:
0.85 × 270 V - 20 V = 210 V and the highest occurring V
i is
1.1 × 270 V + 20 V = 320 V. For an output voltage V
o of 135 V the ratio must thus vary between
δ = 135 : 210 = 0.64 and δ = 135 : 320 = 0.42.
A
considerable problem presenting itself is that of the simultaneous
or non-simultaneous drive of line output transistor 16 with
switching transistor 2, it being understood that in case of
simultaneous drive both transistors are simultaneously bottomed,
that is during the period δ T. This depends on the winding sense of
secondary winding 14 relative to that of primary winding 8. In FIG. 1
it has been assumed that the drive takes place simultaneously so
that the voltage present across winding 14 has the shape shown in
FIG. 2b. This voltage assumes the value n(V
i - V
o )
in the period δ T and the value -nVo in the period (1 - δ )T,
wherein n is the ratio of the number of turns on windings 14 and 8
and wherein V
o is maintained constant at nominal mains voltage V
o = δ V
inom .
However, if as a result of an increase or a decrease of the mains voltage V
i increases or decreases proportionally therewith, i.e., V
i = V
i nom + Δ V, the positive portion of V
14 becomes equal to n(V
i nom - V
o +Δ V) = n [(1 -δ)V
i nom +ΔV] = n(0.5 V
inom +ΔV) if δ = 0.5 for V
i = V
i nom. Relatively, this is a variation which is twice as great. For example, if V
i nom = 270 V and V
o = 135 V, a variation in the mains voltage of from -15 to +10 percent causes a variation of V
i
of from -40.5 V to +27 V which ranges from -30 to +20 percent of
135 V which is present across winding 8 during the period δ T. The
result is that transistor 16 can always be bottomed over a large
range of variation. If the signal of FIG. 2b would be applied through
a resistor to the base of transistor 16, the base current thereof
would have to undergo the same variation while the transistor would
already be saturated in case of too low a voltage. In this case it is
assumed that transformer 9 is ideal (without loss) and that coil 21
has a small inductance as is explained in the U.S. patent
application Ser. No. 737,009 above mentioned. It is therefore found
to be desirable to limit the base current of transistor 16.
This
may be effected by providing a coil 22 having a large value
inductance, approximately 100 μH, between winding 14 and the small
coil 21. The variation of said base current i
b is shown
in FIG. 2c but not to the same scale as the collector current of FIG.
2a. During the conducting interval δ T current i
b
varies as a linear function of time having a final value of wherein L
represents the inductance of coil 22. This not only provides the
advantage that this final value is not immediately reached, but it can
be shown that variation of this final value as a function of the
mains voltage has been reduced, for there applies at nominal mains
voltage that: If the mains voltage V
i = V
i nom +Δ V, then ##SPC1## because V
i nom = 2 V
o . Thus this variation is equal to that of the mains voltage and is not twice as great.
During switching off, t
2 ,
of transistor 16 coil 22 must exert no influence and coil 21 must
exert influence which is achieved by arranging a diode 23 parallel to
coil 22. Furthermore the control circuit of transistor 16 in this
example comprises the two diodes 24 and 25 as described in U.S.
application Ser. No. 26,497 above referred to, wherein one of these
diodes, diode 25 in FIG. 1, must be shunted by a resistor.
The
control circuit of transistor 16 may alternatively be formed as is
shown in FIG. 4. In fact, it is known that coil 21 may be replaced
by the parallel arrangement of a diode 21' and a resistor 21" by
which the inverse current can be limited. To separate the path of
the inverse current from that of the forward current the parallel
arrangement of a the diode 29' and a resistor 29" must then be
present. This leads to the circuit arrangement shown in the upper
part of FIG. 4. This circuit arrangement may now be simplified if it
is noted that diodes 25 and 21' on the one hand and diodes 23 and
29' on the other hand are series-arranged. The result is shown in
the lower part of FIG. 4 which, as compared with the circuit
arrangement of FIG. 1, employs one coil less and an additional
resistor.
FIG. 3 shows possible modifications of the
chopper. FIG. 3a shown in a simplified form the circuit arrangement
according to FIG. 1 wherein the pulsatory voltage present across
the connections of windings 8 has a peak-to-peak amplitude of V
i - V
o = 0.5 V
i
for δ = 0.5, As has been stated, the provision of coil 22 gives a
relative variation for the base current of transistor 16 which is
equal to that of the mains voltage. In the cases according to FIG.
3b, 3c and 3d the peak-to-peak amplitude of the voltage across
winding 8 is equal to V
i so that the provision of coil
22 results in a relative variation which is equal to half that of
the mains voltage which is still more favorable than in the first
case.
Transistors
of the npn type are used in FIG. 3. If transistors of the pnp type
are used, the relevant efficiency diodes must of course be reversed.
In this connection it is to be noted that it is possible to obtain an output voltage V
o with the aid of the modifications according to FIGS. 3b, c and d, which voltage is higher than input voltage V
i .
These modifications may be used in countries such as, for example,
the United of America or France where the nominal mains voltage is
117 or 110 V without having to modify the rest of the circuit
arrangement.
The above-mentioned remark regarding the
sum of the diode currents only applies, however, for the
modifications shown in FIGS. 3a and d.
If line
output transistor 16 is not simultaneously driven with switching
transistor 2, efficiency diodes 7 conducts simultaneously with
transistor 16 i.e., during the period which is denoted by δ T in FIGS.
1 and 2b. During that period the output voltage V
o of
the chopper is stabilized so that the base current of transistor 16
is stabilized without further difficulty. However, a considerable
drawback occurs. In FIG. 1 the reference numeral 26 denotes a safety
circuit the purpose of which is to safeguard switching transistor 2
when the current supplied to load 11 and/or line deflection circuit
17 becomes to high, which happens because the chopper stops. After a
given period output voltage V
o is built up again, but
gradually which means that the ratio δ is initially small in the
order of 0.1. All this is described in U.S. patent No. 3,629,686.
The same phenomenon occurs when the display device is switched on.
Since δ = 0.1 corresponds to approximately 6 μs when T = 64 μs,
efficiency diode 7 c
onducts
in that case for 64 - 6 = 58 μus so that transistor 16 is already
switched on at the end of the scan or at a slightly greater ratio δ
during the flyback. This would cause an inadmissibly high
dissipation. For this reason the simultaneous drive is therefore to
be preferred.
The line deflection circuit itself is
also safeguarded: in fact, if something goes wrong in the supply,
the driver voltage of the line deflection circuit drops out because
the switching voltage across the terminals of primary winding 8 is
no longer present so that the deflection stops. This particularly
happens when switching transistor 2 starts to constitute a
short-circuit between emitter and collector with the result that the
supply voltage V
o for the line deflection circuit in the case of FIG. 1 becomes higher, namely equal to V
i .
However, the line output transformer is now cut off and is
therefore also safe as well as the picture display tube and other
parts of the display device which are fed by terminal 15 or the
like. However, this only applies to the circuit arrangement
according to FIG. 1 or 3a.
Pulse
oscillator 6 applies pulses of line frequency to modulator 5. It
may be advantageous to have two line frequency generators as already
described, to wit pulse oscillator 6 and line oscillator 6' which
is present in the picture display device and which is directly
synchronized in known manner by line synchronizing pulses 7'. In
fact, in this case line oscillator 6' applies a signal of great
amplitude and free from interference to pulse oscillator 6. However,
it is alternatively possible to combine pulse oscillator 6 and line
oscillator 6' in one single oscillator 6" (see FIG. 1) which
results in an economy of components. It will be evident that line
oscillator 6' and oscillator 6" may alternatively be synchronized
indirectly, for example, by means of a phase discriminator. It is to
be noted neither pulse oscillator 6, line oscillator 6' and
oscillator 6" nor modulator 5 can be fed by the supply described
since output voltage V
o is still not present when the
mains voltage is switched on. Said circuit arrangements must
therefore be fed directly from the input terminals. If as described
above these circuit arrangements are to be separated from the mains,
a small separation transformer can be used whose primary winding is
connected between the mains voltage terminals and whose secondary
winding is connected to ground at one end and controls a rectifier at
the other end.
Capacitor 27 is arranged parallel to
efficiency diode 7 so as to reduce the dissipation in switching
transistor 2. In fact, if transistor 2 is switched off by the
pulsatory control voltage, its collector current decreases and its
collector-emitter voltage increases simultaneously so that the
dissipated power is not negligible before the collector current has
becomes zero. If efficiency diode 7 is shunted by capacitor 27 the
increase of the collector-emitter voltage is delayed i.e., this
voltage does not assume high values until the collector current has
already been reduced. It is true that in that case the dissipation in
transistor 2 slightly increases when it is switched on by the
pulsatory control voltage but on the other hand since the current
flowing through diode 7 has decreased due to the presence of the
secondary windings, its inverse current is also reduced when transistor
2 is switched on and hence its dissipation has become smaller. In
addition it is advantageous to delay these switching-on and
switching-off periods to a slight extent because the switching pulses
then contain fewer Fourier components of high frequency which may
cause interferences in the picture display device and which may give
rise to visible interferences on the screen of the display tube.
These interferences occupy a fixed position on the displayed image
because the switching frequency is the line frequency which is less
disturbing to the viewer. In a practical ci
rcuit
wherein the line frequency is 15,625 Hz and wherein switching
transistor 2 is an experimental type suitable for a maximum of 350 V
collector-emitter voltage or 1 A collector current and wherein
efficiency diode 7 is of the Philips type BA 148 the capacitance of
capacitor 27 is approximately 680 pF whilst the load is 70 W on the
primary and 20 W on the secondary side of transformer 9. The collector
dissipation upon switching off is 0.3 W (2.5 times smaller than
without capacitor 27) and 0.7 W upon switching on.
As
is known the so-called pincushion distortion is produced in the
picture display tubes having a substantially flat screen and large
deflection angles which are currently used. This distortion is
especially a problem in color television wherein a raster correction
cannot be brought about by magnetic means. The correction of the
so-called East-West pincushion distortion i.e., in the horizontal
direction on the screen of the picture display tube can be
established in an elegant manner with the aid of the circuit
arrangement according to the invention. In fact, if the voltage
generated by comparison circuit 12 and being applied to modulator 5
for duration-modulating pulsatory voltage 3 is modulated by a
parabola voltage 28 of field frequency, pulsatory voltage 3 is also
modulated thereby. If the power consumption of the line deflection
circuit forms part of the load on the output voltage of the chopper,
the signal applied to the line deflection coils is likewise
modulated in the same manner. Conditions therefore are that the
parabola voltage 28 of field frequency has a polarity such that the
envelope of the sawtooth current of line frequency flowing through
the line deflection coils has a maximum in the middle of the scan of
the field period and that charge capacitor 10 has not too small an
impedance for the field frequency. On the other hand the other
supply voltages which are generated by the circuit arrangement
according to the invention and which might be hampered by this
component of field frequency must be smoothed satisfactorily.
A
practical embodiment of the described example with the reference
numerals given provides an output for the supply of approximately 85
percent at a total load of 90 W, the internal resistance for direct
current loads being 1.5 ohms and for pulsatory currents being
approximately 10 ohms. In case of a variation of ± 10 percent of the
mains voltage, output voltage V
o is stable within 0.4 V.
Under the nominal circumstances the collector dissipation of
switching transistor 2 is approximately 2.5 W.
Since
the internal resistance of the supply is so small, it can be used
advantageously, for example, at terminal 15 for supplying a class-B
audio amplifier which forms part of the display device. Such an
amplifier has the known advantages that its dissipation is directly
proportional to the amplitude of the sound to be reproduced and that
its output is higher than that of a class-A amplifier. On the other
hand a class-A amplifier consumes a substantially constant power so
that the internal resistance of the supply voltage source is of
little importance. However, if this source is highly resistive, the
supply voltage is modulated in the case of a class-B amplifier by the
audio information when the sound intensity is great which may
detrimentally influence other parts of the display device. This
drawback is prevented by means of the supply according to the
invention.
The 50 Hz ripple voltage which is superimposed on the rectified input voltage V
i
is compensated by comparison circuit 12 and modulator 5 since this
ripple voltage may be considered to be a variation of input voltage V
i . A further compensation is obtained by applying a
portion of this ripple voltage with suitable polarity to comparison
circuit 12. It is then sufficient to have a lower value for the
smoothing capacitor which forms part of rectifier circuit 1 (see
FIG. 3). The parabola voltage 28 of field frequency originating from
the field time base is applied to the same circuit 12 so as to
correct the East-West pincushion distortion.
The term "power transformer" as used herein refers to a transformer used
in a commercial power supply network for supplying power to the
deflection circuits from a commercial power supply, and should not be
confused with transformers in other portions of the receiver designated
by different terms. Thus, the expression "television receiver of a power
transformerless type" refers to a television receiver which does not
use the defined power transformer.
It is an object of the
invention to provide in conjunction with a transformerless power supply a
transformer coupling means effective to isolate, d.c. wise, deflection
circuits of the receiver from grounded receiver circuit components while
at the same time enabling a.c. coupling between components to be
coupled to one another.
It is another object of the invention to
provide a transformerless power supply and a transformer coupling means
which co-operate to permit operation of the deflection circuits without
need for connecting the deflection circuits to chassis ground for a.c.
by means of a small coupling condenser or otherwise.
It is a
further object of the invention to provide transformerless coupling
means having a turns ratio between the primary and secondary windings
thereof effective to couple in a forward direction a sync signal
amplifier output to the ungrounded horizontal and vertical deflection
circuits while substantially attenuating in the reverse direction
transients and external noise prevalent in the ungrounded deflection
circuits.
INTEGRAL THYRISTOR-RECTIFIER DEVICE TD3F700R34 TD3F800H46
A
semiconductor switching device comprising a silicon controlled
rectifier (SCR) and a diode rectifier integrally connected in parallel
with the SCR in a single semiconductor body. The device is of the NPNP
or PNPN type, having gate, cathode, and anode electrodes. A portion
of each intermediate N and P region makes ohmic contact to the
respective anode or cathode electrode of the SCR. In addition, each
intermediate region includes a highly conductive edge portion. These
portions are spaced from the adjacent external regions by relatively
low conductive portions, and limit the conduction of the diode
rectifier to the periphery of the device. A profile of gold
recombination centers further electrically isolates the central SCR
portion from the peripheral diode portion.
That
class of thyristors known as controlled rectifiers are semiconductor
switches having four semiconducting regions of alternate
conductivity and which employ anode, cathode, and gate electrodes.
These devices are usually fabricated from silicon. In its normal
state, the silicon controlled rectifier (SCR) is non-conductive until
an appropriate voltage or current pulse is applied to the gate
electrode, at which point current flows from the anode to the cathode
and delivers power to a load circuit. If the SCR is reverse biased,
it is non-conductive, and cannot be turned on by a gating signal.
Once conduction starts, the gate loses control and current flows from
the anode to the cathode until it drops below a certain value
(called the holding current), at which point the SCR turns off and
the gate electrode regains control. The SCR is thus a solid state
device capable of performing the circuit function of a thyratron tube
in many electronic applications. In some of these applications, such
as in automobile ignition systems and horizontal deflection circuits
in television receivers, it is necessary to connect a separate
rectifier diode in parallel with the SCR. See, for example, W. Dietz,
U. S. Pat. Nos. 3,452,244 and 3,449,623. In these applications, the
anode of the rectifier diode is connected to the cathode of the SCR,
and the cathode of the rectifier is connected to the SCR anode. Thus,
the rectifier diode will be forward biased and current will flow
through it when the SCR is reverse biased; i.e., when the SCR cathode
is positive with respect to its anode. For reasons of economy and
ease of handling, it would be preferable if the circuit function of
the SCR and the associated diode rectifier could be combined in a
single device, so that instead of requiring two devices and five
electrical connections, one device and three electrical connections
are all that would be necessary. In fact, because of the
semiconductor profile employed, many SCR's of the shorted emitter
variety inherently function as a diode rectifier when reverse biased.
However, the diode rectifier function of such devices is not isolated
from the controlled rectifier portion, thus preventing a rapid
transition from one function to the other. Therefore, it would be
desirable to physically and electrically isolate the diode rectifier
portion from that portion of the device which functions as an SCR.
METZ 7096 CLASSIC COLOR (CH679G) CHASSIS 679G LINE / HORIZONTAL DEFLECTION WITH THYRISTOR SWITCH TECHNOLOGY OVERVIEW./HORIZONTAL ABLENKUNG MIT THYRISTOREN SCHALTUNG.
HOW THYRISTOR LINE DEFLECTION OUTPUT SCAN STAGES WORK:
INTRODUCTION:
The massive demand for colour television receivers in Europe/Germany
in the 70's brought about an influx of sets from the continent. Many of
these use the thin -neck (29mm) type of 110° shadowmask tube and the
Philips 20AX CRT Tube, plus the already Delta Gun CRT .
Scanning
of these tubes is accomplished by means of a toroidally wound
deflection yoke (conventional 90° and thick -neck 110° tubes operate
with
saddle -wound deflection coils). The inductance of a toroidal yoke is
very much less than that of a saddle -wound yoke, thus higher scan currents are required.
The deflection current necessary for the line scan is about 12A peak
-to -peak. This could be provided by a transistor line output stage but a
current step-up transformer, which is bulky and both difficult and
costly to manufacture, would be required.
An entirely different
approach, pioneered by RCA in America and developed by them and by ITT
(SEL) in Germany, is the thyristor line output stage. In this system the
scanning current is provided via two thyristors and two switching diodes
which due to their characteristics can supply the deflection yoke
without a step-up transformer (a small transformer is still required to
obtain the input voltage pulse for the e.h.t. tripler). The purpose of
this article is to explain the basic operation of such circuits. The
thyristor line output circuit offers high reliability since all
switching occurs at zero current level. C.R.T. flashovers, which can
produce high current surges (up to 60A), have no detrimental effects on
the switching diodes or thyristors since the forward voltage drop across
these devices is small and the duration of the current pulses short. If
a surge limiting resistor is pro- vided in the tube's final anode
circuit the peak voltages produced by flashovers seldom exceed the
normal repetitive circuit voltages by more than 50-100V. This is well
within the device ratings.
Brief Basics: LINE Scan output stages operate on the same basic principle whether
the active device used is a valve, transistor or thyristor. As a
starting point, let's remind ourselves of this principle, which was
first developed by Blumlein in 1932. The idea in its simplest form is
shown in Fig. 1. The scan coils, together with a parallel tuning
capacitor, are connected in series with a switch across the h.t. supply.
When the switch is closed - (a) - current flows through the coils,
building up linearly as required to deflect the beam from the centre to
the right-hand side of the screen. At this point the switch is opened.
The coils and the capacitor then form a resonant circuit. The magnetic
fields generated around the coils during the preceeding forward scan as
current flowed through them when the switch was closed now collapse,
charging the capacitor - (b). As a result of the resonant action the
capacitor next discharges, driving current through the coils in the
opposite direction - (c). Once more magnetic fields are generated around
the coils. This resonant action lasts for one half -cycle of
oscillation, during which the beam is rapidly deflected from the right-
hand side to the centre and then to the left-hand side of the screen.
The flyback is thus complete. If the switch is now closed again further
oscillation is prevented and, as the magnetic fields around the coils
collapse, a decaying current flows through them in the direction shown
at (d). This decaying current flow deflects the beam from the left-hand
side of the screen back towards the centre: the period during which this
occurs is often referred to as the energy recovery part of the scanning
cycle. When the current has decayed to zero we are back at the
situation shown at (a): the current through the coils reverses, driving
the beam to the right-hand side of the screen. This is a very efficient
System, since most of the energy drawn from the supply is subsequently
returned to it. There is negligible resistance in the circuit, so there
is very little power loss.
Basic Transistor Circuit:
In
Blumlein's day valves had to be used to perform the switching action.
Two were required since a valve is a unidirectional device, and as we
have seen current must flow through the switch in both directions.
Nowadays we generally use a transistor to perform the switching action,
arranging the circuit along the lines shown in Fig. 2. The line output
transformer T is used as a load for the transistor and as a simple means
of generating the e.h.t. and other supplies required by the receiver.
The scan -correction capacitor Cs also serves as a d.c. block. Capacitor
Ct tunes the coils during the flyback when the transistor is cut off.
During the forward scan Cs first charges, then discharges, via the scan
coils, thus providing deflection from the left- hand side to the
right-hand side of the screen. One advantage of a transistor is that it
can conduct in either direction. Thus unless we are operating the stage
from an 1.t. line of around 11V - as in the case of many small -screen
portables - we don't need a second switching device. With a supply of
11-12V a shunt efficiency diode - connected in parallel with the
transistor, cathode to collector and anode to emitter, is required
because the linearity is otherwise unacceptable. Another advantage of a
transistor compared to a valve is that it is a much more efficient
switch. When a transistor is saturated both its junctions are forward
biased and its collector voltage is then at little more than chassis
potential. The anode voltage of a saturated pentode however is measured
in tens of volts, and this means that there is considerable wasteful
dissipation. Thyristor Switch If what we need is an efficient switch,
why not use a thyristor???
Thyristors
are even more efficient switches than transistors. They are more
rugged, can pass heavy currents, and are insensitive to the voltage
overloads that can kill off transistors. In addition, in the sort of
circuit we are about to lo
ok
at the power supply requirements can be simplified (a line output
transistor must be operated in conjunction with a stabilised power
supply: this is not necessary in the thyristor circuit since regulation
can be built in). In the nature of things however there must be
disadvantages as well - and there are! First, a thyristor will not act
as a bidirectional switch.
There
is no great problem here however: all we need do is to shunt it with a
parallel efficiency diode. More awkward is the fact that once a
thyristor has been triggered on at its gate it cannot be switched off
again by any further action taken in its gate circuit. In fact it's this
problem of operating the thyristor switch that is responsible for the
complexity of thyristor line output circuits.
A
thyristor can be switched off only by reducing the current through it
below the "hold on" value, either by momentarily removing the voltage
across the device or by passing an opposing current through it in the
opposite direction - this latter technique is used in practical
thyristor line output circuits. Once the reverse current through the
thyristor is about equal to the forward current flowing through it the
net current falls below the "hold on" value and the thyristor switches
off.
Basic Thyristor Circuit:
There
is more than one way of arranging a thyristor line output stage. Only
one basic circuit has been used so far however, though as you'd expect
there are differences in detail in the circuits used by different
setmakers. The basic circuit was first devised and put into production
by RCA in the USA in the late 1960s. It was subsequently popularised in
Europe by ITT, and many continental setmakers have used it, mainly in
colour receiver chassis fitted with 110° delta gun c.r.t.s. They include
Finlux, Grundig, Saba, Siemens and ASA. Korting use it in their 55636
chassis which is fitted with a 90° PIL tube, while Grundig continue to
use it in their latest sets which use the Mullard/Philips 20AX tube.
Amongst Japanese setmakers, Sharp use it in their Model C1831H which is fitted with a Toshiba RIS tube.
Reduced
to its barest essentials, the circuit takes the form shown in Fig. 3.
To start with this looks strange indeed! The right-hand side however is
simply the equivalent of the scanning section of the transistor circuit
shown in Fig. 2, with TH2 and D2 replacing the transistor as the
bidirectional switch.
The
tuning capacitor however is returned to chassis via the left-hand side
of the circuit - in consequence there is no d.c. path between the
right-hand and left-hand sides of the circuit. L1 provides a load. The
efficiency diode D2 conducts during the first part of the forward scan,
after which TH2 is switched on to drive the beam towards the right-hand
side of the screen. The purpose of the left-hand side of the circuit,
the bidirectional switch TH1/D1 and L2, together with the tuning
capacitor Ct, is to switch TH2 off and to provide the flyback action.
The
output from the line oscillator consists of a brief pulse to initiate
the flyback. It occurs just before the flyback time (roughly 3µS before)
and is applied to the gate of TH1, switching it on. When this happens
L2 is connected to chassis and current flows into it, discharging Ct
(previously charged from the h.t. line). L2 is called the commutating
coil, and forms a resonant circuit with Ct. Thus when TH1 is switched on
a sudden pulse builds up and this is used to switch off TH2. In
addition to tuning L2, Ct tunes the scan coils to provide the usual
flyback action.
Roughly
speaking therefore D2 and TH2 conduct alternately during the forward
scan and are cut off during the flyback, while TH1 is triggered on just
before the flyback, TH1 and D I subsequently conducting alternately
during the flyback and then cutting off when the efficiency diode takes
over.
Thyristor Line Scan Practical Circuit:
A
more practical arrangement is shown in Fig. 4. A secondary winding L3
is added to Ll to provide the trigger pulse for TH2: L4, C4 and R I
provide the pulse shaping required. The tuning capacitor Ct is
rearranged as a T network: this is done to reduce the voltage across the
individual capacitors and enable smaller values to be used, all in the
interests of economy. And finally a transformer is coupled to the
circuit by C5 to make use of the flyback pulse for e.h.t. generation and
to provide other supplies. In many recent chassis THUD 1 and TH2/D2 are
encapsu- lated together, in pairs. In practical circuits L1 and L2
generally consist of a single transformer - often a transductor is used,
for convenience rather than for the transductor characteristics. This
makes practical circuits look at first glance rather different to the
basic form shown in Figs. 3 and 4. A further winding is often added to
the transformer to provide a supply for other parts of the receiver,
making the circuit look even more confusing. In addition e.h.t.
regulation, pincushion distortion correction and beam limiting circuitry
is required, and protection circuits may be incorporated.
Scanning Sequence:
It's time to look at the basic scanning sequence in more detail, basing
the description on Figs. 3 and 4. We'll start at the beginning of the
flyback. TH2 and D2 have just been switched off - we'll come to how this
is done later - while TH1 which was triggered on by a pulse from the
line oscillator is still conducting. Energy is stored in the scan coils
in the form of magnetic fields. As these collapse, a decaying current
flows via the coils, Cs, Ct, L2 and TH 1. When this current falls to
zero the charge on Ct will have reversed and TH 1 will switch off. This
completes the first half of the flyback. The left-hand plate of Ct is
charged negatively, while its right-hand plate carries a positive
charge. D1 is now biased on and Ct discharges back into the scan coils
to give the second half of the flyback. Current is flowing via D1, L2,
Ct, Cs and the scan coils. At the end of this period the circuit energy
will have been transferred once again to the scan coils - in the form of
magnetic fields. One complete half cycle of oscillation will have
occurred, returning the beam to the left-hand side of the screen. With
Ct discharged, D 1 switches off. The oscillation tries to continue in
the negative direction, but we then get the normal efficiency diode
action, i.e. D2 conducts shorting out the tuned circuit. As the fields
around the coils collapse a linearly decaying current flows via the
coils, Cs and D2. This gives us the first part of the forward scan.
Towards the centre of the screen TH2 is switched on by the pulse
obtained from L3 and the current in the scan coils reverses to complete
the scan.
Switching the Scan Thyristor Off: The
tricky part is when it comes to switching TH2 off. As we have seen, TH1
is triggered on about 3fitS before the end of the forward scan. Prior
to this Ct will have been charged to the h.t. potential via L 1 and L2.
When TH1 conducts, current flows via TH1, L2, Ct and TH2 (which is on
remember). Because of the tuned circuit formed by L2 and Ct, the current
builds up rapidly in the form of a pulse - the commutating pulse shown
in Fig. 5. When this current, which flows through TH2 in the opposite
direction to the scan current, exceeds the scan current TH2 switches
off. Once TH2 cuts off D2 is able to conduct - it is no longer reverse
biased - which it does for a short period to provide an earth return
path for the remaining duration of the commutating pulse and also to
enable the scan to be completed (Cs discharging via the scan coils).
When the reverse, commutating current falls below the scan current D2
switches off and we then get the flyback action as the magnetic fields
around the coils collapse.
Power Transferring ; during the forward scan Ct is charged via L1 and L2, its right-hand plate being held at little above
through
the conduction of D2 and then TH2. During the flyback, when TH1 and D1
conduct alternately, connecting the junction L1, L2 to chassis, Ct
supplies energy to the scan part of the circuit. The Practical Circuit
so much then for the basic circuit and its action. Turning now to a
practical circuit, Fig. 6 shows the thyristor line output stage used in
the Grundig SuperColor Models 5011 and 6011. Ty511/Di511 form the
flyback switch, T1 is the input/commutating transformer, C516/7/8
comprise the tuning capacitance, Di518 is the efficiency diode and Ty518
the forward scan thyristor. The scan -correction capacitor Cs is C537.
As can be seen, the line output transformer circuit is quite
conventional. The main complication arises because of the need to
provide width/e.h.t. stabilisation. In a valve line output stage it is a
simple matter to achieve stabilisation by using a v.d.r. in a feedback
circuit to alter the bias on the output pentode. We can't do this with a
transistor line output stage, so we have to operate this in conjunction
with a stabilised supply. There is a subtle but quite simple method of
applying stabilisation to a thyristor line output stage however. As we
have seen, the energy supplied to the output side of the circuit is
provided by the tuning capacitors when they discharge during the flyback
period. During the forward scan they charge via the input coil - or
transformer as it is in practice. Now if we shunt the transformer's
input winding with a transductor we can control the inductance in series
with the tuning capacitors and in consequence the charging time of the
capacitors and hence the power supplied to the output side of the
circuit.
EHT/Width Stabilisation:
The
stabilising transductor in Fig. 6 is Td 1, whose load windings are
connected in series with R504/Di504 across the input winding of T1. The
transductor's control winding is driven by transistor Tr506, which
senses the h.t. voltage (via R506) and the amplitude of the signal at
tag d on the line output transformer. R508 in the transistor's base
circuit enables the e.h.t. to be set to the correct voltage (25kV).
Other Circuit Details:
A fourth winding on Ti feeds the 1.t. rectifier and stabiliser which
provide the supply for the low -power circuits in the receiver. The
trigger pulse winding also feeds a stabilised 1.t. supply circuit
(21V).
EW
pincushion distortion correction is applied by connecting the load
windings of a second transductor (Td2) across a section of the line
output
transformer's primary winding. By feeding a field frequency waveform to
the control winding on this transductor the line scanning is modulated
at field frequency. There is a simple but effective safety circuit in
this Grundig line output stage. If the voltage at tag c on the line
output transformer rises above 68V zener diode Di514 conducts,
triggering thyristor Ty511 into conduction with the result that the
cut-out operates. C517 is returned to chassis via a damped coil (L517)
so that the voltage transient when the efficiency diode cuts off is
attenuated. Likewise L512/C512/R512 are added to suppress the voltage
transient when the flyback thyristor Ty511 cuts off. The balancing coil
L516 is included to remove unwanted voltage spikes produced by the
thyristors.
At
the end........This Grundig circuit is representative of the way in
which thyristor line output circuits are used in practice. There are
differences in detail in the thyristor line output stages found in other
setmakers' chassis, but the basic arrangement will be found to be
substantially
Servicing / Throubleshooting / Repairing Thyristor Line Scan Timebases Crt Deflections circuits:
LARGELY
due to advances in colour c.r.t. scan coil design, the thyristor line
output stage has become obsolete laready in the 1981's.
It
was a very good system to use where the line scan coils require large
peak currents with only a moderate flyback voltage - an intrinsic
characteristic of toroidally wound deflection coils.
it was originally devised by RCA. Many sets fitted with
110°, narrow -neck delta -gun tubes used a thyristor line output stage -
for example those in the Grundig and Saba ranges and the Finlux Peacock
, Indesit, Siemens, Salora, Metz, Nordmende, Blaupunkt, ITT, Seleco,
REX, Mivar, Emerson, Brionvega, Loewe, Galaxi, Stern, Zanussi, Wega,
Philco. The circuit continued to find favour in earlier chassis designed
for use with in -line gun tubes, examples being found in the Grundig
and Korting ranges - also, Indesit, Siemens, Salora, Metz, Nordmende,
Blaupunkt, ITT, Seleco, REX, Mivar, Emerson, Brionvega, Loewe, Galaxi,
Stern, Zanussi, Wega, Philco the Rediffusion Mk. III chassis. Deflection
currents of up to 13A peak -to -peak are commonly encountered with 110°
tubes, with a flyback voltage of only some 600V peak to peak. The
total energy requirement is of the order of 6mJ, which is 50 per cent
higher than modern 110° tubes of the 30AX and S4 variety with their
saddle -wound line scan coils. The only problem with this type of
circuit is the large amount of energy that shuttles back and forth at
line frequency. This places a heavy stress on certain components.
Circuit losses produce quite high temperatures, which are concentrated
at certain points, in particular the commutating combi coil. This leads
to deterioration of the soldered joints around the coil, a common cause
of failure. This can have
a cumulative effect, a high resistance joint increasing the local
heating until the joint becomes well and truly dry -a classic symptom
with some Grundig / Emerson sets. The wound components themselves can be
a source of trouble, due to losses - particularly the combi coil and
the regulating transductor. Later chassis are less prone to this sort of
thing, partly because of the use of later generation, higher efficiency
yokes but mainly due to more generous and better design of the wound
components. The ideal dielectric for use in the tuning capacitors is
polypropylene (either metalised or film). It's a truly won- derful
dielectric - very stable, with very small losses, and capable of
operation at high frequencies and elevated temperatures. It's also
nowadays reasonably inexpensive. Unfortunately many earlier chassis of
thi
s type used polyester capacitors, and it's no surprise that they were
inclined to give up. When replacing the tuning capacitors in a
thyristor line output stage it's essential to use polypropylene types -a
good range of axial components with values ranging from 0.001µF to
047µF is available from RS Components, enabling even non-standard values
to be made up from an appropriate combination. Using polypropylene
capacitors in place of polyester ones will not only ensure capacitor
reliability but will also lower the stress on other components by
reducing the circuit losses (and hence power consumption).
Numerous circuit designs for completely transistorized television
receivers either have been incorporated in commercially available
receivers or have been described in detail in various technical
publications. One of the most troublesome areas in such transistor
receivers, from the point of View of reliability and economy, lies in
the horizontal deflection circuits.
As an attempt to avoid the voltage and current limitations of transistor
deflection circuits, a number of circuits have been proposed utilizing
the silicon controlled rectifier (SCR), a semiconductor device capable
of handling substantially higher currents and voltages than transistors.
The circuit utilizes two bi-directionally conductive switching means
which serve respectively as trace and commutating switches.
Particularly, each of the switching means comprises the parallel
combination of a silicon controlled rectifier (SCR) and a diode. The
commutating switch is triggered on shortly before the desired beginning
of retrace and, in conjunction with a resonant commutating circuit
having an inductor and two capacitors, serves to turn off the trace
switch to initiate retrace. The commutating circuit is also arranged to
turn oft the commutating SCR before the end of retrace.
Circuit Operation:
The
basic thyristor line output stage arrangement used in all these chassis
is shown in Fig. 1 - it was originally devised by RCA. The part to th
e
right of the tuning capacitance acts in exactly the same manner as a
transis- tor line output stage, with the scan thyristor Th2 replacing
the transistor. The thyristor is switched on about half way through the
forward scan, the efficiency diode D2 provid- ing the initial part of
the line scan (left-hand side of the screen). The scan coils and line
output transformer (used to generate the e.h.t. plus various other
supply lines and pulse waveforms as required) are a.c. coupled, via the
scan -correction capacitor C5 and C6 respectively. The problem with a
thyristor is that it can be turned on at its gate but not off. To switch
a thyristor off, the current flowing through it must be reduced below a
value known as the hold -on current. This is the main function of the
components on the left-hand side - the line generator, the flyback
thyristor with its parallel diode and the commutat- ing coil. During the
forward scan, the tuning capacitors are charged from the h.t. line via
the input and commutat- ing coils. The line generator produces a pulse
to trigger the flyback thyristor Th1- this occurs just before the actual
flyback. When Thl1 switches on, the junction of the input coil and the
commutating coil is momentarily con- nected to chassis. The tuning
capacitance and the com- mutating coil then resonate, producing a pulse
which draws current via the scan thyristor. Since this current flow is
in the opposite direction to the scan current flow, the two cancel and
the current flowing via the scan thyris- tor falls below the hold -on
current. Th2 is thus switched off, and the scan coils resonate with the
tuning capaci- tance to provide the flyback action. So much for the
basic action. A secondary winding coupled to the input coil produces a
pulse to switch the scan thyristor on, in conjunction with the
shaping/delay network Ll, C4, R1. The tuning capacitors are usually
arranged in the T formation shown to reduce the values required and the
voltages developed across them. In
practical circuits the input
and commutating coils are usually combined in a single unit which for
obvious reasons is generally known as the combi coil. The main point not
so far mentioned is stabilisation. There are two approaches to this. In
earlier circuits a transductor was included in parallel with the
input
coil to vary the impe- dance in series with the tuning capacitance.
This was driven by a transistor which was in turn controlled by feedback
from the line output transformer. A more efficient technique is used in
later circuits, with a current dumping thyristor in series with the
input coil. Practical Circuit As a typical example of the earlier type
of circuit, Fig. 2 shows the thyristor line output stage used in the
Grundig 5010/5011/6010/6011 series. Td1 is the regulating transductor
which is driven by Tr506. Ty511 is the flyback thyristor (commutating
thyristor might be a better name), Ty518 the scan thyristor, Di518 the
efficiency diode and C516/7/8 the tuning capacitance. The scan coils are
cou- pled via C537, while C532 provides coupling between the primary
winding of the line output transformer and chas- sis. A transductor
(Td2) is used for EW raster correction. The combi coil also feeds 1.t.
rectifiers from its secondary windings.
Component Problems: The only problem with this type of circuit is the
large amount of energy that shuttles back and forth at line frequency.
This places a heavy stress on certain components. Circuit losses
produce quite high temperatures, which are concentrated at certain
points, in particular the combi coil. This leads to deterioration of the
soldered joints around the coil, a common cause of failure. This can
have a cumulative effect, a high -resistance joint increasing the local
heating until the joint becomes well and truly dry -a classic symptom
with some Grundig sets. The wound components themselves can be a source
of trouble, due to losses - particularly the combi coil and the
regulating transductor. Later chassis are less prone to this sort of
thing, partly because of the use of later generation, higher efficiency
yokes but mainly due to more generous and better design of the wound
components. The ideal dielectric for use in the tuning capacitors is
polypropylene (either metalised or film). It's a truly won- derful
dielectric - very stable, with very small losses, and capable of
operation at high frequencies and elevated temperatures. It's also
nowadays reasonably inexpensive. Unfortunately many earlier chassis of
this type used polyester capacitors, and it's no surprise that they were
inclined to give up. When replacing the tuning capacitors in a
thyristor line output stage it's essential to use poly- propylene types
-a good range of axial components with values ranging from 0.001µF to
047µF is available from RS Components, enabling even non-standard values
to be made up from an appropriate combination. Using polypropylene
capacitors in place of polyester ones will not only ensure capacitor
reliability but will
also
lower the stress on other components by reducing the circuit losses
(and hence power consumption). The thyristors are also liable to fail,
as are their parallel diodes. Earlier devices were less reliable than
their successors. Since all thyristor line output stages operate in the
same way and under similar conditions, the use of later types of
thyristors and diodes in earlier circuits is a matter of mechanical
rather than electrical con- siderations. One important point should be
noted: the scan thyristor is a faster device and often has a higher
voltage rating than the flyback thyristor. The simplest course is to
keep in stock some of the later scan thyristors that incorporate an
efficiency diode - suitable types are the RCA S3900SF and the Telefunken
TD3-800H. The Telefunken device is in a TO66 package (and can be
obtained quite cheaply) while the RCA type is in a TO220 package. Either
type can be used in the scan or flyback positions and can also be used
as a replacement for the regulating thyristor used in later designs
instead of a transductor. Whenever replacing a thyristor in the line
output stage it's good practice to replace the parallel diode at the
same time. Using one of the above recom- mended devices will do this
automatically, since the thyristor and its parallel diode share the same
encapsulation - always remember to remove the old diode when this is a
separate device however, as some can exhibit high -voltage
leakage/breakdown which is not evident from a quite check with the Avo.
Apart from the wound components (including the line output transformer),
the thyristors and their parallel diodes and the tuning capacitors
several other com- ponents are prone to failure. These include the
tripler, scan/flyback rectifier diodes used to provide various supply
lines, surge limiting resistors, the scan coil coup- ling/scan
correction capacitor (replace with a metalised polypropylene type) and
regulator components such as the thyristor in later types and the
transductor driver transistor in earlier circuits.
Basic Fault Conditions: At
one time every engineer must have scratched his head and cursed the
new-fangled idea of the thyristor line output stage. That they are
awkward to service is a fallacy however. The usual symptom of a fault in
the line output stage is the cutout tripping. All chassis that use a
thyristor line timebase incorporate a trip of some sort. The type varies
from chassis to chassis. Early Grundig sets have a mechanical cutout;
the Saba H chassis uses a thyristor and solenoid to open the mains
on/off switch; a common arrangement consists of a thyristor in series
with the h.t, line and a control transistor which shorts the thyristor's
gate and cathode in the event of excessive current demand (this gives
audible tripping at about 2Hz). Some sets incorporate both excess
current and over -voltage trips, but most have just the former.
There
are two basic fault conditions: when the excess current trip is
activated and the set goes dead, or no e.h.t. with the trip not
activated. The first condition is usually due to a line timebase fault,
the most common being a short-circuit flyback thyristor or its parallel
diode. A straightforward resistance check will sort this out. If this is
not the case, short-circuit the scan thyristor by soldering a wire link
between its anode and cathode. This will prevent any drive to the scan
coils and the line output transformer. If the tripping stops, the fault
could be due to the tripler, the line output transformer, a rectifier
diode fed from a winding on the latter or a short in a circuit supplied
by a scan rectifier diode. If the trip continues to operate and the
flyback thyristor/diode is not the culprit, the most likely causes are
incorrect drive to this thyristor - if possible check with a scope
against the waveform given in the manual - or a rectifier diode fed from
the combi coil. As an example of the latter, Fig. 3 shows the
arrangement used in the Finlux Peacock: the electronic trip will operate
if either D503 or D504 goes short-circuit, a fairly common fault on
these sets. The diodes can also go open-circuit/high resistance to give
the no sound with field collapse symp- tom, but that's another story (
referring to the diodes as D603/4 ). When the set is dead, h.t. is
present and the trip is not activated, suspect the following: the scan
thyristor, the efficiency diode, the line output transformer, the scan -
correction capacitor, or lack of drive to the scan thyristor. Dry
-joints can be the cause of any of these basic fault conditions,
depending on the actual circuit and where the dry -joint has occurred.
Other Symptoms: Hairline
cracks in the ferrite core of a wound com- ponent can give rise to
strange symptoms since this upsets the delicate balance of the tuning
arrangements. There will usually be excessive current which will
probably cause the trip to operate. Alternatively the fault may be
incorrect line frequency which cannot be set by the line hold control.
This fault can also give rise to excessive e.h.t., which can in turn
produce a chain reaction of des- truction, e.g. the tripler is a common
victim as are the two line output stage thyristors. Excessive e.h.t.
leading to instant destruction of these components may also be due to
open -circuit line scan coils or the connections to them. A quick
resistance check done on the board itself will eliminate both the coils
and the leads/connectors. Excessive e.h.t. with foldover in the centre
of the screen and cooking in the tube's first anode supply net- work
occurs in the Grundig 5010 series when L515 in the scan thyristor's
trigger circuit (see Fig. 2) goes short- circuit. The reason for this
situation is that the thyristor is triggered on early. Another common
fault in these sets is failure of Di504/R504 - failure of one seems to
affect the other, so both should be replaced.
The usual symptom is fuzzy verticals and a sawtooth effect on
diagonals. The trip may operate, possibly after period of operation.
These components set up the transductor's operating bias. Linearity
problems are usually caused by the regulator circuit, which can also be
responsible for line "hunting". In the event of lack of width in the
earlier type of circuit, check for dry -joints in the regulator circuit
and suspect the control transistor. Foldover on the left-hand side of
the screen can be caused by an open -circuit flyback diode. Foldover at
the centre of the screen with greatly reduced width is the symptom when
the efficiency diode goes open -circuit - the trip may or may not
operate. Unusual interference patterns on the screen, best viewed with
the contrast control turned to minimum and the brightness control
advanced until a distinctly visible but not over bright white raster is
obtained, can be due to the tripler if there's curved patterning on the
extreme left- hand side of the screen, the regulator clamp diode (Di505
in Fig. 2) if there's curved interference just to the left of centre, or
the flyback thyristor drive circuit if there's a single vertical line
of patterning about four fifths of the way to the right of the screen.
The aim
of this article has been to provide a general guide to servicing rather
than to list faults common to particular models. Much useful
information on individual
chassis with thyristor line output stages has appeared in previous issues of
Obsolete Technology Tellye !- refer to the following as required:
Search with the tag Thyristors at the bottom of the post to select all
posts with this argument on various fabricants.
Horizontal deflection circuit
(Thyristor Horizontalsteuerung)
Description:
1.
A horizontal deflection circuit for generating the deflection
current in the deflection coil of a television picture tube wher
ein
a first switch controls the horizontal sweep, and wherein a second
switch in a so-called commutation circuit with a commutating inductor
and a commutating capacitor opens the first switch and, in addition,
controls the energy transfer from a dc voltage source to an input
inductor, characterized in that the input inductor (Le) and the
commutating inductor (Lk) are combined in a unit designed as a
transformer (U) which is proportioned so that the open-circuit
inductance of the transformer is essentially equal to the value of the
input inductor (Le), while the short-circuit inductance of the
transformer (U) is essentially equal to the value of the commutating
inductor (Lk), and that the second switch (S2) is connected in series
with the dc voltage source (UB) and a first winding (U1) of the
transformer (U). 2. A horizontal deflection circuit according to claim
1, characterized in that the transformer (U) operates as an isolation
transformer between the supply (UB) and the subcircuits connected to a
second winding. 3. A horizontal deflection circuit according to
claim 1, characterized in that the second switch (S2) is connected
between ground and that terminal of the first winding (U1) of the
transformer (U) not connected to the supply potential (+UB). 4. A
horizontal deflection circuit according to claim 1, characterized in
that a capacitor (CE) is connected across the series combination of
the first winding (U1) of the transformer and the second switch (S2).
5. A horizontal deflection circuit according to claim 1,
characterized in that the second winding (U2) of the transformer (U)
is connected in series with a first switch (S1), the commutating
capacitor (Ck), and a third, bipolar switch (S3) controllable as a
function of the value of a controlled variable developed in the
deflection circuit. 6. A horizontal deflection circuit according to
claim 5, characterized in that the third switch (S3) is connected
between ground and the second winding (U2) of the transformer. 7. A
horizontal deflection circuit according to claim 2, characterized in
that the isolation transformer carries a third winding via which
power is supplied to the audio output stage of the television set. 8.
A horizontal deflection circuit according to claims 2, characterized
in that the voltage serving to control the first switch (S1) is
derived from a third winding of the transformer.
Description:
The
present invention relates to a horizontal deflection circuit for
generating the deflection current in the deflection coil of a television
picture tube wherein a first switch controls the horizontal sweep,
and wherein a second switch in a so-called commutation circuit with a
commutating inductor and a commutating capacitor opens the first
switch and, in addition, controls the energy transfer from a dc
voltage source to an input inductor.
German Aus
legeschrift
(DT-AS) No. 1,537,308 discloses a horizontal deflection circuit in
which, for generating a periodic sawtooth current within the
respective deflection coil of the picture tube, in a first branch
circuit, the deflection coil is connected to a sufficiently large
capacitor serving as a current source via a first controlled,
bilaterally conductive switch which is formed by a controlled
rectifier and a diode connected in inverse parallel. The control
electrode of the rectifier is connected to a drive pulse source which
renders the switch conductive during part of the sawtooth trace
period. In that arrangement, the sawtooth retrace, i.e. the current
reversal, also referred to as "commutation", is initiated by a second
controlled switch.
The
first controlled switch also forms part of a seco
nd branch circuit
where it is connected in series with a second current source and a
reactance capable of oscillating. When the first switch is closed, the
reactance, consisting essentially of a coil and a capacitor,
receives energy from the second current source during a fixed time
interval. This energy which is taken from the second current source
corresponds to the circuit losses caused during the previous
deflection cycle.
As can
be seen, such a circuit needs two different, separate inductive
elements, it being known that inductive elements are expensive to
manufacture and always have a certain volume determined by the
electrical properties required.
The object of the invention is to reduce the amount of inductive elements required.
The
invention is characterized in that the input inductor and the
commutating inductor are combined in a unit designed as a transformer
which is proportioned so that the open-circuit inductance of the
transformer is essentially equal to the value of the input inductor,
while the short-circuit inductance of the transformer is essentially
equal to the value of the commutating inductor, and that the second
switch is connected in series with the dc voltage source and a first
winding of the transformer.
This
solution has an added advantage in that, in mass production, both
the open-circuit and the short-circuit inductance are reproducible
with reliability.
According
to another feature of the invention, the electrical isolation
between the windings of the transformer is such that the transformer
operates as an isolation transformer between the supply and the
subcircuits connected to a second winding or to additional windings
of the transformer. In this manner, the transformer additionally
provides reliable mains isolation.
According
to a further feature of the invention, the second switch is
connected between ground and that terminal of the first winding of
the transformer not connected to the supply potential. This
simplifies the control of the switch.
According to a further feature of the invention, to regulate the energy supply, the second winding of the transf
ormer
is connected in series with the first switch, the commutating
capacitor, and a third, bipolar switch controllable as a function of the
value of a controlled variable developed in the deflection circuit.
The
advantage gained by this measure lies in the fact that the control
takes place on the side separated from the mains, so no separate
isolation device is required for the gating of the third switch. Further
details and advantages will be apparent from the following
description of the accompanying drawings and from the claims. In the
drawings,
FIG. 1 is a basic circuit diagram of the arrangement disclosed in German Auslegeschrift (DT-AS) No. 1,537,308;
FIG. 2 shows a first embodiment of the horizontal deflection circuit according to the invention, and
FIG. 3 shows a development of the horizontal deflection circuit according to the invention.
FIG.
1 shows the essential circuit elements of the horizontal deflection
circuit known from the German Auslegeschrift (DT-AS) No. 1,537,308
referred to by way of introduction.
Connected
in series with a dc voltage source UB is an input inductor Le and a
bipolar, controlled switch S2. In the following, this switch will be
referred to as the "second switch"; it is usually called the
"commutating switch" to indicate its function.
In known circuits, the second switch S2 consists of a controlled rectifier and a diode connected in inverse parallel.
The second switch S
2
also forms part of a second circuit which contains, in addition, a
commutating inductor Lk, a commutating capacitor Ck, and a first
switch S1. The first switch S1, controlling the horizontal sweep, is
constructed in the same manner as the above-described second switch
S2, consisting of a controlled rectifier and a diode in inverse
parallel. Connected in parallel with this first switch is a
deflection-coil arrangement AS with a capacitor CA as well as a high
voltage generating arrangement (not shown). In FIGS. 1, 2, and 3,
this arrangement is only indicated by an arrow and by the reference
characters Hsp. The operation of this known horizontal deflection
circuit need not be explained here in detail since it is described
not only in the German Auslegeschrift referred to by way of
introduction, but also in many other publications.
FIGS.
2 and 3 show the horizontal deflection circuit modified in
accordance with the present invention. Like circuit elements are
designated by the same reference characters as in FIG. 1.
FIG.
2 shows the basic principle of the invention. The two inductors Le
and Lk of FIG. 1 have been replaced by a transformer U. To be able to
serve as a substitute for the two inductors Le and Lk, the
transformer must be proportioned in
a special manner. Regardless of
the turns ratio, the open-circuit inductance of the transformer is
chosen to be essentially equal to the value of the input inductor Le,
and the short-circuit inductance of the transformer is essentially
equal to the value of the commutating inductor Lk.
To
permit the second switch S2 to be utilized for the connection of the
dc voltage source UB, it is included in the circuit of that winding
U1 of the transformer connected to the dc voltage UB.
In
principle, it is of no consequence for the operation of the switch
S2 whether it is inserted on that side of the winding U1 connected to
the positive operating potential +UB or on the side connected to
ground. In practice, however, the solution shown in FIGS. 2 and 3 will
be chosen since the gating of the controlled rectifier is less
problematic in this case.
In
compliance with pertinent safety regulations, the transformer U may
be designed as an isolation transformer and can thus provide mains
separation, which is necessary for various reasons. It is known from
German Offenlegungschrift (DT-OS) No. 2,233,249 to provide dc
isolation by designing the commutating inductor as a transformer, but
this measure is not suited to attaining the object of the present
invention.
If the energy
to be taken from the dc voltage source is to be controlled as a
function of the energy needed in the horizontal deflection circuit
and in following subcircuits, the embodiment of the horizontal
deflection circuit of FIG. 3 may be used.
The
circuit including the winding U2 of the transformer U contains a
third controlled switch S3, which, too, is inserted on the grounded
side of the winding U2 for the reasons mentioned above. This third
switch S3, just as the second switch S2, is operated at the frequency
of a horizontal oscillator HO, but a control circuit RS whose input l
is fed with a controlled variable is inserted between the oscillator
and the switch S3. Depending on this controlled variable, the
controlled rectifier of the third switch S3 can be caused to turn on
earlier. A suitable controlled variable containing information on the
energy consumption is, for example, the flyback pulse capable of
being taken from the high voltage generating circuit (not shown).
Details of the operation of this kind of energy control are described
in applicant's German Offenlegungsschrift (DT-OS) No. b 2,253,386
and do not form part of the present invention.
With
mains isolation, the additional, third switch S3 shown here has the
advantage of being on the side isolated from the mains and eliminates
the need for an isolation device in the control lead of the
controlled rectifier.
As
an isolation transformer, the transformer U may also carry additional
windings U3 and U4 if power is to be supplied to the audio output
stage, for example; in addition, the first switch S1 may be gated via
such an additional winding.
The
points marked at the windings U1 and U2 indicate the phase
relationship between the respective voltages. Connected in parallel
with the winding U1 and the second switch S2 is a capacitor CE which
completes the circuit for the horizontal-frequency alternating
current; this serves in particular to bypass the dc voltage source or
the electrolytic capacitors contained therein.
If
required, a well-known tuning coil may be inserted, e.g. in series
with the second winding U2, without changing the basic operation of
the horizontal deflection circuit according to the invention.
METZ 7096 CLASSIC COLOR (CH679G) CHASSIS 679G Electron beam deflection circuit including thyristors Further Discussion and deepening of knowledge, Thyristor horizontal output circuits: (ZEILEN ABLENKUNG MIT THYRISTOR SCHALTUNG)
1.
An electron beam deflection circuit for a cathode ray tube with
electromagnetic deflection by means of a sawtooth current waveform
having a trace portion and a retrace portion, said circuit comprising: a
deflection winding; a first source of electrical energy formed by a
first capacitor; first controllable switching means comprising a
parallel combination of a first thyristor and a first diode connected
together to conduct in opposite directions, for connecting said winding
to said first source during said trace portion, while said first
switching means is turned on; a second source of electrical energy
including a first inductive energy storage means coupled to a voltage
supply; reactive circuit means including a combination of inductive and
capacitive reactances for storing the energy supplied by said second
source; second controllable switching means, substantially similar
to said first one, for completing a circuit including said reactive
circuit means and said first switching means, when turned on before
the end of said trace portion, so as to pass through said first
switching means an oscillatory current in opposite direction to that
which passes through said first thyristor from said first source and
to turn said first thyristor off after these two currents cancel out,
the oscillatory current flowing thereafter through said first diode
for an interval termed the circuit turn-off time, which has to be
greater than the turn-off time of said first thyristor; wherein the
improvement comprises: means for drawing, during at least a part of
said trace portion, a substantial amount of additional current through
said first switching means, in the direction of conduction of said
first diode, whereby to perceptibly shift the waveform of the current
flowing through said first switching means towards the negative
values by an amount equal to that of said substantial additional
current and to lengthen, in proportion thereto, said circuit turn-off
time, without altering the values of the reactances in the reactive
circuit which intervene in the determination of both the circuit
turn-off and retrace portion time intervals.
2.
A deflection circuit as claimed in claim 1, wherein said amount of
additional current is greater than or equal to 5 per cent of the
peak-to-peak value of the current flowing through the deflection
winding.
3. A deflection circuit as claimed in claim 1,
wherein said means for drawing a substantial amount of additional
current through said first switching means comprises a resistor
connected in parallel to said first capacitor.
4. A
deflection circuit as claimed in claim 1, wherein said means for
drawing an additional current is formed by connecting said first and
second energy sources in series so that the current charging said
reactive circuit means forms the said additional current.
5.
A deflection circuit as claimed in claim 1, further including a
series combination of an autotransformer winding and a second
high-value capacitor, said combination being connected in parallel to
said first switching means, wherein said autotransformer comprises
an intermediate tap located between its terminals respectively
connected to said first switching means and to said second capacitor,
said tap delivering, during said trace portion, a suitable DC supply
voltage lower than the voltage across said second capacitor; and
wherein said means for drawing a substantial amount of additional
current comprises a load to be fed by said supply voltage and having
one terminal connected to ground; and further controllable switching
means controlled to conduct during at least part of said trace
portion and to remain cut off during said retrace portion, said
further switching means being connected between said tap and the other
terminal of said load.
Description:
The present invention relates to electron beam deflection circuits
including thyristors, such as silicon controlled rectifiers and
relates, in particular, to horizontal deflection circuits for
television receivers.
The
present invention constitutes an improvement in the circuit
described in U.S. Pat. No. 3,449,623 filed on Sept. 6, 1966, this
circuit being described in greater detail below with reference to
FIGS. 1 and 2 of the accompanying drawings. A deflection circuit of
this type comprises a first thyristor switch which allows the
conenction of the horizontal deflection winding to a constant voltage
source during the time interval used for the transmisstion of the
picture signal and for applying this signal to the grid of the
cathode ray tube (this interval will be termed the "trace portion" of
the scan), and a second thyristor switch which provides the forced
commutation of the first one by applying to it a reverse current of
equal amplitude to that which passes through it from the said voltage
source and thus to initiate the retrace during the horizontal
blanking interval.
A undirectional reverse blocking
triode type thyristor or silicon controlled rectifier (SCR), such as
that used in the aformentioned circuit, requires a certain turn-off
time between the instant at which the anode current ceases and the
instant at which a positive bias may be applied to it without turning
it on, due to the fact that there is still a high concentration of
free carriers in the vicinity of the middle junction, this
concentration being reduced by a process of recombination
independently from the reverse polarity applied to the thyristor.
This turn-off time of the thyristor is a function of a number of
parameters such as the junction temperature, the DC current level,
the decay time of the direct current, the peak level of the reverse
current applied, the amplitude of the reverse anode to cathode
voltage, the external impedance of the gate electrode, and so on,
certain of these varying considerably from one thyristor to another.
In
horizontal deflection circuits for television receivers, the flyback
or retrace time is limited to approximately 20 percent of the
horizontal scan period, the retrace time being in the case of the CCIR
standard of 625 lines, approximately 12 microseconds and, in the
case of the French standard of 819 lines, approximately 9
microseconds. During this relatively short interval, the thyristor
has to be rendered non-conducting and the electron beam has to be
returned to the origin of the scan. The first thyristor is blocked by
means of a series resonant LC circuit which is subject to a certain
number of restrictions (limitations as to the component values
employed) due to the fact that, inter alia, it simultaneously
determines the turn-off time of the circuit which blocks the
thyristor and it forms part of the series resonant circuit which is
to carry out the retrace. To obtain proper operation of the
deflection circuit of the aforementioned Patent, especially when used
for the French standard of 819 lines per image, the values of the
components used have to subject to very close tolerances
(approximately 2%), which results in high costs.
The improved deflection circuit, object o
f
the present invention, allows the lengthening of the turn-off time
of the circuit for turning the scan thyristor off, without altering
the values of the LC circuit, which are determined by other criteria,
and without impairing the operation of the circuit.
According
to the invention, there is provided an electron beam deflection
circuit for a cathode ray tube with electromagentic deflection by
means of a sawtooth current waveform having a trace portion and a
retrace portion, said circuit comprising: a deflection winding; a
first source of electrical energy formed by a first capacitor; first
controllable switching means comprising a parallel combination of a
first thyristor and a first diode, connected together to conduct in
opposite directions, for connecting said winding to said first source
during said trace portion when said first switching means is turned
on; a second source of electrical energy including a first inductive
energy storage means coupled to a voltage supply; reactive circuit
means including a combination of inductive and capacitive reactances
for storing the energy supplied by the said second source; a second
controllable switching means, substantially identical with the first
one, for completing a circuit including said reactive circuit means
and said first switching means, when turned on, so as to pass through
said first thyristor an oscillatory current in the opposite direction
to that which passes through it from said first source and to turn
it off after these two currents cancel out, the oscillatory current
then flowing through said first diode for an interval termed the
circuit turn-off time which has to be greater than the turn-off time
of said first thyristor; and means for drawing duing at least a part
of said trace portion a substantial amount of additional current from
said first switching means in the direction of conduction of said
first diode, whereby said circuit turn-off time is lengthened in
proportion to the amount of said additional current, without altering
the values of the reactances in the reactive circuit by shifting the
waveform of the current flowing through said first switching means
towards the negative by an amount equal to that of said additional
current.
A further object of the invention consists
in using the supplementary current in the recovery diode of the first
switching means to produce a DC voltage which may be used as a power
supply for the vertical deflection circuit of the television
receiver, for example.
The invention will be better
understood and other features and advantages thereof will become
apparent from the following description and the accompanying drawings,
given by way of example, and in which:
FIG. 1 is a
schematic circuit diagram partially in bloc diagram form of a prior
art deflection circuit according to the aforementioned Patent;
FIG. 2 shows waveforms of currents and voltages generated at various points in the circuit of FIG. 1;
FIG.
3 is a schematic diagram of a deflection circuit according to the
invention which allows the principle of the improvement to be
explained;
FIG. 4 is a diagram of the waveforms of the current through the first switching means 4, 5 of the circuit of FIG. 3;
FIG. 5 is a circuit diagram of another embodiment of the circuit according to the invention;
FIG. 6 is a schematic representation of the preferred embodiment of the circuit according to the invention; and
FIG. 7 shows voltage waveforms at various points of the high voltage autotransformer 21 of FIG. 6.
In all these Figures the same reference numerals refer to the same components.
FIG.
1 shows the horizontal deflection circuit described and claimed in
the U.S. Pat. No. 3,449,623 mentioned above, which comprises a first
source of electrical energy in the shape of a first capacitor 2 having
a high capacitance C
2 for supplying a substantially constant voltage Uc
2
across its terminals. A first terminal of the first capacitor 2 is
connected to ground, whilst its second terminal which supplies a
positive voltage is connected to one of the terminals of a horizontal
deflection winding shown as a first inductance 1. A first switching
means 3, consisting of a first reverse blocking triode thyristor 4 (SCR)
and a first recovery diode 5 in parallel, the two being
interconnected to conduct current in opposite directions, is connected
in parallel with the series combination formed by the deflection
winding 1 and the first capacitor 2. The assembly of components 1, 2, 4
and 5 forms the final stage of the horizontal deflection circuit in a
television receiver using electromagnetic delfection.
The
deflection circuit also includes a drive stage for this final stage
which here controls the turning off of the first thyristor 4 to
produce the retrace or fly-back portion of the scan during the
line-blanking intervals i.e. while the picture signal is not
transmitted. This driver stage comprises a second voltage source in
the shape of a DC power supply 6 which delivers a constant high
voltage E. The negative terminal of the power supply 6 is connected to
ground and its positive terminal to one of the terminals of a second
inductance 7 of relatively high value, which draws a substantially
lineraly varying current from the power supply 6 to avoid its
overloading. The other terminal of th
e
second inductance 7 is connected, on the one hand, to the junction
of the deflection winding 1 and the first switching means 3 by means
of a second inductance 8 and a second capacitor 9 in series and, on
the other hand, to one of the terminals of a second controllable
bi-directionally conducting switching means 10, similar to the first
one 3, including a parallel combination of a second thyristor 11 and a
second recovery diode 12 also arranged to conduct in opposite
directions.
The respective values of the third inductance 8 (L
8 ) and of the second capacitor 9 (C
9 ) are principally selected so that, on the one hand, one half-cycle of oscillation of the first series resonant circuit L
8 - C
9 , (i.e. π √ L
8 . C
9 )
is longer than the turn-off time of the first thyristor 4, but still
is as short as possible since this time interval determines the
speed of the commutation of the thyristor 4, and, on the other hand,
one half-cycle of oscillation of another series resonant circuit
formed by L
1 , L
8 and C
9 , i.e. π √ (L
1 + L
8 )
. C
9 , is substantially equal to the required retrace time interval (i.e. shorter than the horizontal blanking interval).
The
gate (control electrode) of the second thyristor 11 is coupled to
the output of the horizontal oscillator 13 of the television receiver
by means of a first pulse transformer 14 and a first pulse shaping
circuit 15 so that it is fed short triggering pulses which are to turn
it on.
The gate of the first thyristor 4 fed with
signals of a substantially rectangular waveform which are negative
during the horizontal blanking intervals, is coupled to a winding 16
by means of a second pulse shaping circuit 17, the winding 16 being
magnetically coupled to the second inductance 7 to make up the
secondary winding of a transformer of which the inductance 7 forms
the primary winding. It will be noted here that it is also possible
to couple the secondary winding 16 magnetically to a primary winding
connected to a suitable output (not shown) of the horizontal
oscillator 13.
The operation of a circuit of this type
will be explained below with reference to FIG. 2 which shows the
waveforms at various points in the circuit of FIG. 1 during
approximately one line period.
FIG. 2 is not to scale since one line period (t
7 - t
0 )
is equal to 64 microseconds in the case of 625 lines and 49
microseconds in the case of 819 lines, while the durations of the
respective horizontal blanking intervals are approximately 12 and 9.5
microseconds.
Waveform A shows the form of the current i
L1 passing through deflection winding 1, this current having a sawtooth waveform substantially linear from t
0 to t
3 and from t
5 to t
7 , and crossing zero at time instants t
0 and t
7 , and reaching values of + I
1m and - I
1m , at time instants t
3 and t
5 respectively, these being its maximum positive and negative amplitudes.
During the second half of the trace portion of the horizontal deflection cycle, that is to say from t
0 to t
3 ,
the thyristor 4 of the first switching means 3 is conductive and
makes the high value capacitor 2 discharge through the deflector
winding 1, which has a high inductance, so that current i
L1 increases linearly.
A few microseconds (5 to 8 μ s) before the end of the trace portion, i.e. at time instant t
1 , the trigger of the second thyristor 11 receives a short voltage pulse V
G11
which causes it to turn on as its anode is at this instant at a
positive potential with respect to ground, which is due to the charging
of the second capacitor 9 through inductances 7 and 8 by the voltage E
from the power supply 6.
When thyristor 11 is made conductive at time t
1 ,
on the one hand, inductance 7 is connected between ground and the
voltage source 6 and a linearly increasing current flows through it
and, on the other hand, the reactive circuit 8, 9 forms a loop
through the second and first switching means 10 and 3, thus forming a
resonant circuit which draws an oscillatory current i
8 ,9 of frequency ##EQU1##
This oscillatory current i
8 ,9 will pass through the first switching means 3, i.e. thyristor 4 and diode 5, in the opposite direction to that of current i
L1 . Since the frequency f
1 is high, current i
8 ,9 will increase more rapidly than i
L1 and will reach the same level at time t
2 , that is to say i
8 ,9 (t
2 ) = -i
L1 (t
2 )
and these currents will cancel out in the thyristor 4 in accordance
with the well known principle of forced commutation. After time
instant t
2 , current i
8 ,9 continues to increase more rapidly than i
L1 , but the difference between them (i
8 ,9 - i
L1 ) passes the diode 5 (see wave form B) until it becomes zero at time instant t
3 which is the turn off time instant of the first switching means 3, at which the retrace begins.
The interval between the time instant t
2 and t
3 , i.e. (t
3 -t
2 ),
during which diode 5 is conductive and the thyristor is reverse
biased will be termed in what follows the circuit turn-off time and it
should
be greater than the turn-off time of the thyristor 4 itself since
the latter will subsequently become foward biased (i.e. from t
3 to t
5 ) by the retrace or flyback pulse (see waveform E) which should not trigger it.
At time instant t
3 , the switching means 3 is opened (i
4 and i
5
are both zero -- see waveforms B and C) and the reactive circuit 8, 9
forms a loop through capacitor 2 and the deflection coil 1 and thus a
series resonant circuit including (L
1 + L
8 ) and C
9 , C
2 being of high value and representing a short circuit for the flyback frequency ##EQU2## thus obtained.
The retrace which stated at time t
3 takes place during one half-cycle of the resonant circuit formed by reactances L
1 , L
8 and C
9 , i.e. during the interval between t
3 and t
5 . In the middle of this interval i.e. at time instant t
4 , both i
L1 (waveform A) and i
8 ,9 (waveform D) pass through zero and change their sign, whereas the voltage at the terminals of the first switching means 3 (V
3 , waveform E) passes through a maximum. Thus, from t
4
onwards, thyristor 11 will be reverse biased and diode 12 will
conduct the current from the resonant circuit 1, 8 and 9 in order to
turn the second thyristor 11 off.
At time instant t
5 , when current i
L1 has reached - I
1m and when voltage v
3 falls to zero, diode 5 of the first switching means 3 becomes conductive and the trace portion of scan begins.
Current i
8 ,9
nevertheless continues to flow in the resonant circuit 8, 9 through
diodes 5 and 12, which causes a break to appear in waveform D at t
5 , and a negative peak to appear in waveform D and a positive one in waveform B in the interval between t
5 and t
6 ,
these being principally due to the distributed capacities of coil 1
or to an eventual capacitor (not shown) connected in parallel to the
first switching means 3.
At time instant t
6 ,
diode 12 of the second switching means 10 ceases to conduct after
having allowed thyristor 11 time to become turned off completely.
The level of current i
8 ,9 at time instant t
5 (i.e. I
c ) as well as the negative peak I
D12 in i
8 ,9 and the positive peak I
D5 in i
5 depend on the values of L
8 and C
9 in the same way as does the turn-off time of the circuit (t
3 - t
2 ). If, for example, L
8 and C
9 , are increased I
D5 increases towards zero and this could cause diode 5 to be cut off in an undesirable fashion. I
c also increases towards zero, which is liable to cause diode 12 to be blocked and thyristor 11 to trigger prematurely.
From the foregoing it can be clearly seen that the choice of values for L
8 and C
9
is subject to four limitations which prevent the values from being
increased to lengthen the turn-off time of the driver circuit of first
switching thyristor 4 so as to forestall its spurious triggering.
Waveform F shows the voltage v
G4 obtained at the gate of thyristor 4 from the secondary winding 16 coupled to the inductor 7. This voltage is positive from t
0 to t
1 and from t
6 to t
7 and is negative between t
2 and t
6 i.e. while the second switching means 10 is conducting.
The
present invention makes the lengthening of the turn-off time of
thyristor 4 possible without altering the parameters of the circuit such
as inductance 8 and capacitor 9.
In
the circuit shown in FIG. 3, which illustrates the principle of the
present invention, means are added to the circuit in FIG. 1 which
enable the turn-off time to be lengthened by connecting a load to
diode 5 so as to increase the current which flows through it during
the time that it is conductive. These means are here formed by a
resistor 18 connected in parallel with a capacitor 20 (which replaces
capacitor 2) which is of a higher capacitance so that, in practice,
it holds its charge during at least one half of the line period. FIG.
4, which shows the waveform of the current in the first switching
means 3 for a circuit as shown in FIG. 3, makes it possible to
explain how this lenthening of the turn-off time is achieved.
In
FIG. 4, the broken lines show the waveform of the current in the
first switch device 3 in the circuit of FIG. 1, this waveform being
produced by adding waveforms B and C of FIG. 2. The current i
4 above the axis flows through thyristor 4 and current i
5 below the axis flows through diode 5. When the capacitance C
20 of the capacitor in series with the deflector coil is increased to some tens of microfarads (C
2
having been of the order of 1 μ F) and when there is connected in
parallel with capacitor 20 a resistor 18 the value of which is
calculated to draw a strong current I
R18 from capacitor 20, that is to say a current at least equal to 0,1 I
m (I
m being of the order of some tens of amperes), current I
R18 is added to that i
5
which flows through diode 5 without in any way altering the
linearity of the trace portion nor the oscillatory commutation of
thyristor 4 which is brought about by the resonant circuit L
8 , C
9 .
The fact of loading capacitor C
20
by means of a resistor 18 thus has the effect of permanently
displacing the waveform of the current in the negative direction by I
R18 . Thus, during the trace portion of the scan, the transfer of the current from the diode 5 to the thyristor 4 begins at time t
10 instead of t
0 , that is to say with a delay proportional to I
R18 .
The effect of the triggering pulse delivered by the horizontal
oscillator (13 FIG. 1) to the second thyristor 11 at time instant t
1 , will be to start the commutation process of the first thyristor 4 when the current it draws is less by I
R18 than that i
4 (t
1 )
which it would have been drawing had there been no resistor 18.
Because of this, the turn-off time of the thyristor 4 proper, which as
has been mentioned increases with the maximum current level passing
throught it, is slightly reduced. Moreover, because the oscillatory
current i
8 ,9 (FIG. 2) from circuit L
8 , C
9 which flows through thyristor 4 in the opposite direction is unchanged, it reaches a value equal to that of the current i
L1 (FIG. 1) flowing in the coil 1 in a shorter time, that is to say at time t
12 . Diode 5 will thus take the oscillatory current i
8 ,9 (FIG. 2) over in advance with respect ro time instant t
2 and will conduct it until it reaches zero value at a time instant t
13 later than t
3 , the amounts of advance (t
2 - t
12 ) and delay (t
13 - t
3 ) being practically equal.
It can thus be seen in FIG. 4 that the circuit turn-off time T
R of a circuit according to the invention and illustrated by FIG. 3 is distinctly longer than that T
r of the circuit in FIG. 1. This increase in the turn-off time (T
R - T
r ) depends on the current I
R18 and increases therewith.
It should be noted at this point that the current I
R18
produces a voltage drop at the terminals of the resistor the only
effect of which is to heat up the resistor since the level of this
voltage (40 to 60 volts) does not necessarily have a suitable value to
be used as a voltage supply for other circuits in an existing
transistorised television receiver.
In accordance with
one embodiment of the invention, illustrated in FIG. 5, an
application is proposed for the additional current which is to be
drawn through diode 5. In FIG. 5, the positive terminal of capacitor
20 is connected by a conductor 19 to the negative pole of the power
supply 6 and the voltage at the terminals of capacitor 20 is thus
added to that E from the source 6.
In the preferred
embodiment of the present invention, which is shown in FIG. 6, it is
possible to cause a supplementary current of a desired value to flow
through the first diode 5 while obtaining a voltage which has a
suitable value for use in another circuit in the television receiver.
If
the voltage at the terminals of capacitor 20 in FIG. 3 is not a
usable value, it is possible to connect in parallel with the series
circuit comprising the deflector coil 1 and the capacitor 2 in FIG.
1, i.e. in parallel with the terminals of the first switching means
3, a series combination of an autotransformer 21 and a high value
capacitor 22 (comparable with capacitor 20 in FIGS. 3 and 5). The
autotransformer 21 has a tap 23 is suitably positioned between the
terminal connected to capacitor 22 at the tap 24 connected to the
first switching means 3. This autotransformer 21 may be formed by the
one conventionally used for supplying a very high voltage to the
cathode ray tube, as described for example in U.S. Pat. No.
3,452,244; such a transformer comprises a voltage step-up winding
between taps 24 and 25, which latter is connected to a high voltage
rectifier (not shown).
The waveform of the voltage at
the various points in the autotransformer is shown in FIG. 7, in
which waveform A shows the voltage at the terminals of capacitor 22,
waveform B the voltage at tap 24 and waveform C the voltage at tap 23
of the autotransformer 21.
The voltage V
c22 at the terminals of capacitor 22 varies slightly about a mean value V
cm . It is increasing while diode 5 is conducting and decreasing during the conduction of the thyristor 4.
The voltage v
24
at tap 24 follows substantially the same curve as waveform E in FIG.
2, that is to say that during the retrace time interval from t
13 to t
5
to a positive pulse called the flyback pulse is produced and, during
the time interval while the first switching means 3 is conducting,
the voltage is zero. The mean valve of the voltage v
24 at tap 24 of the auto-transformer 21 is equal to the mean value V
cm of the voltage at the terminals of capacitors 2 and 22.
Thus,
there is obtained at tap 23 a waveform which is made up, during the
retrace portion, of a positive pulse whose maximum amplitude is less
than that of v
24 at tap 24 and, during the trace
portion, of a substantially constant positive voltage, the level V of
which is less than the mean value V
cm of the voltage v
c22
at the terminals of capacitor 22. By moving tap 23 towards terminals
24 the amplitude of the pulse during fly-back increases while
voltage V falls and conversely by moving tap 23 towards capacitor 22
voltage V increases and the amplitude of the pulse drops.
In more exact terms, the voltage V at tap 23 is such that the means value of v
23 is equal to V
cm .
It has thus been shown that by choosing carefully the position of
tape 23, a voltage V may be obtained during the trace portion of the
scan, which may be of any value between V
cm and zero.
This
voltage V is thus obtained by periodically controlled rectification
during the trace portion of the scan. For this purpose an electronic
switch is used to periodically connect the tap 23 of trnasformer
winding 21 to a load. This switch is made up of a power transistor 26
whose collector is connected to tap 23 and the emitter to a parallel
combination formed by a high value filtering capacitor 27 and the
load which it is desired to supply, which is represented by a
resistor 28. The base of the transistor 26 receives a control voltage
to block it during retrace and to unblock it during the whole or part
of the trace period. A control voltage of this type may be obtained
from a second winding 29 magnetically coupled to the inductance 7 of
the deflection circuit and it may be transmitted to the base of
transistor 26 by means of a coupling capacitor 30 and a resistor 31
connected between the base and the emitter of transistor 26.
It
may easily be seen that the DC collector/emitter current in
transistor 26 flows through the first diode 5 of the first switching
means 3 via a resistor 28 and the part of the winding of
auto-transformer 21 located between taps 23 and 24.
Experience
has shown that a circuit as shown in FIG. 6 can supply 24 volts with
a current of 2 amperes to the vertical deflection circuit of the
same television set, the voltage at the terminals of capacitor 22
being from 50 to 60 volts.
It should be mentioned
that, when the circuit which forms the load of the controlled
rectifier 26, 27 does not draw enough current to sufficiently
lengthen the circuit turn-off time T
R , an additional
resistor (not shown) may be connected between the emitter of
transistor 26 and ground or in parallel to capacitor 22, which
resistor will draw the additional current required.
METZ 7096 CLASSIC COLOR (CH679G) CHASSIS 679G Gating circuit for television SCR deflection system AND
REGULATION / stabilization of horizontal deflection NETWORK CIRCUIT
with Transductor reactor / Reverse thyristor energy recovery circuit.
In a television deflection system
employing
a first SCR for coupling a deflection winding across a source of
energy during a trace interval of each deflection cycle and a second
SCR for replenishing energy to the source of energy during a
commutation interval of each deflection cycle, a gating circuit for
triggering the first SCR. The gating circuit employs a voltage divider
coupled in parallel with the second SCR which develops gating signals
proportional to the voltage across the second SCR.
1.
In a television deflection system in which a first switching means
couples a deflection winding across a source of energy during a trace
interval of each deflection cycle and a second switching means
replenishes e
nergy to said source of energy during a commutation
interval of each deflection cycle, a gating circuit for said first
switching means, comprising:
capacitive
voltage divider means coupled in parallel with said second switching
means for developing gating signals proportional to the voltage
across said second switching means; and
means
for coupling said voltage divider means to said first switching
means to provide for conduction of said first switching means in
response to said gating signals.
2.
A gating circuit according to claim 1 wherein said voltage divider
includes first and second capacitors coupled in series and providing
said gating signals at the common terminal of said capacitors. 3. A
gating circuit according to claim 2 wherein said first and second
capacitors are proportional in value to provide for the desired
magnitude of gating signals. 4. A gating circuit according to claim 3
wherein said means for coupling said voltage divider means to said
first switching means includes an inductor. 5. A gating circuit
according to claim 4 wherein said inductor and said first and second
capacitors comprise a resonant circuit having a resonant frequency
chosen to shape said gating signal to improve switching of said first
switching means.
Description:
BACKGROUND OF THE INVENTION
This
invention relates to a gating circuit for controlling a switching
device employed in a deflection circuit of a television receiver.
Various
deflection system designs have been utilized in television
receivers. One design employing two bidirectional conducting switches
and utilizing SCR's (thyristors) as part of the switches is
disclosed in U.S. Pat. No. 3,452,244. In this type deflection system,
a first SCR is
employed
for coupling a deflection winding across a source of energy during a
trace interval of each deflection cycle, and a second SCR is
employed for replenishing energy during a commutation interval of each
deflection cycle. The first SCR is commonly provided with gating
voltage by means of a separate winding or tap of an input reactor
coupling a source of B+ to the second SCR.
Various
regulator system designs have been utilized in conjunction with the
afore described deflection system to provide for uniform high voltage
production as well as uniform picture width with varying line
voltage and kinescope beam current conditions.
One type
regulator system design alters the amount of energy stored in a
commutating capacitor coupled between the first and second SCR's
during the commutating interval. A regulator design of this type may
employ a regulating SCR and diode for coupling the input reactor to
the source of B+. With this type regulator a notch, the width of
which depends upon the regulation requirements, is created in the
current supplied through the reactor and which notch shows up in the
voltage waveform developed on the separate winding or tap of the
input reactor which provides the gating voltage for the first SCR.
The presence of the notch, even though de-emphasized by a waveshaping
circuit coupling the gating voltage to the first SCR, causes erratic
control of the first SCR.
SUMMARY OF THE INVENTION
In
accordance with one embodiment of the invention, a gating circuit of
a television deflection system employing a first switching means for
coupling a deflection winding across a source of energy during a
trace interval of each deflection cycle and a second switching means
for replenishing energy to said source of energy during a commutation
interval of each deflection cycle includes a voltage divider means
coupled in parallel with the second switching means for developing
gating signals proportional to the voltage across the second switching
means. The voltage divider means are coupled to the first switching
means to provide for conduction of the first switching means in
response to the gating signals.
A more detailed description of a
preferred embodiment of the invention is given in the following
description and accompanying drawing of which:
FIG. 1 is a schematic diagram, partially in block form, of a prior art SCR deflection system;
FIG.
2 is a schematic diagram, partially in block form, of an SCR
deflection system of the type shown in FIG. 1 including a gating
circuit embodying the invention;
FIG. 3 is a schematic diagram,
partially in block form, of one type of a regulator system which
employs an SCR as a control device and which is suitable for use with
the SCR deflection system of FIG.2;
FIG. 4 is a schematic
diagram, partially in block form, of another type of a regulator
system suitable for use with the deflection circuit of FIG. 2; and
FIG.
5 is a schematic diagram, partially in block form, of still another
type of a regulator system suitable for use with the SCR deflection
system of FIG. 2.
DESCRIPTION OF THE PREFERRED EMBODIMENT
FIG.
1 is a schematic diagram, partially in block form, of a prior art
deflection system of the retrace driven type similar to that disclosed
in U.S. Pat. No. 3,452,244. This system includes a commutating switch
12, comprising a silicon controlled rectifier (SCR) 14 and an
oppositely poled damper diode 16. The commutating switch 12 is coupled
between a winding 18a of an input choke 18 and ground. The other
terminal of winding 18a is coupled to a source of direct current
voltage (B+) by means of a regulator network 20 which controls the
energy stored in the deflection circuit 10 when the commutating switch
is off, during an interval T3 to T0' as shown in curve 21 which is a
plot of the voltage level at the anode of SCR 14 during the
deflection cycle. A damping network comprising a series combination
of a resistor 22 and a capacitor 23 is coupled in parallel with
commutating switch 12 and serves to reduce any ringing effects
produced by the switching of commutating switch 12. Commutating
switch 12 is coupled through a commutating coil 24, a commutating
capacitor 25 and a trace switch 26 to ground. Trace switch 26
comprises an SCR 28 and an oppositely poled damper diode 30. An
auxiliary capacitor 32 is coupled between the junction of coil 24 and
capacitor 25 and ground. A series combination of a horizontal
deflection winding 34 and an S-shaping capacitor 36 are coupled in
parallel with trace switch 26. Also, a series combination of a primary
winding 38a of a horizontal output transformer 38 and a DC blocking
capacitor 40 are coupled in parallel with trace switch 26.
A
secondary of high voltage winding 38b of transformer 38 produces
relatively large amplitude flyback pulses during the retrace interval of
each deflection cycle. This interval exists between T1 and T2 of
curve 41 which is a plot of the current through windings 34 and 38a
during the deflection cycle. These flyback pulses are applied to a
high voltage multiplier (not shown) or other suitable means for
producing direct current high voltage for use as the ultor voltage of a
kinescope (not shown).
An auxiliary winding 38c of transformer
38 is coupled to a high voltage sensing and control circuit 42 which
transforms the level of flyback pulses into a pulse width modulated
signal. The control circuit 42 is coupled to the regulator network
20.
A horizontal oscillator 44 is coupled to the gate electrode
of commutating SCR 14 and produces a pulse during each deflection
cycle slightly before the end of the trace interval at T0 of curve 21
to turn on SCR 14 to initiate the commutating interval. The
commutating interval occurs between T0 and T3 of curve 21. A resonant
waveshaping network 46 comprising a series combination of a
capacitor 48 and an inductor 50 coupled between a winding 18b of
input choke 18 and the gate electrode of trace SCR 28 and a damping
resistor 52 coupled between the junction of capacitor 48 and inductor
50 and ground shapes the signal developed at winding 18b (i.e.
voltage waveform 53) to form a gating signal voltage waveform 55 to
enable SCR 28 for conduction during the second half of the trace
interval occurring between T2 and T1' of curve 41.
The
regulator network 20, when of a type to be described in conjunction
with FIG. 3, operates in such a manner that current through winding
18a of input choke 18 during an interval between T4 and T5 (region A)
of curves 21, 53 and 55 is interrupted for a period of time the
duration of which is determined by the signal produced by the high
voltage sensing and control circuit 42. During the interruption of
current through winding 18a a zero voltage level is developed by
winding 18b as shown in interval T4 to T5 of curve 53. The resonant
waveshaping circuit 46 produces the shaped waveform 55 which
undesirably retains a slump in region A corresponding to the notch A
of waveform 53. The slump in waveform 55 applied to SCR 28 occurs in a
region where the anode of SCR 28 becomes positive and where SCR 28
must be switched on to maintain a uniform production of the current
waveshape in the horizontal deflection winding 34 as shown in curve
41. The less positive amplitude current occurring at region A of
waveform 55 may result in insufficient gating current for SCR 28 and
may cause erratic performance resulting in an unsatisfactory raster.
FIG.
2 is a schematic diagram, partially in block form, of a deflection
system 60 embodying the invention. Those elements which perform the
same function in FIG. 2 as in FIG. 1 are labeled with the same
reference numerals. FIG. 2 differs from FIG. 1 essentially in that
the signal to enable SCR 28 derived from sampling a portion of the
voltage across commutating switch 12 rather than a voltage developed
by winding 18b which is a function of the voltage across winding 18a
of input choke 18 as in FIG. 1. This change eliminates the slump in
the enabling signal during the interval T4 to T5 as shown in curve 64
since the voltage across the commutating switch 12 is not adversely
effected by the regulator network 20 operation.
A series
combination of resistor 22, capacitor 23 and a capacitor 62 is
coupled in parallel with commutating switch 12, one terminal of
capacitor 62 being coupled to ground. The junction of capacitors 23
and 62 is coupled to the gate electrode of SCR 28 by means of the
inductor 50. The resistor 52 is coupled in parallel with capacitor
62.
Capacitors
23 and 62 form a capacitance voltage divider which provides a
suitable portion of the voltage across commutating switch 12 for
gating SCR 28 via inductor 50. The magnitude of the voltage at the
junction of capacitors 23 and 62 is typically 25 to 35 volts. It can,
therefore, be seen that the ratio of values of capacitors 23 and 62
will vary depending on the B+ voltage utilized to energize the
deflection system. Capacitors 23 and 62 and inductor 50 form a
resonant circuit tuned in a manner which provides for peaking of the
curve 64 between T4 and T5. This peaking effect further enhances
gating of SCR 28 between T4 and T5.
Since the waveshape of the
voltage across commutating switch 12 (curve 21) is relatively
independent of the type of regulator system employed in conjunction
with the deflection system, the curve 64 also is independent of the
type of regulator system.
When
commutating switch 12 switches off during the interval T3 to T0'
curve 21, the voltage across capacitor 62 increases and the voltage at
the gate electrode of SCR 28 increases as shown in curve 64. As will
be noted, no slump of curve 64 occurs between T3 and T5 because
there is no interruption of the voltage across commutating switch 12.
FIG.
3 is a schematic diagram, partially in block form, of one type of a
regulator system which may be used in conjunction with the invention.
B+ is supplied through a regulator network 20 which comprises an SCR
66 and an oppositely poled diode 68. The diode is poled to provide
for conduction of current from B+ to the horizontal deflection
circuit 60 via winding 18a of input choke 18. Current flows through
the diode during the period T3 to T4 of curve 21 FIG. 1 after which
current tries to flow through the SCR 66 from the horizontal
deflection circuit to B+ since the commutating capacitor 25 is
charged to a voltage higher than B+.
The horizontal deflection
circuit 60 produces a flyback pulse in winding 38a of the flyback
transformer 38 which is coupled to winding 38c. The magnitude of the
pulse on winding 38c determines how long the signal required to
switch SCR 66 on is delayed after T4 curve 21 FIG. 1. If the flyback
pulse is greater than desirable, the SCR 66 turns on sooner than if
the flyback pulse is less than desirable and provides a discharge
path for current in commutating capacitor 25 back to the B+ supply.
In this manner a relatively constant amplitude flyback pulse is
maintained.
FIG.
4 is a schematic diagram, partially in block form, of another
well-known type of a regulator system which may be used in conjunction
with the invention shown in FIG. 2. B+ is coupled through winding 18a
of input choke 18 and through a series combination of windings 70a
and 70b of a saturable reactor 70 and a parallel combination of a
diode 72 and a resistor 74 to the horizontal deflection circuit 60.
Diode 72 is poled to conduct current from the horizontal deflection
circuit 60 to B+.
Flyback pulse variations are obtained from
winding 38c of the horizontal output transformer 38 and applied to a
voltage divider comprising resistors 76, 78 and 80 of the high
voltage sensing and control circuit 42. A portion of the pulse
produced by winding 38c is selected by the position of the wiper
terminal on potentiometer 78 and coupled to the base electrode of a
transistor 82 by means of a zener diode 84. The emitter electrode of
transistor 82 is grounded and a DC stabilization resistor 85 is
coupled in parallel with the base-emitter junction of transistor 82.
When the pulse magnitude on winding 38c exceeds a level which results
in forward biasing the base-emitter junction of transistor 82,
current flows from B+ through a resistor 86, a winding 70c of
saturable reactor 70 and transistor 82 to ground. Due to the
exponential increase of current in winding 70c during the period of
conduction of transistor 82, the duration of conduction of transistor
82 determines the magnitude of current flowing in winding 70c and
thus the total inductance of windings 70a and 70b. The current in
winding 70c is sustained during the remaining deflection period by
means of a diode 88 coupled in parallel with winding 70c and poled not
to conduct current from B+ to the collector electrode of transistor
82. A capacitor 90 coupled to the cathode of diode 88 provides a
bypass for B+. Windings 70a and 70b are in parallel with input reactor
18a and thereby affect the total input inductance of the deflection
circuit and thereby controls the transfer of energy to the deflection
circuit. The dotted waveforms shown in conjunction with a curve 21'
indicate variations from a nominal waveform provided at the input of
horizontal deflection circuit 60 by the windings 70a and 70b.
FIG.
5 is a schematic diagram of yet another type of a regulator system
which may be used in conjunction with the invention. B+ is coupled
through a winding 92a and a winding 92b of a saturable reactor to the
horizontal deflection circuit 60. Windings 92a and 92b are used to
replace the input choke 18 shown in FIGS. 1 and 2 while also providing
for a regulating function corresponding to that provided by regulating
network 20.
Flyback pulse variations are obtained from
winding 38c and applied to the high voltage sensing and control circuit
42 as in FIG. 4. Current flows from B+ through resistor 86, a
winding 92c and transistor 82 to ground. As in FIG. 4 the duration of
the conduction of transistor 82 determines the energy stored in
winding 92c and thus the total inductance of windings 92a and 92b
which control the amount of energy transferred to the deflection
circuit during each horizontal deflection cycle. The variations in
waveforms of curve 21', shown in conjunction with FIG. 4, are also
provided at the input of horizontal deflection circuit 60 by windings
92a and 92b.
For
various reasons including cost or performance, a manufacturer may
wish to utilize a particular one of the regulators illustrated in
FIGS. 3, 4 and 5. Regardless of the choice, the gating circuit
according to the invention may be utilized therewith advantageously by
providing improved performance and the possibility of cost savings
by eliminating taps or extra windings on the wound components which
heretofore normally provided a source of SCR gating waveforms.
The 30AX system, which Philips introduced in 1979, is an important
landmark in the development of colour picture systems. With previous
systems the assembly technician had to workthrough a large number of
complicated setting-up procedures whenever he fitted a television
picture tube with aset of coils for deflecting the electron beams. These
procedures were necessary to ensure that the beams for the three
colours would converge at thescreen for every deflection. They are no
longer necessary with the 30AX system: for a given screen format any
deflection unit can be combined with any tube to form a single
'dynamically convergent' unit. A colour-television receiver can thus be
assembled from its components almost as easily as a monochrome receiver.
The colour picture tube of the PHILIPS 30AX system displays a
noticeably sharper picture over the entire screen surface. This will be
particularly noticeable when data transmissions such as Viewdata and
Teletext are displayed. This has been achieved by a reduction in the
size of the beam spot by about 30%. Absence of coma and the retention of
the 36.5 mm neck diameter have both contributed to increased picture
sharpness. Coma has been eliminated by means of corrective field shapers
embedded in the deflection coils which are sectionally wound saddle
types. The new deflection unit has no rear flanges. enabling uniform
self-convergence to be obtained for all screen sizes. without special
corrections, adjustments, or tolerance compensations. Horizontal raster
distortion is reduced and no vertical correction is required. One of the
inventions in 30AX is an internal magnetic c
orrection
system which obviates static convergence and colour purity errors. This
enables the usual multiple unit to be dispensed with. together with the
need for its adjustment ! New techniques have been employed to achieve
close tolerance construction of the glass envelope. In addition, the
30AX picture tube incorporates two features whereby it can be accurately
adjusted during the last stages of manufacture. One is the internal
magnetic correction system. The other is an array of bosses on the cone
that establish a precise reference for the axial purity positioning of
the deflection unit on the tube axis and for raster orientation. During
its manufacture, each deflection unit is individually adjusted for
optimum convergence. The coil carrier also incorporates reference bosses
that co-operate with those on the cone of the tube. ' Since every
picture tube and every deflection unit is individually pre-aligned, any
deflection unit automatically matches with any picture tube of the
appropriate size. The deflection unit has only to be pushed onto the
neck of the tube unit it seats. Once the reference bosses are engaged,
the combination is accurately aligned and requires no adjustment for
convergence, colour purity or raster orientation. With no multiple unit
and a flangeless deflection unit, there is more space in the receiver
cabinet. Higher deflection sensitivity means that less current is
consumed, and consequently less heat is produced. This increases the
reliability of the TV receiver again. 30AX means simple assembly. Any
picture tube is compatible with any deflection unit of the appropriate
size and is automatically self-aligning as well as being
self-convergent.
Sound is produced by a nice speakerbox integrated in the cabinet allowing super bass sound allowed even by the tone controls.
It's a very good system to use where the line scan coils require large
peak currents with only a moderate flyback voltage an intrinsic
characteristic of toroidally wound deflection coils. The basic thyristor
line output stage arrangement used in all these chassis is shown in
Fig. 1
e
a cumulative effect, a high resistance joint increasing the local
heating until the joint becomes well and truly dry -a classic symptom
with some Grundig / Emerson sets. The wound components themselves can be
a source of trouble, due to losses - particularly the combi coil and
the regulating transductor. Later chassis are less prone to this sort of
thing, partly because of the use of later generation, higher efficiency
yokes but mainly due to more generous and better design of the wound
components. The ideal dielectric for use in the tuning capacitors is
polypropylene (either metalised or film). It's a truly won- derful
dielectric - very stable, with very small losses, and capable of
operation at high frequencies and elevated temperatures. It's also
nowadays reasonably inexpensive. Unfortunately many earlier chassis of
this type used polyester capacitors, and it's no surprise that they were
inclined to give up. When replacing the tuning capacitors in a
thyristor line output stage it's essential to use polypropylene types -a
good range of axial components with values ranging from 0.001µF to
047µF is available from RS Components, enabling even non-standard values
to be made up from an appropriate combination. Using polypropylene
capacitors in place of polyester ones will not only ensure capacitor
reliability but will also lower the stress on other components by
reducing the circuit losses (and hence power consumption).
electronic industry’s most independent and successful
companies, celebrates its rich tradition as it enters its seventieth
year. An amazing success story during a period when numerous well-known
manufacturers had to concede to difficult market conditions and suspend
business activity. In 1938 Metz began producing electronic equipment.
During subsequent years Paul Metz led his company to a position of
worldwide importance. The company currently focuses on three business
areas: entertainment electronics, photo electronics and plastics
technology. Numerous innovations shape both past and present and create a
promising potential for the future. To date this has united the
company’s development and production, which is still owner-led and based
in Germany, guaranteeing a consistently high "made in Germany" standard
of quality.
The
latest successful model was voted "the best flash unit in Europe" at
the end of 2007. It was the world’s first flash to be equipped with a
USB interface. The individual firmware for every version of the model
can be easily updated via computer and internet by means of this
interface. 
