Used ICs: TDA2542 – MC14053 – TDA1048 – TDA1180 – TDA3030A – TDA1170S – TDA3300
- Right side
Supply with Step-Up line synchronized (Supply is 80 Volt converted to 135 Volt)
Synchronization / Line deflection output (Telefunken BU208) EHT + Tripler + E/W Correction.
- Left side
Signal Processing / Video with TDA3300 (MOTOROLA)
Frame deflection with TEA1020SP (Thomson)
Tuner + IF VIDEO AND SOUND BOARD
This chassis runs cold without particularly hot parts. It's higly reliable and durable.
It's
power supplyed by a separation transformer (see picture) wich provides
all mains voltages for the set then these are converted where needed
by line synch SMPS stabilized switching circuitry to supply the main
parts of the receiver (Deflections and Video).
Probabily on of the best chassis made by NORDMENDE During the transition to THOMSON.
We can see a discrete level of integration here and we are in 1980 !!!!
Indeed you can find this Chassis even in some SABA Tellye.
NORDMENDE SPECTRA SK3-COLOR T3137 CHASSIS F9 (492.445)
Receiver tuning circuit with automatic search and AFC using common capacitor:
Signal-seeking
tuning systems are well known for their convenience and ease of
operation, especially in the field of radio and television receivers.
They are commonly used to provide automatic tuning to the next higher
or lower frequency of interest in response to a user-operated
initiating mechanism (typically a momentary-contact switch). The
advent of solid-state, voltage-dependent variable-reactance devices
has permitted substantial improvement in signal-seeking tuning systems
because of the consequent elimination of electric motors and other
moving parts, thereby increasing efficiency and decreasing the number
of malfunctions resulting from mechanical wear, dirt accumulation,
and contact corrosion.
The most common type of
voltage-dependent variable-reactance device is a diode which has an
interelectrode capacitance directly proportional to its reverse-bias
voltage, commonly referred to as a "Varicap" or "varactor" diode. By
placing one or more such diodes in the frequency-selecting portion of
a tuner, station selection may be achieved by progressively
increasing or decreasing the voltage applied to the diode(s) until the
desired frequency is obtained. Moreover, by combining a
varactor-diode tuner with a progressively variable DC control voltage
generator, a signal detector, and a feedback control loop, a
satisfactory solid-state signal-seeking system may be created.
In
conventional signal-seeking systems employing varactor diodes,
however, a temporary loss of signal resulting from "airplane
flutter," transmitter failure, etc., or even receiver deenergization,
varies (or eliminates) the control voltage and/or interrupts the
recognition signal from the signal detector and therefore sends the
system seeking for a new station. The addition of complex delay
circuitry for temporarily maintaining the DC control voltage not only
adds appreciable cost to the system but also does not compensate for
the loss of control voltage due to receiver deenergization such as
when the receiver is turned off for a while.
It is therefore an object of the invention to provide a new and improved signal-seeking system for a voltage-controlled tuner.
It
is a more specific object of the invention to provide such a new and
improved signal-seeking tuning system which is immune to undesired
signal-seeking resulting from a temporary loss of signal or receiver
deenergization.
A
station finder which switches to automatic frequency control during
automatic finding in case of reception of a transmitter and, if
desired, continues to find a transmitter some time later with the
frequency control switched off.
1. A receiver tuning circuit f
or
a tuner comprising means for detecting the presence of a received
signal having an input means for coupling to said tuner; a search tuning
circuit having a capacitor means for a tuning voltage for said
tuner, and an automatic frequency control circuit coupled to said
capacitor, said tuning circuit and said automatic frequency control
circuit charging said capacitor when activated; an operating device
means coupled to said detecting means and said search tuning circuit
for activation of said search tuning circuit and for subsequent
deactivation of said search tuning circuit and activation of said
automatic frequency control circuit upon detection of a received
signal; and time constant circuit means coupled between said
detecting means and said operating device means for repeatedly
activating said search tuning circuit and deactivating said automatic
frequency control circuit a selected time after said search tuning
circuit has been deactivated.
2.
A receiver tuning circuit as claimed in claim 1, wherein said
operating device has a supply lead and the time constant circuit is
coupled to the supply lead of the operating device.
3. A receiver tuning circuit as claimed in
claim 1, wherein the detection circuit is coupled to an output of a
frequency detector and includes a means for preventing pulling in on
the same transmitter upon activation of said search tuning circuit.
Description:
The
invention relates to a receiver tuning circuit including a search
tuning circuit which can be activated by a control device in which the
search tuning circuit is automatically switched off when a received
station is detected by a detection circuit and an automatic frequency
control circuit is switched on, and in which a time constant circuit
changes the state of the receiver tuning circuit after a certain
time.
A receiver tuning circuit of the kind described above is
known from German Offenlegungsschrift 2,023,352 which after
activation of the search tuning stops the search action when a
transmitter transmitting a pilot signal is received and switches on
an automatic frequency control circuit. The search tuning circuit
must again be a
ctivated
when the received transmitter is not desired. When a transmitter
without a pilot signal is received, the search tuning circuit switches
over to a slowed down searching action and the automatic frequency
control remains switched off. The tuning circuit includes a time
constant circuit which renders the detection circuit for the pilot
signal inactive some time after the finder has been activated so that
the circuit can then pull in on transmitters without a pilot signal.
This
known tuning circuit is only suitable for special receivers. An
object of the invention is to provide a tuning circuit which is more
suitable for other receiver types.
To this end a receiver tuning
circuit of the kind described in the preamble according to the
invention is characterized in that the time constant circuit is
incorporated in the tuning circuit in such a manner that again and
again it switches on the search tuning circuit a certain time after
having automatically switched it off and switches off the automatic
frequency control as long as the search tuning circuit is maintained
operative with the aid of the operating device.
By using the
step according to the invention a receiver is obtained which upon
activation of the search tuning circuit receives without distortion
transmitter after transmitter each during a time determined by the time
constant circuit. The search tuning can be rendered inactive with
the aid of the operating device after the desired station has been
found. The tuning circuit is very suitable for radio or television
receivers for domestic use.
Method
and system for increasing the number of instructions transmitted in
digital systems, I.A. in systems for remote control of television
receiver:ITT VOLTAGE SYNTHESIZER TUNING SEARCH SYSTEM NORDMENDE SPECTRA SK3-COLOR T3137 CHASSIS F9 (492.445)
Method
of increasing the number of instructions according to the invention
consists therein that withing the command signal (6) additional
instructions are transmitted, which after being decoded in the
instruction decoder (1) and processed in the strobbin signal generation
circuit (4) strobes the operation of additional controlled units
(5) and control the transmission of the signal through the register
(2) to the controlled units (3).
In
the system according to the invention, between one of the outputs
od the instruction decoder (1) and the unit (3) to be controlled the
register (2) is connected, provided with an additional input for
the record inhibiting instruction (10), whereas to the second output
of the instruction decoder (1) the strobbing signal generation
circuit (4) is connected aimed at controlling the additional
controlled units (5). The register (2) and the strobbing signal
generation circuit (4), employed in the system according to the
invention, can be built-in into each of the integrated circuits or
made in form of a separate integrated circuit.
1. A
method of increasing the number of instructions transmitted in
remote control systems of television receivers and the like in which
decoded signals directly control receiving units, comprising
transmitting coded instructions in a command signal (6), decoding
said instructions into a first part of an instruction signal (8),
processing said first part of the instruction signal (8) in a
strobing signal generation circuit (4) to provide a first signal
(10) in a form for enabling the transmission of a control signal (7)
through a register (2) in the form of a stored signal (11) to first
receiving units (3) to be controlled while simultaneously providing
a second signal (9) in a form for blocking the reception of one of
said instruction signal (8) and said control signal (7) by
additional receiving units (5) to be controlled, transmitting an
additional coded instruction in said command signal, decoding said
additional instruction into a second part of the instruction signal
(8), processing said second part of the instruction signal (8) in
said strobing signal generation circuit (4) to provide said first
signal (10) in a form for blocking further storage of said control
signal (7) in said register (2) while simultaneously providing said
second signal (9) in a form for enabling the reception of said one
of said instruction signal (8) and said control signal (7) by said
additional receiving units (5) to be controlled, and transmitting a
coded erasing instruction in said command signal for restarting the
method. 2. A method according
to claim 1, wherein the controlling of said additional receiving
units (5) by one of said instruction signal (8) and said control
signal (7) is performed while controlling said first receiving units
(3) by said stored signal (11).
3. A system for increasing the number of instructions transmitted
in remote control systems of television receivers and the like,
comprising an instruction decoder (1), a first unit (3) to be
controlled, a main register (2) connected between a first output of
said instruction decoder and said first unit, an additional unit (5)
to be controlled, and a strobing generation circuit (4) connected
to a second output of said instruction decoder for controlling said
additional unit, said additional unit having respective inputs
connected to a strobing signal output of said strobing generation
circuit and one of said first and second outputs of said instruction
decoder. 4. A system
according to claim 3, wherein said strobing generation circuit (4)
has an inhibiting signal output (10) connected to an input of said
main register (2) for inhibiting the storage in said main register of
signals received from said first output of said instruction
decoder. 5. A system according
to claim 3, wherein said strobing generation circuit (4) includes an
internal decoder (12), an internal register (14) and an adding gate
(25), said internal decoder having outputs (13,15,16,17,18)
connected to said internal register, said internal register having
outputs (19-22) connected to said additional unit (5) and to said
adding gate, said adding gate providing said inhibiting signal
output (10) both to said main register (2) and to an inhibit input
of said internal register.
Description:
This
invention relates to a method and a system making it possible to
increase the number of instructions transmitted in systems of remote
control of television or radio receivers, and the like.
One of
the
known remote control systems is a system based on integrated
circuits of the firm ITT. Similarly as in other systems, the
instructions transmitted remotely are coded by a transmitter, for
instance SAA1024, in an electric signal modulating a wave being able to
propagate in the environment. In the receiver for instance SAA
1130, the coded electric signal is received and gives at its outputs
the completely decoded output information signal and decoded output
control signals.
In known application notes of the firm ITT
the decoded output control signals control directly the receiving
devices SAA1021, SAA1020. The decoder of information transmits also
other decoded control signals, for instance analog adjustment
signals, turning a signal on the power supply, and other signals
necessary for the operation of the system. A certain part of the
total number of instructions transmitted in the coded input signal
constitutes a group of additional instructions for decoding by an
additional instructions decoder controlled by the output signal.
The
method of increasing the number of instructions transmitted in
digital systems, i.a. in remote control systems of television
receivers, according to the invention comprises transmitting in the
control signal additional instructions which, on being decoded in an
instruction decoder and after processing in a circuit for generating
strobing signals, strobe the operation of additional controlled
devices and control the transmission of the control signal through a
register to main controlled units. In the system according to the
invention two variants of operation of the system are distinguished.
In the first variant an inhibiting signal coming out of the strobing
signal generation circuit enables storage by the register of the
real values being decoded, the output control signals, and controls
with a suitable signal the main controlled units, while blocking by
another suitable signal the additional controlled devices. In the
second variant of the method according to the invention, after
transmission of the additional instruction in the input signal, the
storage inhibiting signal inhibits the register which stores the
previous instruction and interruptedly controls the controlled unit,
whereby simultaneously another strobing signal enables the
additional controlled units to receive the controlling instruction.
In the system according to the invention the controlling of
additional units is performed in the course of uninterrupted
operation of controlled units.
In the system for increasing
the number of instructions transmitted in digital systems, i.a. in
remote control systems of television receivers, according to the
invention, between one output of the instruction decoder and first
controlled units a register is connected, having an additional input
for a recording inhibiting signal, whereas to another output of the
instruction decoder a strobing signal generation circuit is
connected for controlling additional controlled units.
The
inputs of the additional controlled units are connected with any
outputs of the instruction decoder and with outputs of a register of
the strobing circuit. The register and the strobing generation
circuit, employed in the system according to the invention, can be
built-in in one integrated circuit or may be made in the form of
separate integrated circuits.
Referring to the aforementioned
system of the firm ITT, the list of instructions thereof comprises
10 instructions used for basic servicing of the television
receivers, 16 instructions for program se
lection
and 5 additional instructions. In the method according to the
invention, by using all the additional instructions, additionally 5×16
instructions are obtained. The number of all useful instructions in
the method according to the invention amounts to 10+16+5×16=106
instructions, and thus by 75 instructions more than it was foreseen by
the manufacturer of said systems.
Employing of the method
and the system in a simple constructional arrangement enables one to
multiply the number of transmitted signals, and simultaneously the
number of units to be controlled. With reference to the system of the
firm ITT, based on integrated circuits SAA1024, SAA1130, SAA1021,
SAA1020, this enables one to employ additionally a teletext, a time
programmer, an electronic watch, remote control of a radio receiver,
tuning of a second head to observe another program, and other uses
that were not possible and not foreseen by the manufacturer of said
circuits.
The method and system according to the invention
will be now described by means of an exemplary embodiment with
reference to the accompanying drawing, wherein:
FIG. 1 is the block diagram of the system, and
FIG. 2 is the connection diagram of the strobing circuit.
The
system of an instruction invention consists of the decoder 1, one
output of which is connected through a register 2 with units 3 to be
controlled. Another output of the instruction decoder 1 is connected
with a strobing signal generation system 4 to the output of which
is connected an additional controlled unit 5 having inputs connected
with either output of the decoder 1.
The strobing circuit 4
is equipped with a decoder 12 an output 13 of which is connected
with the clearing input of a register 14, and outputs 15, 16, 17, 18
of which are connected with the recording inputs of the register
14. The registers outputs 19, 20, 21, and 22, however, are connected
with the additional unit 5 (FIG. 1) and with an adding gate 23, the
output 10 of which is connected with the record inhibiting input of
the register 14 and with the record inhibiting input of the
register 2.
In the method according to the invention, the
control signal 6 received by the instruction decoder 1 is decoded
into groups of instructions 7 and 8. The instructions 8 after being
processed in the strobing signal generating circuit 4 strobe the
operation of additional devices 5 in the form of a signal 9, and in
the form of the inhibiting signal 10 they control the operation of
the register 2. A part of instructions 8, after processing in the
strobbing circuit 4, enables with the signal 10 the transmission of
the instructions 7 through the reg
ister
2 to the controlled units 3 in the form of the decoded control
signal 11. Simultaneously, the decoded instruction 8 blocks with the
strobing signal 9 the receiving of instructions 7 or 8 by the
additional units 5 to be controlled. After transmitting the additional
information from the second part of the instructions 8 in the
signal 6, the instruction 8 after processing in the strobing signal
generating circuit 4 blocks with the signal 10 the register 2, which
stores the previous signal 7 and uninterruptedly controls the units
3 to be controlled, and simultaneously enables the additional
controlled units 5 to receive instructions 7 or 8. The transmission
of an erasing instruction in the signal 6 causes the return to the
previous way of transmission and the turning off of the additional
units 5.
The controlling of additional units 5 in the method
according to the invention by means of the signal 7 or 8 is
performed in the course of uninterrupted controlling of the units 3
by means of the signal 11 from the register 2.
- VIDEO CHROMA PROCESSING WITH TDA3300 (MOTOROLA)
TDA3300 3301 TV COLOR PROCESSOR
This device will accept a PAL or NTSC composite video signal and output the
three color signals, needing only a simple driver amplifier to interface to the pic-
ture tube. The provision of high bandwidth on-screen display inputs makes it
suitable for text display, TV games, cameras, etc. The TDA3301 B has user con»
trol laws, and also a phase shift control which operates in PAL, as well as NTSC.
0 Automatic Black Level Setup
0 Beam Current Limiting
0 Uses Inexpensive 4.43 MHZ to 3.58 MHz Crystal
0 No Oscillator Adjustment Required
0 Three OSD Inputs Plus Fast Blanking Input
0 Four DC, High Impedance User Controls
0 lnterlaces with TDA33030B SECAM Adaptor
0 Single 12 V Supply
0 Low Dissipation, Typically 600 mW
The brilliance control operates by adding a pedestal to the output
signals. The amplitude of the pedestal is controlled by Pin 30.
During CRT beam current sampling a standard pedestal is
substituted, its value being equivalent tothe value given by V30 Nom
Brightness at black level with V30 Nom is given by the sum of three gun
currents at the sampling level, i.e. 3x20 |.1A with 100 k reference
resistors on Pins 16, 19, and 22.
During picture blanking the brilliance pedestal is zero; therefore, the
output voltage during blanking is always the minimum brilliance black
level (Note: Signal channels are also gain blanked).
Chrominance Decoder
The chrominance decoder section of the TDA3301 B
consists of the following blocks:
Phase-locked reference oscillator;
Phase-locked 90 degree servo loop;
U and V axis decoders
ACC detector and identification detector; .
Identification circuits and PAL bistable; .
Color difference filters and matrixes with fast blanking
Circuits.
The major design considerations apart from optimum
performance were:
o A minimum number of factory adjustments,
o A minimum number of external components,
0 Compatibility with SECAM adapter TDA3030B,
0 Low dissipation,
0 Use of a standard 4.433618 Mhz crystal rather
than a 2.0 fc crystal with a divider.
The crystal VCO is of the phase shift variety in which the
frequency is controlled by varying the phase of the feedback.
A great deal of care was taken to ensure that the oscillator loop
gain and the crystal loading impedance were held constant in
order to ensure that the circuit functions well with low grade
crystal (crystals having high magnitude spurious responses
can cause bad phase jitter). lt is also necessary to ensure that
the gain at third harmonic is low enough to ensure absence of
oscillation at this frequency.
It can be seen that the
necessary 1 45°C phase shift is obtained by variable addition
ol two currents I1 and I2 which are then fed into the load
resistance of the crystal tuned circuit R1. Feedback is taken
from the crystal load capacitance which gives a voltage of VF
lagging the crystal current by 90°.
The RC network in the T1 collector causes I1 to lag the
collector current of T1 by 45°.
For SECAM operation, the currents I1 and I2 are added
together in a fixed ratio giving a frequency close to nominal.
When decoding PAL there are two departures from normal
chroma reference regeneration practice:
a) The loop is locked to the burst entering from the PAL
delay line matrix U channel and hence there is no
alternating component. A small improvement in signal
noise ratio is gained but more important is that the loop
filter is not compromised by the 7.8 kHz component
normally required at this point for PAL identification
b) The H/2 switching of the oscillator phase is carried out
before the phase detector. This implies any error signal
from the phase detector is a signal at 7.8 kHz and not dc.
A commutator at the phase detector output also driven
from the PAL bistable coverts this ac signal to a dc prior
to the loop filter. The purpose ot this is that constant
offsets in the phase detector are converted by the
commutator to a signal at 7.8 kHz which is integrated to
zero and does not give a phase error.
When used for decoding NTSC the bistable is inhibited, and
slightly less accurate phasing is achieved; however, as a hue
control is used on NTSC this cannot be considered to be a
serious disadvantage.
90° Reference Generation
To generate the U axis reference a variable all-pass network
is utilized in a servo loop. The output of the all-pass network
is compared with the oscillator output with a phase detector of
which the output is filtered and corrects the operating point of
the variable all»pass network .
As with the reference loop the oscillator signal is taken after
the H/2 phase switch and a commutator inserted before the
filter so that constant phase detector errors are cancelled.
For SECAM operation the loop filter is grounded causing
near zero phase shift so that the two synchronous detectors
work in phase and not in quadralure.
The use of a 4.4 MHz oscillator and a servo loop to generate
the required 90° reference signal allows the use of a standard,
high volume, low cost crystal and gives an extremely accurate
90° which may be easily switched to 0° for decoding AM
SECAM generated by the TDA3030B adapter.
ACC and Identification Detectors
During burst gate time the output components of the U and
also the V demodulators are steered into PNP emitters. One
collector current of each PNP pair is mirrored and balanced
against its twin giving push-pull current sources for driving the
ACC and the identification filter capacitors.
The identification detector is given an internal offset by
making the NPN current mirror emitter resistors unequal. The
resistors are offset by 5% such that the identification detector
pulls up on its filter capacitor with zero signal.
Identification
See Figure 11 for definitions.
Monochrome I1 > I2
PAL ldent. OK I1 < lg
PAL ldent_ X l1 > I2
NTSC I3 > I2
Only for correctly identified PAL signal is the capacitor
voltage held low since I2 is then greater than I1.
For monochrome and incorrectly identified PAL signals l1>l2
hence voltage VC rises with each burst gate pulse.
When V,ef1 is exceeded by 0.7 V Latch 1 is made to conduct
which increases the rate of voltage rise on C. Maximum
current is limited by R1.
When Vref2 is exceeded by 0.7 V then Latch 2 is made to
conduct until C is completely discharged and the current drops
to a value insufficient to hold on Latch 2.
As Latch 2 turns on Latch 1 must turn off.
Latch 2 turning on gives extra trigger pulse to bistable to
correct identification.
The inhibit line on Latch 2 restricts its conduction to alternate
lines as controlled by the bistable. This function allows the
SECAM switching line to inhibit the bistable operation by firing
Latch 2 in the correct phase for SECAM. For NTSC, Latch 2
is fired by a current injected on Pin 6.
lf the voltage on C is greater than 1.4 V, then the saturation
is held down. Only for SECAM/NTSC with Latch 2 on, or
correctly identified PAL, can the saturation control be
anywhere but minimum.
NTSC Switch
NTSC operation is selected when current (I3) is injected into
Pin 6. On the TDA33O1 B this current must be derived
externally by connecting Pin 6 to +12 V via a 27 k resistor (as
on TDA33OOB). For normal PAL operation Pin 40 should be
connected to +12 V and Pin 6 to the filter capacitor.
4 Color Difference Matrixing, Color Killing,
and Chroma Blanking
During picture time the two demodulators feed simple RC
filters with emitter follower outputs. Color killing and blanking
is performed by lifting these outputs to a voltage above the
maximum value that the color difference signal could supply.
The color difference matrixing is performed by two
differential amplifiers, each with one side split to give the
correct values of the -(B-Y) and -(Ft-Y) signals. These are
added to give the (G-Y) signal.
The three color difference signals are then taken to the
virtual grounds of the video output stages together with
luminance signal.
Sandcastle Selection
The TDA3301B may be used with a two level sandcastle
and a separate frame pulse to Pin 28, or with only a three level
(super) sandcastle. In the latter case, a resistor of 1.0 MQ is
necessary from + 12 V to Pin 28 and a 70 pF capacitor from
Pin 28 to ground.
Timing Counter for Sample Control
In order to control beam current sampling at the beginning
of each frame scan, two edge triggered flip-flops are used.
The output K ofthe first flip-flop A is used to clock the second
tlip-flop B. Clocking of A by the burst gate is inhibited by a count
of A.B.
The count sequence can only be initiated by the trailing
edge of the frame pulse. ln order to provide control signals for:
Luma/Chroma blanking
Beam current sampling
On-screen display blanking
Brilliance control
The appropriate flip-flop outputs ar matrixed with sandcastle
and frame signals by an emitter-follower matrix.
Video Output Sections
Each video output stage consists of a feedback amplifier in A further drive current is used to control the DC operating
which the input signal is a current drive to the virtual earth from point; this is derived from the sample and hold stage which
the luminance, color difference and on-screen display stages. samples the beam current after frame flyback.
BU208(A)
Silicon NPN
npn transistors,pnp transistors,transistors
Category: NPN Transistor, Transistor
MHz: <1 MHz
Amps: 5A
Volts: 1500V
HIGH VOLTAGE CAPABILITY
JEDEC TO-3 METAL CASE.
DESCRIPTION
The BU208A, BU508A and BU508AFI are
manufactured using Multiepitaxial Mesa
technology for cost-effective high performance
and use a Hollow Emitter structure to enhance
switching speeds.
APPLICATIONS:
* HORIZONTAL DEFLECTION FOR COLOUR TV With 110° or even 90° degree of deflection angle.
ABSOLUTE MAXIMUM RATINGS
Symbol Parameter Value Unit
VCES Collector-Emit ter Voltage (VBE = 0) 1500 V
VCEO Collector-Emit ter Voltage (IB = 0) 700 V
VEBO Emitter-Base Voltage (IC = 0) 10 V
IC Collector Current 8 A
ICM Collector Peak Current (tp < 5 ms) 15 A
TO - 3 TO - 218 ISOWATT218
Ptot Total Dissipation at Tc = 25 oC 150 125 50 W
Tstg Storage Temperature -65 to 175 -65 to 150 -65 to 150 oC
Tj Max. Operating Junction Temperature 175 150 150 °C
NORDMENDE SPECTRA SK3-COLOR T3137 CHASSIS F9 (492.445) Switching regulator
power supply device combined with the horizontal deflection circuit of a
television receiver which it supplies
Step-up
switching regulator power supply device comprising, connected between
the poles of a rectifier circuit supplied by an isolating voltage
step-down transformer and loaded by a first filter capacitor, and
inductance and the collector-emitter path of a first switching
transistor of NPN type, a first diode whose anode is connected to the
junction of the inductance and to the collector of said transistor and
whose cathode is connected to a second filter and storage capacitor
supplying a voltage at its output which supplies a horizontal deflection
circuit of a television receiver.
This horizontal deflection
circuit which comprises in cascade a horizontal oscillator, a driver
stage and an output stage, forms an integral part of the circuit
controlling said first transistor and determines the repetition period
of the switching, because it is started under an initial voltage
slightly less than the unregulated input voltage of the device.
The
switching transistor is being turned off in synchronism with the
turning off of the trace switch transistor by using flyback pulses of
negative polarity to bias the base thereof.
1.
A power supply device with switching regulation and boosting of its DC
output voltage, combined with a horizontal deflection circuit of a
television receiver, supplied thereby and which comprises in cascade a
horizontal oscillator, a driver stage and an output stage including a
trace switch transistor and a line transformer, this device comprising
an inductance and the collector-emitter path of a switching transistor
connected in series between the poles of a DC input voltage source, a
rectifying diode connected by its anode to the junction between the
inductance and the collector of said switching transistor and by its
cathode to one of the terminals of a filtering and storage capacitor
whose other terminal is connected to the emitter of said transistor, so
as to apply across its terminals an initial DC voltage slightly lower
than said input voltage, when said switching transistor is turned off,
and a regulated DC output voltage with a level higher than said input
voltage, when said transistor is recurrently, alternately turned on and
off, the level of said output voltage depending on the duty cycle of
said switching transistor states, and a control circuit feeding the base
of said switching transistor and including a regulator stage comparing
an adjustable fraction of said output voltage to a fixed reference
voltage and supplying a regulating current or voltage proportional to
the difference between said compared voltages, a pulse-width modulator
triggered by means of a recurrent signal and supplying a rectangular
signal whose duty cycle varies as a function of said regulating current
or voltage, another driver stage receiving the rectangular signal and
controlling said switching transistor, the regulation and boosting of
said output voltage being controlled by the initially independent
starting up of the entire horizontal deflection circuit when supplied by
said initial voltage from said power supply device as soon as a DC
input voltage is applied thereto and which then delivers recurrent
trigger pulses to said pulse-width modulator, one of the supply inputs
of said other driver stage receiving directly a first voltage waveform
whose positive alternations comprise constant-voltage plateau and whose
negative alternations comprise negative-going horizontal flyback pulses
provided by a first secondary winding of said line transformer, so as
to control the turning off of said switching transistor substantially
simultaneously with that of the trace switch transistor.
2.
A power supply device as claimed in claim 1, wherein said other driver
circuit comprises a third transistor whose emitter is connected to the
base of said switching transistor and which is of the same type as the
latter, whose collector is connected, through said supply input, to
said first secondary winding of said line transformer to receive
therefrom said first waveform and whose base is coupled to the output
of said pulse-width modulator.
3. A power supply
device as claimed in claim 2, wherein the collector of said third
transistor is connected, through a resistor to the supply input and its
emitter is connected, furthermore, to that of the switching transistor
through another resistor so that the negative-going flyback pulses,
applied to the collector of said third transistor, control the
symmetric (reverse) saturation thereof so as to reversely bias the
base-emitter junction of said switching transistor.
4.
A power supply device as claimed in claim 2, wherein the collector of
said third transistor is connected to said power supply input through a
fourth diode conducting in the normal direction of its
collector-emitter path, and wherein its emitter is further connected,
on the one hand, through a resistor, to the emitter of the switching
transistor and, on the other hand, through another resistor and a fifth
diode conducting in the reverse direction to that of the base-emitter
junction of the switching transistor, so as to transmit to the base
thereof negative-going flyback pulses through a voltage divider formed
by said two resistors in series.
5.
A power supply device as claimed in claim 1, wherein said other driver
circuit comprises a third transistor whose emitter is connected to the
base of said switching transistor, whose collector is connected to
that of this latter so as to form a so-called Darlington circuit and
whose base coupled, moreover, to said pulse-width modulator is further
connected, through a resistor and a diode in series, to said first
secondary winding of said line transformer so as to control the
simultaneous turn off of both transistors of said Darlington circuit by
simultaneously reversely biasing their respective base-emitter
junctions, connected in series, by means of negative-going flyback
pulses.
6.
A power supply device as claimed in any one of the preceding claims,
wherein said pulse-width modulator, supplied at its input with a
voltage waveform whose positive alternations comprise positive-going
flyback pulses and whose negative alternations comprise constant
negative-voltage plateaux, comprises a passive circuit which forms a
simple integrator during positive alternations because one of its
resistors is shunted by a diode and which is a cascaded double
integrator during negative alternations of this waveform so as to
deliver during the trace periods of the scan a linearly decreasing
negative current which, added to the positive regulating current,
supplies the base of a fourth comparator transistor, so that the turning
off of this latter through equality of the negative and positive
currents supplied to this base controls the beginnings of the saturation
of said switching transistor in such a manner that the duration of
this saturation varies inversely with variation of said output voltage.
7.
A power supply device as claimed in claim 6, wherein said comparator
transistor is biased, furthermore, at its base by means of a resistor
which connects it to the positive pole of said input voltage source, so
that it remains saturated in the absence of flyback pulses supplied by
said horizontal deflection circuit so as to maintain the switching
transistor in a cut off state.
8. A power supply device
as claimed in any one of the preceding claims, wherein said control
circuit, except for the regulator stage which is supplied by said output
voltage, is supplied by said input voltage.
9. A
power supply device as claimed in any one of the preceding claims 1 to
6, wherein said DC supply voltage of said control circuit, with the
exception of one of the inputs of said regulator stage receiving said
output voltage, is supplied by a secondary winding of said line
transformer, through a rectifier circuit including a diode and a
filtering capacitor.
Description:
BACKGROUND OF THE INVENTION
The
present invention relates to a switching voltage regulator power
supply device combined with the horizontal deflection circuit of a
television receiver which it supplies with DC voltage. It relates, more
particularly, to DC voltage supply devices of the type which boost or
increase the voltage supplied at the output of the device in relation
to the level of a DC voltage applied to its input and which regulate
this level by recurrent switching of this input voltage, this switching
being synchronous with the (horizontal) line frequency of the
television receiver supplied by this device.
Switched step-up or
boost voltage regulator devices of this type are known, particularly
from the publications U.S. Pat. Nos. 3,571,697 (or 3,736,496) and they
are related to switched mode power supply devices or DC-DC converters
of the so-called unisolated flyback type, in which the
collector-emitter path of a bipolar switching transistor is connected
in series with a commutating inductance between the terminals of a DC
source supplying an input voltage and a rectifying diode is connected
between the junction of the inductance with the transistor and one of
the plates of a filtering or storage capacitor (in parallel with the
load), so that the current stored in the inductance during the
conducting period of the transistor is used for charging the capacitor
(and supplying the load) through the diode during its consecutive
cut-off period. The use of a switched-mode power supply device of this
type in television receivers for supplying, particularly, the
horizontal deflection circuit thereof has been described, for example,
in two articles by VAN SCHAIK entitled respectively "AN INTRODUCTION TO
SWITCHED-MODE POWER SUPPLIES IN TV RECEIVERS" and "CONTROL CIRCUITS
FOR SMPS IN TV RECEIVERS," appearing respectively on pages 93 to 108 of
No. 3, Vol. 34, of September 1976 and on pages 162 to 180 of No. 4 of
this same volume, of December 1976, in the English language Dutch
review "ELECTRONIC APPLICATIONS BULLETIN" of PHILIPS', or on pages 181
to 195 of No. 135 of July 1977 and on pages 210 to 226 of No. 136 of
October 1977 of the British review "MULLARD TECHNICAL COMMUNICATIONS."
Since none of the switched-mode power supply devices described in these
articles, isolated or not from the mains, whether they use a forward
or a flyback converter, supplies at its output a DC voltage for
supplying the horizontal deflection circuit before the switching
transistor has been turned on (saturated or conducting) one or more
times, the control circuit of this transistor must comprise an
independent relaxation oscillator and must be supplied by the same DC
input voltage (rectified and smoothed voltage of the AC mains) as the
switching circuit comprising the inductance and the transistor in
series. Synchronization of the switching with the horizontal deflection
can only occur subsequently, when the horizontal oscillator and/or the
horizontal deflection circuit as a whole have begun to operate, as
soon as the supply voltage supplied thereto by the device which
operates independently on starting up, has become sufficient. This
synchronization of the switching with the horizontal deflection,
advantageous for reducing or eliminating the interferences visible on
the screen which are caused by high-frequency energy radiation due to
abrupt transitions of power switching, particularly when the switching
transistor is being cutt off, is generally carried out by means of a
signal comprising flyback or retrace pulses, taken at the terminals of
an auxiliary secondary winding of the line tranformer whose primary
winding is generally connected between the output of the switched-mode
power supply device and one of the terminals of the trace switch which
is provided in the output stage. It is also possible to use for this
purpose the signal provided by the horizontal oscillator (see, for
example, the publication FR-A-2 040 217).
In
a switched-mode supply for a television receiver described in the
publication FR-A-2 261 670, the circuit for controlling the switching
transistor of a forward-type converter, supplied with the rectified and
smoothed voltage of the mains, comprises a bistable trigger circuit of
flip-flop one of whose outputs is coupled back to one of its trigger
inputs through a regulating circuit comprising a sawtooth voltage
generator and a voltage comparator providing transitions which control
the setting of the flip-flop, when the sawtooth voltage reaches the
level of a voltage proportional to the amplitude of the flyback pulse.
The other one of the two complementary outputs of this flip-flop is
coupled back to its other trigger input through a so-called starting
loop comprising an ascending voltage wave-form which approaches
asymptotically a predetermined voltage level smaller than a
predetermined fraction of the nominal level which the amplitude of the
flyback pulse must reach in normal operation, and a voltage comparator
providing transitions which control the recurrent resetting of the
flip-flop to its initial state until the flyback pulse has reached or
exceeded a threshold amplitude slightly below its nominal amplitude.
When this threshold amplitude has been exceeded, resetting of the
flip-flop is controlled by the flyback pulses themselves, negative-going
in the present case, which supplant the starting pulses. Such an
arrangement is equivalent to an astable multivibrator during the
starting period, which later becomes a monostable one and triggered by
the flyback pulses and whose quasi-stable state has a variable duration,
depending on the amplitude of these pulses so as to obtain regulation
thereof by the duty cycle. The pulse which controls the closing of the
switch (saturation of the switching transistor) begins here with the
leading edge of the flyback pulse and its duration or length is
modulated as a function of the current drawn by the load and of the
variation of the rectified and smoothed voltage, so that its end
controlling the opening of the supply switch (cutting off the
transistor) occurs during the trace portion of the horizontal
deflection. Thus it can be seen that this switched-mode supply, like
most of the known ones, effects regulation of its output voltage by
varying the duty cycle as a reverse function of the level thereof.
Since
the high-frequency radiation is precisely at its most intense during
abrupt transitions of current in the switching inductance and of the
voltage accross its terminals, the appearance of one or more vertical
lines (light or dark according to the sense of the modulation of the
carrier wave by the video signal) may be observed, contrasting with the
normal contents of the picture, whose location on the screen depends on
the duration of the pulse controlling the switching transistor. The
effect of this radiation becomes particularly troublesome when the input
signal of the radio-frequency stages or tuner is small, particularly
when the selected channel is situated in the lower part of the VHF band,
for the automatic gain-control device of the receiver acts on the gain
of the high-frequency and/or intermediate-frequency input stages, so
that the sensitivity (amplification) of the receiver is then maximum and
this also as concerns the spurious radiated signals.
SUMMARY OF THE INVENTION
The
present invention, on the one hand, avoids or at least appreciably
reduces the interferences visible on the screen by controlling the
cutting off of the switching transistor in synchronism with the leading
edge or the flyback pulse and, on the other hand, the starting of the
horizontal deflection circuit by means of a simple circuit without any
special oscillator, and provides efficient protection of the switching
transistor which remains cut off when the horizontal deflection circuit
is not operating. This is made possible by using a step-up switching
regulator supply device of the type described in the publication U.S.
Pat. No. 3,571,697 and whose control circuit includes, in accordance
with the invention, the horizontal deflection circuit, which it
supplies.
The object of the present invention is a power supply
device with boosting and regulation of its output voltage by switching,
combined with a horizontal sweep circuit of a television receiver,
which it supplies and which comprises a horizontal oscillator, a driver
stage and an output stage including a line transformer, this device
comprising an inductance and the collector-emitter path of a switching
transistor connected in series between the poles of a DC input voltage
source, a rectifiying diode connected by its anode to the junction
between the inductance and the collector of the transistor and by its
cathode to one of the terminals of a filtering capacitor whose other
terminal is connected to the emitter of the transistor so as to supply
between its terminals an initial output voltage, slightly lower than the
input voltage, when the transistor is cut off permanently, and a
regulated DC output voltage with a level higher than the input voltage,
when the transistor is recurrently alternately turned on and off, the
level of this output voltage depending on the duty cycle of the
respective states of this transistor, and a control circuit for driving
the base of the transistor and including a regulator stage comparing an
adjustable fraction of the output voltage to a fixed reference voltage
and supplying a regulating current or voltage proportional to the
difference between these compared voltages, to a pulse-width modulator
triggered by means a recurrent signal and supplying a rectangular signal
whose duty cycle varies as a function of this regulating current or
voltage, and another driver stage receiving the rectangular signal and
controlling the switching transistor.
In
accordance with the invention, the horizontal deflection forming an
integral part of the circuit controlling the switching transistor,
determines therefor, from the start, the repetition period of the
rectangular signal controlling it, and one of the supply inputs of the
other driver stage receives directly a first voltage waveform whose
positive alternations, comprise DC voltage plateaux and whose negative
alternations comprise negative-going flyback pulses supplied by a first
secondary winding of the line transformer, so as to control the
cut-off the switching transistor substantially simultaneously with that
of the trace switch transistor.
DESCRIPTION OF THE DRAWINGS
The
invention will be better understood and other of its objects,
characteristics, features and advantages will become clear from the
following description and the accompanying drawings which refer thereto,
given solely by way of example, in which:
FIG. 1 is partly a
block diagram and partly a schematic diagram of a power supply device
combined with the horizontal deflection circuit in accordance with the
invention;
FIG. 2 shows waveforms of two voltages and of a current at different points of the circuit of FIG. 1;
FIG. 3 is a block diagram of the circuit for controlling the switching transistor;
FIGS.
4 and 5 are schematic diagrams of two different embodiments of the
driver circuit 20 forming the output stage of the control circuit of
FIG. 3;
FIG. 6 is the block diagram of one embodiment of the pulse-width modulator 10 of the circuit of FIG. 3;
FIG. 7 shows three voltage waveforms at different points of the circuit of FIG. 6;
FIG.
8 is a schematic diagram of one embodiment of the pulse-width
modulator 10 of the circuit of FIG. 3, using discrete components;
FIG. 9 shows a current waveform and two voltage waveforms at different points of the circuit of FIG. 8;
FIG.
10 is a schematic diagram of a conventional embodiment of a regulator
stage 30 adapted to supply the modulation input of the modulator of
FIG. 8; and
FIGS. 11 and 12 are partial respective schematic
diagrams of two embodiments of a power supply device in accordance with
the invention.
DESCRIPTION OF THE PREFERRED EMBODIMENTS
FIG.
1 shows the schematic diagram of the power stages of the power supply
device and of the horizontal deflection circuit of the television
receiver, which it supplies and in block diagram form the respective
circuits which control them.
The DC input voltage VE which is
not regulated is supplied by a rectifier bridge R with four diodes,
supplied at its input by the secondary winding of an insulating
step-down transformer TS, whose primary winding is supplied by the AC
mains. The output terminals of rectifier bridge R are connected
respectively to the terminals of a first filtering capacitor C1 across
which this input voltage VE is taken.
The positive pole P of
this source of the input voltage VE is connected to one of the terminals
of an energy-storage inductance L, whereas its negative pole N is
connected to ground G of the receiver, which is isolated from the mains.
The other terminal of inductance L is connected, on the one hand, to
the collector of a first NPN bipolar switching transistor T1, whose
emitter is connected to ground G and, on the other hand, to the anode of
a first diode D1 whose cathode is connected to the positive terminal
of a second filtering and storage capacitor C2. With the negative
terminal of this second capacitor C2 connected to ground G, the output
voltage VS which supplies the load is taken between its terminals.
Such
a supply device BS provides both step-up or boost and regulation of
its output voltage level, because the first switching transistor T1 and
the first diode D1 thereof are connected so as to conduct respectively
currents flowing through inductance L in the same direction, it
supplies at its output formed by the terminals of the second capacitor
C2, an initial DC voltage VSI as soon as the primary winding of the
insulating transformer TS is connected to the mains. This initial
voltage VSI which is equal to the input voltage VE less the forward
voltage drop VD1 across the first diode D1, is then supplied to the
load until the control circuit SC is started up, whose output 6 is
connected to the base of the first transistor T1 so as to cause it to
be alternately turned on and off.
When the first transistor T1
is turned on by positively biasing its base-emitter junction, its
collector-emitter path connects the junction of the inductance L with
the anode of the first diode D1 to ground G. Diode D1 being then
reversely biased, it ceases to conduct and the inductance L connected
by the first transistor T1 between the positive P and negative N poles
of the source supplying the unregulated DC input voltage VE, then
conducts a linearly increasing current IL so as to store the energy
which increases with the square of the conduction duration of the first
transistor T1, until this latter is cut off. At the instant when the
first transistor T1 is cut off after the control circuit SC has brought
its base-emitter voltage to zero or below, the voltage at the
terminals of inductance L is reversed so that, at its junction with the
collector of transistor T1 and the anode of diode D1, there appears a
voltage VM greater than the input voltage VE, which results in the
forward biasing of diode D1. Consequently, from the instant when
transistor T1 is cut off, diode D1 conducts a linearly decreasing
current until the energy stored in the form of a current IL in the
inductance L, which charges the second capacitor C2 to an output
voltage VS greater than the input voltage VE, disappears. The regulation
of the level of the output voltage VS is here effected in a
conventional way, by varying the duty cycle, i.e. the radio (quotient)
between the duration of the conducting period of transistor T1 and the
sum of the respective durations of two of its successive conducting and
cut off periods, as a function of the desired output voltage VS
(determined by comparison to a stable reference voltage).
According
to the invention, a supply device BS of the above-described type is
combined with the horizontal deflection circuit SH of a television
receiver, which it supplies, so that this latter forms an integral part
of its control circuit SC and for determining the repetition period of
its operation and so that the above-mentioned regulation by varying the
duty cycle maintains a stable peak-to-peak amplitude of the sawtooth
scanning current and/or the very high voltage for biasing the electrodes
(anode, focusing electrode and accelerating grid) of the cathode-ray
tube, which are obtained by rectifying the horizontal flyback pulses
supplied by a step-up secondary winding (not shown) of the line
transformer TL.
The horizontal deflection circuit SH which
comprises in cascade the horizontal oscillator OH whose known phase
control circuit with respect to the horizontal sync signal separated
from the composite video signal has not been shown here, the driver
stage HD controlled by the horizontal oscillator OH and controlling the
output stage OS of the horizontal deflection, is as a whole supplied by
the above-described regulated power supply device BS. In fact, the
positive supply input AL of the horizontal deflection circuit SH is
connected by means of a fuse FS to the junction of the cathode of the
first diode D1 with the positive terminal of the second capacitor C2,
which forms the positive output terminal SP of the regulated power
supply device BS. This supply input AL is connected directly to that of
the driver circuit HD and, preferably, through a conventional Zener
diode or series ballast transistor voltage regulator VR, to that of the
horizontal oscillator OH, which are moreover connected to the isolated
ground G.
The supply input AL of the horizontal deflection
circuit SH is furthermore connected to one of the primary winding
terminals B1 of the line transformer TL, whose other terminal AB is
connected in parallel to the collector of another switching transistor
TH, of NPN type, called trace switch transistor, to the cathode of a
second so-called shunt recovery diode DR, to one of the terminals of
another capacitor CR, called line-retrace capacitor, and to one of the
plates of an additional capacitor CS, called trace capacitor, which
supplies the horizontal deflection coils LH one terminal of which is
connected to its other terminal during the trace periods of the
scanning. The emitter of the scanning transistor TH, the anode of the
"shunt" recovery diode DR, the other terminal of the retrace capacitor
CR and the other terminal of the horizontal deflection coils LH are all
connected to ground G. This assembly of components thus connected forms
the output stage OS whose operation is well-known and does not form
part of the invention.
As
was mentioned above, as soon as the primary winding of the step-down
isolating transformer TS is connected to the mains, rectifier R
supplies the first filtering capacitor C1 so as to provide between its
terminals P and N a unregulated low DC voltage VE. With the first
transistor T1 then turned off, this input voltage is applied through
the inductance L and the first diode D1 to the second capacitor C2 so
as to obtain between the terminal SP and ground G an initial output
voltage VSI substantially equal to VE-VD1, which is approximately equal
to 60 percent of the regulated output voltage VS. This initial output
voltage VSI (equal to about 0.6 VS) is sufficient to cause the
generation of autonomous oscillations by the horizontal oscillator OH.
This latter supplies at its output, connected to the input of driver
circuit HD, pulses at an independent frequency close to the line
frequency. In response to these pulses, driver circuit HD, also
supplied by device BS, provides at the base of the trace switch
transistor TH pulses controlling its periodical cut off at this
independent frequency and its consecutive turning on after a period
greater than the duration of the flyback period, so that the recovery
diode DR may take the current from the deflector LH during substantially
the first half of the trace portion of the scan. During flyback or
retrace, with both transistor TH and diode DR cut off, the energy stored
in the form of currents respectively in the inductances of deflector
LH and of the primary winding B1 of the line transformer TL which are
then, from the AC current point of view, connected in parallel, flow in
an oscillating manner through the retrace capacitor CR which forms
therewith a parallel resonant circuit whose resonance period determines
the duration of the flyback period.
There then appears
periodically between point AB and ground G a voltage pulse VTH having
substantially a sinusoidal half-wave form, which is shown in Diagram A
of FIG. 2. The average value of this voltage VTH being then equal to
VSI, at start-up, and to VS, during established operation. The line
transformer TL comprises, in addition to a very-high-voltage winding and
other windings for supplying rectifying circuits, not shown, two
secondary windings B2, B3 respectively supplying across their terminals,
voltage waveforms comprising flyback pulses with zero average values
and with respectively negative and positive polarities.
This
means that the first secondary winding B2 supplies a voltage waveform
-VTL which, between two successive flyback pulses, comprises a positive
plateau whose level is equal to the average value of these pulses and
which is used, in accordance with the invention, to control the turn off
of the first transistor T1 so that the interferences which would
otherwise be visible only occur during the line-blanking periods
comprising the line-retrace periods. The second secondary winding B3
then supplies a voltage waveform +VTL which is the reverse of or
complementary to the preceding one -VTL.
One of the terminals of
each of these secondary windings B2, B3 is connected to ground G,
whereas their other terminals are respectively connected to two inputs 2
and 1 of the control circuit SC. A third input 3 of this latter is
connected to the SP output of the supply device BS and a fourth input 4
is connected to the positive pole P of the input voltage source VE. A
fifth terminal 5 of the control circuit SC is connected to ground G (or
negative pole N) and its output 6 is connected to the base of the first
transistor T1. This control circuit SC causes, following the start up
of the horizontal deflection circuit SH, a first saturation of the
first transistor T1 at a time determined by a pulse-width modulator
operating by conventional comparison of a sawtooth voltage waveform the
elaboration of which is controlled by a first flyback pulse, with a
regulating voltage, depending on the output voltage VS. During this
saturation period of transistor T1 which extends as far as the leading
edge of the next flyback pulse, energy is stored in inductance L.
From
the instant when transistor T1 is turned off, diode D1 transfers this
stored energy to the second capacitor C2, at the terminals of which it
causes an increase of the voltage VS with respect to its initial value
VSI, until the current in diode D1 is canceled out, when it becomes
reverse biased.
The collector-emitter voltage waveforms VTH of
the trace switch transistor TH and VCE of the switching transistor T1 in
established operation have been shown respectively by the diagrams A
and B of FIG. 2. Diagram C of FIG. 2 shows the corresponding waveform of
the current IL flowing through the inductance L.
When the base
of the first transistor T1 receives from the output 6 of the control
circuit SC a rectangular signal which turns it on at time instant t1,
its collector-emitter voltage VCE (Diagram B) becomes close to zero (V
CEsat )
and a linearly increasing current IL (Diagram C) flows through
inductance L from time t1 until time t2 when transistor T1 is again
turned off, which is controlled by the leading edge of the flyback pulse
VTH (Diagram A). With the collector current of transistor T1 canceled
at the end of the storage time of the excess minority carriers in the
base, the voltage across the terminals of the inductance L inverses its
polarity so as to be added to the input voltage VE, so that the
collector-emitter voltage VCE (Diagram B) then reaches a level VM
greater than VS (as well as VE), so as to apply forward bias to the
first diode D1, which then conducts the current IL through the
inductance L. This current IL, from time instant t2 when it reaches its
maximum value IM, becomes linearly decreasing and it flows through the
first diode D1 in the passing direction in order to recharge the second
capacitor C2 and supply, in particular, the horizontal deflection
circuit SH.
When the current IL passing through the first diode
D1 is canceled out at time t3, the collector-emitter voltage VCE of the
first transistor T1 becomes equal to the unregulated input voltage VE
until the next turn on of the transistor T1, and the first diode D1
remains reversely biased until the time when this latter is cut off
again.
From the above it can be easily seen that the principal
advantage of this combined device resides in the fact that a single
oscillator OH belonging to the horizontal deflection circuit SH is
sufficient for controlling the two power switching transistors TH and
T1.
Furthermore, a possible overload in the circuitry of the
television receiver, such for example as a short-circuit of the trace
switch transistor TH, results in overloading the diode D and the
inductance L. The first transistor T1 which is consequently cut off is
not subjected to this overload and is therefore protected. In order to
protect the rest of the television receiver as well as inductance L and
the first diode D1, a fuse FS may be connected in series in the supply
line from the second capacitor C2. This fuse FS may also be inserted
between pole P and inductance L.
It
is moreover known that it is difficult to construct switched supplies
for obtaining correct operation when it is not fully charged (for
supplying, for example, a ready-state remote-control receiver). In the
present case, the problem does not come up since, when the supply is in
operation, there is always a minimum load formed by the horizontal
deflection circuit. When this circuit is not operating, the supply
circuit BS does not operate either, but it supplies an output voltage
VSI of a value less than the nominal voltage VS which cannot cause
damage and which may, for example, supply a ready-state receiver for
television receivers having a remote control.
Finally, the
control circuit SC allows transistor T1 to be cut off at the beginning
of each flyback period, when the blanking circuit has extinguished the
spot (s) on the cathode-ray tube. Thus, the spurious signals radiated
into the receiver input circuits will cause no visible effect on the
screen of the cathode-ray tube.
FIG. 3 shows in block diagram form the control circuit SC of FIG. 1.
This
control circuit SC comprises a pulse-width modulator stage 10 a first
input 11 of which, connected to input 1, receives flyback pulses of
positive polarity +VTL from the second secondary winding B3 of the line
transformer TL (see FIG. 1 and a second input 12 of which receives a
so-called regulating voltage or current whose level is proportional to
the difference between the actual output voltage VS and a constant
reference value, delivered by the output 32 of a regulating circuit or
stage 30 whose input 31 is connected through input 3 to the positive
output pole SP of the supply device BS supplying the regulated voltage
VS. The variation of the regulating current or voltage causes the
variation of the time instant when the instantaneous amplitude of a
sawtooth voltage waveform, either with substantially constant slope and
amplitude, reaches the level of this regulating voltage, or with a
slope variable depending of the regulating current (which is added to
the current for linearly charging a capacitor), reaches the
predetermined level of a fixed reference (threshold) voltage, with
respect to the beginning or the end of the sawtooth waveform. Thus a
two-level rectangular signal with constant periodicity is generated,
whose duty cycle varies as a function of the regulating current or
voltage. If it is arranged, which is possible, for a reduction of the
output voltage VS with respect to its nominal value defined by the
reference voltage, to cause an increase in the duty cycle and for an
increase in VS to have the opposite effect, regulation of this output
voltage VS is provided, which tends to be stabilized to this nominal
value.
The output 14 of modulator 10 supplies a first input 21
of the driver stage 20 of the first switching transistor T1, a second
input 22 of which receives the flyback pulses of negative polarity
-VTL, coming from the first secondary winding B2 of the line
transformer TL.
FIGS. 4 and 5 illustrate two different
embodiments of the driver stage 20 of FIG. 3, providing efficient turn
off of the first transistor T1.
In FIG. 4, the driver stage 20A
comprises a third supply input 23 which connected to the positive pole
(P) of the source of the (unregulated) input voltage VE and to one of
the terminals of a first resistor R1 (1.8 kiloohms) whose other
terminal is connected in parallel to the anodes of two diodes D2 and D3
(of type 1N4148). The second of these diodes D3 has its cathode
connected to the base of a third NPN transistor T2 and to one of the
terminals of a second resistor R2 (220 ohms). The emitter of the third
transistor T2 is connected to the other terminal of the second resistor
R2 and to the output 24 of stage 20A, which is connected through the
output 6 of the control circuit SC to the base of the first transistor
T1. The collector of the second transistor T2 is connected through a
third resistor R3 (10 ohms) to the second input 22 of stage 20A
receiving the signal -VTL which comprises the negative-going flyback
pulses and, between them, plateaux of a constant positive level (zero
average value). The base of the first transistor T1 is coupled to its
emitter and to ground G, through a fourth resistor R4 (100 ohms). The
third transistor T2 is thus mounted as a common collector
(emitter-follower) stage.
When
the output 14 of modulator 10 (FIG. 3) which is connected to the input
21 of stage 20A supplies a low state (level), i.e. a voltage close to
zero, the thus positively biased diode D2 becomes conducting so that
its anode will be at a voltage of a few tenths of a volt (0.7+V
CEsat )
which is less than the voltage required for making the three series PN
junctions orientated in the same direction conductive, the first of
which is formed by the third diode D3, the second is the base-emitter
junction of a third transistor T2 and the third that of the first
transistor T1, which will thus remain turned off. When, on the other
hand, output 14 supplies a high state or forms an open circuit (the
output stage of modulator 10 being formed by an open-collector
transistor), diode D2 is cut off by its reverse bias and the voltage VE
applied to the input 23 causes a current to flow through the first
resistor R1, the diode D3 and the respective base-emitter junctions of
transistors T2 and T1 connected in series. Under these circumstances
and if, at the same time, the voltage waveform -VTL applied to the
collector of transistor T3 presents its constant positive level
portion, coinciding with the trace periods of the horizontal scan,
transistors T2 and T1 become simultaneously saturated with the effect
previously described insofar as the supply device BS of FIG. 1 is
concerned. On the other hand, when the voltage waveform -VTL applied to
the collector of the third transistor T2 becomes negative, during
flyback periods, the current then flows between terminals 23 and 22 of
driver stage 20 A, through resistor R1, diode D3, the base-collector
junction of the third transistor T2 and resistor R3. The third
transistor T2 then operates along its symmetrical saturation
characteristics, i.e. it is inverted so that its collector becomes
emitter and vice versa. It then conducts a current in the reverse
direction between ground and the input 22 (negative) through the
resistor R4 across the terminals of which it causes, after removal of
the excess minority carriers from the base of the first transistor T1
through the third transistor T2, a voltage drop biasing said base
negatively with respect to the emitter. This negative voltage applied to
the base of reversely saturated transistor T3 allows a considerable
reduction in the storage time and a rapid turnoff of the first
transistor T1. Since the sawtooth generator of the pulse-width modulator
10 described above is controlled by positive-going flyback pulses, the
rectangular signal applied by its output 14 (FIG. 14) to input 21 of
stage 20A undergoes, during the flyback period following the turn off of
the first transistor T1, a transition from its high state to its low
state which causes diode D2 to conduct and, consequently, the third
transistor T2 (reversed) to be cut off before the waveform -VTL becomes
positive again and rebiases this transistor T2 the right way round.
FIG.
5 shows the schematic diagram of another embodiment of the driver
circuit 20 of FIG. 3, designated by 20B, which has only been modified
with respect to circuit 20A of FIG. 4 insofar as the collector circuit
of the third transistor T2 and the base circuit of the first transistor
T1 are concerned.
This modification is more particularly
intented for the case where the negative peak amplitude of the voltage
waveform -VTL applied to the base of the first transistor T1 through
resistor R3 and the emitter-collector path of the reversely saturated
third transistor T2, exceeds the reverse (Zener) avalanche-effect
breakdown voltage of one of the base-emitter or base-collector junctions
of the first transistor T1. This may occur when the first secondary
winding B2 of the line transformer TL is also used for other functions
in the television receiver.
To prevent the third transistor T2
from being reversely saturated (symmetrically), the circuit 20B
comprises a fourth diode D4 inserted between the input 22 receiving the
voltage waveform -VTL and the collector thereof, in series with the
resistor R3 and connected to conduct in the same direction as its
collector-emitter path. The input 22 is more over connected to the
cathode of a fifth diode D5 (1N4148) whose anode is connected through a
circuit formed by a fifth resistor R5 (330 ohms) and a third capacitor
C3 (1nF) connected in parallel, to the base of the first transistor T1.
Diode D5 isolates the base of transistor T1 from the input 22,
when the waveform -VTL is positive, and connects them together through a
resistive voltage divider formed by resistors R5 and R4 in series,
when it becomes negative. Capacitor C3 accelerates the turn-off by
favoring the transmission to the base of T1 of abrupt transitions of
the negative flybacd pulses.
FIG.
6 is a diagram, partly in block form, of a possible embodiment of the
pulse-width modulator 10 of the control circuit SC of FIG. 3. Diagrams
D, E and F of FIG. 7 show the voltage waveforms applied respectively to
the input 11 (+VTL) and supplied by the output SI (VI) of the sawtooth
generator GD and by the output 14 (VP) of circuit 10A.
Modulator
10A of FIG. 5 comprises a sawtooth generator GD formed by a
conventional integrator circuit comprising a first amplifier A1
(integrated operational amplifier, for example), an integrating resistor
R1 inserted in series between the input 11 receiving the voltage
waveform +VTL illustrated by Diagram D of FIG. 7 and supplied by the
second secondary winding B3 of the line transformer TL, and the input
(inverting) of amplifier A1, as well as an interating capacitor CI
connected between this input and the output SI of amplifier A1
(capacitive feedback). In response to this waveform +VTL, the output of
amplifier A1 forming the output SI of sawtooth generator GD, supplies a
voltage waveform VI illustrated by the diagram E of FIG. 7 which
comprises, during the period between time instants t0 and t2
corresponding to the trace period TA of the scan, a voltage decreasing
linearly between a maximum value (positive) and a minimum value
(negative), and during the flyback intervals preceding time instant t0
and succeding to time instant t2, an increasing voltage of substantially
semi-cosinusoidal shape.
Voltage VI is applied to one of the
inputs (-) of an analog voltage comparator which may be formed by means
of a second differential-type amplifier A2 (integrated operational
amplifier), whose other input (+) connected to the input 12 of modulator
10A, receives the regulating voltage VR supplied by the regulator
stage (30 of FIG. 3). This regulating voltage VR, which is obtained by
comparing the output voltage VS of the supply device BS of the circuit
of FIG. 1 with a reference voltage (VZ supplied by a Zener diode, for
example), is a DC voltage undergoing slow variations, shown in Diagram E
of FIG. 7 by a dash-dot line.
When the waveform VI applied to
the inverting input (-) of comparator A2 is greater than the regulating
voltage VR, which is the case during the period between time instants
t0 and t1, its output connected to the output 14 of modulator 10A
provides a low state. When, on the other hand, it (VI) reaches or
becomes less than VR, which occurs from the time instant t1, the output
14 of modulator 10A provides a high state (which causes saturation of
the first transistor T1). This high state continues until time instant
t4 subsequent to the time instant t2 of the beginning of the following
flyback pulse whose leading edge controls the turn-off of the first
transistor T1, when the waveform VI becomes greater than the regulating
voltage VR. Thus there is obtained at the output 14 of modulator 10A a
rectangular signal VP shown in Diagram F of FIG. 7, formed successively
of a low-level (zero or negative) beginning during the first half of
the flyback period TR and ending at time instant t1, and a high level
going from time instant t1 to time instant t4. Time instant t1 of the
positive transition of signal VP, which determines the beginning of
conduction of the first transistor T1 is then situated during the trace
period of the scan TA and its position with respect to the beginning t0
or to the end t2 thereof varies as a function of the regulating
voltage VR. When the regulating voltage VR is negative (as on the
Diagram E of FIG. 7), a predetermined fraction of the output voltage VS
is greater than the reference voltage, the duration of the high level
state (t2-t1) is less than half of the trace period of the scan T1. In
the opposite case, this duration (t2-t1) is greater than TA/2. The
modification of this duration (t2-t1) and thus of the duty cycle is
carried out in the reverse direction of the variation of the output
voltage VS so as to stabilize it at a previously adjusted level, with
respect to this reference voltage. The waveform -VTL may also be
applied to the input 11 of modulator 10A. In this case, the input of
comparator A2 must also be inverted.
To
obtain suitable operating limits, while taking into consideration
particularly the value of inductance L, the duty cycle or the durations
(t2-t1) must vary between 0, the case where the input voltage VE is
equal to the nominal output voltage VS, and about two-thirds, the case
where the maximum power is supplied for a minimum voltage at the input.
The ratio between the residual alternating voltage (hum) at the
output and the alternating voltage at the input must also allow an
image to be obtained which is not perturbed for the eye. A value less
than or equal to a hundredth for this ratio gives satisfactory results.
FIG.
8 shows the simplified diagram of a practical embodiment (by means of
discrete components) of the pulse-width modulator 10 of FIG. 3.
Different waveforms of a current I1 and input +VTL and output VP
voltages are respectively illustrated by the Diagrams H, J and K of FIG.
9.
The input 11 of modulator 10B of FIG. 3 receives the voltage
waveform +VTL which may be suppled either directly by the second
secondary winding B3 of line transformer TL, or through a coupling
capacitor whose one terminal is connected to the collector of the trace
switch transistor TH (see FIG. 1). This input 11 supplies a passive
shaping circuit, supplying negative-going (decreasing) sawtooth
waveforms during the trace periods of scan T1. This passive circuit
comprises a fourth coupling capacitor C4 (0.1μ) one terminal of which is
connected to the input 11 and the other of which is connected to one
of the terminals of a sixth resistor R6 (10 Kohms). The other terminal
of this resistor R6 is connected to one of the terminals of a seventh
resistor R7 (5.6 Kohms), to one of the terminals of a fifth capacitor C5
(5.6 nF) and to the anode of a sixth diode D6. The other terminal of
capacitor C5 is connected to ground G. The cathode of the sixth diode D6
and the other terminal of resistor R7 are both connected to one of the
terminals of an eighth resistor R8 (33 kohms), to that of a ninth
resistor R9 (470 ohms), to that of a sixth capacitor C6 (4.7 nF) and to
the regulation input 12 of modulator 10B, which is connected to the
output 32 of the regulator stage 30 (see FIG. 3). The other terminal of
capacitor C6 is connected to ground. The other terminal of resistor R8
is connected to the supply input 13 of modulator 10B receiving the
input voltage VE. The other terminal of the ninth resistor R9 is
connected to the base of a fourth NPN transistor T3, which forms the
voltage comparator stage, whose emitter is connected to ground and
whose collector (open), which forms the output 14 of modulator 10 B, is
connected to the input 21 of the driver stage 20A (of FIG. 4) or 20B
(of FIG. 5), formed by the cathode of the second diode D2. The value of
capacitor C6 has been chosen so as to limit the maximum negative
voltage applied to the base-emitter junction of transistor T3 to a
value less than its reverse avalanche breakdown voltage. When the input
voltage waveform +VTL is positive, as during the major portion of the
flyback periods TR, diode D6 short-circuits resistor R7 and we have
then a simple passive RC integrator formed by resistor R6 in series and
two capacitors C5 and C6 in parallel, whose output is connected to the
base of transistor T3 through resistor R9. Transistor T3 becomes
conducting when its base current IB formed by the sum of currents I1
and I2 becomes positive. The current I1 shown by an arrow in FIG. 8 and
on the Diagram H of FIG. 9, results from the application of the +VTL
waveform of Diagram J to the above-mentionned simple integrator, during
its positive alternation, and to the cascaded double integrator R6,
C5, R7, C6 during its negative plateau going from t0 to t2. During this
negative voltage plateau of the +VTL signal, the current I1 becomes
negative and linearly decreasing. When the instantaneous negative
amplitude of current I1 becomes equal to the positive current I2 shown
by another arrow in FIG. 8 and by means of a reversed constant level
(-I2) shown by a broken line in diagram H of FIG. 7, which occurs at
time t1, the base current of transistor T3 is cancelled out and this
latter is cut off. Since the current I2 is due for a large part to the
regulating current IR supplied by the output of the regulator stage (30
in FIG. 3) and proportional to the error voltage, the duration of the
cut-off state (t4-t1) of transistor T3 and, consequently, that (t2-t1)
of the saturated state of the first transistor T1 (as well as the duty
cycle) will vary reversely to the variation of this current IR. The
current IE shown by an arrow in FIG. 8, which flows through the
high-value resistor R8 from the input voltage source VE and which is
one of the components with IR of current I2, forms a small current for
maintaining transistor T3 saturated in the absence of flyback pulses
and thus of horizontal deflection. The fact that resistor R8 is
supplied by the unregulated input voltage VE allows another parameter
to be added for acting on the duty cycle of transistor T3 as a function
thereof. Diagram K of FIG. 9 illustrates the rectangular signal VP
obtained at the output 14 of the modulator 10B of FIG. 8.
FIG.
10 is a schematic diagram of a conventional regulator stage 30 of the
control circuit of FIG. 3. It is formed essentially by a well-known
circuit called differential amplifier having two inputs, the first of
which receives an adjustable fraction of the voltage to be stabilized,
formed, in the present case, by the output voltage VS of the power
supply device (BS, FIG. 1) and the second input of which receives a
stable reference voltage which is generally generated within this stage
(as in most known ballast or switched-mode voltage regulator).
The
reference voltage VZ is here produced by means of a Zener diode D7 (of
the BZX83C type having a stabilized Zener voltage of 7.5 V) whose
cathode is connected to the input 31 receiving the output voltage VS of
the device BS (FIG. 1) and whose anode is connected through an eleventh
resistor R11 (10 Kohms) to ground G. The second input of the
differential amplifier used here is formed by the emitter of a fifth PNP
transistor T4 which is connected to the anode of the Zener diode D7.
The voltage (VS-VZ) biasing this emitter is then fixed with respect to
the output voltage VS. The first input of the differential amplifier is
here formed by the base of transistor T4 which is biased by a
voltage-divider circuit, formed from a fifteenth resistor R15 (4.7
Kohms), a potentiometer R16 (5 Kohms) and a fourteenth resistor R14 (22
Kohms) connected in series between the input terminal 31 and ground G.
The base of transistor T4, connected to the slider of potentiometer R16
receives then a previously adjusted fraction of the output voltage VS
supplying the horizontal deflection circuit (SH), so that it forms a
constant current generator supplying a current proportional to its
emitter-base voltage which is equal to the difference (error voltage)
between the reference voltage VZ and the selected fraction of the output
voltage VS supplied by potentiometer R16. The collector of the fourth
transistor T4, connected by a tenth resistor R10 (2.2 Kohms) to the
output 32, supplies then the regulating current IR to the regulating
input (12, FIGS. 3 and 8) of the pulse-width modulator (10 or 10B, FIGS.
3 and 8).
It will be noted here that a feedback circuit
comprising a twelfth resistor R12 (5.6 Kohms) and a seventh capacitor C7
(4.7 nF) in series connects the collector of transistor 14 to its
base.
The difference between the voltage respectively provided
by the potentiometer R16 and the Zener diode D7 causes more or less
heavy conduction of transistor T4 which delivers the current IR.
In
short, when the output voltage VS increases, the voltage (VS-VZ) at
the emitter of transistor T4 increases more than that applied to its
base and current IR increases. The value of I1 at which transistor T3
is cut off increases then in absolute value and this transistor T3 is
turned off later, which reduces the conducting period of transistor T1.
The peak current in inductance L then diminishes, which causes a
reduction of the output voltage VS which comes back to its nominal
value, taking into account the residual error required for controlled
operation.
FIG. 11 shows the complete simplified diagram of a
power supply device BS of FIG. 1 whose control circuit SCA is
respectively formed by the driver circuit 20A of FIG. 4, by the
modulator 10B of FIG. 8 and the regulator stage 30 of FIG. 10, except
for a few variations.
The variations concern a damping resistor
R17 of 1 kiloohm shunting the inductance L, resistor R8 and resistor
R10 which are both connected directly to the base of transistor T3
instead of being connected to the cathode of diode D6, resistor R11
which has been omitted and a resistor R13 which shunts the slider of
potentiometer R16 to ground. These details of construction have no
influence at all on the operation of the circuit such as it has been
described above, but simply allow easier adjustment.
Another
embodiment is shown in FIG. 12. It allows more especially a television
set to be supplied with power in which the horizontal deflection
circuit operates from a higher DC voltage VS, of about 100 volts for
example, itself obtained from an initial output voltage VSI of about 60
volts. The operation of the circuit is fundamentally the same as that
of FIG. 11 and only the differences will be described below. The
components playing the same role in both diagrams bear the same
references. The values may however be different but their dimensioning
is within the scope of a man skilled in the art. The voltage VS
delivered by the power supply is used principally in the horizontal
deflection circuit which is the component consuming most power in the
television set. The power supply circuit components receiving
permanently a voltage when the horizontal deflection circuit is not
operating, but when the mains is connected, are solely those
indispensable for activating the power supply, i.e. the first switching
transistor T1 and the circuit for measuring the output voltage in the
regulator stage 300.
To simplify the driver stage 100, instead
of the single switching transistor T1, an integrated Darlington circuit
T10 is used of the BU 807 type, for example. Therefore, the gain is
sufficient to omit a discrete driver transistor T2 and to connect the
cathode of diode D3 directly to the base input of T10. The negative
-VTH pulses, coming from an intermediate tapping on coil B2 of the line
output transformer, are applied directly to the base of T10 through
resistor R3 which is connected in series with a diode D9 whose cathode
is connected to this intermediate tapping.
Instead of the input
voltage VE, the power supply input 4 of the control circuit SCB is fed
by a voltage obtained by rectifying the positive half-waves (plateaux)
of the -VTL voltage supplied by the first secondary winding B2, by
means of a diode D8 and a capacitor C8. Thus considerably lower voltage
may be obtained than that supplying the horizontal deflection circuit,
of the order of 13 volts, for example. A voltage of this value allows
video amplification circuits as well as other circuits of the
television set to be supplied while providing for these latter a very
great reliability. This voltage is applied through resistor R1 to the
anodes of diodes D2 and D3 and through resistor R8 to the base of the
transistor T3 of modulator 10B.
The regulator stage 300 here
comprises two PNP transistors T4 and T5 connected differentially. For
that, their emitters receive the voltage rectified by D8 through a
resistor R18 of 1.5 kiloohms. The collector of transistor T5 is
connected to ground through a resistor R20 of 3.9 kiloohms and the
collector of transistor T4, which supplies the regulating current IR,
is connected to the cathode of diode D6 through a resistor R10 of 4.7
kiloohms.
The reference voltage (6.2 volts) is supplied by a
Zener diode D7 whose anode is connected to ground, and cathode to a
resistor R19 (6.8 kiloohms) which receives the voltage rectified by D8.
This reference voltage is applied to the base of transistor 14. A
capacitor C9 (49 microfarads) shunts diode D7 so as to cause the
reference voltage to rise gradually when the apparatus is switched on,
which allows a gradual rise of the output voltage VS to be obtained.
A
potentiometer R16 of 10 kiloohms connected between two stopper
resistors R15 (68 kiloohms) and R14 (5.6 kiloohms) receives the voltage
VS through the resistor R15 and is connected to ground through
resistor R14. The sliding contact of potentiometer R16 allows a
fraction of the voltage VS to be applied to the base T5. A resistor R13
(47 kiloohms) also connects this base to the common point between R15
and R16.
An anti-oscillation capacitor C10 (15 nanofarads) connects the base of the collector of transistor T5.
Thus
the regulating current IR supplied by resistor R10 is directly
dependent on the difference between the output voltage VS, applied to
the horizontal deflection circuit, and the reference voltage determined
by the Zener diode D7. The power supply BS thus stabilizes this voltage
VS and at the same time the rectified voltage supplied by diode D8.
To
stop this power supply, as well as that of FIG. 11 moreover, it is
sufficient to stop by means of a remote control receiver, for example,
the operation of the horizontal oscillator.
In
this case, the input voltage VE is still present, but is considerably
smaller than voltage VS. For the power supply of FIG. 12, this reduced
voltage is only applied to the Darlington transistor T10 and a fraction
thereof to the base of transistor T5 of the regulator stage 300. Thus
the life expectation of the other components of the device BS is
increased. Since the voltage supplied by diode D8 is itself regulated,
it may be used for supplying a major portion of the television set,
except for the horizontal deflection circuit supplied by voltage VS and
the remote control receiver which must be capable of operating
permanently (also in the ready state) so as to detect the turn-on
control signal. The protection which was mentioned earlier on is then
extended to the greatest part of the components of the television set.
It
will be noted here that the three stages 10, 20 and 30 of control
circuit SC (see FIGS. 1 and 3) may be formed by means of circuits
different from those described and shown and which are known per se,
and that it is sufficient to have a secondary winding B2 (in addition
to the very-high-voltage winding) of the line transformer TL, supplying
negative line-flyback pulses which may be used for generating a
decreasing or increasing sawtooth voltage waveform as well as for
controlling the cutting off of the first switching transistor T1.
CRT TV EHT VOLTAGE MULTIPLIER - KASKADE COCKCROFT-WALTON CASCADE CIRCUIT FOR VOLTAGE MULTIPLICATION:
A
Cockcroft-Walton cascade circuit comprises an input voltage source and a
pumping and storage circuit with a series array of capacitors with
pumping and storage portions of the circuit being interconnected by
silicon rectifiers, constructed and arranged so that at least the
capacitor nearest the voltage source, and preferably one or more of the
next adjacent capacitors in the series array, have lower tendency to
internally discharge than the capacitors in the array more remote from
the voltage source.
1. An improved voltage multiplying circuit comprising,
2.
An improved voltage multiplying circuit in accordance with claim 1
wherein said first pumping capacitor is a self-healing impregnated
capacitor which is impregnated with a high voltage impregnant.
3.
An improved voltage multiplying circuit in accordance with claim 1
wherein said first pumping capacitor comprises a foil capacitor.
Description:
BACKGROUND OF THE INVENTION
The
invention relates in general to Cockcroft-Walton cascade circuits for
voltage multiplication and more particularly to such circuits with a
pumping circuit and a storage circuit composed of capacitors connected
in series, said pumping circuits and storage circuit being linked with
one another by a rectifier circuit whose rectifiers are preferably
silicon rectifiers, especially for a switching arrangement sensitive to
internal discharges of capacitors, and more especially a switching
arrangement containing transistors, and especially an image tube
switching arrangement.
Voltage multiplication cascades composed
of capacitors and rectifiers are used to produce high D.C. voltages from
sinusoidal or pulsed alternating voltages. All known voltage
multiplication cascades and voltage multipliers are designed to be
capacitance-symmetrical, i.e., all capacitors used have the same
capacitance. If U for example is the maximum value of an applied
alternating voltage, the input capacitor connected directly to the
alternating voltage source is charged to a D.C. voltage with a value U,
while all other capacitors are charged to the value of 2U. Therefore, a
total voltage can be obtained from the series-connected capacitors of a
capacitor array.
In voltage multipliers, internal resistance is
highly significant. In order to obtain high load currents on the D.C.
side, the emphasis in the prior art has been on constructing voltage
multipliers with internal resistances that are as low as possible.
Internal
resistance of voltage multipliers can be reduced by increasing the
capacitances of the individual capacitors by equal amounts. However, the
critical significance of size of the assembly in the practical
application of a voltage multiplier, limits the extent to which
capacitance of the individual capacitors can be increased as a practical
matter.
In television sets, especially color television sets,
voltage multiplication cascades are required whose internal resistance
is generally 400 to 500 kOhms. Thus far, it has been possible to achieve
this low internal resistance with small dimensions only by using
silicon diodes as rectifiers and metallized film capacitors as the
capacitors.
When silicon rectifiers are used to achieve low
internal resistance, their low forward resistance produces high peak
currents and therefore leads to problems involving the pulse resistance
of the capacitors. Metallized film capacitors are used because of space
requirements, i.e., in order to ensure that the assembly will have the
smallest possible dimensions, and also for cost reasons. These film
capacitors have a self-healing effect, in which the damage caused to the
capacitor by partial evaporation of the metal coating around the point
of puncture (pinhole), which develops as a result of internal
spark-overs, is cured again. This selfhealing effect is highly desirable
as far as the capacitors themselves are concerned, but is not without
its disadvantages as far as the other cirucit components are concerned,
especially the silicon rectifiers, the image tubes, and the components
which conduct the image tube voltage.
It is therefore an important object of the invention to improve voltage multiplication cascades of the type described above.
It is a further object of the invention to keep the size of the entire assembly small and the internal resistance low.
It is a further object of the invention to increase pulse resistance of the entire circuit.
It is a further object of the invention to avoid the above-described disadvantageous effects on adjacent elements.
It
is a further object of the invention to achieve multiples of the
foregoing objects and preferably all of them consistent with each other.
SUMMARY OF THE INVENTION
In
accordance with the invention, the foregoing objects are met by making
at least one of the capacitors in the pumping circuit, preferably
including the one which is adjacent to the input voltage source, one
which is less prone to internal discharges than any of the individual
capacitors in the storage circuit.
The Cockcroft-Walton cascade
circuit is not provided with identical capacitors. Instead, the
individual capacitors are arranged according to their loads and designed
in such a way that a higher pulse resistance is attained only in
certain capacitors. It can be shown that the load produced by the
voltage in all the capacitors in the multiplication circuit is
approximately the same. But the pulse currents of the capacitors as well
as their forward flow angles are different. In particular, the
capacitors of the pumping circuit are subjected to very high loads in a
pulsed mode. In the voltage multiplication cascade according to the
invention, these capacitors are arranged so that they exhibit fewer
internal discharges than the capacitors in the storage circuit.
The
external dimensions of the entire assembly would be unacceptably large
if one constructed the entire switching arrangement using such
capacitors.
The voltage multiplication cascade according to the invention also makes it possible to construct a reliably operating
arrangement
which has no tendency toward spark-overs, consistent with satisfactory
internal resistance of the voltage multiplication cascade and small
dimensions of the entire assembly. This avoids the above cited
disadvantages with respect to the particularly sensitive components in
the rest of the circuit and makes it possible to design voltage
multiplication cascades with silicon rectifiers, which are characterized
by long lifetimes. Hence, a voltage multiplication cascade has been
developed particularly for image tube circuits in television sets,
especially color television sets, and this cascade satisfies the highest
requirements in addition to having an average lifetime which in every
case is greater than that of the television set.
A further aspect
of the invention is that at least one of the capacitors that are less
prone to internal discharges is a capacitor which is impregnated with a
high-voltage impregnating substance, especially a high-voltage oil such
as polybutene or silicone oil, or mixtures thereof. In contrast to
capacitors made of metallized film which have not been impregnated, this
allows the discharge frequency due to internal discharges or
spark-overs to be reduced by a factor of 10 to 100.
According to a
further important aspect of the invention, at least one of the
capacitors that are less prone to internal discharges is either a foil
capacitor or a self-healing capacitor. In addition, the capacitor in the
pumping circuit which is adjacent to the voltage source input can be a
foil capacitor which has been impregnated in the manner described above,
while the next capacitor in the pumping circuit is a self-healing
capacitor impregnated in the same fashion.
Other objects,
features and advantages of the invention will be apparent from the
following detailed description of preferred embodiments, taken in
connection with the accompanying drawing, the single FIGURE of which:
BRIEF DESCRIPTION OF THE DRAWING
is a schematic diagram of a circuit made according to a preferred embodiment of the invention.
DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS
The
voltage multiplier comprises capacitors C1 to C5 and rectifiers D1 to
D5 connected in a cascade. An alternating voltage source UE is connected
to terminals 1 and 2, said voltage source supplying for example a
pulsed alternating voltage. Capacitors C1 and C2 form the pumping
circuit while capacitors C3, C4 and C5 form the storage circuit.
In
the steady state, capacitor C1 is charged to the maximum value of the
alternating voltage UE as are the other capacitors C2 to C5. The desired
high D.C. voltage UA is picked off at terminals 3 and 4, said D.C.
voltage being composed of the D.C. voltages from capacitors C3 to C5.
Terminal 3 and terminal 2 are connected to one pole of the alternating
voltage source UE feeding the circuit, which can be at ground potential.
In the circuit described here, a D.C. voltage UA can be picked off
whose voltage value is approximately 3 times the maximum value of the
pulsed alternating voltage UE. By using more than five capacitors, a
correspondingly higher D.C. voltage can be obtained.
The
individual capacitors are discharged by disconnecting D.C. voltage UA.
However, they are constantly being recharged by the electrical energy
supplied by the alternating voltage source UE, so that the voltage
multiplier can be continuously charged on the output side.
According
to the invention, in this preferred embodiment, capacitor C1 and/or C2
in the pumping circuit are designed so that they have a lower tendency
toward internal discharges than any of the individual capacitors C3, C4
and C5 in the storage circuit.
It is evident that those skilled
in the art, once given the benefit of the foregoing disclosure, may now
make numerous other uses and modifications of, and departures from the
specific embodiments described herein without departing from the
inventive concepts. Consequently, the invention is to be construed as
embracing each and every novel feature and novel combination of features
present in, or possessed by, the apparatus and techniques herein
disclosed and limited solely by the scope and spirit of the appended
claims.
Inventors:Petrick, Paul (Landshut, DT)
Schwedler, Hans-peter (Landshut, DT)
Holzer, Alfred (Schonbrunn, DT)
ERNST ROEDERSTEIN SPEZIALFABRIK
US Patent References:
3714528 ELECTRICAL CAPACITOR WITH FILM-PAPER DIELECTRIC 1973-01-30 Vail
3699410 SELF-HEALING ELECTRICAL CONDENSER 1972-10-17 Maylandt
3463992 ELECTRICAL CAPACITOR SYSTEMS HAVING LONG-TERM STORAGE CHARACTERISTICS 1969-08-26 Solberg
3457478 WOUND FILM CAPACITORS 1969-07-22 Lehrer
3363156 Capacitor with a polyolefin dielectric 1968-01-09 Cox
2213199 Voltage multiplier 1940-09-03 Bouwers et al.
NORDMENDE SPECTRA SK3-COLOR T3137 CHASSIS F9 (492.445) AMBIENT LIGHT RESPONSIVE CONTROL OF BRIGHTNESS, CONTRAST AND COLOR SATURATION Gain control arrangement useful in a television signal processing system.
In
a color television receiver, first and second amplifiers are
respectively included in the luminance and chrominance channels to
permit control of contrast and saturation. The amplifiers have gain
versus control voltage characteristics including linear portions
extrapolated to cut off at predetermined voltages which may or may not
be the same. A first potentiometer is coupled between a source of
fixed voltage equal to the extrapolated cut off voltage of the first
amplifier and a gain controlling voltage source. The gain
controlling voltage may be produced by a circuit including an
element responsive to ambient light. The wiper of the first
potentiometer is coupled to the first amplifier to couple a voltage
developed at a predetermined point of the first potentiometer to
the first amplifier to control its gain. A second potentiometer is
coupled between a source of voltage equal to the extrapolated cut
off voltage of the second amplifier and the gain controlling voltage
source to receive a portion of the gain controlling voltage in
accordance with the ratio of the extrapolated cut off voltages of
the first and second amplifiers. The wiper of the second
potentiometer is coupled to the second amplifier to couple a voltage
developed at a predetermined point of the second potentiometer to
the second amplifier to control its gain. In this manner, the
contrast of the receiver may be varied over a relatively wide range
while saturation is maintained substantially constant.
1.
In a color television signal processing system of the type
including luminance and chrominance signal processing channels,
apparatus comprising:
first and second amplifiers respectively
included in said luminance and chrominance channels, said
amplifiers having gain versus control voltage characteristics
including linear portions extrapolated to cut-off at predetermined
voltages which may or may not be the same voltage;
a gain controlling voltage source;
means for coupling said gain controlling voltage to said first amplifier to control its gain;
potentiometer
means coupled between a fixed voltage substantially equal to the
extrapolated cut-off voltage of said second amplifier and to said
gain controlling voltage source to recieve a portion of said gain
controlling voltage in accordance with the ratio of the
extrapolated cut-off voltages of said first and second amplifiers; and
means
for coupling a voltage developed at a predetermined point on said
potentiometer means to said second amplifier to control its gain.
2.
The apparatus recited in claim 1 wherein said means for coupling
said gain controlling voltage to said first amplifier includes
another potentiometer coupled between a source of fixed voltage
substantially equal to the extrapolated cut-off voltage of said
first amplifier and said gain controlling voltage source.
3. In a color television signal
processing system of the type including luminance and chrominance
signal processing channels, apparatus comprising:
first and
second amplifiers respectively included in said luminance and
chrominance channels, said amplifiers having gain control voltage
characteristics including linear portions extrapolated to cut-off at
substantially the same predetermined voltage;
a source of gain controlling voltage; and
means for coupling said gain controlling voltage to said first and second amplifiers.
4. Apparatus comprising:
first
variable gain amplifying means for amplifying a first signal in
response to a first DC control signal, said first amplifying means
having a first gain versus DC control voltage characteristic
including a linear region, said linear region having a gain
substantially equal to 0 at a DC control voltage equal to V
O ;
second
variable gain amplifying means for amplifying a second signal in
response to a second DC control signal, said second amplifying means
having a second gain versus DC control voltage characteristic
including a linear region, said linear region having a gain
substantially equal to 0 at a DC control voltage equal to AV
O, where A is a number greater than 0;
a first source of fixed voltage substantially equal to V
O ;
a second source of fixed voltage substantially equal to AV
O ;
means for developing a third DC control voltage v;
means for developing a portion Av of said third control voltage v;
first
means for deriving said first control voltage including means for
providing the difference between said third control voltage v and
said fixed voltage V
O and means for adding a predetermined portion of the difference between said third control voltage v and said fixed voltage V
O to said DC control voltage v; and
second
means for deriving said second control voltage including means for
providing the difference between a portion Av of said third control
voltage v and said fixed voltage AV
O and means for adding a predetermined portion of the difference between said portion Av and said fixed voltage AV
O to said DC control voltage v.
5.
The apparatus recited in claim 4 wherein A is equal to 1.
6. The apparatus recited in claim 4
wherein said first amplifying means is included in a luminance
channel of a televeision signal processing system and said second
amplifying means is included in a chrominance channel of said
television signal processing system.
7. The apparatus recited in claim 6 wherein means for
developing said third control voltage includes means responsive to
ambient light. 8. The apparatus
recited in claim 4 wherein said first means includes first voltage
divider means coupled between said fixed voltage V
O and
said third DC control voltage v; and wherein said second means
includes second voltage divider means coupled between said fixed
voltage AV
O and said portion Av.
9. The apparatus recited in claim 8 wherein said first
voltage divider means includes a first potentiometer, said first
potentiometer having a wiper coupled to said first amplifying means;
and wherein said second voltage divider means includes a second
potentiometer, said second potentiometer having a wiper coupled to
said amplifying means. 10. The
apparatus recited in claim 4 wherein said second gain versus DC
control voltage characteristic includes a region between said voltage
AV
O and a voltage V
B where the gain is greater than 0, said voltage V
B
being substantially equal to the voltage at which said second
amplifying means has a gain substantially equal to 0; and wherein said
second source of fixed voltage includes means for coupling said
voltage V
B to said second amplifying means.
11. The apparatus recited in claim 10 wherein
said second source of said voltage AV
O includes a third source of fixed voltage V
B ; potentiometer means coupled between said third source of fixed voltage V
B
and said means for developing said third DC control voltage; and
means coupled to said potentiometer means for developing said
voltage AV
O at a point along said potentiometer means;
said potentiometer means including a wiper coupled to said second
amplifier means, said wiper being adjustable to couple a DC voltage
V
FB and said third control voltage to said second amplifying means.
Description:
The
present invention pertains to gain controlling apparatus and
particularly to apparatus for controlling the gains of amplifiers
included in the luminance and chrominance channels of a television
signal processing system.
Recently, the maximum brightness
available from television receivers has increased sufficiently so that a
pleasing image may be reproduced under conditions of high ambient
light as well as under conditions of low ambient light. Apparatus
is known for automatically controlling the contrast and brightness
properties of a television receiver in response to ambient light to
provide a pleasing image over a range of ambient light conditions.
Such apparatus is described in U.S. Pat. Nos. 3,027,421, entitled
"Circuit Arrangements For Automatically Adjusting The Brightness
And The Contrast In A Television Receiver," issued to H.
Heijligers on Mar. 27, 1962 and 3,025,345, entitled "Circuit
Arrangement For Automatic Readjustment Of The Background Brightness
And The Contrast In A Television Receiver," issued to R. Suhrmann
on Mar. 13, 1962.
Apparatus is also known for automatically
controlling the contrast and saturation properties of a color
television receiver by controlling the gains of luminance and
chrominance channel amplifiers, respectively, in response to ambient
light. Such apparatus is described in U.S. Pat. Nos. 3,813,686
entitled "Ambient Light Responsive Control Of Brightness, Contrast
And Color Saturation," issued to Eugene Peter Mierzwinski, on May
28, 1974 and 3,814,852 entitled "Ambient Light Responsive Control
Of Brightness, Contrast and Color Saturation," issued to Eugene P.
Mierzwinski on June 4, 1974.
Also of interest is apparatus
for manually controlling the gains of luminance and chrominance
channel amplifiers. Such apparatus is described in U.S. Pat. Nos.
3,374,310, entitled "Color Television Receiver with Simultaneous
Brightness and Color Saturation Controls," issued to G.L. Beers on
Mar. 19, 1968; 3,467,770, entitled "Dual Channel Automatic Control
Circuit," issued to DuMonte O. Voigt on June 7, 1966; and
3,715,463, entitled "Tracking Control Circuits Using a Common
Potentiometer," issued to Lester Tucker Matzek, on Feb. 6, 1973.
When
the gain of luminance channel is adjusted to control the contrast
of an image, either manually or automatically, in response to
ambient light, it is desirable to simultaneously control the gain of
the chrominance channel in such a manner that the ratio of the
gains of the luminance and chrominance channels is substantially
constant over a wide range of contrast control to maintain constant
saturation. If the proper ratio between the amplitudes of the
chrominance and luminance signals is not maintained incorrect color
reproduction may result. For instance, if the amplitude of the
luminance signals are increased without correspondingly increasing
the amplitude of the chrominance signals, colors may become
desaturated, i.e., they will appear washed out or pastel in shade.
Furthermore, it may be desirable to provide controls for presetting
the gains of the luminance and chrominance channels to compensate
for tolerance variations in other portions of the television signal
processing apparatus.
In
accordance with the present invention, apparatus is provided which
may be utilized in a color television receiver to control contrast
over a relatively wide range while maintaining constant
saturation. The apparatus includes first and second amplifiers
having gain versus control voltage characteristics including linear
portions extrapolated to cut off at predetermined voltages which
may or may not be the same. Means couple a gain controlling voltage
source to the first amplifier to control its gain. Potentiometer
means are coupled between a source of fixed voltage substantially
equal to the extrapolated cut off voltage of the second amplifier
and the source of gain controlling voltage to receive a portion of
said gain controlling voltage in accordance with the ratio of the
extrapolated cut off voltages of the amplifiers. A voltage
developed at a predetermined point along the potentiometer means is
coupled to the second amplifier to control its gain.
In
accordance with another feature of the present invention, the means
for coupling said gain controlling voltage to said first amplifier
includes another potentiometer coupled between a source of fixed
voltage substantially equal to the extrapolated cut off voltage of
said first amplifier and said gain controlling voltage source.
In
accordance with still another feature of the present invention the
gain controlling voltage source includes an element responsive to
ambient light .
These and other aspects of the present
invention may best be understood by references to the following
detailed description and accompanying drawing in which:
FIG. 1
shows the general arrangement, partly in block diagram form and
partly in schematic diagram form, of a color television receiver
employing an embodiment of the present invention;
FIG. 1A shows, in schematic form, a modification to the embodiment shown in FIG. 1;
FIG.
2 shows graphical representation of gain versus control voltage
characteristics of amplifiers utilized in the embodiment shown in
FIG. 1;
FIG. 3 shows graphical representations of gain
versus control voltage characteristics of amplifiers which may be
utilized in the receiver shown in FIG. 1;
FIG. 4 shows, in
schematic form, another embodiment of the present invention which
may be utilized to control the amplifiers whose gain versus control
voltage characteristics are shown in FIG. 3;
FIG. 5 shows, in schematic form, an amplifier which may be utilized in the receiver shown in FIG. 1; and
FIG. 6 shows, in schematic form, another amplifier which may be utilized in the receiver shown in FIG. 1.
Referring now
to
FIG. 1, the general arrangement of a color television receiver
employing the present invention includes a video signal processing unit
112 responsive to radio frequency (RF) television signals for
generating, by means of suitable intermediate frequency (IF) circuits
(not shown) and detection circuits (not shown), a composite video
signal comprising chrominance, luminance, sound and synchronizing
signals. The output of signal processing unit 112 is coupled to
chrominance channel 114, luminance channel 116, a channel 118 for
processing the synchronizing signals and a channel (not shown) for
processing sound signals.
Chrominance processing channel 114
includes chrominance processing unit 120 which serves to remove
chrominance signals from the composite video signal and otherwise
process chrominance signals. Chrominance signal processing unit 120
may include, for example, automatic color control (ACC) circuits for
adjusting the amplitude of the chrominance channels in response to
amplitude variations of a reference signals, such as a color burst
signal, included in the commposite video signal. Chrominance
signal processing circuits of the type described in the U.S. Pat.
No. 3,740,462, entitled "Automatic Chroma Gain Control System,"
issued to L.A. Harwood, on June 19, 1973 and assigned to the same
assignee as the present invention are suitable for use as
chrominance processing unit 120.
The output of the
chrominance signal processing unit 120 is coupled to chrominance
amplifier 122 which serves to amplify chrominance signals in response
to a DC signal v
C generated by gain control network 142.
As illustrated, chrominance amplifier 122 provides chrominance
signals to a chroma demodulator 124. An amplifier suitable for use
as chrominance amplifier 122 will subsequently be described with
reference to FIG. 6.
Chroma demodulator 124 derives color
difference signals representing, for example, R-Y, B-Y and G-Y
information from the chrominance signals. Demodulator circuits of
the general type illustrated by the chrominance amplifier CA 3067
integrated circuit manufactured by RCA Corporation are suitable for
use as chrominance demodulator 124.
The color difference
signals are applied to a video driver 126 where they are combined
with the output signals -Y of luminance channel 116 to produce
color signals of the appropriate polarity, representing for example,
red (R), green (G) and blue (B) information. The color signals are
coupled to kinescope 128.
Luminance channel 116 includes a
first luminance signal processing unit 129 which relatively
attenuates undesirable signals, such as chrominance or sound
signals or both, present in luminance channel 116 and otherwise
processes the luminance signals. The output of first luminance
processing unit 129 is coupled to luminance amplifier 130 which
serves to amplify the luminance signals in response to a DC control
signal v
L generated by gain control unit 142 to thereby
determine the contrast of a reproduced image. An amplifier suitable
for use as luminance amplifier 130 will subsequently be described
with reference to FIG. 5. The output of luminance amplifier 130 is
coupled to second luminance signal processing unit 132 which serves
to further process luminance signals. A brightness control unit
131 is coupled to luminance signal processing unit 132 to control
the DC content of the luminance signals. The output -Y of luminance
processing unit 132 is coupled to kinescope driver 126.
Channel
118 includes a sync separator 134 which separates horizontal and
vertical synchronizing pulses from the composite video signal. The
synchronizing pulses are coupled to horizontal deflection circuit
136 and vertical deflection circuit 138. Horizontal deflection
circuit 136 and vertical deflection circuit 138 are coupled to
kinescope 128 and to a high voltage unit 140 to control the
generation and deflection of one or more electron beams generated
by kinescope 128 in the conventional manner. Deflection circuits
136 and 138 also generate horizontal and vertical blanking signals
which are coupled to luminance signal processing unit 132 to
inhibit its operation during the horizontal and vertical retrace
intervals.
Gain
control unit 142 is coupled to luminance amplifier 130 and to
chrominance amplifier 122 to control their gains. Gain control unit
142 includes a PNP transistor 152 arranged as an emitter-follower
amplifier. The collector of transistor 152 is coupled to ground while
its emitter is coupled through a series connection of a
potentiometer 156 and fixed resistor 154 to a source of positive
supply voltage V
O. The wiper of potentiometer 156 is
coupled to luminance amplifier 130. The series connection of a
potentiometer 158 and a variable resistor 159 is coupled between the
source of positive supply voltage V
O and the emitter of transistor 152. The wiper of potentiometer 158 is coupled to chrominance amplifier 122.
The
base of transistor 152 is coupled to the wiper of a potentiometer
146. One end of potentiometer 146 is coupled to the source of
positive supply voltage V
O through a fixed resistor 144.
The other end of potentionmeter 146 is coupled to ground through a
light dependent resistor (LDR) 148. LDR 148 is a resistance element
whose impedance varies in inverse relationship with light which
impinges on it. LDR 148 may comprise a simple cadmium sulfide type
of light dependent element or other suitable light dependent device.
LDR 148 is desirably mounted to receive ambient light in the
vicinity of the screen of kinescope 128.
A single pole
double-throw switch 150 has a pole coupled to the junction of
potentiometer 146 and LDR 148. A resistor 151 is coupled between the
wiper of potentiometer 146 and the other pole of switch 150. The
arm of switch 150 is coupled to ground.
The general
arrangement shown in FIG. 1 is suitable for use in a color
television receiver of the type shown, for example, in RCA Color
Television Service Data 1973 No. C -8 for a CTC-68 type receiver,
published by RCA Corporation, Indianapolis, Indiana.
In
operation, gain control circuit 142 maintains the ratio of the
gain of chrominance amplifier 122 to the gain of amplifier 130
constant in order to maintain constant saturation while providing
for contrast adjustment either manually by means of potentiometer
146 or automatically by means of LDR 148. If the gain of luminance
were adjusted to control the contrast of an image without a
corresponding change in the gain of chrominance amplifier 122, the
amplitudes of luminance signals -Y and color difference signals
R-Y, B-Y and G-Y would not, in general, be in the correct ratio
when combined by divider 126 to provide the desired color.
When
switch 140 is in the MANUAL position, the gains of chrominance
amplifier 122 and luminance amplifier 130 are controlled by
adjustment of the position of potentiometer 146. When switch 150 is
in the AUTO position the gain of the chrominance amplifier 122 and
luminance amplifier is automatically controlled by the response of
LDR 148 to ambient light conditions. The voltage developed at the
wiper of potentiometer 146 (base of transistor 152) when switch 150
is in the AUTO position is inversely related to the ambient light
recieved by LDR 148. It is noted that the values of resistors 114,
potentiometer 146, LDR 148 and resistor 151 are desirably selected
such that the adjustment of the wiper arm of potentiometer 146 when
switch 150 is in the MANUAL position does not substantially affect
the voltage developed at the base of transister 152 when switch
150 is placed in the AUTO position.
The control voltage v
developed at the wiper arm of potentiometer 146 is coupled through
emitter-follower transistor 152 to the common junction of
potentiometer 156 and variable resistor 159. A control voltage v
L comprising v plus a predetermined portion of the difference V
O
-v developed across the series connection of fixed resistor 154
and potentiometer 156, depending on the setting of potentiometer
156, is coupled to luminance amplifier 130 to control its gain.
Similarly, a control voltage v
C comprising v plus a predetermined portion of the difference voltage V
O
-v developed across the series connection of potentiometer
resistor 158 and variable resistor 159, depending on the setting of
the wiper of potentiometer 158, is coupled to chrominance
amplifier 122 to control its gain.
The gain of luminance
amplifier 130 may be pre-set to a desired value by the factory
adjustment of potentiometer 156. Similarly, variable resistor 159
is provided to allow factory pre-set of the gain of the chrominance
amplifier 122. Potentiometer 158 is provided to allow customer
control of saturation.
R
eferring to FIG. 2, the gain versus voltage characteristics of chroma amplifier 122 (g
C) and luminance amplifier 130 (g
L) are shown. The characteristic g
C has a reversed S-shape including a linear portion 214. Extrapolated linear portion 214 of g
C intersects the GAIN axis at G
C and intersects the CONTROL VOLTAGE axis at V
O. Similarly, the characteristics g
L has a reverse S-shape characteristic including a linear portion 212. Extrapolated linear portion 214 of g
L intersects the GAIN axis at G
L and intersects the CONTROL VOLTAGE axis at V
O.
From FIG. 2, the expression for linear portion 212 of g
L is ##EQU1## The expression for linear portion 214 of g
C is ##EQU2## From FIG. 1, the expression for v
L is v
L = v + (V
O -v) K
1 [3]
where K
1
is determined by the voltage division of fixed resistor 154 and
potentiometer 156 at the wiper of potentiometer 156. When the wiper
of potentiometer 156 is at the emitter of transistor 152, K
1 =0. The expression for v
C is v
C = v + (V
O -v)K
2 [4]
where K
2
is determined by the voltage division of potentiometer 158 and
fixed resistor 159 at the wiper of potentiometer 158. By combining
equations [1] and [3], the equation for g
L becomes ##EQU3## By combining equations [2] and [4], the equation for g
C becomes ##EQU4## The ratio of g
L to g
C
is thus ##EQU5## It is noted that this ratio is independent of DC
control voltage v. Thus, although DC control voltage v may be
varied either manually or in response to ambient light to control
the contrast of an image reproduced by kinescope 128, the
saturation remains constant.
With re
ference to FIG. 2, it is noted that although the linear portion 214 of g
C has an extrapolated gain equal to 0 at a control voltage equal to V
O, the non-linear portion of g
C does not attain a gain equal to 0 until a control voltage equal to V
B. That is, a control voltage of V
O will not cut-off chrominance amplifier 122.
In
FIG. 1A there is shown, in schematic form, a modification to the
arrangement of gain control network 142 of FIG. 1 with provisions
which allow a viewer to cut off chrominance amplifier 122 to produce
a more pleasing image under conditions of poor color reception
due, for example, to noise or interference. The modifications to
gain control unit 142 shown in FIG. 1A include coupling
potentiometer resistor 158 between a source of positive supply
voltage V
B, the value of V
B being greater than the value of V
O,
and coupling a resistor 160 from a tap-off point 162 along
potentiometer 158 to ground. The value of potentiometer 158 and resistor
160 and the location of tap 162 are selected so that voltage V
O is developed at tap 162.
The
arrangement shown in FIG. 1A allows for the adjustment of contrast
while constant saturation is maintained and additionally allows a
viewer, by adjusting the wiper of potentiometer 158 to voltage V
B, to cut off chrominance amplifier 122.
Referring
to FIG. 3 there are shown gain versus DC control voltage
characteristics of chrominance and luminance amplifiers which do not
have the same extrapolated linear cut off control voltage. The gain
versus control voltage characteristic g
L ' of the
luminance amplifier has a reverse S-shape characteristic including a
linear portion 312. Extrapolated linear portion 312 of g
L ' intersects the GAIN axis at a gain G
L ' and intersects the CONTROL VOLTAGE axis at a voltage V
O '. The gain versus control voltage characteristic g
C
' of the chrominance amplifier has a reverse S-shape
characteristic having a linear portion 314. Extrapolated linear
portion 314 of g
C ' intersects the GAIN axis at a gain G
C ' and intersects the CONTROL VOLTAGE axis at a voltage AV
O ', where A is a number greater than zero.
From FIG. 3, the expression for linear portion 312 of g
L ' is ##EQU6## where v
L ' is the DC conrol voltage coupled to the luminance amplifier. The expression for linear portion 314 of g
C ' is ##EQU7## where v
C ' is the DC control voltage coupled to the chrominance amplifier.
A
modified form of the control network 142 of FIG. 1 suitable for
controlling the gain of a chrominance and a luminance amplifier
having characteristics such as shown in FIG. 3 is shown in FIG. 4.
Similar portions of FIGS. 1 and 4 are identified by reference
numbers having the same last two significant digits and primed (')
designations. The modified portions of FIG. 1 shown in FIG. 4
include the series connection resistors 460 and 462 coupled between
the emitter of transistor 452 to ground. The values of resistors
460 and 462 are selected so that a portion Av' of the DC control
voltage v' developed at the emitter of transistor 452 is developed
at the junction of resistors 460 and 462. Furthermore, the series
connection of potentiometer 458 and variable resistor 459 is
coupled between the junction of resistor 460 and 462 and a source
of positive supply voltage AV
O '.
From FIG. 4, the expression for control voltage v
L ' developed at the wiper of potentiometer 456 is v
L ' = v' + (v
O '-v')K
1 ' [10]
where K
1 ' is determined by the voltage division at the wiper of potentiometer 456. The expression for control voltage v
C ' developed at the wiper of potentiometer 458 is V
C ' = Av' + (AV
O ' - Av')K
2 ' [11]
where K
2
' is determined by the voltage division at the wiper of
potentiometer 458. By combining equations [8] and [10], ##EQU8## By
combining equations [9] and [11], ##EQU9## The ratio of g
L ' to g
C
' is given by the expression ##EQU10## It is noted that this ratio
is independent of DC control voltage v'. Therefore, gain control
network 442 of FIG. 4 also allows for the adjustment of contrast
while maintaining constant saturation.
It is noted that if A
were made equal to 1, the arrangement gain control unit 442 would be
suitable to control the gains of chrominance and luminance
amplifiers having the characteristics shown in FIG. 2.
In
FIG. 5, there is shown an amplifier suitable for use as luminance
amplifier 130 of FIG. 1. The amplifier includes a differential
amplifier comprising NPN transistors 532 and 534. The commonly
coupled emitters of transistors 532 and 534 are coupled to the
collector of an NPN transistor 528. The emitter of transistor 528 is
coupled via a resistor 530 to ground. The collector of transistor
532 and the collector of transistor 534, via load resistor 536, is
coupled to a bias voltage provided by bias supply 546, illustrated
as a series connection of batteries. The bases of transistors 532
and 534 are respectively coupled to a lower bias voltage through
resistors 533 and 535 respectively.
An input signal, such as,
for example, the output signal provided by first luminance
processing circuit 129 of FIG. 1 is coupled to the base of transistor
532 via terminal 542. The output signal of the amplifier is
developed at the collector of transistor 534 and coupled to output
terminal 544.
A DC control voltage, such as v
L
provided by gain control unit 142 of FIG. 1, is coupled to the base
of an NPN transistor 514, arranged as an emitter-follower, via
terminal 512. The collector of transistor 514 is coupled to bias
supply 546. The emitter of transistor 514 is coupled to ground
through the series connection of resistor 516, a diode connected
transistor 518 and resistor 520.
The anode of diode 520 is
coupled to the base of an NPN transistor 538. The collector of
transistor 538 is coupled to the collector of transistor 534 while
its emitter is coupled to ground through resistor 540. Transistor
538, resistor 540, diode 518 and resistor 520 are arranged in a
current mirror configuration.
The emitter of transistor 514
is coupled to the base of a PNP transistor 522. The emitter of
transistor 522 is coupled to bias supply 546 while its collector is
coupled to the base of transistor 528 and to ground through the
series connection of a diode connected transistor 524 and resistor
526. Transistor 528, resistor 530, diode 524 and resistor 526 are
arranged in a current mirror configuration
In operation, the
DC control voltage coupled to terminal 512 is coupled in inverted
fashion to the anode of diode 524 by transistor 522. As a result,
current directly related to the voltage developed at the anode of
diode 524 flows through diode 524 and resistor 526. Due to the
operation of the current mirror arrangement of diode 524, resistor
526, transistor 528 and resistor 530, a similar current flows
through the emitter circuit of transistor 528. The gain of the
differential amplifier comprising transistors 532 and 534 is
directly related to this current flowing in the emitter circuit of
transistor 528, and therefore is inversely related to the DC
control voltage at terminal 512. The gain versus DC control voltage
characteristics of the differential is similar to g
L shown in FIG. 2.
Further,
a current is developed through the series connection of resistor
516, diode 518 and resistor 520 in direct relationship to the DC
control coupled to terminal 512. A similar current is developed
through resistor 540 due to the operation of the current mirror
comprising diode 518, resistor 520, transistor 538 and resistor 540.
This current is of the opposite sense to that provided by the
current mirror arrangement of diode 524, resistor 526, transistor
528 and resistor 530 and is coupled to the collector of transistor
534 so that the DC voltage at output terminal 544 does not
substantially vary with the DC control voltage.
In FIG. 6, ther
e
is shown an amplifier suitable for use as chroma amplifier 120 of
FIG. 1. The amplifier shown in FIG. 6 is of the type described in
U.S. patent application Ser. No. 530,405 entitled "Controllable Gain
Signal Amplifier," fled by L.A. Harwood et al. on Dec. 6, 1974.
The
amplifier comprises a differential amplifier including NPN
transistors 624 and 625 having their bases coupled to terminal 603 via
a resistor 626. Chrominance signals, provided by a source of
chrominance signals such as chrominance processing unit 120 of FIG. 1,
are coupled to terminal 603. The current conduction paths between
the collectors and emitters of transistors 624 and 625 are
respectively coupled to ground via resistors 628, 629 and 630.
A
current splitter circuit comprising an NPN transistor 632 and a
diode 634 is coupled to the collector of transistor 624. Diode 634
and the base-emitter junction of transistor 632 are poled in the same
direction with respect to the flow of collector current in
transistor 624. It desirable that conduction characteristics of
transistor 632 and diode 635 be substantially matched. Similarly, the
collector of transistor 625 is coupled to a second current
splitter comprising a transistor 633 and a diode 635.
An
output load circuit comprising series connected resistors 636 and 638
is coupled between the collector of transistor 632 and a source of
operating voltage provided by bias supply 610. Amplified
chrominance signals are provided at output terminal 640 for
coupling, for example, to a chroma demodulator such as chroma
demodulator 124 of FIG. 1. Similarly, series connected load
resistors 637 and 639 are coupled between the collector of
transistor 633 and bias supply 610. An output terminal 641 at the
junction of resistors 637 ad 639 provides oppositely phased
chrominance signals to those provided at terminal 640. The gain
associated with the cascode combination of transistors 624 and 632 is
controlled in response to a DC control voltage, such as, for
example, v
C provided by gain control unit 142 of FIG. 1,
coupled to the base of an NPN transistor 646 via terminal 602.
Direct control current is supplied from the emitter of transistor
646 to diode 634 and 635 via a series resistor 652. A signal
by-pass circuit comprising a series resonant combination 654 of
inductance and capacitance is coupled from the anode of diode 634
to ground. Resonant circuit 654 is tuned, for example, to 3.58 MHz
to provide a low impedance path to ground for color subcarrier
signals.
Bias
voltages and currents are supplied to the amplifier arrangement by
bias supply 610, illustrated as a series connection of batterys. A
voltage B+ is coupled to the collector of transistor 646. A lower
bias voltage is coupled to the load circuits of transistors 632 and
633. The bases of transistors 632 and 633 are coupled in common to a
still lower bias voltage. The bases of transistors 624 and 625 are
coupled to a still lower bias voltage via substantially equal in
value resistors 658 and 659. A resistor 694 is coupled from the
common junction of resistors 658 and 659 to ground.
In
operation, a quiescent operating current is provided through
resistor 630. In the absence of an input signal at terminal 603,
this current will divide substantially equally between the
similarly biased transistors 624 and 625. If the DC control voltage
at terminal 602 is near ground potential, transistor 646 will be
effectively cut off and no current will flow in resistor 652 and
diodes 634 and 635. In that case, neglecting the normally small
difference betweeen collector and emitter currents of NPN
transistors, the collector currents of transistors 624 and 625 will
flow, respectively, in transistors 632 and 633. The transistors 632
and 633 are operated in common base mode and form cascode signal
amplifiers with respective transistors 624 and 625. With the DC
control voltage near ground potential, one-half of the quiescent
current from resistor 630 flows in each of the load circuits and
maximum gain for chrominance signals supplied from terminal 603 is
provided.
Transistor 646 will conduct when the DC control
voltage approaches the bias voltage supplied to the bases of
transistors 632 and 633 of the current splitters. By selection of
the circuit parameters, diodes 634 and 635 may be arranged to
operate in a range between cut off to the conduction of all of the
quiescent operating current supplied via resistor 630, thereby
cutting off transistors 632 and 633 to provide no output signals at
terminals 640 and 641.
At a DC control voltage intermediate
to that corresponding to cut off of transistors 632 and 633 on the
one hand and cut off of diodes 634 and 635 on the other hand, the
voltage gain of the illustrated amplifier will vary in a
substantially linear manner with the DC control voltage.
It
is noted that although the characteristics shown in FIGS. 2 and 3
were reversed S-shaped characteristics, the characteristics could
have other shapes including linear portions. For example, the
characteristics could be substantially linear. Furthermore, with
reference to FIG. 3, although g
C ' was shown as having a
linear portion that had a cut off control voltage lower than the cut
off control voltage of the linear portion of g
L ', the cut off control voltage of the linear portion of g
C ' could be greater than the cut off voltage for the linear region of g
L
'. In addition, the gain control units and associate amplifiers
could be arranged to utilize voltages opposite in polarity to those
shown. These and other modifications are intended to be within the
scope of the invention.
e here:NORDMENDE SPECTRA SK2-COLOR TP9716 YEAR 1978.
(1885-1940) in Dresden. Following the destruction of the plant during the bombing raids in 1945, Martin Mende (the founder's son) created a new company in Bremen in 1947, in a former Focke-Wulf plant, under the name North German Mende Broadcast GmbH.
The name was subsequently changed to Nordmende: subsequently the
company became one of the prominent German manufacturers of radios,
televisions, tape recorders and record players in the 1950s and 1960s.
Nordmende
was well known for its televisions throughout Ireland during the
1970s and 1980s, the company bought the rights to the name and
launched a range of white goods including fridges, freezers, washing machines, and dishwashers, alongside a revamped range of flat-screen TVs and stereos.
Commons: Nordmende – Sammlung von Bildern, Videos und Audiodateien
