-
The IMPERIAL CHASSIS F960 (F960Z011B) was first IMPERIAL chassis
completely redesigned to switch off all previous models based around
TELEFUNKEN Chassis types.
- The chassis was used in models from 21 to 28 inches color screens and stereo or dual audio featured.
- The CHASSIS F960 (F960Z011B) was very reliable and durable offering
excellent features in a small market penetration and low cost final
product market also used in PHILCO and CGE brands with various CRT types and screen formats..
IMPERIAL 25BF88 YUMA CHASSIS F960 (F960Z011B) Supply is based on TDA4600 (SIEMENS).
What is a Flyback Transformer?
The
low cost, simplicity of design and intrinsic efficiency of flyback
transformers have made them a popular solution for power supply designs
of below 100W to 150W. Other advantages of the flyback transformer over
circuits with similar topology include isolation between primary and
secondary and the ability to provide multiple outputs and a choice of
positive or negative voltage for the output.
Flyback transformer, or,
line output transformers are a part of the power supplies in cathode
ray tubes. The flyback transformer generates a high voltage, as needed
by the CRT display or similar devices (e.g. plasma lamps). A flyback
transformer generates a voltage between a few kilovolts to 50 kilovolts
and uses high frequency switched currents between 17 kHz and 50 kHz.
The
chief difference between a flyback transformer and main/audio
transformer is that flybacks transfer as well as store energy, for a
just a fraction of an entire switching period. The secret behind that is
the coil winding on a ferrite core that has an air gap; it increases
the magnetic circuit reluctance for storing the energy.
The
reason it is called a flyback transformer is because the primary winding
uses a relatively low-voltage saw-tooth wave. The wave gets
strengthened first and then gets switched off abruptly; this causes the
beam to fly back from right to left on the display.
Applications
Cathode ray tube.
Televisions.
Plasma Lamps.
Any display requiring high voltage to operate and much more.
Power supply Description based on TDA4601d (SIEMENS)
TDA4601 Operation. * The TDA4601 device is a single in line, 9 pin chip. Its predecessor was the TDA4600 device, the TDA4601 however has improved switching, better protection and cooler running. The (SIEMENS) TDA4601 power supply is a fairly standard parallel chopper switch mode type, which operates on the same basic principle as a line output stage. It is turned on and off by a square wave drive pulse, when switched on energy is stored in the chopper transformer primary winding in the form of a magnetic flux; when the chopper is turned off the magnetic flux collapses, causing a large back emf to be produced. At the secondary side of the chopper transformer this is rectified and smoothed for H.T. supply purposes. The advantage of this type of supply is that the high chopping frequency (20 to 70 KHz according to load) allows the use of relatively small H.T. smoothing capacitors making smoothing easier. Also should the chopper device go short circuit there is no H.T. output. In order to start up the TDA4601 I.C. an initial supply of 9v is required at pin 9, this voltage is sourced via R818 and D805 from the AC side of the bridge rectifier D801, also pin 5 requires a +Ve bias for the internal logic block. (On some sets pin 5 is used for standby switching). Once the power supply is up and running, the voltage on pin 9 is increased to 16v and maintained at this level by D807 and C820 acting as a half wave rectifier and smoothing circuit. PIN DESCRIPTIONS Pin 1 This is a 4v reference produced within the I.C. Pin 2 This pin detects the exact point at which energy stored in the chopper transformer collapses to zero via R824 and R825, and allows Q1 to deliver drive volts to the chopper transistor. It also opens the switch at pin 4 allowing the external capacitor C813 to charge from its external feed resistor R810. Pin 3 H.T. control/feedback via photo coupler D830. The voltage at this pin controls the on time of the chopper transistor and hence the output voltage. Normally it runs at Approximately 2v and regulates H.T. by sensing a proportion of the +4v reference at pin 1, offset by conduction of the photo coupler D830 which acts like a variable resistor. An increase in the conduction of transistor D830 and therefor a reduction of its resistance will cause a corresponding reduction of the positive voltage at Pin 3. A decrease in this voltage will result in a shorter on time for the chopper transistor and therefor a lowering of the output voltage and vice versa, oscillation frequency also varies according to load, the higher the load the lower the frequency etc. should the voltage at pin 3 exceed 2.3v an internal flip flop is triggered causing the chopper drive mark space ratio to extend to 244 (off time) to 1 (on time), the chip is now in over volts trip condition. Pin 4 At this pin a sawtooth waveform is generated which simulates chopper current, it is produced by a time constant network R810 and C813. C813 charges when the chopper is on and is discharged when the chopper is off, by an internal switch strapping pin 4 to the internal +2v reference, see Fig 2. The amplitude of the ramp is proportional to chopper drive. In an overload condition it reaches 4v amplitude at which point chopper drive is reduced to a mark-space ratio of 13 to 1, the chip is then in over current trip. The I.C. can easily withstand a short circuit on the H.T. rail and in such a case the power supply simply squegs quietly. Pin 4 is protected by internal protection components which limit the maxi
mum voltage at this pin to 6.5v. Should a fault occur in either of the time constant components, then the chopper transistor will probably be destroyed. Pin 5 This pin can be used for remote control on/off switching of the power supply, it is normally held at about +7v and will cause the chip to enter standby mode if it falls below 2v. Pin 6 Ground. Pin 7 Chopper switch off pin. This pin clamps the chopper drive voltage to 1.6v in order to switch off the chopper. Pin 8 Chopper base current output drive pin. Pin 9 L.T. pin, approximately 9v under start-up conditions and 16v during normal running, Current consumption of the I.C. is typically 135mA. The voltage at this pin must reach 6.7v in order for the chip to start-up.
Semiconductor
circuit for supplying power to electrical equipment, comprising a
transformer having a primary winding connected, via a parallel
connection of a collector-emitter path of a transistor with a first
capacitor, to both outputs of a rectifier circuit supplied, in turn, by a
line a-c voltage; said transistor having a base controlled via a
second capacitor by an output of a control circuit acted upon, in turn
by the rectified a-c line voltage as actual value and by a reference
voltage; said transformer having a first secondary winding to which
the electrical equipment to be supplied is connected; said
transformer having a second secondary winding with one terminal
thereof connected to the emitter of said transistor and the other
terminal thereof connected to an anode of a first diode leading to
said control circuit; said transformer having a third secondary
winding with one terminal thereof connected, on the one hand, via a
series connection of a third capacitor with a first resistance, to
the other terminal of said third secondary winding and connected, on
the other hand, to the emitter of said transistor, the collector of
which is connected to said primary winding; a point between said
third capacitor and said first resistance being connected to the
cathode of a second diode; said control circuit having nine terminals
including a first terminal delivering a reference voltage and
connected, via a voltage divider formed of a third and fourth
series-connected resistances, to the anode of said second diode; a
second terminal of said control circuit serving for zero-crossing
identification being connected via a fifth resistance to said cathode
of said second diode; a third terminal of said control-circuit
serving as actual value input being directly connected to a divider
point of said voltage divider forming said connection of said first
terminal of said control circuit to said anode of said second diode; a
fourth terminal of said control circuit delivering a sawtooth
voltage being connected via a sixth resistance to a terminal of said
primary winding of said transformer facing away from said transistor;
a fifth terminal of said control circuit serving as a protective
input being connected, via a
seventh resistance to the cathode of
said first diode and, through the intermediary of said seventh
resistance and an eighth resistance, to the cathode of a third diode
having an anode connected to an input of said rectifier circuit; a
sixth terminal of said control circuit carrying said reference
potential and being connected via a fourth capacitor to said fourth
terminal of said control circuit and via a fifth capacitor to the
anode of said second diode; a seventh terminal of said control
circuit establishing a potential for pulses controlling said transistor
being connected directly and an eighth terminal of said control
circuit effecting pulse control of the base of said transistor being
connected through the intermediary of a ninth resistance to said first
capacitor leading to the base of said transistor; and a ninth
terminal of said control circuit serving as a power supply input of
said control circuit being connected both to the cathode of said first
diode as well as via the intermediary of a sixth capacitor to a
terminal of said second secondary winding as well as to a terminal of
said third secondary winding.
Description:
The
invention relates to a blocking oscillator type switching power
supply for supplying power to electrical equipment, wherein the
primary winding of a transformer, in series with the emitter-collector
path of a first bipolar transistor, is connected to a d-c voltage
obtained by rectification of a line a-c voltage fed-in via two
external supply terminals, and a secondary winding of the transformer
is provided for supplying power to the electrical equipment, wherein,
furthermore, the first bipolar transistor has a base controlled by
the output of a control circuit which is acted upon in turn by the
rectified a-c line voltage as actual value and by a set-point
transmitter, and wherein a starting circuit for further control of the
base of the first bipolar transistor is provided.
Such
a blocking oscillator switching power supply is described in the
German periodical, "Funkschau" (1975) No. 5, pages 40 to 44. It is well
known that the purpose of such a circuit is to supply electronic
equipment, for example, a television set, with stabilized and
controlled supply voltages. Essential for such switching power supply
is a power switching transistor i.e. a bipolar transistor with high
switching speed and high reverse voltage. This transistor therefore
constitutes an important component of the control element of the
control circuit. Furthermore, a high operating frequency and a
transformer intended for a high operating frequency are provided,
because generally, a thorough separation of the equipment to be
supplied from the supply naturally is desired. Such switching power
supplies may be constructed either for synchronized or externally
controlled operation or for non-synchronized or free-running operation.
A blocking converter is understood to be a switching power supply in
which power is delivered to the equipment to be supplied only if the
switching transistor establishing the connection between the primary
coil of the transformer and the rectified a-c voltage is cut off.
The power delivered by the line rectifier to the primary coil of the
transformer while the switching transistor is open, is interim-stored
in the transformer and then delivered to the consumer on the
secondary side of the transformer with the switching transistor cut
off.
In the blocking converter described in the aforementioned
reference in the literature, "Funkschau" (1975), No. 5, Pages 40 to
44, the power switching transistor is connected in the manner defined
in the introduction to this application. In addition, a so-called
starting circuit is provided. Because several diodes are generally
provided in the overall circuit of a blocking oscillator according to
the definition provided in the introduction hereto, it is necessary,
in order not to damage these diodes, that due to the collector peak
current in the case of a short circuit, no excessive stress of these
diodes and possibly existing further sensitive circuit parts can
occur.
Considering the operation of a blocking oscillator,
this means that, in the event of a short circuit, the number of
collector current pulses per unit time must be reduced. For this
purpose, a control and regulating circuit is provided.
Simultaneously, a starting circuit must bring the blocking converter
back to normal operation when the equipment is switched on, and after
disturbances, for example, in the event of a short circuit. The
starting circuit shown in the literature reference "Funkschau" on
Page 42 thereof, differs to some extent already from the conventional
d-c starting circuits. It is commonly known for all heretofore known
blocking oscillator circuits, however, that a thyristor or an
equivalent circuit replacing the thyristor is essential for the
operation of the control circuit.
It is accordingly an object
of the invention to provide another starting circuit. It is a further
object of the invention to provide a possible circuit for the
control circuit which is particularly well suited for this purpose. It
is yet another object of the invention to provide such a power
supply which is assured of operation over the entire range of line
voltages from 90 to 270 V a-c, while the secondary voltages and
secondary load variations between no-load and short circuit are
largely constant.
With the foregoing and other objects in
view, there is provided, in accordance with the invention, a blocking
oscillator-type switching power supply for supplying power to
electrical equipment wherein a primary winding of a transformer, in
series with an emitter-collector path of a first bipolar transistor,
is connected to a d-c voltage obtained by rectification of a line a-c
voltage fed-in via two external supply terminals, a secondary winding
of the transformer being connectible to the electrical equipment for
supplying power thereto, the first bipolar transistor having a base
controlled by the output of a control circuit acted upon, in turn, by
the rectified a-c line voltage as actual value and by a set-point
transmitter, and including a starting circuit for further control of
the base of the first bipolar transistor, including a first diode in
the starting circuit having an anode directly connected to one of the
supply terminals supplied by the a-c line voltage and a cathode
connected via a resistor to an input serving to supply power to the
control circuit, the input being directly connected to a cathode of a
second diode, the second diode having an anode connected to one
terminal of another secondary winding of the transformer, the other
secondary winding having another terminal connected to the emitter of
the first bipolar transmitter.
In accordance with another
feature of the invention, there is provided a second bipolar
transistor having the same conduction type as that of the first
bipolar transistor and connected in the starting circuit with the base
thereof connected to a cathode of a semiconductor
diode, the semiconductor diode having an anode connected to the
emitter of the first bipolar transistor, the second bipolar
transistor having a collector connected via a resistor to a cathode
of the first diode in the starting circuit, and having an emitter
connected to the input serving to supply power to the control circuit
and also connected to the cathode of the second diode which is
connected to the other secondary winding of the transformer.
In
accordance with a further feature of the invention, the base of the
second bipolar transistor is connected to a resistor and via the
latter to one pole of a first capacitor, the anode of the first diode
being connected to the other pole of the first capacitor.
In
accordance with an added feature of the invention, the input serving
to supply power to the control circuit is connected via a second
capacitor to an output of a line rectifier, the output of the line
rectifier being directly connected to the emitter of the first
bipolar transistor.
In accordance with an additional feature
of the invention, the other secondary winding is connected at one end
to the emitter of the first bipolar transistor and to a pole of a
third capacitor, the third capacitor having another pole connected,
on the one hand, via a resistor, to the other end of the other
secondary winding and, on the other hand, to a cathode of a third
diode, the third diode having an anode connected via a potentiometer
to an actual value input of the control circuit and, via a fourth
capacitor, to the emitter of the first bipolar transistor.
In
accordance with yet another feature of the invention, the control
circuit has a control output connected via a fifth capacitor to the
base of the first bipolar transistor for conducting to the latter
control pulses generated in the control circuit.
In accordance
with a concomitant feature of the invention, there is provided a
sixth capacitor shunting the emitter-collector path of the first
transistor.
Other features which are considered as characteristic for the invention are set forth in the appended claim.
Although
the invention is illustrated and described herein as embodied in a
blocking oscillator type switching power supply, it is nevertheless
not intended to be limited to the details shown, since various
modifications and structural changes may be made therein without
departing from the spirit of the invention and within the scope and
range of equivalents of the claims.
The construction and method of operation of the invention, however,
together with additional objects and advantages thereof will be best
understood from the following description of specific embodiments when
read in connection with the accompanying drawings, in which:
FIGS. 1 and 2 are circuit diagrams of the blocking oscillator type switching power supply according to the invention; and
FIG. 3 is a circuit diagram of the control unit RS of FIGS. 1 and 2.
Referring
now to the drawing and, first, particularly to FIG. 1 thereof, there is
shown a rectifier circuit G in the form of a bridge current, which is
acted upon by a line input represented by two supply terminals 1' and
2'. Rectifier outputs 3' and 4' are shunted by an emitter-collector path
of an NPN power transistor T1 i.e. t
he
series connection of the so-called first bipolar transistor referred to
hereinbefore with a primary winding I of a transformer Tr. Together
with the inductance of the transformer Tr, the capacitance C1 determines
the frequency and limits the opening voltages of the switch embodied by
the first transistor T1. A capacitance C2, provided between the base of
the first transistor T1 and the control output 7,8 of a control circuit
RS, separates the d-c potentials of the control or regulating circuit
RS and the switching transistor T1 and serves for addressing this
switching transistor T1 with pulses. A resistor R1 provided at the
control output 7,8 of the control circuit RS is the negative-feedback
resistor of both output stages of the control circuit RS. It determines
the maximally possible output pulse current of the control circuit RS. A
secondary winding II of the transformer Tr takes over the power supply
of the control circuit, in steady state operation, via the diode D1. To
this end, the cathode of this diode D1 is directly connected to a power
supply input 9 of the control circuit RS, while the anode thereof is
connected to one terminal of the secondary winding II. The other
terminal of the secondary winding II is connected to the emitter of the
power switching transistor T1.
The cathode of the diode D1 and,
therewith, the power supply terminal 9 of the control circuits RS are
furthermore connected to one pole of a capacitor C3, the other pole of
which is connected to the output 3' of the rectifier G. The capacitance
of this capacitor C3 thereby smoothes the positive half-wave pulses and
serves simultaneously as an energy storage device during the starting
period. Another secondary windi
ng
III of the transformer Tr is connected by one of the leads thereof
likewise to the emitter of the first transistor T1, and by the other
lead thereof via a resistor R2, to one of the poles of a further
capacitor C4, the other pole of which is connected to the
first-mentioned lead of the other secondary winding III. This second
pole of the capacitor C4 is simultaneously connected to the output 3' of
the rectifier circuit G and, thereby, via the capacitor C3, to the
cathode of the diode D1 driven by the secondary winding II of the
transformer Tr as well as to the power supply input 9 of the control
circuit RS and, via a resistor R9, to the cathode of a second diode D4.
The second pole of the capacitor C4 is simultaneously connected directly
to the terminal 6 of the control circuit RS and, via a further
capacitor C 6, to the terminal 4 of the control circuit RS as well as,
additionally, via the resistor R6, to the other output 4' of the
rectifier circuit G. The other of the poles of the capacitor C4 acted
upon by the secondary winding II is connected via a further capacitor C5
to a node, which is connected on one side thereof, via a variable
resistor R4, to the terminals 1 and 3 of the control circuit RS, with
the intermediary of a fixed resistor R5 in the case of the terminal 1.
On the other side of the node, the latter and, therefore, the capacitor
C5 are connected to the anode of a third diode D2, the cathode of which
is connected on the one hand, to the resistor R2 mentioned hereinbefore
and leads to the secondary winding III of the transformer Tr and, on the
other hand, via a resistor R3 to the terminal 2 of the control circuit
RS.
The nine terminals of the control circuit RS have the following purposes or functions:
Terminal
1 supplies the internally generated reference voltage to ground i.e.
the nominal or reference value required for the control or regulating
process;
Terminal 2 serves as input for the oscillations provided
by the secondary winding III, at the zero point of which, the pulse
start of the driving pulse takes place;
Terminal 3 is the control
input, at which the existing actual value is communicated to the
control circuit RS, that actual value being generated by the rectified
oscillations at the secondary winding III;
Terminal 4 is
responsive to the occurrence of a maximum excursion i.e. when the
largest current flows through the first transistor T1 ;
Terminal 5
is a protective input which responds if the rectified line voltage
drops too sharply; Terminal 6 serves for the power supply of the control
process and, indeed, as ground terminal;
Terminal 7 supplies the
d-c component required for charging the coupling capacitor C2 leading
to the base of the first transistor T1 ;
Terminal 8 supplies the control pulse required for the base of the first transistor T1 ; and
Terminal 9 serves as the first terminal of the power supply of the control circuit RS.
Further details of the control circuit RS are described hereinbelow.
The
capacity C3 smoothes the positive half-wave pulses which are provided
by the secondary winding II, and simultaneously serves as an energy
storage device during the starting time. The secondary winding III
generates the control voltage and is simultaneously used
as
feedback. The time delay stage R2 /C4 keeps harmonics and fast
interference spikes away from the control circuit RS. The resistor R3 is
provided as a voltage divider for the second terminal of the control
circuit RS. The diode D2 rectifies the control pulses delivered by the
secondary winding III. The capacity C5 smoothes the control voltage. A
reference voltage Uref, which is referred to ground i.e. the potential
of terminal 6 is present at the terminal 1 of the control circuit RS.
The resistors R4 and R5 form a voltage divider of the input-difference
control amplifier at the terminal 3. The desired secondary voltage can
be set manually via the variable resistor R4. A time-delay stage R6 /C6
forms a sawtooth rise which corresponds to the collector current rise of
the first bipolar transistor T1 via the primary winding I of the
transformer Tr. The sawtooth present at the terminal 4 of the control
circuit RS is limited there between the reference voltage 2 V and 4 V.
The voltage divider R7 /R8 (FIG. 2), brings to the terminal 5 of the
control circuit RS the enabling voltage for the drive pulse at the
output 8 of the control circuit RS.
The diode D4, together with
the resistor R9 in cooperation with the diode D1 and the secondary
winding II, forms the starting circuit provided, in accordance with the
invention. The operation thereof is as follows:
After the
switching power supply is switched on, d-c voltages build up at the
collector of the switching transistor T1 and at the input 4 of the
control circuit RS, as a function in time of the predetermined time
constants. The positive sinusoidal half-waves charge the capacitor C3
via the starting diode D4 and the starting resistor R9 in dependence
upon the time constant R9.C3. Via the protective input terminal 5 and
the resisto
r
R11 not previously mentioned and forming the connection between the
resistor R9 and the diode D1, on the one hand, and the terminal 5 of the
control circuit RS, on the other hand, the control circuit RS is biased
ready for switching-on, and the capacitor C2 is charged via the output
7. When a predetermined voltage value at the capacitor C3 or the power
supply input 9 of the control circuit RS, respectively, is reached, the
reference voltage i.e. the nominal value for the operation of the
control voltage RS, is abruptly formed, which supplies all stages of the
control circuit and appears at the output 1 thereof. Simultaneously,
the switching transistor T1 is switched into conduction via the output
8. The switching of the transistor T1 at the primary winding T of the
transformer Tr is transformed to the second secondary winding II, the
capacity C3 being thereby charged up again via the diode D1. If
sufficient energy is stored in the capacitor C3 and if the re-charge via
the diode D1 is sufficient so that the voltage at a supply input 9 does
not fall below the given minimum operating voltage, the switching power
supply then remains connected, so that the starting process is
completed. Otherwise, the starting process described is repeated several
times.
In FIG. 2, there is shown a further embodiment of the
circuit for a blocking oscillator type switching power supply, according
to the invention, as shown in FIG. 1. Essential for this circuit of
FIG. 2 is the presence of a second bipolar transistor T2 of the type of
the first bipolar transistor T1 (i.e. in the embodiments of the
invention, an npn-transistor), which forms a further component of the
starting circuit and is connected with the collector-emitter path
thereof between the resistor R9 of the starting circuit and the current
supply input 9 of the control circuit RS. The base of this second
transistor T2 is connected to a node which leads, on the one hand, via a
resistor R10 to one electrode of a capacitor C7, the other electrode of
which is connected to the anode of the diode D4 of the starting circuit
and, accordingl
y,
to the terminal 1' of the supply input of the switching power supply G.
On the other hand, the last-mentioned node and, therefore, the base of
the second transistor T2 are connected to the cathode of a Zener diode
D3, the anode of which is connected to the output 3' of the rectifier G
and, whereby, to one pole of the capacitor C3, the second pole of which
is connected to the power supply input 9 of the control circuit RS as
well as to the cathode of the diode D1 and to the emitter of the second
transistor T2. In other respects, the circuit according to FIG. 2
corresponds to the circuit according to FIG. 1 except for the resistor
R11 which is not necessary in the embodiment of FIG. 2, and the missing
connection between the resistor R9 and the cathode of the diode D1,
respectively, and the protective input 5 of the control circuit RS.
Regarding the operation of the starting circuit according to FIG. 2,
it can be stated that the positive sinusoidal half-wave of the line
voltage, delayed by the time delay stage C7, R10 drives the base of the
transistor T2 in the starting circuit. The amplitude is limited by the
diode D3 which is provided for overvoltage protection of the control
circuit RS and which is preferably incorporated as a Zener diode. The
second transistor T2 is switched into conduction. The capacity C3 is
charged, via the serially connected diode D4 and the resistor R9 and the
collector-emitter path of the transistor T2, as soon as the voltage
between the terminal 9 and the terminal 6 of the control circuit RS i.e.
the voltage U9, meets the condition U9 <[UDs -UBE (T2)].
Because
of the time constant R9.C3, several positive half-waves are necessary
in order to increase the voltage U9 at the supply terminal 9 of the
control circuit RS to such an extent that the control circuit RS is
energized. During the negative sine half-wave, a partial energy
chargeback takes place from the capacitor C3 via the emitter-base path
of the transistor T2 of the starting circuit and via the resistor R10
and the capacitor C7, respectively, into the supply network. At
approximately 2/3 of the voltage U9, which is limited by the diode D3,
the control circuit RS is switched on. At the terminal 1 thereof, the
reference voltage Uref then appears. In addition, the voltage divider R5
/R4 becomes effective. At the terminal 3, the control amplifier
receives the voltage forming the actual value, while the first bipolar
transistor T1 of the blocking-oscillator type switching power supply is
addressed pulsewise via the terminal 8.
Because the capacitor C6
is charged via the resistor R6, a higher voltage than Uref is present at
the terminal 4 if the control circuit RS is activated. The control
voltage then discharges the capacitor C6 via the terminal 4 to half the
value of the reference voltage Uref, and immediately cuts off the
addressing input 8 of the control circuit RS. The first driving pulse of
the switching transistor T1 is thereby limited to a minimum of time.
The power for switching-on the control circuit RS and for driving the
transistor T1 is supplied by the capacitor C3. The voltage U9 at the
capacitor C3 then drops. If the voltage U9 drops below the switching-off
voltage value of the control circuit RS, the latter is then
inactivated. The next positive sine half-wave would initiate the
starting process again.
By switching the transistor T1, a voltage
is transformed in the secondary winding II of the transformer Tr. The
positive component is rectified by the diode D1, recharing of the
capacitor C3 being thereby provided. The voltage U9 at the output 9 does
not, therefore, drop below the minimum value required for the operation
of the control circuit RS, so that the control circuit RS remains
activated. The power supply continues to operate in the rhythm of the
existing conditions. In operation, the voltage U9 at the supply terminal
9 of the control circuit RS has a value which meets the condition U9
>[UDs -UBE (T2)], so that the transistor T2 of the starting circuit
remains cut off.
For the internal layout of the control circuit
RS, the construction shown, in particular, from FIG. 3 is advisable.
This construction is realized, for example, in the commercially
available type TDA 4600 (Siemens AG).
The block diagram of the control circuit according to FIG. 3
shows
the power supply thereof via the terminal 9, the output stage being
supplied directly whereas all other stages are supplied via Uref. In the
starting circuit, the individual subassemblies are supplied with power
sequentially. The d-c output voltage potential of the base current gain
i.e. the voltage for the terminal 8 of the control circuit RS, and the
charging of the capacitor C2 via the terminal 7 are formed even before
the reference voltage Uref appears. Variations of the supply voltage U9
at terminal 9 and the power fluctuations at the terminal 8/terminal 7
and at the terminal 1 of the control circuit RS are leveled or smoothed
out by the voltage control. The temperature sensitivity of the control
circuit RS and, in particular, the uneven heating of the output and
input stages and input stages on the semiconductor chip containing the
control circuit in monolithically integrated form are intercepted by the
temperature compensation provided. The output values are constant in a
specific temperature range. The message for blocking the output stage,
if the supply voltage at the terminal 9 is too low, is given also by
this subassembly to a provided control logic.
The outer voltage divider of the terminal 1 via the r
esistors
R5 and R4 to the control tap U forms, via terminal 3, the variable side
of the bridge for the control amplifier formed as a differential
amplifier. The fixed bridge side is formed by the reference voltage Uref
via an internal voltage divider. Similarly formed are circuit portions
serving for the detection of an overload short circuit and circuit
portions serving for the "standby" no-load detection, which can be
operated likewise via terminal 3.
Within a provided trigger
circuit, the driving pulse length is determined as a function of the
sawtooth rise at the terminal 4, and is transmitted to the control
logic. In the control logic, the commands of the trigger circuit are
processed. Through the zero-crossing identification at input 2 in the
control circuit RS, the control logic is enabled to start the control
input only at the zero point of the frequency oscillation. If the
voltages at the terminal 5 and at the terminal 9 are too low, the
control logic blocks the output amplifier at the terminal 8. The output
amplifier at the terminal 7 which is responsible for the base charge in
the capacitor C2, is not touched thereby.
The base current gain
for the transistor T1 i.e. for the first transistor in accordance with
the definition of the invention, is formed by two amplifiers which
mutually operate on the capacitor C2. The roof inclination of the base
driving current for the transistor T1 is impressed by the collector
current simulation at the terminal 4 to the amplifier at the terminal 8.
The control pulse for the transistor T1 at the terminal 8 is always
built up to the potential present at the terminal 7. The amplifier
working into the terminal 7 ensures that each new switching pulse at the
terminal 8 finds the required base level at terminal 7.
Supplementing
the comments regarding FIG. 1, it should also be mentioned that the
cathode of the diode D1 connected by the anode thereof to the one end of
the secondary winding II of the transformer Tr is connected via a
resistor R11 to the protective input 5 of the control circuit RS
whereas, in the circuit according to FIG. 2, the protective input 5 of
the control circuit RS is supplied via a voltage divider R8, R7 directly
from the output 3', 4' of the rectifier G delivering the rectified line
a-c voltage, and which obtains the voltage required for executing its
function. It is evident that the first possible manner of driving the
protective input 5 can be used also in the circuit according to FIG. 2,
and the second possibility also in a circuit in accordance with FIG. 1.
The
control circuit RS which is shown in FIG. 3 and is realized in detail
by the building block TDA 4600 and which is particularly well suited in
conjunction with the blocking oscillator type switching power supply
according to the invention has 9 terminals 1-9, which have the following
characteristics, as has been explained in essence hereinabove:
Terminal
1 delivers a reference voltage Uref which serves as the
constant-current source of a voltage divider R5.R4 which supplies the
required d-c voltages for the differential amplifiers provided for the
functions control, overload detection, short-circuit detection and
"standby"-no load detection. The dividing point of the voltage divider
R5 -R4 is connected to the terminal 3 of the control circuit RS. The
terminal 3 provided as the control input of RS is controlled in the
manner described hereinabove as input for the actual value of the
voltage to be controlled or regulated by the secondary winding III of
the transformer Tr. With this input, the lengths of the control pulses
for the switching transistor T1 are determined.
Via the input
provided by the terminal 2 of the control circuit RS, the zero-point
identification in the control circuit is addressed for detecting the
zero-point o
f
the oscillations respectively applied to the terminal 2. If this
oscillation changes over to the positive part, then the addressing pulse
controlling the switching transistor T1 via the terminal 8 is released
in the control logic provided in the control circuit.
A
sawtooth-shaped voltage, the rise of which corresponds to the collector
current of the switching transistor T1, is present at the terminal 4 and
is minimally and maximally limited by two reference voltages. The
sawtooth voltage serves, on the one hand as a comparator for the pulse
length while, on the other hand, the slope or rise thereof is used to
obtain in the base current amplification for the switching transistor
T1, via the terminal 8, a base drive of this switching transistor T1
which is proportional to the collector current.
The terminal 7 of
the control circuit RS as explained hereinbefore, determines the
voltage potential for the addressing pulses of the transistor T2. The
base of the switching transistor T1 is pulse-controlled via the terminal
8, as described hereinbefore. Terminal 9 is connected as the power
supply input of the control circuit RS. If a voltage level falls below a
given value, the terminal 8 is blocked. If a given positive value of
the voltage level is exceeded, the control circuit is activated. The
terminal 5 releases the terminal 8 only if a given voltage potential is
present.
Forei
gn References:
DE2417628A1 1975-10-23 363/37
DE2638225A1 1978-03-02 363/49
Other References:
Grundig Tech. Info. (Germany), vol. 28, No. 4, (1981).
IBM Technical Disclosure Bulletin, vol. 19, No. 3, pp. 978, 979, Aug. 1976.
German Periodical, "Funkschau", (1975), No. 5, pp. 40 to 44.
Inventors:
Peruth, Gunther (Munich, DE) Siemens Aktiengesellschaft (Berlin and Munich, DE)
TDA8185 HORIZONTAL AND VERTICAL PROCESSOR
DESCRIPTION
The TDA8185I is a monolithic integrated circuit in
24 pins dual in line plastic package intended for TV
signal processing and driving Horizontal and Vertical
output stages. It was specially designed for
VCR working conditions.
503kHz REFERENCE OSCILLATOR .5.5V SUPPLY VOLTAGE INTERNALLY
REGULATED .VERY SOPHISTICATED SYNC. SEPARATOR .
COUNTDOWN TIMING LOGIC .ADAPTS AUTOMATICALLY TO 625
LINE/50Hz AND 525 LINE/60Hz STANDARDS .50/60 Hz IDENTIFICATION OUTPUT .AUTOMATIC VERTICAL AMPLITUDE CORRECTION
50/60Hz .CRT PROTECTION CIRCUIT .PHASE-CORRECTED HORIZONTAL OUTPUT
WITH CONSTANT DUTY CYCLE
- Video chrominance and Luminance with TDA3562A,
TDA3562A
TDA3562A (Philips)PAL/NTSC ONE-CHIP DECODER, DESCRIPTION
The TDA3562A is a monolithic IC designed as
decode PAL and/or NTSC colour television standards
and it combines all functions required for the
identification and demodulation of PAL and NTSC
signals.
.CHROMINANCE SIGNAL PROCESSOR
.LUMINANCE SIGNAL PROCESSING WITH
CLAMPING
.HORIZONTAL AND VERTICAL BLANKING
.LINEAR TRANSMISSION OF INSERTED
RGB SIGNALS
.LINEAR CONTRAST AND BRIGHTNESS
CONTROL ACTING ON INSERTED AND MATRIXED
SIGNALS
.AUTOMATIC CUT-OFF CONTROL
.NTSC HUE CONTROL
FEATURES:
· A black-current stabilizer which
controls the black-currents of the
three electron-guns to a level low
enough to omit the black-level
adjustment
· Contrast control of inserted RGB
signals
· No black-level disturbance when
non-synchronized external RGB
signals are available on the inputs
· NTSC capability with hue control.
APPLICATIONS
· Teletext/broadcast antiope
· Channel number display.
GENERAL DESCRIPTION
It follows that the
external switches and filters which
are required for the TDA3562A are
not required for the TDA3566A.
There is no difference between the
amplitudes of the colour output
signals in the PAL or NTSC mode.
· The clamp capacitor at pins 10, 20
and 21 in the black-level
stabilization loop can be reduced to
100 nF provided the stability of the
loop is maintained. Loop stability
depends on complete application.
The clamp capacitors receive a
pre-bias voltage to avoid coloured
background during switch-on.
· The crystal oscillator circuit has
been changed to prevent parasitic
oscillations on the third overtone of
the crystal. Consequently the
optimum tuning capacitance must
be reduced to 10 pF.
· The hue control has been improved
(linear)
.CHROMINANCE SIGNALPROCESSOR .LUMINANCE SIGNAL PROCESSING WITH
CLAMPING .HORIZONTAL AND VERTICAL BLANKING .LINEAR TRANSMISSION OF INSERTED
RGB SIGNALS .LINEAR CONTRAST AND BRIGHTNESS
CONTROL ACTING ON INSERTED AND MATRIXED
SIGNALS .AUTOMATIC CUT-OFF CONTROL .NTSC HUE CONTROL
DESCRIPTION
The TDA3562A is a monolithic IC designed as
decode PAL and/or NTSC colour television standards
and it combines all functions required for the
identification and demodulation of PAL and NTSC
signals.
THE PHILIPS TDA3562A Circuit arrangement for the control of a picture tube :
1. Circuit arrangeme
nt for the control of at least one beam current in a picture tube by a picture comprising
a control loop which in one sampling interval obtains a measuring
signal from the value of the beam current on the occurrence of a given
reference level in the picture signal, stores a control signal derived
therefrom until the next sampling interval and thereby adjusts the beam
current to a value preset by a reference signal.
and a trigger
circuit which suppresses auxiliary pulses used to generate the beam
current after the picture tube has been started up and issues a
switching signal for the purpose of closing the control loop during the
sampling intervals and for releasing the control of the beam current by
the picture signal after the measuring signal has exceeded the threshold
value,
a change detection arrangement which delivers a change
signal when the stored signal has assumed a largely constant value, and
a logic network which does not release the control of the beam current
by the picture signal outside the sampling intervals until the change
signal has also been issued after the switching signal.
2. Circuit arrangement as set forth in claim 1, in
which the picture signal comprises several color signals for the control
of a corresponding number of beam currents for the display of a color
picture in the picture tube and the control loop stores a part measuring
signal or a part control signal derived therefrom for each color
signal, characterized in that the change detection arrangement includes a
change detector for each color signal which delivers a part change
signal when the relevant stored signal has assumed a largely constant
value, and the logic network does not release the control of the beam
currents by the color signals outside the sampling intervals until the
part change signals have been delivered by all change detectors.
3. Circuit arrangement as set forth in claim 1,
including a comparator arrangement which compares the measuring signal
with the reference signal and derives the control signal from this
comparison, characterized in that the change detection arrangement
detects a change in the control signal with respect to time and issues
the change signal when the control signal has assumed a largely constant
value.
4. Circuit arrangement as set forth in claims 1, 2, 3
including a control signal memory which contains at least one
capacitor, characterized in that the change detection arrangement
delivers the change signal when a charge-reversing current of the
capacitor occuring during the starting up of the picture tube falls
below a limit value.
5. Circuit arrangement as set forth in claim 2,
including a comparator arrangement which compares the measuring signal
with the reference signal and derives the control signal from this
comparison, characterized in that the change detection arrangement
detects a change in the control signal with respect to time and issues
the change signal when the control signal has assumed a largely constant
value.
Description:
BACKGROUND OF THE INVENTION
The invention
relates to a circuit arrangement for the control of at least one beam
current in a picture tube by a picture signal with a control loop which
in one sampling interval obtains a measuring signal from the value of
the beam current on the occurrence of a given reference level in the
picture signal, stores a control signal derived therefrom until the next
sampling interval and by this means adjusts the beam current to a value
preset by a reference signal, and with a trigger circuit which
suppresses auxiliary pulses used to generate the beam current after the
picture tube is turned on and issues a switching signal for the purpose
of closing the control loop during the sampling intervals and releasing
the control of the beam current by the picture signal after the
measuring signal has exceeded a threshold value.
Such a circuit
arrangement has been described in Valvo Technische Information 820705
with regard to the integrated color decoder circuit PHILIPS TDA3562A and is
used in this as a so-called cut-off point control. In the known circuit
arrangement, such a cut-off point control provides automatic
compensation of the so-called cut-off point of the picture tube, i.e. it
regulates the beam current in the picture tube in such a way that for a
given reference level in the picture signal the beam current has a
constant value despite tolerances and changes with time (aging, thermal
modifications) in the picture tube and the circuit arrangement, thereby
ensuring correct picture reproduction.
Such a blocking point
control is part
icularly advantageous for the operation of a picture tube
for the display of color pictures because in this case there are
several beam currents for different color components of the color
picture which have to be in a fixed ratio with one another. If this
ratio changes, for example, as the result of manufacturing tolerances or
ageing processes, distortions of the colors occur in the reproduction
of the color picture. The beam currents, therefore, have to be very
accurately balanced. The said cut-off point control prevents expensive
adjustment and maintenance time which is otherwise necessary.
Conventional
picutre tubes are constructed as cathode-ray tubes with hot cathodes
which require a certain time after being turned on for the hot cathodes
to heat up. Not until a final operating temperature has been reached do
these hot cathodes emit the desired beam currents to the full extent,
while gradually rising beam currents occur in the time interval when the
hot cathodes are heating up. The instantaneous values of these beam
currents depend on the instantaneous temperatures of the hot cathodes
and on the accelerating voltages for the picture tube which build up
simultaneously with the heating process and are undefined until the end
of the heating time. After the picture tube is turned on, these values
initially produce a highly distorted picture until the beam currents
have attained their final value. These picture distortions after the
picture tube is turned on are even further intensified by the fact that
the cut-off point control is not yet adjusted to the beam currents which
flow after the heating time is over.
For the purpose of
suppressing distorted pictures during the heating time of the hot
cathodes, the known circuit arrangement has a turn-on delay element
operating as a trigger circuit which, in essence, contains a bistable
flip-flop. When the picture tube and the circuit arrangement controlling
the beam currents flowing in it are turned on, the flip-flop is
switched into a first state in which it interrupts the supply of the
picture signal to the picture tube. Thus, during the heating time the
beam currents are suppressed, and the picture tube does not yet display
any picture. In sampling intervals which are provided subsequent to
flybacks of the cathode beam into an initial position on the changeover
from the display of one picture to the display of a subsequent picture
and even within the changeover, that is outside the display of pictures,
the picture tube is controlled for a short time in such a way that beam
currents occur when the hot cathodes are sufficiently heated up and an
accelerating voltage is resent. If these currents exceed a certain
threshold value, the flip-flop circuit switches into a second state and
releases the picture signal for the control of the beam currents and the
cut-off point control.
It is found, however, that the picture
displayed in the picture tube immediately after the switching over of
the flip-flop is still not fault-free. Because, in fact, the beam
currents are supported during the heating time of the hot cathodes, the
cut-off point control cannot respond yet. This response of the cut-off
point control takes place only after the beam currents are switched on,
i.e. after the flip-flop is switched into the second state and therefore
at a time in which the picture signal already controls the beam
currents. In this way the response of the blocking point control makes
its presence felt in the picture displayed.
With the known
circuit arrangement the brightness of the picture gradually increases,
during the response of the cut-off point control, from black to the
final value.
This slow increase in the picture brightness after
the tube is turned on is disturbing to the eyes of the viewer not only
in the case of the black-and-white picture tubes with one hot cathode,
but especially so in the case of colour picture tubes which usually have
three hot cathodes. With a color picture tube, color purity errors can
also occur in addition to the change in the picture brightness if, as a
result of different speeds of response of the cut-off point control for
the three beam currents, there are found to be intermittent variations
from the interrelation between the beam currents required for a correct
picture reproduction.
SUMMARY OF THE INVENTION
The
aim of the invention is to create a circuit arrangement which
suppresses the above-described disturbances of brightness and color of
the displayed picture when the picture tube is being started.
The
invention achieves this aim in that a circuit arrangement of the type
mentioned in the preamble contains a change detection arrangement which
emits a change signal when the stored signal has assumed an essentially
constant value, and a logic network which does not release the control
of the beam current by the picture signal until the change signal has
also been emitted after the switching signal.
In the circuit
arrangement according to the invention, therefore, the display of the
picture is suppressed after the picture tube is turned on until the
cut-off point control has responded. If the picture signal then starts
to control the beam current, a perfect picture is displayed immediately.
In this way, all the disturbances of the picture which affect the
viewer's pleasure are suppressed. The circuit arrangement of the
invention is of simple design and can be combined on one semiconductor
wafer with the existing picture signal processing circuits and also,
for
example, with the known circuit arrangement for cut-off point control.
Such an integrated circuit arrangement not only requires very little
space on the semiconductor wafer, but also needs no additional external
leads. Thus the circuit arrangement of the invention can be arranged,
for example, in an integrated circuit which has precisely the same
external connections as known integrated circuits. This means that an
integrated circuit containing the circuit arrangement of the invention
can be directly incorporated in existing equipment without the need for
additional measures.
In one embodiment of the said circuit
arrangement, in which the picture signal contains several color signals
for the control of a corresponding number of beam currents for
representing a color picture in the picture tube and, for each color
signal, the control loop stores a part measuring signal or a part
control signal derived from it, the change detection arrangement
contains a change detector for each color signal which emits a part
change signal when the relevant stored signal has assumed an essentially
constant value, and the logic network does not release the control of
the beam currents by the color signals outside the sampling intervals
until the part change signals have been emitted from all change
detectors.
In principle, therefore, such a circuit arrangement
has three cut-off point controls for the three beam currents controlled
by the individual color signals. To reduce the cost of the circuitry,
the measuring stage is common to all the cut-off point controls, as in
the known circuit arrangement. All three beam currents are then measured
successively by this measuring stage. In this way, a part measuring
signal or a part control signal derived from it is obtained for each
beam current and is stored sesparately according to which of the beam
currents it belongs. Changes in the part measuring signal or part
control signal are detected for each beam current by one of the change
detectors each time. Each of these change detectors issues a part change
signal to the logic network. The latter does not release the control of
the beam currents by the picture signal outside the sampling intervals
until all the part change signals indicate that the part measuring
signal or the part control signal, as the case may be, remains constant.
This ensures that the cut-off point controls for the beam currents of
all color signals have responded when the picture appears in the picture
tube.
In a further embodiment of the circuit arrangement
accord
ing to the invention with a comparator arrangement which compares
the measuring signal with the reference signal and derives the control
signal from this comparison, the change detection arrangement detects a
change in the control signal with respect to time and issues the change
signal when the control signal has assumed an essentially constant
value. In the case of the representation of a color signal the
comparator arrangement derives several part control signals, whose
changes with time are detected by the change detectors, from a
corresponding comparison of the part measuring signals with the
reference signal. In this embodiment of the circuit arrangement of the
invention, preference is given to storage of only the control signal or
the part control signals for the purpose of controlling the beam
currents.
In another embodiment of the circuit arrangement of the
invention which includes a control signal memory which contains at
least one capacitor in which a charge or voltage corresponding to the
control signal is stored, the change detection arrangement issues the
change signal when a charge-reversing current of the capacitor occurring
during the turning on of the picture tube has fallen below a limit
value and has thus at least largely decayed. Such a detection of the
steady state of the cut-off point control is independent of the actual
magnitude of the control signal and therefore independent of, for
example, the level of the picture tube cut-off voltage, circuit
tolerances or ageing processes in the circuit arrangement or the picture
tube.
Detection of whether or not the charge-reversing current
exceeds the limit value is performed preferentially by a current
detector which is designed with a current mirror system which is
arranged in a supply line to a capacitor acting as a control signal
store. A current mirror arrangement of this kind supplies a current
which coincides very precisely with the charging current of the
capacitor. This current is then compared, preferably in a further device
contained in the change detection arrangement, with a current
representing a limit value or, after conversion into a voltage, with a
voltage representing the limit value. The change signal is obtained from
the result of this comparison.
On the other hand, digital
memories may also be used as control signal memories, especially when
the picture signal is supplied as a digital signal and the blocking
point control is constructed as a digital control loop. In such a case,
the comparator arrangement, the change detection arrangement and the
trigger circuit are also designed as digital circuits. Then, the change
detection arrangement advantageously forms the difference of the signals
stored in the control signal memory in two successive sampling
intervals and compares this with the limit value formed by a digital
value. If the difference falls short of the limit value, the change
signal is issued.
BRIEF DESCRIPTION OF THE DRAWINGS
An embodiment of the invention is described in greater detail below with the aid of the drawings in which:
FIG. 1 shows a block circuit diagram of the embodiment,
FIG. 2 shows a somewhat more detailed block circuit diagram of the embodiment,
FIG. 3 shows time-dependency diagrams of some signals occurring in the circuit diagram shown in FIG. 2, and
FIG. 4 shows a somewhat moredetailed block circuit diagram of a part of the circuit diagram shown in FIG. 2.
DETAILED DESCRIPTION OF THE INVENTION
FIG.
1 shows a block circuit diagram of a circuit arrangement to which a
picture signal is fed via a first input 1 of a combinatorial stage 2.
From the output 3 of the combinatorial stage 2 the picture signal is fed
to the picture signal input of a controllable amplifier 5 which at an
output 6 issues a current controlled by the picture signal. This current
is fed via a measuring stage 7 to a hot cathode 8 in a picture tube 9
and forms therein a beam current of a cathode ray by means of which a
picture defined by the picture signal is displayed on a fluorescent
screen of the picture tube 9.
The measuring stage 7 measures the
current fed to the hot cathode 8, i.e. the the beam current in the
picture tube 9, and at a measuring signal output 10, issues a measuring
signal corresponding to the magnitude of this current. This is fed to a
measuring signal input 11 of a comparator arrangement 12 to which a
reference signal is supplied at a reference signal input 13. In a
preferably periodically recurring sampling interval during the
occurrence of a given reference level in the picture signal, the
comparator arrangement 12 forms a control signal from the value of the
measuring signal fed to the measuring signal input 11 at this time, on
the one hand, and the reference signal, on the other, by means of
substraction and delivers this at a control signal output 14. From there
the control signal is fed to an input 15 of a control signal memory 16
and is stored in the latter. The control signal is fed via an output 17
of the control signal memory 16 to a second input 18 of combinatorial
stage 2 in which it is combined with the picture signal, e.g. added to
it.
The combinatorial stage 2, the controllable amplifier 5, the
measuring stage 7, the comparator arrangement 12 and the control signal
memory 16 form a control loop with which the beam current is guided
towards the reference signal in the sampling interval during the
occurrence of the reference level in the picture signal. For the
reference
level, use is made in particular of a black level or a level
with small, fixed distance from the black level, i.e. a value in the
picture signal which produces a black or almost back picture area in the
displayed picture in the picture tube. In this case the control loop,
as described, forms a cut-off point control for the picture tube. If the
reference level is away from the black level, the control loop is also
designated as quasi-cut-off-point control.
The circuit
arrangement as shown in FIG. 1 also has a trigger circuit 19 to which
the measuring signal from the measuring signal output 10 of measuring
stage 7 is fed at a measuring signal input 20. When the circuit
arrangement and therefore the picture tube are turned on, the trigger
circuit 19 is set in a first state in which by means of a first
connection 21 it blocks the comparator arrangement 12 in such a way that
the latter delivers no control signal or a control signal with the
value zero at its control signal output 14. This prevents the control
signal memory 16 from storing undefined values for the control signal at
the moment of turning on or immediately thereafter.
The circuit
arrangement shown in FIG. 1 also has a logic network 22 which is
connected via a second connection 23, by means of which a switching
signal is supplied, with the trigger circuit 10 and via a third
connection 24 with the controllable amplifier 5. Like the trigger
circuit 19, the logic network 22 also finds itself controlled, when the
circuit arrangement is being turned on, by the switching signal in a
first stage in which by way of the third connection 24 it blocks the
controllable amplifier 5 with a blocking signal in such a way that no
beam currents controlled by the picture signal can yet flow in the
picture tube 9. Thus the picture tube 9 is blanked; no picture is
displayed yet.
When picture tube 9 is turned on, the hot cathode 8
is still cold so that no beam current can flow anyhow. The hot cathode 8
is then heated up and, after a certain time, begins gradually to emit
electrons as the result of which a cathode ray and therefore a beam
current can form. However, during the heating up of the hot cathode 8,
and because the cut-off point control has not yet responded, this would
be undefined and is therefore suppressed by the controllable amplifier
5. Only in time intervals which are provided immediately subsequent to
flybacks of the cathode rays into an initial position at the changeover
from the display of one image to that of a subsequent image, but even
before the start of the display of the subsequent image, the
controllable amplifier 5 delivers a voltage in the form of an auxiliary
pulse for a short time at its output 6, and when the hot cathode 8 in
the picture tube 9 is heated up sufficiently, this voltage produces a
beam current. The time interval for the delivery of this voltage is
selected in such a way that a cathode ray produced by its does not
produce a visibl
e image in the picture tube 9, and coincides for example
with the sampling interval.
The measuring stage 7 measures the
short-time cathode current produced in the manner described and, at its
measuring signal output 10, delivers a corresponding measuring signal
which is passed via measuring signal output 20 to the trigger circuit
19. If the measuring signal exceeds a definite preset threshold value,
the trigger circuit 19 is switched into a second state in which it
releases the comparator arrangement 12 via the first connection 12 and,
by means of the second connection 23, uses the switching signal to also
bring the logic network 22 into a second state. The comparator
arrangement 12 now evaluates the measuring signal supplied to it via the
measuring signal input 11, i.e. it forms the control signal as the
difference between the measuring signal and the reference signal
supplied via the reference signal input 13. The control signal is
transferred via the control signal output 14 and the input 15 into the
control signal memory 16. It is subsequently fed via the output 17 of
the control signal memory 16 to the second input 18 of the combinatorial
stage 2 and is there combined with the picture signal at the first
input 1, e.g. is superimposed on it by addition. This superimposed
picture signal is fed to the picture signal input 4 of the controllable
amplifier 5 via the output 3 of the combinatorial stage 2.
In the
second state of the logic network 22 the controllable amplifier 5 is
switched via the third connection 24 by the blocking signal in such a
way that the picture signal controls the beam currents only during the
sampling intervals and that, for the rest, no image appears yet in the
picture tube. The cut-off point control now gebins to respond, i.e. the
value of the control signal is changed by the control loop comprising
the combinatorial stage 2, the controllable amplifier 5, the measuring
stage 7, the comparator arrangement 12 and the control signal me
mory 16
until such time as the beam current in the picture tube 9 at the
blocking point or at a fixed level with respect to it is adjusted to a
value preset by the reference signal. For this purpose the sampling
interval, in which the picture signal controls the beam current via the
controllable amplifier 5 is selected in such a way that within it the
picture signal just assumes a value corresponding to the cut-off point
or to a fixed level with respect to it.
During the response of
the cut-off point control the control signal fed to the control signal
memory 16 changes continuously. Between the control signal output 14 of
the comparator arrangement 12 and the input 15 of the control signal
memory 16 is inserted a changed detection arrangement 25 which detects
the variations of the control signal. When the cut-off point control has
responded, i.e. the control signal has assumed a constant value, the
change detection arrangement 25 delivers a change signal at an output 26
which indicates that the steady stage of the cut-off point control is
achieved and the said signal is fed to a change signal input 27 of the
logic network 22. The logic network then switches into a third state in
which via the third connection 24 it enables the controllable amplifier 5
in such a way that the beam currents are now controlled without
restriction by the picture signal. Thus a correctly represented picture
appears in the picture tube 9.
A shadow-like representation of
individual constituents of the circuit arrangement in FIG. 1 is used to
indicate a modification by which this circuit arrangement is equipped
for the representation of color pictures in the picture tube 9. For
example, three color signals are fed in this case as the picture signal
via the input 1 to the combinatorial stage 2. Accordingly, the input 1
is shown in triplicate, and the combinatorial stage 2 has a logic
element, e.g. an adder, for example of these color signals. The
controllable amplifier 5 now has three amplifier stages, one for each of
the color signals, and the picture tube now contains three hot cathodes
8 instead of one so that three independent cathode rays are available
for the three color signals.
However, to simplify the circuit
arrangement and to save on components, only one measuring stage 7 is
provided which measures all three beam currents successively. Also, the
comparator arrangement 12 forms part control signals from the
successively arriving part measuring signals for the individual beam
currents with the reference signal, and these part control signals are
allocated to the individual color signals and passed on to three storage
units which are contained in the control signal memory 16. From there,
the part control signals are sent via the second input 18 of the
combinatorial stage 2 to the assigned logic elements.
The circuit
arrangement thus forms three independently acting control loops for the
cut-off point control of the individual color signals, in which case
only the measuring stage 7 and to some extent at least the comparator
arrangement 12 are common to these control loops.
The change
detection arrangement 25 now has three change detectors each of which
detects the changes with time of the part control signals relating to a
color signal. Then via the output 26 each of these change detectors
delivers a part change signal to the change signal input 27 of the logic
network 22. These part change signals occur independently of one
another when the relevent control loop has responded. The logic network
22 evaluates all three part change signals and does not switch into its
third stage until all part change signals indicate a steady state of the
control loops. Only then, in fact, is it ensured that all the color
signals from the beam currents controlled by them are correctly
reproduced in the picture tube, and thus no distortions of the displayed
image, especially no color purity errors, occur. The color picture
displayed then immediately has the correct brightness and color on its
appearance when the picture tube is turned on.
FIG. 2 shows a
somewhat more detailed block circuit diagram of an embodiment of a
circuit arrangement equipped for the processing of a picture signal
containing three colour signals. Three color signals for the
representation of the colors red, green and blue are fed to this circuit
arrangement via three input terminals 101, 102, 103. A red color signal
is fed via the first input terminal 101 to a first adder 201, a green
colour signal is fed via the second input terminal to a second adder
202, and a blue colour signal is fed via the third input terminal 103 to
a third adder 203. From outputs 301, 302 and 303 of the adders 201,
202, 203 the color signals are fed to amplifier stages 501, 502 and 503
respectively. Each of the amplifier stages contains a switchable
amplifier 511, 512 and 513, an output amplifier 521, 522 and 523 as well
as a measuring transistor 531, 532 and 533 respectively. The emitters
of these measuring transistors 531, 532, 533 are each connected to a hot
cathode 801, 802, 803 of the picture tube 9 and deliver the cathode
currents, whereas the collectors of measuring transistors 521, 532, 533
are connected to
one another and to a first terminal 701 of a measuring
resistor 702 the second terminal of which 703 is connected to earth. The
current gain of the measuring transistors 531, 532 and 533 is so great
that their collector currents coincide almost with the cathode currents.
By measuring the voltage drop produced by the cathode currents at the
measuring resistor 802 it is then possible to measure the cathode
currents and therefore the beam currents in the picture tube 9 with
great accuracy.
The falling voltage at the measuring resistor 702
is fed as a measuring signal to an input 121 of a buffer amplifier 120
with a gain factor of one, at the output 122 of which the unchanged
measuring signal is therefore available at low impedance. From there it
is fed to a first terminal 131 of a reference voltage source 130 which
is connected with its second terminal 132 to inverting inputs 111, 112
and 113 of three differential amplifiers 123, 124, 125 respectively. The
differential amplifiers 123, 124, 125 also each have a non-inverting
input 114, 115, and 116 respectively. These are connected to each other
at a junction 117, to earth via a leakage current storage capacitor 126
and to the output 122 of the buffer amplifier 120 via decoupling
resistor 118 and a leakage current sampling switch 119. In addition, the
input 121 of the buffer amplifier 120 can be connected to earth via a
short-circuiting switch 127.
From outputs 141, 142, and 143
respectively of the differential amplifiers 123, 124 and 125, part
control signals relating to the individual color signals are fed in the
form of electrical voltages (or, in some cases, charge-reversing
currents) via control signal sampling switches 154, 155 and 156, in the
one instance, to first terminals 151, 152 and 153 respectively of
control signal storage capacitors 161, 162, 163 which form the storage
units of the control signal memory 16 and store inside them charges
corresponding to these voltages (or formed by the charge-reversing
currents). In the other instance, the part control signals are fed to
second inputs 181, 182 and 183 of the first, second or third adders 201,
202, 203 respectively and are added therein to the color signals from
the first, second or third input terminals 101, 102 or 103 respectively.
The operation of the comparator arrangement 12 which consists
mainly of the buffer amplifier 120, the reference voltage source 130 and
differential amplifiers 123, 124, 125 will be explained below with the
aid of the pulse diagrams in FIG. 3. FIG. 3a shows a horizontal blanking
signal for a television signal which, as the picture signal, controls
the beam currents in the picture tube 9. In this diagram, H represents
horizontal blanking pulses which follow one another in the picture
signal at the time interval of one line duration and by means of which
the beam currents are switched off during line flyback between the
display of the individual picture lines in the picture tube. FIG. 3b
shows a vertical blanking pulse V by means of which the beam currents
are switched off during the change ober from the display of one picture
to the display of the next picture. FIG. 3c shows a measuring signal
control pulse VH which is formed from a vertical blanking pulse
lengthened by three line duration.
The short-circuiting switch
127 is now controlled in such a way that it is non-conducting only
throughout the duration of the measuring signal control pulse VH and
during the remaining time short-circuits the input 121 of the buffer
amplifier 120 to earth. This means that a measuring signal only reaches
the comparator arrangement 12 during frame change so that the parts of
the picture signal which control the beam currents producing the picture
in the picture tube exert no influence on comparator arrangement 12 and
therefore on the blocking point control.
Throughout the duration
of the measuring signal control pulse VH, the measuring signal from
output 122, reduced by a reference voltage issued by the reference
voltage source 130 between its first 131 and its second terminal 132, is
present at the inverting inputs 111, 112, 113 of differential
amplifiers 123, 124, 125. If the differential amplifiers 123, 124, 125
were not present, this difference would be fed directly as part control
signals to the control signal storage capacitors 161, 162, 162. The
differential amplifiers 123, 124, 125 amplify the difference and thus
form the control amplifiers of the control loops.
The comparator
arrangement 12 further contains a device for compensation of the
influence of any leakage currents occurring in the picture tube 9. For
this purpose, a voltage to which the leakage current storage capacitor
126 is charged is fed to the non-inverting inp
uts 114, 115, 116 of the
three differential amplifiers 123, 124 and 125. The charging is
performed by the measuring signal from output 122 of the buffer
amplifier 120 via the decoupling resistor 118 and the leakage current
sampling switch 119 which is closed only within the period of the
vertical blanking pulse V, and in certain cases only during part of the
latter. Within this time the beam currents are, in fact, totally
switched off by the picture signal so that in certain cases only a
leakage current flows through the measuring resistor 702. Consequently,
throughout the duration of the vertical blanking pulse V the measuring
signal corresponds to this leakage current. Because the leakage current
also flows during the remaining time, even outside the duration of the
vertical blanking pulse the measuring signal contains a component
originating from the leakage current which therefore is also contained
in the voltage fed to the inverting inputs 111, 112, 113 of differential
amplifiers 123, 124, 125 and is subtracted out in the differential
amplifiers 123, 124, 125.
The part control signal is fed from
output 141 of differential amplifier 123 by the first control signal
sampling switch 154 to the first terminal 151 of the first control
signal storage capacitor 161 during the period of a storage pulse L1 and
is stored in the said capacitor. Similarly, the part control signal
from output 143 of differential amplifier 125 is fed to the third
control signal storage capacitor 163 during the period of a storage
pulse L2 and the part control signal from output 142 of differential
amplifier 124 is fed to the second control signal storage capacitor 162
during a storage pulse L3. The storage pulses L1, L2 and L3 are
illustrated in FIGS. 3d, e and f. They lie in sequence in one of the
three line periods by which the measuring signal control pulse VH is
longer than the vertical blan
king pulse V. These three line periods form
the sampling interval for the measuring signal or the part measuring
signals, as the case may be. During the remaining periods the outputs,
141, 152, 143 of the differential amplifiers 123, 124, 125 are isolated
from the control signal storage capacitors 161, 162, 163 so that no
interference can be transmitted from there and any distortion of the
stored part control signals caused thereby is eliminated. For the
duration of storage pulses L1, L2 and L3 the color signals at the input
terminals 101, 102, 103 are at their reference level i.e. in the present
embodiment at a level, corresponding to the blocking point or at a
fixed level with respect to it so that the control loops can adjust to
this level.
The switchable amplifiers 511, 512, and 513 each
receive at each input 241, 242, 243 a blanking signal BL1, BL2, BL3
respectively, the curves of which are shown in FIGS. 3g, h, i. These
blanking signals interrupt the supply of the color signals during line
flybacks and frame change, i.e. during the period of the measuring
signal control pulse VH, and thus the beam currents in these time
intervals are switched off. Naturally, the red color signal is let
through during the first line period after the end of the vertical
blanking pulse V, the blue color signal during the second line period
after the end of the vertical blanking pulse V and the green color
signal during the third line period after the end of the vertical
blanking pulse V by the switchable amplifiers 511, 512, 513 respectively
so that they can control the beam currents. Blanking signals BL1, BL2
and BL3 also provide for interruptions in the frame change blanking
pulse, which corresponds to the measuring signal control pulse, in the
corresponding time intervals. In these time intervals the beam currents
are measured and part control signals are determined from the part
measuring signals and stored in the control signal storage capacitors
161, 162, 163.
The circuit arrangement shown in FIG. 2 further
contains a trigger circuit 19 to which a supply voltage is fed via a
supply terminal 190. Via a reset input 191 a voltage is also
supplied to
the trigger circuit 19 from a third terminal 133 of the reference
voltage source 130. When the circuit arrangement is turned on, this
voltage is designed so as to be delayed with respect to the supply
voltage so that when the circuit arrangement is brought into operation
the interplay of the two voltages produces a switch-on reset signal such
that a low-value voltage pulse occurs at the reset input 191 during
turn on, which means that the trigger circuit 19 is set in its first
state. The reset input 191 can also be connected to another circuit of
any configuration which generates a switch-on reset signal when the
picture tube is turned on.
The trigger circuit 19 is further
connected via a second connection 23 to a logic network 22 which, when
the circuit arrangement is turned on,
is also set into a first state via
the second connection 23. In this first state the logic network 22
delivers a blocking signal at a blocking output 240 which is fed to the
three switchable amplifiers 511, 512, 513. By this means the supply of
the color signals to the output amplifiers 521, 522, 523 is interrupted
completely so that no beam currents can be generated by these. No
picture is therefore displayed.
An insertion signal EL which
extends over the three line periods by which the measuring signal
control pulse VH is longer than the vertical blanking pulse V, i.e. over
the sampling interval, is also fed via a line 233 to the trigger
circuit 19 and the logic network 22. As long as the trigger circuit 19
is in its first state, this insertion pulse EL is issued via a control
output 192 from the trigger circuit 19 and fed to the pulse generator
244. During the period of the insertion pulse EL this generator produces
a voltage pulse of a definite magnitude and passes this to output
amplfiiers 521, 522, 523 as an auxiliary pulse via switching diodes 245,
246, 247. By this means the beam currents are switched on for a short
time so as to receive a measuring signal despite the disconnected color
signals as soon as at least one of the hot cathodes 801, 802, 803
delivers a beam current.
In its first state the trigger circuit
19 also delivers a signal via a control line 211, and this signal is
used to switch the outputs 141, 142, 143 of the differential amplifiers
123, 124, 125 to earth potential or practically to earth potential. This
suppresses effects of voltages at the inputs 111 to 116 of the
differential amplifiers 123, 124, 125, especially effects of the
reference voltage source 130 which may in some cases initiate incorrect
charging of the control signal storage capacitors 161, 162, 163.
The
measuring signal produced by means of the pulse generator 244 at the
input 121 of the buffer amplifier 120 is also fed to the trigger circuit
19 via a measuring signal input 20. If it exceeds a preset threshold
value, the trigger circuit 19 switched into its second state. The logic
network 22 is then also switched into its second state via the second
connection 23. The differential amplifiers 123, 124, 125, too, are
triggered by the signal along the control line 211 into issuing a
control signal defined by the difference in the voltages at its inputs
111 to 116. The pulse generator 244 is blocked by the control output
192. The blocking signal issued from the blocking output 240 of the
logic network 22 now turns on the switchable amplifiers 511, 512, 513 in
the time intervals defined by the storage pulses L1, L2, L3 in such a
way that in these time intervals the color signals can produce beam
currents to form a measuring signal by which the control loops respond.
However, the display of the picture is still suppressed. The control
signal storage capacitors 161, 162, 163 are charged up in this process.
In the leads to the first terminals 151, 152, 153 there are change
detectors 251, 252, 253 which detect the changes of the charging
currents of the control signal storage capacitors 161, 162, 163 and at
their outputs 261, 262, 263 in each case deliver a part change signal
when the charging current of the control signal storage capacitor in
question has decayed and thus the relevant control loop has responded.
The part change signals are fed to three terminals 271, 272, 273 of the
change signal input 27 of the logic network 22.
When part change
signals are present from all change detectors 251, 252, 253, when
therefore all control loops have responded, the logic network 22
switches from its second to its third state. The blocking signal from
the blocking output 240 is now completely disconnected such that the
switchable amplifiers 511, 512, 513 are now switched only by the
blanking signals BL1, BL2, BL3. The colour signals are then switched
through to the output amplifiers 521, 522, 523 and the picture is
displayed in the picture tube.
FIG. 4 shows an embodiment for a
trigger circuit 19 and a logic network 22 of the circuit arrangements as
shown in FIGS. 1 or 2. The trigger circuit 19 contains a flip-flop
circuit formed from two NAND-gates 194, 195 to which the switch-on reset
signal, by which the trigger circuit 19 is returned to its first stage,
is fed via the reset input 191. All the elements of the circuit
arrangement in FIG. 4 are shown in positive logic. Thus, a short-time
low voltage at the reset input 191 immediately after the circuit
arrangement is started up is used to set the flip-flop circuit 194, 195
in such a way that a high voltage occurs at the output of the second
NAND gate 194 and a low voltage at the output of the second NAND gate
195. The low voltage at the output of the second NAND gate 195 blocks
differential amplifiers 123, 124, 125 via the control line 211 in the
manner described.
The insertion pulse EL is fed via the line 233
to the trigger circuit 19, is combined via an AND gate 196 with the
signal from the output of the first NAND gate 194 and is delivered at
the control output 192 for the purpose of controlling the pulse
generator 244.
The signals from the outputs of the NAND-gates
194, 195 are fed via a first line 231 and a second line 232 of the
second connection 23 as a switching signal to the logic network 22. The
first line 231 is connected to reset inputs R of three part change
signal
memories 221, 222, 223 in the form of bistable flip-flop circuits
which when the circuit arrangement is started up are reset via the
first line 231 in such a way that they carry a low voltage at their
outputs Q. The second line 232 of the second connection 23 leads via
three AND gates 224, 225, 226 to setting inputs S of the three part
change signal memories 221, 222, 223. By means of the AND gates 224,
225, 226 the signal on the second line 232 of the second connection 23
is combined each time with one of the part change signals supplied via
the terminals 271, 272, 273. The signals from the outputs Q of the part
change signal memories 221, 222, 223 are combined by means of a
collecting gate 227 in the form of an NAND gate and are held ready at
its output 228.
The measuring signal is fed to the trigger
circuit 19 via the measuring signal input 20 and passed to a first input
197 of a threshold detector 198 to which at a second input a threshold
value, in the form of a threshold voltage for example, produced by a
threshold generator 199 is also supplied. When the voltage at the first
input 197 of the threshold detector 198 is smaller than the voltage
delivered by the threshold generator 199, the threshold detector 198
delivers a high voltage at its output 200. When, on the other hand, the
voltage at the first input 197 is greater than the voltage of the
threshold generator 199, the voltage at the output 200 jumps to a low
value. This voltage is supplied as the setting signal of the flip-flop
circuit 194, 195, reverses the latter and thereby switches the trigger
circuit 19 into its second state when the voltage at the first input 197
exceeds the voltage of the threshold generator 199.
Between the
output 200 and the flip-flop circuit 194, 195 in the circuit arrangem
ent
shown in FIG. 4 there is inserted an inquiry gate 181 in the form of an
OR gate to which an inquiry pulse is fed via an inquiry input 193 of
the trigger circuit 19. This ensures that the flip-flop circuit 194, 195
is switched over only at a time fixed by the inquiry pulse--in the
present case a negative voltage pulse--and not at any other times due to
disturbances. As such an inquiry pulse it is possible to use, for
example, a pulse which occurs in the second line period after the end of
the vertical blanking pulse V, i.e. one which largely corresponds to
the storage pulse L2.
After the switching over of the flip-flop
circuit 194, 195 corresponding to the setting of the trigger circuit 19
into the second state, appropriately modified signals are supplied via
the control line 211 and the output 192 for the purpose of controlling
the pulse generator 244 and the differential amplifiers 123, 124, 125.
Modified voltages also appear on the lines 231, 232 of the second
connection 23, and these voltages release the part change signal
memories 221, 222, 223 such that they can each be set when the part
change signals reach the terminals 271, 272, 273.
In certain
cases, a further flip-flop circuit 234 is inserted in the lines 231, 232
to delay the signals passing along these lines; this is reset via the
first line 231 when the circuit arrangement is started up and thus it
also resets the part change signal memories
221, 222, 223. However,
after the trigger circuit 19 is switched into the second state the
further flip-flop circuit 234 is not set via the second line 232 of the
second connection 23 until a release pulse arrives via a release input
235 and another AND gate 236, for example a period of approximately the
interval of two vertical blanking pulses V after the switching of the
trigger circuit 19 into the second state. In this way it is possible to
bridge a period of time in which no defined signal values are present at
the terminals 271, 272, 273.
The signal at the output 228 of the
collecting gate 227 changes its state when the last of the three part
change signals has also arrived and has set the last of the three part
change signal memories. The signal is then combined via a gate
arrangement 229 of two NAND gates and one AND gate with the insertion
pulse EL of line 223 and with the signal on the second line 232 of the
second connection 23 or from the output Q of the further flip-flop
circuit 234 to the blocking signal delivered at the blocking output 24
which is fed to the switchable amplifiers 511, 512, 513.
FIGS.
31, m, n show the combinations of the blocking signal with the blanking
signals BL1, BL2, and BL3 at the blanking inputs 241, 242, 243 of the
switchable amplifiers 511, 512, 513 in the form of logic AND operations.
The dot-dash lines show resulting insertion signals A1, A2, A3 formed
by these operations after the starting up of the circuit arrangement and
before the occurrence of a beam current, i.e. in the first state of the
logic network 22. Here the resulting insertion signals A1, A2, A3 are
constant at low level. The dash curves show the resulting insertion
signals A1, A2, A3 after the appearance of a beam current and before the
steady state of the cut-off point control is reached, i.e. in the
second state of the logic network 22, while the continuous curves
represent the resulting insertion signals A1, A2, A3 in the steady state
of the cut-off point control, i.e. in the third state of logic network
22. The dash curves have similar shapes to storage pulses L1, L2, L3,
whereas the continuous curves correspond in shape to the inverses of the
blanking signals BL1, BL2, BL3. In this case a high level of the
resulting insertion signals A1, A2 or A3 means that the switchable
amplifier 511, 512 or 513 feeds the colour signal to the relevant output
amplifier 521, 522 or 523 respectively, whereas a low level in the
resulting insertion signal A1, A2 or A3 means that the relevant
switchable amplifier 511, 512 or 513 is blocked for the color signal.
The
circuit arrangement described is designed in such a way that the
trigger circuit 19 remains in its second state and logic network 22
remains in its third state even if charging currents reappear at the
difference signal storage cpacitors 161, 162, 163 due to disturbances
during the operation of the circuit arrangement. The cutoff point
control then makes readjustments without the displayed picture being
disturbed.
In the circuit arrangement shown in F
IG. 2, the green
color signal can also be let through during the second line period after
the end of the vertical blanking pulse V and the blue color signal
during the third line period after the end of the vertical blanking
pulse V by the switchable amplifiers 511, 512, 513 for the purpose of
controlling the beam currents. The storage pulses L2 and L3 at the
control signal sampling switches 155 and 156 and the second and third
blanking signals BL2 and BL3 at the blanking inputs 242 and 243 are then
to be interchanged. The resulting insertion signals A2 and A3 as shown
in FIGS. 3m and n are also interchanged then accordingly.
In FIG.
2 a dashed line is used to indicate which components of the circuit
arrangement can be combined advantageously to form an integrated
circuit. The first terminals 151, 152, 153 of the difference signal
storage capacitors 161, 162, 163, one terminal 128 of leakage current
storage capacitor 126, three terminals 524, 525, 526 in the leads to the
output amplifiers 521, 522, 523 as well as a line connection 704
between the first terminal 701 of the measuring resistor 702 and the
input 121 of the buffer amplifier 120 will then form the connecting
contacts of this integrated circuit
-----------------------------------------------------
TDA8140 HORIZONTAL DEFLECTION POWER DRIVER
DESCRIPTION
The TDA 8140 is a monolithic integrated circuit designed
to drive the horizontal deflectionpower transistor.
The current source characteristic of this device is
adapted to the on-linear current gain behaviour of
the power transistor providing a minimum power
dissipation. The TDA8140 is internally protected
against short circuit and thermal overload.
During the active deflection phase the collector
current of the power transistor is linearly rising and
the driving circuitry mustbe adaptedto the required
base current in order to ensure the power transistor
saturation.
According to the limited components number the
typical approach of the present TVs provides only
a rough approximation of this objective ; in Figure 5
wegive a comparisonbetweenthe typical real base
current and the ideal base current waveform and
the collector waveform.
The marked area represents a useless base current
which gives an additional power dissipation on
the power transistor.
Furthermoreduring the turn-ONand turn-OFFtransient
phase of the chassis the power transistor is
extremely stressed when the conventionalnetwork
cannot guarantee the saturation ; for this reason,
generally, the driving circuit must be carefully designed
and is different for each deflection system.
The new approach, using the TDA 8140, overcomes
these restrictions by means of a feedback
principle.
As shown in Figure 5, at each instant of time the
ideal base current of the power transistor results
from its collector current divided by such current
gain which ensure the saturation ; thus the required
base current Ib can be easily generated by a feedback
transconductanceamplifier gm which senses
the deflection current across the resistor Rs at the
emitter of the power transistor and delivers :
Ib = RS . gm . Ie
The transconductance must only fulfill the condition
:
1
1 + bmin V 1
RS
<>
RS
Where bmin is the minimum current gain of the
transistor. This method always ensures the correct
base current and acts time independent on principle.
For the turn-OFF, the base of the power transistor
must be discharged by a quasi linear time decreasing
current as given in Figure 6.
Conventional driver systems inherently result into
a stable condition with a constant peak current
magnitude.
This is due to the constant base charge in the
turn-ON phase independent from the collector current
; hence a high peak current results into a low
storage time of the transistor because the excess
base charge is a minimum and vice versa. In the
active deflection the required function, high peak
current-fast switch-OFF and low peak current-slow
switch-OFF, is obtained by a controlled base discharge
current for the power transistor ; the negative
slope of this ramp is proportional to the actual
sensed current.
As a result, the active driving system even improves
the sharpnessof vertical lines on the screen
compared with the traditional solution due to the
increasedstability factor of the loop representedas
the variation of the storagetime versus the collector
peak current.
A flyback transformer (FBT), also called a line output transformer
(LOPT), is a special transformer, which is used for conversion of energy
(current and voltage) in electronic circuits. It was initially designed
to generate high current sawtooth signals at a relatively high
frequency. In modern applications is used extensively in switched-mode
power supplies for both low (3V) and high voltage (over 10 kV) supplies.
Flyback Transformer
It was invented as a means to control the horizontal movement of the
electron beam in a cathode ray tube (CRT). Unlike conventional
transformers, a flyback transformer is not fed with a signal of the same
waveshape
as the intended output current. A convenient side effect of such a
transformer is the considerable energy that is available in its magnetic
circuit. This can be exploited using extra windings that can be used to
provide power to operate other parts of the equipment. In particular,
very high voltages are easily obtained using relatively few turns of
winding which, once rectified, can provide the very high accelerating
voltage for a CRT. Many more recent applications of such a transformer
dispense with the need to produce high currents and just use the device
as a relatively efficient means of producing a wide range of lower
voltages using a transformer much smaller than a conventional mains
transformer would be.
TDA8170 TV VERTICAL DEFLECTION OUTPUT CIRCUIT
The functions incorporated are :
.POWERAMPLIFIER
.FLYBACKG
ENERATOR
.REFERENCE VOLTAGE
.THERMAL PROTECTION
DESCRIPTION
The TDA8170 is a monolithic integrated circuit in
HEPTAWATTTM package. It is a high efficiency
power booster for direct driving of verticalwindings
of TV yokes. It is intended for use in Colour and B
&Wtelevision receivers as well as in monitorsand
displays.
IMPERIAL 21DX88 MALIBU CHASSIS F960 (F960Z011B) Frequency synthesizer tuning system for television receivers:
SHOWING M3872IMB1 + M206B1
"
A method for tuning a television receiver having automatic
frequency control to the carrier frequency of a selected broadcast
channel with an associated channel number including generating a
variable frequency signal by means of a local oscillator,
generating a reference frequency signal by means of a reference
oscillator, and generating a local oscillator correction signal for
matching an intermediate frequency signal derived from said local
oscillator signal and the carrier frequency signal with a
predetermined nominal intermediate frequency signal, said method
being characterized by the use of a microcomputer and comprising:
generating
binary signals representing first and second digital tune words,
said digital tune words representing a selected channel;
storing said first and second digital tune words in a first data memory in said microcomputer;
reading
said first and second digital tune words from said first memory
and generating a divided-down local oscillator frequency by the use
of said first digital tune word and a divided-down reference
oscillator frequency by the use of said second digital tune word;
comparing
said divided-down local oscillator and reference frequencies and
generating a control signal representative of the difference in
frequency of said divided-down local oscillator and reference
frequencies;
coupling said control signal to said local
oscillator for causing it to be locked to the frequency of said
received carrier signal;
mixing the local oscillator frequency signal and the carrier frequency signal to generate an intermediate frequency signal;
comparing
said intermediate frequency signal with said predetermined
nominal intermediate frequency signal and providing a tuning voltage
to said microcomputer, said tuning voltage being indicative of the
magnitude and direction of a tuning error between said
intermediate frequency signal and said predetermined nominal
intermediate frequency signal;
incrementally adjusting the
reference oscillator frequency by means of a tuning signal provided
to said reference oscillator by said microcomputer in response to
said tuning voltage;
detecting when the incrementally
changing, divided-down reference oscillator frequency causes the
intermediate frequency signal to pass said predetermined nominal
intermediate frequency signal; and
incrementally stepping the
divided-down reference oscillator frequency back a predetermined
number of steps following the passage of said predetermined nominal
intermediate frequency signal by said intermediate frequency
signal in tuning said television receiver to the selected channel.
"
A
television tuning system employs a frequency synthesizer system
for establishing the tuning of the receiver. A programmable
frequency divider counter is connected between the output of a
reference oscillator and a phase comparator to which the output of
the local oscillator in the tuner also is applied. The phase
comparator output provides a tuning voltage for controlling the
tuning of the local oscillator. A microprocessor is used to control
the count of the programmable frequency divider and initially to
set a count corresponding to the selected channel in a counter
connected between the output of the local oscillator and the phase
comparator. The tuning consists of three discrete time periods.
First, a settling time to allow channel change transients to
settle; second, a short period of forced search at a relatively
rapid rate to insure proper tuning; and third, a slower rate of
step-by-step correction to accomodate for station drift and the
like during reception. This third time period is initiated either
by the passage of a fixed length of time following the start of the
forced search period or by sensing a preestablished number of
changes of state in the output of the frequency discriminator during
the forced/search period.
1. A tuning
system for the tuner of a television receiver capable of receiving a
composite television signal and including frequency discriminator
(AFT) circuit means, said system including in combination:
a reference oscillator providing a reference signal at a predetermined frequency;
a
local oscillator in the tuner providing a variable output frequency
in response to the application of a control signal thereto;
a
programmable frequency divider means having first and second inputs
coupled respectively to the output of said reference oscillator
and said local oscillator for producing signals on first and second
outputs having frequencies which are a programmable fraction of the
frequency of the signals applied to the inputs thereto;
phase
comparator means having one input coupled with the first output of
said programmable frequency divider means and having another input
coupled with the second output of said programmable frequency
divider means for developing a control signal and applying such
control signal to said local oscillator for controlling the output
frequency thereof;
counter circuit means coupled with said
programmable frequency divider means for initially setting said
divider means to a predetermined division ratio and operating to
change the programmable fraction of division thereof in accordance
with changes in the count in said counter circuit means;
control
circuit means coupled with the output of said frequency
discriminator means and further coupled with said counter circuit
means for causing said counter circuit means to count at a first
rate in a predetermined direction determined by the state of the
output signal from said discriminator means in the absence of a
predetermined signal output from said frequency discriminator means
until a predetermined maximum count is attained, thereupon resetting
said counter circuit means to a count which is a predetermined
amount less than said maximum predetermined count and continuing to
count at said first rate in the same predetermined direction from
said new count to continuously change the programmable fraction of
said frequency divider means in accordance with the state of
operation of said counter circuit means, said control means
operating in response to said predetermined signal output from the
frequency discriminator means for terminating operation of said
counter circuit means; and
further means for terminating
operation of said counter circuit means at said first rate and
causing operation thereof at a second slower rate.
2. The
combination according to claim 1 wherein said further means includes
timing means initiated into operation simultaneously with the
setting of said divider means to a predetermined division ratio,
and after a predetermined time interval said timing means producing
an output signal applied to said counter circuit means to cause
operation thereof to take place at said second slower rate.
3. The combination according to claim
1 wherein said counter circuit means includes a reversible digital
counter coupled with said programmable frequency divider, means
and said control circuit means causes said counter circuit means to
count in said predetermined direction when the output of said
frequency discriminator is of a first state and to count in the
opposite direction when the output of said frequency discriminator is
of second state; and said further means comprises means coupled with
the output of said frequency discriminator and with said counter
circuit means to take place at said second slower rate in response
to a predetermined number of changes of state of frequency
discriminator. 4. The
combination according to claim 3 further including means responsive
to the selection of a new channel in said television receiver for
resetting said further means to an initial condition of operation.
5. The combination according
to claim 4 wherein said further means comprises a search
termination counter means operative to provide an output signal
applied to said counter circuit means in response to a count
thereby of a predetermined number of changes of state of said
frequency discriminator to cause said counter circuit means to be
operated at said second slower rate.
Description:
BACKGROUND OF THE INVENTION
Both of the above mentioned pat
ents
are directed to frequency synthesizer tuning systems for use with
television receivers to enable operation of the receivers with
minimal viewer fine tuning adjustments. By the utilization of the
frequency synthesizer tuning systems of these patents, the fine
tuning adjustment which is necessary with conventional types of
television receiver tuning systems has been substantially
eliminated. The system employed in the '953 patent permits utilization
of a frequency synthesizer tuning system which correctly tunes to a
desired television station or channel even if the transmitted
signals from that station are not precisely maintained at the
proper frequencies. The '535 patent is directed to a signal seek
tuning system adaptation of the frequency synthesizer tuning system
of the '953 patent which still permits implementation of all of
the desired wide-band pull in range of the frequency synthesizer
system of the '953 patent.
The systems of the foregoing
patents operate effectively to correct automatically for frequency
offsets in a frequency synthesizer tuning system without affecting
the operation of the conventional frequency synthesizer used in the
system. The systems of these patents are in widespread use
commercially and permit direct selection, with automatic fine
tuning adjustment, of any desired VHF channel which the viewer
wishes to observe. In addition, the signal seek adaptation disclosed
in the '535 patent couples all of the advantages of the frequency
synthesizer tuning system of the '953 patent with the desirability
of providing bidirectional signal seek operation.
While the
systems disclosed in the foregoing patents operate in a highly
satisfactory manner to accomplish the desired results of accurate
tuning without the necessity of fine tuning adjustments, the
circuitry for accomplishing the desired results is somewhat
complex. It is desirable to reduce the circuit complexity and the
number of signal detectors for accomplishing these results without
compromising the accuracy of operation of the system.
SUMMARY OF THE INVENTION
Accordingly, it is an object of this invention to provide an improved tuning system for a television receiver.
It
is an additional object of this invention to provide an improved
frequency synthesizer tuning system for a television receiver.
It
is another object of this invention to provide an improved
frequency synthesizer tuning system for a television receiver which
includes a provision for adjusting the synthesizer loop for
frequency offsets in the received signal with a minimum number of
signal detectors.
It
is a further object of this invention to tune the local RF
oscillator of a television receiver to the correct frequency for a
selected channel with a frequency synthesizer tuning system, and
automatically to change the reference frequency of the synthesizer
system, or adjust the count of a programmable divider that produces a
signal that divides the frequency of the local oscillator of the
tuner, if the AFT signal produced by the AFT frequency discriminator
of the receiver is outside a predetermined range corresponding to
correct tuning.
It is still another object of this invention
to provide an improved frequency synthesizer tuning system for a
television receiver which operates to adjust the synthesizer loop for
frequency offsets in the received signal over a relatively wide
pull in range in response to the output of the receiver frequency
discriminator by changing the division ratio of a programmable
frequency divider in the reference oscillator leg or local oscillator
leg of the synthesizer loop at a first relatively high rate from
an initial nominal value to a pre-established maximum in one
direction, and then resetting the division ratio to a second nominal
value once the maximum is reached and continuing to incrementally
change the division ratio in the same direction from the second
nominal value until a properly tuned condition is indicated by the
output of the receiver AFT frequency discriminator, followed by
control at a lower rate of operation to maintain tuning during
transmitting station drifts.
In accordance with a preferred
embodiment of this invention, the frequency synthesizer tuning
system for a television receiver includes a stable reference
oscillator and a voltage controlled local oscillator in the tuner. A
programmable frequency divider is connected between the output of
the reference oscillator and one input to a phase comparator, the
other input of which is supplied by the output of the local
oscillator. The output of the phase comparator then comprises a
control signal which is supplied to the local oscillator to control
the frequency of its operation.
A
counter circuit is connected to the programmable frequency divider
for initially setting the divider to a predetermined division
ratio upon selection of a desired channel by the viewer. The
counter then operates to change the programmable fraction of the
division ratio at a first relatively high rate in a direction
controlled by the output from the receiver picture carrier
discriminator in the absence of a predetermined signal output
derived from the discriminator. A control means causes the counter
circuit to count in this direction until it is determined that a
station is tuned or a predetermined maximum count is attained if no
station is correctly tuned, thereupon resetting the counter circuit
to a count which is a predetermined amount less than the maximum
predetermined count. Counting is continued in the same predetermined
direction from the new lesser count to continuously change the
programmable fraction of the frequency divider in accordance with
the state of operation of the counter.
The
high rate operation of the counter is terminated by the control
means in response to a predetermined signal from the output of the
discriminator, indicating that a station is correctly tuned, or after
a fixed time-out interval; so that the system automatically
adjusts for frequency offsets of the received signal which
otherwise would cause the station to be mistuned if a conventional
frequency synthesizer tuning system were used. After termination of
the high rate operation of the counter, it is switched to a lower
rate operation for maintaining tuning during transmitting station
drifts.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a block diagram of a television receiver employing a preferred embodiment of the invention;
FIG. 2 is a detailed block diagram of a portion of the circuit of the preferred embodiment shown in FIG. 1;
FIG. 3 is a detailed circuit diagram of a portion of a circuit shown in FIG. 1;
FIG. 4 is a flow chart of the control sequence of operation of the circuit shown in FIG. 1 and 2; and
FIG.
5 shows a waveform and time/frequency chart, respectively, useful
in explaining the operation of the circuit shown in FIGS. 1, 2 and
3.
DETAILED DESCRIPTION
Referring now to the drawings,
the same reference numbers are used throughout the several figures
to designate the same or similar components.
FIG. 1 is a block diagram of a television receiver, which may be a black and white or color television receiver. Mo
st
of the circuitry of this receiver is conventional, and for that
reason it has not been shown in FIG. 1. Added to the conventional
television receiver circuitry of FIG. 1, however, is a frequency
synthesizer tuning system, in accordance with a preferred embodiment
of the invention, which is capable of automatically changing the
reference frequency when a frequency offset exists in the received
signal for a particular channel.
Transmitted composite
television signals, either received over the air or distributed by
means of a master antenna TV distribution system, are received by an
antenna 10 or on antenna input terminals to the receiver. As is
well known, these composite signals include picture and sound
carrier components and synchronizing signal components, with the
composite signal applied to an RF and tuner stage 11 of the
receiver. The stage 11 includes the conventional RF amplifiers and
tuner sections of the receiver, including a VHF oscillator section
and a UHF oscillator section. Preferably, the UHF and VHF
oscillators are voltage controlled oscillators, the freuency of
operation of which are varied in response to a tuning voltage
applied to them to effect the desired tuning of the receiver.
The
output of the RF and tuner stages 11 is applied to the remainder
of the television receiver 14, which includes the IF amplifier
stages for supplying conventional picture (video) and sound IF
signals to the video and sound processing stages of the receiver 14.
The circuitry of the receiver 14 may be of any conventional type
used to separate, amplify and otherwise process the signals for
application to a cathode ray tube 16 and to a loudspeaker 17 which
reproduce the picture and sound components, respectively, of the
received signal.
The receiver 14 also includes a conventional
AFT or automatic fine tuning discriminator circuit and
additionally may include a synch separator circ
uit
for producing an output in response to the presence of vertical
synchronizatin pulses, a picture carrier detection circuit, and an
automatic gain control (AGC) amplifier. Outputs representative of
these sensor components are shown as being coupled over a group of
lead 20 to sensory circuitry 22, which in turn couples outputs
representative of the operation of these various sensor circuits to
a microprocessor unit 23 for controlling the operation of the
microprocessor unit.
The microprocessor unit 23 is utilized
in the system of FIG. 1 for controlling the operation of a
frequency synthesizer tuning system capable of automatic offset
correction. When the viewer desires to select a new channel, he
enters the desired channel number into a channel selection keyboard
25. There are a number of different keyboards which may be employed
to accomplish this function, and the particular design is not
important to this invention. The channel selector keyboard 25 also
may include switches or keys for initiating a signal seek function
in either the "up" or "down" direction.
Information
represented by the selection of channel numbers on the keyboard 25 is
supplied to the microprocessor unit 23 which provides output
signals over a corresponding set of leads 27 to the tuners (local
oscillators) 11 to effect the appropriate band switching control for
the tuners 11 in accordance with the particular channel which has
been selected. In addition, the keyboard 25, operating through the
microprocessor unit 23, provides output signals which operate a
channel number display 29 to provide an appropriate display of the
selected channel number to the viewer.
The
microprocessor M3870 unit 23 also processes the signals which are
used to operate the channel number display 29 through a
multiplexing circuit operation to decode the selected channel
number into a parallel encoded signal. This signal is applied to
corresponding inputs of the count-down counter or programmable
frequency divider 31 to cause the division number of the divider 31
to relate to the divided down frequency of the tuner local
oscillators connected to the input of the divider 31 through a
prescaler divider circuit 32 to the frequency of the reference
oscillator 34. Thus, the division number or division ratio of the
local oscillator frequency obtained from the output of the
programmable divider 31 is appropriately related to the frequency of
the reference crystal oscillator 34.
The
output of the oscillator 34 also is applied through a countdown
circuit or programmable frequency divider 35. Conventional frequency
synthesizer techniques are employed; and the microprocessor unit 23
automatically compensates, through appropriate code converter
circuitry, for the non-uniform channel spacing of the television
signals. It has been found most convenient to cause the programmable
frequency divider 31 to divide by numbers corresponding directly to
the oscillator frequency of the selected channel, for example, 101,
107, 113 . . . up to 931.
In accordance with the time
division multiplex operation of the microprocessor 23, the count of
the programmable frequency divider 35 initially is adjusted to a
fixed count by the application of appropriate output signals from
the microprocessor unit 23 to a point selected to be at or near the
mid-point of the operating range of the programmable frequency
divider 35. Thus, the output of the divider 35 is a stable
reference frequency (because the input is from the reference
crystal oscillator 34) which is used to establish initially and to
maintain tuning of the receiver to the selected channel.
The
output of the programmable divider 35 is applied to one of two
inputs of a phase comparator circuit 37. The other input to the
phase comparator circuit 37 is supplied from the selected one of
the VHF or UHF oscillators in the tuner stages 11 through the
programmable frequency divider 31. The phase comparator circuit 37
operates in a conventional manner to supply a DC tuning control
signal through a phase locked loop filter circuit 39 and over a
lead 40 to the oscillators in the tuner system 11 to change and
maintain their operating frequency.
With the exception of the
use of the microprocessor unit 23, the operation of the system
which has been described thus far is that of a relatively
conventional frequency synthesizer system incorporated into a
television receiver. This system is similar to the system of the
'953 patent. As in the system of that patent, the system shown in
FIG. 1, when the transmitted station or station received on a
master antenna distribution system provides the station or channel
signals at the proper frequency, operates as a relatively
conventional frequency synthesizer system. If, however, there is a
frequency offset in the received signal to cause the carrier of the
received signal to be displaced from the frequency which it should
have to some other frequency, it is possible that the system would
give the appearance of mistuning to the received station. The
microprocessor 23, operating in conjunction with the sensory
circuitry 22, is employed in conjunction with the countdown or
programmable frequency divider circuit 35 to eliminate this
disadvantage and still retain the advantages of frequency
synthesizer tuning.
Reference now should be made to FIG. 2 which shows details of t
he
interface between the keyboard 25, the microprocessor unit 23, and
the circuitry used in the frequency synthesizer portions of the
system. A commercially available microprocessor which has been used
for the microprocessor 23, and which forms the basis for the
diagramatic representation of the microprocessor in FIG. 2, is the
Matsushita Electronics Corporation MN1402 four-bit single-chip
microcomputer. This microcomputer has two, four-bit parallel input
ports labeled "A" and "B". In addition, three output ports, a five-bit
output port "C" and two four-bit output ports "D" and "E" are
provided. The internal configuration of the microcomputer 23 includes
an arithmetic logic unit (ALU), a read only memory (ROM) for
storing instructions and constants, and a random access memory
(RAM) used for data memory, arranged into four files, each file
containing 16 four-bit words. These words are selected by X and Y
registers and this memory is used, for example, for timers,
counters, etc., and also is used to hold intermediate results. To
facilitate an understanding of the operation of the system, a
portion of this memory is shown in FIG. 2 as a clock 81 and a
reversible counter 82 connected between the "B" input port and the
"D" output port. The microcomputer 23 is programmed to permit it to
operate in conjunction with the remainder of the circuits shown in
FIG. 2. The programming techniques are standard, and the
microcomputer 23 itself is a standard commercially available
circuit component.
There are several system parameters that
must be selected in the operation of the system shown in FIG. 2.
The selection of the nominal frequency of the two signals that feed
the phase comparator circuit 37 is an example. Channel selection is
provided by changing the frequency division ratio of the selector
counter 31 which divides the local oscillator signal after this
signal is passed through a prescaler circuit 32 and a divide-by-two
divider circuit 41. The nominal frequency from the programmable
frequency divider 31 (selector counter) is selected so that the
local oscillator (tuner) 11 can be set exactly on frequency for all
channels.
Since
the frequency divider 31 is able to divide only by integer
numbers, one distinct frequency possibility in the range of one KHz
is obtained, another in the range of two KHz, etc. A choice must
be made as to which of these values is optimum. Each value yields
the nominal frequency of all of the 82 channels by simply
multiplying by an appropriate integer for each channel. To simplify
the phase locked loop filtering problem by the filter 39, it is
desirable that the frequencies of the signals supplied to the phase
comparator 37 are as high as possible. This permits rapid
acquisition of a new channel along with a very clean DC control
signal to adjust the local oscillator. A trade-off for this,
however, must be made to permit fine tunning adjustment of the local
oscillator automatically to correctly tune in stations which are
off their assigned frequency, or to manually provide this feature,
if desired. The two-speed operation of the system in accordance
with the present invention allows a better trade-off to be made by
allowing rapid acquisition and then a slower speed for precise
tuning.
A compromise solution which is utilized in the circuit
of FIG. 2 is to cause the frequency division chain from the local
oscillator 11 in the tuner to the phase comparator 37 to be composed
of the fixed divide-by-256 prescaler 32, and a fixed divide-by-4
division, which is accomplished by the divider 41 at the input of
the counter 31 and a second divider 42 at the output of the counter
31. The variable frequency divider counter 31 then is loaded by
means of three latch circuits 44, 45 and 46 at an appropriate time
by the time division multiplex operation of the microcomputer 23
and a number that programs the programmable frequency divider
counter 31 to divide by the numerical value of the frequency of the
local oscillator in MHz for the channel selected. For example, if
the receiver is to be tuned to channel 2, which has a nominal local
oscillator frequency of 101 MHz, the programmable frequency
divider 31 is set to divide by 101. If the receiver is to be tuned
to channel 83, which has a nominal local oscillator frequency of
931 MHz, the programmable frequency divider 31 is set to divide by
931. In both cases, the variable divider 31 produces a 1 MHz
signal. However, because of the fixed divide-by-256 and the two
fixed divide-by-two dividers in series with the programmable divider
31, an output frequency of 976.5625 Hz is supplied from the output
of the divider 42 to the upper input of the phase comparator 37.
The
division ratio of the selector counter 31 is established by
appropriate output signals from the latch circuits 44, 45 and 46, as
mentioned above. The initial operation for changing, or maintaining,
the division ratio of the divider 31 is established by an entry of
the two digits of the selected channel number in the keyboard 25.
The microcomputer 23 operates as a time division multiplex system
for continuously monitoring the input ports and the output ports to
control the operation of the remainder of the system. The selection
of the two digits of the desired channel number is affected by a
time division multiplex iscanning of the outputs of the D output
port of microcomputer 23 and providing that information at the A
input port.
From
here the information is translated again to the D output ports to
the appropriate drivers of the channel number display circuit 29 and
to the latches 44, 45 and 46, and to a pair of similar four bit
latches 49 and 50 which control the divider ratio of the counter 35.
Although
the D output ports of the microcomputer 23 are connected in common
to all of these various portions of the circuit, the selection of
which of the latches are enabled to respond to the particular
output signals appearing on the D output ports at any given time is
effected through the C and E output ports of the microcomputer 23
in a time division multiplex fashion. A decoder circuit 52,
connected to the lowermost three outputs of the E output port of
the microcomputer 23, is used to apply unique decoding signals at
different times in the tim
e
division multiplex sequence of operation of the microcomputer 23
to the five latch circuits 44, 45, 46, 49 and 50, respectively. At
any given time in the sequence, only one of these latch circuits is
enabled for operation. A latch load signal is applied from the
upper output (EO3) at each cycle of operation of the signals
appearing on the E output port to set the latch circuit which is
enabled by the output of the decoding circuit 52 with the data
appearing on the other inputs to the latch circuit. This data
simultaneously appears on the four outputs of the D output port of
the microcomputer 23.
Thus, in rapid sequence, the latch
circuits 44, 45 and 46 are set to store the division number
corresponding to the selected channel entered onto the keyboard 25,
and the latch circuits 49 and 50 are each operated to set the
programmable divider reference counter 35 to a center or nominal
count, which is always the same upon the selection of a new channel
on the keyboard 25. Similarly, the two right-hand outputs of the C
output port (CO6 and CO5) enter the two digits of the selected
channel number in the drivers of the display circuit 29 at the
proper time in the binary encoded sequence when these digits appear
on the four-bit binary encoded representation of the D output
port. This results in a visual display of the channel number
selected.
In addition to the selection of a channel number
directly by the keyboard 25, the keyboard also may include an
additional switch 56, which is scanned in the time division multiplex
sequence to determine if the receiver is placed in a "seek" mode
of operation (when the signal seek capability is incorporated into
such a receiver). Operating in conjunction with the signal seek
switch 56 are a pair of "up" and "down" seek direction input
switches shown with a graphic representation of the seek directions
on the keyboard 25. A further provision is provided by two keys
labeled "U" and "D", which are used for "manual" fine tuning of the
receiver in the "up" or "down" directions depending upon which of
the two keys U or D has been operated. The keyboard 25 includes one
additional switch 58 which may be used to disable the automatic fine
tuning (AFT) portion of the circuit by rendering the microcomputer
insensitive to the signal output from the AFT circuit, in a manner
described more fully subsequently.
As is apparent from the
foregoing, the microcomputer 23 provides the intelligence, decision
making, and control for the system operation. It is a complete self
contained computer. The decisions or signal inputs upon which the
microcomputer 23 bases its operation include, in addition to the
inputs from the keyboard 25, inputs on sensory inputs into the B
input port and into the SNS1 and SNS0 inputs as shown in FIG. 2.
These input signals are used to provide an indication to the
microcomputer 23 of the presence or absence of a received signal;
and if the presence of such a signal is indicated, the inputs
provide a further indication of the accuracy of the tuning of the
receiver to that signal. If the system is being operated solely in a
manual mode of operation (AFT switch 58 open), the microcomputer
23 disregards all of this sensory information and tunes to the
frequency allocation of the channel selected in the manner described
above. The system will stay tuned to this condition, operating as a
conventional frequency synthesizer, whether or not a station is
present in the received signal.
When
the system is placed in its automatic mode of operation (similar
to the mode of operation of the above mentioned '953 patent), the
counter 82, integrally formed as part of the microcomputer 23,
continuously adds or subtracts one number at a time from the nominal
value or programmable division fraction entered into the programmable
frequency divider 35 at the outset of each new channel number
selection when frequency offset (mistuning) is present. The counter
82 is driven at a relatively high counting rate by clock pulses from
the clock 81 during this initial or forced search mode of
operation. Thus, automatic offset correction is provided for any
channel which is off its assigned frequency. The offset correction
automatically adjusts the frequency of the local oscillator by
changing the division ratio of the signal from the reference
oscillator 35 applied to the lower input of the phase comparator 37.
By doing this, the output of the phase comparator 37 applied to
the local oscillator 11 varies to cause the oscillator to be tuned
in the proper direction to compensate for the transmitting station
mistuning.
When the system is operating in its automatic mode
of operation, the microcomputer 23 responds to the sensor
information applied to it on its B input ports and on the S1 input
port shown in FIG. 2. These inputs are obtained from the various
outputs of the operational amplifiers shown connected to the
corresponding input ports in the detailed circuit of FIG. 3.
Depending upon whether the receiver is provided with a signal seek
feature or not, one or more of the sensory inputs of the circuit of
FIG. 3 are used. The s
ystem
shown in the drawings has a capability of correcting for frequency
offsets larger than 1.5 MHz on channels 2 and 7 and approximately 2
MHz on channels 6 and 13. The remainder of the channels have a
range between these two values.
If the receiver is not tuned
properly, the micromputer 23 executes the localized search of the
tuning range mentioned above. Since there is a necessary settling
down time for the tuning of a television receiver immediately
following selection of a new channel, a time interval of 250
milliseconds has been selected to prevent any localized search or
offset frequency correction until the expiration of this "settling
down" time period. If, at the end of this 250 millisecond time
interval, a properly tuned station is present, this is indicated by
the sensory outputs from the television receiver and no localized
search is effected to change the division ratio or programmable
divider count in the reference counter 35 for a system that also
has signal seek.
A system with no signal seek capability is
described later that requires less sensory input but which uses a
time period where a forced search is required directly after the
settling time interval.
Upon
termination of the 250 millisecond settling down period, the
microcomputer 23 is rendered responsive to the sensory input signals on
its sensory input signal ports. In the simplest form, only the
output of the frequency discriminator 60 (FIG. 3) applied to three
comparators 61, 62 and 63 is used to provide the necessary tuning
information to the microcomputer 23. The outputs of these comparators
are applied to the B12 and B11 inputs of the microcomputer.
The
comparator 61 simply is a conventional comparator for determining
whether or not the output of the frequency discriminator is
positive or negative, as indicated in the upper waveform of FIG. 5.
The comparators 62 and 63 are each adjusted with appropriate
reference input levels to provide a narrow window centered about
the center tuning frequency (fc) of the receiver. If the tuning of
the receiver, as indicated by the output of the frequency
discriminator 60, is outside this window on either side of the
central axis shown in FIG. 5, one output condition is indicated on
the input terminal B11 of the microcomputer. Only when the tuning
frequency is within the tuning window, indicative of a properly
tuned receiver, is the appropriate input applied to the
microcomputer input terminal B11. This input overrides any other
input that may be present on the input terminal B12 and is
indicative of a properly tuned receiver. The input from the
frequency discriminator 60, as applied to the microcomputer on its
input port B12, is used to determine the direction of operation of
the counter 82 of the microcomputer for the localized search count
signals applied to the latch circuits 49 and 50 to change the count
of the reference programmable divider counter 35 on a step-by-step
basis.
The lower graph of FIG. 5 plots the relative frequency
of the local oscillator 11 to the received signal frequency with
respect to time. The various arrows are used to indicate the manner
of operation of the counter 82 in the microcomputer 23 in
conjunction with the reference counter 35 for adjusting for any
mistuning conditions which may exist after the initial station
selection has been effected in the manner described above.
If
the receiver is properly tuned, the outputs from the comparators 62
and 63 of FIG. 3 which are combined together and applied to the
input port B11 of the microcomputer 23, provide an indication that
the tuning is within the properly tuned center frequency window. As
a consequence, no further operation of the microcomputer to change
any of the outputs applied to the latch circuits 49 and 50 for the
duration of this condition is effected. On the other hand, if the
receiver is mistuned on either side of the proper tuning frequency,
the various operating characteristics shown in FIG. 5 are effected.
Assume
initially that the receiver is capable of making tuning
adjustments over a range of fc plus Δf to fc minus Δf, as indicated
in the top waveform of FIG. 5. Three specific examples of
mistuning will then be considered. Initially, assume that the local
oscillator is mistuned relative to the received signal to a
frequency f1 as shown in the lower graph of FIG. 5. In this
condition, the outout of the frequency discriminator 60 is positive
since this signal frequency lies to the lefthand side of the
center or properly tuned region of operation of the discriminator.
Under this condition of the operation, the input signal applied to
the sensor port B12 of the microcomputer 23 is such that the
microcomputer counter 82 is caused to advance in a positive
direction to change the programmable division ratio or count of the
reference counter 35 in a manner to force the output of the phase
comparator 37 to adjust the frequency of the local oscillator until
the proper tuning indicated at point B in the lower graph of FIG. 5
is reached. The time interval for accomplishing this result is
measured from the upper end of the arrow representative of the
frequency f1 to the point B.
Now assume that the receiver
mistuning is to a frequency f2 which as shown in FIG. 5 as located
on the righthand-side of the center axis fc. In this condition, the
discriminator output is negative. This is reflected in the output
of the comparator 61 applied to the input port B12 of the
microcomputer 23. The polarity of this sign
al
is identified by the microcomputer 23 to cause the counter 82 in
it to operate in the reverse direction. As this count is applied on
a step-by-step basis through the latch circuits 49 and 50 to the
reference counter 35, the division ratio or count of the reference
counter (divider) 35 is changed. As a result, the reference
oscillator signal applied to the phase comparator 37 causes the
phase comparator 37 output to drive the local oscillator frequency
in a direction opposite to that considered in the first example.
This is shown by the vector interconnecting the top of the arrow
representative of f2 to point A on the time/frequency graph of FIG.
5.
As discussed in the general discussion above, whenever the
tuning frequency reaches the narrow window on either side of fc, the
outputs of the comparators 62 and 63 provide the necessary
indication on the sensory input port terminal B11 to cause
termination of the operation of the counter 82 in the microcomputer
23. Then the reference counter 35 remains set to the count attained
just prior to the appearance of this input signal on the input port
B11 of the microcomputer 23.
A third mistuning condition can
exist, and ordinarily this condition results in an ambiguity which
cannot be corrected simply by responding to the signal polarity at
the output of the frequency discriminator. This is indicated by
the mistuned condition where the difference between the local
oscillator frequency f3 and the transmitter frequency is such that
the signal f3 lies in the range to the right of the negative
portion of the discriminator output shown in the upper waveform of
FIG. 5. In this condition, the associated sound causes the
discriminator output to be positive; so that the television
receiver normally would attempt to tune toward the next adjacent
channel and away from the properly tuned center frequency of the
channel which is desired. The output of the discriminator 60 in
this situation is the same as it was in th
e
first example considered for frequency f1; so that the counter 82
of the microprocessor 23 operates to change the count in the
reference counter 35 in a manner to cause the local oscillator
frequency to go higher toward a frequency f3 +Δf, as shown in FIG.
5.
A predetermined number of counts of the counter 82 in the
microcomputer 23 are necessary for the microcomputer to count
through the frequency range Δf, and this range is selected to be
within the pull in or operating range of the system. Once this count
has been attained, the microcomputer counter 82 immediately is
reset back to a count which corresponds to a frequency 2 Δf lower
than the frequency attained by the maximum count. This is indicated
in FIG. 5 by the frequency f3-Δf. Because the microcomputer counter
82 is limited to counting a number of counts equal to Δf, this new
frequency now is on the lefthand side of the center line fc, shown
in both waveforms of FIG. 5. This places the local oscillator
frequency at a point such that the frequency discriminator output is
the positive output shown on the lefthand-side of the upper
waveform of FIG. 5. Counting continues in the same direction as
previously. This time, however, it is in a proper direction to bring
about correct tuning; and when the center frequency is reached,
the output of the comparators 62 and 63 cause the microcomputer 23
to stop its count. The proper tuning point attained is indicated at
point C on the graph of the lower part of FIG. 5.
Because
the counter 82 of the microcomputer is limited to a maximum count
equivalent to Δf above its initial count and thereupon is reset to a
new count equivalent to 2 Δf lower than the maximum count, it is
not necessary to utilize any other sensory inputs in order to
properly tune the receiver over a wide pull in range (as much as
plus or minus 2 MHz). Only the output of the conventional frequency
discriminator 60 is used to provide the necessary sensory inputs.
The
counter 82 of the microcomputer 23 is operated by the clock 81
during the foregoing sequence of operation, immediately following the
selection of a new channel by the operation of the keyboard 25, at
a fast or high speed operation. Typically, the counter steps are
10 milliseconds per step; so that there are no initial visual
effects which can be noticed by an observer of the television
screen of the receiver being tuned. The maximum forced search
period is approximately 900 milliseconds in duration. At the end of
this time interval, a timer in the microcomputer 23 causes a
signal to be applied through the outputs of the E output port to
the decoder circuit 52 indicative of the completion of this time
interval. The decoder 52 then applies a pulse on an output lead
connected to the B13 input of the B input port of the microcomputer
23. This pulse is sensed by the microcomputer 23 and is applied to
the clock 81 to change the clock rate to a much slower rate,
approximately one-third (1/3) or one-fourth (1/4) the rate used
previously during the forced search mode of operation. This then
permits the system to accomodate station drifts which normally
occur at a very slow rate during the transmission and reception of a
television signal. As a consequence, it is possible to use more
filtering in the filter 39 on the tuning line (FIG. 1) and employ a
smaller frequency window for the channel verification sensed by
the circuitry shown in FIG. 3.
The
result is a more precise tuning from the receiver than is
otherwise possible if only a high speed operation of the clock 81
is utilized.
When the channel once again is changed by
operation of the keys in the keyboard 25 or operation of the
channel selection circuitry from a remote control unit, this new
channel input is sensed by the microcomputer 23 from the signals
applied to the A input port and the clock 81 is reset to its fast
time or the forced search mode of operation; and the process
resumes.
Instead of employing an additional decoding function
in the decoder 52, a separate decoder also could be connected to
the outputs of the D output ports to feed back the signal to the
B13 input terminal of the B input port of the microcomputer 23. The
operation of the system to change the rate or frequency of the
pulses applied by the clock 81 to the counter 82 otherwise is the
same as described above.
Although applicant has found that it
is preferable to correct for mistuning or frequency offsets by
adjusting the count or division ratio of the counter 35, such
offset adjustments also could be effected by adjusting the count in
the counter 31 in the local oscillator signal line. The operation in
such a case is the same as described above for adjusting the count
in the counter 35.
If the receiver is to be used with an
automatic signal seek mode of operation, however, additional sensory
inputs are necessary. These inputs operate in conjunction with the
output of the frequency discriminator 60. The operation of the
microcomputer 23 in controlling the count of the reference
programmable frequency counter divider 35 is the same as described
above. The additional sensory inputs simply are used in conjunction
with the outputs of the comparators 62 and 63 to signal the
microcomputer 23 to assure that tuning is to a picture channel
rather than an adjacent sound channel. This is accomplished by
utilizing the output of the synchronizing signal separator 65 which
is applied to a comparator 67 to produce an output signal to the
SNS1 sensory input of the microcomputer 23 only when vertical
synchronizing signal components are present.
In addition, the
output of a picture carrier detector 69 is applie
d to the input of a
comparator 70 to produce an output to the B10 sensory input of the
microcomputer 23. If the picture carrier detector 69 is producing
an output indicative of the presence of a carrier, but no output is
being obtained from the vertical synch separator 65 at the same
time, the system is mistuned to a sound carrier and the
microcomputer 23 is permitted to continue its localized search until a
properly tuned station is found. Only when there is coincidence of
signals from the picture carrier detector 69, the synch signal
separator 65, and the automatic frequency discriminator window as
determined by the comparators 62 and 63, is the microcomputer
operation terminated to indicate that a properly tuned channel is
present.
Further insurance of tuning the receiver only to a
strong signal also can be provided by the addition of an AGC
amplifier 72. This is connected to a comparator 74 coupled to the
B10 input port along with the output of the picture carrier
detector comparator 70. When the AGC amplifier 72 is used as a
sensory input, the microcomputer operation, when the system is used
in a signal seek mode, is only terminated to indicate reception of
a valid signal when that signal is strong enough to produce the
desired output from the comparator 74. The signal level which is
acceptable is set by a potentiometer 75.
It should be noted
that when the system is operated in a signal seek mode, the sensory
inputs must indicate the reception of a properly tuned signal
within a pre-established time period. If no signal is sensed by the
various sensory input circuits operating in conjunction with one
another as described above, the microcomputer 23 automatically steps
to the next channel number and repeats the sequence of operation
described above. This is when it is placed in its signal seek mode of
operation. If signal seek is not employed, the additional sensory
circuits 65, 69 and 72 are not necessary, and the inputs to the
microcomputer which are provided from these sensory circuits are not
utilized. The sensory signal input which is used both for a
receiver without a signal seek capability of operation and for a
receiver which has a signal seek mode of operation in it, is the
output of the frequency discriminator 60 operating in conjunction
with the comparators 61, 62 and 63 as described above.
As
indicated above, the wideband method of tuning precisely to an
incoming signal that is at the wrong frequency described here only
needs the frequency discriminator sensory information. The method
that uses the additional sensors described above is needed to make
this system operate compatibly with signal seek but it is not
restricted to seek operation.
For
a system that does not use signal seek operation, only the
frequency discriminator sensory input is required for proper
operation. The discriminator 60 is used for both fine tuning
direction information and to produce a frequency window to indicate
the presence of a correctly tuned station (channel verification).
Initially, after a channel change, there is a 250 millisecond
settling time, the same as the operation described above with
compatible seek. After that, however, comes a period of time where a
forced localized search is produced by the microcomputer 23. The
forced search is needed to insure that the system will correctly
tune to stations that initially may be tuned to the undesired zero
voltage crossover in the right half of the upper curve of FIG. 5.
Such signals may be within the frequency window of the discriminator
60; and if a search is not forced, this system will not correctly
tune. The compatible seek system described previously correctly
tunes the local oscillator without a forced search, because the
picture carrier detector and vertical detector do not give an output
for this situation and the system automatically goes into its search
mode of operation. However, the non-seek system does not have a
picture carrier sensor input and must be forced to search for an
initial period of time sufficient to allow the system to tune up to
its maximum frequency and then reset (loop) back to a frequency of 2
Δf lower. Then it is tuned to the positive left half portion of
the discriminator curve (FIG. 5) and the frequency window created
by the discriminator 60 is sufficient to insure proper tuning. If
the discriminator output produced by the desired incoming signal
created an initial situation that produces the correct tuning
direction information, i.e., in the left half of the curve of FIG.
5, or in the right half portion that gives the correct direction
and
frequency
window information, the forced search would not be needed.
However, the forced search will produce a correct tuning situation
anyway. In these cases, the tuning either is correct to begin with
or correct tuning is reached quickly. Then, even though the forced
search is active, it simply alternates up and down through the
correct tuning point because each time the receiver is tuned a little
high in frequency, it produces a negative output from the
discriminator 60; and the tuning direction signal causes the system
to tune down in frequency.
Then,
a positive discriminator output is produced, and the system tunes
up in frequency. This continues until the forced search is removed
by time-out of the microcomputer 23 (a fraction of a second). At
such time, the receiver is correctly tuned by the frequency window of
the discriminator to be very near fc. The system cannot tune to
the undesired discriminator crossover shown in the right half
portion of FIG. 5 because the polarity of the tuning direction
signal always causes it to tune away from that point.
The
fast time or forced search operation of the system can be
terminated in a different way other than the preestablished
time-out period described above in conjunction with the operation
of the circuit shown in FIG. 2. Generally, it is desirable to build
into the system (or program into the system by means of software)
such a maximum time-out period to effect the operation which has
been described above to terminate the search and cause the clock 81
thereafter to operate in a low speed mode of operation. Termination
also can be accomplished by sensing the number of changes in the
direction sensor input applied to the B12 terminal of the B input
port to cause the search to be terminated when this direction
changes three times (or more). By doing this, any flicker that
might be observed on the screen of the television receiver is
minimized, since the forced search still takes place at the high
rate of application of clock pulses from the clock 81 to the
counter 82 in the same manner described above.
Termination
of the search, however, also may be effected by means of a search
terminate counter 78 (FIG. 3), which is advanced by pulses applied
to it each time the output of the comparator 61 changes its sign
(indicative of a change in direction for the counter 82) as applied
to it through the B12 input port, as described earlier. After three
of these changes, or some other number if desired, an output pulse
is obtained from the search terminate counter 78 and is applied to
the SNS0 input of the microcomputer 23. This causes the operation
of the clock 81 to be switched to its low speed mode of operation
to terminate the fast or "forced search" mode of operation. The
next time a new channel number is entered on the keyboard 25, a
reset pulse is applied to the search terminate counter 78 to reset
it to its original or zero count, thereby readying it for another
sequence of operation. It is apparent that the search terminate
counter 78 may not always be operated to terminate the count, since
the time-out interval which is sensed by the decode circuit 52 and
applied to the B13 input port of the microcomputer 23 may occur
before there are three changes of direction of the search. In any
event, the next time a new channel number is entered into the
keyboard 25, the search terminate counter 78 is reset; so that it
is irrelevant whether this counter reaches a full count or not to
effect the termination of the forced search operation of the
system.
FIG. 4 shows the control sequence of the system which
is stored in the ROM (Read Only Memory) of the microcomputer 23.
The microcomputer 23 operates by always running through the flow
sequence, via loops L1, L2 and L3. Loop L1 corresponds to a new
channel selection by two digit number entry. Loop L2 corresponds to
channel number increment or decrement by an up or down key
operation, respectively, or by seek operation. Loop L3 corresponds
to fine tuning, either manual or automatic. To obtain exact timing for
system control, the microcomputer 23 receives a standard timing
pulse from the output of the reference counter 35 divided in a
divide-by-five counter 80 and applied to the A13 input port of the
microcomputer 23. The control functions which are programmed into
the microcomputer 23, as indicated in the flow chart of FIG. 4, are
outlined in the following paragraphs.
Channel Number
Correction: An invalid two digit channel number entry (0, 1, 84,
99) is corrected. When the operation of the receiver is in the
signal seek mode, the next channel up from 83 is channel 2, and the
next lower channel from channel 2 is 83.
PLL
Control I: For a given channel number, a corresponding binary code
for the PLL selector counter 31 is derived as described
previously. For UHF channels, the local oscillator frequency
separation between two adjacent channels is 6 MHz and the code for
PLL is generated by the microcomputer 23 through means of a simple
calculation. This code then is transferred from the microcomputer
23 to the latches 44, 45 and 46 as described previously.
PLL
Control II: This routine of the microcomputer 23 is used to
transfer the fine tuning data to the latches 49 and 50 which
control the count of the reference counter 35 in the PLL circuit.
Channel
Number Display: The channel number is transferred from the
microcomputer 23 to the driver latches of the display driver
circuit 29.
Key Input Detection: The keyboard is arranged as
the matrix circuit shown in FIG. 2. ROM programming for scanning
and acknowledging a keyboard entry only after successive
indications provides protection against false entry due to contact
bounce. The four data output lines of the D output port of the
microcomputer 23 are used to transfer data to the phase lock loop
section of the circuit and to the display circuit 29, as well as for
scanning the keyboard matrix circuit.
Time Count: The
microcomputer 23 receives a basic timing pulse of approximately 200 Hz
from the output of the divider 80 and performs various controls for
each timing pulse. By way of example, sensing for the vertical
synch input (when the system is used with a signal seek capability)
on the input port SNS1 takes place every 2.5 milliseconds.
Automatic seek timing is selected to be 133 milliseconds for UHF
channels. All of these timing pulses are derived from the basic
synchronization timing pulse applied to the microcomputer on the
A13 input port from the output of the divider 80. Various other
timing values used in the microcomputer to properly time multiplex
sequence the operation are derived from this basic timing pulse.
Sensor
Input Detection: As described previously, the output of the
comparators shown in FIG. 3 reflect the status of the tuning of the
television receiver. If no signal seek mode of operation is used,
only the frequency discriminator or AFT discriminator 60 is
necessary. When a system is being used in a signal seek mode, a
proper television signal receipt is indicated by the presence of a
vertical synch signal at the output of the synch signal separator
65 and corresponding outputs are applied to the input leads B10 and
B11 (high level input signals) indicative of tuning to the
"correct tuned" frequency discriminator window and reception of a
picture carrier. As stated previously, the signal present on the B12
input lead is used to determine the direction of tuning when the
receiver is operated in its automatic mode.
Mode Detection: The
status of the seek and automatic/manual (A/M) switches are
detected. If the A/M switch (not shown) is in its automatic
position, automatic seek and offset correction are active. If only
the seek switch is on, only seek is performed. If the A/M switch is
in manual, manual fine tuning (MFT) is active.
Automatic
Mode: If the TV receiver is not properly tuned for VHF channels in
automatic, the local oscillator frequency is shifted automatically
toward proper tuning. The fine tuning data is generated in the
microcomputer 23 and is transferred to the latches 49 and 50 for the
reference counter 35 in the PLL circuit.
Manual Fine Tuning
(MFT) Control: The local oscillator frequency is shifted by pushing
the fine tuning up (U) or down (D) pushbutton or switch. This MFT
control can be applied to VHF channels as well as to UHF channels.
Channel
Up/Down: When a channel up (upward pointing arrow) or down
(downward pointing arrow) key closure in the keyboard 25 is
detected, or upon a direct access to an unused channel, this routine
is activated and the system will advance to the next channel in
the selected direction.
The foregoing embodiment of the
invention which has been described above and which is illustrated in
the drawings is to be considered illustrative of the inventi
on,
which is not limited to the specific embodiment selected for this
purpose. For example, hard-wired logic could be used to achieve the
various circuit operations which are accomplished by the
microcomputer 23 in conjunction with the other portions of the
system. The relative ease of programming and debugging the
microcomputer 23, however, make it much simpler to implement the
system operation with the microcomputer than with hard-wired logic.
With respect to the sensor circuit inputs to the system, an added
degree of operating assurance can be provided by the addition of a
sound carrier sensor in addition to the picture carrier sensor shown
in FIG. 3. If this feature is desired, the output of the
comparator for the sound carrier is combined with the outputs of
the comparators 70 and 74 at the input terminal B10 of the B input
port of the microcomputer 23. Because of the manner of the circut
operation which has been described previously, however, the addition
of a sound carrier detector to the system is not considered
necessary, even for a system operating in the signal seek mode of
operation. This is in contrast to conventional television receivers
having a signal seek operation, in which detection of the sound
carrier generally is a necessity to insure that mistuning of the
receiver to an adjacent sound carrier does not take place.
TDA2541 IF AMPLIFIER WITH DEMODULATOR AND AFC
DESCRIPTION
The TDA2540 and 2541 are IF amplifier and A.M.
demodulator circuits for colour and black and white
television receivers using PNP or NPN tuners. They
are intended for reception of negative or positive
modulation CCIR standard.
They
incorporate the following functions : .Gain controlled amplifier
.Synchronous demodulator .White spot inverter .Video preamplifier with
noise protection .Switchable AFC .AGC with noise gating .Tuner AGC
output (NPN tuner for 2540)-(PNP
tuner for 2541) .VCR switch for video output inhibition (VCR
play back).
.SUPPLYVOLTAGE : 12V TYP
.SUPPLYCURRENT : 50mATYP
.I.F. INPUT VOLTAGE SENSITIVITY AT
F = 38.9MHz : 85mVRMS TYP
.VIDEO OUTPUT VOLTAGE (white at 10% of
top synchro) : 2.7VPP TYP
.I.F. VOLTAGE GAIN CONTROL RANGE :
64dB TYP .SIGNAL TO NOISE RATIO AT VI = 10mV :
58dB TYP
.A.F.C. OUTPUT VOLTAGE SWING FOR
Df = 100kHz : 10V TYP
A SCART Connector (which stands for Syndicat des Constructeurs d'Appareils Radiorécepteurs et Téléviseurs) is a standard for connecting audio-visual equipment together. The official standard for SCART is CENELEC document number EN 50049-1. SCART is also known as Péritel (especially in France) and Euroconnector but the name SCART will be used exclusively herein. The standard defines a 21-pin connector (herein after a SCART connector) for carrying analog television signals. Various pieces of equipment may be connected by cables having a plug fitting the SCART connectors. Television apparatuses commonly include one or more SCART connectors.
Although a SCART connector is bidirectional, the present invention is concerned with the use of a SCART connector as an input connector for receiving signals into a television apparatus. A SCART connector can receive input television signals either in an RGB format in which the red, green and blue signals are received on Pins 15, 11 and 7, respectively, or alternatively in an S-Video format in which the luminance (Y) and chroma (C) signals are received on Pins 20 and 15. As a result of the common usage of Pin 15 in accordance with the SCART standard, a SCART connector cannot receive input television signals in an RGB format and in an S-Video format at the same time.This kind of connector is todays obsoleted !Consequently many commercially available television apparatuses include a separate SCART connectors each dedicated to receive input television signals in one of an RGB format and an S-Video format. This limits the functionality of the SCART connectors. In practical terms, the number of SCART connectors which can be provided on a television apparatus is limited by cost and space considerations. However, different users wish the input a wide range of different combinations of formats of television signals, depending on the equipment they personally own and use. However, the provision of SCART connectors dedicated to input television signals in one of an RGB format and an S-Video format limits the overall connectivity of the television apparatus. Furthermore, for many users the different RGB format and S-Video format are confusing. Some users may not understand or may mistake the format of a television signal being supplied on a given cable from a given piece of equipment. This can result in the supply of input television signals of an inappropriate format for the SCART connector concerned.
