SONY KV-27XR TA CHASSIS SCC-783B-A (SX) INTERNAL VIEW.

The Sony CHASSIS SCC-783B-A (SX) Is a somewhat brother with different circuit design and components design compared to the older awesome RX2 CHASSIS OF 1985 with further improvement and added features.

As pictured it's well organized:

- Left upside Power supply
- Middle bottom all television receiver functions.
- Right upside HF and IF Stages.

The chassis SCC-783B-A (SX) is highly reliable and runs almost cool, the Sony dry joint era was far unknown at the time.

NOTE:

- The set was never serviced before and even never opened, I have opened first time !

- The power cord is cut before i got the set, I powered up directly at Power supply Unit and it
RUNS obviously perfect, many today's People are ugly and BAD Believe me !!



SONY  KV-27XR TA  CHASSIS SCC-783B-A  (SX) CIRCUITS DESCRIPTION:

TDA3505 Video control combination circuit with automatic cut-off control


GENERAL DESCRIPTION
The TDA3505 and TDA3506 are monolithic integrated circuits which perform video control functions in a PAL/SECAM
decoder. The TDA3505 is for negative colour difference signals -(R-Y), -(B-Y) and the TDA3506 is for positive colour
difference signals +(R-Y), +(B-Y).
The required input signals are: luminance and colour difference (negative or positive) and a 3-level sandcastle pulse for
control purposes. Linear RGB signals can be inserted from an external source. RGB output signals are available for
driving the video output stages. The circuits provide automatic cut-off control of the picture tube.
Features
· Capacitive coupling of the colour difference and
luminance input signals with black level clamping in the
input stages
· Linear saturation control acting on the colour difference
signals
· (G-Y) and RGB matrix
· Linear transmission of inserted signals
· Equal black levels for inserted and matrixed signals
· 3 identical channels for the RGB signals
· Linear contrast and brightness controls, operating on
both the inserted and matrixed RGB signals
· Peak beam current limiting input
· Clamping, horizontal and vertical blanking of the three
input signals controlled by a 3-level sandcastle pulse
· 3 DC gain controls for the RGB output signals (white
point adjustment)
· Emitter-follower outputs for driving the RGB output
stages
· Input for automatic cut-off control with compensation for
leakage current of the picture tube

Notes
1. < 110 mA after warm-up.
2. Values are proportional to the supply voltage.
3. When V11-24 < 0,4 V during clamping time - the black levels of the inserted RGB signals are clamped on the black
levels of the internal RGB signals.
When V11-24 > 0,9 V during clamping time - the black levels of the inserted RGB signals are clamped on an internal
DC voltage (correct clamping of the external RGB signals is possible only when they are synchronous with the
sandcastle pulse).
4. When pins 21, 22 and 23 are not connected, an internal bias voltage of 5,5 V is supplied.
5. Automatic cut-off control measurement occurs in the following lines after start of the vertical blanking pulse:
line 20: measurement of leakage current (R + G + B)
line 21: measurement of red cut-off current
line 22: measurement of green cut-off current
line 23: measurement of blue cut-off current
6. Black level of the measured channel is nominal; the other two channels are blanked to ultra-black.
7. All three channels blanked to ultra-black.
The cut-off control cycle occurs when the vertical blanking part of the sandcastle pulse contains more than 3 line
pulses.
The internal blanking continues until the end of the last measured line.
The vertical blanking pulse is not allowed to contain more than 34 line pulses, otherwise another control cycle begins.
8. The sandcastle pulse is compared with three internal thresholds (proportional to VP) and the given levels separate
the various pulses.
9. Blanked to ultra-black (-25%).
10. Pulse duration ³ 3,5 ms.


TDA4555 TDA4556 Multistandard decoder
GENERAL DESCRIPTION
The TDA4555 and TDA4556 are monolithic integrated
multistandard colour decoders for the PAL, SECAM,
NTSC 3,58 MHz and NTSC 4,43 MHz standards. The
difference between the TDA4555 and TDA4556 is the
polarity of the colour difference output signals (B-Y)
and (R-Y).
Features
Chrominance part
· Gain controlled chrominance amplifier for PAL, SECAM
and NTSC
· ACC rectifier circuits (PAL/NTSC, SECAM)
· Burst blanking (PAL) in front of 64 ms glass delay line
· Chrominance output stage for driving the 64 ms glass
delay line (PAL, SECAM)
· Limiter stages for direct and delayed SECAM signal
· SECAM permutator
Demodulator part
· Flyback blanking incorporated in the two synchronous
demodulators (PAL, NTSC)
· PAL switch
· Internal PAL matrix
· Two quadrature demodulators with external reference
tuned circuits (SECAM)
· Internal filtering of residual carrier
· De-emphasis (SECAM)
· Insertion of reference voltages as achromatic value
(SECAM) in the (B-Y) and (R-Y) colour difference output
stages (blanking)
Identification part
· Automatic standard recognition by sequential inquiry
· Delay for colour-on and scanning-on
· Reliable SECAM identification by PAL priority circuit
· Forced switch-on of a standard
· Four switching voltages for chrominance filters, traps
and crystals
· Two identification circuits for PAL/SECAM (H/2) and
NTSC
· PAL/SECAM flip-flop
· SECAM identification mode switch (horizontal, vertical
or combined horizontal and vertical)
· Crystal oscillator with divider stages and PLL circuitry
(PAL, NTSC) for double colour subcarrier frequency
· HUE control (NTSC)
· Service switch.




TDA1082 East-West correction driver circuit


GENERAL DESCRIPTION
The TDA1082 is a monolithic integrated circuit driving east-west correction of colour tubes in television receivers.
The circuit can be used for class-A and class-D operation and incorporates the following functions:
· differential input amplifier
· squaring stage
· differential output amplifier with driver stage
· protection stage with threshold
· switching off the correction during flyback
· voltage stabilizer.


TDA2595 Horizontal combination

GENERAL DESCRIPTION
The TDA2595 is a monolithic integrated circuit intended for use in colour television receivers.
Features
· Positive video input; capacitively coupled (source impedance < 200 W)
· Adaptive sync separator; slicing level at 50% of sync amplitude
· Internal vertical pulse separator with double slope integrator
· Output stage for vertical sync pulse or composite sync depending on the load; both are switched off at muting
· j1 phase control between horizontal sync and oscillator
· Coincidence detector j3 for automatic time-constant switching; overruled by the VCR switch
· Time-constant switch between two external time-constants or loop-gain; both controlled by the coincidence detector j3
· j1 gating pulse controlled by coincidence detector j3
· Mute circuit depending on TV transmitter identification
· j2 phase control between line flyback and oscillator; the slicing levels for j2 control and horizontal blanking can be set
separately
· Burst keying and horizontal blanking pulse generation, in combination with clamping of the vertical blanking pulse
(three-level sandcastle)
· Horizontal drive output with constant duty cycle inhibited by the protection circuit or the supply voltage sensor
· Detector for too low supply voltage
· Protection circuit for switching off the horizontal drive output continuously if the input voltage is below 4 V or higher
than 8 V
· Line flyback control causing the horizontal blanking level at the sandcastle output continuously in case of a missing
flyback pulse
· Spot-suppressor controlled by the line flyback control.


TDA2545A Quasi-split-sound circuitGENERAL DESCRIPTION The TDA2545A is a monolithic integrated circuit for quasi-split-sound processing in television receivers. Features · 3-stage gain controlled i.f. amplifier · A.G.C. circuit · Reference amplifier and limiter amplifier for vision carrier (V.C.) processing · Linear multiplier for quadrature demodulation.


TDA2541 IF AMPLIFIER WITH DEMODULATOR AND AFC
DESCRIPTION
The TDA2540 and 2541 are IF amplifier and A.M.
demodulator circuits for colour and black and white
televisionreceiversusingPNPorNPNtuners. They
are intended for reception of negative or positive
modulation CCIR standard.
They incorporate the following functions : .Gain controlled amplifier .Synchronous demodulator .White spot inverter .Video preamplifier with noise protection .Switchable AFC .AGC with noise gating .Tuner AGC output (NPN tuner for 2540)-(PNP
tuner for 2541) .VCR switch for video output inhibition (VCR
play back).


uPC1394C SWITCHING REGULATOR IC FOR TV SET

The ,uPC1394C is a switching regurator IC especially designed for TV sets. lt can be used for both type of TV sets, insulated
type and no insulated type.
It operates in synchronizing with the horizontal retrace pulse, so does not generates any visual noise in the picture on CRT.
The output transistor in a powersupply circuit is protected doubly by the internal protection circuit for over load.
ON/OFF operation of the powersupply is able to operated easily without any mechanical relay using provided terminal. So
2 timer operation, remote control and etc. are very easy.
Wide range of regulating input line voltage. : AC 80 to 280 V
The output power transistor is doubly protected by the '
current limitter and the shut down circuit.
I No visual noise due to horizontal synchronous operation.
A terminal for remote control, timer operation and etc.
of the powersupply is provided.
Shut down circuit is easily resetable using ON/OFF

Low stand-by and starting current. (2 mA)

SONY  KV-27XR TA  CHASSIS SCC-783B-A  (SX)   Synchronized switch-mode power supply:

In a switch mode power supply, a first switching transistor is coupled to a primary winding of an isolation transformer. A second switching transistor periodically applies a low impedance across a second winding of the transformer that is coupled to an oscillator for synchronizing the oscillator to the horizontal frequency. A third winding of the transformer is coupled via a switching diode to a capacitor of a control circuit for developing a DC control voltage in the capacitor that varies in accordance with a supply voltage B+. The control voltage is applied via the transformer to a pulse width modulator that is responsive to the oscillator output signal for producing a pulse-width modulated control signal. The control signal is applied to a mains coupled chopper transistor for generating and regulating the supply voltage B+ in accordance with the pulse width modulation of the control signal.
Some television receivers have signal terminals for receiving, for example, external video input signals such as R, G and B input signals, that are to be developed relative to the common conductor of the receiver. Such signal terminals and the receiver common conductor may be coupled to corresponding signal terminals and common conductors of external devices, such as, for example, a VCR or a teletext decoder.

To simplify the coupling of signals between the external devices and the television receiver, the common conductors of the receiver and of the external devices are connected together so that all are at the same potential. The signal lines of each external device are coupled to the corresponding signal terminals of the receiver. In such an arrangement, the common conductor of each device, such as of the television receiver, may be held "floating", or conductively isolated, relative to the corresponding AC mains supply source that energizes the device. When the common conductor is held floating, a user touching a terminal that is at the potential of the common conductor will not suffer an electrical shock.

Therefore, it may be desirable to isolate the common conductor, or ground, of, for example, the television receiver from the potentials of the terminals of the AC mains supply source that provide power to the television receiver. Such isolation is typically achieved by a transformer. The isolated common conductor is sometimes referred to as a "cold" ground conductor.

In a typical switch mode power supply (SMPS) of a television receiver the AC mains supply voltage is coupled, for example, directly, and without using transformer coupling, to a bridge rectifier. An unregulated direct current (DC) input supply voltage is produced that is, for example, referenced to a common conductor, referred to as "hot" ground, and that is conductively isolated from the cold ground conductor. A pulse width modulator controls the duty cycle of a chopper transistor switch that applies the unregulated supply voltage across a primary winding of an isolating flyback transformer. A flyback voltage at a frequency that is determined by the modulator is developed at a secondary winding of the transformer and is rectified to produce a DC output supply voltage such as a voltage B+ that energizes a horizontal deflection circuit of the television receiver. The primary winding of the flyback transformer is, for example, conductively coupled to the hot ground conductor. The secondary winding of the flyback transformer and voltage B+ may be conductively isolated from the hot ground conductor by the hot-cold barrier formed by the transformer.

It may be desirable to synchronize the operation of the chopper transistor to horizontal scanning frequency for preventing the occurrence of an objectionable visual pattern in an image displayed in a display of the television receiver.

It may be further desirable to couple a horizontal synchronizing signal that is referenced to the cold ground to the pulse-width modulator that is referenced to the hot ground such that isolation is maintained.

A synchronized switch mode power supply, embodying an aspect of the invention, includes a transfromer having first and second windings. A first switching arrangement is coupled to the first winding for generating a first switching current in the first winding to periodically energize the second winding. A source of a synchronizing input signal at a frequency that is related to a deflection frequency is provided. A second switching arrangement responsive to the input signal and coupled to the second winding periodically applies a low impedance across the energized second winding that by transformer action produces a substantial increase in the first switching current. A periodic first control signal is generated. The increase in the first switching current is sensed to synchronize the first control signal to the input signal. An output supply voltage is generated from an input supply voltage in accordance with the first control signal.


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SAA5230 TELETEXT VIDEO PROCESSORDESCRIPTION
The SAA5230 is a bipolar integrated
circuit intended as a successor to
SAA5030. lt extracts teletext data from
the video signal, regenerates teletext
clock, and synchronizes the text display
to the television syncs. The integrated
circuit is intended to work in conjunction
with CCT (SAA5040, Computer Con-
trolled Teletext), EUROM SAA5350 or
other compatible devices.

SAA5230
Teletext Video Processor

FEATURES PIN CONFIGURATION
Adaptive data slicer N Package
Data clock regenerator
Sync separator, line phase svnc our
detector, and 6MHz VCO forming
display phase-locked loop (PLL)
Performs all of the functions of mas

Integration and signal quality
detection zsno LEVEL
» when used with the sAAs24o,
microprocessor-controlled
teletext data acquisition system ms;
can be easily implemented
o Good data slicing capability in
the presence of echoes and
noise with high-frequency loss euo gg gn vw
compensation nc in in Tru
0 On-chip clock regeneration
circuitry can operate with
different data rates
0 On-chip PLL allows display to be
easily locked to a VCR
0 Minimal number of external
components/adjustments

APPLICATIONS
0 Teletext
0 Data sllclng and clock
regeneration
0 Phase locking with incoming video

SONY  KV-27XR TA  CHASSIS SCC-783B-A  (SX) SONY TRINITRON CONVERGENCE DEFLECTING DEVICE FOR SINGLE-GUN, PLURAL-BEAM COLOR PICTURE TUBEIn a color picture tube of the single-gun, plural-beam type in which a central beam and two side beams originate in a common horizontal plane and are all made to pass through the center of an electron lens for focussing the beams on the color screen with the central beam emerging from the lens along the optical axis of the latter and the side beams emerging from the lens along paths that are oppositely divergent from the axis, the divergent side beams are acted upon by an electrostatic convergence deflecting device constituted by pairs of horizontally spaced plates arranged along the divergent paths and having voltages applied thereacross to produce electric fields by which the divergent side beams passing therethrough are deflected to converge at a common spot with the central beam on the apertured grill or mask associated with the screen, and a main deflection yoke produces magnetic fields by which the beams are deflected horizontally and vertically, respectively, for causing the beams to scan the screen; the horizontal distances between the plates of each pair are varied in the vertical direction from a maximum at the common horizontal plane to minimums at the opposed edges of the plates remote from such common plane so as to correspondingly vary the strengths of the electric fields and thus correct distortions in the rasters of the side beams.


1. A single-gun, plural-beam color picture tube comprising a color screen, beam generating means directing a central beam and two side beams in a common horizontal plane toward said screen, electron lens means defining a focusing field having a center through which the beams pass and by which the bundle of electrons in each of the beams are focused on said color screen with the central beam emerging from said lens along the optical axis of the latter and said two side beams emerging from said lens along paths that are oppositely divergent from said central beam, electrostatic convergence deflecting means including a pair of horizontally spaced plates arranged along each of said divergent paths, said spaced plates of each pair being disposed at the inside and outside, respectively, of the side beam in the related divergent path and having voltages applied thereacross to produce an electric field by which the respective side beam passing therethrough is deflected horizontally to converge at a common spot with said central beam and the other of said side beams, and a main deflection yoke producing magnetic fields by which said beams are deflected horizontally and vertically respectively, for causing the beams to scan said screen and produce respective rasters on the latter; said convergence deflecting means being located within the field produced by said yoke to deflect said beams vertically so that said beams are similarly deflected vertically within said convergence deflecting means, and the horizontal distance between said plates of each of said pairs varying progressively in the vertical direction normal to said common horizontal plane from a maximum at said common horizontal plane to minimums at the opposed edges of the plates remote from said common plane so as to correspondingly vary the strength of the respective electric field for changing the rasters of said side beams with respect to the raster of said central beam and thereby compensating for deviations between said rasters as produced by said magnetic fields of the main deflection yoke. 2. A single gun, plural-beam color picture tube according to claim 1, in which the inner plate of each of said pairs which is closest to said central beam is flat, and the other plate of the respective pair is convex at the side thereof facing away from said inner plate. 3. A single-gun, plural-beam color picture tube according to claim 1, in which the plates of each of said pairs are convex at the sides thereof facing away from each other.

Description:

This invention relates generally to color picture tubes of the single-gun, plural-beam type, and particularly to tubes of that type in which the plural beams are passed through the optical center of a common electron lens by which the beams are focussed on the color phosphor screen.

In single-gun, plural-beam color picture tubes of the described type, for example, as specifically disclosed in U.S. Pat. No. 3,448,316, issued June 3, 1969, and having a common assignee herewith, three laterally spaced electron beams are emitted by a beam generating or cathode assmebly and directed in a common substantially horizontal plane with the central beam coinciding with the optical axis of the single electron focussing lens and the two outer or side beams being converged to cross the central beam at the optical center of the lens and thus emerge from the latter along paths that are divergent from the optical axis. Arranged along such divergent paths are respective pairs of convergence deflecting plates constituting a convergence deflecting device and having voltages applied thereacross to produce electric fields which laterally deflect the divergent beams in a substantially horizontal plane for causing all beams to converge at a common spot on the apertured beam selecting grill or shadow mask associated with the color screen. Further, arranged between the convergence deflecting device and the screen is a main deflection yoke which, in response to its reception of horizontal and vertical sweep signals, produces horizontal and vertical magnetic deflection fields acting on all of the beams to cause the latter to scan the color screen in predetermined rasters. Since the beams are horizontally spaced and non-parallel during their passage through the horizontal deflection field, the distances that the side beams travel through such field will be respectively greater and less than the distance that the central beam travels through the field when the beams are deflected toward one side or the other side of the screen. If the horizontal deflection field has a uniform flux density thereacross, the side beam traveling therethrough for the greater distance will be deflected to a greater extent than the side beam traveling the shorter distance through the field and misconvergence of the beams will result. Even if the horizontal deflection field is given a non-uniform flux density thereacross, misconvergence of the beams can be thereby avoided only when the beams are deflected toward one side or the other of the screen midway between the top and bottom of the screen, that is, when the common plane of the beams passing through the horizontal deflection field is directed horizontally, that is, substantially perpendicular to the vertical lines of magnetic flux of the horizontal deflection field. However, when the common plane of the beams passing through the horizontal deflection field is substantially inclined from the horizontal, that is, when the vertical deflection field deflects the beams to cooperate with the horizontal deflection field in directing the beams toward an upper or lower corner of the screen, the difference between the distances traveled by the side beams through the horizontal deflection field is further increased and hence may not be compensated by the non-uniform flux density established across the horizontal deflection field. Thus, the rasters of the side beams may have shapes that are oppositely distorted with respect to the shape of the raster of the central beam.

Accordingly, it is an object of this invention to provide a single-gun, plural-beam color picture tube in which the rasters of the several beams are free of distortion with respect to each other.

Another object is to provide a single-gun, plural-beam color picture tube in which distortions of the rasters of the several beams are avoided by a particular construction of the convergence deflecting device.

In accordance with an aspect of the invention, the described distortions of the rasters of the side beams with respect to the raster of the central beam are avoided by suitably varying, in the direction perpendicular to the common plane in which the beams originate, the distances between the paired plates of the convergence deflecting device, whereby to correspondingly vary the strengths of the electric fields between such plates by which the side beams are convergently deflected.

The above, and other objects, features and advantages of this invention, will be apparent in the following detailed description of illustrative embodiments which is to be read in connection with the accompanying drawing, wherein:

FIG. 1 is a schematic sectional view in a horizontal plane passing through the axis of a single-gun, plural-beam color picture tube of the type to which this invention is preferably applied;

FIG. 2 is a diagrammatic view to which reference is hereinafter made in explaining the invention;

FIG. 3 is a diagrammatic view showing the possible relative distortions of the rasters of the several beams, as seen from the viewer's side of the tube screen, and which are to be avoided by this invention;

FIG. 4 is a diagrammatic, transverse sectional view through the convergence deflecting device of a color picture tube according to a first embodiment of this invention; and

FIGS. 5-8 are views similar to FIG. 4, but showing other embodiments of the invention.

Referring to the drawings in detail, and initially to FIG. 1 thereof, it will be seen that a single-gun, plural-beam color picture tube of the type to which this invention may be applied comprises a glass envelope (indicated in broken lines) having a neck N and cone C extending from the neck to a color screen S provided with the usual arrays of color phosphors S _R , S _G and S _B and with an apertured beam selecting grill or shadow mask G _P . Disposed within neck N is an electron gun A having cathodes K _R , K _G and K _B , each of which is constituted by a beam-generating source with the respective beam-generating surfaces thereof disposed as shown in a plane which is substantially perpendicular to the axis of the electron gun A. In the embodiment shown, the beam-generating surfaces are arranged in a straight line so that the respective beams B _R , B _G and B _B emitted therefrom are directed in a substantially horizontal plane containing the axis of the gun, with the central beam B _G being coincident with such axis. A first grid G ₁ is spaced from the beam-generating surfaces of cathodes K _R , K _G and K _B and has apertures g _1R , g _1G and g _1B formed therein in alignment with the respective cathode beam-generating surfaces. A common grid G ₂ is spaced from the first and grid G ₁ and has apertures g _2R , g _2G and g _{2B 1} . Successively arranged in the axial direction away from the common grid G ₂ are open-ended, tubular grids or electrodes G ₃ , G ₄ and G ₅ , respectively with cathodes K _R , K _G and K _B , grids G ₁ and G ₂ , and electrodes G ₃ , G ₄ and G ₅ being suitably maintained in the depicted, assembled positions thereof. formed therein in alignment with the respective apertures of the first grid G
For operation of the electron gun A of FIG. 1, appropriate voltages are applied to the grids G _{1 2} and to the electrodes G ₃ , G ₄ and G ₅ . Thus, for example, a voltage of 0 to minus 400V is applied to the grid G ₁ , a voltage of 0 to 500V is applied to the grid G ₂ , a voltage of 13 to 20KV is applied to the electrodes G ₃ and G ₅ , and a voltage of 0 to 400V is applied to the electrode G ₄ , with all of these voltages being based upon the cathode voltage as a reference. As a result, the voltage distributions between the respective electrodes and cathodes, and the respective lengths and diameters thereof, may be substantially identical with those of a unipotential-single beam type electron gun which is constituted by a single cathode and first and second, single-apertured grids. and G
With the applied voltage distribution as described hereinabove, an electron lens field will be established between grid G ₂ and the electrode G ₃ to form an auxiliary lens L' as indicated in dashed lines, and an electron lens field will be established around the axis of electrode G ₄ , by the electrodes G ₃ , G ₄ and G ₅ , to form a main lens L, again as indicated in dashed lines. In a typical use of electron gun A, bias voltages of 100V, 0V, 300V, 20KV, 200V and 20V may be applied respectively to the cathodes K _R , K _G and K _B , the first and second grids G ₁ and G ₂ and the electrodes G ₃ , G ₄ and G ₅ .

Further included in the electron gun A of FIG. 1 and electron beam convergence deflecting means F which comprise inner shielding plates P and P' disposed in the depicted spaced, relationship at opposite sides of the gun axis, and axially extending, deflector plates Q and Q' which are disposed, as shown, in outwardly spaced, opposed relationship to shielding plates P and P', respectively. Although depicted as substantially straight, it is to be understood that the deflector plates Q and Q' may, alternatively, be somewhat curved or outwardly bowed, as is well known in the art.

The shielding plates P and P' are equally charged and disposed so that the central electron beam B _G will pass substantially undeflected therebetween, while the deflector plates Q and Q' have negative charges with respect to the plates P and P' so that electron beams B _B and B _R will be convergently deflected as shown by the respective passages thereof between the plates P and Q and the plates P' and Q'. More specifically, a voltage V _P which is equal to the voltage applied to the electrode G ₅ , may be applied to both shielding plates P and P', and a voltage V _Q , which is some 200 to 300V lower than the voltage V _P , is applied to the plates Q and Q' to result in the plates P and P' being at the same potential, and in the application of a deflecting voltage difference or convergence deflecting voltages V _C between the plates P' and Q' and the plates P and Q and it is, of course, this convergence deflecting voltage V _C which will impart the requisite convergent deflection to the electron beams B _B and B _R .

In operation, the electron beams B _R , B _G and B _B which emanate from the beam generating surfaces of the cathodes K _R , K _G and K _B will pass through the respective grid apertures g _1R , g _1G and g _1B , to be intensity modulated with what may be termed the "red", "green" and "blue" intensity modulation signals applied between the said cathodes and the first grid G ₁ . The electron beams will then pass through the common auxiliary lens L' to cross each other at the center of the main lens L. Thereafter, the central electron beam B _G will pass substantially undeflected between sheilding plates P and P' since the latter are at the same potential. Passage of the electron beam B _B between the plates P' and Q' and of the electron beam B _R between the plates P and Q will, however, result in the convergent deflections thereof as a result of the convergence deflecting voltage V _Q applied therebetween, and the system of FIG. 1 is so arranged that the electron beams B _B , B _G and B _R will desirably converge or cross each other at a common spot centered in an aperture of the beam selecting grill or mask G _P so as to diverge therefrom to strike the respective color phosphors of a corresponding array thereof on screen S. More specifically, it may be noted that the color phosphor screen S is composed of a large plurality of sets or arrays of vertically extending "red", "green" and "blue" phosphor stripes or dots S _R , S _{G B} with each of the arrays or sets of color phosphors forming a color picture element. Thus, it will be understood that the common spot of beam convergence corresponds to one of the thusly formed color picture elements. and S
The voltage V _P may also be applied to the lens electrodes G ₃ and G ₅ and to the screen S as an anode voltage as well as to the aperture grill G _p . Electron beam scanning of the face of the color phosphor screen is effected in conventional manner, for example, main deflection yoke means indicated in broken lines at D and which receives horizontal and vertical sweep signals to produce horizontal and vertical deflection fields by which the beams are made to scan the screen for providing a color picture thereon. Since, with this arrangement, the respective electron beams are each passed, for focussing, through the center of the main lens L of the electron gun A, the beam spots formed by impingement of the beams on the color phosphor screen S will be substantially free from the effects of coma and/or astigmatism of the same main lens, whereby improved color picture resolution will be provided.

In the color picture tube as illustrated on FIG. 1, plates P and P' and plates Q and Q' are shown flat and parallel with each other so that the electric fields between plates P and Q and plates P' and Q' are substantially uniform thereacross, that is, in the direction perpendicular to the common horizontal plane of beams B _B , B _G and B _B . Thus, as the beams are vertically deflected by the vertical deflection field of yoke D so as to be directed at the upper or lower portions of screen S and such vertical deflection field vertically displaces the beams within convergence deflecting device F, the deflecting effects on beams B _B and B _R of the fields between plates P and Q and plates P' and Q', respectively, are substantially unchanged. However, as shown on FIG. 2, when the horizontal deflection field of yoke D deflects the beams toward the left side of the screen as seen from the viewer's side of the latter, that is, downwardly as viewed on FIG. 2, the side beams B _B and B _R travel distances through such horizontal deflection field that are respectively greater than and smaller than the distance that the central beam B _G travels through the horizontal deflection field. Conversely, when the horizontal deflection field of yoke D deflects the beams toward the right side of the screen as viewed from the viewer's side, the distances traveled by the beams B _B and B _R through the horizontal deflection field are respectively smaller than and greater than the distance that the central beam B _G travels through such field. By reason of the foregoing differences between the distances that the beams travel through the horizontal deflection field when deflected by the latter toward one side or the other of the screen S, the raster of beam B _B and the raster of beam B _R would be displaced toward the left and toward the right, respectively, from the raster of the beam B _G , as seen from the viewer's side of the screen. If the horizontal deflection field of yoke D is given a non-uniform flux density thereacross, for example, a greater flux density at the sides than at the middle of the field, the described relative displacements of the rasters can be compensated for so long as the common plane of the beams is substantially horizontal, that is, so long as the beams are directed at the screen substantially midway between the top and bottom of the screen. However, when the horizontal deflection field of yoke D directs the beams toward one side or the other of the screen at a time when the vertical deflection field of yoke D deflects the beams vertically so that the common plane of the beams is substantially inclined from the horizontal to direct the beams toward a corner of the screen, the differences between the distances traveled by the beams through the horizontal deflection field are further increased, as compared with the differences in the distances traveled through the field when the common plane of the beams is horizontal, so that even the mentioned non-uniform flux density across the horizontal deflection field of yoke D would be ineffective to avoid distortions of the rasters of beams B _B and B _R relative to the raster of beam B _G .

Assuming that the raster of central beam B _G has a rectangular shape, as indicated at L _G on FIG. 3, the raster L _B of beam B _B , as seen from the viewer's side of the screen, is distorted in the sense that its sides are convex toward the right, while the raster L _R of beam B _R is oppositely distorted, that is, its sides are convex toward the left.

In accordance with the present invention, such distortions of the rasters of side beams B _B and B _R relative to the raster of central beam B _G are avoided by suitably varying, in the direction perpendicular to the common plane in which the beams originate, for example, in the vertical direction for the tube of FIG. 1, the distances by which plates P and Q and plates P' and Q' are spaced from each other. For example, in the embodiment shown by FIG. 4, plates P and P' are made flat or planar while plates Q and Q' are outwardly concave in the vertical direction or the direction across the plates, whereby the distances between plates P and Q and between plates P' and Q' are relatively small at the horizontal plane 21 containing the tube axis and such distances between the plates increase progressively in the direction of vertical plane 22 upwardly and downwardly from horizontal plane 21 in which the beams all originate.

Since convergence deflecting device F is disposed adjacent the main deflecting yoke D (FIG. 1), it will be apparent that the vertical deflection field of yoke D will extend into device F, and thereby influence the vertical positions of the beams B _B , B _G and B _R in passing through device F. Thus, when the vertical and horizontal deflection fields of yoke D are effective to direct the beams toward a corner of the screen, the vertical deflection field of yoke D will vertically displace beams B _R , B _G and B _B either upwardly or downwardly from plane 21 within convergence deflection device F. By reason of the increased distance betweeen plates P and Q and plates P' and Q' at such displaced positions of beams B _B and B _R , the parts of the electric fields then acting on such beams will be of relatively reduced intensity thereby to similarly reduce the convergent deflections imparted to beams B _B and B _R . Thus, for example, when the beams are horizontally and vertically deflected by yoke D so as to be directed at the upper or lower left-hand corner of the screen, as seen from the viewer's side thereof, the left-ward deflection of beam B _B by the field between plates P and Q will be reduced and the right-ward deflection of beam B _R by the field between plates P' and Q' will be similarly reduced, whereby to bring the left-hand sides of the rasters L _B and L _R , as seen on FIG. 3, into agreement with the left-hand side of the raster L _G . Similarly, when the beams are horizontally and vertically deflected by yoke D so as to be directed at the upper or lower right-hand corner of the screen as viewed on FIG. 3, the left-ward and right-ward deflections of beams B _B and B _R , respectively, by the fields between plates P and Q and plates P' and Q' will be reduced whereby to bring the right-hand sides of rasters L _B and L _R into agreement with the right-hand side of raster L _G . Thus, distortions of the rasters L _B and L _R relative to the raster L _G can be effectively avoided by suitably selecting the position of convergence deflecting device F relative to yoke D and the shapes of plates Q and Q'.

As shown on FIGS. 5 and 7, the effect described above may also be achieved by providing flat or planar outer plates Q and Q' and outwardly convex inner plates P and P' (FIG. 5), or by providing outer plates Q and Q' that are inwardly convex and inner plates P and P' that are outwardly convex (FIG. 7). In each of these modifictions, the distances between plates P and Q and between P' and Q' vary from a minimum at the horizontal plane passing through the tube axis to maximums at the upper and lower portions of the plates to conversely vary the strengths of the electrical fields between plates P and Q and plates P' and Q'. Since plates P and P' are at equal potential there is no electric field established therebetween, and thus the varying distance between plates P and P' in FIGS. 5 and 7 does not affect beam B _G as the latter is vertically deflected.

Of course, in the foregoing, it has been assumed that the distortions of rasters L _B and L _R relative to raster L _G that are to be corrected are those shown on FIG. 3. However, a situation may arise, for example, by reason of a particular configuration of the horizontal deflection field produced by yoke D, in which the raster of beam B _B has the shape indicated at L _R on FIG. 3 while the raster of beam B _R has the shape indicated at L _R . In the latter case, the plates P and Q and the plates P' and Q' are shaped so that the distances therebetween are maximum at the horizontal plane containing the axis of the tube and decrease progressively therefrom in the vertical direction, that is, in the direction perpendicular to the common plane in which the beams originate. In achieving such variations in the distances between the plates, plates P and P' may be flat or planar and plates Q and Q' may be outwardly convex (FIG. 6), or plates P and P' may be inwardly convex and plates Q and Q' may be outwardly convex (FIG. 8).

Further, in each of the above described embodiments of this invention, the convergence deflection device F consists of only a single pair of plates P and Q or P' and Q' acting on each of the beams B _B and B _R to deflect the respective beam in the direction for convergence with the central beam B _G . However, the invention can also be applied to color picture tubes, for example, as disclosed in the copending U.S. application Ser. No. 718,738, filed Apr. 4, 1968, and having a common assignee herewith, in which the beams following paths diverging from the tube axis upon emerging from the focussing lens are each successively acted upon by two pairs of deflecting plates, with the first pair of plates establishing an electric field therebetween by which the respective beam is further diverged from the tube axis and the second pair of plates establishing a field therebetween by which the beam is deflected in the direction for converging with the other beams. The foregoing arrangement makes it possible to increase the angles of incidence of the side beams B _B and B _R at the beam selecting apertured grill or mask G _P , whereby to permit a decrease in the distance of the latter from screen S for facilitating the accurate locating and mounting of the grill or mask G _P relative to the screen S. Where each of the side beams B _B and B _R is successively acted upon by two pairs of deflecting plates, as aforesaid, one or the other of such pairs of plates, and preferably the pair of plates closest to the location of the main deflection yoke, is provided with a distance between the plates that varies in the direction perpendicular to the common plane in which the beams originate so as to avoid distortion of the raster of the respective beam in accordance with this invention.

Having described various embodiments of this invention, it is to be understood that the invention is not limited to those precise embodiments, and that various changes and modifications may be effected therein by one skilled in the art without departing from the scope or spirit of the invention.

SONY  KV-27XR TA  CHASSIS SCC-783B-A  (SX) SONY TRINTRON DYNAMIC CONVERGENCE CIRCUIT

A dynamic convergence circuit for color television receivers which has a dynamic convergence winding connected in series to an output coil provided for a horizontal deflection output device performing the switching operation and an impedance element connected in parallel to the dynamic convergence winding. A horizontal pulse voltage appears at the output coil and the output coil is operative to integrate the horizontal pulse voltage in cooperation with the impedance element to supply a current of generally parabolic waveform with a horizontal scanning period repetition to the dynamic convergence winding, to thereby maintain the proper beam convergence in response to beam scanning.

1. A dynamic convergence circuit for a plural beam cathode ray tube comprising: 2. A dynamic convergence circuit as recited in claim 1 including a power source for operating the horizontal deflection output device and wherein the series connection of the inductance means and the convergence coil device is connected between the output of the output device and one end of the power source. 3. A dynamic convergence circuit as recited in claim 2, wherein the output device comprises a transistor performing the switching operation in response to a horizontal driving signal supplied thereto from an external source. 4. A dynamic convergence circuit as recited in claim 1, wherein the impedance means comprises a series connection of a capacitor and a resistor. 5. A dynamic convergence circuit as recited in claim 4, wherein the resistor comprises a variable resistor for varying the tilt of the sawtoothed waveform voltage supplied to the convergence coil device. 6. A dynamic convergence circuit as recited in claim 5 further comprising an additional variable resistor connected in parallel with the convergence coil device for varying the amplitude of the parabolic waveform current flowing through the convergence coil device. 7. A dynamic convergence circuit for a plural beam cathode ray tube comprising: 8. A dynamic convergence circuit as recited in claim 7, wherein the current supplying means comprises a vertical deflection circuit and connecting means for connecting the vertical deflection circuit to the convergence coil device. 9. A dynamic convergence circuit as recited in claim 8, wherein the connecting means includes filter means for preventing the current of parabolic waveform with horizontal period repetition from being fed to the vertical deflection circuit. 10. A dynamic convergence circuit as recited in claim 7, wherein the current supplying means comprises a pin-cushion compensating circuit provided for modulating the horizontal beam deflection current with a signal of parabolic waveform with vertical scanning period repetition.

Description:

BACKGROUND OF THE INVENTION

1. Field of the Invention

This invention relates generally to dynamic convergence circuits for plural electron beam display apparatus such as a color television receiver, and is more particularly directed to an improved dynamic convergence circuit of reduced complexity provided together with a horizontal deflection circuit.

2. Description of the Prior Art

In most color cathode ray tubes employed in color television receivers for commercial use at present, plural electron beams, for example, three electron beams are utilized. In such a color cathode ray tube, respective electron beams emitted from its electron gun are deflected for beam scanning by a deflection yoke provided around the neck portion of the tube. An aperture mask is provided in the tube in front of the color phosphor screen for determining the impinging positions of the electron beams on the color phosphor screen. The respective electron beams impinge on the positions corresponding to red, green and blue color phosphors in response to their incident angles to the aperture of the mask. Thus, the electron beams scan the color phosphor screen under the control of the deflection yoke to form separate images of different primary colors and hence to display a full color image on the color phosphor screen. In order to form a correct full color image on the screen it is required that the plural primary color images should be formed on the screen with a superposition relation over all the points on the screen. To this end, arriving positions of the plural electron beams on the screen are required to be in superposition. This superposition is achieved by not only a static correction means but also by a dynamic correction means generally called a convergence means.

The static convergence means is provided for converging the plural electron beams at the center of the screen when the deflection yoke is inoperative. However, when the deflection yoke is operative the plural electron beams are subjected to different degrees of deflection by the deflection yoke because the electron beams pass through the deflection field established by the deflection yoke at different portions thereof. As a result, the electron beams may mis-converge as they move from the center of the screen to its periphery.

To correct or compensate for the misconvergence of the electron beams, an additional dynamic convergence coil is provided as a dynamic convergence means in addition to the deflection yoke for beam scanning. The additional dynamic convergence coil is supplied with a current in accordance with a beam position to correct or compensate for the beam deflection state. To this end, a waveform of a generally parabolic shape with horizontal and/or vertical scanning period repetition is used as the current supplied to the dynamic convergence coil. Thus, the plural electron beams are deflected by the beam deflection field of the dynamic convergence coil to be converged correctly at all of points on the screen.

In the prior art, it has been proposed that the current having a waveform of parabolic shape with a repetition which is the same as the horizontal scanning period and which is fed to the dynamic deflection coil be formed by a circuit in which a horizontal pulse appearing at an output transformer of the horizontal deflection circuit is integrated by a series connection of a coil and a capacitor. The voltage of sawtooth waveform obtained across the capacitor is then fed to the dynamic convergence coil so as to apply the current of parabolic shape waveform. Such a circuit, however, is required to provide means for deriving the horizontal pulse from the horizontal output transformer, means for integrating the thus obtained horizontal pulse, means for adjusting the integrated pulse in amplitude and so on, separately, so that the circuit becomes complicated in construction.

SUMMARY OF THE INVENTION

The above and other disadvantages are overcome by the present invention of a dynamic convergence circuit for a plural beam cathode ray tube comprising a horizontal deflection output device provided for supplying a horizontal beam deflection current of generally sawtoothed waveform to a deflection coil for the horizontal scanning of beams, inductance means connected to the output of the output device, with a horizontal pulse voltage being produced at the inductance means, convergence coil means connected in series with the inductance means, and impedance means connected to the inductance means and in parallel with the convergence coil device, the impedance means being operative to integrate the horizontal pulse voltage in cooperation with the inductance means to supply a sawtoothed waveform voltage across the convergence coil and, by means of the sawtoothed waveform voltage, to have a current of generally parabolic waveform flow through the convergence coil device, thereby to maintain the proper convergence of the plural beams in response to the beam scanning.

In one preferred embodiment the output device comprises a transistor performing the switching operation in response to a horizontal driving signal supplied thereto. The impedance means comprises a series connection of a capacitor and a resistor. Furthermore in some embodiments the resistor comprises a variable resistor for varying the tilt of the sawtoothed waveform voltage supplied to the convergence coil device.

Accordingly, it is an object of this invention to provide an improved dynamic convergence circuit of reduced complexity for a plural beam color cathode ray tube.

Another object of this invention is to provide an improved dynamic convergence circuit which is simplified by being designed together with a horizontal deflection circuit.

The foregoing and other objectives, features, and advantages of the invention will be more readily understood upon consideration of the following detailed description of certain preferred embodiments of the invention, taken in conjunction with the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic circuit diagram showing one embodiment of a dynamic convergence circuit according to the present invention;

FIGS. 2 and 4 show waveforms used for explanation of the present invention; and

FIGS. 3, 5, 6 and 7 are schematic circuit diagrams respectively showing other embodiments of dynamic convergence circuits according to the present invention.

DESCRIPTION OF CERTAIN PREFERRED EMBODIMENTS

FIG. 1 is a circuit diagram for illustrating an embodiment of this invention. In the figure reference numeral 1 designates a horizontal driving circuit whose output terminal is connected to the base electrode of an NPN-type transistor 2 which forms a horizontal output circuit. The emitter electrode of the transistor 2 is grounded while its collector electrode is connected through a horizontal output winding 3 and a dynamic convergence coil 13 to an electric power source terminal 4 which is supplied with a DC voltage from an external source (not shown). The collector electrode of the transistor 2 is grounded through a parallel circuit of a damper diode 5 and a capacitor 6 and also through a series circuit of a horizontal deflection coil 7 and a deflection current wave compensation capacitor 8.

The dynamic convergence coil 13 is connected in series between the power source terminal 4 and the end of the horizontal output winding 3 remote from the transistor 2. A series circuit of a capacitor 11 and a variable resistor 12 is connected in parallel with the dynamic convergence coil 13. A variable resistor 14 for correction of the amplitude of a parabolic waveform current is also connected in parallel with the dynamic convergence coil 13. In this case, the capacitance of the capacitor 11 may be selected, for example, as 0.022 micro-Farads (μF), the resistance value of the variable resistor 12 may be selected within a range of from 220 ohms (Ω ) to 500 ohms (Ω ) and the inductance value of the dynamic convergence coil 13 may be selected to be 14 milli-Henries (mH) to resonate with a signal with a frequency of 15.75 KHz.

With the circuit constructed as above, a horizontal pulse obtained at the horizontal output winding 3 is substantially integrated by the horizontal output winding 3 and the capacitor 11 and then a sawtooth waveform current flows from the power source terminal 4 to the circuit ground through the capacitor 11, the variable resistor 12 and the horizontal output winding 3 to impress a sawtooth waveform voltage across the dynamic convergence coil 13. This results in a parabolic shape waveform current i _c with the horizontal scanning period repetition, which is shown in FIG. 2, flowing through dynamic convergence coil 13 to achieve the horizontal dynamic convergence compensation.

As mentioned above, with the circuit shown in FIG. 1 the parabolic shape waveform current flows through the dynamic convergence coil 13 without the provision of a separately provided coil for integration, so that the circuit construction is simplified.

Further, according to this invention if the resistance value of the variable resistor 12 is adjusted the phase or tilt of the parabolic shape waveform current i _c can be controlled as shown in FIG. 2 by a dotted line. If the resistance value of the variable resistor 14 is adjusted the amplitude of the parabolic shape waveform current i _c for the dynamic convergence compensation is controlled. In this case, it should be noted that, it is possible to adjust the amplitude and the tilt of the parabolic shape waveform current independently, which is an advantage of this invention.

FIGS. 3 and 5, respectively show other embodiments of this invention in which horizontal and vertical convergence compensations are both performed. In these figures reference numerals similar to those of FIG. 1 designate similar elements so that their description is omitted for the sake of brevity.

In the embodiment of FIG. 3, the collector electrode of the transistor 2 for the horizontal output circuit is connected directly to the power source terminal 4 and the parallel circuit of the damper diode 5 and capacitor 6 is connected between the collector and emitter electrodes of the transistor 2. The series circuit of the horizontal deflection coil 7 and capacitor 8 for deflection current wave compensation is also connected between the emitter and collector electrodes of the transistor 2. The emitter electrode of the transistor 2 is grounded through the series circuit of the horizontal output winding 3 and dynamic convergence coil 13. The connection point between the winding 3 and the coil 13 is grounded through the series circuit of the capacitor 11 and variable resistor 12 and also through the variable resistor 14. Thus, a parabolic shape waveform current flows through the horizontal dynamic convergence coil 13 in the same manner as in FIG. 1. The connection point between the horizontal output winding 3 and the dynamic convergence coil 13 is further connected to a coil 15, which servies as a horizontal frequency stopper, such that a parabolic shape waveform current with horizontal scanning period repetition is obtained at the coil 15 and is blocked from being applied to a point a.

In FIG. 3 reference numeral 16 indicates a vertical driving circuit whose output terminal is connected to base electrode of an NPN-type transistor 17. The collector electrode of the transistor 17 is connected through the base-collector junction of a transistor 18 to the base electrode of a transistor 21, which forms a SEPP-type output stage together with a transistor 20. The collector electrode of transistor 17 is also connected to the cathode of a diode 19 whose anode is connected to the base electrode of the transistor 20. The connection point between the emitter electrode of the transistor 20 and the collector electrode of the transistor 21 is connected to the emitter electrode of transistor 18 and through a series circuit of a vertical deflection coil 22, capacitors 23 and 24 to the emitter electrode of the transistor 17. A sawtooth waveform current flows through the vertical deflection coil 22 so that a parabolic shape waveform current with a vertical scanning period repetition is delivered to the connection point a between the two capacitors 23 and 24.

With the circuit shown in FIG. 3 a current i' _c , in which the parabolic shape waveform current with the vertical scanning period repetition for vertical dynamic convergence compensation is superimposed on the parabolic shape waveform current with the horizontal scanning period repetition for horizontal dynamic convergence compensation is obtained as shown in FIG. 4 to perform both vertical and horizontal dynamic convergence compensation.

In the embodiment of FIG. 5 a parabolic shape waveform current with the vertical scanning period repetition is obtained at the emitter electrode of the transistor 21 as described above in reference to the embodiment of FIG. 3. The connection point between the horizontal output winding 3 and the horizontal dynamic convergence coil 13 is connected through the coil 15, serving as a horizontal frequency stopper, to the common connection point a' of the emitter electrode of the transistor 21, a resistor 25 and a capacitor 26. The connection point between the emitter electrode of the transistor 20 and the collector electrode of the transistor 21 is connected through the vertical deflection coil 22 to another electric power source terminal 4' which is supplied with a DC voltage. The other circuit elements are connected in a manner similar to FIG. 3. The embodiment of FIG. 5 operates to attain the same effect as that of the embodiment of FIG. 3.

FIGS. 6 and 7, respectively show further embodiments of this invention in which reference numerals similar to those of the foregoing figures indicate similar elements. In these embodiments a pin-cushion compensation signal, which is applied to the horizontal deflection circuit for compensation of pin-cushion distortion of the raster, is used for vertical dynamic convergence.

In the embodiment of FIG. 6, the connection point between the horizontal output winding 3 and the dynamic convergence coil 13 is grounded through the series circuit of the coil 15 serving as a horizontal frequency stopper and a capacitor 27. The connection point between the coil 15 and the capacitor 27 is connected to the collector electrode of an NPN-type transistor 28 whose emitter electrode is grounded. An input terminal 28a for a pin-cushion compensation signal is connected to the base electrode of the transistor 28. The input terminal 28a may be supplied with a parabolic shape waveform current with a vertical scanning period repetition for pin-cushion compensation. The dynamic convergence coil 13 is grounded through a capacitor 29 and the connection point between them is grounded through a series circuit of a variable resistor 30 and a capacitor 31 for amplitude compensation of the parabolic shape waveform current with the vertical scanning period repetition.

In the embodiment constructed as above, the parabolic shape waveform current with the vertical scanning period repetition for pin-cushion compensation is applied to the base electrode of the transistor 28, which is connected in parallel to the dynamic convergence coil 13, through the input terminal 28a, so that a first parabolic shape waveform current with a vertical scanning period repetition such as, for example, shown in FIG. 4, flows through the dynamic convergence coil 13 where a second parabolic shape waveform current, with the horizontal scanning period, is superimposed on the first parabolic shape waveform current. Accordingly, it should be apparent that the vertical and horizontal convergence compensations are achieved by this embodiment as in the embodiments shown in FIGS. 3 and 5.

Since the parabolic shape waveform current with the vertical scanning period repetition for pin-cushion compensation is used in the embodiment of FIG. 6 as mentioned above, a separate circuit for producing the parabolic shape waveform current can be dispensed with.

The embodiment shown in FIG. 7 is similar to that shown in FIG. 6 except that the dynamic convergence circuit of FIG. 6 is connected to the power source side of the horizontal output transistor 2. It will be easily understood that this embodiment performs the same effect as that mentioned above.

The terms and expressions which have been employed here are used as terms of description and not of limitation, and there is no intention in the use of such terms and expressions, of excluding equivalents of the features shown and described, or portions thereof, it being recognized that various modifications are possible within the scope of the invention claimed.

SONY  KV-27XR TA  CHASSIS SCC-783B-A  (SX) SONY TRINTRON Convergence means for color cathode ray tube

The beam forming means and static convergence correcting means in a color cathode ray tube are arranged to provide for proper convergence of the beams at regions remote from the center of the screen and closer to the corners. The resulting misconvergence at the center of the screen is then corrected by dynamic convergence correcting means which produces less beam distortion then if it had to correct misconvergence at the corners.


1. A convergence correction system for a color cathode ray tube comprising a fluorescent screen and means to produce three electron beams, said system comprising a deflection yoke to deflect said beams at line repetition rate in a raster pattern repeated at field repetition rate on said screen, and system further comprising:
static convergence correction means to cause said beams to be substantially fully converged to common points at certain outer regions of said screen and to be only partially converged at the central region of said screen; and
magnetic, dynamic, convergence correction means comprising a coil and current-generating means connected thereto to supply to said coil a magnetic convergence correction current that has a repetitive waveform with a maximum magnitude when said beams strike the central region of said screen and a lesser magnitude when said beams are deflected to strike said certain outer regions of said screen to cause said coil to produce a magnetic convergence field of greatest intensity when said beams strike said central region, whereby said beams are substantially fully converged at said central region.
2. The convergence correction system of claim 1 in which said static convergence correction means comprises:
electrostatic deflection means within said tube and positioned therein between said means to produce said beams and the location of said deflection means; and
substantially constant voltage means connected to said electrostatic deflection means to apply thereto deflection voltages of magnitudes sufficient to cause said beams to converge to common points at the outer region of said raster pattern and less than sufficient to cause said beams to converge to a common point at the center of said raster pattern.
3. The convergence correction system of claim 1 in which said vurrent-generating means comprises means to generate a correction current in which said repetitive waveform comprises parabolic segments of substantially equal amplitude and the same repetition rate as said line repetition rate. 4. The convergence correction system of claim 3 in which said current-generating means generates a current having second substantially parabolic waveform segments at a repetition rate equal to the field repetition rate of said raster, said first-named correction current and said second current being connected additively to said magnetic dynamic convergence correction means and the additive value of said first-named current and said second current being substantially equal to zero when said beams are deflected substantially to the corners of said raster. 5. A convergence correction system for a color cathode ray tube comprising a fluorescent screen and means to produce three electron beams directed generally toward said screen, said system comprising a magnetic deflection yoke located on said tube in a region between said means to produce said beams and said screen to deflect said beams in a raster pattern on said screen in response to deflection currents applied to said deflection yoke, said deflection yoke producing an electron lens with a strength that is a function of the deflection current and is substantially zero at the center of said raster, said system further comprising:
electrostatic static convergence deflection plates in said tube in a region between said means to produce said beams and said region on which said deflection yoke is located, said deflection plates having a fixed voltage applied thereto to produce a static convergence field to converge said beams in combination with the focusing effect of said yoke when said beams are deflected by said yoke to the outermost parts of said raster;
magnetic dynamic convergence means defining a lens field and comprising a coil; and
means to generate a convergence correction current to be applied to said coil to cause said magnetic dynamic convergence means to produce a magnetic electron lens having different horizontal and vertical strengths, the magnitudes of said strengths being a function of the magnitude of said current and varying from substantially zero when said beams are deflected to the outermost parts of said raster to a maximum when said beams are not deflected from the center of said raster, whereby said beams are converged at the center of said raster by the combined effects of said statis convergence field and said lens field of said magnetic dynamic convergence means when said deflection current in said yoke is substantially zero.
6. A convergence correction system for a color cathode ray tube comprising a fluorescent screen and means to produce three electron beams, sais system comprising a deflection yoke to produce a deflection field to deflect all of said beams simultaneously in a rectangular raster pattern comprising a plurality of substantially parallel lines generated on said screen at line repetition rate, said system further comprising:
static convergence means to produce, in cooperation with the deflection field of said yoke, a convergence field to cause said beams to be substantially fully converged to common points only when said beams are deflected to outer regions of said raster pattern;
magnetic dynamic convergence correction means comprising a coil and current generating means connected thereto to supply to said coul a convergence correction current comprising a parabolic waveform repetitive at said line repetition rate, said current having a maximum magnitude when said beams are directed to the central region of said screen and substantially zero magnitude when said beams are deflected to said outer regions of said raster pattern.
7. The method of correcting convergence of electron beams on a color cathode ray tube screen, said method comprising the steps of:
statically converging the beams near outer regions of the screen; and
imposing additional dynamic magnetic convergence fields on selective ones of said beams, said dynamic magnetic convergence fields having maximum intensity when the beams are in the central region of the screen to converge the beams in said central region.
8. The method of correcting convergence of a plurality of electron beams disposed in spaced relation substantially in a common plane and deflected along a series of lines defining a rectangular raster, said lines being substantially parallel to said plane and being the points of interception of said beams with a cathode ray tube screen, said method comprising:
statically deflecting said beams selectively parallel to said plane to cause all of said beams to converge at the corners of said raster; and
selectively imposing on said beams dynamic magnetic convergence fields having maximum intensity when the beams strike the central region of the raster, said dynamic convergence fields applying converging force to said beams in a direction parallel to said plane and substantially perpendicular to said beams.
9. The method of claim 8 in which said dynamic, magnetic, convergence fields have minimum intensity when beams are deflected to each end of each of said lines. 10. The method of claim 8 in which said dynamic magnetic convergence fields have minimum intensity only when said beams are deflected to the corners of said raster.

Description:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to convergence correction apparatus for color cathode ray tubes and particularly to apparatus that includes static and dynamic convergence correcting devices, at least the latter of which is a magnetic correcting device.
2. Description of the Prior Art
It has been the practice heretofore to provide proper focusing and convergence of the electron beams of a color cathode ray tube at the center of the screen when the magnetic deflection fields are not present and therefore are not contributing to any distortion of the beam or to any misconvergence. However, as the beams are deflected away from the center of the screen and particularly at the most distant locations in the four corners of the screen, the beams are subjected to magnetic fields and in some cases to electrostatic fields that cause the beams to strike different locations instead of being converged to a small area and further cause the cross sections of the beams to be distorted. Both of these effects cause the quality of the image to be deteriorated at the corners of the picture.
In addition, the change of beam size due to distortion affects the current density. Steps taken to correct the misconvergence at the corners still may leave the current density uncorrected. Since the luminance of the different phosphors is relatively linear only up to a certain maximum amount and is then saturated, and the point of saturation is different for the different phosphors, the hue of the image will be incorrect at the corners due to the fact that one of the phosphors will start to saturate first.
OBJECTS AND SUMMARY OF THE INVENTION
It is one of the objects of this invention to provide a simpler and better convergence arrangement for a color cathode ray tube.
Another object is to provide more uniform color balance over the entire cathode ray tube screen.
A further object is to provide improved convergence of the beams of a multibeam color cathode ray tube without producing high distortion of the beams.
Further objects will become apparent from the following description including the drawings.
In accordance with this invention a multibeam color cathode ray tube, particularly a tube of the general type shown and described in U.S. Pat. No. Re 27,751, has a static convergence correction device, such as a set of electrostatic deflection plates with applied voltages of the magnitude to cause static convergence of the beams at the corners of the cathode ray tube. The result is misconvergence at the center. However, the misconvergence at the center is corrected by a dynamic correction device that causes the beams to converge at a time when the beams are not also being subjected to the magnetic deflection fields.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a simplified cross sectional view of the electron gun region and part of the convergence and deflection coils of a color cathode ray tube.
FIG. 2 illustrates the relationship between the dynamic convergence apparatus and the electron beams in the device in FIG. 1 when operated according to the prior art.
FIGS. 3 and 4 illustrate two types of misconvergence of electron beams on a cathode ray tube screen in a tube of the type represented in FIG. 1.
FIG. 5 is a waveform of correction current applied to the dynamic correction device in FIG. 1 according to the prior art.
FIG. 6 is a waveform of a modified correction current to correct for the misconvergence shown in FIG. 4.
FIG. 7 illustrates the proper cross sectional shape of an electron beam in a tube of the type shown in FIG. 1.
FIG. 8 shows a typical distortion of the cross sectional shape of the beam in FIG. 7.
FIG. 9 shows a beam pattern similar to that in FIG. 3 but with static correction applied according to the present invention.
FIG. 10 shows a beam pattern corresponding to that in FIG. 4 but with proper static convergence according to the present invention.
FIG. 11 is a waveform of dynamic convergence correction current to effect convergence of the beams having the type of misconvergence shown in FIG. 9.
FIG. 12 is a waveform of the current applied to a dynamic convergence correction device according to the present invention to correct misconvergence of the type illustrated in FIG. 10.
FIG. 13 is a graph of luminance versus beam current for different phosphors .
DETAILED DESCRIPTION OF THE EMBODIMENTS
The cathode ray tube in FIG. 1 includes means for forming three electron beams. In the embodiment illustrated the tube is provided with three cathodes K _R , K _G and K _B as the origin of the three beams. The cathodes are supported by insulating means within a control grid G ₁ that has appropriately spaced apertures for the three beams. In front of, and spaced slightly from, the first grid is a second grid G ₂ that also has appropriately spaced apertures. Beyond the second grid G ₂ , that is, to the right of that grid as shown in FIG. 1, is the beam focusing structure that includes a three-element electron lens consisting of three generally cylindrical electrodes identified as G ₃ , G ₄ and G ₅ . Commonly electrodes G ₃ and G ₅ are directly electrically connected together and are operated at or close to the most positive voltage of the tube.
Beyond the electrode G ₅ is an electrostatic convergence structure 1 comprising an inner pair of deflection plates 2 and 3 juxtaposed, respectively, with a pair of outer deflection plates 4 and 5. The plates 2 and 3 are electrically connected together to a voltage terminal E _b and the plates 4 and 5 are electrically connected together to a terminal E _c .
External to the tube in FIG. 1 are an electromagnetic convergence device 6 and part of a deflection yoke 7. The latter is arranged to deflect the electron beams, for the most part, after they have been subjected to convergence forces by the structure 1 and the structure 6.
The cathodes K _R , K _G and K _B are preferably located in the same plane, which may be considered to be the plane of the drawing. The cathode K _G is at the center at the axis of the tube and the other two cathodes are parallel to the cathode K _G and equally spaced from it on opposite sides. The beams originally emitted from the cathodes are substantially parallel until they reach a lens identified as L _S , formed generally by electrostatic fields in the region between the second grid G ₂ and the anode, or third grid, G ₃ . This lens is commonly called an auxiliary lens. The focal length of the auxiliary lens is such that it causes the three beams to intersect in the lens region L _M approximately centrally located in the three-element lens formed by the electrodes G ₃ -G ₅ . As is now well known, this permits the three beams identified as R, G and B to be focused by nearly the same electrostatic field in the three-electrode lens so as to minimize distortion of the spots produced by the electron beams at the screen (not shown). After passing through the lens field L _M and being focused thereby (an action which is not illustrated), the beams diverge along continuations of the lines by which they entered the lens field L _M . The beam that will eventually strike green phosphor elements and is therefore identified by the reference character G, continues along the tube axis midway between the deflection plates 2 and 3. Since these plates are at the same voltage, the beam G is not substantially affected by the voltage on those plates. The beam B passes between the plates 2 and 4 and the beam R passes between the plates 3 and 5. Since these beams originate at points that are symmetrically displaced with respect to the beam G, and since the deflection plates of the structure 1 are also substantially symmetrically arranged, voltages applied to the terminals E _b and E _c deflect the beams B and R to intersect the beam G once more at the region of the screen of the cathode ray tube. In accordance with prior technology, if the screen has a 22 inch size, the voltage E _b , which is considered the anode voltage of the tube, is approximately 1300 volts higher than the voltage E _c . This voltage brings the three beams together at the center of the cathode ray screen and is referred to as the static convergence correction condition. It is illustrated in either FIG. 3 or FIG. 4 by the single dot at the center of the screen S of those two figures.
The dynamic convergence correction device 6 is located at substantially the same point on the Z-axis of the cathode ray tube as the static convergence correction device 1. As shown in FIG. 2, the dynamic convergence correction device 6 comprises two U-shaped magnetic cores 8 and 9. A coil 10 is wound on the core 8 and a similar core 11 is wound on the core 9. The coils are connected in series and are polarized so that the current of a given polarity following through them will produce magnetic fields in the cores 8 and 9 to result in north and south magnetic poles N and S as illustrated in FIG. 2. The direction of flux across the poles of the core 8 and across the poles of the core 9 is indicated by the reference character H ₁ . Flux between the upper ends of the cores 8 and 9 and between the lower ends of these cores is denoted by reference character H ₂ . The arrangement of the cores 8 and 9 is called a four-pole construction. The forces produced by magnetic fields of the cores 8 and 9 acting on electron beams B, G and R are indicated as the forces F ₁ and F ₂ . The force F ₁ is produced by the flux H ₁ and the force F ₂ is produced by the flux H ₂ . In the simplified representation in FIG. 2, these forces are illustrated as being substantially perpendicular to the respective magnetic fields that cause them, and the combined effect of these forces is to flatten the beams vertically and to spread them apart horizontally.
The beam pattern produced on the screen S of a cathode ray tube in accordance with the prior art is indicated in FIG. 3. At the center of the screen S, the three beams are caused to converge to a single dot by electrostatic fields on the deflection plates 2-5. These plates are not illustrated in FIG. 2, but would be located in a manner consistent with the cross sectional view illustrated in FIG. 1 so that the electrostatic fields acting upon the beams B and R would both be horizontally inward in FIG. 2 to cause them to intersect at the center of the screen S in FIG. 3. The type of misconvergence illustrated in FIG. 3 varies only horizontally and not vertically and, in accordance with the teachings of the prior art, has heretofore been corrected by applying a parabolic current of the type shown in FIG. 5 to the coils 10 and 11 in the dynamic convergence correction structure 6 in FIG. 2. This parabolic current has a periodicity of 1H corresponding to the horizontal deflection frequency.
FIG. 4 shows another typical misconvergence pattern, and FIG. 6 shows the prior art convergence correction current applied to the coils 10 and 11 in FIG. 2. The misconvergence illustrated in FIG. 4 has both a horizontal and a vertical component and therefore the correction current waveform in FIG. 6 includes a parabolic horizontal component 1H and a parabolic vertical component 1V. The combined currents reach a maximum when the beams are deflected to the four corners of the screen S.
FIG. 7 represents the cross section of any one of the beams R, B or G when the current flowing through the dynamic convergence correction structure 6 in FIG. 2 is zero under the conditions of the prior art. That is, the correction current applied to the coils 10 and 11 in the structure 6 is zero and the beams are not deflected from the center of the screen S. However, when the beams are deflected toward the corners under the conditions of the prior art, which requires that the current through the coils 10 and 11 be at the peak values shown in FIG. 5 to correct the type of misconvergence in FIG. 3 or at the peak values shown in FIG. 6 to correct the type of misconvergence in FIG. 4, the beams are flattened as illustrated in FIG. 8. This is due to the force F ₁ pulling the electron beams horizontally so as to spread them apart and the force F ₂ compressing the beams vertically. This distortion of the beams adversely affects the quality of the television picture, mainly by adversely affecting the focus of the beams at the outer part of the screen.
The present invention overcomes the disadvantage of the prior art by changing the convergence correction fields. In accordance with the present invention, an anode voltage E _b supplied to the inner deflection plates 2 and 3 of the static convergence device 1 and the convergence voltage E _c applied to the outer deflection plates 4 and 5 are more nearly at the same level than in the prior art. For example, the difference between the voltage E _{b c} may be lower, thus creating a different convergent lens than the prior art. This can be accomplished by making the voltage E _c only about 1100 volts lower than the anode voltage E _b for a 22 inch color cathode ray tube instead of 1300 volts in accordance with the prior art. This causes the beams to be properly converged at the outer sides of the screen S in the case of a cathode ray tube having a misconvergence only in the horizontal direction as shown in FIG. 9. The dynamic correction current applied to the coils 10 and 11 from a source 12 is of the type shown in FIG. 11, which has the same parabolic waveform shown in FIG. 5 but which reaches zero value when the electron beams are deflected to the edges of the screen. This parabolic current has a negative value that reaches a maximum value when the beams are at the center of each horizontal line, and little or no dynamic convergence force is applied by the magnetic field when the beams are at the ends of each line. and the voltage E
In the case of a tube having both horizontal and vertical components of misconvergence, the reduction in the voltage difference between the inner deflection plates 2 and 3 and the outer deflection plates 4 and 5 eliminates misconvergence at the corners of the screen S as shown in FIG. 10. The correction current applied to the coils 10 and 11 from a source 12 must be of the type illustrated in FIG. 12. This current has the same waveform as the correction current shown in FIG. 6 but reaches zero value at the corners of the screen and a maximum negative value at the center of the middle line of the raster.
The current values required for dynamic convergence correction in accordance with this invention and as illustrated in FIGS. 11 and 12 do not necessarily have the same magnitudes as the current values in FIGS. 5 and 6. When the beams are in the exact center of the screen, they are not subjected to any deflection fields, which, when present, have not only a deflecting effect but a focusing effect that is a function of the deflection current and of the configuration of the deflection yoke 7. As a result dynamic convergence current may be less than in the case of the maximum dynamic convergence current in FIGS. 5 or 6. The magnetic field produced in the structure 6 in FIG. 2 is, in effect, a magnetic lens that has unequal horizontal and vertical effects on the beams. In the case of the present invention, this lens has maximum power due to maximum current when the beams are at the center of the screen and are thus not subjected to the combined lens and prism effects of the deflection yoke 7 shown in FIG. 1. As a result the beams B, G and R are not distorted in the manner shown in FIG. 8 or at least are distorted less than under the conditions of the prior art. This produces a picture of relatively uniform high resolution, not only at the outer part of the screen, but in the central region.
FIG. 13 shows the relationship between luminance and beam current for three typical phosphors used in color cathode ray tubes. For low beam currents the luminance of all three phosphors varies substantially linearly with the beam current. At a certain beam current the green phosphor begins to saturate so that additional current does not produce a corresponding additional green luminance. In the absence of any correcting circuits, if the beam current extends to a high enough value for all three phosphors so that the green phosphor is saturated, an image of a white object would take on a magenta hue due to an excess of red and blue light with respect to the green.
When the convergence correction device 6 is used in accordance with the prior art, maximum distortion of the beam spots occurs at the outer parts of the screen S. The beam distortion concentrates the beams at the outer parts of the screen and thus produces the effect of excess beam current, even if the current remains constant. The reason is that the constant current is concentrated into a smaller area by the distortion and thus the phosphor elements are subjected to increased current density. This produces the same adverse effect on hue as if the current had simply been increased without beam distortion.
By correcting the beam convergence according to the present invention, there is relatively little distortion of the beams at any part of the screen S and thus there is less tendency to have a high density that will adversely effect the color balance.

SONY DST EHT FBT TRANSFORMER Bobbin structure for high voltage transformers EHT Output.
A coil bobbin for a fly-back transformer or the like having a bobbin proper. A plurality of partition members or flanges are formed on the bobbin proper with a slot between adjacent ones. At least first and second coil units are formed in the bobbin proper, each having several slots, formed between the flanges, and first and second high voltage coils are wound on the first and second coil units in opposite directions, respectively. A rectifying means is connected in series to the first and second coil units, and a cut-off portion or recess is provided on each of the partition members. In this case, a wire lead of the coil units passes from one slot to an adjacent slot through the cut-off portion which is formed as a delta groove, and one side of the delta groove is corresponded to the tangent direction to the winding direction.


1. A fly-back transformer comprising a coil bobbin comprising a plurality of parallel spaced discs with a first adjacent plurality of said disc formed with delta shaped slots having first edges which extend tangentially to a first winding direction and a first winding wound on said first adjacent plurality of said discs in said first winding direction, a second adjacent plurality of said discs formed with delta shaped slots having first edges which extend tangentially to a second winding direction opposite said first winding direction and a second winding wound on said second adjacent plurality of said discs in said second winding direction, a third adjacent plurality of said discs formed with delta shaped slots having first edges which extend tangentially to said first winding direction and a third winding wound on said third adjacent plurality of said discs in said first winding direction and said second plurality of adjacent discs mounted between said first and third plurality of adjacent discs. 2. A fly-back transformer according to claim 1 wherein adjacent ones of said first adjacent plurality of discs are mounted such that their delta shaped slots are orientated 180 degrees relative to each other. 3. A fly-back transformer according to claim 2 including a first winding turning partition mounted between said first and second adjacent plurality of discs and formed with grooves and notches for changing winding direction between said first and second windings and a second winding turning partition mounted between said second and third adjacent plurality of discs and formed with grooves and notches for changing the winding direction between said second and third windings. 4. A fly-back transformer according to claim 3 wherein said first and second winding turning partitions are formed with winding guiding slots for guiding the winding between the first, second and third adjacent plurality of discs. 5. A fly-back transformer according to claim 2 including a first rectifying means connected between one end of said first winding and one end of said second winding, and a second rectifying means connected between the second end of said second winding and one end of said third winding. 6. A fly-back transformer according to claim 5 wherein the second end of said first winding is grounded and a third rectifying means connected between the second end of said third winding and an output terminal.

Description:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to a bobbin structure for high voltage transformers, and is directed more particularly to a bobbin structure for high voltage transformer suitable for automatically winding coils thereon.
2. Description of the Prior Art
In the art, when a wire lead is reversely wound on a bobbin separately at every winding block, a boss is provided at every winding block and the wire lead is wound on one block, then one end of the wire lead is tied to the boss where it will be cut off. The end of the wire lead is tied to another boss, and then the wire lead is wound in the opposite direction. Therefore, the prior art winding method requires complicated procedures and the winding of the wire lead cannot be rapidly done and also the winding can not be performed automatically. Further, the goods made by the prior art method are rather unsatisfactory and have a low yield.
OBJECTS AND SUMMARY OF THE INVENTION
Accordingly an object of the invention is to provide a coil bobbin for a fly-back transformer or the like by which a wire lead can be automatically wound on winding blocks of the coil bobbin even though the winding direction is different among the different winding blocks.
Another object of the invention is to provide a coil bobbin for a fly-back transformer or the like in which a bridge member and an inverse engaging device for transferring a wire lead from one wiring block to an adjacent wiring block of the coil bobbin and wiring the wire lead in opposite wiring directions between adjacent wiring blocks, and a guide member for positively guiding the wire lead are provided.
According to an aspect of the present invention, a coil bobbin for a fly-back transformer or the like is provided which comprises a plurality of partition members forming a plurality of slots, a first coil unit having several slots on which a first high voltage coil is wound in one winding direction, a second coil unit having several slots on which a second high voltage coil is wound in the other direction, a rectifying means connected in series to the first and second coil units, and a cut-off portion provided on each of the partition members, a wire lead passing from one slot to an adjacent slot through the cut-off portions, each of the cut-off portions being formed as a delta groove, and one side of the delta groove corresponding to a tangent to the winding direction.
The other objects, features and advantages of the present invention will become apparent from the following description taken in conjunction with the accompanying drawings through which the like reference numerals and letters designate the same elements and parts, respectively.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a schematic diagram showing the construction of a fly-back transformer;
FIG. 2 is a connection diagram showing an example of the electrical connection of the fly-back transformer shown in FIG. 1;
FIG. 3 is a schematic diagram showing an example of a device for automatically winding a wire lead of the fly-back transformer on its bobbin;
FIG. 4 is a perspective view showing an example of the coil bobbin according to the present invention;
FIG. 5 is a plan view of FIG. 4;
FIGS. 6 and 7 are views used for explaining recesses or cut-off portions shown in FIGS. 4 and 5; and FIGS. 8A and 8B cross-sectional views showing an example of the inverse engaging means according to the present invention.
DESCRIPTION OF THE PREFERRED EMBODIMENT
When the high voltage winding of a fly-back transformer used in a high voltage generating circuit of a television receiver is divided into plural ones and then wound on a bobbin, the divided windings (divided coils) are connected in series through a plurality of rectifying diodes.
When the winding is divided into, for example, three portions, such as divided coils La, Lb and Lc, they are wound on a bobbin proper 1 from, for example, left to right sequentially in this order as shown in FIG. 1. In this case, if the divided coils La and Lc are selected to have the same sense of turn and the middle coil Lb is selected to have the opposite sense of turn from the coils La and Lc, the distance between the terminal end of coil La and the start of coil Lb and the distance between the terminal end of coil Lb and the start of coil Lc can be got relatively long. Therefore, diodes Da and Db can be mounted by utilizing the space above the block on which the middle coil Lb is wound as shown in FIG. 1, so that it becomes useless to provide spaces for diodes between the divided coils La and Lb and between the divided coils Lb and Lc and hence the bobbin proper 1 can be made compact.
FIG. 2 is a connection diagram showing the connection of the above fly-back transformer. In FIG. 2, reference numeral 2 designates a primary winding (Primary coil) of the fly-back transformer, reference letter L designates its high voltage winding (secondary coil), including divided coils La, Lb and Lc, 3 an output terminal, and 4 a lead wire connected to the anode terminal of a cathode ray tube (not shown), respectively.
An example of the bobbin structure according to the invention, which is suitable to automatically wind coils, which are different in sense of turn in each winding block as shown in FIG. 1, on the bobbin, will be hereinafter described with reference to the drawings.
FIG. 3 is a diagram showing an automatic winding apparatus of a wire lead on a coil bobbin. If it is assumed that the wire lead is wound in the order of winding blocks A, B and C in FIG. 1 and the wire lead is wound on the block A with the bobbin proper 1 being rotated in the counter-clockwise direction as shown in FIG. 3, the relation between the bobbin proper 1 and the wire lead becomes as shown in FIG. 3. In this figure, reference numeral 6 designates a bobbin for feeding the wire lead.
Turning to FIG. 4, an example 10 of the bobbin structure or coil bobbin according to the present invention will be described now. In this example, the winding blocks A, B and C for the divided coils La, Lb and Lc are respectively divided into plural slots or sections by plural partition members or flanges 11, and a cut-off portion or recess 12 is formed on each of the flanges 11 through which the wire lead in one section is transferred to the following winding section.
As shown in FIG. 6, each recess 12 is so formed that its one side extends in the direction substantially coincident with the tangent to the circle of the bobbin proper 1 and its direction is selected in response to the sense of turn of the winding or wire lead. In this case, the direction of recess 12 means the direction of the opening of recess 12, and the direction of recess 12 is selected opposite to the sense of turn of the winding in the present invention.
Now, recesses 12A, which are formed in the winding block A, will be now described by way of example. The positions of recesses 12A formed on an even flange 11Ae and an odd flange 11A ₀ are different, for example, about 180° as shown in FIGS. 6A and 6B. Since the bobbin proper 1 is rotated in the counter-clockwise direction in the winding block A and hence the sense of turn of the wire lead is in the clockwise direction, the recess 12A is formed on the even flange 11Ae at the position shown in FIG. 6A. That is, the direction of recess 12A is inclined with respect to the rotating direction of bobbin proper 1 as shown in FIG. 6A. In this case, one side 13a of recess 12A is coincident with the tangent to the circle of bobbin proper 1, while the other side 13b of recess 12A is selected to have an oblique angle with respect to the side 13a so that the recess 12A has a predetermined opening angle.
The opening angle of recess 12A is important but the angle between the side 13a of recess 12A and the tangent to the circle of bobbin proper 1 is also important in the invention. When the wire lead is bridged or transferred from one section to the following section through the recess 12A, the wire lead in one section advances to the following section in contact with the side 13a of recess 12A since the bobbin proper 1 is rotated. In the invention, if the side 13a of recess 12A is selected to be extended in the direction coincident with the tangent to the circle of bobbin proper 1, the wire lead can smoothly advance from one section to the next section without being bent.
In the invention, since the middle divided coil Lb is wound opposite to the divided coil La, a recess 12B provided on each of flanges 11B of the winding block B is formed to have an opening opposite to that of recess 12A formed in the winding block A as shown in FIGS. 6C and 6D.
As shown in FIG. 5, terminal attaching recesses 14 are provided between the winding blocks A and B to which diodes are attached respectively. In the illustrated example of FIG. 5, a flange 15AB is formed between the flanges 11A ₀ and 11B ₀ of winding blocks A and B, and the recesses 14 are formed between the flanges 11A ₀ and 15AB and between 15AB and 11B ₀ at predetermined positions. Then, terminal plates 16, shown in FIG. 4, are inserted into the recesses 14 and then fixed there to, respectively. The terminal plates 16 are not shown in FIG. 5. Between the winding blocks B and C and between the blocks A and B, similar terminal attaching recesses 14 are formed, and terminal plates 16 are also inserted thereinto and then fixed thereto.
As described above, since the divided coil Lb is wound opposite to the divided coils La and Lc, it is necessary that the winding direction of the wire lead be changed when the wire lead goes from the block A to block B and also from the block B to block C, respectively.
Turning to FIG. 7, an example of the winding or wire lead guide means according to the present invention will be now described. In FIG. 7, there are mainly shown a bridge member for the wire lead and an inverse member or means for the wire lead which are provided between the winding blocks A and B. At first, a bridge means 20 and its guide means 21, which form the bridge member, will be described. The bridge means 20 is provided by forming a cut-out portion or recess in the middle flange 15AB located between the winding blocks A and B. In close relation to the bridge means or recess 20, the guide means 21 is provided on a bridge section X _A at the side of block A. This guide means 21 is formed as a guide piece which connects an edge portion 20a of recess 20 at the winding direction side to the flange 11A ₀ of block A in the oblique direction along the winding direction through the section X _A .
Next, an inverse engaging means 22 will be now described with reference to FIGS. 7 and 8. If the flange 11B ₀ of FIG. 7 is viewed from the right side, the inverse engaging means 22 can be shown in FIG. 8A. In this case, the tip end of one side 13a of recess 12B ₁ is formed as a projection which is extended outwards somewhat beyond the outer diameter of flange 11B ₀ . The inverse engaging means 22 may take any configuration but it is necessary that when the rotating direction of the bobbin proper 1 is changed to the clockwise direction, the wire lead can be engaged with the recess 12B ₁ or projection of one side 13a and then suitably transferred to the next station.
Another guide means 23 is provided on a bridge section X _B at the side of winding block B in close relation to the inverse engaging means 22. The guide means 23 is formed as a guide surface which is a projected surface from the bottom surface of section X _B and extended obliquely in the winding direction. This guide means or guide surface 23 is inclinded low into the means 22 and has an edge 23a which is continuously formed between the middle flange 15AB and the flange 11B ₀ .
In this case, it is possible that the guide means 21 and guide surface 23 are formed to be the same in construction. That is, both the guide means 21 and 23 can be made of either the guide piece, which crosses the winding section or guide surface projected upwards from the bottom surface of the winding section. It is sufficient if the guide means 21 and 23 are formed to smoothly transfer the wire lead from one section to the next section under the bobbin proper 1 being rotated.
Although not shown, in connection with the middle flange 15BC between the winding blocks B and C, there are provided similar bridge means 20, guide means 21, inverse engaging means 22 and another guide means 23, respectively. In this case, since the winding direction of the wire lead is reversed, the forming directions of the means are reverse but their construction is substantially the same as that of the former means. Therefore, their detailed description will be omitted.
According to the bobbin structure of the invention with the construction set forth above, the wire lead, which is transferred from the block A to the section X _A by the rotation of bobbin proper 1, is wound on the section X _B from the section X _A after being guided by the guide piece 21 to the recess 20 provided on the middle flange 15AB, and then transferred to the recess 22 provided on the flange 11B ₀ guide surface 23, bridged once to the first section of winding block B through the recess 22 (refer to dotted lines b in FIG. 7). Then, if the rotating direction of the bobbin proper 1 is reversed, the wire lead is engaged with the bottom of recess 22 (refer to solid lines b in FIG. 7). Thus, if the above reverse rotation of bobbin proper 1 is maintained, the wire lead is wound on the block B in the direction reverse to that of block A. When the wire lead is transferred from the block B to block C, the same effect as that above is achieved. Therefore, according to the present invention, the wire lead can be automatically and continuously wound on the bobbin proper 1.
After the single wire lead is continuously wound on blocks A, B and C of bobbin proper 1 as set forth above, the wire lead is cut at the substantially center of each of its bridging portions. Then, the cut ends of the wire lead are connected through diodes Da, Db and Dc at the terminal plates 16, respectively by solder.
In the present invention, the projection piece, which has the diameter greater than that of the flange 11B, is provided in the bridge recess 12 to form the inverse engaging means 22 as described above, so that when the winding direction is changed, the wire lead engages with the inverse engaging means 22 without errors when reversing the winding direction of the wire lead.
If the diameter of the projection piece of means 22 is selected, for example, to be the same as that of the flange 11B, it will not be certain that the wire lead engages with the means 22 because it depends upon the extra length of the wire lead and hence errors in winding cannot be positively avoided.
Further, in this invention, the bridge means is provided on the flange positioned at the bridging portion of the bobbin which has a number of dividing blocks separated by flanges, and the inverse engaging means is provided and also the guide means is provided at the former winding section to cooperate with the inverse engaging means. Therefore, the wire lead can be positively fed to the bridge means, and the transfer of the wire lead to the following winding section can be carried out smoothly.
Further, in this invention since one side of the recess 12 is selected coincident with the tangent of the outer circle of the bobbin proper 1 and also with the winding direction, the wire lead can be smoothly bridged to the following section. Due to the fact that the direction of recess 12 is changed in response to the winding direction, even if there is a block on which the wire lead is wound in the opposite direction to that of the other block, the wire lead can be continuously and automatically wound through the respective blocks.
The above description is given for the case where the present invention is applied to the coil bobbin for the high voltage winding of a fly-back transformer, but it will be clear that the present invention can be applied to other coil bobbins which require divided windings thereon with the same effects.
It will be apparent that many modifications and variations could be effected by one skilled in the art without departing from the spirits or scope of the novel concepts of the present invention, so that the spirits or scope of the invention should be determined by the appended claims only.

SONY  KV-27XR TA  CHASSIS SCC-783B-A  (SX)  Television receiver which can indicate the numeral of a channel SONY On Screen Display TECHNOLOGY.

A television receiver having a CPU (central processing unit), a ROM (read only memory) in which a program and a font data are written, and a RAM (random access memory) for work area and a shift register. The font data to be indicated as a channel numeral is loaded to the shift register by an interrupt procedure and the output from the shift register is supplied to the video signal system whereby to indicate the channel numeral after the channel is changed.



1. A television receiver for receiving a video signal that includes a synchronizing signal, said receiver comprising:
a central processing unit having an interrupt function;
bus means connected to said central processing unit;
read only memory means connected to said central processing unit through said bus means and containing a control program to be executed by said central processing unit;
random access memory means connected to said central processing unit through said bus means and used as a work area of said central processing unit;
channel selecting means connected to said central processing unit through said bus means for selecting one of a plurality of channels;
control signal receiving circuit means connected to said central processing unit through said bus means for receiving a control signal and controlling said channel selecting means;
shift register means connected to said central processing unit through said bus means;
clock pulse generating means for supplying a clock pulse to said shift register means synchronized with the synchronizing signal of said video signal and generating a serial signal representing a character pattern from said shift register means; and
mixing means for mixing said video signal and said serial signal;
said control program in said read only memory means containing font data to be displayed, a main program for decoding said control signal and controlling said channel selecting means, and an interrupt program for loading the font data from said read only memory means into said shift register means.
2. A television receiver according to claim 1; further comprising an integrated circuit chip, said central processing unit, said bus means, said read only memory means, said random access memory means and said shift register means being formed on said chip. 3. A television receiver according to claim 1; wherein said synchronizing signal includes a horizontal synchronizing pulse, said central processing unit is interrupted by said horizontal synchronizing pulse, and said interrupt program is started by said horizontal synchronizing pulse. 4. A television receiver according to claim 3; wherein a horizontal trace period follows said synchronizing signal and said font data from said read only memory means is loaded into said shift register means during a first portion of the horizontal trace period and said serial signal is generated during a second portion of the horizontal trace period.

Description:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to a television receiver and more particularly is directed to a television receiver which can indicate the numeral of a channel after the channel is changed.
2. Description of the Prior Art
There is proposed a television receiver in which when a channel is changed, the numeral indicative of the channel after the channel is changed is indicated on the screen of a cathode ray tube during a predetermined period. Such previously proposed television receiver is disclosed in U.S. Pat. No. 3,748,645, U.S. Pat. No. 3,812,285 and so on. A conventional channel indicator used in such television receiver requires a special LSI (large scale integration) chip to indicate the numeral of the channel. However, such LSI chip requires a substantial investment in time and money from its designing to the completion, and when the designing thereof is changed midway, it is quite difficult to cope with such change.
Moreover, it is difficult to give an individuality to the character pattern of the numeral indicating the channel. Furthermore, the number of ICs (integrated circuits) is increased and hence the manufacturing cost is inevitably raised.
OBJECTS AND SUMMARY OF THE INVENTION
Accordingly, it is an object of the present invention to provide an improved television receiver which is free from the problem inherent to the prior art.
It is another object of the present invention to provide a television receiver which can indicate the numeral of a channel after the channel is changed by employing a microcomputer.
It is still another object of the present invention to provide a television receiver in which an individuality can easily be given to the character pattern of the numeral of a channel to be indicated.
It is further object of the present invention to provide a television receiver which can reduce the number of integrated circuits.
According to one aspect of the present invention, there is provided a television receiver comprising:
(a) a central processing unit having an interrupt function;
(b) a bus means connected to said central processing unit;
(c) a read only memory means connected to said central processing unit through said bus means and containing a control program to be executed by said central processing unit;
(d) a random access memory means connected to said central processing unit through said bus means and used as a work area of said central processing unit;
(e) a channel selecting means connected to said central processing unit through said bus means for selecting one of a plurality of channels and producing a video signal; and
(f) a control signal receiving circuit means connected to said central processing unit through said bus means for receiving a control signal and controlling said channel selecting means;
characterized in that said television receiver comprises:
(g) a shift register means connected to said central processing unit through said bus means;
(h) a clock pulse generating means for supplying a clock pulse to said shift register means synchronized with the synchronizing signal of said video signal and generating a serial signal representing a character pattern from said shift register;
(i) a mixing means for mixing said video signal and said serial signal; and
(j) an interrupt means for interrupting an operation of said central processing unit synchronized with a synchronizing pulse of the video signal, said control program in said read only memory means containing a font data to be displayed, a main program for decoding said control signal and controlling said channel selecting means, and an interrupt program for loading the font data from said read only memory means to said shift register means.
The other objects, features and advantages of the present invention will become apparent from the following description taken in conjunction with the accompanying drawings through which the like references designate the same elements and parts.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a schematic block diagram of an embodiment of a television receiver according to the present invention;
FIG. 2 is a table showing a 16-bit font data used in the present invention;
FIG. 3 is a diagram showing a screen of the television receiver of the present invention on which a numeral of channel is indicated and waveforms of pulses used in explanation thereof;
FIG. 4 is a diagram showing the format of a remote control signal used in the present invention; and
FIGS. 5 to 8 are respectively flow charts used to explain the operation of the present invention.
DESCRIPTION OF THE PREFERRED EMBODIMENT
Now, an embodiment of a television receiver according to the present invention will hereinafter be described with reference to the attached drawings.
In FIG. 1 showing an example of the present invention, reference numeral 10 generally designates a video signal system, 11 a tuner, 12 a video intermediate frequency (VIF) amplifier, 13 a video detecting circuit, 14 a video amplifier and 15 a cathode ray tube, respectively. In this case, the tuner 11 is formed as an electronic tuning system which can receive the video signal of a desired channel by changing a value of a tuning voltage Ec supplied thereto.
Reference numeral 20 generally designates a microcomputer, 21 a 4-bit parallel CPU (central processing unit), 22 a ROM (read only memory) in which a program and a font data for indicating a numeral of a channel are written or stored, 23 a RAM (random access memory) for a work area and 31 to 36 input/output ports. These circuits 22 to 36 are connected through a bus 24 to the CPU 21.
Reference numeral 37 designates a 16-bit serial/parallel input and serial output shift register. This shift register 37 is used to generate a signal Sn which indicates the numeral of the channel. To the shift register 37 loaded line by line in parallel is a 16-bit font data indicating the numeral of a channel as, for example, shown in FIG. 2 from the port 32. The font data loaded to the shift register 37 is delievered therefrom in series from MSB (most significant bit) as the signal Sn. At that time, the serial input terminal of the shift register 37 is made at "0" level.
The signal Sn derived from the shift register 37 is supplied to the video amplifier 14 in which the signal Sn is composed on or mixed with the video signal.
The microcomputer 20 together with this shift register 37 is formed as one chip IC (integrated circuit).
Reference numeral 41 designates a D/A (digital-to-analog) converter. The output from the port 31 is supplied to this D/A converter 41 from which the tuning voltage Ec is derived. This tuning voltage Ec is supplied to the tuner 11.
Reference numeral 42 designates a receiving element which receives a remote control signal and 43 its receiving circuit connected thereto. When the remote control signal is, for example, an infrared remote control signal, the receiving element 42 is formed as an infrared ray receiving element and the receiving circuit 43 generates a remote control signal Sr. This remote control signal Sr is the signal which corresponds to an output from a remote control signal transmitter (not shown) and has a format as, for example, shown in FIG. 4. Namely, in this remote control signal, a guide pulse having a pulse width of 2400 μsec exists in the beginning and code pulses of 16 bits from b ₀ to b ₁₅ follow the guide pulse with an interval of 600 μsec. In this case the code pulses b ₀ to b ₁₅ indicate "0" or "1" in respose to the content of the remote control. When "0", the pulse width is selected as 600 μsec, while when "1", the pulse width is selected as 1200 μsec. This remote control signal Sr is supplied to the port 33.
Reference numeral 44 designates a non-volatile memory which is connected to the port 34 and in which a digital value of the tuning voltage Ec at each channel is stored. Reference numeral 45 designates an input key which is used to change the channel, the sound volume and so on, in which the dynamic scan is carried out by the output from the port 35, and the switching output from which is inputted to the port 36 to detect which key is operated.
Reference numeral 51 designates a synchronizing (sync) separating circuit to which the video signal from the video detector circuit 13 is supplied and from which a vertical synchronizing pulse Pv and a horizontal synchronizing pulse Ph are derived respectively. These pulses Pv and Ph are supplied to the CPU 21 as interrputing signals H-INT and V-INT. The pulse Ph is supplied to a monostable multivibrator 52 which generates a pulse P ₅₂ which becomes "1" from a falling down or trailing edge time point t ₁ of the pulse Ph to a start time point t ₂ of the display period of the numeral of the channel as shown in FIG. 3 (in which reference numeral 151 designates the screen of the cathode ray tube). This pulse P ₅₂ is supplied to a gated oscillating circuit 53 as its oscillating control signal so that from the gated oscillating circuit 53 is derived an oscillating pulse P ₅₃ during the period from t ₂ to t ₄ in which the pulse P ₅₂ is "0" as shown in FIG. 3. This pulse P ₅₃ is supplied to the shift register 37 as the clock. At that time, the frequency of the pulse P ₅₃ is selected as a value corresponding to a dot pitch in the lateral direction of the numeral of the channel to be indicated.
Accordingly, since the font data on, for example, the first line in FIG. 2 is loaded to the shift register 37 during the first half period from t ₁ to t ₂ of the 45th horizontal trace period, this font data is extracted from the shift register 37 as the serial signal Sn in response to the pulse P ₅₃ during the second half period from t ₂ to t ₃ of the above horizontal trace period and then supplied to the video amplifier 14, the numeral of the channel on the first line is indicated on the screen 151 in the interval corresponding to the period from t ₂ to t ₃ of the 45th line. Although during the period from t ₃ to t ₄ the pulse P ₅₃ is supplied to the shift register 37, the serial input terminal of the shift register 37 is at "0" level and this "0" level is derived from the shift register 37 during the period from t ₃ to t ₄ so that no numeral of the channel is indicated on the screen 151 in the interval corresponding to the period from t ₃ to t ₄ .
When such operation is performed for the 45th to 51st horizontal lines by employing the font data on the 1st to 7th lines shown in FIG. 2, the channel numeral corresponding to the font data in FIG. 2 is displayed as shown in FIG. 3. If the data of all "0" is loaded to the shift register 37 as the font data, the channel numeral is not indicated.
FIGS. 5 to 8 respectively show flow charts of the programs written in the ROM 22 and FIG. 5 shows the main routine thereof.
This main routine shown in FIG. 5 starts from a step 501 and in a step 502 the initializing is carried out. Thus, a flag FLG, a buffer BUFF and counters CHCNT, HCNT and WCNT are set in, for example, the RAM 23 and these are all reset (cleared) to "0".
A step 503 is such a step in which the existence or not of the remote control signal Sr is judged by the existence or not of the guide pulse, namely, by detecting whether the "1" level of the signal Sr lasts 2400 μsec or not. A step 504 is such a step which judges whether or not there is the input to the key 45, and a step 531 is such a step which judges whether the counter CHCNT is "0" or not. Consequently, when powered, CHCNT=0 is established in the step 502 so that the loop of step 503➝step 504➝step 531➝step 503 is repeated to thereby poll the input of the remote control signal Sr and the input from the key 45. In this case, the counter CHCNT serves as a flag indicative of the existence or not of the request for changing the channel and a timer for setting the displaying period of the channel numeral.
When the remote control signal Sr exists, the bits b ₀ to b ₁₅ of the signal Sr are latched in a step 800 and the step is moved to a step 511. Also when an input exists in the step 504, the step 504 moves to the step 511, too. In the step 511, it is judged whether the remote control input in the step 800 and the key input in the step 504 are the commands for changing the channel or not.
When the above inputs are the command for changing the channel, the counter CHCNT is set to "1" in a next step 512. Subsequently, in a step 513, on the basis of the channel data indicated by the remote control signal Sr inputted at the step 800 and the key input in the step 504, a digital tuning voltage data E _D for tuning to the channel is read out from the non-volatile memory 44 (see FIG. 1). This digital tuning voltage data E _D is outputted to the port 31 in a step 514. Thus, by the analog tuning voltage Ec from the D/A converter 41, the television receiver is set in the receiving state of the channel inputted in the step 800 or 504, thereafter.
In a step 515, from the ROM 22, a font data (data as, for example, shown in FIG. 2) displayed as a numeral of a new channel after the channel is changed is loaded to the buffer BUFF. Although the detail will be described later, the font data in the buffer BUFF is sequentially loaded line by line to the shift register 37 during the 45th to 51st horizontal trace period t ₁ to t ₂ of each field in accordance with a subroutine 700 shown in FIG. 7. As a result, the channel numeral after the channel is changed is indicated on the screen 151.
When the channel numeral is indicated on the screen 151, the procedure step is returned to the step 503. At that time, since CHCNT=1 is established in the step 512, the procedure step is moved in the order of the step 503➝the step 504➝the step 531➝a step 532. In this step 532, the counter CHCNT is incremented by "1" and in a next step 533, whether the count CHCNT reaches a predetermined value MAX or not is checked where the value MAX is the value corresponding to the period during which the channel numeral is displayed upon changing the channel.
And, if CHCNT
When CHCNT=MAX is esbalished, the buffer BUFF is cleared to "0" in a step 541. Therefore, since "0" is loaded through the buffer BUFF to the shift register 37 as the font data, Sn="0" is established thereafter so that the channel numeral is not indicated any more.
In a next step 542, the counter CHCNT is reset to "0" and the procedure step is returned to the step 503.
As described above, when the channel change data is inputted, the channel is changed and the channel numeral after the channel is changed is indicated during a constant period.
When the inputs in the steps 800 and 504 are not the commands for changing the channel but the commands for changing, for example, the sound volume, in a step 521 the counter CHCNT is reset to "0" and then in a step 522, the operation based on the commands inputted in the steps 800 and 504 is carried out. The circuitry for executing the procedure except for changing the channel can be made the same as in the prior art and hence it is omitted to show the same in FIG. 1.
On the other hand, FIGS. 6 and 7 respectively show subroutines in which the font data in the buffer BUFF is loaded to the shift register 37. The subroutine 600 shown in FIG. 6 is the interrupt subroutine which is executed when the interrupt procedure is executed by the vertical synchronizing pulse Pv. When the vertical synchronizing pulse Pv is supplied to the CPU 21, this subroutine 600 starts from a step 601 and in a step 602, the counter HCNT is reset to "0". In a step 603, the subroutine 600 is ended and returned to the original main routine.
Accordingly, by this subroutine 600, the counter HCNT is reset to "0" at every start point of each field.
The subroutine 700 shows in FIG. 7 is the interrupt subroutine which is executed when the interrupt procedure is executed by the horizontal synchronizing pulse Ph. When the horizontal synchronizing pulse Ph is supplied to the CPU 21, the subroutine 700 starts from a step 701 and in a step 702, a flag FLG indicative of whether the subroutine 700 is executed or not is set to "1". Then, in a step 703, the counter HCNT is incremented by "1". In this case, since the counter HCNT is reset to "0" by the subroutine 600 at every start point of each field and the subroutine 700 is executed at each horizontal syncronizing pulse Ph, the counter HCNT indicates the line number of the horizontal line at each field period.
In a next step 704, the magnitude of the counter HCNT is checked. When 45≤HCNT≤51, in a step 711, the font data in the buffer BUFF (the data as, for example, shown in FIG. 2) is loaded line by line to the shift register 37 from the buffer BUFF each time when the counter HCNT is incremented by "1" each (at every horizontal lines). On the other hand, when 45≤HCNT≤51 is not established, in a step 721, all "0" is loaded to the shift register 37. Then, the subroutine 700 is ended at a next step 712 and returned to the original main routine.
If necessary, the subroutine 700 is provided with a timer routine by which the duration of time necessary for completing the subroutine 700 is set as 40 μsec (the period shorter than the period from t ₁ to t ₂ ).
Consequently, during the period from t ₁ to t ₂ in the 45th to 51st horizontal trace periods, by the subroutine 700 the data in the buffer BUFF is loaded to the shift register 37. Then, if the data loaded to the shift register 37 is the font data, the channel numeral is indicated during the period from t ₂ to t ₃ . While during the period from t ₁ to t ₂ in other horizontal trace period, the data indicative of all "0" is loaded to the shift register 37 from the buffer BUFF so that the channel numeral during the period t ₂ to t ₃ is not displayed.
Upon changing the channel, during the predetermined period, the font data regarding the channel numeral after the channel is changed is loaded to the buffer BUFF in the step 515. After that, since the data indicative of all "0" is loaded to the buffer BUFF in the step 541, in accordance with the subroutine 700, during the predetermined period from the change of the channle, the channel numeral after the channel is changed is indicated on the screen 151 as shown in FIG. 3. After the predetermined period elapses, the display is not carried out any more.
FIG. 8 shows a subroutine 800 which is used to read the remote control signal Sr. This subroutine 800 starts from a step 801. In a next step 802, a pointer i is reset to "0" and in a succeeding step 811, a delay corresponding to the "0" level period of 600 μsec between the trailing edge of the guide pulse and the rising edge of the bit b ₀ (see FIG. 4) is carried out. Further, in a next step 821, the counter WCNT is reset to "0". In this case, the pointer i indicates a particular bit of the bits b ₀ to b ₁₅ of the remote control signal Sr and i=0 to 15. Also, the counter WCNT is used to check the respective pulse widths of the bits b ₀ to b ₁₅ .
After the delay of 70 μsec is performed in a succeeding step 822, whether the flag FLG is "0" or "1" is checked in a next step 823. When FLG=0, namely, the interrupt procedure is not executed, the counter WCNT is incremented by "1" in a following step 824. When FLG=1, namely, the interrupt procedure is executed, the counter WCNT is incremented by "2" in a step 825 and the processing time due to the interrupt procedure is corrected. Thereafter, the flag FLG is reset to "0" in a next step 826. Then, in a step 827, it is checked whether the level of ith bit of the remote control signal Sr reaches the "0" level or not, namely, whether ith bit is ended or not. When ith bit is not ended, the step 827 returns to the step 822, while when ended, the step 827 advances to a step 831.
Accordingly, during the period in which the level of ith bit of the signal Sr is at the "1" level, the loop from the steps 822 to 827 is repeated. Upon repeating the loop from the steps 822 to 827, if the interrupt subroutine 700 is not executed at all, the FLG=0. Therefore, in the steps 822 and 824, the counter WCNT is incremented by "1" each at every 40 μsec. Thus, at the time when the above loop is ended, if ith bit is "0" (namely, the pulse width is 600 μsec), WCNT=15, while if ith bit is "1" (namely, the pulse width is 1200 μsec), WCNT=30 (the processing time necessary for other steps is neglected for simplicity).
Upon repeating this loop from the steps 822 to 827, if the interrupt subroutine 700 is executed, 40 μsec is consumed to execute such subroutine. This is the same as that necessary for executing the step 822 once. Also, at that time, since FLG=1 (step 702), the counter WCNT is incremented by "2" in the step 825. As a result, at the time when this loop is ended, if ith bit is "0", WCNT=15, while if ith bit is "1", WCNT=30.
After the above loop is ended, the counter WCNT is checked in the step 831. If WCNT≤15, the level "0" of ith bit is set in the RAM 23 in a step 832, while if WCNT>15, the level "1" of ith bit is set in the RAM 23 in a step 833. In a next step 834, whether the above procedure is executed for all the bits of the remote control signal Sr or not is checked by the pointer i. When the above procedure is not yet executed for all the bits, the pointer i is incremented by "1" in a step 835 and then the step 835 returns to the step 811. On the contrary, when the above procedure is executed for all the bits, the step 834 advances to a step 841.
In the step 841, the remote control signal Sr is judged on the basis of the data in the steps 832 and 833. And, in a step 842, this subroutine 800 is ended and returned to the original main routine.
As set forth above, according to the present invention, it is possible to perform the change of the channel and to indicate the channel numeral at that time. In this case, particularly in accordance with the present invention, the change of the channel and the indication of the channel numeral after the channel is changed are carried out by the use of the ordinary microcomputer 20 so that the time and cost necessary from designing to completing can be reduced extremely. Moreover, when the designing is changed in the midway thereof, the designing can be changed with ease.
Further, the individuality can be given to the character pattern of the numeral of the channel to be indicated with ease. Also, since the number of the ICs can be reduced, this is advantageous for reducing the manufacturing cost and for increasing reliablity.
In addition, in the above description, it is possible to provide the steps 531 to 542 in the subroutine 600.
The above description is given on a single preferred embodiment of the invention, but it will be apparent that many modifications and variations could be effected by one skilled in the art without departing from the spirits or scope of the novel concepts of the invention, so that the scope of the invention should be determined by the appended claims only.

SONY  KV-27XR TA  CHASSIS SCC-783B-A  (SX)  SONY Automatic pre-programming system for TV receiver/ Automatically presetting channel Program selecting system :A channel selecting system for use in a receiver having a voltage controlled tuning element which has an automatic channel presetting function which utilizes a pulse generator and a binary counter connected to the generator to count the pulses and to generate a binary coded output in accordance with the sum of the pulses. A digital-to-analog converter changes the binary coded output into a linearly increasing tuning sweep voltage which in turn conditions the voltage controlled tuning element to scan the frequency range of the tuner as the tuning voltage increases. As the frequencies are scanned, a detector, connected to the tuning element, senses the presence of a broadcast channel. When a channel is detected, the scan is interrupted and a binary memory is utilized to store the binary coded output which corresponds to the frequency of the detected broadcast channel. A control gate signal generator driven by the detector controls the pulse generator and memory such that the scan is continued until the entire frequency range has been scanned. Channel selection is accomplished by switch means actuatable to address the memory to read out a selected binary code output corresponding to the channel desired which causes the converter to generate a voltage to condition the tuning element to tune to the desired frequency. The voltage control tuning element may comprise several different elements, one for each of a plurality of different frequency ranges. Means are provided for selecting an appropriate tuner such that channels from any of the frequency ranges may be selected. "

An automatic tuning scheme for use in TV receivers includes a start/stop circuit which creates a search start signal and a search stop signal upon the receipt of a search start instruction and a detected incoming signal, respectively, a tuning voltage generator which generates a gradually varying tuning voltage under control of the search start signal and search stop signal, and a memory circuit for storing the tuning voltage from the generator when desired. The tuning voltage stored in the memory circuit is supplied to a tuner including a well known voltage-sensitive capacitance diode.

1. An automatic tuning scheme for use in TV receivers including an AFT detector comprising:
start/stop circuit means for creating a search start signal and a search stop signal upon the receipt of a search start instruction and the presence of a detected incoming signal, respectively, the presence of a detected incoming signal being determined at least in part in response to an output of said AFT detector;
tuning voltage generator means for generating a gradually varying tuning voltage under control of the search start signal and search stop signal;
memory circuit means for storing the tuning voltage from said tuning voltage generator means;
signal decision circuit means for determining whether the detected incoming signal is a true television signal including a television synchronizing signal by detecting the presence of the television synchronizing signal and the search stop signal, said signal decision circuit means providing a memory store instruction for the memory circuit means in the presence of the true television signal and providing a search re-start instruction for the start/stop circuit means in the absence of the true television signal, the tuning voltage stored in the memory circuit means being supplied to a tuner including a voltage-sensitive capacitance diode.
2. The automatic tuning scheme according to claim 1 further comprising a memory skip circuit for inhibiting the supply of the memory store instruction to the memory circuit and skipping an undesired broadcasting station. 3. An automatic tuning scheme for use in TV receivers including an AFT detector comprising:
start/stop circuit means for creating a search start signal and a search stop signal upon the receipt of a search start instruction and a detected incoming signal, respectively;
tuning voltage generator means for generating a gradually varying tuning voltage under control of the search start signal and search stop signal;
memory circuit means for storing the tuning voltage from the tuning voltage generator means
means for detecting the presence of synchronizing signals within the detected incoming signal;
noise skip circuit means which determines whether the detected synchronizing signal is a true synchronizing signal or noise and provides a search re-start instruction for the start/stop circuit means in the presence of noise; and
signal decision circuit means for determining whether there is a true television signal by counting the number of the true synchronizing signals derived from the noise skip circuit means and counting a predetermined number of the true synchronizing signals in a predetermined period of time, and then providing a memory store instruction for the memory circuit means in the presence of the true television signal and a search re-start instruction to the start/stop circuit means in the absence thereof, the tuning voltage stored in the memory circuit means being supplied to a tuner.
4. In an automatic tuning scheme for use in TV receivers including an AFT detector, which produces search start and stop signals upon receipt of a search start instruction and a detected incoming signal, a combination comprising:
means for detecting the presence of synchronizing signals within the detected incoming signal;
noise skip circuit means for determining whether the synchronizing signal is a true synchronizing signal or noise and provides a search restart instruction to said tuning scheme in the presence of noise; and
means for adjusting a skip level in the noise skip circuit means in accordance with the intensity of the detected incoming signal.
5. An automatic tuning scheme for use in TV receivers including an AFT detector comprising:
start/stop circuit means which creates a search start signal and a search stop signal upon the receipt of a search start instruction and a detected incoming signal, respectively;
tuning voltage generator means for generating a gradually varying tuning voltage under control of the search start signal and search stop signal;
memory circuit means for storing the tuning voltage from the generator, the tuning voltage stored in the memory circuit means being supplied to a tuner;
speed changer means for reducing the rate of variation in the tuning voltage derived from the tuning voltage generator means to enable a low speed searching operation slower than that of the normal searching operations when detecting an AFT detector output;
means for detecting the presence of synchronizing signals within the detected incoming signal; and
means for determining whether the synchronizing signal is a true synchronizing signal or noise and providing a search re-start instruction to said tuning scheme in the presence of noise.
6. An automatic tuning scheme for use in TV receivers including an AFT detector comprising:
start/stop circuit means for creating a search start signal and a search stop signal upon the receipt of a search start instruction and a detected incoming signal, respectively;
tuning voltage generator means for generating a gradually varying tuning voltage under control of the search start signal and search stop signal;
memory circuit means for storing the tuning voltage from the tuning voltage generator means, the tuning voltage stored in the memory circuit means being supplied to a tuner; and
speed changer means for reducing the rate of variation in the tuning voltage derived from the tuning voltage generator means to enable a low speed searching operation slower than that of the normal searching operation when detecting an AFT detector output, the direction of variation of the tuning voltage being reversed in accordance with the polarity of the AFT detector output.
7. An automatic tuning scheme for use in TV receivers including an AFT detector comprising:
start/stop circuit means for creating a search start signal and a search stop signal upon the receipt of a search start instruction and a detected incoming signal, respectively;
tuning voltage generator means for generating a gradually varying tuning voltage under control of the search start signal and search stop signal;
memory circuit means for storing the tuning voltage from the tuning voltage generator means, the tuning voltage stored in the memory circuit means being supplied to a tuner;
out-of-tuning detector means for supplying a search re-start signal to the start/stop circuit means when detecting the out-of-tuning condition;
means for detecting the presence of synchronizing signals within the detected incoming signal; and
means for determining whether the synchronizing signal is a true synchronizing signal or noise and providing a search re-start instruction to said tuning scheme in response thereto.
8. The automatic tuning scheme according to claim 7 wherein the out-of-tuning condition is sensed by comparing the AFT detector output to a given reference voltage. 9. An automatic tuning scheme for use in TV receivers including an AFT detector comprising:
start/stop circuit means for creating a search start signal and a search stop signal upon the receipt of a search start instruction and a detected incoming signal, respectively;
tuning voltage generator means for generating a gradually varying tuning voltage under control of the search start signal and search stop signal;
means for detecting the presence of synchronizing signals within the detected incoming signal; and
means for determining whether the detected synchronizing signal is a true synchronizing signal or noise and providing a search re-start instructions to said tuning scheme in the presence of noise.
10. The automatic tuning scheme according to claim 9 further comprising alarm means enabled by the tuning instruction for notifying the operator of the automatic tuning operation. 11. The automatic tuning scheme according to claim 10 wherein said alarm means release alarm signals in the form of sound. 12. The automatic tuning scheme according to claims 3, 4, 5, 6, 7, or 9 wherein the reception of a true television signal is determined by the use of said true synchronizing signal and an AFT output.

Description:

BACKGROUND OF THE INVENTION
The present invention relates to an automatic pre-programming tuning circuit which performs tuning operation automatically.
It is customary to perform the tuning operations in TV receivers while a viewer manually rotates a tuning knob. However, the tuning operation is bothersome particularly in case of the continuously varying tuning operation such as in UHF reception. Though tuning operation is considerably simpler in case of TV receivers of the recently developed touch control type or remote control type, it is difficult for a non-skilled person the to preset tuning operation, namely, to adjust the tuning frequencies for respective broadcasting stations before starting to watch a TV receiver.
SUMMARY OF THE INVENTION
Accordingly, it is an object of the present invention to provide an automatic tuning scheme which enables automatic preselectable tuning operation by sequentially memorizing tuning voltages of respective automatically selected broadcasting channels.
In its broadest aspect, an automatic tuning device of the present invention comprises a tuning voltage generator which generates a tuning voltage gradually variable during tuning operation, a memory circuit which receives the tuning voltage derived from the generator upon receipt of normal reception signals and memorizes a plurality of discrete tuning voltages each associated with a respective one of normal reception signal corresponding to a serviceable broadcasting station and means for picking up selectively one of the discrete tuning voltages from the memory circuit and supplying it to a tuner.
BRIEF DESCRIPTION OF THE DRAWINGS
Other objects and attendant advantages of the present invention will be easily appreciated as the same becomes better understood by reference to the following detailed description when considered in conjunction with the accompanying drawings in which like reference numerals designate like part throughout the figures thereof, and wherein:
FIG. 1 is a schematic diagram of the automatic tuning apparatus embodying the present invention;
FIG. 2 is a more detailed circuit diagram of the automatic tuning apparatus shown in FIG. 1;
FIG. 3 is a schematic diagram of another embodiment of the present invention;
FIGS. 4 and 5 are a circuit diagram and a waveform diagram showing a noise skip circuit included in FIG. 3 embodiment;
FIG. 6 is an improvement in the noise skip circuit shown in FIGS. 4 and 5;
FIGS. 7 and 8 are embodiments effective to modify the searching speed in the automatic tuning apparatus;
FIGS. 9 through 11 are refresh means effective in the automatic tuning apparatus of the present invention;
FIG. 12 shows another embodiment including a memory skip circuit effective in the automatic tuning apparatus;
FIGS. 13 and 14 show alarm means effective in the automatic tuning apparatus.
DETAILED DESCRIPTION OF THE INVENTION
A basic circuit of a TV receiver having an automatic tuning scheme implemented with the present invention is shown in FIG. 1, which includes an antenna 1, a tuner 2, an intermediate frequency (IF) circuit 3, an automatic fine tuning (AFT) circuit 4, a video circuit 5, a synchronizing separator 6, a deflection circuit 7, a picture tube 8. According to the present invention, a start/stop circuit 9, a tuning voltage generator 10, a memory circuit 11 and a signal decision circuit 12 are further provided to form the automatic tuning scheme of the present invention.
It will be noted that the tuner 2 can be implemented with a well known electronic tuning circuit which includes a voltage-sensitive capacitance diode as disclosed in U.S. Pat. No. 3,233,179 entitled "AUTOMATIC FINE TUNNING CIRCUIT USING CAPACITANCE DIODES" issued on Feb. 1, 1966.
If the start/stop circuit 9 is given a search start command or au automatic tuning instruction prior to effecting of the preset tuning operation, then the start/stop circuit 9 will develop a search start pulse which is turn is supplied to the tuning voltage generator 10. Under the circumstance the tuning voltage generator 10 develops a sweep voltage or staircase voltage which is gradually rising or dropping during the automatic tuning operation. The sweep or staircase voltage is supplied as the tuning voltage to the tuning capacitance diode in the tuner 2 by way of the memory circuit 11. This implies that the reception frequency in the tuner 2 is gradually varied.
In this way, when the television signal of a specific broadcasting channel is received, the television video signal is derived from the IF circuit 3 and the synchronizing signal from the synchronizing separator 6. These signals are applied to the start/stop circuit 9. Meantime, the AFT detector output is derived from the AFT circuit 4 and supplied to the start/stop circuit 9.
More particularly, when the television signal is accurately received, the AFT detector output voltage will change in polarity so that the start/stop circuit 9 is permitted to develop a search stop pulse and the vertical synchronizing signal. In the given example the vertical synchronizing signal may serve as the search stop pulse. The search stop pulse is supplied to the tuning voltage generator 10, barring the generator 10 from developing the sweep or staircase voltage. The voltage at this moment remains unchanged since then and keeps being supplied as the tuning voltage to the tuner 2 via the memory circuit.
The vertical synchronizing signal derived from the start/stop circuit 9 is supplied to the signal decision circuit 12 to determine as to whether the signal being received is a normal or true television signal. If the affirmative answer is given, then the signal decision circuit 12 will issue a memory instruction which in turn is supplied to the memory circuit 11 so that the instantaneous tuning voltage derived from the generator 10 is stored within the memory circuit 11.
Contrarily, if a false synchronizing signal is derived from the start/stop circuit 9, then the signal decision circuit 12 reacts to it so that the circuit 12 issues a search re-start pulse. This is supplied to the start/stop circuit 9 to repeat the same procedure as when executing the first search start pulse. The procedure is repeated in this manner until the start/stop circuit 9 recognizes a true television vertical synchronizing signal or accurate reception is available by the tuner 2.
In other words, the memory instruction is not issued from the signal decision circuit 12 until the optimum reception state is guaranteed. Upon issuance of the memory instruction the instantaneous tuning voltage is stored in the memory circuit 11 and subsequently supplied to the tuner 2.
Once the preset tuning operation (i,e, the presetting of the optimum reception frequency) has been completed for the specific broadcasting channel, the tuning voltage stored in the memory circuit 11 will be automatically supplied to the tuner in response to release of a tuning instruction from an operational panel of the known touch control type or remote control type. The searching procedure is not required at this time.
It is obvious that the memory circuit 11 shown in FIG. 1 includes a predetermined number of memory elements the number of which corresponds to the number of serviceable broadcasting stations. The same searching or presetting procedure is repeated when it is desired to search and memorize a predetermined number of discrete tuning voltages prior to use of a TV receiver.
As noted earlier, when the search start instruction is given and the search start signal is released from the start/stop circuit 9, the tuning voltage generator 10 starts generating the sweep voltage (or the staircase voltage), which is supplied to the tuner 2 via the memory circuit 11 while showing a gradual variation. Alternatively, the gradually varying voltage may be supplied to the tuner 2 directly. If the search stop signal is derived from the start/stop circuit 9 upon receipt of the television signal, the sweep voltage generating function of the tuning voltage generator will come to a halt. The instantaneous tuning voltage supplied to the tuner 2 is held unchanged for a while.
At this time the signal decision circuit 12 decides whether the received signal is true or false. After confirming the presence of the true television signal, the memory instruction is issued for the memory circuit 11 so that the tuning voltage available from the tuning voltage generator 10 is held within the memory circuit 10 to complete the presetting of the optimum reception frequency for the specific television station.
On the contrary, when the signal decision circuit 12 does not sense the presence of the true television signal, the search re-start signal is issued for the start/stop circuit 9 to start the above mentioned operation again. Each time the memorizing operation or the tuning frequency presetting operation is completed in the memory circuit 11 for a specific one of broadcasting stations, the search start instruction is issued again for the start/stop circuit 9. Eventually, a plurality of discrete tuning voltages are stored in sequence in the memory circuit 9, completing the over-all loading operation of the discrete tuning voltages.
FIG. 2 shows a detailed way of implementation of the present invention briefly described with respect to FIG. 1. When a search switch SW₁ is turned on, a latch FF₁ is placed to the set state with the Q output at a high level "H" and the Q output at a low level "L". A gate G₃ is enabled such that clock pulses from a clock pulse generator 13 are sequentially supplied to a counter 14 to increment it at a high speed. The output of the counter 14 is supplied to a digital-to-analog converter 15 which converts the output of the counter 14 into a DC voltage correspondingly. This DC voltage is supplied as the tuning voltage to the tuner 2. Therefore, the gradually rising sweep voltage is transferred from the digital-to-analog converter 15 to the tuner 2 so that the reception frequency in the tuner 2 is gradually varied in the ascending order.
When the television signal of a specific broadcasting station is received, the television video signal is derived from the IF circuit 3 and the horizontal and vertical synchronizing signals are derived from the synchronizing separator 6. In the case where the detector output voltage from the AFT circuit 4 is positive, a gate G₂ is enabled to place the latch FF₁ into the reset state. At the moment the Q and Q outputs of the latch FF₁ are respectively inverted into "L" and "H" levels. A gate G₃ is disabled to stop supply of the clock pulses to the counter 14 so that the digital-to-analog converter 15 supplies the tuner 2 with the output voltage of a fixed value. In other words, the searching operation comes to a halt.
When the true television signal is being received, the horizontal synchronizing pulse derived from the synchronizing separator 6 is in phase with the flyback pulse derived from the deflection circuit 7. A transistor Tr₁ is turned on in reponse to the horizontal synchronizing pulse with an increase in the emitter potential thereof. Gates G₄ and G₅ are enabled so that the vertical synchronizing pulse is supplied as the memory instruction to the memory circuit 11 via these gates G₄ and G₅. At this moment the output of the counter 14 is loaded into the first address of the memory circuit 11 in a digital fashion.
However, if the signal being received is not the true television signal, then the horizontal synchronizing pulse will neither be synchronous with the flyback pulse nor will the transistor Tr₁ be turned on. Even though the vertical synchronizing pulse from the synchronizing separator 6 or the false synchronizing pulse forces the latch FF₁ into the reset state, the gate G₅ is never enabled but the gate G₆ is enabled. The pulse transferred via the gate G₆ is supplied as the search re-start pulse to the latch FF₁ which then resorts to the reset state again to restart the searching procedure.
After the searching/memory operation has been completed for a specific one of broadcasting stations, the memory circuit 11 releases the search start pulse again, which is then supplied to the latch FF₁ via the gate G₁ to set the latch FF₁.
The same operation is thus repeated. A different tuning voltage of the next suceeding station is digitally stored at the second address of the memory circuit 11. In this way, a predetermined number of discrete tuning voltages are digitally stored in sequence until the end of the presetting operation.
Once the presetting operation has been accomplished, all that is necessary for the operator to do is to select a desired one of channel selection switches 16₁ through 16_n. Then, digital information indicative of the tuning voltage previously stored at its associated address of the memory circuit 11 is called forth in accordance with its associated selection codes within an address specifying circuit 17. The digital information is applied via the counter 14 to the digital-to-analog converter 15 which decodes it into the analog tuning voltage. The tuning voltage is supplied to the tuning capacitance diode included within the tuner 2.
FIG. 3 shows another example of the tuning scheme further comprising a noise skip circuit. As described above, when the true television signal is received, the output from the AFT detector will change in polarity and upon such change the television synchronizing signal will be derived from the start/stop circuit 9. This synchronizing signal is supplied to a noise skip circuit 18 to decide whether or not this is the true television vertical synchronizing signal. Particularly when the true vertical synchronizing signal is confirmed, this is applied to the signal decision circuit 12 and simultaneously applied as the search stop pulse to the tuning voltage generator 10. Contrarily, when concluded as noise and not the synchronizing signal, this will be supplied as the re-start pulse to the start/stop circuit 9. This permits the recurring of the same operation as when the search start instruction is issued for the first time. In the given example, the vertical synchronizing signal obtained from the noise skip circuit 18 is utilized as the search stop pulse.
In this way the search stop pulse is developed from noise skip circuit 18 and sent to the tuning voltage generator 10, stopping the generator 10 from generating the sweep voltage. The instantaneous voltage is thereafter kept and sent to the tuner 2 via the memory circuit 11. Under these circumstances the signal decision circuit 12 determines again whether the vertical synchronizing signal developed from the start/stop circuit 9 is the true television synchronizing signal.
By way of example, the signal decision circuit 12 may be adapted to count the number of the synchronizing signals and determine whether a predetermined number of the synchronizing signals are present during a given period of time. If the true synchronizing signal is sensed, then the signal decision circuit 12 will release the memory instruction, permitting the memory circuit 11 to store the tuning voltage supplied from the generator 10.
Nevertheless, even if the noise skip circuit 18 delivers the false synchronizing signal inadvertently, the signal decision circuit 12 never overlooks it so that the circuit 12 issues the search re-start pulse. The start/stop circuit 9 receives such pulse to repeat the above mentioned operation. In other words, the operation is repeated to assure the optimum reception condition until the true television synchronizing signal is available from the start/stop circuit 9 and the noise skip circuit 18. The memory instruction will be issued immediately after the optimum reception condition is reached.
Details of the noise skip circuit 18 are shown in FIG. 4. This is split into three major portions: an integration circuit portion 21 consisting of resistors R₁ and R₂ and capacitors C₁ and C₂ ; a noise detection circuit portion 22 consisting of transistors Q₁, Q₂ and Q₃, a diode D₁ and so on; and a synchronizing signal amplifier portion 23 consisting of a transistor Q₄ and so on. Assume now that the true television synchronizing signal (with negative polarity) as viewed from FIG. 5 a is derived from the start/stop circuit 9. This signal is integrated with the integration circuit portion 21 as shown in FIG. 5 b . The base bias voltage of the first stage transistor Q₁ in the noise detector portion 22 is fixed, say at approximately 0.3 volts, by the resistors R₃, R₄ and R₅ and the diode D₁. Thus, this signal at the positive polarity side is extremely shallow and the transistor Q₁ is placed into the cut off state as long as the genuine vertical synchronizing signal is derived. The remaining transistors Q₂ and Q₃ are also placed into the cut off state. Therefore, the noise detector portion 22 does not deliver the output signal or the search stop pulse. The vertical synchronizing pulse as shown in FIG. 5 c is applied to the base of the transistor Q₄ via the capacitor C₃ for amplification. The vertical synchronizing signal with the positive polarity as shown in FIG. 5 d is developed at the collector of the transistor Q₄ and supplied to the signal decision circuit 12 and as the search stop pulse to the tuning voltage generator 10.
On the other hand, if the noise signal, for example, as shown in FIG. 5 e is derived from the start/stop circuit 9, then this will be integrated with the integration circuit portion 21. The result is shown in FIG. 5 f , which has both positive and negative polarity components. Since the positive polarity component is well above the conduction level (say, 0.6 volts) of the transistor Q₁, the transistor Q₁ is turned on whenever an the transistors Q₂ and Q₃ are also turned on. The signal appearing at the emitter of the transistors Q₃ is shown in FIG. 5 h and returned as the search re-start pulse to the start/stop circuit 9.
By the action of the noise skip circuit 18. Whether the signal derived from the start/stop circuit 9 is the true synchronizing signal or noise is determined by the positive voltage level of that signal. Then, the synchronizing signal is supplied to the signal decision circuit 12 and the tuning voltage generator 10, while the noise is supplied as the search re-start pulse to the start/stop circuit. As shown in FIG. 6, a skip level adjusting variable resistor VR₁ installed in the noise detector portion 22 makes the above mentioned positive voltage level freely variable. It also becomes possible to supply the noise as the search re-start pulse to the start/stop circuit 9 when the normal television synchronizing signal is received but relatively strong noise is superimposed thereon.
Within the tuning scheme having the noise skip circuit, there is no opportunity inadvertently the tuning voltage generator 10 with the search stop instruction due to noise. In addition, only broadcasting stations with comparatively strong television signals can be preset in sequence while skipping ones with comparatively weak television signals. Although in the illustrated example the noise skip level is manually variable through the use of the variable resistor VR₁, it is noted that the skip level can be varied in response to the intensity of the television signals being received by applying an AGC voltage thereto.
Details of modifications in the start/stop circuit 9 and the tuning voltage generator 10 are shown in FIG. 7 wherein the search speed is variable.
Provided that the search start instruction or the search restart pulse is supplied via an OR gate 34 to a reset input terminal of an R-S type latch 33, the latch 33 will be in the reset state so that the Q output thereof assumes a "H" level to enable an AND gate 35. Another latch 39 of the R-S type 39 is also placed into the reset state in response to the search start instruction or the search re-start pulse. The Q ouput of the latch 39 assumes a "L" level and the Q output assumes a "H" level, enabling an AND gate 40. At this time clock pulses of, for example, 320 Hz are generated via an AND gate 40, an OR gate 47 and an AND gate 35 from a high speed clock pulse generator 36 and supplied to a counter 42 in the tuning voltage generator 10. The count of the counter 42 varies sequentially at a relatively high rate and is converted through a digital-to-analog converter 43. As a consequence, the converter 43 develops a gradually rising or dropping DC voltage, which is supplied to the tuner 2 via the memory circuit 11. A rate of variations in the tuning voltage derived from the generator 43 is relatively high and the searching procedure is carried out at a high speed.
While a specific television signal is received, the detector output is derived from the AFT circuit 4 and the vertical synchronizing signal is derived from the synchronizing separator 6. When an AFT negative output detector 44 senses the AFT detector output of the negative polarity, the output of the detector 44 increases to a "H" level. The AND gate 45 is enabled so that the vertical synchronizing signal is supplied to a set input terminal of the R-S type latch 39. The latch 39 is placed into the set state with the Q output thereof having a "H" level and the Q output thereof having a "L" level. The AND gate 40 is disabled concurrently with the enabling of the AND gate 46. Under these circumstances clock pulses of, for example, 160 Hz from a low speed clock pulse generator 47 are supplied to the counter 42 via the AND gate 46, the OR gate 41 and the AND gate 35. The counter 42 performs the counting operation at a low speed. A rate of variations in the tuning voltage or the DC voltage obtainable from the digital-to-analog converter 43 is reduced to one-half its initial rate and the searching procedure is carried out at a low speed.
If the polarity of the AFT detector output changes from negative to positive during the low speed searching operation, then the output of an AFT positive output detector will increase to a "H" level. The AND gate 38 is enabled and the vertical synchronizing signal is supplied via the AND gates 38 and 48 to the set input terminal of the R-S type latch 33 (the AND gate 48 is now enabled because of the Q output of the latch 39 at a "H" level). The latch 33 is therefore set. As a result, the Q output of the latch 33 changes to a "L" level to disable the AND gate 35. The counter 42 is supplied with the clock pulses no longer. Afterward, the count of the counter 42 remains unchanged and the tuning voltage derived from the digital-to-analog converter 43 is held at a fixed value. The searching operation comes to a stop.
Then, when the search start instruction of the search re-start pulse is issued again, the latch 33 and 39 are reset to enable AND gates 35 and 40. The clock pulses from the high speed clock pulse generator 36 are supplied to the counter 42, restarting the searching operation.
Another modification in the start/stop circuit 9 and the tuning voltage generator 10 is shown in FIG. 8. When the search start instruction or the search re-start pulse is supplied to the reset input terminal of the latch 33 via the OR gate 34, the Q output of the latch 33 in the reset state will assume a "H" level with the AND gates 35 and 49 enabled. The other latches 39 and 50 are also reset in response to the search start instruction or the search re-start pulse with the Q outputs thereof at a "L" level and the Q outputs thereof a "H" level. The AND gate 40 is enabled while the AND gate 46 and 51 remain disabled. The 320 Hz clock pulses from the high speed clock pulse generator 36 are derived via the AND gate 40, the OR gate 41 and the AND gate 35 and supplied to a count up input terminal of an up/down counter 42' in the tuning voltage generator 10. The counter 42' is sequentially incremented at a high speed, the count of which is supplied to the digital-to-analog converter 43. As a result, the converter 43 develops a gradually rising DC voltage which is supplied as the tuning voltage to the tuner 2 via the memory circuit 11. In this case variations in the tuning voltage are comparatively quicker and the searching operation is carried out by the increase of the local oscillation frequency.
Under these circumstances, when the television signal is received, The AFT circuit 4 develops the AFT detector output and the synchronizing separator 6 develops the vertical synchronizing signal. If there is the negative output sensed by the AFT negative output detector 44, the output of the detector 44 will assume a "H" level to enable the AND gate 45. The vertical synchronizing signal is supplied to the set input terminal of the R-S type latch 39 via the AND gate 45, setting the same. Since the Q and Q outputs of the latch 39 assume "H" and "L" levels respectively, the AND gate 46 is enabled and the AND gate 40 is disabled. The clock pulses with 160 Hz from the low frequency clock pulse generator 47 are supplied via the AND gate 46, the OR gate 41 and the AND gate 35 to the count up input terminal of the counter 42' to execute the counting operation at a relatively low speed. The DC voltage or the tuning voltage derived from the digital-to-analog converter 43 shows variations at a rate which is reduced to one half its initial rate. The searching operation is carried out with low speed in order to eventually increase the local oscillation frequency.
Thereafter, when the polarity of the AFT detector output changes from negative to positive during the slow searching operation, the output of the AFT positive output detector 37 increases to a "H" level, enabling the AND gate 38 such that the vertical synchronizing signal is supplied to a set input terminal of an R-S type latch 50 therethrough. The result is that the latch 50 is placed into the set state with the Q output thereof at a "H" level and the Q output thereof at a "L" level. An AND gate 57 is enabled and the AND gates 40 and 46 are disabled. Therefore, clock pulses with, for example, 20 Hz are derived from an extremely low speed clock pulse generator 52 and supplied to a count down input terminal of the counter 42' via AND gates 51 and 49. The count of the counter 42' is gradually decremented at an extremely low speed. A gradually dropping tuning voltage is suddenly obtainable from the converter 43 and a rate of variations in the tuning voltage is reduced to a large extent. The searching operation is carried out with extremely low speed in a sense to decrease the local oscillation frequency.
If the output of the AFT positive output detector 37 changes to a "L" level while executing the extremely slow searching operation in the opposite direction, an output of an inverter 53 will change to a "L" level with the output of the AND gate 48 at a "H" level. The latch 33 is set with the Q output changing to a "L" level. The AND gates 35 and 49 are disabled to stop supplying the counter 42' with the clock pulses any more. Thereafter, the content of the counter 42' is fixed and the tuning voltage from the digital-to-analog converter 43 remains unchanged. In this way, the searching operation comes to a halt at the normal point of local oscillation.
If the search start instruction or the search re-start pulse is then given, then all of the latches 33, 39 and 50 are reset to enable the AND gates 35 and 40 again. The clock pulses from the high speed clock pulse generator 36 are supplied to the counter 42', executing the high speed searching operation.
Although in the given example the three clock pulse generators 36, 47 and 52 are employed for the high speed phase, low speed phase and extremely low speed phase of the searching operation, a single clock pulse generator with the frequency division ability can be a substitute therefor.
An embodiment of the present invention shown in FIGS. 9 through 11 includes an out-of-tuning detector 65 in addition to the start/stop circuit 9, the tuning voltage generator 10, the memory circuit 11 and the signal decision circuit 12.
When the search start instruction is given to the start/stop circuit 9 during the presettable tuning operation, an AFT ON/OFF switch 64 will be turned off automatically, shifting from one terminal a to another b . A reference voltage from a reference voltage generator 63 is supplied to an AFT terminal of the tuner 2. The preset tuning operation keeps on under these circumstances.
The re-preset tuning operation is carried out in the following manner. If the memory circuit 11 associated with a desired channel is given the tuning instruction, then the tuning voltage stored in that memory circuit 11 is supplied to the tuner 2 via the tuning voltage generator 10 in order to select the desired channel.
The out-of-tuning detector 65 is enabled at a moment upon receipt of the above mentioned tuning instruction, where the AFT detector output voltage obtained from the AFT circuit 4 is compared with the given reference voltage from the reference voltage generator 63. If there is almost no deviation from the optimum tuning point, both the voltages are substantially equal with no development of the output pulse. On the other hand, if a difference therebetween exceeds a critical value, this is sensed to deliver the output pulse which in turn is supplied as the search re-start pulse to the start/stop circuit 9. The preset tuning operation restarts when the tuner 2 has becomes out of tuning.
The out-of-tuning detector 65 is illustrated in detail in FIG. 10, which comprises switches SW₁₁ and SW₁₂, transistor Q₁₁ and Q₁₂, resistors R₁₁, R₁₂ and R₁₃, an OR gate OR₁₁ and so on. Upon receipt of the tuning instruction the switches SW₁₁ and SW₁₂ are turned on instantly so that the reference voltage from the reference voltage generator 63 is applied to the base of the transistor Q₁₁ and the emitter of the transistor Q₁₂ via the switch SW₁₁ and the resistor R₁₁, whereas the AFT detector output voltage from the AFT circuit 4 is applied to the emitter of the transistor Q₁₁ and the base of the transistor Q₁₂ via the switch SW₁₂. Provided that the local oscillation frequency stands at the normal point without any substantial deviation, the AFT detector output voltage will be nearly equal to the reference voltage (say, within one volt) and the transistors Q₁₁ and Q₁₂ will be in the cut off state. No output voltage is developed at the collectors of the transistors Q₁₁ and Q₁₂. When being in the out-of-tuning state, the AFT detector output voltage will tend to somewhat increase over the reference voltage (say, one volt higher), placing the transistor Q₁₁ into the on state with a positive pulse voltage appearing at the collector thereof. This pulse is supplied to the tuning voltage generator 10 directly or via the start/stop circuit 9 and supplied as the start/stop pulse to the start/stop circuit 9 via the OR gate OR₁₁. As a result, the re-search operation is initiated and the tuning voltage at the tuning voltage generator 10 is gradually increased. Therefore, the local oscillation frequency will be reverted back to the normal point of tuning. When the signal decision circuit 12 issues the memory instruction, the instantaneous tuning voltage is loaded into the memory circuit 11 thereby completing the re-preset tuning operation. If the local oscillation frequency will be increased above the normal point, the transistor Q₁₂ is turned on to develop the output pulse at the collector thereof. This is supplied to the start/stop circuit 9 and the tuning voltage generator 10, gradually decreasing the tuning voltage at the tuning voltage generator 10.
An embodiment shown in FIG. 12 is effective with the ability of temporarily inhibiting the supply of the memory instructions to the memory circuit and skipping the memorizing of undesired channels when the capacity of the memory circuit 11 is small. There is further provided a memory skip circuit 66 which controls the transferring of the memory instructions from the signal decision circuit 12 to the memory circuit 11. While the memory skip circuit 11 is normally connected to the contact a , the memory instruction is supplied from the signal decision circuit 12 to the memory circuit 13 via the skip circuit 13 each time a specific channel is selected. The respective tuning voltages are therefore stored in the memory circuit 11 at these moments.
If an undesired channel is selected and received, then a skip instruction is given to the memory skip circuit 66 by way of any means, putting it toward the contact b . At this moment the memory instruction is supplied as the search restart pulse to the start/stop circuit 9 which restarts the searching operation to seek the next succeeding channel. Since the memory skip circuit 66 has then been returned to the contact a , the next memory instruction is supplied to the memory circuit 11, loading the tuning voltage of that channel into the memory circuit 11.
In an embodiment shown in FIG. 13, the tuning instruction from the signal decision circuit 12 is supplied to a blinking enable circuit 70 which comprises an AND gate and an amplifying transistor. Pulses derived from a pulse oscillator 71 are gated as well as the tuning instruction, energizing a light emitting diode 72 to notify the operator of the tuning operation.
An embodiment shown in FIG. 14 is adapted to produce audiable sounds instead of release of light. An audio silence circuit 75 is enabled by the tuning instruction from the signal decision circuit 12, which provides the output thereof for an audio circuit 76 to shut out the television audio signals. No television audio signals are released from a loud speaker 77. Meanwhile, the tuning instruction is supplied to an intermittent sound generator 78 which creates intermittent sound signals through synthesis of pulse signals from a pulse oscillator 79 and a frequency divider 80. The synthesized sound signals are supplied to the audio circuit 76.
As a result, intermittent sounds are released from the loud speaker 7 during the automatic tuning operation. Once the tuning operation has been completed and the true television signal has been received, these intermittent sounds are prohibited and the true television sounds are released from the loud speaker 77.
The tuning instruction with a "H" level from the signal decision circuit 12 is amplified by the audio silence circuit 75 and supplied to the audio circuit 76, which shuts out the television sound signals. The tuning instruction with a "H" level is also supplied to an AND gate 81 in the intermittent sound circuit 78. The AND gate 81 always receives pulses from the pulse oscillator 79 consisting of a multivibrator. These pulses are also supplied to the frequency divider 80 such that the AND gate 81 develops intermittent pulse signals, which are supplied to the audio circuit 76 and then the loud speaker 77.
The invention being thus described, it will be obvious that the same may be varied in many ways. Such variations are not to be regarded as a departure from the spirit and scope of the invention, and all such modifications are intended to be included within the scope of the following claims.