This CHASSIS is a improved version of the TX containing the multi standard feature developed around additional units.
The first unit is the AM SOUND UNIT 4822 212 20459 with TDA1039P
The second unit is fitted under the above mentioned unit.
The Philips TX monochrome portable chassis has been in production for several years and large numbers have been sold in the Philips model ranges. several versions, with 12 and 14in. tubes, and with/without remote control. There have also been a number of modifications - most of these are of little significance from the servicing point of view, though it's worth noting that a simplified field generator stage is used in later production.
Power Supply Circuit:
As with any set, the power supply is the key to what goes on. The circuit of the TX's power supply, which consists basically of a transformer -fed mains bridge rectifier followed by a series regulator, is shown in Fig. 5. This is conventional though there are one or two points worth noting. First, one of the diodes in the bridge rectifier circuit, D110, also serves as the reverse polarity protection diode on battery operation. Switch SK2 is part of the battery input socket. This can cause problems, as we shall see. Secondly the error detector/amplifier transistor TS112 is operated from the line output stage derived 26V boost rail. This provides protection against excessive voltages in the line output stage, since excessive boost voltage will cut off TS112 and in turn TS111 and TS110. In the event of line output stage failure, TS112, TS111 and TS110 will again be cut off. The result could be excess voltage on the 10.8V line which will also be unstabilised, i.e. fed via RHO only. This would damage the tube, whose heater is connected across the 10.8V rail. To avoid this situation, diodes D115 and D116 conduct when the line output stage is not working, thus reducing the voltage on the 10.8V line. These diodes were not fitted in early production sets. The fourth transistor TS113 provides the tuner with a stabilized 11.3V supply. The tuning voltage is stabilized by a TAA550 in the usual way.Line Timebase:
The line generator circuit (Fig. 6) is rather unusual. The first transistor TS380 provides
the flywheel sync action: a line -frequency sawtooth is applied to its emitter while the line sync pulses are applied to its base. Following the flywheel sync filter, TS392 sets the voltage conditions in the line hold control network. The oscillator itself consists of TS390 and TS391 which are connected in an emitter coupled astable multivibrator configuration.
No Sound or Raster:
If there's no sound or raster, check the voltage at the emitter of TS110. If there's no voltage here, check the fuses - VL100 (on the mains transformer), VL110 and VL111. If VL100 or VL110 is open -circuit, check the bridge rectifier diodes D110/111/113/114 and the protection capacitors C116-9 for shorts and if necessary the mains transformer T110 for shorted turns. If VL111 is open -circuit, the 1.t. reservoir capacitor C112 could be leaky. Alternatively there could be a short-circuit in the line or sound output stage. Check the output transistor TS450, then D450, C450 and the scan coupling capacitor C455 in the line output stage. Check the smoothing capacitor C314 (47μF) and the output coupling capacitor C311 (100μF) in the audio output stage. If the fuses are o.k., check the voltage at the collector of TS110. If this is low at 2-8V, check TS110, TS111 and TS112 as necessary. If the voltage at the collector of TS110 is more than 8V, check the boost voltage - at pin 6 of the line output transformer. If the voltage here is less than 15V, check the line output transistor, check whether C455 is leaky, then check the line output transformer by substitution. If the voltage at pin 6 is in excess of 15V, check whether R451 is open -circuit, thus removing the supply to the line oscillator. In the event of R451 being open -circuit, check for shorts in the field generator circuit. If R451 is o.k., check the voltage at the base of the line driver transistor TS410. The reading should be about -0.1V. If this is present, check TS410 and TS450. If the reading is absent, check whether R401 is open -circuit, thus removing the supply to the line oscillator stage. Finally check TS390, TS391 and TS410 by replacement.
Normal Sound, No Raster:
For the sound normal, no raster condition, first check whether the tube's heater is alight. If not, check the continuity of the heater winding. Next remove the aerial plug. If there's insufficient brightness, check the a.g.c. amplifier transistor TS351 (BC548) by replacement. If there's still no brightness, turn the contrast to minimum, the brightness to maximum, and make voltage checks at the c.r.t. base. The cathode voltage (pin 2) should be 67V. If this is incorrect, check the video output transistor TS560 (BF422) and if necessary the field flyback blanking transistor TS565 (BC548C). If the voltage at pin 2 is correct, check the grid voltage (pin 5) which should be about 57V. If this voltage is missing, check whether the grid decoupling capacitor C572 (0.1μF) is short-circuit, then check whether the 95V supply is being developed across C452. If not, check R450 and D453 for being open -circuit. Next check the first anode voltage (pin 6) which should be 160V. If not, check R570 (820kOhm), R452 and D455. Finally check the e.h.t. circuit if necessary - from pin 8 of the line output transformer through the rectifier to the final anode of the c.r.t. Normal Sound, Weak or No Picture In the event of normal sound with a weak picture or no picture, check the voltage at the emitter of the video output transistor TS560. This should be 3.3V. If incorrect, check TS560; if correct, check the video driver transistor TS350 (BC558).
Field Collapse:
In the event of field collapse, check whether the field output stage feed resistor R529 (33n) is open -circuit. If so replace it and check the output transistors TS521/2 (BC338/BC328). Next check the field output stage midpoint voltage - 10.1V at the emitter of TS521. If this is incorrect, check the output transistors, the field driver transistor TS523 (BC548) and the preamplifier transistor TS520 (BC559B). If necessary che
ck the scan coupling capacitor C527 (100μF) and the earth return resistor R527 (4.7Ohm), then suspect the field generator circuit. Check the transistors TS505/TS509/TS515 and the values of resistors R515 (470kf1), R517 (3901(n) and R516 (height control - 220kn). The original field generator circuit is shown in Fig. 1. The charging capacitor C503 charges from the 26V rail via R503, R507 and the constant -current transistor TS505. When the ramp at the emitter of TS505 reaches the voltage at its base, set by R502/4, TS505 switches off. The positive -going voltage at its collector then switches TS509 on, and in turn TS515 to discharge C503.
Loss of Line Sync:
In the event of loss of line sync, first remove the aerial input and check that the 1.t. line is correctly set for 10.8V. If the correct voltage cannot be obtained by adjusting R113, check TS110, TS111, TS112 and make sure that R114 is 3.9Ohm (in some sets it's 4.7MOhm). If the supplies are correct, check the voltage at the positive side of the a.g.c. smoothing capacitor C351 (47μF). With the aerial discon- nected the reading should be 4.3V. With the aerial connected a reading of 6-8V should be obtained. If the voltage conditions are incorrect, suspect the a.g.c. amplifier transistor TS351 (BC548). If necessary, try adjusting the line hold control R394 with the emitter of the flywheel sync transistor TS380 shorted to chassis and the aerial connected. If line lock cannot be obtained, replace the line oscillator transistors TS390 and TS391. If line lock can be obtained but the sync floats on removing the shorting link, suspect TS380 and TS392.
Miscellaneous Faults and Modifications:
Sound buzz with unstable picture, possibly intermittent: Suspect the battery socket - the switch can become tarnished. Replacement cures. Uncontrollable sound: Suspect the d.c. volume control R302 (4.710 or the TBA120AS intercarrier sound chip (IC310). Intermittent line collapse, with vertical line: Change C393 to 0.0015μF. Philips advise that the value of C393 in all sets bearing factory code HU on the chassis or serial plate is checked and changed to 0.0015μF if necessary. Bright vertical line at left-hand side: If a replacement line output transformer does not cure this, change C412 to 0.006814F and TS410 to a BC637 (note that the base connections differ). Distortion at low volume: Change R300 to 18kOhm, R311 to 56f1, R312 to 3.3kOhm/ and R315 to 120kOhm. Brightness range: Where the tube is type 12VCUP4, R576 should be 470kOhm Where the tube is type 12BJP4 it should be 820kOhm.
Power supply is realized with mains transformer and Linear transistorized power supply stabilizer, A DC power supply apparatus includes a rectifier circuit which rectifies an input commercial AC voltage. The rectifier output voltage is smoothed in a smoothing capacitor. Voltage stabilization is provided in the stabilizing circuits by the use of Zener diode circuits to provide biasing to control the collector-emitter paths of respective transistors.A linear regulator circuit according to an embodiment of the present invention has an input node receiving an unregulated voltage and an output node providing a regulated voltage. The linear regulator circuit includes a voltage regulator, a bias circuit, and a current control device.
In one embodiment, the current control device is implemented as an NPN bipolar junction transistor (BJT) having a collector electrode forming the input node of the linear regulator circuit, an emitter electrode coupled to the input of the voltage regulator, and a base electrode coupled to the second terminal of the bias circuit. A first capacitor may be coupled between the input and reference terminals of the voltage regulator and a second capacitor may be coupled between the output and reference terminals of the voltage regulator. The voltage regulator may be implemented as known to those skilled in the art, such as an LDO or non-LDO 3-terminal regulator or the like.
The bias circuit
may include a bias device and a current source. The bias device has a
first terminal coupled to the output terminal of the voltage regulator
and a second terminal coupled to the control electrode of the current
control device. The current source has an input coupled to the first
current electrode of the current control device and an output coupled
to the second terminal of the bias device. A capacitor may be coupled
between the first and second terminals of the bias device.In the bias device and current source embodiment, the bias device may be implemented as a Zener diode, one or more diodes coupled in series, at least one light emitting diode, or any other bias device which develops sufficient voltage while receiving current from the current source. The current source may be implemented with a PNP BJT having its collector electrode coupled to the second terminal of the bias device, at least one first resistor having a first end coupled to the emitter electrode of the PNP BJT and a second end, a Zener diode and a second resistor. The Zener diode has an anode coupled to the base electrode of the PNP BJT and a cathode coupled to the second end of the first resistor. The second resistor has a first end coupled to the anode of the Zener diode and a second end coupled to the reference terminal of the voltage regulator. A second Zener diode may be included having an anode coupled to the cathode of the first Zener diode and a cathode coupled to the first current electrode of the current control device.
A circuit
is disclosed for improving operation of a linear regulator, having an
input terminal, an output terminal, and a reference terminal. The
circuit includes an input node, a transistor, a bias circuit, and first
and second capacitors. The transistor has a first current electrode
coupled to the input node, a second current electrode for coupling to
the input terminal of the linear regulator, and a control electrode. The
bias circuit has a first terminal for coupling to the output terminal
of the linear regulator and a second terminal coupled to the control
electrode of the transistor. The first capacitor is for coupling between
the input and reference terminals of the linear regulator, and the
second capacitor is for coupling between the output and reference
terminals of the linear regulator. The bias circuit develops a voltage
sufficient to drive the control terminal of the transistor and to
operate the linear regulator. The bias circuit may be a battery, a bias
device and a current source, a floating power supply, a charge pump, or
any combination thereof. The transistor may be implemented as a BJT or
FET or any other suitable current controlled device.
Power
Supply: The examples chosen are taken from manufacturers' circuit
diagrams and are usually simplified to emphasise the fundamental nature
of the circuit. For each example the particular transistor properties
that are exploited to achieve the desired performance are made clear. As
a rough and ready classification the circuits are arranged in order of
frequency: this part is devoted to circuits used at zero frequency,
field frequency and audio frequencies. Series Regulator Circuit Portable
television receivers are designed to operate from batteries (usually
12V car batteries) and from the a.c. mains. The receiver usually has an
11V supply line, and circuitry is required to ensure that the supply
line is at this voltage whether the power source is a battery or the
mains. The supply line also needs to have good regulation, i.e. a low
output resistance, to ensure that the voltage remains constant in spite
of variations in the mean current taken by some of the stages in the
receiver. Fig. 1 shows a typical circuit of the power -supply
arrangements. The mains transformer and bridge rectifier are designed to
deliver about 16V. The battery can be assumed to give just over 12V.
Both feed the regulator circuit Trl, Tr2, Tr3, which gives an 11V output
and can be regarded as a three -stage direct -coupled amplifier. The
first stage Tr 1 is required to give an output current proportional to
the difference between two voltages, one being a constant voltage
derived from the voltage reference diode D I (which is biased via R3
from the stabilised supply). The second voltage is obtained from a
preset potential divider connected across the output of the unit, and is
therefore a sample of the output voltage. In effect therefore Tr 1
compares the output voltage of the unit with a fixed voltage and gives
an output current proportional to the difference between them. Clearly a
field-effect transistor could do this, but the low input resistance of a
bipolar transistor is no disadvantage and it can give a current output
many times that of a field-effect transistor and is generally preferred
therefore. The output current of the first stage is amplified by the two
subsequent stages and then becomes the output current of the unit.
Clearly therefore Tr2 and Tr3 should be current amplifiers and they
normally take the form of emitter followers or common emitter stages
(which have the same current gain). By adjusting the preset control we
can alter the fraction of the output voltage' applied to the first stage
and can thus set the output voltage of the unit at any desired value
within a certain range. By making assumptions about the current gain of
the transistors we can calculate the degree of regulation obtainable.
For example, suppose the gain of Tr2 and Tr3 in cascade is 1,000, and
that the current output demanded from the unit changes by 0.1A (for
example due to the disconnection of part of the load). The corresponding
change in Tr l's collector current is 0.1mA and, if the standing
collector current of Tr 1 is 1mA, then its mutual conductance is
approximately 4OmA/V and the base voltage must change by 2.5mV to bring
about the required change in collector current. If the preset potential
divider feeds one half of the output voltage to Tr l's base, then the
change in output voltage must be 5mV. Thus an 0.1A change in output
current brings about only 5mV change in output voltage: this represents
an output resistance of only 0.0552.PHILIPS 12B711 /00 TRIXI CHASSIS TX CIRCUIT ARRANGEMENT FOR SURPRESSING THE CHROMINANCE SUBCARRIER IN PAL SIGNAL:
A circuit for eliminating the color component of a composite television signal has two comb filters. Both filters have internal feedback and one uses subtraction, while the other uses addition. This prevents a loss of vertical definition in the picture.1. A circuit for suppressing the color signal component of a composite color television signal comprising a pair of comb filters; means for applying at least said color signal component to said filters; each of said filters comprising a delay line having a delay substantially equal to one line period of said television signal and having an input coupled to receive said color signal component and an output, means coupled to said delay line output for combining the delayed and undelayed color signal component, a first of said combining means adding said signals, the remaining second combining means subtracting said delayed from said undelayed color signal components, means for feeding back a portion of said combining means output to the input of said respective delay lines; first and second means for amplifying the output signals from said combining means by selected values; and means for subtracting said amplified signals from said composite television signal; whereby a luminance signal is produced. 2. A circuit as claimed in claim 1 wherein said second combining means comprises a phase inverter coupled to the second filter delay line, and an adder coupled to said phase inverter and to receive the undelayed signal. 3. A circuit as claimed in claim 1 wherein said applying m
eans comprises a bandpass filter for passing only the color signal component, said filter having a given time delay; and further comprising a delay line having a delay substantially equal to said bandpass filter delay and having an input coupled to receive said composite signal and an output coupled to said subtracting means. 4. A circuit as claimed in claim 1 wherein said amplifying means amplify by the same amount, and both of said feedback means satisfy the equation v = (1 - k)/2 + 2k wherein v is the value of said amplification, and k is the value of said feedback, k being greater than zero. 5. A circuit as claimed in claim 1 wherein both of said delay lines having a delay time that satisfies the equation 1/T = fz (1 - e/n) wherein T is said delay time, fz is the line frequency, e is equal to 0.25, and n equals 284.
Description:
The invention relates to a circuit arrangement for suppressing the color information signal present in a video signal (FBAS signal) of a PAL color television signal.
The circuit arrangement is to separate the interlaced frequency spectral lines of the luminance signal and the chrominance signal and to suppress the chrominance signal. FIG. 1 shows the frequency spectrum of a PAL signal. The spectral lines or the components of the luminance (Y) signal are located at integral multiples of the line frequency f z and may extend into the frequency range of the chrominance subcarrier f o = 4.43 MHz. In the frequency range of the chrominance subcarrier the spectral lines or the components of the color difference signals U, V and the chrominance sub carrier component are grouped around the Y-components, every time shifted over one fourth of the line frequency. In commercial TV receivers a bandpass filter or a wavetrap in the chrominance subcarrier range is considered to be satisfactory for the separation of the last-mentioned components from the luminance signal and interference in color and in the finer picture details are taken into account at the boundaries of the pass and suppression regions.
In transcoding, for example, of a video signal in accordance with the PAL standard into a signal in accordance with the SECAM standard, small amplitude signals at these boundaries cause disturbing interference in the SECAM chrominance subcarrier(s).
A filter for filtering the luminance signal Y should thus have a characteristic as shown in FIG. 1b in which the ratio of the output voltage relative to the input voltage is given as a function of the frequency. Filters having such a characteristic in which the zero points occur periodically along the frequency axis are called comb filters. In this case generally a signal is applied directly and through a delay line to an adder or subtractor circuit. The output voltage of such a circuit is then dependent on the phase shift caused in the signal by the delay line: at a phase shift of 180° a minimum (maximum) occurs at the output of the adder circuit (subtractor circuit) while at a phase shift of 0° or 360° a maximum (minimum) occurs. If the delay period T of the delay line is chosen to be as large as one line period 1/f z , the luminance signal may also be passed on or cut off at the high frequencies, dependent on whether the delayed and the undelayed signal are added together or subtracted from each other. On the other hand, if one of the components U or V of the color difference signal is to be filtered, the delay period T must be longer. In that case the following equation must be satisfied 1/T = f z (1-e/n) wherein for PAL e = 0.25 and n = 284 (compare Telefunken Zeitung, Vol. 37 (1964) No. 2 pages 115-135).
Such comb filters have sometimes been used for separating the chrominance signal. However, a principal drawback of all these known circuits is the deterioration of the definition of the picture in the vertical direction. This will be explained in greater detail with reference to FIG. 2. It is assumed that the luminance from the end of a line u changes stepwise, that is to say, the Y-signal amplitude changes from, for example, 100 percent to 0. This luminance signal step at the input of the comb filter is shown in FIG. 2a as a function of the number of line periods. During the line n + 1 the undelayed Y-signal (Y in ) is 0; the delayed Y-signal has, however, still the value of 100 percent (from the previous line) so that after addition or subtraction of both the signals at the output of the comb filter a mean value near 50 percent of the previous output signal (Y out ) is produced (see FIG. 2b). Since in the PAL system the signal is to be partially delayed for two lines, a mean value is also produced during the line n + 2 and then only the output signal follows the input signal.
A further drawback is that without additional steps the pass regions always have the shape of half a period of sine curve. However, the comb filter must have a very wide pass region for the Y-signal, as is shown in FIG. 1b, because the spectrum of the Y-signal in contrast with the spectrum of the chrominance signal and being different from that shown in FIG. 1a does not have sharp lines in the region of the chrominance sub-carrier. It is known from the said Article that the pass region may be formed in the desired manner by suitable feedback from the output of the comb filter to the input of the delay line. However, this causes the definition in the vertical direction to be still worse because the delayed signal is brought through the feedback to the input of the delay line again and this delay line continues again, although in a weaker form, so that the output signal of the comb filter cannot follow the step of the input signal during many line periods.
In a known circuit arrangement (Internationale Elektronische Rundschau 1969, No. 8 particularly FIG. 5) this integrating action of the comb filter which deteriorates the definition in the vertical direction is obviated to a great extent in that the video signal and the color information is divided with the aid of a highpass and a lowpass filter, in which only the portion of high frequency containing the color information is passed on to the comb filter, while the low-frequency portion which does not contain color information is delayed for one line period and undergoes a vertical aperture correction. However, the vertical aperture correction involves high costs.
An object of the present invention is to obviate the mentioned drawbacks. Starting from a circuit arrangement for suppressing the color inf
ormation signal (F signal) present in a PAL color television signal (FBAS signal) by means of at least one comb filter which includes one delay line which delays the FBAS signal or the components of the FBAS signal located in the frequency range of the F signal by approximately the duration of the period of the line frequency, and adds the delayed signal to the undelayed signal or subtracts it therefrom and feeds back the sum or the difference to the input of the delay line, this object according to the invention is achieved in that at least the components of the FBAS signal located in the frequency range of the F signal are applied to the parallel-arranged inputs of two comb filters one of which adds the delayed signal to the undelayed signal, while the other subtracts the delayed signal from the undelayed signal, and in that the signals at the output of the comb filters are amplified by a given factor, added together and subtracted from the FBAS signal.
In order that the invention may be readily carried into effect an embodiment thereof will now be described in detail by way of example with reference to the accompanying diagrammatic drawings, in which:
FIG. 3 shows a block diagram of a circuit arrangement according to the invention,
FIG. 4 shows the frequency characteristic of a transfer element used in the circuit arrangement of FIG. 3 for the total FBAS signal (4a), the frequency characteristic of the first comb filter (4b), the frequency characteristic of the second comb filter (4c) and the frequency characteristic at the output of a circuit arrangement according to FIG. 3 (4d).
FIG. 5 shows the variation with time of the output signal of the circuit arrangement of FIG. 3 when an input signal in accordance with FIG. 2a is changed.
In the circuit arrangement shown in FIG. 3 the video signal of a PAL color television signal including luminance and color information is applied to a bandpass filter 4 and to a delay line 5 whose delay period corresponds to the delay of the signals passing through the bandpass filter 4. The output of the delay line 5 is connected to a subtractor circuit 3. The bandpass filter 4 only passes those frequency components of the input signal which include color components and applies the signals filtered in this manner to the inputs of two comb filters 1 and 2 where output signals are amplified by amplifiers 6 and 7, respectively, added together and applied to the input of the subtractor circuit 3 where they are subtracted from the FBAS signal coming in through the delay element 5.
The bandpass filter 4 renders the use of simple delay lines having a small bandwidth (2 MHz) possible and ensures that the integrating action of the comb filter for the Y signal also occurring to a slight extent in the circuit arrangement according to the invention only exerts influence on the signal components of high frequencies.
The comb filters are in principle formed identically. Each comb filter includes an adder stage 11 and an adder stage 21, respectively, which add the delayed and the undelayed signal. The resultant signal is fed back from the output of the adder stage by means of a feedback network 12 (22) to the input of a further adder circuit 13 (23). This further adder circuit adds the feed-back signal and the output signal of the bandpass filter 1 and applies its output signal to the input of the delay line 14 (24) which delay line delays the signal by a period of T, in which for a conventional PAL signal the relation 1/T = f z (1 - e/n) with e = 0.25 and n = 284 is satisfied, and wherein f z is the line frequency. In addition the amplified signal in the comb filter 2 is shifted 180° in phase by the inverter circuit 25 and is applied to the adder circuit 21. (A subtractor circuit may of course alternatively be used which then takes the place of the parts 21 and 25 and subtracts the delayed signal from the undelayed signal).
The comb filters described are known per se from the previously mentioned Article, particularly FIG. 27. Exclusively the components of a first color difference signal U (comb filter 2) and of a second color difference signal V (c
omb filter 1) present in the PAL signal appear at the output. Their action together with the rest of the circuit arrangement may be illustrated with reference to the frequency characteristics shown in FIG. 4.
FIG. 4a illustrating the frequency characteristic of the delay element 5 shows that the total FBAS signal reaches the output of the subtractor circuit 3 in an unattenuated form. FIG. 4b and FIG. 4c show the frequency characteristics of the comb filters 2 and 1, respectively, which pass only the color difference signal components U and V, respectively, every time. The pass characteristics have sharper peaks as the positive feedback is larger. When the amplification of the amplifiers 6 and 7 is chosen to be such that the amplitude of the U and V components applied to the subtractor circuit has the same value as that of the U and V components in the FBAS signal, then they are compensated eminently in the signal at the output of the subtractor circuit 3 so that the total filter characteristic shown in FIG. 4d is produced.
Other properties of the circuit arrangement according to the invention are apparent from a quantitative analysis. The output voltage U 2 , in so far as it is located in the frequency range of the chrominance signal, can be calculated from
u 2 = u 1 - v 1 u s - v 2 u d (1)
In this case u 1 is the input voltage, u s and u d are the output voltages of the comb filters 1 and 2, respectively. The quantities u 1 , u 2 , u s and u d represent complex voltage amplitudes. The references v 1 and v 2 indicate the amplification factors of the amplifiers 6 and 7.
The voltages u s and u d in accordance with equations 21 and 22 of the previously mentioned Articles are as follows:
and
In these formulas k 1 and k 2 are the (positive) feedback factors (k 1 , K 2 < 1) of the feedback networks 12 and 22; w is the angular frequency. If the Equations 2 and 3 are substituted in the Equation 1 then this results in the following formula, provided that v 1 = v 2 = v and k 1 = k 2 = k:
If v is chosen to be such that in the Equation (4) the second term becomes 1 at a maximum (maximum values of this term occur as exp (-2jwT) = + 1), then the function value is zero, and in this case there must apply that
The zero values are located at the frequencies of the chrominance subcarriers, the U-components and the V-components for which there applies that 1/T = f z (1-e/n). After substitution of the Equation (5) in the Equation (4) and after some derivation this results in:
Equation (6) shows that for k = 0 the output voltage u 2 becomes 0. This is readily evident because the action of the delay line 14 is eliminated by that of the delay line 24 because subtraction is effected once and addition is effected once. This means that a feedback (k ≠ 0) is absolutely necessary.
The minimum zero values of the quotient u 2 /u 1 occur, as already shown, at exp (2-jwT) = + 1. The maximum values occur at exp (- 2jwT) = - 1. These values are located exactly in the middle between the minimum values and thus at the area of the components of the Y-signal. The maximum values are:
The maximum value for k = 0.7 has a value of for example 0.94. The Y-components of the output signal u 2 -- in so far as they are located in the frequency range of the chrominance signal -- thus have an amplitude which is 6 percent lower than the Y-components in the input signal u 1 or the low-frequency components of the Y-signal applied to the input of the subtractor circuit. This slight difference, which is the slighter as k is larger, may optionally be eliminated by an additional amplification of the high-frequency Y-components.
In case of a step of the Y (luminance) signal at the input of the circuit from 100 percent to 0, as is shown in FIG. 2a, the following takes place: the Y-signal provided through the delay element 5 or through the bandpass filter 4 occurs directly after the step 0 when the delay of the elements 4 and 5 is left out of consideration. The delay line 14 (24) acts, however, as a memory for the signal value present before the step. Since this value added to U 1 (or subtracted therefrom) yields u 2 (u d ) it must have the value u s + u 1 (u d + u 1 ). The signals provided by the delay lines 14 and 24 yield u s + u d after addition likewise as before the step. However since (for k = 0.7) the Y-component of the signals coming through the comb filters reduces the Y-component of the signal u 1 by only 6 percent, this small component of the Y-signal only appears at the input and -- because no signal is provided anymore through the amplifier element 5 -- at the out
put of the subtractor device. As a result of the feedback to the inputs of the delay lines 14 and 24, a signal attenuated by the feedback factor k is produced at the end of the line period, which signal is further attenuated at the end of the next line. The signal values occurring at the output of the subtractor circuits are, however, so small that they are not disturbing.
The circuit reacts in the same manner in case of one of the vertical color steps which occur rarely. Since the U and V components coming through the delay line have a large amplitude (100 percent of the U and V components present in the signal u 1 ) a severe color distortion might be produced at the outputs. This distortion may be prevented in known manner (compare the Internationale Elektronische Rundschau 1969, No. 8, page 199, FIG. S) by a chrominance subcarrier suppression circuit not further shown in the drawing. Such a chrominance subcarrier suppression circuit suppresses the greater part of the energy present in the chrominance signal in a limited region around the chrominance subcarrier.
The circuit arrangement is to separate the interlaced frequency spectral lines of the luminance signal and the chrominance signal and to suppress the chrominance signal. FIG. 1 shows the frequency spectrum of a PAL signal. The spectral lines or the components of the luminance (Y) signal are located at integral multiples of the line frequency f z and may extend into the frequency range of the chrominance subcarrier f o = 4.43 MHz. In the frequency range of the chrominance subcarrier the spectral lines or the components of the color difference signals U, V and the chrominance sub carrier component are grouped around the Y-components, every time shifted over one fourth of the line frequency. In commercial TV receivers a bandpass filter or a wavetrap in the chrominance subcarrier range is considered to be satisfactory for the separation of the last-mentioned components from the luminance signal and interference in color and in the finer picture details are taken into account at the boundaries of the pass and suppression regions.
In transcoding, for example, of a video signal in accordance with the PAL standard into a signal in accordance with the SECAM standard, small amplitude signals at these boundaries cause disturbing interference in the SECAM chrominance subcarrier(s).
A filter for filtering the luminance signal Y should thus have a characteristic as shown in FIG. 1b in which the ratio of the output voltage relative to the input voltage is given as a function of the frequency. Filters having such a characteristic in which the zero points occur periodically along the frequency axis are called comb filters. In this case generally a signal is applied directly and through a delay line to an adder or subtractor circuit. The output voltage of such a circuit is then dependent on the phase shift caused in the signal by the delay line: at a phase shift of 180° a minimum (maximum) occurs at the output of the adder circuit (subtractor circuit) while at a phase shift of 0° or 360° a maximum (minimum) occurs. If the delay period T of the delay line is chosen to be as large as one line period 1/f z , the luminance signal may also be passed on or cut off at the high frequencies, dependent on whether the delayed and the undelayed signal are added together or subtracted from each other. On the other hand, if one of the components U or V of the color difference signal is to be filtered, the delay period T must be longer. In that case the following equation must be satisfied 1/T = f z (1-e/n) wherein for PAL e = 0.25 and n = 284 (compare Telefunken Zeitung, Vol. 37 (1964) No. 2 pages 115-135).
Such comb filters have sometimes been used for separating the chrominance signal. However, a principal drawback of all these known circuits is the deterioration of the definition of the picture in the vertical direction. This will be explained in greater detail with reference to FIG. 2. It is assumed that the luminance from the end of a line u changes stepwise, that is to say, the Y-signal amplitude changes from, for example, 100 percent to 0. This luminance signal step at the input of the comb filter is shown in FIG. 2a as a function of the number of line periods. During the line n + 1 the undelayed Y-signal (Y in ) is 0; the delayed Y-signal has, however, still the value of 100 percent (from the previous line) so that after addition or subtraction of both the signals at the output of the comb filter a mean value near 50 percent of the previous output signal (Y out ) is produced (see FIG. 2b). Since in the PAL system the signal is to be partially delayed for two lines, a mean value is also produced during the line n + 2 and then only the output signal follows the input signal.A further drawback is that without additional steps the pass regions always have the shape of half a period of sine curve. However, the comb filter must have a very wide pass region for the Y-signal, as is shown in FIG. 1b, because the spectrum of the Y-signal in contrast with the spectrum of the chrominance signal and being different from that shown in FIG. 1a does not have sharp lines in the region of the chrominance sub-carrier. It is known from the said Article that the pass region may be formed in the desired manner by suitable feedback from the output of the comb filter to the input of the delay line. However, this causes the definition in the vertical direction to be still worse because the delayed signal is brought through the feedback to the input of the delay line again and this delay line continues again, although in a weaker form, so that the output signal of the comb filter cannot follow the step of the input signal during many line periods.In a known circuit arrangement (Internationale Elektronische Rundschau 1969, No. 8 particularly FIG. 5) this integrating action of the comb filter which deteriorates the definition in the vertical direction is obviated to a great extent in that the video signal and the color information is divided with the aid of a highpass and a lowpass filter, in which only the portion of high frequency containing the color information is passed on to the comb filter, while the low-frequency portion which does not contain color information is delayed for one line period and undergoes a vertical aperture correction. However, the vertical aperture correction involves high costs.
An object of the present invention is to obviate the mentioned drawbacks. Starting from a circuit arrangement for suppressing the color inf
ormation signal (F signal) present in a PAL color television signal (FBAS signal) by means of at least one comb filter which includes one delay line which delays the FBAS signal or the components of the FBAS signal located in the frequency range of the F signal by approximately the duration of the period of the line frequency, and adds the delayed signal to the undelayed signal or subtracts it therefrom and feeds back the sum or the difference to the input of the delay line, this object according to the invention is achieved in that at least the components of the FBAS signal located in the frequency range of the F signal are applied to the parallel-arranged inputs of two comb filters one of which adds the delayed signal to the undelayed signal, while the other subtracts the delayed signal from the undelayed signal, and in that the signals at the output of the comb filters are amplified by a given factor, added together and subtracted from the FBAS signal.In order that the invention may be readily carried into effect an embodiment thereof will now be described in detail by way of example with reference to the accompanying diagrammatic drawings, in which:
FIG. 3 shows a block diagram of a circuit arrangement according to the invention,
FIG. 4 shows the frequency characteristic of a transfer element used in the circuit arrangement of FIG. 3 for the total FBAS signal (4a), the frequency characteristic of the first comb filter (4b), the frequency characteristic of the second comb filter (4c) and the frequency characteristic at the output of a circuit arrangement according to FIG. 3 (4d).
FIG. 5 shows the variation with time of the output signal of the circuit arrangement of FIG. 3 when an input signal in accordance with FIG. 2a is changed.
In the circuit arrangement shown in FIG. 3 the video signal of a PAL color television signal including luminance and color information is applied to a bandpass filter 4 and to a delay line 5 whose delay period corresponds to the delay of the signals passing through the bandpass filter 4. The output of the delay line 5 is connected to a subtractor circuit 3. The bandpass filter 4 only passes those frequency components of the input signal which include color components and applies the signals filtered in this manner to the inputs of two comb filters 1 and 2 where output signals are amplified by amplifiers 6 and 7, respectively, added together and applied to the input of the subtractor circuit 3 where they are subtracted from the FBAS signal coming in through the delay element 5.The bandpass filter 4 renders the use of simple delay lines having a small bandwidth (2 MHz) possible and ensures that the integrating action of the comb filter for the Y signal also occurring to a slight extent in the circuit arrangement according to the invention only exerts influence on the signal components of high frequencies.
The comb filters are in principle formed identically. Each comb filter includes an adder stage 11 and an adder stage 21, respectively, which add the delayed and the undelayed signal. The resultant signal is fed back from the output of the adder stage by means of a feedback network 12 (22) to the input of a further adder circuit 13 (23). This further adder circuit adds the feed-back signal and the output signal of the bandpass filter 1 and applies its output signal to the input of the delay line 14 (24) which delay line delays the signal by a period of T, in which for a conventional PAL signal the relation 1/T = f z (1 - e/n) with e = 0.25 and n = 284 is satisfied, and wherein f z is the line frequency. In addition the amplified signal in the comb filter 2 is shifted 180° in phase by the inverter circuit 25 and is applied to the adder circuit 21. (A subtractor circuit may of course alternatively be used which then takes the place of the parts 21 and 25 and subtracts the delayed signal from the undelayed signal).
The comb filters described are known per se from the previously mentioned Article, particularly FIG. 27. Exclusively the components of a first color difference signal U (comb filter 2) and of a second color difference signal V (c
omb filter 1) present in the PAL signal appear at the output. Their action together with the rest of the circuit arrangement may be illustrated with reference to the frequency characteristics shown in FIG. 4.FIG. 4a illustrating the frequency characteristic of the delay element 5 shows that the total FBAS signal reaches the output of the subtractor circuit 3 in an unattenuated form. FIG. 4b and FIG. 4c show the frequency characteristics of the comb filters 2 and 1, respectively, which pass only the color difference signal components U and V, respectively, every time. The pass characteristics have sharper peaks as the positive feedback is larger. When the amplification of the amplifiers 6 and 7 is chosen to be such that the amplitude of the U and V components applied to the subtractor circuit has the same value as that of the U and V components in the FBAS signal, then they are compensated eminently in the signal at the output of the subtractor circuit 3 so that the total filter characteristic shown in FIG. 4d is produced.
Other properties of the circuit arrangement according to the invention are apparent from a quantitative analysis. The output voltage U 2 , in so far as it is located in the frequency range of the chrominance signal, can be calculated from
u 2 = u 1 - v 1 u s - v 2 u d (1)
In this case u 1 is the input voltage, u s and u d are the output voltages of the comb filters 1 and 2, respectively. The quantities u 1 , u 2 , u s and u d represent complex voltage amplitudes. The references v 1 and v 2 indicate the amplification factors of the amplifiers 6 and 7.
The voltages u s and u d in accordance with equations 21 and 22 of the previously mentioned Articles are as follows:
and
In these formulas k 1 and k 2 are the (positive) feedback factors (k 1 , K 2 < 1) of the feedback networks 12 and 22; w is the angular frequency. If the Equations 2 and 3 are substituted in the Equation 1 then this results in the following formula, provided that v 1 = v 2 = v and k 1 = k 2 = k:
If v is chosen to be such that in the Equation (4) the second term becomes 1 at a maximum (maximum values of this term occur as exp (-2jwT) = + 1), then the function value is zero, and in this case there must apply that
The zero values are located at the frequencies of the chrominance subcarriers, the U-components and the V-components for which there applies that 1/T = f z (1-e/n). After substitution of the Equation (5) in the Equation (4) and after some derivation this results in:
Equation (6) shows that for k = 0 the output voltage u 2 becomes 0. This is readily evident because the action of the delay line 14 is eliminated by that of the delay line 24 because subtraction is effected once and addition is effected once. This means that a feedback (k ≠ 0) is absolutely necessary.
The minimum zero values of the quotient u 2 /u 1 occur, as already shown, at exp (2-jwT) = + 1. The maximum values occur at exp (- 2jwT) = - 1. These values are located exactly in the middle between the minimum values and thus at the area of the components of the Y-signal. The maximum values are:
The maximum value for k = 0.7 has a value of for example 0.94. The Y-components of the output signal u 2 -- in so far as they are located in the frequency range of the chrominance signal -- thus have an amplitude which is 6 percent lower than the Y-components in the input signal u 1 or the low-frequency components of the Y-signal applied to the input of the subtractor circuit. This slight difference, which is the slighter as k is larger, may optionally be eliminated by an additional amplification of the high-frequency Y-components.
In case of a step of the Y (luminance) signal at the input of the circuit from 100 percent to 0, as is shown in FIG. 2a, the following takes place: the Y-signal provided through the delay element 5 or through the bandpass filter 4 occurs directly after the step 0 when the delay of the elements 4 and 5 is left out of consideration. The delay line 14 (24) acts, however, as a memory for the signal value present before the step. Since this value added to U 1 (or subtracted therefrom) yields u 2 (u d ) it must have the value u s + u 1 (u d + u 1 ). The signals provided by the delay lines 14 and 24 yield u s + u d after addition likewise as before the step. However since (for k = 0.7) the Y-component of the signals coming through the comb filters reduces the Y-component of the signal u 1 by only 6 percent, this small component of the Y-signal only appears at the input and -- because no signal is provided anymore through the amplifier element 5 -- at the out
put of the subtractor device. As a result of the feedback to the inputs of the delay lines 14 and 24, a signal attenuated by the feedback factor k is produced at the end of the line period, which signal is further attenuated at the end of the next line. The signal values occurring at the output of the subtractor circuits are, however, so small that they are not disturbing.The circuit reacts in the same manner in case of one of the vertical color steps which occur rarely. Since the U and V components coming through the delay line have a large amplitude (100 percent of the U and V components present in the signal u 1 ) a severe color distortion might be produced at the outputs. This distortion may be prevented in known manner (compare the Internationale Elektronische Rundschau 1969, No. 8, page 199, FIG. S) by a chrominance subcarrier suppression circuit not further shown in the drawing. Such a chrominance subcarrier suppression circuit suppresses the greater part of the energy present in the chrominance signal in a limited region around the chrominance subcarrier.
PHILIPS 12B711 /00 TRIXI CHASSIS TX B-W TELEVISION DIAGRAM AND DEFLECTION CIRCUIT:
A
unidirectional conductive device is coupled from a base terminal to a
collector terminal of a horizontal deflection output transistor in a
television receiver and poled in a direction to prevent the transistor
from saturating when it is driven into its conductive state during a
portion of each deflection cycle. Biasing means is coupled to the diode
to preselect the desired operating voltage of the transistor during
its conduction period.
1.
In a television receiver, a deflection circuit comprising:
2. A circuit as defined in claim 1 wherein
said transformer is an auto-transformer and said second terminal is
intermediate said first and 3. In
a television receiver, a deflection circuit comprising:
Description:
The present invention relates to transistorized deflection circuits utilized in television receivers.
In present day transistor deflection circuits, for example, those used in the horizontal output stage of a television receiver; the output transistor is normally operated in a switching mode, that is, the transistor is driven into saturation during a trace interval of each deflection cycle and driven out of conduction during the retrace portion of each deflection cycle. By operating the transistor in its saturation region, average power losses are minimized. With saturated operation, however, the accumulation of minority carriers in the base region will effect a continuation in the flow of collector current after the trace interval during the initial portion of the retrace interval while the transistor is being driven into its non-conducting state. In addition to causing this undesirable delay time in turning off the transistor, losses occurring during this period may be localized in small areas commonly referred to as "hot spots." These losses are characterized in being regenerative and tend to cause second breakdown of the device. This effect is explained in greater detail in a paper authored by the present inventor and entitled "Thermal Regeneration in Power Dissipating Elements" which appeared in "The Electronic Engineer" publication in the January 1967 issue. Although operating the horizontal output transistor in its saturated region may reduce the average power dissipated in this device during its conduction interval, it increases the possibility of second breakdown during the turn-off time. With the advent of high voltage (1,500 volts) transistors, it is possible to develop the necessary output energy utilizing one of these transistors which can be operated in a non-saturated mode. The circuit of the present invention insures that the deflection output transistor will not be driven into saturation.
Certain
low power transistor switching circuits, such as employed in computer
applications, have utilized diodes in conjunction with resistive
biasing means coupled between the base and collector terminals to
prevent the transistor from saturating and thereby increase the maximum
switching frequency of the circuit by reducing the turn-off time of
the device.
In the solid state deflection art, however, it is desirable to reduce the turn-off time of the device not to increase the frequency of operation of the circuit, but rather to prevent second breakdown of the device as the relatively large inductive voltage pulse appears during the initial portion of the flyback interval, when current flowing through the deflection winding is interrupted to initiate the retrace portion of each deflection cycle.
The non-saturated operation of the deflection output transistor is achieved in circuits embodying the present invention by automatically holding the collector voltage above the saturation level by shunting excess base drive from the base to emitter junction into the collector circuit. Prior transistor deflection systems employ only the saturated operation of the deflection output device.
Circuits embodying the present invention include a deflection output transistor having a diode coupled between its base and collector terminals and poled to prevent the transistor from being driven into saturation during its conduction period of each deflection cycle.
The invention can be more fully understood by referring to the drawings together with the description below and the accompanying claims.
In the drawings:
FIG. 1 illustrates in block and schematic diagram form, a television receiver including a solid state deflection output stage embodying the present invention;
FIG. 2a is a waveform diagram of the voltage present at the collector terminal 55c of transistor 55 in FIG. 1;
FIG. 2b shows the drive current to terminal A in FIG. 1;
FIG. 2c is a waveform diagram of the current in diode 56 in FIG. 1;
FIG. 2d is a waveform diagram of the base current flowing in transistor 55 of FIG. 1;
FIG. 3 is a schematic diagram of an alternative embodiment of the present invention;
FIG. 4a is a waveform diagram of the voltage appearing at the terminal 366 in FIG. 3;
FIG. 4b is a waveform diagram of the drive current to terminal A in FIG. 3;
FIG. 4c is a waveform diagram of the current in diode 356 in FIG. 3; and
FIG. 4d is a waveform diagram of the base drive current to transistor 355 in FIG. 3.
Referring specifically to FIG. 1,an
antenna 10 receives television signals and couples these signals to a
tuner 12 which selects the desired radio frequency signals of a
predetermined broadcast channel, amplifies these signals, and converts
the amplified radio frequency signals to a lower intermediate
frequency (I.F.). The tuner 12 is coupled to an I.F. amplifier 14
which amplifies the intermediate frequency signals. The I.F. amplifier
14 is coupled to a video detector 16 which derives video information
from the I.F. signals. The video detector 16 is coupled to a video
driver stage 18 which amplifies the video signals. The video driver
stage 18 is coupled to a video output stage 20, an automatic gain
control stage 25 and a synchronizing separator stage 42. An output
signal from video driver stage 18 may also be coupled to a sound
channel (not shown) to reproduce the audio portion of the transmitted
television program. The video output stage 20 couples amplified video
information to a control element, such as a cathode 28, of a kinescope
30.
The automatic gain control stage 25 operates in a
conventional manner to provide gain control signals which are applied
to a radio frequency amplifier included in tuner 12 and to the I.F.
amplifier 14. Sync separator 42 separates the synchronization
information from the video information and also separates the
horizontal synchronizing information for the vertical synchronizing
information. The vertical synchronizing pulses derived from sync
separator 42 are applied to the vertical deflection system 44 which
provides the required deflection current to a vertical deflection
winding 43 associated with kinescope 30 by means of the
interconnection Y--Y. The horizontal synchronizing pulses from sync
separator 42 are applied to an automatic frequency control detector 45
which serves to synchronize a horizontal oscillator 46 with the
horizontal synchronizing pulses. The horizontal oscillator stage 46 is
coupled to a horizontal driver stage 48 which develops the required
drive signal and may be coupled by means of an output transformer in
stage 48 (not shown) to a transistorized horizontal output stage 50.
The transformer secondary, coupled to terminal A, provides a direct current path for the drive current.
The horizontal output stage 50 includes an output transistor 55 having a base, a collector and an emitter terminal 55b, 55c and 55e, respectively. A resistor 52 and a capacitor 53 are coupled in parallel between the horizontal driver stage 48 and the base terminal 55b of transistor 55.
The output stage includes a unidirectional conductive device such as a diode 56 coupled between the base and collector terminals 55b and 55c of transistor 55. Stage 50 also includes a damper diode 57 coupled across transistor 55, a retrace capacitor 58 coupled across transistor 55 and the series combination of a horizontal deflection winding 59 and an S-shaping capacitor 60 also coupled across transistor 55. Output stage 50 also includes a flyback transformer 61 with a primary winding 61p coupled from a source of operating potential (B+) to the collector terminal 55c of transistor 55. A secondary winding 61s on transformer 61 develops high voltage pulses which are coupled to a high voltage rectifier 63 to provide the ultor voltage for application to a terminal 32 on kinescope 30. Flyback transformer 61 may also include additional windings (not shown) for providing, for example, keying pulses to the AGC stage 25.
The output stage 50 in FIG. 1 is a conventional shunt fed trace driven circuit with the exception of the diode 56 and the bias network including resistor 52 and capacitor 53. Beginning at the center of the trace interval of the deflection cycle, the yoke current is zero and capacitor 60 has a maximum charge. The drive signal applied to the base terminal 55b of transistor 55 turns this device on, thereby completing the conduction path for yoke current which includes capacitor 60, yoke 59 and the collector to emitter current path through transistor 55. During this portion of scan the yoke current is supplied by the charge on capacitor 60 and increases to a maximum value in one direction at which time scan retrace is initiated by driving transistor 55 out of conduction by applying an appropriate signal from the driver stage 48 to the base 55b of transistor 55. During the latter portion of the trace interval when the magnitude of the yoke current is increasing, the output transistor of prior circuits is normally driven into saturation and is in this conduction state at the instant retrace is initiated. During the first portion of retrace, the yoke current is at a maximum and resonates with the retrace capacitor 58 by charging capacitor 58 in a polarity to reverse bias the damper diode 57. As the yoke current decreases to zero, capacitor 58 has a maximum charge impressed upon it; and during the second portion of retrace, the capacitor (58) drives current through the yoke in a reverse direction until it is discharged and the voltage across it reverses sufficiently to forward bias damper diode 57. Diode 57 then conducts during this first portion of trace to complete the current path for yoke current which is, at this instant, at a maximum value in a direction in yoke 59 to charge capacitor 60 and is increasing toward zero. At the mid-point of trace the yoke current has reached zero and the cycle is completed by driving transistor 55 into conduction once again.
Turning now to the operation of the circuitry of FIG. 1 including the present invention, reference is made to the waveform diagrams of FIG. 2. The initial portion of trace is represented in FIG. 2 by the time period between t 0 and t 1 in the figure. It is recalled that during this period damper diode 57 is conducting. The voltage at collector terminal 55c of transistor 55 is represented by the voltage waveform (V c ) in FIG. 2a and is equal to the forward voltage drop across diode 57 which is of the order of -0.7 volts. At some non-critical time before t 1 , the horizontal driver 48 provides a drive current (I A ), as is shown in FIG. 2b. This current flows through diode 56 as is illustrated in FIG. 2c, since the diode is forward biased. [The cathode of diode 56 is at the same voltage as collector terminal 55c (-0.07 volts) and the drive current produces a positive voltage at point A which is at the anode of diode 56.] As time t 1 (the center of trace) is reached, damper diode 57 turns off allowing the collector voltage on transistor 55 to increase as shown in FIG. 2a. At the same time, a portion of the drive current flowing into terminal A is conducted by the now forward biased base to emitter junction of transistor 55 as is illustrated by the waveform of FIG. 2d. Transistor 55 is now conducting the increasing yoke current during the latter portion of scan represented by the period from t 1 to t 2 in FIG. 2. As the magnitude of the yoke current increases during the t 1 to t 2 interval, the base current in transistor 55 increases as shown in FIG. 2d. Diode 56 conducts as illustrated in FIG. 2c to shunt the remaining portion of the applied drive current at terminal A. It is noted that the sum of the currents shown in FIGS. 2c and 2d will equal the current shown in FIG. 2b. T
he
values of resistor 52 and capacitor 53 can be selected to hold the
transistor collector voltage at a preselected value sufficient to
prevent saturation of the transistor 55. If, for example, the voltage
across capacitor 53 is 5.3 volts, the voltage at terminal A with
respect to ground will be approximately 6 volts (5.3 volts plus the
forward voltage drop across the base-emitter junction of transistor
55). The collector voltage will then be approximately equal to the
voltage at terminal A less the forward voltage drop across diode 56. It
is desirable to choose values of resistor 52 and capacitor 53 to
operate transistor 55 near but not into the saturation region of
conduction during the latter portion of each trace interval.
At time t 2 retrace is initiated by applying a relatively large negative drive signal as shown in FIG. 2b to the base terminal of transistor 55. During the retrace interval (t 2 to t 0 in FIG. 2), the collector voltage increases in a typical manner as illustrated in FIG. 2a. At time t 0 the cycle is again repeated.
The circuit modification illustrated in FIG. 3 is another embodiment of the invention which reduces the change in voltage applied to the yoke 59 of FIG. 1 at time t 1 . As shown in FIG. 2a, when diode 57 turns off and transistor 55 conducts, the voltage at the collector terminal 55c of transistor 55 changes by as much, for example, as 6 volts. This voltage change, which is coupled to the yoke 59, will vary the rate of change of yoke current during the center of trace and may, in certain circuits, cause an undesirable non-linearity in the scanning rate. As FIG. 4a illustrates, the circuit of FIG. 3 reduces this change in voltage at the mid-point of trace (t 1 ).
Referring
to FIG. 3, the circuit elements which correspond to those of FIG. 1
are prefaced by the numeral 3. In explaining FIG. 3, it is helpful to
refer to the waveform diagrams of FIG. 4. Transformer 364 in FIG. 3 is a
tightly coupled auto-transformer wherein the tap point 365 may be,
for example, at the 5 percent point on the transformer.
That is, the segment between terminals 365 and 366 contain 5 percent
of the total number of windings on transformer 364. Transformer 364
may also include a secondary winding such as the high voltage winding
which is not shown in the figure. In operation, as drive current is
applied at sometime prior to t 1 as is shown in FIG. 4b,
damper diode 357 is conducting and the voltage at terminal 366 is
therefore at approximately -0.7 volts. Drive current flowing into
terminal A as represented in FIG. 4b will be conducted by diode 356
during this interval as indicated by the diode current waveform in
FIG. 4c. At the middle portion of trace (t 1 ), the damper
diode turns off and voltage at terminal 366 is thereby allowed to go
slightly positive (less than 0.7 volts). The collector voltage of
transistor 355 is held at a value of approximately 5 volts (assuming,
for example, the B+ voltage is equal to 100 volts and the collector is
coupled to the tap 365 on transformer 364 at a 5 percent point). At
this instant, the base to emitter junction will be forward biased and
transistor 355 conducts. It is seen that the anode voltage of diode
356 is at approximately +0.7 volts and its cathode which is coupled to
terminal 366 is at a less positive voltage. Diode 356 begins to
conduct during the latter portion of trace as illustrated by the
current waveform diagram shown in FIG. 4c.
During the latter portion of trace, the transistor tends to saturate and the collector voltage at terminal 355c tends to decrease. As this occurs, more current will flow from the B+ terminal through the upper portion of transformer 364. Due to the relatively tight coupling of the segments of transformer 364, terminal 366 experiences a decrease in voltage which controls the forward bias applied to diode 356 to shunt sufficient drive current to hold the transistor 355 out of saturation. The collector voltage of transistor 355 is thus held at some preselected value depending on the location of tap point 365 on transformer 364. Since transformer 364 is utilized, terminal 366 will
remain at a low voltage during the latter portion of trace as shown
in FIG. 4a, and diode 356 will be forward biased during the
application of a positive drive signal to terminal A. As before, the
base drive current will increase and diode 356 conduction will
decrease generally as shown in FIGS. 4c and 4d during the latter
portion of trace. At time t 2 in FIG. 4, a negative drive pulse is applied to the circuit which initiates the retrace interval of the deflection cycle.
Although the specific embodiments of the invention are illustrated in the horizontal deflection output stage of a black and white television receiver, the invention has equal applicability to other deflection systems and may be utilized in a color television receiver.
In present day transistor deflection circuits, for example, those used in the horizontal output stage of a television receiver; the output transistor is normally operated in a switching mode, that is, the transistor is driven into saturation during a trace interval of each deflection cycle and driven out of conduction during the retrace portion of each deflection cycle. By operating the transistor in its saturation region, average power losses are minimized. With saturated operation, however, the accumulation of minority carriers in the base region will effect a continuation in the flow of collector current after the trace interval during the initial portion of the retrace interval while the transistor is being driven into its non-conducting state. In addition to causing this undesirable delay time in turning off the transistor, losses occurring during this period may be localized in small areas commonly referred to as "hot spots." These losses are characterized in being regenerative and tend to cause second breakdown of the device. This effect is explained in greater detail in a paper authored by the present inventor and entitled "Thermal Regeneration in Power Dissipating Elements" which appeared in "The Electronic Engineer" publication in the January 1967 issue. Although operating the horizontal output transistor in its saturated region may reduce the average power dissipated in this device during its conduction interval, it increases the possibility of second breakdown during the turn-off time. With the advent of high voltage (1,500 volts) transistors, it is possible to develop the necessary output energy utilizing one of these transistors which can be operated in a non-saturated mode. The circuit of the present invention insures that the deflection output transistor will not be driven into saturation.
Certain
low power transistor switching circuits, such as employed in computer
applications, have utilized diodes in conjunction with resistive
biasing means coupled between the base and collector terminals to
prevent the transistor from saturating and thereby increase the maximum
switching frequency of the circuit by reducing the turn-off time of
the device.In the solid state deflection art, however, it is desirable to reduce the turn-off time of the device not to increase the frequency of operation of the circuit, but rather to prevent second breakdown of the device as the relatively large inductive voltage pulse appears during the initial portion of the flyback interval, when current flowing through the deflection winding is interrupted to initiate the retrace portion of each deflection cycle.
The non-saturated operation of the deflection output transistor is achieved in circuits embodying the present invention by automatically holding the collector voltage above the saturation level by shunting excess base drive from the base to emitter junction into the collector circuit. Prior transistor deflection systems employ only the saturated operation of the deflection output device.
Circuits embodying the present invention include a deflection output transistor having a diode coupled between its base and collector terminals and poled to prevent the transistor from being driven into saturation during its conduction period of each deflection cycle.
The invention can be more fully understood by referring to the drawings together with the description below and the accompanying claims.
In the drawings:
FIG. 1 illustrates in block and schematic diagram form, a television receiver including a solid state deflection output stage embodying the present invention;
FIG. 2a is a waveform diagram of the voltage present at the collector terminal 55c of transistor 55 in FIG. 1;
FIG. 2b shows the drive current to terminal A in FIG. 1;
FIG. 2c is a waveform diagram of the current in diode 56 in FIG. 1;
FIG. 2d is a waveform diagram of the base current flowing in transistor 55 of FIG. 1;
FIG. 3 is a schematic diagram of an alternative embodiment of the present invention;
FIG. 4a is a waveform diagram of the voltage appearing at the terminal 366 in FIG. 3;
FIG. 4b is a waveform diagram of the drive current to terminal A in FIG. 3;
FIG. 4c is a waveform diagram of the current in diode 356 in FIG. 3; and
FIG. 4d is a waveform diagram of the base drive current to transistor 355 in FIG. 3.
Referring specifically to FIG. 1,
an
antenna 10 receives television signals and couples these signals to a
tuner 12 which selects the desired radio frequency signals of a
predetermined broadcast channel, amplifies these signals, and converts
the amplified radio frequency signals to a lower intermediate
frequency (I.F.). The tuner 12 is coupled to an I.F. amplifier 14
which amplifies the intermediate frequency signals. The I.F. amplifier
14 is coupled to a video detector 16 which derives video information
from the I.F. signals. The video detector 16 is coupled to a video
driver stage 18 which amplifies the video signals. The video driver
stage 18 is coupled to a video output stage 20, an automatic gain
control stage 25 and a synchronizing separator stage 42. An output
signal from video driver stage 18 may also be coupled to a sound
channel (not shown) to reproduce the audio portion of the transmitted
television program. The video output stage 20 couples amplified video
information to a control element, such as a cathode 28, of a kinescope
30.The automatic gain control stage 25 operates in a
conventional manner to provide gain control signals which are applied
to a radio frequency amplifier included in tuner 12 and to the I.F.
amplifier 14. Sync separator 42 separates the synchronization
information from the video information and also separates the
horizontal synchronizing information for the vertical synchronizing
information. The vertical synchronizing pulses derived from sync
separator 42 are applied to the vertical deflection system 44 which
provides the required deflection current to a vertical deflection
winding 43 associated with kinescope 30 by means of the
interconnection Y--Y. The horizontal synchronizing pulses from sync
separator 42 are applied to an automatic frequency control detector 45
which serves to synchronize a horizontal oscillator 46 with the
horizontal synchronizing pulses. The horizontal oscillator stage 46 is
coupled to a horizontal driver stage 48 which develops the required
drive signal and may be coupled by means of an output transformer in
stage 48 (not shown) to a transistorized horizontal output stage 50.
The transformer secondary, coupled to terminal A, provides a direct current path for the drive current.
The horizontal output stage 50 includes an output transistor 55 having a base, a collector and an emitter terminal 55b, 55c and 55e, respectively. A resistor 52 and a capacitor 53 are coupled in parallel between the horizontal driver stage 48 and the base terminal 55b of transistor 55.
The output stage includes a unidirectional conductive device such as a diode 56 coupled between the base and collector terminals 55b and 55c of transistor 55. Stage 50 also includes a damper diode 57 coupled across transistor 55, a retrace capacitor 58 coupled across transistor 55 and the series combination of a horizontal deflection winding 59 and an S-shaping capacitor 60 also coupled across transistor 55. Output stage 50 also includes a flyback transformer 61 with a primary winding 61p coupled from a source of operating potential (B+) to the collector terminal 55c of transistor 55. A secondary winding 61s on transformer 61 develops high voltage pulses which are coupled to a high voltage rectifier 63 to provide the ultor voltage for application to a terminal 32 on kinescope 30. Flyback transformer 61 may also include additional windings (not shown) for providing, for example, keying pulses to the AGC stage 25.
The output stage 50 in FIG. 1 is a conventional shunt fed trace driven circuit with the exception of the diode 56 and the bias network including resistor 52 and capacitor 53. Beginning at the center of the trace interval of the deflection cycle, the yoke current is zero and capacitor 60 has a maximum charge. The drive signal applied to the base terminal 55b of transistor 55 turns this device on, thereby completing the conduction path for yoke current which includes capacitor 60, yoke 59 and the collector to emitter current path through transistor 55. During this portion of scan the yoke current is supplied by the charge on capacitor 60 and increases to a maximum value in one direction at which time scan retrace is initiated by driving transistor 55 out of conduction by applying an appropriate signal from the driver stage 48 to the base 55b of transistor 55. During the latter portion of the trace interval when the magnitude of the yoke current is increasing, the output transistor of prior circuits is normally driven into saturation and is in this conduction state at the instant retrace is initiated. During the first portion of retrace, the yoke current is at a maximum and resonates with the retrace capacitor 58 by charging capacitor 58 in a polarity to reverse bias the damper diode 57. As the yoke current decreases to zero, capacitor 58 has a maximum charge impressed upon it; and during the second portion of retrace, the capacitor (58) drives current through the yoke in a reverse direction until it is discharged and the voltage across it reverses sufficiently to forward bias damper diode 57. Diode 57 then conducts during this first portion of trace to complete the current path for yoke current which is, at this instant, at a maximum value in a direction in yoke 59 to charge capacitor 60 and is increasing toward zero. At the mid-point of trace the yoke current has reached zero and the cycle is completed by driving transistor 55 into conduction once again.
Turning now to the operation of the circuitry of FIG. 1 including the present invention, reference is made to the waveform diagrams of FIG. 2. The initial portion of trace is represented in FIG. 2 by the time period between t 0 and t 1 in the figure. It is recalled that during this period damper diode 57 is conducting. The voltage at collector terminal 55c of transistor 55 is represented by the voltage waveform (V c ) in FIG. 2a and is equal to the forward voltage drop across diode 57 which is of the order of -0.7 volts. At some non-critical time before t 1 , the horizontal driver 48 provides a drive current (I A ), as is shown in FIG. 2b. This current flows through diode 56 as is illustrated in FIG. 2c, since the diode is forward biased. [The cathode of diode 56 is at the same voltage as collector terminal 55c (-0.07 volts) and the drive current produces a positive voltage at point A which is at the anode of diode 56.] As time t 1 (the center of trace) is reached, damper diode 57 turns off allowing the collector voltage on transistor 55 to increase as shown in FIG. 2a. At the same time, a portion of the drive current flowing into terminal A is conducted by the now forward biased base to emitter junction of transistor 55 as is illustrated by the waveform of FIG. 2d. Transistor 55 is now conducting the increasing yoke current during the latter portion of scan represented by the period from t 1 to t 2 in FIG. 2. As the magnitude of the yoke current increases during the t 1 to t 2 interval, the base current in transistor 55 increases as shown in FIG. 2d. Diode 56 conducts as illustrated in FIG. 2c to shunt the remaining portion of the applied drive current at terminal A. It is noted that the sum of the currents shown in FIGS. 2c and 2d will equal the current shown in FIG. 2b. T
he
values of resistor 52 and capacitor 53 can be selected to hold the
transistor collector voltage at a preselected value sufficient to
prevent saturation of the transistor 55. If, for example, the voltage
across capacitor 53 is 5.3 volts, the voltage at terminal A with
respect to ground will be approximately 6 volts (5.3 volts plus the
forward voltage drop across the base-emitter junction of transistor
55). The collector voltage will then be approximately equal to the
voltage at terminal A less the forward voltage drop across diode 56. It
is desirable to choose values of resistor 52 and capacitor 53 to
operate transistor 55 near but not into the saturation region of
conduction during the latter portion of each trace interval.At time t 2 retrace is initiated by applying a relatively large negative drive signal as shown in FIG. 2b to the base terminal of transistor 55. During the retrace interval (t 2 to t 0 in FIG. 2), the collector voltage increases in a typical manner as illustrated in FIG. 2a. At time t 0 the cycle is again repeated.
The circuit modification illustrated in FIG. 3 is another embodiment of the invention which reduces the change in voltage applied to the yoke 59 of FIG. 1 at time t 1 . As shown in FIG. 2a, when diode 57 turns off and transistor 55 conducts, the voltage at the collector terminal 55c of transistor 55 changes by as much, for example, as 6 volts. This voltage change, which is coupled to the yoke 59, will vary the rate of change of yoke current during the center of trace and may, in certain circuits, cause an undesirable non-linearity in the scanning rate. As FIG. 4a illustrates, the circuit of FIG. 3 reduces this change in voltage at the mid-point of trace (t 1 ).
Referring
to FIG. 3, the circuit elements which correspond to those of FIG. 1
are prefaced by the numeral 3. In explaining FIG. 3, it is helpful to
refer to the waveform diagrams of FIG. 4. Transformer 364 in FIG. 3 is a
tightly coupled auto-transformer wherein the tap point 365 may be,
for example, at the 5 percent point on the transformer.
That is, the segment between terminals 365 and 366 contain 5 percent
of the total number of windings on transformer 364. Transformer 364
may also include a secondary winding such as the high voltage winding
which is not shown in the figure. In operation, as drive current is
applied at sometime prior to t 1 as is shown in FIG. 4b,
damper diode 357 is conducting and the voltage at terminal 366 is
therefore at approximately -0.7 volts. Drive current flowing into
terminal A as represented in FIG. 4b will be conducted by diode 356
during this interval as indicated by the diode current waveform in
FIG. 4c. At the middle portion of trace (t 1 ), the damper
diode turns off and voltage at terminal 366 is thereby allowed to go
slightly positive (less than 0.7 volts). The collector voltage of
transistor 355 is held at a value of approximately 5 volts (assuming,
for example, the B+ voltage is equal to 100 volts and the collector is
coupled to the tap 365 on transformer 364 at a 5 percent point). At
this instant, the base to emitter junction will be forward biased and
transistor 355 conducts. It is seen that the anode voltage of diode
356 is at approximately +0.7 volts and its cathode which is coupled to
terminal 366 is at a less positive voltage. Diode 356 begins to
conduct during the latter portion of trace as illustrated by the
current waveform diagram shown in FIG. 4c.During the latter portion of trace, the transistor tends to saturate and the collector voltage at terminal 355c tends to decrease. As this occurs, more current will flow from the B+ terminal through the upper portion of transformer 364. Due to the relatively tight coupling of the segments of transformer 364, terminal 366 experiences a decrease in voltage which controls the forward bias applied to diode 356 to shunt sufficient drive current to hold the transistor 355 out of saturation. The collector voltage of transistor 355 is thus held at some preselected value depending on the location of tap point 365 on transformer 364. Since transformer 364 is utilized, terminal 366 wil
l
remain at a low voltage during the latter portion of trace as shown
in FIG. 4a, and diode 356 will be forward biased during the
application of a positive drive signal to terminal A. As before, the
base drive current will increase and diode 356 conduction will
decrease generally as shown in FIGS. 4c and 4d during the latter
portion of trace. At time t 2 in FIG. 4, a negative drive pulse is applied to the circuit which initiates the retrace interval of the deflection cycle.Although the specific embodiments of the invention are illustrated in the horizontal deflection output stage of a black and white television receiver, the invention has equal applicability to other deflection systems and may be utilized in a color television receiver.
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