SAMSUNG MOD:CZ-6844W CHASSIS KS3A INTERNAL VIEW.

The SAMSUNG DIGITAL CHASSIS KS3A was first featuring the DIGIT 3000 CHIPSET from ITT/Micronas, allowing the developing of a DIGITAL Color TV CHASSIS with high integration level.

This chassis was fitted in various models even with bigger and more bigger screen formats and types.

This chassi was suffering by a high rate of dry joint landing to Line deflection and frame deflection varying faults.

The Frame IC output stage was running hot by design and was sometime a nightmare to repair in a reliable way.

The chassis is controlled by a PHILIPS UC for all functions.

All based architeture on ITT/MICRONAS DIGIT3000 CHIPSET: An embodiment of a digital television chip for converting analog signals into digital signals is provided. The digital television receives a VGA/YPbPr signal, a couple of S-video signals SY and SC, a couple of Tuner CVBS signals VIF and SIF and a CVBS Line-in Video signal. The digital television chip comprises a multiplexer, a first converting unit and a second converting unit.
The multiplexer receives the S-video signals SY and SC, the Tuner CVBS signals VIF and SIF and the CVBS Line-in Video signal. Besides, the multiplexer, according to a control signal, outputs one of the S-video signals SY and SC to the first converting unit, outputs the other of the S-video signals SY and SC to the second converting unit, outputs one of the Tuner CVBS signals VIF and SIF to the first converting unit, outputs the other of the Tuner CVBS signals VIF and SIF to the second converting unit, or outputs the CVBS Line-in Video signal to one of the first and second converting units.
The first converting unit converts one of the S-video signals SY and SC, one of the Tuner CVBS signals VIF and SIF, or the CVBS Line-in Video signal into a first digital signal for signal processing. The second converting unit converts unit converting one of the S-video signals SY and SC, one of the Tuner CVBS signals VIF and SIF, or the CVBS Line-in Video signal into a second digital signal for signal processing.
Another embodiment of a digital television system is provided. The digital television system comprises a display for displaying images and a digital television chip for converting analog signals into the digital signals. The digital television chip receives a VGA/YPbPr signal, a couple of S-video signals SY and SC, a couple of Tuner CVBS signals VIF and SIF and a CVBS Line-in Video signal. The digital television chip comprises a multiplexer, a first converting unit and a second converting unit.
The multiplexer receives the S-video signals SY and SC, the Tuner CVBS signals VIF and SIF and the CVBS Line-in Video signal. Besides, the multiplexer, according to a control signal, outputs one of the S-video signals SY and SC to the first converting unit, outputs the other of the S-video signals SY and SC to the second converting unit, outputs one of the Tuner CVBS signals VIF and SIF to the first converting unit, outputs the other of the Tuner CVBS signals VIF and SIF to the second converting unit, or outputs the CVBS Line-in Video signal to one of the first and second converting units.
The first converting unit converts one of the S-video signals SY and SC, one of the Tuner CVBS signals VIF and SIF, or the CVBS Line-in Video signal into a first digital signal for signal processing. The second converting unit converts one of the S-video signals SY and SC, one of the Tuner CVBS signals VIF and SIF, or the CVBS Line-in Video signal into a second digital signal for signal processing.
Another embodiment of a layout size reduction method by sharing converting units for a digital television chip is provided. The method comprises using a multiplexer to receive a couple of S-video signals SY and SC, a couple of Tuner CVBS signals VIF and SIF and a CVBS Line-in Video signal, outputting one of the S-video signals SY and SC, one of the Tuner CVBS signals VIF and SIF, or the CVBS Line-in Video signal to a first converting unit according to a control signal, and outputting the other of the S-video signals SY and SC, the other of the Tuner CVBS signals VIF and SIF, or the CVBS Line-in Video signal to a second converting unit according to the control signal.


SAMSUNG MOD:CZ-6844W CHASSIS KS3A  CIRCUITS DESCRIPTIONS:


Colour television receivers or sets are known in which the majority of signal processing that takes place therein is carried out digitally. That is, a video or television signal is received in a conventional fashion using a known analog tuning circuit and then, following the tuning operation, the received analog television signal is converted into a digital signal and digitally processed before subsequently being converted back to an analog signal for display on a colour cathode ray tube.
A colour television set of the above kind is described in an article by Thomas Fischer entitled "Schaltungtechnik eines Fernsehgeraetes mit DIGIVISION (Circuitry of a television set with DIGIVISION) appearing at pages 189 and 190 of FUNK-TECHNIK, Vol. 38, No. 5, 1983, Munich, Heidelberg. The set described in the article comprises a central control unit (CCU) which supplies control and setting values, for example of loudness, colour saturation or frame height, to digital audio and video signal processors. The central control unit comprises a microcomputer; and a non-volatile memory which is programmed during production of the set with balance values for the chassis and in which the user can store (by way of a keyboard or remote control commander) desired setting values and desired channels.
Although digital signal processing has many advantages over conventional analog signal processing, one problem that is presented by digital signal processing relates to the state of the circuitry at the time immediately following the manufacture of the television set or receiver or following servicing of the set by a repair technician. Although conventional analog components and signal processing elements can be set easily to an appropriate value, such as a midpoint of a range, at the time of manufacture, and such values will be held until adjusted later, digital circuits employing memory units, registers, and so forth do not have any initial settings and, indeed, cannot be set initially in the absence of some sort of digital pre-programming source. Examples of some of the various parameters that may be preset in the digital circuitry of a colour television receiver are contrast, brightness, hue, colour saturation degree, white balance and, perhaps most importantly, horizontal and vertical deflections. The problem arises that if the television receiver is turned on before appropriate initial values are set for the above-identified parameters, it is quite possible that random or zero values present in the digital memories may be abnormal and outside of tolerable limits. Such abnormal values then would cause adverse influence on appropriate circuit portions. For example, were the horizontal and vertical amplitudes increased or horizontal and vertical oscillation frequencies decreased drastically, there is a good likelihood that the horizontal or vertical output circuits will be destroyed.

According to the invention, there is provided, control apparatus for controlling the operation of a television receiver that processes a television signal in digital form under the control of digital data stored in at least one register of the receiver, the control apparatus comprising:
  first memory means in the television receiver for storing control data representing display parameters to be set in the at least one register on turning on the television receiver for controlling the television receiver, said control data comprising standard data values input during an adjusting mode and offset data; and
  second memory means in the television receiver, the second memory means being non-volatile and non-rewritable;
  characterised by:
  the second memory means containing, prior to the television receiver being turned on for the first time, predetermined initial control data representing initial display parameters for the receiver; and
  control means in the television receiver connected to the first and second memory means and operable when the television receiver is turned on for the first time, in said adjusting mode, to cause the predetermined initial control data from the second memory means to be set in the at least one register instead of said control data from said first memory means.
The invention also provides a method of operating a television receiver that processes a television signal in digital form under the control of digital data stored in a register of the receiver and includes an adjusting controller, the method comprising the steps of:
  providing first memory means in the television receiver for storing control data representing display parameters to be set in the at least one register on turning on the television receiver for controlling the television receiver, said control data comprising standard data values input during an adjusting mode and offset data; and
  providing second memory means in the television receiver, the second memory means being non-volatile and non-rewritable;
  characterised by:
  the second memory means containing, prior to the television receiver being turned on for the first time, predetermined initial control data representing initial display parameters for the receiver; and
determining whether the television receiver is in said adjusting mode and, when the television receiver is determined to be in said adjusting mode, for the first time the television receiver is turned on, causing the predetermined initial control data from the second non-volatile memory means to be set in the at least one register instead of said control data from said first memory means.

The use of such stored predetermined initialisation or initial control data can eliminate or at least alleviate the above-noted defects. Specifically, it can prevent circuit portions of the receiver from having undue signal levels and/or frequencies impressed thereon as a result of abnormal initial settings.
Preferably, memory units associated with one or more microcomputers utilised as part of the receiver are provided to accommodate the desired initial control data.

Preferably, the initial control data is selected statistically to be average data and such data is entered at the very first time a power switch of the television receiver is turned on. Such specific data initialisation also can occur following a servicing operation on the receiver.


Fairchild Power Switch (FPS) KA3S1265R:

Description
The Fairchild Power Switch(FPS) product family is specially
designed for an off line SMPS with minimal external
components. The Fairchild Power Switch(FPS) consist of
high voltage power SenseFET and current mode PWM IC.
Included control IC features a trimmed oscillator, under
voltage lock-out, leading edge blanking, optimized gate
turn-on/turn-off driver, thermal shut down protection, over
voltage protection, temperature compensated precision
current sources for loop compensation and fault protection
circuit. compared to discrete MOSFET and controller or
RCC switching converter solution, a Fairchild Power
Switch(FPS) can reduce total component count, design size,
weight and at the same time increase efficiency,
productivity, and system reliability. It has a basic platform
well suited for cost-effective C-TV power supply.



Features
• Wide operatimg frequency range up to (150kHz)
• Pulse by pulse over current limiting
• Over load protection
• Over voltage protecton (Min. 23V)
• Internal thermal shutdown function
• Under voltage lockout
• Internal high voltage sense FET
• External sync terminal
• Auto Restart Mode.


Absolute Maximum Ratings:
Note:
1. Tj=25°C to 150°C
2. Repetitive rating: Pulse width limited by maximum junction temperature
3. L=10mH, VDD=50V, RG=27Ω, starting Tj=25 °C
Characteristic Symbol Value Unit
Maximum drain voltage (1) VD,MAX 650 V
Drain-gate voltage (RGS=1MΩ) VDGR 650 V
Gate-source (GND) voltage VGS ±30 V
Drain current pulsed (2) IDM 48.0 ADC
Single pulsed avalanche energy (3) EAS 785 mJ
Continuous drain current (TC=25°C) ID 12 ADC
Continuous drain current (TC=100°C) ID 8.4 ADC
Maximum supply voltage VCC,MAX 30 V
Input voltage range VFB −0.3 to VSD V
Total power dissipation
PD 269 W
Derating 2.17 W/°C
Operating ambient temperature TA −25 to +85 °C
Storage temperature TSTG −55 to +150 °C.



KA393 Dual Differential Comparator:


Descritpion
The KA293 series consists of two independent voltage
comparators designed to operate from a single power supply
over a wide voltage range.

 Features
• Single Supply Operation: 2V to 36V
• Dual Supply Operation: ± 1V to ±18V
• Allow Comparison of Voltages Near Ground Potential
• Low Current Drain 800µA Typ.
• Compatible with all Forms of Logic
• Low Input Bias Current 25nA Typ.
• Low Input Offset Current ±5nA Typ.
• Low Offset Voltage ±1mV Typ.

 Absolute Maximum Ratings
Parameter Symbol Value Unit
Power Supply Voltage VCC ±18 or 36 V
Differential Input Voltage VI(DIFF) 36 V
Input Voltage VI - 0.3 to +36 V
Output Short Circuit to GND - Continuous -
Power Dissipation PD 570 mW
Operating Temperature
KA393/KA393A
KA293/KA293A
KA2903
TOPR 0 ~ + 70
- 25 ~ + 85
- 40 ~ + 85
°C
Storage Temperature TSTG - 65 ~ + 150 °C.



LA7845 Vertical Deflection Output Circuit:
SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN




Overview
The LA7845 is a vertical deflection output IC for highresolution
television and CRT display systems that use a
bus controller system signal processing IC. It can directly
drive the deflection yoke (including the required DC
component) from the bus controller system signal
processing IC's sawtooth waveform output. Connecting
the LA7845 and a Sanyo TV bus control system signal
processing IC in the LA7615 series allows all functions of
a color television signal system to be processed by the bus
system. Since the LA7845 has a maximum deflection
current of 2.2 Ap-p, it is optimal for use in large aperture
products, and is capable of driving 33 to 37 inch class
monitors.
Features
• Low power dissipation due to the provision of a built-in
pump circuit
• Vertical output circuit
• On-chip thermal protection circuit
• Good crossover characteristics
• Supports DC coupling.


Specifications
Maximum Ratings at Ta = 25°C
Parameter Symbol Conditions Ratings Unit
Maximum supply voltage VCC6 max 40 V
Output block supply voltage VCC3 max 85 V
Deflection output current I2 max –1.5 to +1.5 Ap-o
Thermal resistance qj-c 4.0 °C/W
Allowable power dissipation Pd max With an arbitrarily large heat sink 11 W
Operating temperature Topr –20 to +85 °C
Storage temperature Tstg –40 to +150 °C.


SDA55xx TVText Processor:


1. Introduction
The Micronas SDA 55xx TV microcontroller is dedicated
to 8 bit applications for TV control and provides
dedicated graphic features designed for modern low
class to mid range TV sets.
The SDA 55xx is a microcontroller and single chip teletext
decoder for decoding World System Teletext data
as well as other data services as Video Programming
System (VPS), Program Delivery Control (PDC), and
Wide Screen Signalling (WSS) data used for PAL plus
transmissions (in line 23). The data slicer and display
part of the SDA 55xx supports a wide range of TV
standards including PAL, NTSC as well as the acquisition
of the above mention data services as VPS, WSS,
PDC, TTX and Closed Caption data.
The slicer combined with its dedicated hardware
stores TTX data in a VBI buffer of 1 kByte. The Microcontroller
firmware available from Micronas performs
all the acquisition tasks (hamming and parity checks,
page search and evaluation of header control bits)
once per field. Additionally, the firmware can provide
high end teletext features like Packet-26-handling,
FLOF, TOP and list page mode. The Application Program
Interface (API) to the user software is optimized
for a minimum SW overhead.
The on-chip display unit used to display teletext data
up to level 1.5 can also be used for customer defined
on-screen displays (OSD). The display generator is
able to handle parallel display attributes, pixel oriented
displays and dynamically re-definable characters
(DRCS).
The SDA 55xx provides also an integrated generalpurpose,
fully 8051-compatible microcontroller with
specific hardware features especially suitable in TV
sets. The microcontroller core has been enhanced to
provide powerful features such as memory banking,
data pointers and additional interrupts, etc.
The internal XRAM consists of up to 16 kBytes. The
microcontroller provides an internal ROM of up to
128 kBytes. ROMless versions can access up to
1 MByte of external RAM and ROM.
The 8-bit microcontroller runs at 33.33 MHz internal
clock. SDA 55xx is realized in 0.25 micron technology
with 2.5 V supply voltage for the core and 3.3 V for the
I/O port pins to make them TTL compatible.
Based on the SDA 55xx microcontroller the MINTS
software package was developed and provides dedicated
device drivers for many Micronas video & audio
products and includes a full blown TV control SW for
the PEPER application chassis. The SDA 55xx is also
supported with powerful design tools like emulators
from Hitex, Kleinhenz, iSystems, the Keil C51 Compiler
and TEDIpro OSD development SW by Tara Systems.
This support provided by Micronas leads to:
– Shorter time to market
– Re-usability of the SW also for future Micronas
products
– Target independent SW development based on
ANSI C.
– Verification and validation of SW before targeting
and improved SW test concept
– Graphical interface design requiring a minimum
effort for OSD programming and TV controlled know
how.
– Complete, modular and open tool chain available
and configurable by customer.
1.1. General Features
– 8051 compatible microcontroller with TV related
special features and advanced OSD display
– Feature selection via special function register
– Simultaneous processing of TTX, VPS, PDC and
WSS (line 23) data
– Supply voltage 2.5 V for core and 3.3 V for ports
– ROM version package PSDIP52-2, PMQFP64-1
– Romless version package PMQFP100-2
– 128 kByte Flash ROM version package PSDIP52-2
1.1.1. External Crystal and Programmable Clock
Speed
– Normal mode 33.33 MHz CPU clock, power save
mode 8.33 MHz
– CPU clock speed selectable via special function
registers.
– Single external 6 MHz crystal, all necessary clock
signals are generated internally by means of PLLs
1.1.2. Microcontroller Features
– 8-bit 8051 instruction set compatible CPU
– Two 16-bit timers
– Watchdog timer
– Capture compare timer for infrared remote control
decoding
– Pulse width modulation unit (2 channels 14 bit,
6 channels 8 bit).

– ADC (4 channels, 8 bit)
– UART
1.1.3. Memory
– Non-multiplexed 8-bit data and 16…20-bit address
bus (ROMless version)
– Memory banking up to 1 MByte (ROMless version)
– Up to 128 kByte on-chip program ROM
– Eight 16-bit data pointer registers (DPTR)
– 256-bytes on-chip processor internal RAM (IRAM)
– 128 bytes extended stack memory
– Display RAM and TXT/VPS/PDC/WSS Data Acquisition
Buffer directly accessible via MOVX command
– Up to 16 kByte on-chip extended RAM (XRAM) consisting
of
• 1 kByte on-chip ACQ buffer RAM (access via
MOVX)
• 1 kByte on-chip extended RAM (XRAM, access via
MOVX) for user software
• 3 kByte display memory
1.1.4. Display Features
– ROM character set supports all east and west European
languages in a single device
– Mosaic graphic character set
– Parallel display attributes
– Single/double width/height of characters
– Variable flash rate
– Programmable screen size
(25 rows × 33 … 64 columns)
– Flexible character matrixes (H x V) 12 x 9 … 16
– Up to 256 dynamically re-definable characters in
standard mode; 1024 dynamically re-definable characters
in enhanced mode
– CLUT with up to 4096 color combinations
– Up to 16 colors per DRCS character
– One out of eight colors for foreground and background
colors for 1-bit DRCS and ROM characters
– Shadowing & contrast reduction
– Pixel by pixel shiftable cursor with up to 4 different
colors
– Support of progressive and 100 Hz double scan
– 3 × 4 bits RGB-DACs on chip
– Free programmable pixel clock from 10 MHz to
32 MHz
– Pixel clock independent from CPU clock
– Multinorm H/V-display synchronization in master or
slave mode
1.1.5. Acquisition Features
– Multistandard digital data slicer
– Parallel multinorm slicing (TTX, VPS, WSS, CC, G+)
– Four different framing codes available
– Data caption only limited by available memory
– Programmable VBI-buffer
– Full channel data slicing supported
– Fully digital signal processing
– Noise measurement and controlled noise compensation
– Attenuation measurement and compensation
– Group delay measurement and compensation
– Exact decoding of echo disturbed signals
1.1.6. Ports
– One 8-bit I/O-port with open drain output and
optional I2C bus emulation support (Port 0)
– Two 8-bit multifunction I/O-ports (Port 1, Port 3)
– One 4-bit port working as digital or analog inputs for
the ADC (Port 2)
– One 2-bit I/O-port with secondary functions (P4.2,
4.3, 4.7)
– One 4-bit I/O-port with secondary function (P4.0,
4.1, 4.4) Not available in PSDIP52-2).


TVText Pro versions and packages overview
Version Type Package
SDA 5550M – ROMless version
– 16 kByte RAM
PMQFP100-1
SDA 5550 – ROMless version
– 16 kByte RAM
PLCC84-1
SDA 555xFL – 128 kByte Flash memory on chip (re-programmable)
– 16 kByte RAM
PSDIP52-2
SDA 555x
x = 1...5
– 32-128 kByte user ROM
– 8-16 kByte RAM
PMQFP64-1, PSDIP52-1, PSDIP52-2
See note
SDA 5521 – OSD-only version
– 32 kByte user ROM on chip
– 8 kByte RAM
PSDIP52-1, PSDIP52-2
See note
SDA 5522 – OSD-only version
– 64 kByte user ROM on chip
– 8 kByte RAM
PSDIP52-1, PSDIP52-2
See note
SDA 5523 – OSD-only version
– 64 kByte user ROM on chip
– 16 kByte RAM
PSDIP52-1, PSDIP52-2
See note
SDA 5525 – OSD only version
– 128 kByte user ROM on chip
– 16 kByte RAM
PSDIP52-1, PSDIP52-2
See note
SDA 5577 – Standalone co-processor for teletext
reception, decoding, and display
– 10 pages
– ROM fix-programmed with the software
P116
PSDIP52-1, PSDIP52-2.

2. Functional Description
2.1. Clock System
2.1.1. General Function
The on-chip clock generator provides the TVTpro with
its basic clock signal. The oscillator runs with an external
crystal and the appropriate internal oscillator circuitry
(see Fig. on page 174).
For applications with lower timing accuracy requirements
(and if the RTC is not used) an external ceramic
resonator can be used. The usage of a ceramic resonator
is not recommended for Teletext applications as
depending on the absolute tolerance of the ceramic
resonator the data slicer may not work correctly. Additional
this might also require that display timing parameters
and the baud rate prescaler have to be adapted.
In timing critical applications the horizontal frequency
of the incoming CVBS signal can be used to measure
the actual timing deviation and to re-program the clock
PLL.
The 6 MHz clock signal is used to generate the internal
300 MHz display reference clock by means of an onchip
phase locked loop (PLL). The PLL can be
bypassed to reduce the power consumption. If an
immediate wake up from power down is not required
the PLL can also be switched off in this mode.
From the output frequency of the main clock PLL two
clock systems are derived.
2.1.2. System Clock
The 33.33 MHz system clock (fCPU) is provided to the
microcontroller core, all microcontroller related peripherals,
the sync timing logic, the A/D converters, the
slicer, the display generator and the color lookup
tables CLUT.
It is possible to use 8.33 MHz (1/4 of 33.33 MHz) for
the system clock domain (slow down mode). Setting
SFR-bit PLLS = 1 the user is able to send the PLL into
a power save mode.
Note: Before the PLL is switched to power save mode
(PLLS = 1), the software has to switch the clock
source from 200 MHz PLL clock to the 3 MHz
oscillator clock (SFR bit CLK_src = 1). In this
mode the slicer, acquisition, DAC and display
generator are switched off.
To switch back to full frequency operation, the software
has to end the PLL power save mode (SFR-bit
PLLS = 0), reset the PLL for 10 µs (3 machine cycles,
SFR bit PLL_res = ‘1’, then ‘0’ again), wait for 150 µs
(38 machine cycles) and switch back to the PLL clock
(SFR-bit SCR_src = 0).
If the power down mode is activated, PLL and oscillator
are send to sleep mode (SFR bit PDS = 1). Furthermore,
there are additional possibilities to disable the
clocks for the peripherals.

2.1.3. Pixel Clock
The second clock system is the pixel clock (fPIX), which
is programmable in a range from 10 … 32 MHz. It
serves the output part of the display FIFO and the D/A
converters. The pixel clock is derived from the high frequent
output of the PLL and line by line phase shifted
to the positive edge of the horizontal sync signal (normal
polarity). Because the final display clock is derived
from a DTO (digital time oscillator) it has no equidistant
clock periods although the average frequency is exact.
This pixel clock generation system has several advantages:
– The frequency of the pixel clock can be programmed
independently from the horizontal line
period.
– Because the input of the PLL is already a signal with
a relative high frequency, the resulting pixel frequency
has an extremely low jitter.
– The resulting pixel clock follows the edge of the Hsync
impulse without any delay and has always the
same quality than the sync timing of the deflection
controller.


2.2. Slicer and Data Acquisition
2.2.1. General Function
TVTPro provides a full digital data slicer including digital
H- and V-sync separation and digital sync processing.
The acquisition interface is capable to process all
known data services transmitted in the Vertical Blanking
Interval VBI of a CVBS signal (Teletext, VPS, CC,
G+, WSS). Four different framing codes (two of them
freely programmable for each field) are available for
each field. Digital signal processing algorithms are
applied to compensate various disturbing influences
as there are:
– Noise measurement and compensation.
– Attenuation measurement and compensation.
– Group delay measurement and compensation.
Note: TVTPro is optimized for precise data clock
recovery and error free reception of data. Thus,
the reception of data services is widely unaffected
by noise and the actual transmission
channel characteristics.
The CVBS input contains an on chip clamping circuit.
The integrated A/D converter has a 7 bit resolution.
The sampling frequency is 33.33 MHz.
The sliced data are synchronized to the data clock frequency
given by the clock-run-in. The framing code will
define the start of the data stream. The resulting valid
data will be written to the VBI data buffer. After line 23
is received an interrupt will be issued to the microcontroller.
The microcontroller starts processing the buffered
data. That means, a SW module will check the
data for errors and store them in an assigned memory
area.
To improve the data signal quality the slicer control
logic generates horizontal and vertical windows during
which the reception of the framing code is allowed.
The framing code can be programmed individually for
each line, so that in each line a different data service
can be received. For VPS and WSS the framing code
is hardwired. All following acquisition tasks are performed
by the internal controller, so in principal the
data of any data service can be acquired.
2.2.2. Slicer Architecture
The slicer consists of three main blocks:
– The slicer
– The H/V synchronization for the slicer
– The acquisition interface.

2.2.2.1. Distortion Processing
After A/D conversion the digital CVBS bit stream is
applied to internal circuitry which corrects the input
signal for distortions created in the transmission channel.
In order to apply the right algorithm for the correction,
a signal measurement is done in parallel. This
measurement unit can detect the following distortions.
2.2.2.1.1. Noise
The noise measurement unit incorporates two different
algorithms. Both algorithms use the value between two
equalizing pulses, which corresponds to the black
level. As the system knows the black level, a window is
placed between this two equalizing pulses (located in
line 4).
The first algorithm compares successive the amplitude
samples inside that window. The difference between
these samples is measured and a flag is set as soon
as this difference over several TV lines is greater than
a specified value. This algorithm is able to detect
higher frequency noise (e.g. white noise).
The second algorithm measures the difference
between the black value and the actual sampled value
inside this window. As soon as this difference over several
TV lines is greater than a specified value a second
flag is set. This algorithm is sensitive against low frequency
noise as it is known from co-channel distortion.
Both flags can be used to optimize the response of the
compensation circuits in order to achieve best reception
performance.
2.2.2.1.2. Frequency Attenuation
During signal transmission the CVBS signal can
severely be attenuated. This attenuation normally is
frequency depending. That means that the higher the
frequency the stronger the attenuation. As the clock
run-in (from now on referred to as CRI) for teletext represents
the highest possible frequency (3.5 MHz) it
can be used to measure the attenuation. Only strong
negative attenuation causes problems during data slicing.
A flag is needed to notify highly negative attenuation
to the SW. If this flag is set a special peaking filter
is switched on in the data-path.
2.2.2.1.3. Group Delay
Quite often the data stream is corrupted because of
group delay distortion introduced by the transmission
channel. The teletext framing code (E4H) is used as a
measurement reference. The delay of the edges inside
this code can be used to measure the group delay distortion.
The measurement is done during every teletext
line and filtered over several lines.
It can be detected whether the signal has positive,
negative or no group delay distortions. Two flags are
set accordingly. By means of these two flags, an allpass
contained in the compensation circuit is configured
to compensate positive or negative group delay.
All of the above mentioned filters can be individually be
disabled, set to forced mode, or automatic mode via
control registers.
2.2.2.2. Data Separation
Parallel to signal analysis and distortion compensation
another filter is calculating the required slicing level.
The slicing level is the mean value of the clock run-in
CRI. As teletext is coded using the NRZ format, the
slicing level can not be calculated outside the CRI timing
window and is therefore frozen after CRI. Using the
found slicing level the data are sliced from the digitized
CVBS signal. The result is a stream of zeros and ones.
In order to find the logical zeros and ones which have
been transmitted, the data clock needs to be recovered.
Therefore during the CRI timing window a digital
data PLL (D-PLL) is synchronized to the transitions in
the sliced data stream which represent the original
data clock. The frequency of the D-PLL is also frozen
after the CRI timing window.
Timing information to freeze the slicing level, the DPLL
and to control other actions are generated by the
timing circuit. It generates also all control signals which
have to be synchronized to the data start.
2.2.3. H/V-Synchronization
Data slicer and acquisition interface require different
control signals which have to be synchronized to the
incoming CVBS (e.g. line number, field sequence or
line start of a TV line). Therefore a slicing level for the
sync pulses is calculated and the sync signal is sliced
from the filtered digital CVBS signal.
Using a digital integrator vertical and horizontal sync
pulses are separated. The horizontal pulses are fed
into a digital H-PLL which has flywheel functionality.
The H-PLL includes a counter which is used to generate
all the necessary horizontal control signals. The
vertical sync pulse is used to synchronize the line
counter, which generates the required vertical control
signals.
The synchronization block includes a watchdog for
supervision of the actual lock condition of the H-PLL.
The watchdog can produce an interrupt (CC_IR) if synchronization
has been lost. It could therefore be an
indication for a channel change or missing input signal.


2.2.4. Acquisition Interface
The acquisition interface manages the data transfer
from between slicer and memory. From slicer to memory
first of all a bit synchronization is performed (Framing
Code (FC) check). Following this, the data is serial/
parallel converted. 8 bit wide words will be shifted into
the memory. The data acquisition supports several features.
The FC check is able to handle four different
framing codes for one field. Two of this framing codes
are programmable and could therefore be changed
from field to field. The acquisition can be switched from
normal mode (line 6 to 23) to full channel mode (line 6
to the end of a field).
In the other direction parameters are loaded from the
memory to the slicer. This parameter down loading
takes place after the vertical sync and after the horizontal
sync. These parameters are used for the slicer
configuration.
2.2.4.1. Framing Code Check
There are four Framing Codes FC implemented which
are compared with the FC of the incoming signal.
– The first one is 8-bit wide and is loaded down with
the field parameters.
– The second one is 16-bit wide and fixed to the FC of
VPS.
– The third one is 16-bit wide as well, but can be
loaded with the field parameters. If the third one is
used, the user can specify not only the FC but also a
“don’t-care” mask.
– The fourth FC is reserved for WSS. The actual FC
can be changed line by line.
2.2.4.1.1. Framing Code FC1
This FC should be used for all services with 8-bit framing
codes (e.g. for TTX). The actual framing code is
loaded down each field. The check can be done without
any bit error tolerance or with a tolerance of one
bit.
2.2.4.1.2. Framing Code FCVPS
This FC is fixed to that of VPS. Only an error-free signal
will enable the reception of the VPS data line.
Note: If VPS should be sliced in field 1 and TTX in field
2, the appropriate line parameters for line 16
have to be changed dynamically from field to
field.
2.2.4.1.3. Framing Code FC3
This 16-bit FC is loaded with the field parameters as
well as a “don’t care” mask. The incoming signal is
compared with both, the framing code and the “don’t
care” mask. Further reception is enabled if all bits
which are not “don’t care” match the incoming data
stream.
2.2.4.1.4. Framing Code FCWSS
This FC is pre-programmed to that of WSS. Only an
error-free signal will enable the reception of the WSS
data line.
2.2.4.1.5. FC Check Select
There is a two bit line parameter called FCSEL. By
means of this parameter the user is able to select
which FC check is used for the actual line. If NORM is
set to WSS the WSS FC check is used independently
of FCSEL.
2.2.4.2. Interrupts
Some events which occur inside the slicer, sync separation
or acquisition interface should cause an interrupt.
They are summarized in register CISR0 and
CISR1. The slicer hardware sets the related interrupt
flag which must be reset by the application software
before the next interrupt can be accepted.
2.2.4.3. VBI Buffer and Memory Organization
The implemented SW has to provide configuration
parameters for the slicer and the acquisition interface.
Both circuits will produce status information for the
CPU.
Some of these parameters and status bits are constant
during the duration of a field. Those parameters are
called field parameters. They are downloaded after the
vertical sync.
Other parameters and status bits may change from
line to line (e.g. data service depending values). Those
parameters are called line parameters. They are downloaded
after each horizontal sync impulse.
The start address of the VBI buffer can be configured
with a special function register ‘STRVBI’. 9 Bytes are
needed for the field parameter. 47 Bytes should be
reserved for every sliced data line. If 18 lines of data
(in full channel mode 314) have been send to memory
no further data acquisition will take place until the next
vertical pulse appears and the H-PLL is still locked.

2.2.7. Microcontroller
2.2.8. Architecture
Every CPU machine cycle consists of 12 internal CPU
clock periods.
The CPU manipulates operands in two memory
spaces: The program memory space, and the data
memory space. The program memory address space
is provided to accommodate relocatable code.
The data memory address space is divided into the
256-Byte internal data RAM, XRAM (extended data
memory, accessible with MOVX instructions) and the
128-Byte Special Function Register (SFR) address
space.
Four register banks (each bank has eight registers),
128 addressable bits, and the stack reside in the internal
data RAM. The stack depth is limited only by the
available internal data RAM. Its location is determined
by the 8-bit stack pointer. All registers except the program
counter and the four 8-register banks reside in
the special function register address space.
These memory mapped registers include arithmetic
registers, pointers, I/O-ports, registers for the interrupt
system, timers, pulse width modulator, capture control
unit, watchdog timer, UART, display, acquisition control
etc. Many locations in the SFR address space are bitwise
addressable.
Note: Reading from unused locations within data
memory will yield undefined data.
Conditional branches are performed relative to the
16 bit program counter. The register indirect jump permits
branching relative to a 16-bit base register with an
offset provided by an 8-bit index register. Sixteen-bit
jumps and calls permit branching to any location in the
memory address space.
The microcontroller has five methods for addressing
source operands: Register, direct, register-indirect,
immediate, and base register plus index register-indirect
addressing.
The first three methods can be used for addressing
destination operands. Most instructions have a “destination,
source” field that specifies the data type,
addressing methods and operands involved. For operations
other than moves, the destination operand is
also a source operand.
Registers in the four 8-register banks can be accessed
through register, direct, or register-indirect addressing.
The lower 128 Bytes of internal data RAM can be
accessed through direct or register-indirect addressing,
the upper 128 Bytes of internal data RAM through
register-indirect addressing; and the special function
registers through direct addressing. Look-up tables
resident in program memory can be accessed through
base register plus index register-indirect addressing.
2.2.8.1. CPU Hardware
2.2.8.1.1. Instruction Decoder
Each program instruction is decoded by the instruction
decoder. This unit generates the internal signals that
control the functions of each unit within the CPU section.
These signals control the sources and destination
of data, as well as the function of the Arithmetic/Logic
Unit (ALU).
2.2.8.1.2. Program Control Section
The program control section controls the sequence in
which the instructions stored in the program memory
are executed. The conditional branch logic enables
conditions internal and external to the microcontroller
to cause a change in the sequence of program execution.
The 16-bit program counter holds the address of
the instruction to be executed. It is manipulated with
the control transfer instructions listed in
Section 2.2.10..
2.2.8.1.3. Internal Data RAM
The internal data RAM provides a 256-Byte scratch
pad memory, which includes four register banks and
128 direct addressable software flags. Each register
bank contains registers R0 … R7. The addressable
flags are located in the 16-Byte locations starting at
Byte address 20H and ending with Byte location 2FH of
the RAM address space.
In addition to this standard internal data RAM the
microcontroller contains an extended internal RAM. It
can be considered as a part of an external data memory.
It is referenced by MOVX instructions (MOVX A,
@DPTR), the memory organization is explained in
Section 2.5. on page 47.
2.2.8.1.4. Arithmetic/Logic Unit (ALU)
The arithmetic section of the microcontroller performs
many data manipulation functions and includes the
Arithmetic/Logic Unit (ALU) and the ACC, B, and PSW
registers. The ALU accepts 8-bit data words from one
or two sources and generates an 8-bit result under the
control of the instruction decoder. The ALU performs
the arithmetic operations of add, subtract, multiply,
divide, increment, decrement, BCD-decimal-add adjust
and compare, and the logic operations like and, or,exclusive-or, complement and rotate (right, left, or nibble
swap).
The register ACC is the accumulator, the register B is
dedicated during multiply and divide and serves as
both source and destination. During all other operations
the register B is simply another location of the
special function register space and may be used for
any purpose.
2.2.8.1.5. Boolean Processor
The Boolean processor is an integral part of the microcontroller
architecture. It is an independent bit processor
with its own instruction set, its own accumulator
(the carry flag) and its own bit-addressable RAM and I/
O. The bit manipulation instructions allow the direct
addressing of 128 bits within the internal data RAM
and several bits within the special function registers.
The special function registers which have addresses
exactly divisible by eight contain directly addressable
bits.
The Boolean processor can perform, on any addressable
bit, the bit operations of “set”, “clear”, “complement”,
“jump-if-set”, “jump-if-not-set”, “jump-if-set thenclear”
and “move to/from carry”. Between any addressable
bit (or its complement) and the carry flag it can
perform the bit operation of logical AND or logical OR
with the result returned to the carry flag.
2.2.8.1.6. Program Status Word Register (PSW)
The PSW flag bits record microcontroller status information
and control the operation of the microcontroller.
The carry (CY), auxiliary carry (AC), two user flags (F0
and F1), register bank select (RS0 and RS1), overflow
(OV) and parity (P) flags reside in the program status
word register. These flags are bit-memory-mapped
within the Byte-memory-mapped PSW. The CY, AC,
and OV flags generally reflect the status of the latest
arithmetic operations. The CY flag is also the Boolean
accumulator for bit operations. The P-flag always
reflects the parity of the register ACC. F0 and F1 are
general purpose flags which are pushed onto the stack
as part of a PSW save (see Table 2–7).
The two register bank select bits (RS1 and RS0) determine
which one of the four register banks is selected
as show in Table 2–6.
See Section 3. on page 110 for detailed register
description.
2.2.8.1.7. Stack Pointer (SP)
The 8-bit stack pointer contains the address at which
the last Byte was pushed onto the stack. This is also
the address of the next Byte that will be popped. The
SP is incremented during a push. SP can be read or
written to under software control. The stack may be
located anywhere within the internal data RAM
address space and may be as large as 256 Bytes.

2.2.8.2. CPU Timing
Timing generation is completely self-contained, except
for the frequency reference which can be a crystal or
external clock source. The on-board oscillator is a parallel
anti-resonant circuit. The XTAL2 pin is the output
of a high-gain amplifier, while XTAL1 is its input. A
crystal connected between XTAL1 and XTAL2 provides
the feedback and phase shift required for oscillation.
In slowdown mode, the microcontroller runs at one
fourth the normal frequency. This mode is useful when
power consumption needs to be reduced. Slow down
mode is entered by setting the bit SD in PCON register.


2.2.8.3.1. Register Addressing
Register addressing accesses the eight working registers
(R0 … R7) of the selected register bank. The
PSW register flags RS1 and RS0 determine which register
bank is enabled. The least significant three bits of
the instruction opcode indicate which register is to be
used. ACC, B, DPTR and CY, the Boolean processor
accumulator, can also be addressed as registers.
2.2.8.3.2. Direct Addressing
Direct Byte addressing specifies an on-chip RAM location
(only low part) or a special function register. Direct
addressing is the only method of accessing the special
function registers. An additional Byte is appended to
the instruction opcode to provide the memory location
address. The highest order bit of this Byte selects one
of two groups of addresses: Values between
00H … 7FH access internal RAM locations, while values
between 80H … 0FFH access one of the special
function registers.
2.2.8.3.3. Register Indirect Addressing
Register indirect addressing uses the contents of
either R0 or R1 (in the selected register bank) as a
pointer to locations in the 256 Bytes of internal RAM.
Note that the special function registers are not accessible
by this method.
Execution of PUSH and POP instructions also use register-
indirect addressing. The stack pointer may reside
anywhere in internal RAM.
2.2.8.3.4. Immediate Addressing
Immediate addressing allows constants to be part of
the opcode instruction in program memory.
An additional Byte is appended to the instruction to
hold the source variable. In the assembly language
and instruction set, a number sign (#) precedes the
value to be used, which may refer to a constant, an
expression, or a symbolic name.
2.2.8.3.5. Base Register plus Index Register Indirect
Addressing
Base register plus index register indirect addressing
allows a Byte to be accessed from program memory
via an indirect move from the location whose address
is the sum of a base register (DPTR or PC) and index
register, ACC. This mode facilitates accessing to lookup
table resident in program memory.
2.2.9. Ports and I/O-Pins
There are 34 Port pins available, out of which 24 are I/
O pins configured as three 8-bit wide ports P0, P1, and
P3. Port 4 consists of 6 I/O bits, out of which only 3 are
available in the PSDIP52-2 package. All 6 port pins are
only available in the other packages with higher pin
count. Each pin can be individually and independently
programmed as input or output and each can be configured
dynamically. One 4-bit-port P2 is input only.
An instruction that uses a port's bit/Byte as a source
operand reads a value that is the logical AND of the
last value written to the bit/Byte and the polarity being
applied to the pin/pins by an external device (this
assumes that none of the microcontroller's electrical
specifications are being violated).
An instruction that reads a bit/Byte, operates on the
content, and writes the result back to the bit/Byte,
reads the last value written to the bit/Byte instead of
the logic level at the pin/pins.
Pins of a single port can be individually configured as
inputs and outputs by writing a ‘one’ to each pin that is
to be an input. Each time an instruction uses a complete
port as destination, the SW has to make sure that
‘ones’ are written to those bits that correspond to the
pins used as inputs. An external input signal to a port
pin needs not to be synchronized to the internal clock.
All the port latches have ‘one’ s written to them by the
reset function. If a ‘zero’ is subsequently written to a
port latch, it can be reconfigured as an input by writing
a ‘one’ to it.
The instructions that perform a read of, operation on,
and write to a port’s bit/Bytes are INC, DEC, CPL, JBC,
SETB, CLR, MOV P.X, CJNE, DJNZ, ANL, ORL, and
XRL. The data read by these instructions is the last
value that was written to the port, without regard to the
levels being applied at the pins. This insures that bits
written to a ‘one’ (for use as inputs) are not inadvertently
cleared.
Port 0 has an open-drain output. Writing a ‘one’ to the
bit latch leaves the output transistor off, so the pin
floats.
In that condition it can be used as a high-impedance
input. Port 0 is considered ‘true bidirectional’, because
when configured as an input it floats.
Ports 1, 3 and 4 have ‘quasi-bidirectional’ output drivers.
In ports P1, P3 and P4 the output drivers provide
source current for one system clock period if, and only
if, software updates the bit in the output latch from a
‘zero’ to an ‘one’. Sourcing current only on ‘zero to one’
transition prevents a pin, programmed as an input,from sourcing current into the external device that is
driving the input pin.
It is not allowed to drive Port 3.6 to logic low level while
reset state changes from the active to inactive state
otherwise a special test mode is activated.
Secondary functions can be selected individually and
independently for the pins of Port 1 and 3. Further
information on Port 1's secondary functions is given in
Section 2.9. on page 59. P3 generates the secondary
control signals automatically as long as the pin corresponding
to the appropriate signal is programmed as
an input, i. e. if the corresponding bit latch in the P3
special function register contains a ‘one’.

Table 2–9: Ports and I/O-pins
Port I/O Default
Function
Alternate Function 2 Alternate Function 3
Toggle Function Toggle Function
Control bit Function Control bit Function
P0(0…7) I/O Port pin – – – –
P1(0) I/O Port pin PWME(E0) PWM 8 bit channel 0 – –
P1(1) I/O Port pin PWME(E1) PWM 8 bit channel 1 – –
P1(2) I/O Port pin PWME(E2) PWM 8 bit channel 2 – –
P1(3) I/O Port pin PWME(E3) PWM 8 bit channel 3 – –
P1(4) I/O Port pin PWME(E4) PWM 8 bit channel 4 – –
P1(5) I/O Port pin PWME(E5) PWM 8 bit channel 5 – –
P1(6) I/O Port pin PWME(E6) PWM 14 bit channel 0 – –
P1(7) I/O Port pin PWME(E7) PWM 14 bit channel 1 – –
P2(0) I Port pin CADCCO(AD0) ADC channel 0 – –
P2(1) I Port pin CADCCO(AD1) ADC channel 1 – –
P2(2) I Port pin CADCCO(AD2) ADC channel 2 – –
P2(3) I Port pin CADCCO(AD3) ADC channel 3 – –
P3(0) I/O Port pin CSCR0(O_E_P3_0) ODD/Even indicator – –
P3(1) I/O Port pin Port input mode External extra Int 0 Port output
mode
TXD
P3(2) I/O Port pin Port input mode External interrupt 0 – –
P3(3) I/O Port pin Port input mode External interrupt 1 – –
P3(4) I/O Port pin Port input mode Timer/counter 0 input – –
P3(5) I/O Port pin Port input mode Timer/counter 1 input – –
P3(6) I/O Port pin – – – –
P3(7) I/O Port pin Port input mode External extra Int 1 Port input
mode
RXD
P4(0)1) I/O A17 CSCR1(A17_P4_0) Port pin – –
1) Not available in PSDIP52-2.


2.2.9.1. Read Modify Write Feature
‘Read-modify-write’ commands are instructions that
read a value, possibly change it, and then rewrite it to
the latch. The read-modify-write instructions are listed
in Table 2–10.
If the destination operand is a port or a port bit, these
instructions read the information stored in the latch
rather than the status of the pin. The read-modify-write
instructions are directed to the latch rather than to the
pin in order to avoid a possible misinterpretation of the
voltage level at the pin. For example, a port bit might
be used to drive the base of a transistor. If a ‘one’ is
written to the bit, the transistor is turned on.
If the CPU would read back the status of the same port
bit from the pin rather than the latch, it would read the
base-emitter voltage of the transistor and interpret it as
a logic ‘0’. Reading the latch rather than the pin will
return the correct value of logic ‘1’.
P4(1)1) I/O A18 CSCR1(A18_P4_1) Port pin – –
P4(2) I/O Port pin CSCR1(ENARW) Read signal – –
P4(3) I/O Port pin CSCR1(ENARW) Write signal – –
P4(4)1) I/O A19 CSCR1(A19_P4_4) Port pin – –
P4(7) I/O Port/VS in CSCR0(VS_OE,
P4_7_ALT)
VS output CSCR0
(VS_OE,
P4_7_ALT)
OddEven output
1) Not available in PSDIP52-2
Table 2–9: Ports and I/O-pins, continued
Port I/O Default
Function
Alternate Function 2 Alternate Function 3
Toggle Function Toggle Function
Control bit Function Control bit Function
Table 2–10: Read-modify-write instructions
Mnemonic Description Example
ANL
ORL
XRL
JBC
CPL
INC
DEC
DJNZ
MOV PX.Y, C1)
CLR PX.Y1)
SET PX.Y1)
Logical AND
Logical OR
Logical EX – OR
Jump if bit = 1 and clear bit
Complement bit
Increment
Decrement
Decrement and jump if not zero
Move carry bit to bit Y of Port X
Clear bit Y of Port X
Set bit Y of Port X
ANL P1, A
ORL P2, A
XRL P3, A
JBC P1.1, LABEL
CPL P3.0
INC P1
DEC P1
DJNZ P3, LABEL
MOV P1.7, C
CLR P2.6
SET P3.5
1) The instruction reads the port Byte (all 8 bits), modifies the addressed bit, then writes the new Byte back to the
latch.





VDP 31xxB Video Processor Family:

 Video, Display, and Deflection Processor: ITT/MICRONAS VDP3112

 1. Introduction
The VDP 31xxB is a Video IC family of high-quality
single-chip video processors. Modular design and a
submicron technology allow the economic integration of
features in all classes of TV sets. The VDP 31xxB family
is based on functional blocks contained in the two chips:
VPC 3200A Video Processor and DDP 3300A Display
and Deflection Processor.
Each member of the family contains the entire video,
display, and deflection processing for 4:3 and 16:9
50/60 TV sets. Its performance and flexibility allow the
user to standardize his product development. Hardware
and software applications can profit from the modularity,
as well as manufacturing, systems support, or maintenance.

1.1. VDP Applications
As a member of the VDP 31xxB family, the VDP 3120B
offers all video features necessary to design a state-ofthe-
art TV set:
Video Decoding
– 4 composite inputs, 1 S-VHS input
– composite video & sync output
– integrated high-quality A/D converters
– adaptive 2H comb filter Y/C separator
– 1H NTSC comb filter
– multistandard color decoder (1 crystal)
– multistandard sync decoder
– black line detector
Video Processing
– horizontal scaling (0.25 to 4)
– panorama vision
– black level expander
– dynamic peaking
– soft limiter (gamma correction)
– color transient improvement
RGB Processing
– programmable RGB matrix
– digital color bus interface
– additional analog RGB / fast blank input
– half-contrast switch
– picture frame generator
Deflection
– scan velocity modulation output
– high-performance H/V deflection
– separate ADC for tube measurements
– EHT compensation
Miscellaneous
– one 20.25 MHz crystal, few external components
– embedded RISC controller (80 MIPS)
– I2C-Bus Interface
– single 5 V power supply
– submicron CMOS technology
– 64-pin PSDIP package.

2. Functional Description
2.1. Analog Front-End
This block provides the analog interfaces to all video inputs
and mainly carries out analog-to digital conversion
for the following digital video processing. A block diagram
is given in Fig. 2–1.
Most of the functional blocks in the front-end are digitally
controlled (clamping, AGC, and clock-DCO). The control
loops are closed by the Fast Processor (‘FP’) embedded
in the decoder.
2.1.1. Input Selector
Up to five analog inputs can be connected. Four inputs
are for input of composite video or S-VHS luma signal.
These inputs are clamped to the sync back porch and
are amplified by a variable gain amplifier. One input is
for connection of S-VHS carrier-chrominance signal.
This input is internally biased and has a fixed gain amplifier.


2.1.2. Clamping
The composite video input signals are AC coupled to the
IC. The clamping voltage is stored on the coupling capacitors
and is generated by digitally controlled current
sources. The clamping level is the back porch of the video
signal. S-VHS chroma is also AC coupled. The input
pin is internally biased to the center of the ADC input
range.

2.1.3. Automatic Gain Control
A digitally working automatic gain control adjusts the
magnitude of the selected baseband by +6/–4.5 dB in 64
logarithmic steps to the optimal range of the ADC. The
gain of the video input stage including the ADC is 213
steps/V with the AGC set to 0 dB.
2.1.4. Analog-to-Digital Converters
Two ADCs are provided to digitize the input signals.
Each converter runs with 20.25 MHz and has 8 bit resolution.
An integrated bandgap circuit generates the required
reference voltages for the converters.

2.1.5. ADC Range
The ADC input range for the various input signals and
the digital representation is given in Table 2–1 and Fig.
2–2. The corresponding output signal levels of the
VDP 31xxB are also shown.

2.1.6. Digitally Controlled Clock Oscillator
The clock generation is also a part of the analog front
end. The crystal oscillator is controlled digitally by the
control processor; the clock frequency can be adjusted
within ±150 ppm.

2.1.7. Analog Video Output
The input signal of the Luma ADC is available at the analog
video output pin. The signal at this pin must be buffered
by a source follower. The output voltage is 2 V, thus
the signal can be used to drive a 75 line. The magnitude
is adjusted with an AGC in 8 steps together with the
main AGC.

2.2. Adaptive Comb Filter
The adaptive comb filter is used for high-quality luminance/
chrominance separation for PAL or NTSC signals.
The comb filter improves the luminance resolution
(bandwidth) and reduces interferences like cross-luminance
and cross-color artifacts. The adaptive algorithm
can eliminate most of the mentioned errors without
introducing new artifacts or noise.
A block diagram of the comb filter is shown in Fig. 2–3.
The filter uses two line delays to process the information
of three adjacent video lines. To have a fixed phase relationship
of the color subcarrier in the three channels, the
system clock (20.25 MHz) is fractionally locked to the
color subcarrier. This allows the processing of all color
standards and substandards using a single crystal frequency.
The CVBS signal in the three channels is filtered at the
subcarrier frequency by a set of bandpass/notch filters.
The output of the three channels is used by the adaption
logic to select the weighting that is used to reconstruct
the luminance/chrominance signal from the 4 bandpass/
notch filter signals. By using soft mixing of the 4 signals
switching artifacts of the adaption algorithm are completely
suppressed.
The comb filter uses the middle line as reference, therefore,
the comb filter delay is one line. If the comb filter is
switched off, the delay lines are used to pass the luma/
chroma signals from the A/D converters to the luma/
chroma outputs. Thus, the comb filter delay is always
one line.
Various parameters of the comb filter are adjustable,
hence giving to the user the ability to adjust his own desired
picture quality.
Two parameters (KY, KC) set the global gain of luma and
chroma comb separately; these values directly weigh
the adaption algorithm output. In this way, it is possible
to obtain a luma/chroma separation ranging from standard
notch/bandpass to full comb decoding.
The parameter KB allows to choose between the two
proposed comb booster modes. This so-called feature
widely improves vertical high to low frequency transitions
areas, the typical example being a multiburst to dc
change. For KB=0, this improvement is kept moderate,
whereas, in case of KB=1, it is maximum, but the risk to
increase the “hanging dots” amount for some given color
transitions is higher.
Using the default setting, the comb filter has separate
luma and chroma decision algorithms; it is however possible
to switch the chroma comb factor to the current
luma adaption output by setting CC to 1.
Another interesting feature is the programmable limitation
of the luma comb amount; proper limitation,
associated to adequate luma peaking, gives rise to an
enhanced 2-D resolution homogeneity. This limitation is
set by the parameter CLIM, ranging from 0 (no limitation)
to 31 (max. limitation).
The DAA parameter (1:off , 0:on) is used to disable/enable
a very efficient built-in “rain effect” suppressor;
many comb filters show this side effect which gives
some vertical correlation to a 2-D uniform random area,
due to the vertical filtering. This unnatural-looking phenomenon
is mostly visible on tuner images, since they
are always corrupted by some noise; and this looks like
rain.

2.3. Color Decoder
In this block, the standard luma/chroma separation and
multi-standard color demodulation is carried out. The
color demodulation uses an asynchronous clock, thus
allowing a unified architecture for all color standards.
A block diagram of the color decoder is shown in Fig.
2–5. The luma as well as the chroma processing, is
shown here. The color decoder provides also some special
modes, e.g. wide band chroma format which is intended
for S-VHS wide bandwidth chroma.
If the adaptive comb filter is used for luma chroma separation,
the color decoder uses the S-VHS mode processing.
The output of the color decoder is YCrCb in a 4:2:2
format.

2.3.1. IF-Compensation
With off-air or mistuned reception, any attenuation at
higher frequencies or asymmetry around the color subcarrier
is compensated. Four different settings of the IFcompensation
are possible:
– flat (no compensation)
– 6 dB/octave
– 12 dB/octave
– 10 dB/MHz
The last setting gives a very large boost to high frequencies.
It is provided for SECAM signals that are decoded
using a SAW filter specified originally for the PAL standard.

2.3.2. Demodulator
The entire signal (which might still contain luma) is now
quadrature-mixed to the baseband. The mixing frequency
is equal to the subcarrier for PAL and NTSC, thus
achieving the chroma demodulation. For SECAM, the
mixing frequency is 4.286 MHz giving the quadrature
baseband components of the FM modulated chroma.
After the mixer, a lowpass filter selects the chroma components;
a downsampling stage converts the color difference
signals to a multiplexed half rate data stream.
The subcarrier frequency in the demodulator is generated
by direct digital synthesis; therefore, substandards
such as PAL 3.58 or NTSC 4.43 can also be demodulated.

2.3.3. Chrominance Filter
The demodulation is followed by a lowpass filter for the
color difference signals for PAL/NTSC. SECAM requires
a modified lowpass function with bell-filter characteristic.
At the output of the lowpass filter, all luma information is
eliminated.
The lowpass filters are calculated in time multiplex for
the two color signals. Three bandwidth settings (narrow,
normal, broad) are available for each standard. For PAL/
NTSC, a wide band chroma filter can be selected. This
filter is intended for high bandwidth chroma signals, e.g.
a nonstandard wide bandwidth S-VHS signal.
Fig. 2–6: Frequency response of chroma filters
PAL/NTSC
SECAM.

2.3.4. Frequency Demodulator
The frequency demodulator for demodulating the SECAM
signal is implemented as a CORDIC-structure. It
calculates the phase and magnitude of the quadrature
components by coordinate rotation.
The phase output of the CORDIC processor is differentiated
to obtain the demodulated frequency. After the
deemphasis filter, the Dr and Db signals are scaled to
standard CrCb amplitudes and fed to the crossoverswitch.

2.3.5. Burst Detection
In the PAL/NTSC-system the burst is the reference for
the color signal. The phase and magnitude outputs of
the CORDIC are gated with the color key and used for
controlling the phase-lock-loop (APC) of the demodulator
and the automatic color control (ACC) in PAL/NTSC.
The ACC has a control range of +30...–6 dB.
For SECAM decoding, the frequency of the burst is measured.
Thus, the current chroma carrier frequency can
be identified and is used to control the SECAM processing.
The burst measurements also control the color killer
operation; they can be used for automatic standard
detection as well.

2.3.6. Color Killer Operation
The color killer uses the burst-phase/burst-frequency
measurement to identify a PAL/NTSC or SECAM color
signal. For PAL/NTSC, the color is switched off (killed)
as long as the color subcarrier PLL is not locked. For SECAM,
the killer is controlled by the toggle of the burst frequency.
The burst amplitude measurement is used to
switch-off the color if the burst amplitude is below a programmable
threshold. Thus, color will be killed for very
noisy signals. The color amplitude killer has a programmable
hysteresis.

2.3.7. PAL Compensation/1-H Comb Filter
The color decoder uses one fully integrated delay line.
Only active video is stored.
The delay line application depends on the color standard:
– NTSC: 1-H comb filter or color compensation
– PAL: color compensation
– SECAM: crossover-switch
In the NTSC compensated mode, Fig. 2–7 c), the color
signal is averaged for two adjacent lines. Thus, crosscolor
distortion and chroma noise is reduced. In the
NTSC combfilter mode, Fig. 2–7 d), the delay line is in
the composite signal path, thus allowing reduction of
cross-color components, as well as cross-luminance.
The loss of vertical resolution in the luminance channel
is compensated by adding the vertical detail signal with
removed color information.


2.3.8. Luminance Notch Filter
If a composite video signal is applied, the color information
is suppressed by a programmable notch filter. The
position of the filter center frequency depends on the
subcarrier frequency for PAL/NTSC. For SECAM, the
notch is directly controlled by the chroma carrier frequency.
This considerably reduces the cross-luminance.

2.3.9. Skew Filtering
The system clock is free-running and not locked to the
TV line frequency. Therefore, the ADC sampling pattern
is not orthogonal. The decoded YCrCb signals are converted
to an orthogonal sampling raster by the skew filters,
which are part of the scaler block.
The skew filters allow the application of a group delay to
the input signals without introducing waveform or frequency
response distortion.
The amount of phase shift of this filter is controlled by the
horizontal PLL1. The accuracy of the filters is 1/32
clocks for luminance and 1/4 clocks for chroma. Thus
the 4:2:2 YCrCb data is in an orthogonal pixel format
even in the case of nonstandard input signals such as
VCR.

2.4. Horizontal Scaler
The 4:2:2 YCrCb signal from the color decoder is processed
by the horizontal scaler. The scaler block allows
a linear or nonlinear horizontal scaling of the input video
signal in the range of 0.25 to 4. Nonlinear scaling, also
called “panorama vision”, provides a geometrical distortion
of the input picture. It is used to fit a picture with 4:3
format on a 16:9 screen by stretching the picture geometry
at the borders. Also, the inverse effect can be produced
by the scaler. A summary of scaler modes is given
in Table 2–2.
The scaler contains a programmable decimation filter, a
1-line FIFO memory, and a programmable interpolation
filter. The scaler input filter is also used for pixel skew
correction, see 2.3.9. The decimator/interpolator structure
allows optimal use of the FIFO memory. The controlling
of the scaler is done by the internal Fast Processor.

2.5. Black-Line Detector
In case of a letterbox format input video, e.g. Cinemascope,
PAL+ etc., black areas at the upper and lower
part of the picture are visible. It is suitable to remove or
reduce these areas by a vertical zoom and/or shift operation.
The VDP 31xxB supports this feature by a letterbox detector.
The circuitry detects black video lines by measuring
the signal amplitude during active video. For every
field the number of black lines at the upper and lower
part of the picture are measured, compared to the previous
measurement and the minima are stored in the
I2C-register BLKLIN. To adjust the picture amplitude, the
external controller reads this register, calculates the vertical
scaling coefficient and transfers the new settings,
e.g. vertical sawtooth parameters, horizontal scaling coefficient
etc., to the VDP.
Letterbox signals containing logos on the left or right
side of the black areas are processed as black lines,
while subtitles, inserted in the black areas, are processed
as non-black lines. Therefore the subtitles are
visible on the screen. To suppress the subtitles, the vertical
zoom coefficient is calculated by selecting the larger
number of black lines only. Dark video scenes with a low
contrast level compared to the letterbox area are indicated
by the BLKPIC bit.

2.6. Test Pattern Generator
The YCrCb outputs of the front-end can be switched to
a test mode where YCrCb data are generated digitally
in the VDP 31xxB. Test patterns include luma/chroma
ramps, flat fields and a pseudo color bar pattern.


2.7. Video Sync Processing
Fig. 2–11 shows a block diagram of the front-end sync
processing. To extract the sync information from the
video signal, a linear phase lowpass filter eliminates all
noise and video contents above 1 MHz. The sync is separated
by a slicer; the sync phase is measured. A variable
window can be selected to improve the noise immunity
of the slicer. The phase comparator measures the
falling edge of sync, as well as the integrated sync pulse.
The sync phase error is filtered by a phase-locked loop
that is computed by the FP. All timing in the front-end is
derived from a counter that is part of this PLL, and it thus
counts synchronously to the video signal.
A separate hardware block measures the signal back
porch and also allows gathering the maximum/minimum
of the video signal. This information is processed by the
FP and used for gain control and clamping.
For vertical sync separation, the sliced video signal is integrated.
The FP uses the integrator value to derive vertical
sync and field information.
The information extracted by the video sync processing
is multiplexed onto the hardware front sync signal (FSY)
and is distributed to the rest of the video processing system.
The format of the front sync signal is given in
Fig. 2–12.
The data for the vertical deflection, the sawtooth, and the
East-West correction signal is calculated by the
VDP 31xxB. The data is buffered in a FIFO and transferred
to the back-end by a single wire interface.
Frequency and phase characteristics of the analog video
signal are derived from PLL1. The results are fed to
the scaler unit for data interpolation and orthogonalization
and to the clock synthesizer for line-locked clock
generation. Horizontal and vertical syncs are latched
with the line-locked clock.


2.8. Display Part
In the display part the conversion from digital YCrCb to
analog RGB is carried out. A block diagram is shown in
Figure 2–20. In the luminance processing path, contrast
and brightness adjustments and a variety of features,
such as black level expansion, dynamic peaking and
soft limiting, are provided. In the chrominance path, the
CrCb signals are converted to 20.25 MHz sampling rate
and filtered by a color transient improvement circuit. The
YCrCb signals are converted by a programmable matrix
to RGB color space.
The display processor provides separate control settings
for two pictures, i.e. different coefficients for a
‘main’ and a ‘side’ picture.
The digital OSD insertion circuit allows the insertion of
a 5-bit OSD signal. The color space for this signal is controlled
by a partially programmable color look-up table
(CLUT) and contrast adjustment.
The OSD signals and the display clock are synchronized
to the horizontal flyback. For the display clock, a gate
delay phase shifter is used. In the analog backend, three
10-bit digital-to-analog converters provide the analog
output signals.
2.8.1. Luma Contrast Adjustment
The contrast of the luminance signal can be adjusted by
multiplication with a 6-bit contrast value. The contrast
value corresponds to a gain factor from 0 to 2, where the
value 32 is equivalent to a gain of 1. The contrast can be
adjusted separately for main picture and side picture.
Lin
Lout
Lmin
Lmax
Lt
Ltr
Fig. 2–13: Characteristics of the black level expander
Ltr
BAM
BTHR
BTLT
2.8.2. Black Level Expander
The black level expander enhances the contrast of the
picture. Therefore the luminance signal is modified with
an adjustable, non-linear function. Dark areas of the picture
are changed to black, while bright areas remain unchanged.
The advantage of this black level expander is
that the black expansion is performed only if it will be
most noticeable to the viewer.
The black level expander works adaptively. Depending
on the measured amplitudes ‘Lmin’ and ‘Lmax’ of the lowpass-
filtered luminance and an adjustable coefficient
BTLT, a tilt point ‘Lt’ is established by
Lt = Lmin + BTLT (Lmax – Lmin).
Above this value there is no expansion, while all luminance
values below this point are expanded according
to:
Lout = Lin + BAM (Lin – Lt)
A second threshold, Ltr, can be programmed, above
which there is no expansion. The characteristics of the
black level expander are shown in Fig. 2–13 and Fig.
2–14.
The tilt point Lt is a function of the dynamic range of the
video signal. Thus, the black level expansion is only performed
when the video signal has a large dynamic
range. Otherwise, the expansion to black is zero. This allows
the correction of the characteristics of the picture
tube.

2.8.3. Dynamic Peaking
Especially with decoded composite signals and notch filter
luminance separation, as input signals, it is necessary
to improve the luminance frequency characteristics.
With transparent, high-bandwidth signals, it is
sometimes desirable to soften the image.
In the VDP 31xxB, the luma response is improved by ‘dynamic’
peaking. The algorithm has been optimized regarding
step and frequency response. It adapts to the
amplitude of the high frequency part. Small AC amplitudes
are processed, while large AC amplitudes stay
nearly unmodified.
The dynamic range can be adjusted from 14 to
14 dB for small high frequency signals. There is separate
adjustment for signal overshoot and for signal undershoot.
For large signals, the dynamic range is limited
by a non-linear function that does not create any visible
alias components. The peaking can be switched over to
“softening” by inverting the peaking term by software.

The center frequency of the peaking filter is switchable
from 2.5 MHz to 3.2 MHz. For S-VHS and for notch filter
color decoding, the total system frequency responses
for both PAL and NTSC are shown in figure 2–16.
Transients, produced by the dynamic peaking when
switching video source signals, can be suppressed via
the priority bus.


2.8.4. Digital Brightness Adjustment
The DC-level of the luminance signal can be adjusted by
adding an 8-bit number in the luminance signal path in
front of the softlimiter.
With a contrast adjustment of 32 (gain 1) the signal can
be shifted by 100%. After the brightness addition, the
negative going signals are limited to zero. It is desirable
to keep a small positive offset with the signal to prevent
undershoots produced by the peaking from being cut.
The digital brightness adjustment is separate for main
and side picture.
2.8.5. Soft Limiter
The dynamic range of the processed luma signal must
be limited to prevent the CRT from overload. An appropriate
headroom for contrast, peaking and brightness
can be adjusted by the TV manufacturer according to the
CRT characteristics. All signals above this limit will be
‘soft’-clipped. A characteristic diagram of the soft limiter
is shown in Fig. 2–17. The total limiter consists of three
parts:
Part 1 includes adjustable tilt point and gain. The gain
before the tilt value is 1. Above the tilt value, a part
(0...15/16) of the input signal is subtracted from the input
signal itself. Therefore, the gain is adjustable from 16/16
to 1/16, when the slope value varies from 0 to 15. The
tilt value can be adjusted from 0 to 511.
Part 2 has the same characteristics as part 1. The subtracting
part is also relative to the input signal, so the
total differential gain will become negative if the sum of
slope 1 and slope 2 is greater than 16 and the input signal
is above the both tilt values (see characteristics).
Finally, the output signal of the soft limiter will be clipped
by a hard limiter adjustable from 256 to 511.
2.8.6. Chroma Input
The chroma input signal is a multiplexed CR and CB signal
in 8-bit binary offset code. It can be switched between
normal and inverted signal and between two’s
complement and binary offset code. The delay in respect
to the luminance input can be adjusted in 5 steps
within a range of 2 clock periods.
2.8.7. Chroma Interpolation
A linear phase interpolator is used to convert the chroma
sampling rate from 10.125 MHz (4:2:2) to 20.25 MHz
(4:4:4). All further processing is carried out at the full
sampling rate.

2.8.8. Chroma Transient Improvement
The intention of this block is to enhance the chroma
resolution. A correction signal is calculated by differentiation
of the color difference signals. The differentiation
can be selected according to the signal bandwidth, e.g.
for PAL/NTSC/SECAM or digital component signals,
respectively. The amplitude of the correction signal is
adjustable. Small noise amplitudes in the correction signal
are suppressed by an adjustable coring circuit. To
eliminate ‘wrong colors’, which are caused by over and
undershoots at the chroma transition, the sharpened
chroma signals are limited to a proper value automatically.


2.8.9. Inverse Matrix
A 6-multiplier matrix transcodes the Cr and Cb signals
to R–Y, B–Y, and G–Y. The multipliers are also used to
adjust color saturation in the range of 0 to 2. The coefficients
are signed and have a resolution of 9 bits. There
are separate matrix coefficients for main and side pictures.
The matrix computes:
R–Y MR1*Cb MR2*Cr
G–Y MG1*Cb MG2*Cr
B–Y MB1*Cb MB2*Cr
The initialization values for the matrix are computed
from the standard ITUR (CCIR) matrix:
R
G
B
111
0
0.345
1.773
1.402
0.713
0
Y
Cb
Cr
For a contrast setting of CTM 32, the matrix values are
scaled by a factor of 64, see also table 3–1.
2.8.10. RGB Processing
After adding the post-processed luma, the digital RGB
signals are limited to 10 bits. Three multipliers are used
to digitally adjust the white drive. Using the same multipliers
an average beam current limiter is implemented.
See also section 2.9.1. ‘CRT Measurement and Control’.
2.8.11. OSD Color Lookup Table
The VDP 31xxB has five input lines for an OSD signal.
This signal forms a 5-bit address for a color look-up table
(CLUT). The CLUT is a memory with 32 words where
each word holds a RGB value.
Bits 0 to 3 (bit 4 0) form the addresses for the ROM part
of the OSD, which generates full RGB signals (bit 0 to 2)
and half-contrast RGB signals (bit 3).
Bit 4 addresses the RAM part of the OSD with 16 freely
programmable colors, addressable with bit 0 to 3. The
programming is done via the I2C-bus.
The amplitude of the CLUT output signals can be adjusted
separately for R, G and B via the I2C-bus. The
switchover between video RGB and OSD RGB is done
via the Priority bus.

2.8.12. Picture Frame Generator
When the picture does not fill the total screen (height or
width too small) it is surrounded with black areas. These
areas (and more) can be colored with the picture frame
generator. This is done by switching over the RGB signal
from the matrix to the signal from the OSD color look-up
table.
The width of each area (left, right, upper, lower) can be
adjusted separately. The generator starts on the right,
respectively lower side of the screen and stops on the
left, respectively upper side of the screen. This means,
it runs during horizontal, respectively vertical flyback.
The color of the complete border can be stored in the
programmable OSD color look-up table in a separate
address. The format is 3 4 bit RGB. The contrast can
be adjusted separately.
The picture frame generator includes a priority master
circuit. Its priority is programmable and the border is
generated only if the priority is higher than the priority at
the PRIO bus. Therefore the border can be underlay or
overlay depending on the picture source.
2.8.13. Priority Codec
The priority decoder has three input lines for up to eight
priorities. The highest priority is all three lines at low level.
A 5-bit information is attached to each priority (see
table 3–1 ‘Priority Bus’). These bits are programmable
via the I2C-bus and have the following meanings:
– one of two contrast, brightness and matrix values for
main and side picture
– RGB from video signal or color look-up table
– disable/enable black level expander
– disable/enable peaking transient suppression when
signal is switched
– disable/enable analog fast blank input 1
– disable/enable analog fast blank input 2

2.8.14. Scan Velocity Modulation
The RGB input signal of the SVM is converted to Y in a
simple matrix. Then the Y signal is differentiated by a filter
of the transfer function 1–Z–N, where N is programmable
from 1 to 6. With a coring, some noise can be suppressed.
This is followed by a gain adjustment and an
adjustable limiter. The analog output signal is generated
by an 8-bit D/A converter.
The signal delay can be adjusted by ±3.5 clocks in halfclock
steps. For the gain and filter adjustment there are
two parameter sets. The switching between these two
sets is done with the same RGB switch signal that is
used for switching between video-RGB and OSD-RGB
for the RGB outputs. (See Fig. 2–19).
2.8.15. Display Phase Shifter
A phase shifter is used to partially compensate the
phase differences between the video source and the flyback
signal. By using the described clock system, this
phase shifter works with an accuracy of approximately
1 ns. It has a range of 1 clock period which is equivalent
to ±24.7 ns at 20.25 MHz. The large amount of phase
shift (full clock periods) is realized in the front-end circuit.


2.9. Analog Back End
The digital RGB signals are converted to analog RGBs
using three video digital to analog converters (DAC) with
10-bit resolution. An analog brightness value is provided
by three additional DACs. The adjustment range is 40%
of the full RGB range.
Controlling the whitedrive/analog brightness and also
the external contrast and brightness adjustments is
done via the Fast Processor, located in the front-end.
Control of the cutoff DACs is via I2C-bus registers.
Finally cutoff and blanking values are added to the RGB
signals. Cutoff (dark current) is provided by three 9-bit
DACs. The adjustment range is 60% of full scale RGB
range.
The analog RGB-outputs are current outputs with current-
sink characteristics. The maximum current drawn
by the output stage is obtained with peak white RGB. An
external half contrast signal can be used to reduce the
output current of the RGB outputs to 50%.
2.9.1. CRT Measurement and Control
The display processor is equipped with an 8-bit PDMADC
for all measuring purposes. The ADC is connected
to the sense input pin, the input range is 0 to 1.5V. The
bandwidth of the PDM filter can be selected; it is
40/80 kHz for small/large bandwidth setting. The input
impedance is more than 1 MW

Cutoff and white drive current measurement are carried
out during the vertical blanking interval. They always use
the small bandwidth setting. The current range for the
cutoff measurement is set by connecting a sense resistor
to the MADC input. For the whitedrive measurement,
the range is set by using another sense resistor and the
range select switch 2 output pin (RSW2). During the active
picture, the minimum and maximum beam current
is measured. The measurement range can be set by using
the range select switch 1 pin (RSW1) as shown in
Fig. 2–21 and Fig. 2–22. The timing window of this measurement
is programmable. The intention is to automatically
detect letterbox transmission or to measure the actual
beam current. All control loops are closed via the
external control microprocessor.

In each field two sets of measurements can be taken:
a) The picture tube measurement returns results for
– cutoff R
– cutoff G
– cutoff B
– white drive R or G or B (sequentially)
b) The picture measurement returns data on
– active picture maximum current
– active picture minimum current
The tube measurement is automatically started when
the cutoff blue result register is read. Cutoff control for
RGB requires one field only while a complete white-drive
control requires three fields. If the measurement mode
is set to ‘offset check’, a measurement cycle is run with
the cutoff/whitedrive signals set to zero. This allows to
compensate the MADC offset as well as input the
leakage currents. During cutoff and whitedrive measurements,
the average beam current limiter function (ref.
2.9.3.) is switched off and a programmable value is used
for the brightness setting. The start line of the tube measurement
can be programmed via I2C-bus, the first line
used for the measurement, i.e. measurement of cutoff
red, is 2 lines after the programmed start line.
The picture measurement must be enabled by the control
microprocessor after reading the min./max. result
registers. If a ‘1’ is written into bit 2 in subaddress 25, the
measurement runs for one field. For the next measurement
a ‘1’ has to be written again. The measurement is
always started at the beginning of active video.


The vertical timing for the picture measurement is programmable,
and may even be a single line. Also the signal
bandwidth is switchable for the picture measurement.
Two horizontal windows are available for the picture
measurement. The large window is active for the entire
active line. Tube measurement is always carried out with
the small window.

2.9.2. SCART Output Signal
The RGB output of the VDP 31xxB can also be used to
drive a SCART output. In the case of the SCART signal,
the parameter CLMPR (clamping reference) has to be
set to 1. Then, during blanking, the RGB outputs are automatically
set to 50% of the maximum brightness. The
DC offset values can be adjusted with the cutoff parameters
CR, CG, and CB. The amplitudes can be adjusted
with the drive parameters WDR, WDG, and WDB.

2.9.3. Average Beam Current Limiter
The average beam current limiter (BCL) uses the sense
input for the beam current measurement. The BCL uses
a different filter to average the beam current during the
active picture. The filter bandwidth is approx. 2 kHz. The
beam current limiter has an automatic offset adjustment
that is active two lines before the first cutoff measurement
line.
The beam current limiter function is located in the frontend.
The data exchange between the front-end and the
back-end is done via a single-wire serial interface.
The beam current limiter allows the setting of a threshold
current. If the beam current is above the threshold, the
excess current is low-pass filtered and used to attenuate
the RGB outputs by adjusting the white-drive multipliers
for the internal (digital) RGB signals, and the analog contrast
multipliers for the analog RGB inputs, respectively.
The lower limit of the attenuator is programmable, thus
a minimum contrast can always be set. During the tube
measurement, the ABL attenuation is switched off. After
the white drive measurement line it takes 3 lines to
switch back to BCL limited drives and brightness.

2.9.4. Analog RGB Insertion
The VDP 31xxB allows insertion of 2 external analog
RGB signals. Each RGB signal is key-clamped and inserted
into the main RGB by the fast blank switch. The
selected external RGB input is virtually handled as a
priority bus signal. Thus, it can be overlaid or underlaid
to the digital picture. The external RGB signals can be
adjusted independently as regards DC-level (brightness)
and magnitude (contrast).
Which analog RGB input is selected depends on the fast
blank input signals and the programming of a number of
I2C-bus register settings (see Table 2–3 and Fig. 2–25).
Both fast blank inputs must be either active-low or active-
high.
All signals for analog RGB insertion (RIN1/2, GIN1/2,
BIN1/2, FBLIN1/2, HCS) must be synchronized to the
horizontal flyback, otherwise a horizontal jitter will be visible.
The VDP 31xxB has no means for timing correction
of the analog RGB input signals.

2.9.5. Fast Blank Monitor
The presence of external analog RGB sources can be
detected by means of a fast blank monitor. The status of
the selected fast blank input can be monitored via an I2C
bus register. There is a 2 bit information, giving static and
dynamic indication of a fast blank signal. The static bit is
directly reading the fast blank input line, whereas the dynamic
bit is reading the status of a flip-flop triggered by
the negative edge of the fast blank signal.
With this monitor logic it is possible to detect if there is
an external RGB source active and if it is a full screen insertion
or only a box. The monitor logic is connected directly
to the FBLIN1 or FBLIN2 pin. Selection is done via
I2C bus register.


2.9.6. Half Contrast Control
Insertion of transparent text pages or OSD onto the video
picture is often difficult to read, especially if the video
contrast is high. The VDP 31xxB allows contrast reduction
of the video background by means of a half contrast
input (HCS pin). This input can be supplied with a fast
switching signal (similar to the fast blank input), typically
defining a rectangular box in which the video picture is
displayed with reduced contrast. The analog RGB inputs
are still displayed with full contrast.
The HCS input is multiplexed with the PORT0 input/output
on the same pin, selection is done via I2C-bus register.
If the HCS input is selected, then the port function of
this pin is disabled and writing data into PORT0 will have
no effect. If the HCS input is not selected, the I2C-bus
register bits HCSFOH and HCSPOL must be used to
disable the half contrast function.

2.10. IO Port Expander
The VDP 31xxB provides a general purpose IO port to
control and monitor up to seven external signals. The
port direction is programmable for each bit individually.
Via I2C bus register it is possible to write or read each
port pin. Because of the relatively low I2C bus speed,
only slow or static signals can be handled.
The port signals are multiplexed with other signals to
minimize pin count. PORT0 is multiplexed with the HCS
input signal, PORT1 is multiplexed with the FSY output
signal, PORT[6:2] are multiplexed with the color bus input
COLOR[4:0]. The pin configuration is programmable
via I2C bus register. All register bits can be read back, the
default configuration after reset is input on PORT[1:0]
and COLOR[4:0] enabled.


2.11. Synchronization and Deflection
The synchronization and deflection processing is
distributed over front-end and back-end. The video
clamping, horizontal and vertical sync separation and all
video related timing information are processed in the
front-end. Most of the processing that runs at the horizontal
frequency is programmed on the internal Fast
Processor (FP). Also the values for vertical and East/
West deflection are calculated by the FP software.
The information extracted by the video sync processing
is multiplexed onto the hardware front sync signal (FSY)
and distributed internally to the rest of the video processing
system.
The data for the vertical deflection, the sawtooth and the
East/West correction signal is calculated in the front
end. The data is transferred to the back-end by a single
wire interface.
The display related synchronization, i.e. generation of
horizontal and vertical drive and synchronization of horizontal
and vertical drive to the video timing extracted in
the front-end, are implemented in hardware in the backend.
2.11.1. Deflection Processing
The deflection processing generates the signals for the
horizontal and vertical drive (see Fig. 2–28). This block
contains two phase-locked loops:
– PLL2 generates the horizontal and vertical timing, e.g.
blanking, clamping and composite sync. Phase and
frequency are synchronized by the front sync signal.
– PLL3 adjusts the phase of the horizontal drive pulse
and compensates for the delay of the horizontal output
stage. Phase and frequency are synchronized by the
oscillator signal of PLL2.
The horizontal drive circuitry uses a digital sine wave
generator to produce the exact (subclock) timing for the
drive pulse. The generator runs at 1 MHz; in the output
stage the frequency is divided down to give drive-pulse
period and width. In standby mode, the output stage is
driven from an internal 1 MHz clock that is derived from
the 5 MHz clock signal and a fixed drive pulse width is
used. When the circuit is switched out of standby
operation, the drive pulse width is programmable. The
horizontal drive uses an open drain output transistor.
The Main Sync (MSY) signal that is generated from
PLL3 is a multiplex of all display-related data
(Fig. 2–29). This signal is intended for use by other processors,
e.g. a PIP processor can use this signal to adjust
to a certain display position.
2.11.2. Horizontal Phase Adjustment
This section describes a simple way to align PLL phases
and the horizontal frame position.
1. The parameter NEWLIN in the front-end has to be
adjusted. The minimum possible value is 34 (recommended
for a standard 4:3 signal).
2. With HDRV, the duration of the horizontal drive pulse
has to be adjusted.
3. With POFS2, the clamping pulse for the analog RGB
input has to be adjusted to the correct position, e.g.
the pedestal of the generator signal.
4. With POFS3, the horizontal position of the analog
RGB signal (from SCART) has to be adjusted.
5. With HPOS, the digital RGB output signal (from VPC)
has to be adjusted to the correct horizontal position.
6. With HBST and HBSO, the start and stop values for
the horizontal blanking have to be adjusted.
Note: The processing delay of the internal digital video
path differs depending on the comb filter option of the
VDP 31xxB. The versions with comb filter have an additional
delay of 35 clock cycles. Therefore, the timing of
the external analog RGB signals has to be adjusted (with
POFS2 and POFS3) according to the actual hardware
version of the VDP 31xxB. The hardware version can be
read out via FP subaddress 0xF1.

2.11.3. Vertical and East/West Deflection
The calculations of the vertical and East/West deflection
waveforms is done by the internal Fast Processor (FP).
The algorithm uses a chain of accumulators to generate
the required polynomial waveforms. To produce the
deflection waveforms, the accumulators are initialized at
the beginning of each field. The initialization values must
be computed by the TV control processor and are written
to the front-end once. The waveforms are described as
polynomials in x, where x varies from 0 to 1 for one field.
P: a + b(x–0.5) + c(x–0.5)2 + d(x–0.5)3 + e(x–0.5)4
The initialization values for the accumulators a0..a3 for
vertical deflection and a0..a4 for East/West deflection
are 12-bit values.
The vertical waveform can be scaled according the
average beam current. This is used to compensate the
effects of electric high tension changes due to beam current
variations. In order to get a faster vertical retrace
timing, the output impedance of the vertical
D/A-converter can be reduced by 50% during the retrace.
Fig. 2–30 shows several vertical and East/West deflection
waveforms. The polynomial coefficients are also
stated.
2.11.4. Protection Circuitry
– Picture tube and drive stage protection is provided
through the following measures:
– Vertical flyback protection input: this pin searches for
a negative edge in every field, otherwise the RGB
drive signals are blanked.
– Drive shutoff during flyback: this feature can be selected
by software.
– Safety input pin: this input has two thresholds. Between
zero and the lower threshold, normal functioning
takes place. Between the lower and the higher
threshold, the RGB signals are blanked. Above the
higher threshold, the RGB signals are blanked and the
horizontal drive is shut off. Both thresholds have a
small hysteresis.
– The main oscillator and the horizontal drive circuitry
are run from a separate (standby) power supply and
are already active while the TV set is powering up.


2.12. Reset Function
Reset of most VDP 31xxB functions is performed by the
RESET pin. When this pin becomes active, all internal
registers and counters are lost. When the RESET pin is
released, the internal reset is still active for 4 ms. After
that time, the initialization of all required registers is performed
by the internal Fast Processor. During this initialization
procedure (see Fig. 2–31) it is not possible to access
the VDP 31xxB via the serial interface (I2C).
Access to other ICs via the serial bus is possible during
that time.
The 5 MHz clock divider and the 1 MHz standby clock divider
are not affected by reset. The clock source for the
horizontal output generator is switched to the standby
clock during reset.

2.13. Standby and Power-On
In standby mode the whole signal processing of the VDP
31xxB is disabled and only some basic functions are
working. The standby mode is realized by switching off
the supplies for analog front-end (VSUPF), analog backend
(VSUPO) and digital circuitry (VSUPD). The standby
supply (VSTBY) still has its nominal voltage.
To disable all the analog and digital functions, it is necessary
to bring the analog and digital supplies below 0.5 V.
Only this guarantees that all the normal functions are
disabled and the standby current for analog and digital
supply is at its minimum.
When switched off, the negative slope of the supply
voltage VSUPD should not be larger than approximately
0.2 V/ms (see Recommended Operating Conditions).
In the standby mode, all registers and counter values in
the VDP 31xxB are lost, they will be re-initialized via the
internal Fast Processor after analog and digital supplies
are switched on again and the RESET pin is released.


In the standby mode the following functions are still
available (see also 2.11.1.):
– 20.25 MHz crystal oscillator
– 5 MHz clock output (CLK5)
– horizontal drive output (HOUT)
The clock source for the horizontal output generator is
switched to the standby clock which is derived from the
5 MHz clock. The duty cycle of HOUT is set to 50%.
Protection modes with safety and horizontal flyback pins
are not available.
The VDP 31xxB has clock and voltage supervision circuits
to generate a stable HOUT signal during power-on
and standby. The HOUT signal is disabled until a proper
CLK5 signal (5 MHz clock) is detected. When released,
the HOUT generator runs with the standby clock. Coupling
the HOUT generator to the deflection PLL has to
be done by CCU using the EHPLL bit.

Switching the HOUT signal into standby mode can be
done by the CCU via the EHPLL bit or by the internal voltage
supervision. The voltage supervision activates a
power-down signal when the supply for the digital circuits
(VSUPD) goes below 4.5 V for more than 50ns.
This power down signal is extended by 50ms after
VSUPD is back again. The power-down signal switches
the clock source for the HOUT generation to the standby
clock and sets the duty cycle to 50%. This is exactly what
the EHPLL bit does.
As the clocks from the deflection PLL and the standby
clock are not in phase, the actual phase (High/Low) of
the HOUT signal may be up to one PLL or standby clock
( 1 ms) longer than a regular one when the clock source
is changed.


MSP3400C MSP3411 Multistandard, Sound Processor:

Multistandard Sound Processor
Release Notes: The hardware description in this
document is valid for the MSP 3400C – C8 and newer
codes. Revision bars indicate significant changes
to the previous version.
1. Introduction
The MSP 3400C is designed as single-chip Multistandard
Sound Processor for applications in analog and
digital TV sets, satellite receivers and video recorders.
The MSP-family, which is based on the MSP 2400, demonstrates
the progressive development towards highly
integrated multi-functional ICs.
The MSP 3400C, again, improves function integration:
The full TV sound processing, starting with analog
sound IF signal-in, down to processed analog AF-out, is
performed in a single chip. The IC is produced in 0.8 mm
CMOS technology, combined with high performance
digital signal processing.
The MSP 3400C 0.8 m CMOS version is fully pin and
software compatible to the 1.0 m MSP 3400 and MSP
3410. The main difference between the MSP 3400C and
the MSP 3410, consists of the MSP 3410 being able to
decode NICAM signals.
The MSP 3400C is available in PLCC68, PSDIP64,
PSDIP52, and PQFP80 package.
Note: To achieve compatibility with the functions of MSP
3400 and MSP 3410 (except NICAM), the load sequences
must be programmed as described in the data
sheet of MSP 3410.

MSP 3400C Integrated Functions:
– FM-demodulation of all terrestrial standards (incl. identification decoding)
– FM-demodulation of all satellite standards
– various deemphasis types (incl. Panda1)
– volume, balance, bass, treble, loudness for loudspeaker and headphone output
– automatic volume correction (A.V.C.)
– 5 band graphic equalizer
– subwoofer output alternatively with headphone output
– spatial effect (pseudostereo/basewidth enlargement)
– ADR together with DRP 3510 A
– Dolby ProLogic together with DPL 3418/19/20 A
– 3 pairs of D/A converters
– 1 pair of A/D converters
– SCART switches

2. Features of the MSP 3400C
2.1. Features of the Demodulator and Decoder
Sections
The MSP 3400C is designed to perform demodulation
of FM-mono TV sound and two carrier FM systems according
to the German or Korean terrestrial specs. With
certain constraints, it is also possible to do AM-demodulation
according to the SECAM system. Alternatively, the
satellite specs can be processed with the MSP 3400C.
For FM carrier detection in satellite operation, the AMdemodulation
offers a powerful feature to calculate the
carrier field strength, which can be used for automatic
search algorithms. So, the IC facilitates a first step towards
multistandard capability with its very flexible
application and may be used in TV-sets, satellite tuners,
and video recorders.
The MSP 3400C facilitates profitable multistandard capability,
offering the following advantages:
– two selectable analog inputs (TV and SAT-IF sources)
– Automatic Gain Control (AGC) for analog input: input
range: 0.14 – 3 Vpp
– integrated A/D converter for sound-IF inputs
– all demodulation and filtering is performed on chip and
is individually programmable
– no external filter hardware is required
– only one crystal clock (18.432 MHz) is necessary
– FM carrier level calculation for automatic search algorithms
and carrier mute function
– high deviation FM-mono mode (max. deviation:
approx. 360 kHz)
2.2. Features of the DSP-Section
– flexible selection of audio sources to be processed
– digital input and output interfaces via I2S-Bus for external
DSP-processors, surround sound, ADR etc.
– digital interface to process ADR (Astra Digital Radio)
together with DRP 3510 A
– performance of all deemphasis systems including
adaptive Wegener Panda 1 without external components
or controlling
– digitally performed FM-identification decoding and dematrixing
– digital baseband processing: volume, bass, treble,
5-band equalizer, loudness, pseudostereo, and basewidth
enlargement
– simple controlling of volume, bass, treble, equalizer
etc.
– increased audio bandwidth for FM-Audio-signals
(20 Hz – 15 kHz, 1 dB)
2.3. Features of the Analog Section
– three selectable analog pairs of audio baseband inputs
(= three SCART inputs)
input level: 32 V RMS,
input impedance: .25 kW


– one selectable analog mono input (i.e. AM sound),
input level: 32 V RMS,
input impedance: .10 kW
– two high quality A/D converters, S/N-Ratio: .85 dB
– 20 Hz to 20 kHz Bandwidth for SCART-to-SCARTCopy
facilities
– MAIN (loudspeaker) and AUX (headphones): two
pairs of 4-fold oversampled D/A-converters
output level per channel: max. 1.4 V RMS
output resistance: max. 5 kW
S/N-Ratio: .85 dB at maximum volume
max. noise voltage in mute mode: 310 mV (BW: 20 Hz
...16 kHz)
– one pair of four-fold oversampled D/A-converters supplying
two selectable pairs of SCART-Outputs. Output
level per channel: max. 2 V RMS, output resistance:
max. 0.5 kW, S/N-Ratio: .85 dB
(20 Hz...16 kHz)

3. Application Fields of the MSP 3400C
The MSP 3400C processes TV sound according to the
German and Korean two carrier system and the commonly
used satellite systems. In the following sections,
a brief overview on the German FM-Stereo system
shows what is required of a multistandard audio IC.
3.1. German 2-Carrier System (DUAL FM System)
Since September 1981, stereo and dual sound programs
have been transmitted in Germany using the
2-carrier system. Sound transmission consists of the already
existing first sound carrier and a second sound
carrier additionally containing an identification signal.

4. Architecture of the MSP 3400C
Fig. 4–1 shows a simplified block diagram of the IC. Its
architecture is split into three functional blocks:
1. demodulator section
2. digital signal processing (DSP) section performing
audio baseband processing
3. analog section containing two A/D-converters,
6 D/A-converters, and SCART switching facilities
4.1. Demodulator Block
4.1.1. Analog Sound IF – Input Section
The input pins ANA_IN1+, ANA_IN2+, and ANA_IN–
offer the possibility to connect two different sound IF
sources to the MSP 3400C. By means of bit [8] of
AD_CV (see Table 6–3), either terrestrial or satellite
sound IF signals can be selected. The analog-to-digital
conversion of the preselected sound IF signal is done by
a flash-converter, whose output can be used to control
an automatic gain circuit (AGC), providing optimum level
for a wide range of input levels. It is possible to switch
between automatic gain control and a fixed (setable) input
gain. In the optimum case, the input range of the A/D
converter is completely covered by the sound IF source.
Some combinations of SAW filters and sound IF mixer
ICs, however, show large picture components on their
outputs. In this case, filtering is recommended. It was
found that the high pass filters formed by the coupling
capacitors at pins ANA_IN1+ and ANA_IN2+ as shown
in the application diagram are sufficient in most cases.
4.1.2. Quadrature Mixers
The digital input coming from the integrated A/D converter
may contain audio information at a frequency range
of theoretically 0 to 9 MHz corresponding to the selected
standards. By means of two programmable quadrature
mixers two different audio sources, for example FM1
and FM2, may be shifted into baseband position. In the
following, the two main channels are provided to process
either:
– FM mono (channel 2) or
– FM2 (channel 1) and FM1 (channel 2).
Two independent digital oscillators are provided to generate
two pairs of sin/cos-functions. Two programmable
increments, to be divided up into Low- and High Part, determine
frequency of the oscillator, which corresponds
to the frequency of the desired audio carrier. In section
6.1., format and values of the increments are listed.

4.1.3. Lowpass Filtering Block for Mixed Sound IF
Signals
FM bandwidth limitation is performed by a linear phase
Finite Impulse Response (FIR-filter). Just like the oscillators’
increments, the filter coefficients are programmable
and are written into the IC by the CCU via the control
bus. Two not necessarily different sets of coefficients
are required, one for channel 1 (FM2) and one for channel
2 (FM1=FM-mono). In section 6.2.4., several coefficient
sets are proposed.
4.1.4. Phase and AM Discrimination
The filtered sound IF signals are demodulated by means
of the phase and amplitude discriminator block. On the
output, the phase and amplitude is available for further
processing. AM signals are derived from the amplitude
information, whereas the phase information serves for
FM demodulation.
4.1.5. Differentiators
FM demodulation is completed by differentiating the
phase information output.
4.1.6. Lowpass Filter Block for Demodulated
Signals
The demodulated FM and AM signals are further lowpass
filtered and decimated to a final sampling frequency
of 32 kHz. The usable bandwidth of the final baseband
signals is about 15 kHz.
4.1.7. High Deviation FM Mode
By means of MODE_REG [9], the maximum FM-deviation
can be extended to approximately 360 kHz.
Since this mode can be applied only for the MSPC sound
IF channel 2, the corresponding matrices in the baseband
processing must be set to sound A. Apart from this,
the coefficient sets 380 kHz FIR_REG2 or 500 kHz
FIR_REG2 must be chosen for the FIR_REG_2. For a
given deviation, in relation to the normal FM-mode, the
audio level of the high-deviation mode is reduced by
6 dB.
4.1.8. MSPC-Mute Function in the Dual Carrier FM
Mode
To prevent noise effects or FM identification problems in
the absence of one of the two FM carriers, the
MSP 3400 C offers a carrier detection feature, which
must be activated by means of AD_CV[9]. The mute level
may be programmed by means of AD_CV[10,11].
(see section 6.2.1.) If no FM carrier is available at the
MSPC channel 1, the corresponding channel FM2 is
muted. If no FM carrier is available at the MSPC channel
2, the corresponding channel FM1 is muted. In case of
the absence of both FM carriers, pure noise will be amplified
by the input AGC. Therefore, a proper mute function
depends on the noise quality of the TV set’s IF part
and cannot be guaranteed. The mute function is not recommended
for the satellite mode.

4.2. Analog Section and SCART Switching Facilities
The analog input and output sections offer a wide range
of switching facilities, which are shown in Fig. 4–3. To
design a TV-set with 3 pairs of SCART-inputs and two
pairs of SCART-outputs, no external switching hardware
is required.
The switches are controlled by the ACB bits defined in
the audio processing interface (see section 7. Programming
the Audio Processing Part).
If the MSP 3400C is switched off by first pulling STANDBYQ
low, and then disconnecting the 5 V, but keeping
the 8 V power supply (‘Standby’-mode), the switches
S1, S2, and S3 maintain their position and function. This
facilitates the copying from selected SCART-inputs to
SCART-outputs in the TV-sets standby mode.

In case of power-on start or starting from standby, the IC
switches automatically to the default configuration,
shown in Fig. 4–3. This takes place after the first I2C
transmission into the DFP part. By transmitting the ACB
register first, the default setting mode can be changed.


4.3. MSP 3400C Audio Baseband Processing
By means of the DFP processor, all audio baseband
functions are performed by digital signal processing
(DSP). The DSP functions are grouped into three processing
parts: input preprocessing, channel selection,
and channel postprocessing.
The input preprocessing is intended to prepare the various
signals of all input sources in order to form a standardized
signal at the input to the channel selector. The
signals can be adjusted in volume, are processed with
the appropriate deemphasis, and are dematrixed if necessary.
Having prepared the signals that way, the channel selector
makes it possible to distribute all possible source signals
to the desired output channels.
The ability to route in an external coprocessor for special
effects like surround and sound field processing is of
special importance. Routing can be done with each input
source and output channel via the I2S inputs and outputs.
All input and output signals can be processed simultaneously.
Note that the NICAM input signals are only
available in the MSP 3410 version. While processing the
adaptive deemphasis, no dual carrier stereo (German or
Korean) is possible. Identification values are not valid either.
4.3.1. Dual Carrier FM Stereo/Bilingual Detection
In the German and Korean TV standard, audio information
can be transmitted in three modes: mono, stereo, or
bilingual. To obtain information about the current audio
operation mode, the MSP 3400C detects the so-called
identification signal. Information is supplied via the Stereo
Detection Register to an external CCU.

4.4. Audio PLL and Crystal Specifications
The MSP 3400C runs at 18.432 MHz. A detailed specification
of the required crystal for different packages and
master/slave applications can be found in Table 8.5.2.
The clock supply of the entire system depends on the
MSP 3400C operation mode:
1. FM-Stereo/I2S Master operation:
The system clock runs free on the crystal’s 18.432 MHz.
2. I2S Slave operation:
In this case, the system clock is synchronizing on the
I2S_WS signal, which is fed into the MSP 3400C
(Mode_Reg[3] = 1).
3. D2-MAC operation:
In this case, the system clock is locked to a synchronizing
signal (DMA_SYNC) supplied by the D2-MAC chip
(Mode_Reg[0] = 1). The DMA and the AMU chips can be
driven by the MSP 3400C audio clock (AUD_CL_OUT).
Remark on using the crystal:
External capacitors at each crystal pin to ground are required.
They are necessary for tuning the open-loop frequency
of the internal PLL and for stabilizing the frequency
in closed-loop operation. The higher the
capacitors, the lower the clock frequency results. The
nominal free running frequency should match the center
of the tolerance range between 18.433 and 18.431 MHz
as closely as possible. Due to different layouts of customer
PCBs, the matching capacitor size should be defined
in the application.

 5.3. Start Up Sequence
After power on or RESET, the IC is in an inactive state.
The CCU has to transmit the required coefficient set for
a given operation via the I2C bus. Initialization must start
with the demodulator part. If required for any reason, the
audio processing part can be loaded before the demodulator
part.
The reset pin should not be >0.45 DVSUP (see recommended
operation conditions) before the 5 Volt digital
power supply (DVSUP) and the analog power supply
(AVSUP) are >4.75 Volt and the MSP-Clock is running
(Delay: 2 ms max, 0.5 ms typ.).
This means, if the reset low-high edge starts with a delay
of 2 ms after DVSUP>4.75 Volt and AVSUP>4.75 Volt,
even under worst case conditions, the reset is ok.

 6.4.3. Automatic Search Function for FM-Carrier Detection
The AM demodulation ability of the MSP 3400C offers
the possibility to calculate the “field strength” of the momentarily
selected FM carrier, which can be read out by
the CCU. In SAT receivers, this feature can be used to
make automatic FM carrier search possible.
Therefore, the MSPC has to be switched to AM-mode
(MODE_REG[8]), FM-Prescale must be set to
7Fhex=+127dez, and the FM DC Notch must be switched
off. The sound-IF frequency range must now be
“scanned” in the MSPC-channel 2 by means of the programmable
quadrature mixer with an appropriate incremental
frequency (i.e. 10 kHz).
After each incrementation, a field strength value is available
at the quasi-peak detector output (quasi-peak detector
source must be set to FM), which must be examined
for relative maxima by the CCU. This results in
either continuing search or switching the MSP 3400C
back to FM demodulation mode.
During the search process, the FIR_REG_2 must be
loaded with the coefficient set “AUTOSEARCH”, which
enables small bandwidth, resulting in appropriate field
strength characteristics. The absolute field strength value
(can be read out of “quasi peak detector output FM1”)
also gives information on whether a main FM carrier or
a subcarrier was detected, and as a practical consequence,
the FM bandwidth (FIR_REG_1/2) and the
deemphasis (50 ms or adaptive) can be switched automatically.
Due to the fact that a constant demodulation frequency
offset of a few kHz, leads to a DC-level in the demodulated
signal, a further fine tuning of the found carrier can
be achieved by evaluating the “DC Level Readout FM1”.
Therefore, the FM DC Notch must be switched on, and
the demodulator part must be switched back to FM-demodulation
mode.
For a detailed description of the automatic search function,
please refer to the corresponding MSP 3400C Windows
software.
Note: The automatic search is still possible by evaluating
only the DC Level Readout FM1 (DC Notch On) as
it is described with the MSP 3410, but the above mentioned
method is faster.
6.4.4. Automatic Standard Detection
The AM demodulation abilit

y of the MSP 3400 C enables
a simple method of deciding between standard
B/G (FM-carrier at 5.5 MHz) and standard I (FM-carrier
at 6.0 MHz). It is achieved by tuning the MSP 3400C in
the AM-mode to the two discrete frequencies and evaluating
the field strength via the DC level register or the
quasi-peak detector output.

 

 SAMSUNG MOD:CZ-6844W CHASSIS KS3A  FBT, its bleeder resistor, and device for coupling bleeder resistor



An FBT (fly-back transformer), its bleeder resistor (installed on the top of the FBT), and a device for coupling the bleeder resistor are disclosed. The bleeder resistor 100 is accommodated within a resistor case 180, and the resistor case 180 is installed on the top of an FBT case 110. A resistor pattern 140 is printed on the substrate 130 of the bleeder resistor 100. Openings 150 are formed within the wavy portions of the resistor pattern 140, and the resistor case 180 has a plurality of isolating sheets 160 within its interior 170, so that the isolating sheets 160 can be inserted into the openings 150. When manufacturing the bleeder resistor, the glass coating, the baking, the epoxy resin dipping are eliminated, but the voltage breakdown resisting property is improved. Further, the manufacturing cost is lowered owing to the simplification of the process.



Inventors:
Choi, Dae Sung (KyungKi-do, KR)  Samsung Electro-Mechanics Co., Ltd. (Kyungki-do, KR)

 1. An FBT bleeder resistor coupling device comprising:

a bleeder resistor including a substrate and a resistance pattern on said substrate, said substrate including openings interposed between relatively adjacent portions of said resistance pattern;

a resistor case for receiving said bleeder resistor, said resistor case having isolating sheets positioned for insertion into said openings of said bleeder resistor substrate and for projecting above said bleeder resistor pattern; and

a lid for covering a top of said resistor case, after insertion of said bleeder resistor into said case.


2. The FBT bleeder resistor coupling device as claimed in claim 1, wherein said lid has a plurality of insertion grooves for receiving a plurality of said isolating sheets of said resistor case.

3. The FBT bleeder resistor coupling device as claimed in claim 1, in combination with an FBT case, wherein said resistor case for accommodating said bleeder resistor is formed integrally with said FBT case by an injection molding process.

4. The FBT bleeder resistor coupling device as claimed in claim 1, wherein an interior of said resistor case for accommodating said bleeder resistor is not dipped into an insulating resin.

5. The FBT bleeder resistor coupling device as claimed in claim 1, wherein said isolating sheets are formed integrally in said resistor case.

6. The FBT bleeder resistor coupling device as claimed in claim 1, wherein said substrate has opposite edges and a face extending between said opposite edges, said resistor pattern being disposed on said face, and said openings including alternating first and second openings, said first openings extending from one opposite edge part way across said face and the second opening extending from the other opposite edge part way across said face.

7. The FBT bleeder resistor coupling device as claimed in claim 6, wherein the first and second openings extend more than half way across said face.

8. The FBT bleeder resistor coupling device as claimed in claim 1, wherein said FBT case has side walls, and said isolating sheets extend inwardly from said side walls.

9. The FBT bleeder resistor coupling device as claimed in claim 8, wherein said isolating sheets include alternating first and second sheets, said first sheets extending inwardly from one side wall of said FBT case and the second sheets extending inwardly from another side wall of said FBT case opposite said one side wall.

10. The FBT bleeder resistor coupling device as claimed in claim 9, wherein the first and second sheets extend more than half the distance between said one and another side walls.

11. An FBT comprising:

high voltage and low voltage bobbins, with coils being wound thereon for generating a high voltage;

an FBT case for accommodating said high voltage and low voltage bobbins and filled with an insulating resin;

a bleeder resistor including a resistance pattern;

a bleeder resistor substrate having one or more pair of adjacently disposed first and second openings, said first opening being open at one edge of said substrate, said second opening being open at an opposite edge of said substrate, and a sum total of lengths of said first and second openings being larger than an average width of said substrate between said first and second openings;

said resistance pattern extending wavily between said first and second openings;

a resistor case for receiving said bleeder resistor, and having isolating sheets for being inserted into said openings of said bleeder resistor and projecting above said bleeder resistor; and

a lid for covering a top of said resistor case, after insertion of said bleeder resistor into said case.


12. The FBT as claimed in claim 11, wherein said lid has a plurality of insertion grooves for receiving a plurality of said isolating sheets of said resistor case.

Description:

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to an FBT (fly-back transformer), its bleeder resistor (installed on the top of the FBT), and a device for coupling the bleeder resistor, the FBT being for generating a high voltage in cathode ray tube for use in television, monitor or the like. Particularly, the present invention relates to an FBT, its bleeder resistor, and a device for coupling the bleeder resistor, in which two or more openings are formed adjacently to a resistance pattern on a substrate, and the first and second openings are formed alternately and mutually facingly. Further, the sum total of the lengths of the first and second openings is made larger than the average distance between the first and second openings. Thus, when manufacturing the non-coated bleeder resistor, there are not needed the glass coating, the baking, the dipping into the epoxy resin, and the curing. Notwithstanding, the voltage resistant property is reinforced, and the manufacturing process is simplified. Thus the bleeder resistor can be manufactured in an easy manner with a decreased cost.

2. Description of the Prior Art

Generally, the conventional bleeder resistor is manufactured in the following manner. That is, as shown in FIG. 1, there is prepared a ceramic substrate 10 made of Al2 O3 having a purity of about 96%. Its thickness is about 0.5-1.2 mm, and its area is 400-1500 mm2. Upon the ceramic substrate 10, there is printed PbAg, PtAg, Ag or their combination paste. Then the printed substrate is baked at a temperature of about 800° C., and thus, a printed circuit board is formed, and then lead wires are soldered. Then RuO2 is printed thereupon, and then the structure is baked at a temperature of about 850° C. Thus a resistor having a certain thickness is completed.

Meanwhile, in this resistor, electric current can flow only if the electrical resistance per unit length of the resistor is smaller than the air contact electrical resistivity. In the case where the voltage breakdown resistivity of air is 0.5 KV/mm, if a voltage of 20 KV is supplied across a resistor 12, there has to be secured a distance of 20 KV÷0.5 KV/mm=40 mm. Further, if the thermal degradation and the environmental factors are taken into account, then the safe distance must be 1.8 times as large as the above distance, that is, 40 mm×1.8=72 mm. Meanwhile, in the case where the resistor 12 is printed on the ceramic substrate 10 in a straight line, the length of the ceramic substrate has to be longer, with the result that the total bulk of the ceramic substrate becomes too large.

Therefore, the resistor 12 on the ceramic substrate 10 has to be made curved, so as to reduce the bulk of the ceramic substrate 10. In this case, however, the potential difference over per unit length of the curved pattern exceeds the straight line voltage breakdown resisting distance 0.5 KV/mm. If the environmental factors and the thermal degradation are taken into account, the potential difference per unit length far more exceeds the air voltage breakdown resisting distance, with the result that glow discharges may occur between the curved patterns. Therefore, conventionally after forming the curved resistor, the resistor patterns are insulated by a glass coating, and then, a sealed baking is carried out, thereby preventing the occurrence of the glow discharges.

Meanwhile, although the glass coating can insulate the patterns, the moisture and the thermal impact during the curing of the crystalline epoxy resin weakens the insulation, or damage the bleeder. Therefore, a dipping into the epoxy resin is carried out after the glass coating.

However, the bleeder resistor manufactured in the above method is accompanied by the following disadvantages.

First, the resistor 12 is printed upon the ceramic substrate 10, then a glass coating is carried out, then a baking is carried out, then the epoxy resin 15 is coated, and then its curing is carried out. Therefore, due to this complicated manufacturing process, the productivity is lowered, and the manufacturing cost rises.

Second, the resistor 12 is printed upon the ceramic substrate 10, then a glass coating is carried out to insulate the resistor patterns, then a baking is carried out, then the epoxy resin 15 is coated, and then its curing is carried out. Therefore, the characteristics of the printed resistor 12 are degraded, and the resistance error fluctuation rate is increased.

Third, due to the continued baking, the grains of the resistor are continuously rearranged, and therefore are easily deranged. Therefore, the surface of the resistor becomes rough and sharp, with the result that the resistance against the voltage breakdown steeply drops.

Fourth, the resistance error become higher as described above, and therefore, to cater to the consumers, incomplete products are discarded. Ultimately, the product price has to be decided higher.

Fifth, due to the use of glass and soft epoxy resin, the material cost is increased, with the ultimate result that the price is further increased.

FIGS. 2A-2E illustrate various examples of the conventional bleeder resistors. The total area of the ceramic substrate 10 on which the resistor is printed is dipped into the molten epoxy resin to coat the substrate. FIG. 2A illustrates a bleeder resistor having three lead lines 14, the lead lines being connected by soldering. Therefore, this resistor has the above described disadvantages. FIG. 2B illustrates a bleeder resistor in which the resistor patterns are formed very densely, and only one face of the ceramic substrate is coated.

FIG. 2C illustrates another conventional bleeder resistor in which only a part of one face of the ceramic substrate is coated with silicon. FIG. 2D illustrates a bleeder resistor in which a focus volume substrate is formed integrally, the resistor 12 is coated with an epoxy resin, and an opening is formed at a part of the substrate. FIG. 2E illustrates an example in which the focus volume substrate is integrally formed (it is not a bleeder resistor), and the straight distance between the openings (which are for insulating the patterns) is smaller than the width (W) of the ceramic substrate.

In the above described conventional techniques, there are the above described disadvantages due to the adoption of the glass coating and the soft epoxy coating. Besides, even if there are openings, glow discharges occur between the patterns all the same when the voltage rises to the rated level. Further, as described above, the complicated processes bring the lowering of the workability and the productivity.

SUMMARY OF THE INVENTION

The present invention is intended to overcome the above described disadvantages of the conventional techniques.

Therefore it is an object of the present invention to provide an FBT and its bleeder resistor, in which the glass coating, the baking, the dipping into the epoxy resin, and its curing are all eliminated, but the voltage breakdown resisting property is improved, and the product can be easily manufactured owing to the simplification of the manufacturing process.

It is another object of the present invention to provide a bleeder resistor and a coupling device for the bleeder resistor, in which openings are formed between wavily curved resistor patterns so as to prevent glow discharges at a high voltage, and the bleeder resistor is inserted into a casing to perfectly insulate the resistor patterns, thereby improving the electrical characteristics of the bleeder resistor.

In achieving the above objects, the FBT bleeder resistor according to the present invention includes: a substrate, and a wavily curved resistor pattern formed on the substrate. The FBT bleeder resistor further includes: one or more pairs of openings formed in the substrate, each pair of the openings consisting of a first opening and a second opening; the first opening being open at one edge of the substrate; the second opening being open at an opposite edge of the substrate; the first and second openings extending laterally on the substrate; and a sum total of lengths of the first and second openings being larger than an average width of the substrate between the first and second openings.

In another aspect of the present invention, the FBT bleeder resistor coupling device according to the present invention includes: a bleeder resistor; a resistor case for receiving the bleeder resistor having openings alternately and mutually facingly arranged; isolating sheets formed within the resistor case, for being inserted into the openings of the bleeder resistor, and projecting above the bleeder resistor; and a lid for covering the top of the resistor case, after the insertion of the bleeder resistor into the case.

In still another aspect of the present invention, the FBT according to the present invention includes: high voltage and low voltage bobbins, with coils being wound thereon for generating a high voltage; an FBT case for accommodating the high voltage and low voltage bobbins and filled with an insulating resin; a bleeder resistor including a resistance pattern; a bleeder resistor substrate having one or more pair of adjacently disposed first and second openings, the first opening being open at one edge of the substrate, the second opening being open at the opposite edge of the substrate, and a sum total of lengths of the first and second openings being larger than an average width of the substrate between the first and second openings; the resistance pattern extending wavily between the first and second openings; a resistor case for receiving the bleeder resistor, and having a plurality of isolating sheets for being inserted into the openings of the bleeder resistor and projecting above the bleeder resistor; and a lid for covering the top of the resistor case, after the insertion of the bleeder resistor into the case.

BRIEF DESCRIPTION OF THE DRAWINGS

The above objects and other advantages of the present invention will become more apparent by describing in detail the preferred embodiment of the present invention with reference to the attached drawings in which:

FIG. 1 illustrates the manufacturing process for the general FBT bleeder resistor;

FIGS. 2A-2E illustrate various examples of the bleeder resistors for use on the conventional FBT;

FIG. 3 is an exploded perspective view showing the FBT, the bleeder resistor and the lid according to the present invention;

FIG. 4 is a perspective view showing the bleeder resistor according to the present invention;

FIG. 5 is a perspective view showing another embodiment of the bleeder resistor according to the present invention; and

FIG. 6 is a perspective view showing the lid of the resistor case.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

FIG. 3 is an exploded perspective view showing the FBT, the bleeder resistor and the lid according to the present invention. FIG. 4 is a perspective view showing the bleeder resistor according to the present invention.

Inside the FBT of the present invention, there are high voltage and low voltage bobbins with coils would thereon. An FBT case 110 accommodates the high voltage and low voltage bobbins, and contains an insulating resin for insulating the high voltage and low voltage bobbins. On the top of the FBT case 110, there are installed a resistor case 180. The resistor case 180 accommodates a bleeder resistor 100 which includes a substrate 130 and a resistor pattern 140 formed on the substrate 130. The resistor case 180 is covered with a lid 210.

As shown in FIGS. 4 and 5, the bleeder resistor 100 is formed such that a resistor pattern 140 is printed on the substrate 130, and that first and second openings 150 and 150' are formed alternately mutually facingly within the wavy portions of the resistor pattern 140.

That is, one or more pairs of the first and second openings 150 and 150' are formed adjacently to each other on the substrate 130. The first opening 150 is open at one edge of the substrate 130.

The second opening 150' is open at the opposite edge of the substrate 130, and the first and second openings 150 and 150' are formed laterally in the substrate 130. The sum total (L1 +L2) of the lengths of the first and second openings 150 and 150' is made larger than an average substrate width Ws between the first and second openings 150 and 150'.

As shown in FIG. 3, on the top of the FBT case 110, there is installed a resistor case 180, and the resistor case 180 has a plurality of isolating sheets 160 within the interior 170 of the resistor case 180, so that the isolating sheets 160 can be inserted into the openings 150 and 150'. As shown in FIG. 6, a lid 210 is coupled to the resistor case 180, and has a plurality of insertion grooves 200, so that the lid can be coupled to the resistor case 180. The insertion grooves 200 are formed by the surrounding walls 190.

The present invention constituted as above will now be described as to its action and effects.

As shown in FIGS. 3 to 6, the resistor case 180 is installed on the top of the FBT case 110, and the bleeder resistor 100 is installed within the resistor case 180. On the substrate 130 of the bleeder resistor 100, there is printed a wavy (sweep) resistor pattern 140. Within the adjacent wavy portions of the resistor pattern 140, there are formed openings 150 and 150' of a certain depth, and the openings are for insulation.

As shown in FIG. 4, within the wavy portions of the resistor pattern 140 which is printed on the substrate 130 of the bleeder resistor 100, there are formed at least one or more pairs of the first and second openings 150 and 150'. Further, the first opening 150 is open at one edge of the substrate 130, and the second opening 150' is open at the opposite edge of the substrate 130.

The first and second openings 150 and 150' are formed laterally in the substrate 130, and the sum total (L1 +L2) of the lengths of the first and second openings 150 and 150' is made larger than the average substrate width Ws between the first and second openings 150 and 150'. Thus through between the oppositely open first and second openings 150 and 150', the resistor pattern 140 can be printed in a wavy (sweep) form. Thus sufficient insulating distances are secured, and more reinforced insulation is ensured owing to the openings 150 and 150'.

FIG. 5 is a perspective view showing another embodiment of the bleeder resistor according to the present invention. In this case, the width of the substrate 130 is not constant, but the pairs of the first and second openings 150 and 150' are properly formed laterally in the substrate 130. Further, the sum total (L1 +L2) of the lengths of the first and second openings 150 and 150' is made larger than the average substrate width Ws between the first and second openings 150 and 150'.

As shown in FIG. 3, if the bleeder resistor 100 is to be conveniently installed on the top of the FBT case 110, the resistor case 180 having the isolating sheets 160 has to be installed on the top of the FBT case 110. The resistor case 180 not only secures the bleeder resistor 100 but also reinforces the insulating characteristics of the bleeder resistor 100.

That is, a plurality of the isolating sheets 160 are formed within the resistor case 180, so that the isolating sheets 160 can be precisely mated with the openings 150 and 150'. Thus not only the bleeder resistor 100 can be firmly secured, but also the wavy portions of the printed resistor pattern 140 can be perfectly insulated from each other. Here the height of the isolating sheets 160 has to be larger than the thickness t of the substrate 130.

Meanwhile, as shown in FIG. 6, the lid 210 is for covering the resistor case 180, and the lid 210 has a plurality of surrounding walls 190 to form a plurality of insertion grooves 200. After the bleeder resistor 100 is installed within the resistor case 180, the lid 210 is fitted to the resistor case 180, with the isolating sheets 160 being closely mated with the insertion grooves 200 of the lid 210.

Therefore, if a high voltage is supplied to an input terminal of the resistor pattern 140 (which is printed on the ceramic substrate 130), the voltage drops across the resistor pattern 140. Under this condition, glow discharges do not occur owing to the isolating sheets 160 which come between the wavy portions of the resistor pattern 140.

For example, if a voltage of 20 KV(dc) is supplied to the input terminal 120 of the resistor pattern 140, and if the ceramic substrate 130 has a width of 10 mm and a length of 30 mm, then the total length of the resistor pattern 140 becomes 80 mm. If the air voltage breakdown resisting limit of 0.5 KV/mm and the environmental factors and the thermal degradation are taken into account, then a factor of 1.8 is needed. That is, 0.5 KV/mm÷1.8 KV/mm=0.28 KV/mm has to be maintained, and therefore, 20 KV(dc)÷0.28 KV/mm=71.4 mm is needed. Meanwhile the resistor pattern 140 has a length of 80 mm, and therefore, a sufficient resistance is ensured. Further, the wavy portions of the resistor pattern 140 are isolated by the isolating sheets 160, and therefore, any glow discharge can be prevented.

Thus a perfect insulation is achieved, and therefore, the conventional glass coating becomes needless. Therefore, the bleeder resistor can be used under the air, and therefore, the conventional resin dipping which causes cracks needs not be carried out.

In order to prevent the intrusion of moisture, a final sealing is carried out after installing the bleeder resistor and after fitting the lid 210 to the resistor case 180. The final sealing is carried out by dipping the completed FBT into epoxy resin, thereby perfectly insulating the FBT from the outside. Thus the bleeder resistor is not influenced by the contraction phenomenon of the conventional epoxy resin coating. Further, the final coating such as glass coating and epoxy resin dipping has to be done even on the soldered lead lines. Further, the input terminal 120 and the output terminal 120' of the resistor pattern 140 can be made of a contact spring or an insulating rubber.

According to the present invention as described above, when manufacturing the bleeder resistor of the FBT, the glass coating, the baking, the soft epoxy resin dipping and the curing are eliminated. However, the voltage breakdown resisting property is improved. The simplification of the manufacturing process makes it possible to manufacture the bleeder resistor in an easy manner, and the manufacturing cost is significantly lowered. Further, the openings are formed within the wavy portions of the curved resistor pattern on the substrate, and therefore, any glow discharge can be prevented. The bleeder resistor with the openings formed is accommodated within the resistor case having isolating sheets, in such a manner that the isolating sheets are inserted into the openings of the bleeder resistor. Thus the wavy portions of the curved resistor pattern are perfectly insulated from each other, thereby further improving the electrical characteristics of the bleeder resistor.

References:
5859407    Connecting board for connection between base plate and mounting board    1999-01-12    Saiki et al.    338/307
4829282    High efficiency high heat output electrical heater assembly    1989-05-09    Waugh et al.    338/279
4521761    Small outline potentiometer    1985-06-04    Welch    338/184
4369424    Slide rheostat    1983-01-18    Miyamoto    338/184
3860789    HEATING ELEMENT ASSEMBLY    1975-01-14    Maake    219/532
3588642    N/A    1971-06-28    Fabricius    338/184
3543213    GRID-TYPE RESISTOR    1970-11-24    Weyenberg    338/290
3069598    Modular electronic circuit device    1962-12-18    Darly et al.    338/184
2367170    Heater    1945-01-09    Fahrenwald    219/540

Foreign References:
KR95-011766    May, 1995
KR950011766A    1995-05-16

 Flyback transformer and device for holding bleeder resistor in such transformer
 
  A flyback transformer, used as a high voltage generator for supplying a high voltage to the CRT of a TV receiver or a monitor, and a bleeder resistor holding device for such transformers is disclosed. The bleeder resistor holding device is designed to hold a bleeder resistor at a position between a high voltage bobbin and a low voltage bobbin of the transformer, thus accomplishing compactness and smallness of a focus pack of the transformer. In the flyback transformer of this invention, the bleeder resistor is positioned at a gap defined between the pin terminals of the high voltage bobbin and the low voltage bobbin such that the bleeder resistor is spaced apart from the pin terminal of the low voltage bobbin by a predetermined distance.
 
  Inventors:Cho, Dong Hwan (Hwasung-gun, KR) Samsung Electro-Mechanics Co., Ltd.
 
 1. A flyback transformer, comprising: a high voltage bobbin and a low voltage bobbin, each provided with a pin terminal, in addition to an internal coil used for generating a high voltage; a flyback transformer casing receiving both the high voltage bobbin and the low voltage bobbin, and electrically insulated by an insulating resin; and a bleeder resistor consisting of a ceramic board printed with a resistor pattern on a top surface thereof, said bleeder resistor being positioned at a gap defined between the pin terminals of the high voltage bobbin and the low voltage bobbin such that the bleeder resistor is spaced apart from the pin terminal of said low voltage bobbin by a predetermined distance.

2. The flyback transformer according to claim 1, further comprising a board holding device projecting from at least one of the high voltage bobbin and the low voltage bobbin, said board holding device receiving an end of said ceramic board of the bleeder resistor for holding the bleeder resistor in the flyback transformer.

3. The flyback transformer according to claim 1, wherein the distance between the bleeder resistor and the pin terminal of the low voltage bobbin is not less than 1.0 mm.

4. The flyback transformer according to claim 2, wherein said board holding device consists of first and second holders, respectively projecting from the low voltage bobbin and the high voltage bobbin and receiving opposite ends of said ceramic board of the bleeder resistor to hold the bleeder resistor in the flyback transformer.

5. The flyback transformer according to claim 4, wherein the second holder projecting from the high voltage bobbin is spaced apart from the pin terminal of the low voltage bobbin by at least 2.5 mm, and the distance between the bleeder resistor and the pin terminal of the low voltage bobbin is not less than 2.5 mm.

6. The flyback transformer according to claim 4, wherein the first holder projecting from the low voltage bobbin is spaced apart from the pin terminal of the low voltage bobbin by at least 1.5 mm, and the distance between the bleeder resistor and the pin terminal of the low voltage bobbin is not less than 1.5 mm.

7. A device for holding a bleeder resistor in a flyback transformer including a bleeder resistor consisting of a ceramic board printed with a resistor pattern on a top surface thereof, and a high voltage bobbin and a low voltage bobbin each provided with an internal coil for generating a high voltage, comprising: resistor holding means projecting from at least one of the high voltage bobbin and the low voltage bobbin at a position between pin terminals of the high voltage bobbin and the low voltage bobbin, said holding means receiving an end of said ceramic board of the bleeder resistor for holding the bleeder resistor in the flyback transformer, whereby the bleeder resistor held by the holding means is positioned at a gap defined between the pin terminals of the high voltage bobbin and the low voltage bobbin such that the bleeder resistor is spaced apart from the pin terminal of said low voltage bobbin by a predetermined distance.

8. The device according to claim 7, wherein the resistor holding means consists of first and second holders, respectively projecting from the low voltage bobbin and the high voltage bobbin and receiving opposite ends of said ceramic board of the bleeder resistor to hold the bleeder resistor in the flyback transformer.

9. The device according to claim 8, wherein the second holder projecting from the high voltage bobbin is spaced apart from the pin terminal of the low voltage bobbin by at least 2.5 mm, and the distance between the bleeder resistor and the pin terminal of the low voltage bobbin is not less than 2.5 mm.

10. The device according to claim 8, wherein the first holder projecting from the low voltage bobbin is spaced apart from the pin terminal of the low voltage bobbin by at least 1.5 mm, and the distance between the bleeder resistor and the pin terminal of the low voltage bobbin is not less than 1.5 mm.

Description:
BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The present invention relates, in general, to flyback transformers used as high voltage generators for supplying high voltages to the CRTs of TV receivers or monitors and, more particularly, to a flyback transformer having a structurally improved bleeder resistor holding structure, which is designed to hold a bleeder resistor at a position between a high voltage bobbin and a low voltage bobbin of the flyback transformer, thus accomplishing compactness and smallness of a focus pack of the transformer.

[0003] 2. Description of the Prior Art

[0004] FIG. 1 is a perspective view, showing the construction of a conventional bleeder resistor for flyback transformers (hereinbelow, referred to simply as “FBT”). As shown in the drawing, the bleeder resistor consists of a focus pack board 110 and a bleeder resistor board 170. The FBT focus pack board 110 is printed on its top surface with two screen focus resistor patterns 120 and 130. Two screen focus voltage output terminals 140 are provided at the centers of the two resistor patterns 120 and 130, respectively. In addition, two screen focus voltage input terminals 150 are provided at the outer ends of the two resistor patterns 120 and 130, respectively. The bleeder resistor board 170, printed on its top surface with a resistor pattern 160, is positioned at a side of the focus pack board 110, and is connected to the focus pack board 110, thus forming a bleeder resistor.

 

 

 

 

[0005] FIG. 2 shows a conventional structure for holding such a bleeder resistor in an FBT. As shown in the drawing, the bleeder resistor 207 is held in an EBT by both a resistor holder 205 formed in a focus pack 201 and a resistor insert groove 204 formed in an FBT casing 203. A high voltage bobbin 208 is inserted in the FBT casing 203. However, this bleeder resistor holding structure is problematic in that it is necessary to secure additional space in the focus pack 203 for holding the bleeder resistor 207. Therefore, this holding structure fails to accomplish the recent trend of compactness or smallness of the focus pack 201.

 

 

 

 

 

 

 

[0006] In an effort to overcome the above-mentioned problem, an FBT of FIG. 3 having a structurally improved bleeder resistor holding structure has been used. The FBT of FIG. 3 is disclosed in Korean Utility Model Publication No. 87-4463. In this FBT, a resistor holder 303 is integrally formed at a coil separating wall 302 of a high voltage bobbin 301, with a resistor holding channel 305 formed in the resistor holder 303. A bleeder resistor 304 is inserted in the holding channel 305 of the holder 303 such that the resistor 304 is positioned at a side of the high voltage bobbin 301 while extending outside the bobbin 301 in an axial direction of the bobbin 301. This bleeder resistor holding structure is advantageous in that it accomplishes smallness of the FBT. However, this structure is problematic in that the bleeder resistor 304 may interfere with the high voltage output coils of the high voltage bobbin 301. The above holding structure also undesirably increases the length of the bleeder resistor 304 by the length of the bobbin 301, thus enlarging the size of the bleeder resistor 304 and increasing the production cost of the bleeder resistors.

[0007] In an effort to accomplish compactness and smallness of FBTs, in addition to providing a stable structure for holding the bleeder resistors in the FBTs, an FBT having another bleeder resistor holding structure of FIG. 4 was proposed. This FBT is disclosed in Japanese Patent laid-open Publication No. Heisei. 7-75339. In this FBT, a bleeder resistor 401 consisting of a plurality of small boards is held on a high voltage bobbin 403 while being connected to the high voltage output coils 405 and the diodes 407 of the bobbin 403. Since this FBT uses the bleeder resistor 401 consisting of the small-sized boards, it is possible to accomplish compactness and smallness of the FBTs, in addition to providing a stable structure for holding the bleeder resistor 401 in the FBT without causing interference of the bleeder resistor 401 with the high voltage output coils 405 of the high voltage bobbin 403. However, since the small boards of the

bleeder resistor 401 are held at positions between the high voltage output coils 405 and the diodes 407 of the bobbin 403, it is difficult to produce the EBT. Another problem of this FBT resides in that it is necessary to provide a complex circuit for connecting the small boards of the bleeder resistor 401 to the high voltage output coils 405 and the diodes 407 of the bobbin 403.

[0008] Therefore, it has been required to provide a bleeder resistor holding structure for FBTs, which accomplishes compactness and smallness of the FBTS, stably holds bleeder resistors in the FBTs while allowing the bleeder resistors to have a desired size, and easily receives a bleeder resistor when installing the bleeder resistor in an FBT.
SUMMARY OF THE INVENTION

[0009] Accordingly, the present invention has been made keeping in mind the above problems occurring in the prior art, and an object of the present invention is to provide a bleeder resistor holding device for FBTs, which holds a bleeder resistor at a gap defined between a high voltage bobbin and a low voltage bobbin of an FBT, thus accomplishing compactness and smallness of the FBT and reducing the production cost of the FBT, and which easily receives the bleeder resistor when installing the bleeder resistor in the FBT.

[0010] Another object of the present invention is to provide a bleeder resistor holding device for FBTs, which stably holds a bleeder resistor in an FBT at a gap defined between the high voltage bobbin and the low voltage bobbin.

[0011] A further object of the present invention is to provide an FBT having such a bleeder resistor holding device.

[0012] In order to accomplish the above objects, the present invention provides a flyback transformer, comprising: a high voltage bobbin and a low voltage bobbin, each provided with a pin terminal, in addition to an internal coil used for generating a high voltage; an FBT casing receiving both the high voltage bobbin and the low voltage bobbin, and electrically insulated by an insulating resin; and a bleeder resistor consisting of a ceramic board printed with a resistor pattern on the top surface thereof, the bleeder resistor being positioned at a gap defined between the pin terminals of the high voltage bobbin and the low voltage bobbin such that the bleeder resistor is spaced apart from the pin terminal of the low voltage bobbin by a predetermined distance.

[0013] The present invention also provides a device for holding a bleeder resistor in such a flyback transformer, comprising: a resistor holding means projecting from at least one of the high voltage bobbin and the low voltage bobbin at a position between pin terminals of the high voltage bobbin and the low voltage bobbin, the holding means receiving an end of the ceramic board of the bleeder resistor for holding the bleeder resistor in the flyback transformer, whereby the bleeder resistor held by the holding means is positioned at a gap defined between the pin terminals of the high voltage bobbin and the low voltage bobbin such that the bleeder resistor is spaced apart from the pin terminal of the low voltage bobbin by a predetermined distance.
BRIEF DESCRIPTION OF THE DRAWINGS

[0014] The above and other objects, features and other advantages of the present invention will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0015] FIG. 1 is a perspective view showing the construction of a conventional bleeder resistor for flyback transformers, including a focus pack board and a bleeder resistor board;

[0016] FIG. 2 is an exploded perspective view of an FBT having a bleeder resistor holding structure according to an embodiment of the prior art;

[0017] FIG. 3 is a view of an FBT having a bleeder resistor holding structure according to another embodiment of the prior art;

[0018] FIG. 4 is a perspective view of an FBT having a bleeder resistor holding structure according to a further embodiment of the prior art;

[0019] FIG. 5 is an exploded perspective view, showing the construction of a high voltage bobbin and a low voltage bobbin of an FBT having a bleeder resistor holding device in accordance with the preferred embodiment of the present invention;

[0020] FIG. 6 is a perspective view of the low voltage bobbin of the FBT having a first holder of the bleeder resistor holding device according to this invention;

[0021] FIGS. 7a and 7b are views showing the construction of the low voltage bobbin of this invention in more detail, in which:

[0022] FIG. 7a is a front view of the low voltage bobbin; and

[0023] FIG. 7b is a side view of the low voltage bobbin;

[0024] FIGS. 8a and 8b are views of the high voltage bobbin of the FBT having a second holder of the bleeder resistor holding device according to this invention, in which:

[0025] FIG. 8a is a view of the high voltage bobbin; and

[0026] FIG. 8b is a view of the second holder of the bleeder resistor holding device; and

[0027] FIGS. 9a and 9b are views of the assembled FBT, with a bleeder resistor installed in the FBT by the bleeder resistor holding device of this invention, in which:

[0028] FIG. 9a is a front view of the FBT; and

[0029] FIG. 9b is a plan view of the FBT.
DETAILED DESCRIPTION OF THE INVENTION

[0030] Reference now should be made to the drawings, in which the same reference numerals are used throughout the different drawings to designate the same or similar components.

[0031] FIG. 5 is an exploded perspective view showing a high voltage bobbin and a low voltage bobbin of an FBT in accordance with the preferred embodiment of this invention. FIG. 6 is a perspective view of the low voltage bobbin having a first holder of a bleeder resistor holding device according to this invention. FIGS. 7a and 7b are views showing the construction of the low voltage bobbin of this invention in more detail. FIGS. 8a and 8b are views of the high voltage bobbin having a second holder of the bleeder resistor holding device according to this invention. FIGS. 9a and 9b are views of the FBT, with a bleeder resistor installed in the FBT by the bleeder resistor holding device of this invention.

[0032] As shown in the drawings, a high voltage bobbin 3 of the FBT is a hollow cylindrical body having a pin terminal 5 at one end thereof, and axially receives a low voltage bobbin 1 therein. The low voltage bobbin 1 has a first holder 2, while the high voltage bobbin 3 has a second holder 4. The first and second holders 2 and 4 project from the low voltage bobbin 1 and the high voltage bobbin 3, respectively, and form a bleeder resistor holding device of this invention. The two holders 2 and 4 of the bleeder resistor holding device receive the opposite ends of a bleeder resistor, thus holding the bleeder resistor in the FBT.

[0033] The construction of the first and second holders 2 and 4 are shown in detail in FIGS. 6 to 8b. As shown in FIGS. 6, 7a and 7b, the first holder 2 is formed on the low voltage bobbin 1 at a position under a pin terminal 5. This first holder 2 has a box shape, which is formed by top and bottom walls and has a channel defined between the top and bottom walls so as to receive one end of the bleeder resistor board. The bottom wall of the first holder 2 is slit along its central axis from the outer edge to a predetermined length, thus more easily receiving the bleeder resistor board in the channel of the first holder 2. The above first holder 2 is preferably formed at a position around the pin terminal 5, at which a voltage output coil is connected to the low voltage bobbin 1.

[0034] FIGS. 8a and 8b show the second holder 4 formed at the high voltage bobbin 3. As shown in FIG. 8a, the second holder 4 is formed on the high voltage bobbin 3 at a position above an output cable terminal 7. This holder 4 has a channel for receiving the other end of the bleeder resistor board. In a detailed description, the second holder 4 is formed on the high voltage bobbin 3 at a position corresponding to the first holder 2 of the low voltage bobbin 1, and so the opposite ends of the bleeder resistor board are inserted into the channels of the first and second holders 2 and 4, respectively.

[0035] In the present invention, the first and second holders 2 and 4 may be integrally formed on the bobbins 1 and 3. Alternatively, the holders 2 and 4 may be produced separate from the bobbins 1 and 3 prior to being attached to the bobbins 1 and 3 using an appropriate means, such as bonding agent or setscrews. The first and second holders 2 and 4 must be designed such that the bleeder resistor is spaced apart from the pin terminal 5 of the low voltage bobbin 1 by a predetermined distance when the board of the bleeder resistor is inserted at its opposite ends into the two holders 2 and 4. That is, when the low voltage bobbin 1 is assembled with the high voltage bobbin 3 into a single body, the bleeder resistor must be positioned at a gap defined between the pin terminals of the two bobbins 1 and 3. In such a case, the bleeder resistor must be spaced apart from the pin terminals of the bobbins 1 and 3 by the distance so as to prevent any interference of the bleeder resistor with the pin terminals.

[0036] The distance between the bleeder resistor and the pin terminal 5 of the low voltage bobbin 1 is preferably set to at least 1.0 mm. In order to accomplish the above object, the first holder 2 is preferably spaced apart from the pin terminal 5 of the low voltage bobbin 1 by at least 1.0 mm. In an operation of the FBT, a high voltage of about 10˜12 kV is typically generated at the bleeder resistor set in the first holder 2, while a low voltage of only several hundred volts is generated at the pin terminal 5 of the low voltage bobbin 1. Therefore, there is a potential difference of about 10˜12 kV between the first holder 2 and the pin terminal 5 of the low voltage bobbin 1, and so it is necessary to space the first holder 2 from the pin terminal 5 by at least 1.0 mm, and electrically insulate the pin terminal 5 from the first holder 2 by filling an epoxy resin in the gap between the first holder 2 and the pin terminal 5. Since the insulating power of the epoxy resin is at least 12 kV per 1 mm thickness, the epoxy resin filled in the gap between the first holder 2 and the pin terminal 5 effectively insulates the pin terminal 5 from the first holder 2. In the present invention, it is more preferable to space the first holder 2 from the pin terminal 5 of the low voltage bobbin 1 by at least 1.5 mm. In such a case, the distance between the bleeder resistor and the pin terminal 5 of the low voltage bobbin 1 is set to at least 1.5 mm.

[0037] The second holder 4 of the high voltage bobbin 3 is preferably spaced apart from the pin terminal 5 of the low voltage bobbin 1 by at least 2.5 mm. In an operation of the FBT, a high voltage of about 25˜30 kV is typically generated at the bleeder resistor set in the second holder 4, and so there is a potential difference of about 25˜30 kV between the second holder 4 and the pin terminal 5. It is thus necessary to space the pin terminal 5 from the second holder 4 by at least 2.5 mm, and insulate the pin terminal 5 from the second holder 4 by filling an epoxy resin in the gap between the second holder 4 and the pin terminal 5. In such a case, the epoxy resin, the insulation power of which is at least 12 kV per 1 mm thickness, effectively insulates the pin terminal 5 from the second holder 4.

[0038] FIGS. 9a and 9b are views of the assembled FBT, with a bleeder resistor installed in the FBT by the bleeder resistor holding device of this invention. The operational effect of the bleeder resistor holding device of this invention will be described herein below with reference to FIGS. 9a and 9b.

[0039] As shown in FIGS. 9a and 9b, in order to fabricate an FBT, the low voltage bobbin 1 having the first holder 2 is assembled with the high voltage bobbin 3 having the second holder 4 into a single body. In such a case, the board of a bleeder resistor 9 is inserted at its opposite ends into the holders 2 and 4 such that the bleeder resistor 9 is spaced apart from the pin terminal 5 of the low voltage bobbin 1 by a predetermined distance due to the specified positions of the two holders 2 and 4. The assembled bobbins 1 and 3 with the bleeder resistor 9 are inserted into an FBT casing 11 prior to injecting an epoxy resin into desired portions for accomplishing insulating effect. Thereafter, a ferrite core and a high voltage cable are set in the FBT casing 11, thus completely fabricating a desired FBT.

[0040] As shown in FIG. 9b, the bleeder resistor 9 is positioned at the gap defined between the pin terminals of the low voltage bobbin 1 and the high voltage bobbin 3. In such a case, the bleeder resistor 9 is installed in the FBT casing 11 without being exposed to the outside of the FBT casing 11. Due to the holders 2 and 4 formed on the bobbins 1 and 3, it is not necessary to secure additional space for installing the bleeder resistor in the FBT, and so compactness and smallness of the FBT is accomplished. Particularly, the bleeder resistor holding device of this invention desirably simplifies the structure of an FBT focus pack, and so it is possible to more effectively accomplish compactness and smallness of FBTs.

[0041] As described above, the present invention provides a bleeder resistor holding device for FBTs, which is designed to hold a bleeder resistor at a gap defined between a high voltage bobbin and a low voltage bobbin of an FBT. The bleeder resistor holding device of this invention thus accomplishes compactness and smallness of the FBTs and reduces the production cost of the FBTs, in addition to easily receiving the bleeder resistor when installing the bleeder resistor in an FBT.

[0042] Although a preferred embodiment of the present invention has been described for illustrative purposes, those skilled in the art will appreciate that various modifications, additions and substitutions are possible, without departing from the scope and spirit of the invention as disclosed in the accompanying claims.


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