GRUNDIG ST70-900 DOLBY ELEGANCE 70 CHASSIS CUC2032 INTERNAL VIEW.

GRUNDIG ST70-900 DOLBY ELEGANCE 70  CHASSIS  CUC2032 Switched-mode power supply control circuit: Siemens Function and Application of the Switch Mode Powersupply IC TDA4605;

 A controller for a switch mode power supply includes an undervoltage protection circuit responsive to an input supply voltage indicative signal. The input supply voltage indicative signal is also coupled to a foldback point correction circuit. The correction circuit causes a decrease in a maximum duty cycle of a control signal when the input supply voltage increases and is still smaller than a predetermined magnitude. A zener diode limits the input supply voltage indicative signal in a manner to prevent a further decrease in the duty cycle when the input supply voltage exceeds the predetermined magnitude.

1. A switch mode power supply, comprising: a source of an input supply voltage;
a switch responsive to a first control signal having a controllable duty cycle and coupled to said source of input supply voltage for generating an output supply voltage, in accordance with said duty cycle of said first control signal;

a duty cycle modulator responsive to a second control signal for generating said first control signal and for controlling said duty cycle of said first control signal in accordance therewith, said modulator being responsive to a signal that is indicative of said input supply voltage for decreasing said duty cycle when said input supply voltage increases; and
a limiter coupled to said modulator for limiting the decrease in duty cycle, for a given increase in said input supply voltage, when said input supply voltage exceeds a first magnitude.


2. A power supply according to claim 1, wherein said duty cycle of said first control signal varies within a control range, in accordance with said second control signal, and wherein said limiter limits a decrease of said duty cycle when said duty cycle is at an end of said control range.

3. A power supply according to claim 1, wherein said limiter comprises a clamper coupled in a signal path of said input supply voltage indicative signal for clamping said input voltage indicative signal, when said input supply voltage exceeds said first magnitude, and for disabling the clamping thereof, when said input supply voltage does not exceed said first magnitude.

4. A power supply according to claim 3, wherein said voltage clamper comprises a diode.

5. A power supply according to claim 3, further comprising a disabling circuit responsive to said input supply voltage indicative signal for disabling said output supply voltage, when said input supply voltage is smaller than a second magnitude and wherein said voltage clamper is coupled in a common signal path of said input supply voltage indicative signal with respect to each of an input of said disabling circuit and an input of said limiter.

6. A power supply according to claim 1, wherein said modulator comprises a foldback point corrector for decreasing said duty cycle, when said input supply voltage increases and wherein said limiter is coupled to said corrector.

7. A power supply according to claim 1, wherein said second control signal is produced in a feedback path for regulating said output supply voltage.

8. A power supply according to claim 1, wherein said input supply voltage indicative signal is coupled to said modulator from said source of input supply voltage via a signal path that bypasses said switch.

9. A power supply according to claim 8, wherein said limiter comprises a clamp coupled in said signal path for clamping said input supply voltage indicative signal, when said input supply voltage exceeds said first magnitude, and for disabling the clamping operation, when said input supply voltage does not exceed said first magnitude.

10. A power supply, comprising: an input supply voltage, a transformer and a switch coupled for switch mode generation of a regulated output supply voltage, said switch being responsive to a first control signal having a controllable duty cycle;
a duty cycle modulator for generating said first control signal responsive to a second control signal for limiting a duty cycle of said switch, said modulator operating in a first mode when said second control signal is in a predetermined range of voltage levels and operating in a second mode when said second control signal is outside of said range; and
a voltage monitor circuit for generating said second control signal, said second control signal representing a first proportion of said input supply voltage in a first range of input supply voltage values and a second proportion of said input supply voltage in a second range of input supply voltage values.


11. A power supply according to claim 10 wherein said voltage monitor circuit comprises a clamp coupled in a signal path of said second control signal.

12. A power supply according to claim 11, wherein said second signal is coupled to said modulator from said input supply voltage via a signal path that bypasses said switch.

13. A power supply, comprising: an input supply voltage, a transformer and a switch coupled for switch mode generation of a regulated output supply voltage, said switch being responsive to a first control signal having a controllable duty cycle;
a duty cycle modulator for generating said first control signal responsive to a second control signal, said modulator operating in a first mode when said second control signal is in a predetermined range of voltage levels and operating in a second mode when said second control signal is outside of said range; and
a voltage monitor circuit for generating said second control signal, said second control signal representing a first proportion of said input supply voltage in a first range of input supply voltage values and a second proportion of said input supply voltage in a second range of input supply voltage values, such that as long as said input supply voltage is in said first range of input supply voltage values, said second control signal varies when said input supply voltage varies and said modulator operates in said first mode of operation.


14. A power supply, comprising: an input supply voltage, a transformer and a switch coupled for switch mode generation of a regulated output supply voltage, said switch being responsive to a first control signal having a controllable duty cycle;
a duty cycle modulator for generating said first control signal responsive to a second control signal, said modulator operating in a first mode when said second control signal is in a predetermined range of voltage levels and operating in a second mode when said second control signal is outside of said range; and
a nonlinear voltage divider circuit coupled to said input supply voltage for generating said second control signal, said second control signal representing a first proportion of said input supply voltage in a first range of input supply voltage values and a second proportion of said input supply voltage in a second range of input supply voltage values.

Description:

The invention relates to a switch mode power supply control circuit.
Switched-mode power supplies efficiently generate a variety of regulated voltages from a single line voltage level (e.g., 220 volts AC). One important use of these power supplies is within a television signal receiver where they are used to produce a regulated B+ voltage for the horizontal deflection circuit as well as other regulated voltages for powering various digital and analog circuits.
Typically, a switched-mode power supply contains a full-wave rectifier, a power supply controller, a switch, and an output transformer. The switch is typically a high-power transistor such as a MOSFET. To regulate the output voltages, the controller activates and deactivates (e.g., pulse width modulates) the gate of the transistor in response to power supply loading and other control parameters. The switched voltage from the transistor drives a primary winding of the transformer, while various power supply loads are connected to one or more secondary windings. As such, the power supply converts an AC input voltage into one or more DC voltages.
One particular controller is an integrated circuit available from Siemens as Model TDA 4605. This power supply controller is typically used to drive the MOSFET transistor, which in turn drives the primary coil of the transformer. This specific integrated circuit, as well as others used in the art, typically contain a control mechanism that disables the power supply when the input voltage drops below a pre-defined voltage level. Such protection is necessary because, to produce regulated output voltages, the switched-mode power supply increases the duty cycle of the control signal driving the transistor as the input voltage decreases. At some point, the input voltage decreases to a level where the output of the power supply is unregulated (e.g., the maximum pulse length is used to drive the transistor). Such unregulated operation can damage the power supply electronics, but is more likely to damage the load electronics.

For the integrated circuit (IC) TDA4605, as defined in the TDA4605 Technical Manual available from Siemens AG, dated Jul. 27, 1989, pin 3 of the integrated circuit is used for sensing or monitoring the primary input voltage (vp) for the power supply (e.g., the rectified AC voltage). The threshold voltage for disabling or deactivating the integrated circuit, and thus the power supply, is pre-established by the controller at one volt. As such, the primary input voltage (vp) is reduced using a voltage divider at the input of pin 3. By selecting appropriate resistor values within the voltage divider, a nominal value of monitoring voltage is applied to pin 3. Typically, this voltage is approximately 2.0 volts for a primary input voltage of 120 volts. When the primary input voltage falls to a level that causes the monitoring voltage at pin 3 to fall below one volt, the power supply is deactivated to avoid unregulated operation.
As stated above, this form of switched-mode power supply has been finding use within television signal receivers. However, television receivers, in particular, present peculiar loading characteristics to a power supply. Specifically, a television receiver power supply is called upon to produce a regulated B+ voltage, typically of approximately 140 volts, as well as a low voltage DC level of 16 volts for powering all of the digital and analog circuitry within the receiver. When the television receiver is switched from stand-by to run mode, a heavy load is produced by the in-rush of current into filter capacitors connected to the regulated B+ voltage. This heavy load causes the power supply to temporarily operate in an unregulated (maximum pulse width) mode, and may cause the primary input voltage to drop to a low level. Furthermore, when the degaussing circuit is activated to degauss the cathode ray tube (CRT), the main AC supply voltage is depressed due to the substantial load presented by the degaussing circuit. Consequently, the drop in line voltage could typically cause the monitoring voltage to drop below the 1 volt, first threshold level, and as such, to disable the power supply.
Therefore, there it is desirable to produce a monitoring voltage indicative of the primary input voltage, but to insure that the power supply will not be deactivated for the expected heavy loads found in a television receiver.

The IC TDA 4605 includes a foldback point correction circuit that reduces the maximum duty cycle of the MOSFET control signal, when the monitoring voltage exceeds a second threshold level of approximately 1.7 V. The monitoring voltage is applied to the correction circuit also via pin 3.
In a circuit embodying an inventive feature, a resistive voltage divider that produces the monitoring input or sense signal from the primary input voltage is designed such that the first threshold level is not attained during the expected temporary loading of the primary input voltage. However, such a voltage divider results in a higher voltage being applied to the monitoring voltage input of the controller during normal operation of the power supply. As such, an increase of the primary input voltage to a higher level, which is still within the acceptable tolerance range of the AC line voltage, can cause the monitoring voltage to rise to a level that exceeds the second threshold level at which the integrated circuit begins to limit the maximum duty cycle of the control signal that controls the MOSFET, i.e., the controller applies a foldback correction technique. When the second threshold level is exceeded, the power supply automatically limits the output power of the power supply for an increase in the primary voltage. As a result of the voltage divider design that provides sufficient headroom to overcome loading generated drop outs in the primary input voltage, the maximum power supply output could be, undesirably, significantly reduced at high primary input voltage.
In carrying out an inventive feature, to insure that such inconsequential increase in the primary input voltage does not cause the power supply to significantly reduce the maximum duty cycle of the control signal and thereby, the power output of the power supply, a zener diode is coupled to the voltage divider. The zener diode limits the magnitude of the monitoring voltage to a level that avoids further maximum duty cycle limiting when the primary input voltage further increases. Consequently, when the power supply is used in a television signal receiver, the voltage divider provides enough head room for the primary voltage to drop substantially due to degaussing circuit activation or other loading conditions, while the zener diode insures that the primary voltage can rise above its nominal voltage without causing a significant power limitation of the power supply output.
A switch mode power supply, embodying an aspect of the invention, includes a source of an input supply voltage. A switch is responsive to a first control signal having a controllable duty cycle and coupled to the source of input supply voltage for generating an output supply voltage, in accordance with the duty cycle of the first control signal. A duty cycle modulator is responsive to a second control signal for generating the first control signal and for controlling the duty cycle of the first control signal in accordance therewith in a manner to control the current pulses. An increase in the duty cycle produces an increase in a magnitude of the current pulses. The modulator is responsive to a signal that is indicative of the input supply voltage for decreasing the duty cycle when the input supply voltage increases. A limiter is coupled to the modulator for limiting the decrease in duty cycle, for a given increase in said input supply voltage, when the input supply voltage exceeds a first magnitude.

FIG. 1 depicts a schematic diagram of a switched-mode power supply incorporating the teachings of the present invention.

FIG. 1 depicts a schematic diagram of a switched-mode power supply 100 incorporating the present invention. The embodiment shown is designed for use as a power supply for a television signal receiver, wherein the power supply generates a regulated B+ voltage (e.g., 140 volts) and a low voltage (e.g., 16 volts). The regulated B+ voltage is used to power a horizontal deflection circuit and the regulated low voltage is used to power the digital and analog electronics (continuous load 118). Other applications for the power supply may require slight variation in the depicted components and their interconnections; however, such variations are well within the scope of the present invention.
The power supply contains a number of major components, including a full-wave rectifier 102, the power supply controller 106, a MOSFET transistor Q1, a monitor voltage generator 110, an output transformer 112, and a plurality of circuit components used to complete the power supply electronics. Illustratively, the input to the power supply is a 110-volt AC, 60 hertz voltage.
Rectifier 102 is a conventional full-wave bridge rectifier coupled to an AC input voltage source 101. The output of the bridge rectifier 102 is coupled to capacitor C1 approximately 680 μF). A voltage RAW B+ forms raw (unregulated) B+ voltage (also referred to herein as the primary input voltage vp) having a nominal value of approximately 150 volts. Capacitor C1, connected from the output of the rectifier to ground, smoothes the voltage from the bridge rectifier such that a DC voltage, i.e., the primary input voltage vp, is available at the upper terminal of the transformer's primary winding W₁.
The primary input voltage forms an input to the monitor voltage generator 110 which produces a monitor voltage VZ1 for the controller 106. The monitor voltage generator is discussed in detail below.
The controller is illustratively a TDA4605 power supply controller available from Siemens AG of Munich, Germany. The eight pins of the controller are connected to signals and voltages that enable the controller to produce a pulse width or duty cycle modulated signal at pin five for controlling the duty cycle of the transistor Q1. Specifically, pin 4 of controller 106 is grounded. Pin 3 is coupled to the monitor voltage.
Pin 2 is supplied information concerning the primary current. A primary current increase in the primary winding W₁ is simulated as a voltage rise of a periodical, ramp voltage VC2 at pin 2 using an external RC element formed by resistor R3, capacitor C2, and resistor R4 (where R3 is approximately 360 kΩ, C2 is approximately 6,800 pF; and R4 is approximately 220 Ω). These elements are connected in series from the primary input voltage to ground. Pin 2 of the controller 106 is coupled to the junction of R3 and C2. A pulse width modulator 106c of the controller 106 controls the duration of the forward phase, and thus, the primary peak current, using ramp voltage VC2 that is proportional to the drain current of the transistor Q1. As indicated before, the ramp voltage is derived from the primary input voltage using the RC elements connected to pin 2, i.e., the ramp voltage simulates the primary current. Controller pin 1 is supplied secondary voltage information which internally compares the control voltage sampled from the regulating winding W3 of the transformer 112 and compares that sample voltage with an internal reference voltage.
Pin 5 generates a duty cycle modulated control signal or voltage VOUT via a push-pull output driver for rapid charge and discharge of the input capacitance of a MOSFET power transistor Q1 (Model IRF740).
Pin 6 is coupled to the supply voltage for the controller. Pin 7 forms a soft start input terminal. Capacitor C5 (0.1 μF) is connected from pin 7 to ground to reduce the pulse duration during start-up. Lastly, pin 8 is the input pin for the oscillator feedback.
In operation, the transistor Q1 is used as a power switch controlled by the controller 106. A snubber circuit is connected to the drain of the transistor Q1. The snubber circuit contains a combination of diode D3, resistor R16 and capacitor C12, which together limit the voltage overshoot when the transistor is turned off. D3 is a MUR450 diode, C12 is a 1000 pF capacitor, and R16 is a 2-watt, 30 kΩ resistor.
Together with the stray capacitance of the transformer, capacitor C7 (470 pF connected from drain terminal to ground) determines the no-load frequency, and consequently, the maximum slew rate of the drain voltage for a transistor Q1.
Transistor Q1 is driven with pulse width modulated signal VOUT produced at pin 5 of controller 106 and coupled to the gate terminal of the transistor via resistor R11 (35 Ω). Furthermore, a capacitor C6 (4700 pF) is coupled from the source terminal to the drain terminal. The source terminal is coupled to ground through resistor R13 (0.27 KΩ). Resistor R12 (10 kΩ) is optionally connected between the source terminal and gate terminal to ensure that the transistor will not be activated if power is applied to the power supply without the controller 106 being installed. The drain terminal is coupled to one terminal of the primary winding W1 of transformer 112. Consequently, the transistor Q1 controls the current flow from the primary input voltage through the primary winding.
The secondary circuit of the transformer 112 consists of several windings, each of which has a different number of turns, polarity, and load capacity. Specifically, winding W2 forms the output voltage for the regulated B+, while winding W4 forms the output winding for the regulated 16-volt low voltage output, and winding W3 generates the feedback voltage for the controller 106.
The load circuitry includes, connected to winding W2, an output diode D4 and capacitor C13 that couple power to the horizontal deflection circuit 116. Additionally, the center tap of the output secondary winding is connected to ground, and winding W4 is coupled to diode D5 and capacitor C14. This output is the 16 volts that powers the continuous load 118 of the television receiver, e.g., all of the electronics and integrated circuits. This circuit 118 also controls the timing of when the degaussing circuit 114 is activated using degaussing control line 120. The control line for the continuous load is the run/standby control signal that essentially turns the television receiver on and off. The continuous load circuitry 118 is also coupled to the horizontal deflection circuit 116 to provide control signals therefor.
The controller 106 is started up using resistor R17 (100 KΩ) as a start resistor. As such, capacitor C11 (100 μF) is charged with half-wave currents at the voltage supply pin of the controller 106, e.g., pin 6. These half-wave currents are supplied from the primary input voltage through resistor R17 (100 KΩ) to ground through series connected resistor R14 (202 Ω), diode D2 (148 Ω) and regulating winding W3. When the voltage at C11 reaches the switch-on threshold, the switched-mode power supply begins to function and supplies the feedback voltage, via winding W3, resistor R14 and diode D2. This feedback voltage, when rectified by diode D2 and smoothed by capacitor C11, forms the supply voltage (v_cc) for the controller 106 via pin 6.
A control signal or voltage VCT for pin 1 is generated in a circuit parallel to the controller supply voltage circuit. The control voltage is produced by diode D1 (ERB43) charging capacitor C3 (1.5 μF) through resistor R8 (10 Ω). The RC element, consisting of series connected R15 (30 Ω) and C10 (0.01 μF), prevents peak value rectification of high frequency components of the feedback signal.
More specifically, regulating winding W3 is coupled to one terminal of resistor R15. The other terminal of resistor R15 is coupled to capacitor C10 to ground. Diode D1 is connected at the junction of resistor R15 and capacitor C10. Capacitor C9 (1000 pF) is connected in parallel with diode D1. Diode D1 has an output voltage that is coupled to series connected R8 and C3 which couples the output of the diode to ground. The output of the diode is also coupled through resistive divider network R6 and R7 which are respectively connected in series to ground. The voltage at the junction of R6 and R7 forms control voltage VCT and is coupled to pin 1 of the controller 106. These resistors define the no-load frequency of oscillation of the controller 106. Therefore, they are typically 0.1% accurate resistors having R6 being 5.49 KΩ, and R7 being 174 Ω. Control voltage VCT is coupled to a pulse-width modulator 106c within controller 106 that controls the duty cycle modulation of voltage VOUT for regulating, for example, voltage REGB+.
During the power supply start-up, capacitor C5 at the soft-start pin (e.g., pin 7), influences the duration of the forward phase by controlling the error voltage of the pulse width modulator. The controller detects the end of the transformer discharge phase via resistor R10 (20 KΩ) that is coupled at one end to controller pin 8 and at the other end to resistor R14, and ultimately to the regulating winding W3. Additionally, capacitor C8 (0.022 μF) is coupled from the junction of R10 and R14 to ground. At this point, the voltage changes polarity from positive to negative, i.e., the voltage represents zero crossings.
A voltage VZ1, embodying an inventive feature, is generated by the monitor voltage generator 110 and is coupled to pin 3 of the controller 106. Voltage VZ1 is used both for determining the minimum line voltage that will allow the power supply to operate and for controlling a foldback point correction circuit 106b within the controller 106.
The monitor voltage generator 110 contains resistor R1 (270 kΩ) coupled in series with resistor R2 (5100 Ω) to form a resistive voltage divider network with respect to primary input voltage RAW B+. The junction of the two resistors is coupled to the pin 3 of controller 106. Furthermore, a zener diode Z1 (B2X55/C3VO), embodying an inventive feature, is connected in parallel with resistor R2 from the junction point to ground. Zener diode Z1 forms a limiter for limiting the maximum voltage across R2 to the breakdown voltage of the zener diode Z1. Consequently, the voltage at the output of the monitor voltage generator 110 tracks the primary input voltage RAW B+ up to the threshold point where the zener diode Z1 begins to conduct.
The controller 106 includes an under-voltage detector 106a that uses a fixed, internal voltage threshold that causes the controller to disable the power supply whenever the monitor voltage VZ1 drops below a first threshold voltage. For the TDA 4605 integrated circuit, this first threshold voltage is one volt. As such, the divider network of R1 and R2 defines a voltage at the output that under typical operation would not cause the controller to deactivate the power supply.
In one particular application, e.g., a television signal receiver, a degaussing circuit 114 for a television signal receiver is typically connected directly across the input AC power. Consequently, when the degaussing circuit is activated, it will typically cause a drop in the AC voltage that is applied to the input of the voltage rectifier 102. Consequently, the primary input voltage RAW B+ will drop significantly during the degaussing period. Since this is a normal behavior of a conventional television receiver circuit, it is desirable that the monitor voltage generator 110 be designed such that the controller 106 will not deactivate the power supply during the degaussing period.
For a primary input voltage of 120 volts and using a resistive divider of 270 KΩ for R1 and 5100 Ω for R2, the nominal voltage VZ1 at the voltage monitor input pin is 2 volts. Such a value for the voltage monitor voltage will avoid power supply deactivation during the degaussing period or other heavy load period.
When the duty cycle of voltage VOUT is at the maximum as a result of an overload condition, an increase in voltage RAW B+, produced by an increase in the AC line voltage, causes the voltage across primary winding w₁ to increase. As the primary input voltage RAW B+ rises, the available input power to the power supply increases which could damage the power supply when the power supply is overloaded. During a period of overloaded, unregulated output, the modulator 106c generates the voltage VOUT having a maximum duty cycle for driving transistor Q1. As a result, a primary current IP in winding W₁ of transformer 112 has also a maximum duty cycle. Therefore, undesirably an increase in voltage RAW B+ can produce a large voltage across the transistor that could damage the transistor or other circuitry.
To maintain the power supply within a safe operation range, the controller 106 includes what is known as a foldback or overload point correction circuit 106b. This foldback point correction circuit reduces the maximum duty cycle of voltage VOUT when the primary input voltage exceeds a predetermined magnitude. An increase above the predetermined magnitude causes the foldback point correction circuit 106b to decrease the maximum duty cycle of signal VOUT as voltage RAW B+ increases. The decrease is done by generating a correction current ICOR that is coupled to capacitor C2 causing an increase in the rate of change of voltage VC2 at pin 2 of controller 106 when voltage VZ1 exceeds a second threshold voltage.
When voltage RAW B+ increases and causes voltage VZ1 to further increase above the second threshold voltage an increase in current ICOR produces a decrease in the maximum duty cycle of signal VOUT, in a well know manner. The second threshold voltage occurs when voltage VZ1 is above a voltage level of approximately 1.7 V. The result is that, when voltage RAW B+ further increases the maximum duty cycle decreases proportionally. The decrease in the maximum duty cycle tends to stabilize the maximum power produced in the power supply against an increase of voltage RAW B+. On the other hand, an increase of voltage VZ1 when voltage VZ1 is below the 1.7 V level, does not affect current ICOR and the duty cycle of voltage VOUT.
Because the divider network (R1 and R2) establishes a sufficiently large monitor voltage VZ1 that provides sufficient headroom for preventing power supply shutdown when the degaussing circuit is activated, primary input voltage RAW B+ may be at a level that causes voltage VZ1 to exceed the second threshold voltage of circuit 106b by an excessive amount even when voltage RAW B+ is within the normal tolerance range. Therefore, disadvantageously, the maximum duty cycle may further decrease by a significant amount in a manner to lower the maximum power that can be derived. Such significant reduction in power capability can occur even though primary input voltage is not truly at such a high level that could damage the power supply.
In accordance with an inventive feature, to prevent current ICOR from further reducing the maximum duty cycle of voltage VOUT when voltage RAW B+ increases above a threshold magnitude that corresponds to voltage VZ1 being equal to 3 V, the monitor voltage generator 110 contains the zener diode Z1 operating as a limiter which limits the primary input voltage indicative voltage VZ1 to 3 V. Consequently, the monitor voltage VZ1 can never rise above a pre-defined level (e.g., 3 volts) that would otherwise cause the foldback point correction circuit 106b within the controller 106 to further decrease the maximum duty cycle. In this way, advantageously, the decrease in the maximum duty cycle as a function of an increase in voltage RAW B+ is limited.
The decrease in the duty cycle of voltage VOUT produced by current ICOR, for a given increase in voltage RAW B+, is limited when voltage RAW B+ is greater than a threshold magnitude that corresponds to voltage VZ1 equal to 3 V. In contrast, the decrease in the duty cycle produced by current ICOR is not limited but varies proportionally to voltage RAW B+ when voltage VZ1 is between 1.7 V and 3 V. Thus, zener diode Z1 operates as a limiter for limiting the decrease in the duty cycle when the voltage RAW B+ exceeds the threshold magnitude relative to when voltage RAW B+ does not exceed the threshold magnitude. An increase in voltage RAW B+ that produces voltage VZ1 below the second threshold voltage of 1.7 V, does not affect current ICOR.
Specifically, for the TDA 4605 integrated circuit control, the zener diode has a value of three volts. Consequently, the input signal to the monitor voltage generator cannot rise above the three volt level before the zener diode will begin to conduct current to ground. As such, the monitor voltage generator establishes a range of voltages that pre-defines a range of primary input voltages at which the controller 106 operates in a normal manner that avoids both an undervoltage power supply deactivation and a further decrease in the maximum duty cycle. The input voltage dynamic range is thereby extended.

 

GRUNDIG ST70-900 DOLBY ELEGANCE 70  CHASSIS  CUC2032 TDA4605-3 Control IC for Switched-Mode Power Supplies usingMOS-Transistor


The IC TDA 4605-3 controls the MOS-power transistor and performs all necessary control and
protection functions in free running flyback converters. Because of the fact that a wide load range
is achieved, this IC is applicable for consumer as well as industrial power supplies.
The serial circuit and primary winding of the flyback transformer are connected in series to the input
voltage. During the switch-on period of the transistor, energy is stored in the transformer. During the
switch-off period the energy is fed to the load via the secondary winding. By varying switch-on time
of the power transistor, the IC controls each portion of energy transferred to the secondary side
such that the output voltage remains nearly independent of load variations. The required control
information is taken from the input voltage during the switch-on period and from a regulation winding
during the switch-off period. A new cycle will start if the transformer has transferred the stored
energy completely into the load.

In the different load ranges the switched-mode power supply (SMPS) behaves as follows:
No load operation
The power supply is operating in the burst mode at typical 20 to 40 kHz. The output voltage can be
a little bit higher or lower than the nominal value depending of the design of the transformer and the
resistors of the control voltage divider.
Nominal operation
The switching frequency is reduced with increasing load and decreasing AC-voltage.
The output voltage is only dependent on the load.
Overload point
Maximal output power is available at this point of the output characteristic.
Overload
The energy transferred per operation cycle is limited at the top. Therefore the output voltages
declines by secondary overloading.


Circuit Description
Application Circuit
The application circuit shows a flyback converter for video recorders with an output power rating of
70 W. The circuit is designed as a wide-range power supply for AC-line voltages of 180 to 264 V.
The AC-input voltage is rectified by the bridge rectifier GR1 and smoothed by C1 . The NTC limits
the rush-in current.
In the period before the switch-on threshold is reached the IC is suppled via resistor R 1 ; during the
start-up phase it uses the energy stored in C2 , under steady state conditions the IC receives its
supply voltage from transformer winding n1 via diode D1. The switching transistor T1 is a BUZ 90.
The parallel connected capacitor C3 and the inductance of primary winding n 2 determine the
system resonance frequency. The R 2-C4-D2 circuitry limits overshoot peaks, and R 3 protects the
gate of T1 against static charges.
During the conductive phase of the power transistor T1 the current rise in the primary winding
depends on the winding inductance and the mains voltage. The network consisting of R 4-C5 is used
to create a model of the sawtooth shaped rise of the collector current. The resulting control voltage
is fed into pin 2 of the IC. The RC-time constant given by R 4-C5 must be designed that way that
driving the transistor core into saturation is avoided.
The ratio of the voltage divider R 10/R 11 is fixing a voltage level threshold. Below this threshold the
switching power supply shall stop operation because of the low mains voltage. The control voltage
present at pin 3 also determines the correction current for the fold-back point. This current added to
the current flowing through R 4 and represents an additional charge to C5 in order to reduce the turnon
phase of T1. This is done to stabilize the fold-back point even under higher mains voltages.
Regulation of the switched-mode power supplies via pin 1. The control voltage of winding n1 during
the off period of T1 is rectified by D3, smoothed by C6 and stepped down at an adjustable ratio by
R 5 , R 6 and R 7 . The R 8-C7 network suppresses parasitic overshoots (transformer oscillation). The
peak voltage at pin 2, and thus the primary peak current, is adjusted by the IC so that the voltage
applied across the control winding, and hence the output voltages, are at the desired level.
When the transformer has supplied its energy to the load, the control voltage passes through zero.
The IC detects the zero crossing via series resistors R 9 connected to pin 8. But zero crossings are
also produced by transformer oscillation after T1 has turned off if output is short-circuited. Therefore
the IC ignores zero crossings occurring within a specified period of time after T1 turn-off.
The capacitor C8 connected to pin 7 causes the power supply to be started with shorter pulses to
keep the operating frequency outside the audible range during start-up.
On the secondary side, five output voltages are produced across winding n3 to n7 rectified by D4 to
D8 and smoothed by C9 to C13 . Resistors R 12 , R 14 and R 19 to R 21 are used as bleeder resistors.
Fusable resistors R 15 to R 18 protect the rectifiers against short circuits in the output circuits, which
are designed to supply only small loads.

Pin 1
The regulating voltage forwarded to this pin is compared with a stable internal reference voltage VR
in the regulating and overload amplifier. The output of this stage is fed to the stop comparator. If
the control voltage is rather small at pin 1 an additional current is added by means of current source
which is controlled according the level at pin 7. This additional current is virtually reducing the
control voltage present at pin 1.
Pin 2
A voltage proportional to the drain current of the switching transistor is generated there by the
external RC-combination in conjunction with the primary current transducer. The output of this
transducer is controlled by the logic and referenced to the internal stable voltage V2B . If the voltage
V2 exceeds the output voltage of the regulations amplifier, the logic is reset by the stop comparator
and consequently the output of pin 5 is switched to low potential. Further inputs for the logic stage
are the output for the start impulse generator with the stable reference potential VST and the
supply voltage motor.
Pin 3
The down divided primary voltage applied there stabilizes the overload point. In addition the logic is
disabled in the event of low voltage by comparison with the internal stable voltage VV in the primary
voltage monitor block.
Pin 4
Ground
Pin 5
In the output stage the output signals produced by the logic are shifted to a level suitable for MOSpower
transistors.
Pin 6
From the supply voltage V6 are derived a stable internal references VREF and the switching
threshold V6A , V6E , V6 max and V6 min for the supply voltage monitor. All references values (VR ,
V2B , VST) are derived from VREF . If V6 > VVE , the VREF is switched on and switched off when V6 <
V 6A . In addition, the logic is released only for V6 min < V6 < V6 max .
Pin 7
The output of the overload amplifier is connected to pin 7. A load on this output causes a reduction
in maximal impulse duration. This function can be used to implement a soft start, when pin 7 is
connected to ground by a capacitor.

Pin 8
The zero detector controlling the logic block recognizes the transformer being discharged by
positive to negative zero crossing of pin 8 voltage and enables the logic for a new pulse. Parasitic
oscillations occurring at the end of a pulse cannot lead to a new pulse (double pulsing), because an
internal circuit inhibits the zero detector for a finite time tUL after the end of each pulse.
Start-Up Behaviour
The start-up behaviour of the application circuit per sheet 88 is represented an sheet 90 for a line
voltage barely above the lower acceptable limit time t0 the following voltages built up:
– V6 corresponding to the half-wave charge current over R1
– V2 to V2 max (typically 6.6 V)

– V3 to the value determined by the divider R 10/R 11 .
The current drawn by the IC in this case is less than 1.6 mA.
If V6 reaches the threshold V6E (time point t1), the IC switches on the internal reference voltage. The
current draw max. rises to 12 mA. The primary current- voltage reproducer regulates V2 down to V2B
and the starting impulse generator generates the starting impulses from time point t5 to t6 . The
feedback to pin 8 starts the next impulse and so on. All impulses including the starting impulse are
controlled in width by regulating voltage of pin 1. When switching on this corresponds to a shortcircuit
event, i.e. V1 = 0. Hence the IC starts up with "short-circuit impulses" to assume a width
depending on the regulating voltage feedback (the IC operates in the overload range). The IC
operates at the overload point. Thereafter the peak values of V2 decrease rapidly, as the starting
attempt is aborted (pin 5 is switched to low). As the IC remains switched on, V6 further decreases
to V6 . The IC switches off; V6 can rise again (time point t4) and a new start-up attempt begins at
time point t1 . If the rectified alternating Iine voltage (primary voltage) collapses during load, V3 can
fall below V3A , as is happening at time point t3 (switch-on attempt when voltage is too low). The
primary voltage monitor then clamps V3 to V3S until the IC switches off (V6 < V6A). Then a new startup
attempt begins at time point t1 .

Regulation, Overload and No-Load Behaviour
When the IC has started up, it is operating in the regulation range. The potential at pin 1 typically is
400 mV. If the output is loaded, the regulation amplifier allows broader impulses (V5 = H). The peak
voltage value at pin 2 increases up to V2S max . If the secondary load is further increased, the
overload amplifier begins to regulate the pulse width downward. This point is referred to as the
overload point of the power supply. As the IC-supply voltage V6 is directly proportional to the
secondary voltage, it goes down in accordance with the overload regulation behaviour. If V6 falls
below the value V6 min , the IC goes into burst operation. As the time constant of the half-wave
charge-up is relatively large, the short-circuit power remains small. The overload amplifier cuts back
to the pulse width tpk . This pulse width must remain possible, in order to permit the IC to start-up
without problems from the virtual short-circuit, which every switching on with V1 = 0 represents. If
the secondary side is unloaded, the loading impulses (V5 = H) become shorter. The frequency
increases up to the resonance frequency of the system. If the load is further reduced, the secondary
voltages and V6 increase. When V6 = V6 max the logic is blocked. The IC converts to burst
operation.This renders the circuit absolutely safe under no-load conditions.
Behaviour when Temperature Exceeds Limit
An integrated temperature protection disables the logic when the chip temperature becomes too
high. The IC automatically interrogates the temperature and starts as soon as the temperature
decreases to permissible values.





GRUNDIG ST70-900 DOLBY ELEGANCE 70  CHASSIS  CUC2032 CNY17F-1 6-PIN DIP OPTOCOUPLERS FOR POWER SUPPLY APPLICATIONS (NO BASE CONNECTION):

 FEATURES
The MOC810X and CNY17F-X devices consist of a gallium arsenide LED optically coupled to a silicon phototransistor in a dual-in-
line package.
•
Closely Matched Current Transfer Ratio (CTR) Minimizes Unit-to-Unit Variation
•
Narrow (CTR) Windows that Translate to a Narrow and Predictable Open Loop Gain Window
•
Very Low Coupled Capacitance along with No Chip to Pin 6 Base Connection for Minimum Noise Susceptibility
•
To order devices that are tested and marked per VDE 0884 requirements, the suffix “.300” must be included at the end
of part number. e.g. MOC8101.300 VDE 0884 is a test option.
APPLICATIONS
•
Switchmode Power Supplies (Feedback Control)
•
AC Line/Digital Logic Isolation
•
Interfacing and coupling systems of different potentials and impedances.



GRUNDIG ST70-900 DOLBY ELEGANCE 70  CHASSIS  CUC2032 PHILIPS TDA8843 I2C-bus controlled PAL/NTSC/SECAM TV processor: 

GENERAL DESCRIPTION:
The various versions of the TDA 884X/5X series are
I2C-bus controlled single chip TV processors which are
intended to be applied in PAL, NTSC, PAL/NTSC and
multi-standard television receivers. The N2 version is pin
and application compatible with the N1 version, however,
a new feature has been added which makes the N2 more
attractive. The IF PLL demodulator has been replaced by
an alignment-free IF PLL demodulator with internal VCO
(no tuned circuit required). The setting of the various
frequencies (33.4, 33.9, 38, 38.9, 45,75 and 58.75 MHz)
can be made via the I2C-bus.
Because of this difference the N2 version is compatible
with the N1, however, N1 devices cannot be used in an
optimised N2 application.
Functionally the IC series is split up is 3 categories, viz:
· Versions intended to be used in economy TV receivers
with all basic functions (envelope: S-DIP 56 and QFP
64)
· Versions with additional features like E-W geometry
control, H-V zoom function and YUV interface which are
intended for TV receivers with 110° picture tubes
(envelope: S-DIP 56)
· Versions which have in addition a second RGB input
with saturation control and a second CVBS output
(envelope: QFP 64)
FUNCTIONAL DESCRIPTION
Vision IF amplifier
The IF-amplifier contains 3 ac-coupled control stages with
a total gain control range which is higher then 66 dB. The
sensitivity of the circuit is comparable with that of modern
IF-IC’s.
The video signal is demodulated by means of an
alignment-free PLL carrier regenerator with an internal
VCO. This VCO is calibrated by means of a digital control
circuit which uses the X-tal frequency of the colour
decoder as a reference. The frequency setting for the
various standards (33.4, 33.9, 38, 38.9, 45.75 and 58.75
MHz) is realised via the I2C-bus. To get a good
performance for phase modulated carrier signals the
control speed of the PLL can be increased by means of the
FFI bit.
The AFC output is generated by the digital control circuit of
the IF-PLL demodulator and can be read via the I2C-bus.
For fast search tuning systems the window of the AFC can
be increased with a factor 3. The setting is realised with the

AFW bit. The AFC data is valid only when the horizontal
PLL is in lock (SL = 1)
Depending on the type the AGC-detector operates on
top-sync level (single standard versions) or on top sync
and top white- level (multi standard versions). The
demodulation polarity is switched via the I2C-bus. The
AGC detector time-constant capacitor is connected
externally. This mainly because of the flexibility of the
application. The time-constant of the AGC system during
positive modulation is rather long to avoid visible variations
of the signal amplitude. To improve the speed of the AGC
system a circuit has been included which detects whether
the AGC detector is activated every frame period. When
during 3 field periods no action is detected the speed of the
system is increased. For signals without peak white
information the system switches automatically to a gated
black level AGC. Because a black level clamp pulse is
required for this way of operation the circuit will only switch
to black level AGC in the internal mode.
The circuits contain a video identification circuit which is
independent of the synchronisation circuit. Therefore
search tuning is possible when the display section of the
receiver is used as a monitor. However, this ident circuit
cannot be made as sensitive as the slower sync ident
circuit (SL) and we recommend to use both ident outputs
to obtain a reliable search system. The ident output is
supplied to the tuning system via the I2C-bus.
The input of the identification circuit is connected to pin 13
(S-DIP 56 devices), the “internal” CVBS input (see Fig.6).
This has the advantage that the ident circuit can also be
made operative when a scrambled signal is received
(descrambler connected between pin 6 (IF video output)
and pin 13). A second advantage is that the ident circuit
can be used when the IF amplifier is not used (e.g. with
built-in satellite tuners).
The video ident circuit can also be used to identify the
selected CBVS or Y/C signal. The switching between the
2 modes can be realised with the VIM bit.

Video switches
The circuits have two CVBS inputs (internal and external
CVBS) and a Y/C input. When the Y/C input is not required
the Y input can be used as third CVBS input. The switch
configuration is given in Fig.6. The selection of the various
sources is made via the I2C-bus.
For the TDA 884X devices the video switch configuration
is identical to the switch of the TDA 8374/75 series. So the
circuit has one CVBS output (amplitude of 2 VP-P for the
TDA 884X series) and the I2C-bus control is similar to that
of the TDA 8374/75. For the TDA 885X IC’s the video
switch circuit has a second output (amplitude of 1 VP-P)
which can be set independently of the position of the first
output. The input signal for the decoder is also available on
the CVBS1-output.
Therefore this signal can be used to drive the Teletext
decoder. If S-VHS is selected for one of the outputs the
luminance and chrominance signals are added so that a
CVBS signal is obtained again.
Sound circuit
The sound bandpass and trap filters have to be connected
externally. The filtered intercarrier signal is fed to a limiter
circuit and is demodulated by means of a PLL
demodulator. This PLL circuit tunes itself automatically to
the incoming carrier signal so that no adjustment is
required.
The volume is controlled via the I2C-bus. The deemphasis
capacitor has to be connected externally. The
non-controlled audio signal can be obtained from this pin
(via a buffer stage).
The FM demodulator can be muted via the I2C-bus. This
function can be used to switch-off the sound during a
channel change so that high output peaks are prevented.
The TDA 8840/41/42/46 contain an Automatic Volume
Levelling (AVL) circuit which automatically stabilises the
audio output signal to a certain level which can be set by
the viewer by means of the volume control. This function
prevents big audio output fluctuations due to variations of
the modulation depth of the transmitter. The AVL function
can be activated via the I2C-bus.
Synchronisation circuit
The sync separator is preceded by a controlled amplifier
which adjusts the sync pulse amplitude to a fixed level.
These pulses are fed to the slicing stage which is operating
at 50% of the amplitude. The separated sync pulses are
fed to the first phase detector and to the coincidence
detector. This coincidence detector is used to detect
whether the line oscillator is synchronised and can also be
used for transmitter identification. This circuit can be made
less sensitive by means of the STM bit. This mode can be
used during search tuning to avoid that the tuning system
will stop at very weak input signals. The first PLL has a
very high statical steepness so that the phase of the
picture is independent of the line frequency.
The horizontal output signal is generated by means of an
oscillator which is running at twice the line frequency. Its
frequency is divided by 2 to lock the first control loop to the
incoming signal. The time-constant of the loop can be
forced by the I2C-bus (fast or slow). If required the IC can
select the time-constant depending on the noise content of
the incoming video signal.
The free-running frequency of the oscillator is determined
by a digital control circuit which is locked to the reference
signal of the colour decoder. When the IC is switched-on
the horizontal output signal is suppressed and the
oscillator is calibrated as soon as all sub-address bytes
have been sent. When the frequency of the oscillator is
correct the horizontal drive signal is switched-on. To obtain
a smooth switching-on and switching-off behaviour of the
horizontal output stage the horizontal output frequency is
doubled during switch-on and switch-off (slow start/stop).
During that time the duty cycle of the output pulse has such
a value that maximum safety is obtained for the output
stage.
To protect the horizontal output transistor the horizontal
drive is immediately switched off when a power-on-reset is
detected. The drive signal is switched-on again when the
normal switch-on procedure is followed, i.e. all
sub-address bytes must be sent and after calibration the
horizontal drive signal will be released again via the slow
start procedure. When the coincidence detector indicates
an out-of-lock situation the calibration procedure is
repeated. The circuit has a second control loop to generate
the drive pulses for the horizontal driver stage. The
horizontal output is gated with the flyback pulse so that the
horizontal output transistor cannot be switched-on during
the flyback time.
Via the I2C-bus adjustments can be made of the horizontal
and vertical geometry. The vertical sawtooth generator
drives the vertical output drive circuit which has a
differential output current. For the E-W drive a single
ended current output is available. A special feature is the
zoom function for both the horizontal and vertical
deflection and the vertical scroll function which are
available in some versions. When the horizontal scan is
reduced to display 4:3 pictures on a 16:9 picture tube an
accurate video blanking can be switched on to obtain well
defined edges on the screen.

Overvoltage conditions (X-ray protection) can be detected
via the EHT tracking pin. When an overvoltage condition is
detected the horizontal output drive signal will be
switched-off via the slow stop procedure but it is also
possible that the drive is not switched-off and that just a
protection indication is given in the I2C-bus output byte.
The choice is made via the input bit PRD. The IC’s have a
second protection input on the j2 filter capacitor pin. When
this input is activated the drive signal is switched-off
immediately and switched-on again via the slow start
procedure. For this reason this protection input can be

used as “flash protection”.
The drive pulses for the vertical sawtooth generator are
obtained from a vertical countdown circuit. This countdown
circuit has various windows depending on the incoming
signal (50 Hz or 60 Hz and standard or non standard). The
countdown circuit can be forced in various modes by
means of the I2C-bus. During the insertion of RGB signals
the maximum vertical frequency is increased to 72 Hz so
that the circuit can also synchronise on signals with a
higher vertical frequency like VGA. To obtain short
switching times of the countdown circuit during a channel
change the divider can be forced in the search window by
means of the NCIN bit. The vertical deflection can be set
in the de-interlace mode via the I2C bus.
To avoid damage of the picture tube when the vertical
deflection fails the guard output current of the TDA
8350/51 can be supplied to the beam current limiting input.
When a failure is detected the RGB-outputs are blanked
and a bit is set (NDF) in the status byte of the I2C-bus.
When no vertical deflection output stage is connected this
guard circuit will also blank the output signals. This can be
overruled by means of the EVG bit.
Chroma and luminance processing
The circuits contain a chroma bandpass and trap circuit.
The filters are realised by means of gyrator circuits and
they are automatically calibrated by comparing the tuning
frequency with the X-tal frequency of the decoder. The
luminance delay line and the delay for the peaking circuit
are also realised by means of gyrator circuits. The centre
frequency of the chroma bandpass filter is switchable via
the I2C-bus so that the performance can be optimised for
“front-end” signals and external CVBS signals. During
SECAM reception the centre frequency of the chroma trap
is reduced to get a better suppression of the SECAM
carrier frequencies. All IC’s have a black stretcher circuit
which corrects the black level for incoming video signals
which have a deviation between the black level and the
blanking level (back porch). The timeconstant for the black
stretcher is realised internally.
The resolution of the peaking control DAC has been
increased to 6 bits. All IC’s have a defeatable coring
function in the peaking circuit. Some of these IC’s have a
YUV interface (see table on page 2) so that picture
improvement IC’s like the TDA 9170 (Contrast
improvement), TDA 9177 (Sharpness improvement) and
TDA 4556/66 (CTI) can be applied. When the CTI IC’s are
applied it is possible to increase the gain of the luminance
channel by means of the GAI bit in subaddress 03 so that
the resulting RGB output signals are not affected.
Colour decoder
Depending on the IC type the colour decoder can decode
PAL, PAL/NTSC or PAL/NTSC/SECAM signals. The
PAL/NTSC decoder contains an alignment-free X-tal
oscillator, a killer circuit and two colour difference
demodulators. The 90° phase shift for the reference signal
is made internally.
The IC’s contain an Automatic Colour Limiting (ACL)
circuit which is switchable via the I2C-bus and which
prevents that oversaturation occurs when signals with a
high chroma-to-burst ratio are received. The ACL circuit is
designed such that it only reduces the chroma signal and
not the burst signal. This has the advantage that the colour
sensitivity is not affected by this function.
The SECAM decoder contains an auto-calibrating PLL
demodulator which has two references, viz: the 4.4 MHz
sub-carrier frequency which is obtained from the X-tal
oscillator which is used to tune the PLL to the desired
free-running frequency and the bandgap reference to
obtain the correct absolute value of the output signal. The
VCO of the PLL is calibrated during each vertical blanking
period, when the IC is in search or SECAM mode.
The frequency of the active X-tal is fed to the Fsc output
(pin 33) and can be used to tune an external comb filter
(e.g. the SAA 4961).
The base-band delay line (TDA 4665 function) is
integrated in the PAL/SECAM IC’s and in the NTSC IC
TDA 8846A. In the latter IC it improves the cross colour
performance (chroma comb filter). The demodulated
colour difference signals are internally supplied to the
delay line. The colour difference matrix switches
automatically between PAL/SECAM and NTSC, however,
it is also possible to fix the matrix in the PAL standard.
The “blue stretch” circuit is intended to shift colour near
“white” with sufficient contrast values towards more blue to
obtain a brighter impression of the picture.

Which colour standard the IC’s can decode depends on
the external X-tals. The X-tal to be connected to pin 34
must have a frequency of 3.5 MHz (NTSC-M, PAL-M or
PAL-N) and pin 35 can handle X-tals with a frequency of
4.4 and 3.5 MHz. Because the X-tal frequency is used to
tune the line oscillator the value of the X-tal frequency
must be given to the IC via the I2C-bus. It is also possible
to use the IC in the so called “Tri-norma” mode for South
America. In that case one X-tal must be connected to pin
34 and the other 2 to pin 35. The switching between the 2
latter X-tals must be done externally. This has the
consequence that the search loop of the decoder must be
controlled by the m-computer. To prevent calibration
problems of the horizontal oscillator the external switching
between the 2 X-tals should be carried out when the
oscillator is forced to pin 34. For a reliable calibration of the
horizontal oscillator it is very important that the X-tal
indication bits (XA and XB) are not corrupted. For this
reason the X-tal bits can be read in the output bytes so that
the software can check the I2C-bus transmission.

RGB output circuit and black-current stabilisation
The colour-difference signals are matrixed with the
luminance signal to obtain the RGB-signals. The TDA
884X devices have one (linear) RGB input. This RGB
signal can be controlled on contrast and brightness (like
TDA 8374/75). By means of the IE1 bit the insertion
blanking can be switched on or off. Via the IN1 bit it can be
read whether the insertion pin has a high level or not.
The TDA 885X IC’s have an additional RGB input. This
RGB signal can be controlled on contrast, saturation and
brightness. The insertion blanking of this input can be
switched-off by means of the IE2 bit. Via the IN2 bit it can
be read whether the insertion pin has a high level or not.
The output signal has an amplitude of about 2 volts
black-to-white at nominal input signals and nominal
settings of the controls. To increase the flexibility of the IC
it is possible to insert OSD and/or teletext signals directly
at the RGB outputs. This insertion mode is controlled via
the insertion input (pin 26 in the S-DIP 56- and pin 38 in the
QFP-64 envelope). This blanking action at the RGB
outputs has some delay which must be compensated
externally.
To obtain an accurate biasing of the picture tube a
“Continuous Cathode Calibration” circuit has been
developed. This function is realised by means of a 2-point
black level stabilisation circuit. By inserting 2 test levels for
each gun and comparing the resulting cathode currents
with 2 different reference currents the influence of the
picture tube parameters like the spread in cut-off voltage
can be eliminated. This 2-point stabilisation is based on
the principle that the ratio between the cathode currents is
coupled to the ratio between the drive voltages according
to:
The feedback loop makes the ratio between the cathode
currents Ik1 and Ik2 equal to the ratio between the
reference currents (which are internally fixed) by changing
the (black) level and the amplitude of the RGB output
signals via 2 converging loops. The system operates in
such a way that the black level of the drive signal is
controlled to the cut-off point of the gun so that a very good
grey scale tracking is obtained. The accuracy of the
adjustment of the black level is just dependent on the ratio
of internal currents and these can be made very accurately
in integrated circuits. An additional advantage of the
2-point measurement is that the control system makes the
absolute value of Ik1 and Ik2 identical to the internal
reference currents. Because this adjustment is obtained
by means of an adaption of the gain of the RGB control
stage this control stabilises the gain of the complete
channel (RGB output stage and cathode characteristic).
As a result variations in the gain figures during life will be
compensated by this 2-point loop.

An important property of the 2-point stabilisation is that the
off-set as well as the gain of the RGB path is adjusted by
the feedback loop. Hence the maximum drive voltage for
the cathode is fixed by the relation between the test
pulses, the reference current and the relative gain setting
of the 3 channels. This has the consequence that the drive
level of the CRT cannot be adjusted by adapting the gain
of the RGB output stage. Because different picture tubes
may require different drive levels the typical “cathode drive
level” amplitude can be adjusted by means of an I2C-bus
setting. Dependent on the chosen cathode drive level the
typical gain of the RGB output stages can be fixed taking

into account the drive capability of the RGB outputs (pins
19 to 21). More details about the design will be given in the
application report.
The measurement of the “high” and the “low” current of the
2- point stabilisation circuit is carried out in 2 consecutive
fields. The leakage current is measured in each field. The
maximum allowable leakage current is 100 mA
When the TV receiver is switched-on the RGB output
signals are blanked and the black current loop will try to set
the right picture tube bias levels. Via the AST bit a choice
can be made between automatic start-up or a start-up via
the m-processor. In the automatic mode the RGB drive
signals are switched-on as soon as the black current loop
has been stabilised. In the other mode the BCF bit is set to
0 when the loop is stabilised. The RGB drive can than be
switched-on by setting the AST bit to 0. In the latter mode
some delay can be introduced between the setting of the
BCF bit and the switching of the AST bit so that switch-on
effects can be suppressed.
It is also possible to start-up the devices with a fixed
internal delay (as with the TDA 837X and the TDA884X/5X
N1). This mode is activated with the BCO bit.
The vertical blanking is adapted to the incoming CVBS
signal (50 Hz or 60 Hz). When the flyback time of the
vertical output stage is longer than the 60 Hz blanking time
the blanking can be increased to the same value as that of
the 50 Hz blanking. This can be set by means of the LBM
bit.
For an easy (manual) adjustment of the Vg2 control voltage
the VSD bit is available. When this bit is activated the black
current loop is switched-off, a fixed black level is inserted
at the RGB outputs and the vertical scan is switched-off so
that a horizontal line is displayed on the screen. This line
can be used as indicator for the Vg2 adjustment. Because
of the different requirements for the optimum cut-off
voltage of the picture tube the RGB output level is
adjustable when the VSD bit is activated. The control
range is 2.5 ± 0.7 V and can be controlled via the
brightness control DAC.
It is possible to insert a so called “blue back” back-ground
level when no video is available. This feature can be
activated via the BB bit in the control2 subaddress.

GRUNDIG ST70-900 DOLBY ELEGANCE 70  CHASSIS  CUC2032 TDA8350 DC-coupled vertical deflection and East-West output circuit:


GENERAL DESCRIPTION
The TDA8350Q is a power circuit for use in 90° and 110°
colour deflection systems for field frequencies of 50
to 120 Hz. The circuit provides a DC driven vertical
deflection output circuit, operating as a highly efficient
class G system and an East-West driver for sinking the
diode modulator current.

FEATURES
• Few external components
• Highly efficient fully DC-coupled vertical output bridge
circuit
• Vertical flyback switch
• Guard circuit
• Protection against:
– short-circuit of the output pins
– short-circuit of the output pins to VP
• High EMC immunity due to common mode inputs
• Temperature (thermal) protection
• East-West output stage with one single conversion
resistor.

PHILIPS TDA8350, FUNCTIONAL DESCRIPTION
The vertical driver circuit is a bridge configuration. The
deflection coil is connected between the output amplifiers,
which are driven in phase opposition. An external resistor
(RM) connected in series with the deflection coil provides
internal feed back information. The differential input circuit
is voltage driven. The input circuit has been adapted to
enable it to be used with the TDA9150, TDA9151B,
TDA9160A, TDA9162, TDA8366 and TDA8367 which
deliver symmetrical current signals. An external resistor
(RCON) connected between the differential input
determines the output current through the deflection coil.
The relationship between the differential input current and
the output current is defined by: Idiff× RCON= I(coil)× RM.
The output current is adjustable from 0.5 A (p-p) to 3 A
(p-p) by varying RM. The maximum input differential
voltage is 1.8 V. In the application it is recommended that
Vdiff= 1.5 V (typ). This is recommended because of the
spread of input current and the spread in the value of
RCON.
The flyback voltage is determined by an additional supply
voltage VFB. The principle of operating with two supply
voltages (class G) makes it possible to fix the supply
voltage VP optimum for the scan voltage and the second
supply voltage VFB optimum for the flyback voltage. Using
this method, very high efficiency is achieved.
The supply voltage VFB is almost totally available as
flyback voltage across the coil, this being possible due to
the absence of a decoupling capacitor (not necessary, due
to the bridge configuration). The output circuit is fully
protected against the following:
• thermal protection
• short-circuit protection of the output pins (pins 5 and 9)
• short-circuit of the output pins to VP.
A guard circuit VO(guard) is provided. The guard circuit is
activated at the following conditions:
• during flyback
• during various short-circuit possibilities at the output
pins
• during open loop
• when the thermal protection is activated.
This signal can be used for blanking the picture tube
screen.
An East-West amplifier is also provided. This amplifier is
an inverting amplifier which is current driven with sink
current only capabilities.

A flyback supply voltage of>50 V up to 60 V is allowed in application. A 220 nF capacitor in series with a 22 Ω resistor
(dependent on IO and the inductance of the coil) has to be connected between pin 7 and ground. The decoupling
capacitor of VFB has to be connected between pin 8 and pin 4. This supply voltage line must have a resistance of
33 Ω
PINNING

Idrive(pos)
1
input power-stage (positive);
includes II(sb) signal bias
Idrive(neg)
2
input power-stage (negative);
includes II(sb) signal bias
VI(fb)
3
feedback voltage input
VP
4
supply voltage
VO(B)
5
output voltage B
n.c.
6
not connected
GND
7
ground
VFB
8
flyback supply voltage
VO(A)
9
output voltage A
VO(guard)
10
guard output voltage
VO(sink)
11
East-West amplifier driver (sink)
output voltage
II(corr)
12
East-West amplifier input
correction current (negative)
II(set)
13
East-West amplifier set input
current (positive)

GRUNDIG ST70-900 DOLBY ELEGANCE 70  CHASSIS  CUC2032 PHILIPS TDA6106Q Video output amplifier:

GENERAL DESCRIPTION
The TDA6106Q is a monolithic video output amplifier with
a 6 MHz bandwidth and is contained in a 9-lead plastic
DIL-bent-SIL medium power package. The device uses
high-voltage DMOS technology and is intended to drive
the cathode of a CRT. To obtain maximum performance,
the amplifier should be used with black current control.

FEATURES
• No external heatsink required
• Black current measurement output for Automatic Black
current Stabilization (ABS)
• Internal 2.5 V reference circuit
• Internal protection against positive appearing CRT
flashover discharges
• Single supply voltage of 200 V
• Simple application with a variety of colour decoders
• Controlled switch-off behaviour.

Notes
1.
The cathode output is protected against peak currents (caused by positive voltage peaks during high-resistance
flash) of 5 A maximum with a charge content of 100 µC.
2.
The cathode output is also protected against peak currents (caused by positive voltage peaks during low-resistance
flash) of 10 A maximum with a charge content of 100 nC.
3.
Human body model: equivalent to discharging a 100 pF capacitor through a 1.5 kΩ resistor.
4.
Machine model: equivalent to discharging a 200 pF capacitor through a 0 Ω resistor.
Flashover protection
The TDA6106Q incorporates a protection diode against
CRT flashover discharges that clamp the cathode output
voltage to a maximum of VDD+ Vdiode. To limit the diode
current, an external 1.5 kΩ carbon high-voltage resistor in
series with the cathode output and a 2 kV spark gap are
needed (for this resistor-value, the CRT has to be
connected to the main PCB). This addition produces an
increase in the rise and fall times of approximately 7.5 ns
and a decrease in the overshoot of approximately 1.3%.
VDD to GND must be decoupled:
1.
With a capacitor larger than 20 nF with good HF
behaviour (e.g. foil). This capacitor must be placed as
close as possible to pins 6 and 4, but definitely within
5 mm.
2.
With a capacitor larger than10 µF on the picture tube
base print (shared by three output stages).
Switch-off behaviour
The output pins of the TDA6106Q are still under the control
of the input pin for a supply voltage down to approximately
30 V

GRUNDIG ST70-900 DOLBY ELEGANCE 70  CHASSIS  CUC2032 SIEMENS SDA5257 

1
General Description
The SDA 525x contains a slicer for TTX, VPS and WSS, an accelerating acquisition
hardware modul, a display generator for “Level 1” TTX data and an 8 bit microcontroller
running at 333 ns cycle time. The controller with dedicated hardware guarantees
flexibility, does most of the internal processing of TTX acquisition, transfers data to/from
the external memory interface and receives/transmits data via
I
2
C and UART user
interfaces. The block diagram shows the internal organization of the SDA 525x. The
Slicer combined with dedicated hardware stores TTX data in a VBI buffer of 1 Kbyte. The
microcontroller firmware does the total acquisition task (hamming- and parity-checks,
page search and evaluation of header control bits) once per field.
2
Features
Acquisition
• Feature selection via special function register
• Simultaneous reception of TTX, VPS and WSS
• Fixed framing code for VPS and TTX
• Acquisition during VBI
• Direct access to VBI RAM buffer
• Acquisition of packets X/26, X/27, 8/30 (firmware)
• Assistance of all relevant checks (firmware)
• 1-bit framing code error tolerance (switchable)
Display
• Features selectable via special function register
• 50/60 Hz display
• Level 1 serial attribute display pages
• Blanking and contrast reduction output
• 8 direct addressable display pages for SDA 5250, SDA 5254 and SDA 5255
• 1 direct addressable display page for SDA 5251 and SDA 5252
• 12
×
10 character matrix
• 96 character ROM (standard G0 character set)
• 143 national option characters for 11 languages
• 288 characters for X/26 display
• 64 block mosaic graphic characters
• 32 characters for OSD in expanded character ROM + 32 characters inside OSD box
• Conceal/reveal
• Transparent foreground/background - inside/outside of a box
• Contrast reduction inside/outside of a box
• Cursor (colour changes from foreground to background colour)
• Flash (flash rate 1s).
• Programmable horizontal and vertical sync delay
• Full screen background colour in outer screen
• Double size / double width / double height characters
Synchronization
• Display synchronization to sandcastle or Horizontal Sync (HS) and Vertical Sync (VS)
with start-stop-oscillator
• Independent clock systems for acquisition, display and controller
Microcontroller
• 8 bit C500-CPU (8051 compatible)
• 18 MHz internal clock
• 0.33
µ
s instruction cycle
• Parallel 8-bit data and 16...19 - bit address bus (ROMless-Version)
• Eight 16-bit data pointer registers (DPTR)
• Two 16-bit timers
• Watchdog timer
• Capture compare timer for infrared remote control decoding
• Serial interface (UART)
• 256 bytes on-chip RAM
• 8 Kbyte on-chip display-RAM (access via MOVX) for SDA 5250, SDA 5254 and
SDA 5255
• 1 Kbyte on-chip display-RAM (access via MOVX) for SDA 5251 and SDA 5252
• 1 Kbyte on-chip TVT/VPS-Acquisition-buffer-RAM (access via MOVX)
• 1 Kbyte on-chip extended-RAM (access via MOVX) for SDA 5250, SDA 5254 and
SDA 5255
• 6 channel 8-bit pulse width modulation unit
• 2 channel 14-bit pulse width modulation unit
• 4 multiplexed ADC inputs with 8-bit resolution
• One 8-bit I/O port with open drain output and optional
I
2
C-Bus emulation (PORT 0)
• Two 8-bit multifunctional I/O ports (PORT 1, PORT 3)
• One 4-bit port working as digital or analog inputs (PORT 2)
• One 2-bit I/O port with optional functions
• One 3-bit I/O port with optional RAM/ROM address expansion up to 512 Kbyte
(ROMless-Version)
– P-SDIP-52-1 Package or P-MQFP-64-1 for ROM-Versions (SDA 5251, SDA 5252,
SDA 5254, SDA 5255)
– P-MQFP-80-1 Package for ROMless-Version (SDA 5250 M)
– P-LCC-84-2 Package for Emulator-Version (SDA 5250)
– 5 V Supply Voltage.
6
Functional Description
6.1
Acquisition
6.1.1
TTX/VPS Slicer
The slicer extracts horizontal and vertical sync information and TTX data from the CVBS
signal. The slicer includes an analog circuit for sync filtering and data slicing. Further
there are two analog PLLs for system clock generation for both TTX and VPS. Therefore
the slicer is able to receive both TTX and VPS in succeeding lines of a vertical blanking
interval. A third data-PLL shifts the phase of the system clock for data sampling. The
internal slicer timing signals are generated from the VPS-PLL.
6.1.2
Acquisition Hardware
The acquisition hardware transforms the sliced bit stream into a byte stream. A framing
code check follows to identify a TTX or VPS line. If the framing code error tolerance is
enabled then one-bit errors will be allowed.
For each line in the VBI in which a framingcode is detected, a maximum of 42 bytes
(VPS: 26 bytes) plus a status word are stored in the VBI-buffer. After framing code
detection a status word is generated which informs about the type of data received (TTX
or VPS) and the signal quality of the TV channel.
Chapter “Acquisition Status Word”
on page 17
shows the format of this status word. The horizontal and vertical windows in
which TTX or VPS data are accepted and checked for framing code errors are generated
automatically. The VBI buffer data will be analyzed (Hamming, parity and acquisition) by
the microcontroller and stored in the dual port display RAM or the external RAM, if
selected. This analysis is repeated for every field.
6.2
Display Generator
The display features of SDA525x are similar to the Siemens SDA5248 TTX controller.
The display generator reads character addresses and control characters from the
display memory, selects the pixel information from the character ROM and translates it
into RGB values corresponding to the World Standard Teletext Norm. The national
option character bits for 11 languages inclusive X/26 characters are also supported.
6.2.1
Display Format and Timing
A page consists of 25 rows of 40 characters each. One character covers a matrix of
12 horizontal and 10 vertical pixels. The pixel frequency should be 12 MHz
corresponding to 1 µs for one character and 40 µs for one row. A total of 250 TV lines
are used for TTX display. The display can be shifted horizontally from 0 µs to 21.33 µs
with respect to HS and vertically from line 1 (314) to line 64 (377) with respect to VS. The
display position is determined by the registers DHD and DVD.
Note: To avoid interferences between the subharmonics of the 18 MHz controller clock
and the 12 MHz pixel clock, a pixel clock of about 11,5 MHz is recommended.
6.2.2
Display Cursor
A cursor is available which changes foreground to background colour for one character.
Cursor flash can be realized via software enabling/disabling the cursor. The cursor
position is defined by cursor position registers DCRP and DCCP.
6.2.3
Flash
A character background flash (character is changed to background colour) is realized by
hardware. The flash frequency is 1 Hz with a duty cycle of 32:18.
6.2.4
Full Screen Background Colour
The SDA 525x delivers the new full screen background colour feature. Special function
register SFR DTIM(7-5) includes three bits which define the default background colour
for the inner and outer screen area.
6.2.5
Clear Page Logic
The clear page logic generates a signal which is interpreted by the character generator
to identify non displayable rows. In row 25 specific information is stored by the
microcontroller indicating which of the rows 0 - 24 should be interpreted as erased during
character generation. At the beginning of each row the special control characters are
read from the display memory.

6.2.7
Character Generator
The character generator includes the character and control code decoder, the RAM
interface and the RGB-, BLAN- and COR-signal generator. The display generator reads
data from the display RAM and calculates appropriate data which drives the RGB output
pins. The pixel clock is generated by a start-stop-oscillator. The synchronization of
display and pixel clock is done via external sandcastle or HS and VS signals. For 60 Hz
display the number of lines per character can be reduced to 9 or 8. In this case pixel
information of line 10 or 9 plus 10 are rejected. With this mode combined with the
variable vertical offset it is possible to generate NTSC displays with 25 rows.
Characters with a binary value < 32 are interpreted as control characters. For binary
values ≥ 32 a ROM character is selected through the addition of the character address,
the language setting in SFR, the europe designation and the graphics control bits
delivered from the control bit decoder.
A total of 64 OSD characters and 64 mosaic graphics characters are available. OSD
characters with addresses 80...SFH can be displayed together with 60 lower case
characters because there is no memory overlapping with any other characters. OSD
characters with addresses 60...7FH can only be displayed if bit OSD in SFR LANGC is
set (see diagrams: Physical Address Space and Vertical Address Space).
Figures 6 - 13 shows the character ROM contents.
The control byte decoder analyses the serial attributes from the display memory and
generates control clocks for the RGB logic and the character address decoder. The
interpretation of control characters is corresponding to World Standard Teletext norm.
Table 5 shows the characters and the appearance on the screen.
The RGB logic combines data from the character address decoder, control byte decoder
and settings from the SFR registers and generates signal R, G, B, BLAN and COR.
6.2.8
On Screen Display (OSD)
A display page in the display memory can also be used for on screen displays. It should
be recognized that all serial attributes of a normal text page are also valid for an OSD
display. Therefore if double height is selected anywhere in a normal text page, row n and
row n-1 (upper row) should be saved and overwritten by OSD data in order to generate
a correct display. Switching back to text display is accomplished by rewriting the text
data to the page. The same procedure is needed for the “erase row bits” in row 25. By
means of enable box bits, transparent control bits and the serial attribute “OSD”, the
OSD screen can be controlled fully independent of the normal text page. The serial
OSD-bit toggles the screen between normal display and OSD.

6.3
Microcontroller
6.3.1
Architecture
The SIEMENS SDA5257 CPU manipulates operands in two memory spaces: the program memory space,
and the data memory space. The program memory address space is provided to
accommodate relocatable code.
The data memory address space is divided into the 256-byte internal data RAM, XRAM
(extended data memory, accessible with MOVX-instructions) and the 128-byte Special
Function Register (SFR) address spaces. Four register banks (each bank has eight
registers), 128 addressable bits, and the stack reside in the internal data RAM. The stack
depth is limited only by the available internal data RAM. It’s location is determined by the
8-bit stack pointer. All registers except the program counter and the four 8-register banks
reside in the special function register address space. These memory mapped registers
include arithmetic registers, pointers, I/O-ports, registers for the interrupt system, timers,
pulse width modulator and serial channel. Many locations in the SFR-address space are
addressable as bits.
Note that reading from unused locations within data memory will yield undefined data.
Conditional branches are performed relative to the 16 bit program counter. The register-
indirect jump permits branching relative to a 16-bit base register with an offset provided
by an 8-bit index register. Sixteen-bit jumps and calls permit branching to any location in
the memory address space.
The processor as five methods for addressing source operands: register, direct, register-
indirect, immediate, and base-register plus index-register indirect addressing.
The first three methods can be used for addressing destination operands. Most
instructions have a “destination, source” field that specifies the data type, addressing
methods and operands involved. For operations other than moves, the destination
operand is also a source operand.
Registers in the four 8-register banks can be accessed through register, direct, or
register-indirect addressing; the lower 128 bytes of internal data RAM through direct or
register-indirect addressing, the upper 128 bytes of internal data RAM through register-
indirect addressing; and the special function registers through direct addressing. Look-
up tables resident in program memory can be accessed through base-register plus
index-register indirect addressing.

6.3.1.1
CPU-Hardware
Instruction Decoder
Each program instruction is decoded by the instruction decoder. This unit generates the
internal signals that control the functions of each unit within the CPU-section. These
signals control the sources and destination of data, as well as the function of the
Arithmetic/Logic Unit (ALU).
Program Control Section
The program control section controls the sequence in which the instructions stored in
program memory are executed. The conditional branch logic enables conditions internal
and external to the processor to cause a change in the sequence of program execution.
The 16-bit program counter holds the address of the instruction to be executed. It is
manipulated with the control transfer instructions listed in Chapter “Instruction Set” on
page 116.
Internal Data RAM
The internal data RAM provides a 256-byte scratch pad memory, which includes four
register banks and 128 direct addressable software flags. Each register bank contains
registers R0 – R7. The addressable flags are located in the 16-byte locations starting at
byte address 32 and ending with byte location 47 of the RAM-address space.
In addition to this standard internal data RAM the processor contains an extended
internal RAM. It can be considered as a part of an external data memory. It is referenced
by MOVX-instructions (MOVX A, @DPTR), the memory map is shown in Figure 21.
Arithmetic/Logic Unit (ALU)
The arithmetic section of the processor performs many data manipulation functions and
includes the Arithmetic/Logic Unit (ALU) and the A, B and PSW-registers. The ALU
accepts 8-bit data words from one or two sources and generates an 8-bit result under
the control of the instruction decoder. The ALU performs the arithmetic operations of
add, subtract, multiply, divide, increment, decrement, BCD-decimal-add-adjust and
compare, and the logic operations of and, or, exclusive-or, complement and rotate (right,
left, or nibble swap).
The A-register is the accumulator, the B-register is dedicated during multiply and divide
and serves as both a source and a destination. During all other operations the B-register
is simply another location of the special function register space and may be used for any
purpose.

Boolean Processor
The Boolean processor is an integral part of the processor architecture. It is an
independent bit processor with its own instruction set, its own accumulator (the carry
flag) and its own bit- addressable RAM and I/O. The bit manipulation instructions allow
the direct addressing of 128 bits within the internal data RAM and several bits within the
special function registers. The special function registers which have addresses exactly
divisible by eight contain directly addressable bits.
The Boolean processor can perform, on any addressable bit, the bit operations of set,
clear, complement, jump-if-set, jump-if-not-set, jump-if-set then-clear and move to/from
carry. Between any addressable bit (or its complement) and the carry flag it can perform
the bit operation of logical AND or logical OR with the result returned to the carry flag.
Program Status Word Register (PSW)
The PSW-flags record processor status information and control the operation of the
processor. The carry (CY), auxiliary carry (AC), two user flags (F0 and F1), register bank
select (RS0 and RS1), overflow (OV) and parity (P) flags reside in the program status
word register. These flags are bit-memory-mapped within the byte-memory-mapped
PSW. The CY, AC, and OV flags generally reflect the status of the latest arithmetic
operations. The CY-flag is also the Boolean accumulator for bit operations. The P-flag
always reflects the parity of the A-register. F0 and F1 are general purpose flags which
are pushed onto the stack as part of a PSW-save.
Stack Pointer (SP)
The 8-bit stack pointer contains the address at which the last byte was pushed onto the
stack. This is also the address of the next byte that will be popped. The SP is
incremented during a push. SP can be read or written to under software control. The
stack may be located anywhere within the internal data RAM address space and may be
as large as 256 bytes.
Data Pointer Register (DPTR)
The 16-bit Data Pointer Register DPTR is the concatenation of registers DPH (high-
order byte) and DPL (low-order byte). The DPTR is used in register-indirect addressing
to move program memory constants and to access the extended data memory. DPTR
may be manipulated as one 16-bit register or as two independent 8-bit registers DPL and
DPH.
Eight data pointer registers are available, the active one is selected by a special function
register (DPSEL).
Port 0, Port 1, Port 2, Port 3, Port 4
The five ports provide 26 I/O-lines and 5 input-lines to interface to the external world. All
five ports are both byte and bit addressable. Port 0 is used for binary l/O and as clock
and data line of a software driven I2C bus. Port 1 provides eight PWM- output channels
as alternate functions while port 2.0 - 2.3 are digital or analog inputs. Port 3 contains
special control signals. Port 4 will usually be selected as memory extension interface
(ROM-less version only).
Interrupt Logic
Controlled by three special function registers (IE, IP0 and IP1) the interrupt logic
provides several interrupt vectors. Each of them may be assigned to high or low priority
(see Chapter “Interrupt System” on page 62).
Timer/Counter 0/1
Two general purpose 16-bit timers/counters are controlled by the special function
registers TMOD and TCON (see Chapter “General Purpose Timers/Counters” on
page 80).
Serial Interface
A full duplex serial interface is provided where one of three operation modes may be
selected. The serial interface is controlled by two special function registers (SCON,
SBUF)

Watchdog Timer
For software- and hardware security, a watchdog timer is supplied, which resets the
processor, if not cleared by software within a maximum time period.
Pulse Width Modulation Unit
Up to six lines of port 1 may be used as 8-bit PWM-outputs and two lines of port 1 may
be used as 14-bit PWM-output. The PWM-logic is controlled by registers
PWCOMP0 … 7, PWCL, PWCH, PWME, PWEXT6, PWEXT7 (see Chapter “Pulse
Width Modulation Unit (PWM)” on page 106).
Capture Compare Timer
For easy decoding of infrared remote control signals, a dedicated timer is available (see
Chapter “Capture Compare Timer” on page 90).
6.3.1.2
CPU-Timing
Timing generation is completely self-contained, except for the frequency reference
which can be a crystal or external clock source. The on-board oscillator is a parallel anti-
resonant circuit. There is a divide-by-6 internal timing which leads to a minimum
instruction cycle of 0.33 µs with an 18-MHz crystal. The XTAL2-pin is the output of a
high-gain amplifier, while XTAL1 is its input. A crystal connected between XTAL1 and
XTAL2 provides the feedback and phase shift required for oscillation.
A machine cycle consists of 6 oscillator periods (software selectable). Most instructions
execute in one cycle. MUL (multiply) and DIV (divide) are the only instructions that take
more than two cycles to complete. They take four cycles.
To reduce the power consumption, the internal clock frequency can be divided by two,
which slows down the processor operations.
This slow down mode is entered by setting SFR-Bit CDC in register AFR.
Note: All timing values and diagrams in this specification refer to an inactivated clock
divider (CDC = 0).
Note: Slow down mode should only be used if teletext reception and the display are
disabled. Otherwise processing of the incoming text data might be incomplete and
the display structure will be corrupted.