SELECO S14E222 CHASSIS PC010 INTERNAL VIEW.

  

 

 

 

 

 

 

 

 

 TDA8349A Multistandard IF amplifier and demodulator:

 GENERAL DESCRIPTION
The TDA8349A is a multistandard IF amplifier and demodulator with AGC and AFC functions for television receivers.
The device has a video recognition circuit and a video switch for internal or external video for full SCART applications.

FEATURES
• Full-range gain-controlled wideband IF amplifier up to 60 MHz
• Wide-band video amplifier with good linearity and a class AB output stage to ensure a very low output impedance
• Supply independent video output level
• Small second harmonic IF output
• AGC circuit which operates on top sync level (negative modulation) or on white level (positive modulation) or on top
level (MAC) with reduced sensitivity for high sound carriers
• AFC circuit with an internal 90° phase shift circuit, a sample-and-hold circuit for negatively modulated signals to reduce
video dependent AFC information and an analog or digital output
• Video recognition possibility based on horizontal pulse duty cycles
• Video switch for selection of internal or external video signals
• Wide supply voltage range and ripple rejection
• Requires few external components
• Tuner AGC output for npn and pnp tuners

FUNCTIONAL DESCRIPTION
General
The IC consists of the following parts as illustrated in Fig.1:
• Gain controlled video IF amplifier
• Quasi-synchronous demodulator
• Video amplifier/buffer with white spot clamp/inverter and
noise clamp
• AGC circuit which operates either on top sync level
(negative modulation) or on white level (positive
modulation) or on top level (MAC)
• AFC circuit with sample-and-hold circuit for negatively
modulated signals, on/off switch and a digital or analog
output (switchable)
• Circuit for switching between positive and negative
modulation
• Video recognition circuit for sound muting and tuning
indication
• Video switch which facilitates selection between two
different video signals, with different gain settings
IF amplifier
The IF amplifier consists of three AC coupled differential gain stages with adjustable feedback in the emitter. The AC coupling allows simple biasing, cascades can be used and no DC feedback is required. This provides a control range above 70 dB with good linearity. The minimum input signal to obtain the nominal output amplitude is 50 μV RMS.

Demodulator
The demodulator is a quasi-synchronous circuit that employs passive carrier regeneration and a tuned circuit for selectivity. The regenerated carrier signal is limited by a clamping circuit before it is fed to the demodulator. Switching between positive and negative modulation is achieved by the system switch which provides currents to the demodulator in a positive or negative direction. Video amplifier The video amplifier based on the feedback principle improves the linearity of the video output buffer. It has an internal bandgap reference to ensure a stable video output at different supply voltages and temperatures. This
bandgap also reduces the supply ripple on the video output to values less than −30 dB. The video amplifier has a typical bandwidth of 10 MHz which allows application for all new video standards with bandwidths of up to 10 to 12 MHz. The video output signal has an amplitude of 2 V (p-p). White spot protection comprises a white spot clamp system combined with a delayed-action inverter which is also highly resistant to high sound carriers. A switchable DC shift for positively modulated IF signals ensures correct signal handling. This switching is obtained via pin 20, which is the same pin used for switching the demodulation polarity in the demodulator. The circuit also has a noise clamp which prevents the video output becoming less than ±400 mV below the top sync level at noise peaks. The output buffer of the video amplifier consists of a class A/B circuit which can handle large source as well as large sink currents. This makes the circuit more flexible in several applications with one or more ceramic filters connected to this output buffer.

AGC control circuit
This converts the AGC detector voltage (pin 5) into a current signal which controls the gain of the IF amplifier. It also provides a tuner AGC control output from pin 4, current limiting is incorporated to prevent internal damage. The AGC starting point is adjusted by a voltage between 3 and 5 V for pnp tuners and between 7 and 9 V for npn tuners via pin 3.

AGC circuit
A new AGC system has been designed for the AGC. It will be a top sync-detector for negatively modulated signals and a top white level AGC for positively modulated signals. For optimal flexibility reasons the load and unload currents of the AGC are chosen such that both, a relatively fast set, as well as a set with a low tilt are possible for positive (L) and negative (B/G) modulated signals. For this reason a tilt ratio between positive (L) and negative (B/G) of approximately 3:1 has been chosen. This means that in a fast set the choice of a typical tilt for negatively modulated signals of 2% will obtain a typical tilt for positively modulated signals (L) of 6%. For a digital set which requires a small tilt the choice of tilt can be a factor of 5 or 10 smaller by increasing the AGC capacitor.

Switching between the first three modes can be achieved by the system switch. This is a 3-level switch which when grounded selects B/G; open or 5 V selects L, and with pin 20 connected to VCC selects positively modulated MAC. The IC operates in a fourth mode if the identification capacitor at pin 19 is connected to VCC, it can be used for negatively modulated MAC. During channel switching a situation can occur that requires the AGC to increase the gain more than for example 50 dB. If this increase of gain has to be done for a positively modulated (L) signal, it will be achieved by the 500 nA load current and is therefore extremely slow. Because the identification information can be used to indicate that the signal is too small, in this event the identification circuit will mute, it is possible to increase the positive unload current to the same value as that used for negatively modulated signals. This switching is fully automatic and cannot be switched off.

AFC circuit
The AFC circuit consists of a demodulator stage which is fed with signals 90° out of phase. A very accurate internally realized 90° phase shift circuit makes it possible to use the demodulator IF regenerator tuned circuit for tuning the AFC circuit. To prevent video ripple on the AFC output voltage a sample-and-hold circuit is used for negatively modulated signals. The output signal of the demodulator is sampled during sync level of the video signal and will be stored with the aid of an external capacitor.

This sample-and-hold circuit is not used in the L mode, but it will function as a low-pass filter in this mode and therefore also reduces the video dependency of the AFC. A gain stage amplifies the voltage swing by 5 times. The output of the AFC circuit will be an inverse analog output on pin 8 when pin 9 is connected to a voltage above 8 V. If pin 9 is connected to a voltage above 10 V the output will be a normal analog output. Normally pins 8 and 9 together provide digital AFC information.

Video recognition circuit
For full scart functions it is necessary to implement a second mute function for non-video signals in the whole television concept. This is realized in this IF-IC. With an internal sync separator and an internal integrator it is possible to achieve a very sensitive identification circuit, which measures the mean frequency of the input signal. This is normally approximately 16 kHz. The integrator capacitor will be loaded during the whole line time and unloaded during the sync pulse. The maximum voltage at this internal capacitor is a value for the main frequency of the video signal. By changing the value of an external capacitor it is possible to influence the speed and sensitivity of the recognition circuit. It is possible to gain sensitivity performance at disturbed signals by increasing the value of the external capacitor, however this will reduce the speed of the identification circuit. Video switch circuit The video switch also provides application for full SCART functions. The circuit has two inputs, one output and a control pin. The switch selects either internal or external video signals. A × 2 gain stage for the external input provides an equal output level for internal or external video from the SCART. The crosstalk of the unwanted signal is better than −50 dB and the total signal handling meets all the requirements for SCART specifications.

TDA8191 TV SOUND CHANNEL:

 The TDA8191 is a monolithic integrated circuit thaincludes all the functions needed for a complete TV

sound channel.The TDA8191 is assembled in a 20
pin dual in line power package.

 . HIGH SENSITIVITY
. EXCELLENT AM REJECTION
. DC VOLUME CONTROL
. PERITELEVISION FACILITY
. 4W OUTPUT POWER
. LOW DISTORTION
. THERMAL PROTECTION
. TURN-ON AND TURN-OFF MUTING.




- VIDEO CHROMA PROCESSING WITH TDA3301 (MOTOROLA)

TDA3300 /  3301 TV COLOR PROCESSOR
TDA3300 3301 TV COLOR PROCESSOR
The Decoder IC The centre -piece of the decoder is the Motorola TDA3300B i.c. which carries out all the luminance and U V Inputs from PAL delay line 9V Frequency nlyv Z 2RV2 100k chroma signal processing required. Features of this 40 -pin chip include: (1) Automatic black -current control via feedback from the RGB output circuits. (2) Peak beam current limiting to prevent blooming on highlights - in addition to the normal beam current limit- ing action. (3) Separate R, G and B input pins for the injection of teletext/data signals (or on -screen display of the channel number with frequency synthesis tuning). These signals can be varied by means of the user brightness and con- trast controls. (4) Low dissipation - about 600mW. (5) By adding a small adaptor panel with a TDA3030A SECAM-to-PAL converter i.c. during production the receiver is given multistandard (PAL, SECAM and NTSC-4.43) capability.

A block diagram of the TDA3300B i.c. is shown in Fig. 3. As with the better known TDA3560 single -chip decoder, both the chroma and the burst pass through the chroma delay line. The U output from this enters the TDA3300B at pin 8, passing to the U detector and to the burst detector. The latter is part of a phase -locked loop, the detector's output being applied via an H/2 (half-line frequency) switch to the 4.43MHz voltage -controlled crystal oscillator. The 4.43MHz reference oscillator's output is applied for PAL switching, and to the U detector via a voltage -controlled 90° phase shifter. This shifter is under the control of the 90° detec- tor which compares its output with the oscillator's output coming via the PAL switch: when the phase shift is cor- rect, the output from the 90° phase detector is zero. The combined effect of the two H/2 switches in the reference oscillator control loop - the two shown on the right-hand side - cancels phase detector offsets. The outputs from the U and V detectors include burst "flag" pulses which are used for a.c.c., ident and colour -killing - there are two colour -killing actions. RGB Output Stages The RGB output stages are of the class AB type and incorporate extra circuitry for c.r.t. black -current sampl- ing and beam limiting. Fig. 4 shows the red output stage. Under most conditions transistor 2TR1 acts as a class A amplifier, driving the tube's cathode via 2D5 and 2TR7. A high -value collector load resistor (2R33) is used to reduce the dissipation in 2TR1. The stage gain is set by the ratio of 2R40 and 2R36 to 2R25 and 2RV3, the latter setting the drive level. For good transient response it's necessary for the tube/base capacitance to be rapidly charged/discharged in accordance with the signal swings. There is no problem when 2TR1 is being driven from off to on, since the capacitance is discharged rapidly via 2D5 and 2TR1. When 2TR1 is driven from on to off however 2D5 will become reverse biased. Under these conditions 2TR4 acts as an emitter -follower so that the capacitance charges rapidly. Black -level stability is critical for good results. As we've 2R46 5k6 2R51 120k 2TR7 BF493S 2C43l Sampling circuit L -J 1k5 Field blanking J Red cathode _Tube input T"and base 810capacitance nlrr Reference Line pedestal blanking Sample -and - hold amplifier-ws switched on rt- Video Urn seen, the TDA3300B chip incorporates circuitry for automatic black -current correction. Making use of this reduces service calls and ensures constant performance despite tube ageing or circuit misadjustment. Feedback is required, and this is provided by the sampling circuit shown in the box with the broken outline. Transistor 2TR7 acts as an emitter -follower between the video output stage and the c.r.t.'s cathode. It's a low leakage type, the components 2C40, 2D10 and 2C43 ensuring that the circuit has negligible effect on the video signal. Since the beam current flows via 2R51, a voltage proportional to the beam current is produced across this resistor. It's fed into the TDA3300B at pin 22. Black -current Control For automatic black -current control the important thing is the small beam current that flows when the tube is biased just above cut off. To enable this current to be sampled, the TDA3300B replaces the video signal with a fixed reference pedestal voltage for a couple of lines at the end of each field blanking period (this pedestal can be seen as a grey line at the top of the picture if the height control's setting is reduced). The sample voltage at pin 22 of the i.c. is fed to one input of a sample -and -hold amp- lifier which is switched on to sample the input for one line only of the reference pedestal period. 2C33 acts as the black -current control reservoir capacitor, holding the charge acquired during the sampling time for the whole field period. This charge is added to the video signal within the i.c., thus maintaining the correct red gun black current. It's interesting to notice that when a set is switched on from cold there's a momentary screen bright -up with flyback lines as the beam current begins to flow. This is because it takes several fields for 2C33 (and the corre- sponding capacitors in the green and blue channels) to charge fully. Since the voltage continuously available across 2R51 is proportional to beam current, it's used within the i.c. for peak beam current limiting during the active line periods. This is in addition to beam current limiting via the con- trast control - and a crowbar trip that operates should the beam current exceed 3mA.
This device will accept a PAL or NTSC composite video signal and output the
three color signals, needing only a simple driver amplifier to interface to the pic-
ture tube. The provision of high bandwidth on-screen display inputs makes it
suitable for text display, TV games, cameras, etc. The TDA3301 B has user con»
trol laws, and also a phase shift control which operates in PAL, as well as NTSC.
0 Automatic Black Level Setup
0 Beam Current Limiting
0 Uses Inexpensive 4.43 MHZ to 3.58 MHz Crystal
0 No Oscillator Adjustment Required
0 Three OSD Inputs Plus Fast Blanking Input
0 Four DC, High Impedance User Controls
0 lnterlaces with TDA33030B SECAM Adaptor
0 Single 12 V Supply
0 Low Dissipation, Typically 600 mW
The brilliance control operates by adding a pedestal to the output
signals. The amplitude of the pedestal is controlled by Pin 30.
During CRT beam current sampling a standard pedestal is
substituted, its value being equivalent tothe value given by V30 Nom
Brightness at black level with V30 Nom is given by the sum of three gun
currents at the sampling level, i.e. 3x20 |.1A with 100 k reference
resistors on Pins 16, 19, and 22.
During picture blanking the brilliance pedestal is zero; therefore, the
output voltage during blanking is always the minimum brilliance black
level (Note: Signal channels are also gain blanked).

Chrominance Decoder
The chrominance decoder section of the TDA3301 B
consists of the following blocks:
Phase-locked reference oscillator;
Phase-locked 90 degree servo loop;
U and V axis decoders
ACC detector and identification detector; .
Identification circuits and PAL bistable; .
Color difference filters and matrixes with fast blanking
Circuits.
The major design considerations apart from optimum
performance were:
o A minimum number of factory adjustments,
o A minimum number of external components,
0 Compatibility with SECAM adapter TDA3030B,
0 Low dissipation,
0 Use of a standard 4.433618 Mhz crystal rather
than a 2.0 fc crystal with a divider.

The crystal VCO is of the phase shift variety in which the
frequency is controlled by varying the phase of the feedback.
A great deal of care was taken to ensure that the oscillator loop
gain and the crystal loading impedance were held constant in
order to ensure that the circuit functions well with low grade
crystal (crystals having high magnitude spurious responses
can cause bad phase jitter). lt is also necessary to ensure that
the gain at third harmonic is low enough to ensure absence of
oscillation at this frequency.

It can be seen that the
necessary 1 45°C phase shift is obtained by variable addition
ol two currents I1 and I2 which are then fed into the load
resistance of the crystal tuned circuit R1. Feedback is taken
from the crystal load capacitance which gives a voltage of VF
lagging the crystal current by 90°.
The RC network in the T1 collector causes I1 to lag the
collector current of T1 by 45°.
For SECAM operation, the currents I1 and I2 are added
together in a fixed ratio giving a frequency close to nominal.
When decoding PAL there are two departures from normal
chroma reference regeneration practice:
a) The loop is locked to the burst entering from the PAL
delay line matrix U channel and hence there is no
alternating component. A small improvement in signal
noise ratio is gained but more important is that the loop
filter is not compromised by the 7.8 kHz component
normally required at this point for PAL identification
b) The H/2 switching of the oscillator phase is carried out
before the phase detector. This implies any error signal
from the phase detector is a signal at 7.8 kHz and not dc.
A commutator at the phase detector output also driven
from the PAL bistable coverts this ac signal to a dc prior
to the loop filter. The purpose ot this is that constant
offsets in the phase detector are converted by the
commutator to a signal at 7.8 kHz which is integrated to
zero and does not give a phase error.
When used for decoding NTSC the bistable is inhibited, and
slightly less accurate phasing is achieved; however, as a hue
control is used on NTSC this cannot be considered to be a
serious disadvantage.


90° Reference Generation
To generate the U axis reference a variable all-pass network
is utilized in a servo loop. The output of the all-pass netw

ork
is compared with the oscillator output with a phase detector of
which the output is filtered and corrects the operating point of
the variable all»pass network .
As with the reference loop the oscillator signal is taken after
the H/2 phase switch and a commutator inserted before the
filter so that constant phase detector errors are cancelled.
For SECAM operation the loop filter is grounded causing
near zero phase shift so that the two synchronous detectors
work in phase and not in quadralure.
The use of a 4.4 MHz oscillator and a servo loop to generate
the required 90° reference signal allows the use of a standard,
high volume, low cost crystal and gives an extremely accurate
90° which may be easily switched to 0° for decoding AM
SECAM generated by the TDA3030B adapter.

ACC and Identification Detectors
During burst gate time the output components of the U and
also the V demodulators are steered into PNP emitters. One
collector current of each PNP pair is mirrored and balanced
against its twin giving push-pull current sources for driving the
ACC and the identification filter capacitors.
The identification detector is given an internal offset by
making the NPN current mirror emitter resistors unequal. The
resistors are offset by 5% such that the identification detector
pulls up on its filter capacitor with zero signal.
Identification
See Figure 11 for definitions.
Monochrome I1 > I2
PAL ldent. OK I1 < lg
PAL ldent_ X l1 > I2
NTSC I3 > I2
Only for correctly identified PAL signal is the capacitor
voltage held low since I2 is then greater than I1.
For monochrome and incorrectly identified PAL signals l1>l2
hence voltage VC rises with each burst gate pulse.
When V,ef1 is exceeded by 0.7 V Latch 1 is made to conduct
which increases the rate of voltage rise on C. Maximum
current is limited by R1.
When Vref2 is exceeded by 0.7 V then Latch 2 is made to
conduct until C is completely discharged and the current drops
to a value insufficient to hold on Latch 2.
As Latch 2 turns on Latch 1 must turn off.
Latch 2 turning on gives extra trigger pulse to bistable to
correct identification.
The inhibit line on Latch 2 restricts its conduction to alternate
lines as controlled by the bistable. This function allows the
SECAM switching line to inhibit the bistable operation by firing
Latch 2 in the correct phase for SECAM. For NTSC, Latch 2
is fired by a current injected on Pin 6.
lf the voltage on C is greater than 1.4 V, then the saturation
is held down. Only for SECAM/NTSC with Latch 2 on, or
correctly identified PAL, can the saturation control be
anywhere but minimum.
NTSC Switch
NTSC operation is selected when current (I3) is injected into
Pin 6. On the TDA33O1 B this current must be derived
externally by connecting Pin 6 to +12 V via a 27 k resistor (as
on TDA33OOB). For normal PAL operation Pin 40 should be
connected to +12 V and Pin 6 to the filter capacitor.

4 Color Difference Matrixing, Color Killing,
and Chroma Blanking
During picture time the two demodulators feed simple RC
filters with emitter follower outputs. Color killing and blanking
is performed by lifting these outputs to a voltage above the
maximum value that the color difference signal could supply.
The color difference matrixing is performed by two
differential amplifiers, each with one side split to give the
correct values of the -(B-Y) and -(Ft-Y) signals. These are
added to give the (G-Y) signal.
The three color difference signals are then taken to the
virtual grounds of the video output stages together with
luminance signal.
Sandcastle Selection
The TDA3301B may be used with a two level sandcastle
and a separate frame pulse to Pin 28, or with only a three level
(super) sandcastle. In the latter case, a resistor of 1.0 MQ is
necessary from + 12 V to Pin 28 and a 70 pF capacitor from
Pin 28 to ground.

Timing Counter for Sample Control
In order to control beam current sampling at the beginning
of each frame scan, two edge triggered flip-flops are used.
The output K ofthe first flip-flop A is used to clock the second
tlip-flop B. Clocking of A by the burst gate is inhibited by a count
of A.B.
The count sequence can only be initiated by the trailing
edge of the frame pulse. ln order to provide control signals for:
Luma/Chroma blanking
Beam current sampling
On-screen display blanking
Brilliance control
The appropriate flip-flop outputs ar matrixed with sandcastle
and frame signals by an emitter-follower matrix.

Video Output Sections
Each video output stage consists of a feedback amplifier in A further drive current is used to control the DC operating
which the input signal is a current drive to the virtual earth from point; this is derived from the sample and hold stage which
the luminance, color difference and on-screen display stages. samples the beam current after frame flyback.












GENERAL BASIC TRANSISTOR LINE OUTPUT STAGE OPERATION:

The basic essentials of a transistor line output stage are shown in Fig. 1(a). They comprise: a line output transformer which provides the d.c. feed to the line output transistor and serves mainly to generate the high -voltage pulse from which the e.h.t. is derived, and also in practice other supplies for various sections of the receiver; the line output transistor and its parallel efficiency diode which form a bidirectional switch; a tuning capacitor which resonates with the line output transformer primary winding and the scan coils to determine the flyback time; and the scan coils, with a series capacitor which provides a d.c. block and also serves to provide slight integration of the deflection current to compensate for the scan distortion that would otherwise be present due to the use of flat screen, wide deflection angle c.r.t.s. This basic circuit is widely used in small -screen portable receivers with little elaboration - some use a pnp output transistor however, with its collector connected to chassis.

Circuit Variations:
Variations to the basic circuit commonly found include: transposition of the scan coils and the correction capacitor; connection of the line output transformer primary winding and its e.h.t. overwinding in series; connection of the deflection components to a tap on the transformer to obtain correct matching of the components and conditions in the stage; use of a boost diode which operates in identical manner to the arrangement used in valve line output stages, thereby increasing the effective supply to the stage; omission of the efficiency diode where the stage is operated from an h.t. line, the collector -base junction of the line output transistor then providing the efficiency diode action without, in doing so, producing scan distortion; addition of inductors to provide linearity and width adjustment; use of a pair of series -connected line output transistors in some large -screen colour chassis; and in colour sets the addition of line convergence circuitry which is normally connected in series between the line scan coils and chassis. These variations on the basic circuit do not alter the basic mode of operation however.

Resonance
The most important fact to appreciate about the circuit is that when the transistor and diode are cut off during the flyback period - when the beam is being rapidly returned from the right-hand side of the screen to the left-hand side the tuning capacitor together with the scan coils and the primary winding of the line output transformer form a parallel resonant circuit: the equivalent circuit is shown in Fig. 1(b). The line output transformer primary winding and the tuning capacitor as drawn in Fig. 1(a) may look like a series tuned circuit, but from the signal point of view the end of the transformer primary winding connected to the power supply is earthy, giving the equivalent arrangement shown in Fig. 1(b).

The Flyback Period:
Since the operation of the circuit depends mainly upon what happens during the line flyback period, the simplest point at which to break into the scanning cycle is at the end of the forward scan, i.e. with the beam deflected to the right-hand side of the screen, see Fig. 2. At this point the line output transistor is suddenly switched off by the squarewave drive applied to its base. Prior to this action a linearly increasing current has been flowing in the line output transformer primary winding and the scan coils, and as a result magnetic fields have been built up around these components. When the transistor is switched off these fields collapse, maintaining a flow of current which rapidly decays to zero and returns the beam to the centre of the screen. This flow of current charges the tuning capacitor, and the voltage at A rises to a high positive value - of the order of 1- 2k V in large -screen sets, 200V in the case of mains/battery portable sets. The energy in the circuit is now stored in the tuning capacitor which next discharges, reversing the flow of current in the circuit with the result that the beam is rapidly deflected to the left-hand side of the screen - see Fig. 3. When the tuning capacitor has discharged, the voltage at A has fallen to zero and the circuit energy is once more stored in the form of magnetic fields around the inductive components. One half -cycle of oscillation has occurred, and the flyback is complete.

Energy Recovery:
First Part of Forward Scan The circuit then tries to continue the cycle of oscillation, i.e. the magnetic fields again collapse, maintaining a current flow which this time would charge the tuning capacitor negatively (upper plate). When the voltage at A reaches about -0.6V however the efficiency diode becomes forward biased and switches on. This damps the circuit, preventing further oscillation, but the magnetic fields continue to collapse and in doing so produce a linearly decaying current flow which provides the first part of the forward scan, the beam returning towards the centre of the screen - see Fig. 4. The diode shorts out the tuning capacitor but the scan correction capacitor charges during this period, its right-hand plate becoming positive with respect to its left-hand plate, i.e. point A. Completion of Forward Scan When the current falls to zero, the diode will switch off. Shortly before this state of affairs is reached however the transistor is switched on. In practice this is usually about a third of the way through the scan. The squarewave applied to its base drives it rapidly to saturation, clamping the voltage at point A at a small positive value - the collector emitter saturation voltage of the transistor. Current now flows via the transistor and the primary winding of the line output transformer, the scan correction capacitor discharges, and the resultant flow of current in the line scan coils drives the beam to the right-hand side of the screen see Fig. 5.

Efficiency:
The transistor is then cut off again, to give the flyback, and the cycle of events recurs. The efficiency of the circuit is high since there is negligible resistance present. Energy is fed into the circuit in the form of the magnetic fields that build up when the output transistor is switched on. This action connects the line output transformer primary winding across the supply, and as a result a linearly increasing current flows through it. Since the width is
dependent on the supply voltage, this must be stabilised.

Harmonic Tuning:
There is another oscillatory action in the circuit during the flyback period. The considerable leakage inductance between the primary and the e.h.t. windings of the line output transformer, and the appreciable self -capacitance present, form a tuned circuit which is shocked into oscillation by the flyback pulse. Unless this oscillation is controlled, it will continue into and modulate the scan. The technique used to overcome this effect is to tune the leakage inductance and the associated capacitance to an odd harmonic of the line flyback oscillation frequency. By doing this the oscillatory actions present at the beginning of the scan cancel. Either third or fifth harmonic tuning is used. Third harmonic tuning also has the effect of increasing the amplitude of the e.h.t. pulse, and is generally used where a half -wave e.h.t. rectifier is employed. Fifth harmonic tuning results in a flat-topped e.h.t. pulse, giving improved e.h.t. regulation, and is generally used where an e.h.t. tripler is employed to produce the e.h.t. The tuning is mainly built into the line output transformer, though an external variable inductance is commonly found in colour chassis so that the tuning can be adjusted. With a following post I will go into the subject of modern TV line timebases in greater detail with other models and technology shown here at  Obsolete Technology Tellye !

TEA2261 SWITCH MODE POWER SUPPLY CONTROLLER:
The control means IP1 provide a soft start for a safe start-up after switching on the line power. This is accomplished via a resistor R5 charging slowly a capacitor C14 with a high capacitance which provides the necessary power for the integrated circuit IP1 at pins 15 and 16.
Additionally the SMPS starts with a low oscillating frequency to avoid a current build-up in the switching transistor T1. A current build-up can arise when the energy stored in the primary inductance is not fully transferred to the secondary side before a new conduction period is initiated. This will lead to operation in continuous mode and the switching transistor T1 may leave therefore his safe operating area. To reduce the oscillating frequency during start-up, the SMPS includes a resistor R511 and a diode D9 in series which connect the capacitor C26 with a capacitor C12 which is charged by the feed-back winding W2. The capacitor C12 is not charged up initially when the SMPS is switched on. Therefore, the diode D9 disconnects capacitor C26 from capacitor C12. The operating frequency is then fixed by R13 and C26, which is a low frequency (a few kHz). After a certain time capacitor C12 is charged up and then D9 will be conducting and an additional current will charge C26 via R511, thus the oscillating frequency increases to its normal operating frequency (about 22 kHz). This ensures that the SMPS starts safely in discontinuous mode, i.e. the energy stored in the primary inductance is always fully transferred to the secondary side before a new conduction period of transistor T1 is initiated.
The start-up of this known SMPS is depending on the charge-up time of capacitor C14 via resistor R5, therefore, depending on the voltage value of the AC mains input voltage. This leads to a quite long start-up time at a low mains input voltage.

The invention relates to a switch mode power supply (SMPS) comprising control means which include an oscillator for generating a pulse width modulated signal.
It is the object of the invention to provide a SMPS as previously described having a fast start-up time over a wide input voltage range. This object is accomplished with a switch mode power supply according to claim 1. The subclaims relate to preferred embodiments.

According to the invention, the switch mode power supply comprises a network which provides in case of a high input voltage a start-up with a low oscillation frequency only for the start-up time. After start-up, the oscillation frequency changes to the normal oscillating frequency. In case of a low input voltage, the network provides a start-up with essentially the normal oscillation frequency. This can be done without safety risk for the switching transistor because the operating voltages are low in this case. Even if a slight current build-up phenomenon occurs during start-up, the switching transistor stays in the safe operating area because of the low voltages. The network, therefore, includes means which change the oscillating frequency only in case of a high mains input voltage. No soft start is provided in case of a low mains input voltage. The frequency control of the oscillation frequency can be done advantageously by frequency control means including a transistor stage which change in case of a high mains input voltage the time constant of the oscillator network which determines the oscillation frequency.
In a special embodiment the network comprises a transistor used in inverse mode as a switching element. With this circuit arrangement an additional diode is not necessary. This utilizes the fact that the maximum collector base breakdown's voltage is distinctly higher than the maximum emitter base breakdown's voltage. The SMPS can be used especially for a TV receiver which works in a mains input voltage range of 90 V to 270 V, in a TV receiver the start-up time of the picture tube has to be considered additionally.

.POSITIVE AND NEGATIVE CURRENT UP TO
1.2A and – 2A
.LOW START-UP CURRENT
.DIRECT DRIVE OF THE POWER TRANSISTOR
.TWO LEVELS TRANSISTOR CURRENT LIMITATION
.DOUBLE PULSE SUPPRESSION
.SOFT-STARTING
.UNDER AND OVERVOLTAGE LOCK-OUT
.AUTOMATIC STAND-BY MODE RECOGNITION
.LARGE POWER RANGE CAPABILITY IN
STAND-BY (Burst mode)
.INTERNAL PWM SIGNAL GENERATOR


DESCRIPTION
The TEA2260/61 is a monolithic integrated circuit
for the use in primary part of an off-line switching
mode power supply.
All functions required for SMPS control under normal
operating,transient or abnormal conditions are
provided.
The capability of working according to the ”masterslave”
concept, or according to the ”primary regulation”
mode makes the TEA2260/61 very flexible
and easy to use. This is particularly true for TV
receivers where the IC provides an attractive and
low cost solution (no need of stand-by auxiliary
power supply).

GENERAL DESCRIPTION
The TEA2260/61 is an off-line switch mode power
supply controller. The synchronization functionand
the specificoperationin stand-bymodemake itwell
adapted to video applications such as TV sets,
VCRs, monitors, etc...
The TEA2260/61 can be used in two types of
architectures :
- Master/slave architecture. In this case, the
TEA2260/61 drives the power transistor according
to the pulse width modulated signals generated
by the secondary located master circuit. A
pulse transformer provides the feedback (see
Figure 1).
- Conventional architecture with linear feedback
signal (feedback sources : optocoupler or transformer
winding) (see Figure 2).

Using the TEA2260/61, the stand-by auxiliary
power supply, often realized with a small but costly
50Hz transformer, is no longer necessary. The
burst mode operation of the TEA2260/61 makes
possible the control of very low output power (down
to less than 1W) with the main power transformer.
When used in a master/slave architecture, the
TEA2260/61and also the power transistor turn-off
can be easily synchronized with the line transformer.
The switching noise cannot disturb the
picture in this case.
As an S.M.P.S.controller, the TEA2260/61features
the following functions :
- Power supply start-up (with soft-start)

- PWM generator
- Direct power transistor drive (+1.2A, -2.0A)
- Safety functions : pulse by pulse current limitation,
output power limitation, over and under voltage
lock-out.
S.M.P.S. OPERATING DESCRIPTION
Starting Mode - Stand By Mode
Power for circuit supply is taken from the mains
through a high value resistor before starting. As
long as VCC of the TEA2260/61 is below VCC start,
the quiescent current is very low (typically 0.7mA)
and the electrolytic capacitor across VCC is linearly
charged. When VCC reaches VCC start (typically
10.3V), the circuit starts, generating output pulses
with a soft-starting. Then the SMPS goes into the
stand-bymode and the output voltage is a percentage
of the nominal output voltage (eg. 80%).
For this the TEA2260/61 contains all the functions
required for primary mode regulation : a fixed frequency
oscillator, a voltage reference, an error
amplifier and a pulse width modulator (PWM).
For transmission of low power with a good efficiency
in stand-by, an automatic burst generation
system is used, in order to avoid audible noise.
Normal Mode (secondary regulation)
The normal operating of the TV set is obtained by
sending to the TEA2260/61regulation pulses generated
by a regulator located in the secondary side
of the power supply.
This architectureuses the ”Master-slave Concept”,
advantages of which are now well-known especially
the very high efficiency in stand-bymode, and
the accurate regulation in normal mode.
Stand-by mode or normal mode are obtained by
supplying or not the secondary regulator. This can
be ordonneredfor exemple by a microprocessor in
relation with the remote control unit.
Regulation pulses are applied to the TEA2260/61
through a small pulse-transformer to the IN input
(Pin 2). This input is sensitive to positive square
pulses. The typical threshold of this input is 0.85V.
The frequency of pulses coming from the secondary
regulator can be lower or higher than the
frequency of the starting oscillator.
The TEA2260/61has no soft-starting system when
it receives pulses from the secondary. The softstarting
has to be located in the secondary regulator.
Due to the principle of the primary regulation,
pulses generated by the starting system automatically

disappear when the voltage delivered by the

SMPS increases.
Stand-by Mode - Normal Mode Transition
During the transition there are simultaneously
pulses coming from the primary and secondary
regulators.
These signals are not synchronizedand some care
has to betaken toensure the safety of theswitching
power transistor.
Avery sure and simple way consist in checking the
transformer demagnetization state.
- A primary pulse is taken in account only if the
transformer is demagnetized after a conduction
of the power transistor required by the secondary
regulator.
- A secondary pulse is taken in account only if the
transformer is demagnetized after a conduction
of the power transistor required by the primary
regulator.
With this arrangement the switching safety area of
the power transistor is respected and there is no
risk of transformer magnetization.
The magnetization state of the transformer is
checked by sensing the voltage across a winding
of the transformer (generally the same which supplies
the TEA2261). This is made by connecting a
resistor between this winding and the demagnetization
sensing input of the circuit (Pin 1).

SECURITY FUNCTIONS OF THE TEA2261 (see flow-chart below)
- Undervoltage detection. This protection works
in association with the starting device ”VCC
switch” (see paragraph Starting-mode - standby
mode). If VCC is lower than VCCstop (typically
7.4V) output pulses are inhibited, in order to avoid
wrong operation of the power supply or bad
power transistor drive.
- Overvoltage detection. If VCC exceedsVCCmax
(typically 15.7V) output pulses are inhibited. Restarting
of the power supply is obtained by reducing
VCC below VCCstop.
- Current limitation of the power transistor. The
current is measured by a shunt resistor. Adouble
threshold system is used :
- When the first threshold (VIM1) is reached, the
conduction of the power transistor is stopped
until the end of the period : a new conduction
signal is needed to obtain conduction again.
- Furthermore as long as the first threshold is
reached (it means during several periods), an
external capacitor C2 is charged. When the
voltage across the capacitor reaches VC2 (typically
2.55V) the output is inhibited.This is called
the ”repetitive overload protection”. If the overload
diseappears before VC2 is reached, C2 is
discharged, so transient overloads are tolerated.
- Second current limitation threshold (VIM2).
When this thresholdis reached the output of the
circuit is immediatly inhibited. This protection is
helpfull in case of hard overload for example to
avoid the magnetization of the transformer.
- Restart of the power supply. After stopping due
to VC2, VIM2, VCCMax or VCCstop triggering, restart
of the power supply can be obtained by the
normal operating of the ”VCC switch” but thanks
to an integrted counter, if normal restart cannot
be obtained after three trials, the circuit is definitively
stopped. In this case it is necessary to
reduce VCC below approximately 5V to reset the
circuit. From a practical point of view, it means
that the power supply has to be temporarily disconnected
from any power source to get the
restart.



Synchronization + FRAME deflection output in one chip with TDA8215B (THOMSON)

FEATURES SUMMARY
■ DIRECT LINE DARLINGTON DRIVE
■ DIRECT FRAME-YOKE DRIVE (± 1A)
■ COMPOSITE VIDEO SIGNAL INPUT
CAPABILITY
■ FRAME OUTPUT PROTECTION AGAINST
SHORT CIRCUITS
■ PLL
■ VIDEO IDENTIFICATION CIRCUIT
■ SUPER SANDCASTLE OUTPUT
■ VERY FEW EXTERNAL COMPONENTS
■ VERY LOWCOST POWER PACKAGE
DESCRIPTION
The TDA8215B is an horizontal and vertical deflection
circuit with super sandcastle generator
and video identification output. Used with
TDA8213 (Video & Sound IF system) and
TDA8217 (Pal decoder and video processor), this
IC permits a complete low-cost solution for PAL
applications. The TDA8215B has been specially
designed for direct drive of line DARLINGTON
transistors.


GENERAL DESCRIPTION
The TDA8215B performs all the video and power
functions required to provide signals for the line
driver and frame yoke.
It contains:
– A synchronization separator
– An integrated frame separator without external
components
– A saw-tooth generator for the frame
– A power amplifier for direct drive of frame yoke
(short circuit protected)
– An open collector output for the line darlington
drive
– A line phase detector and a voltage control
oscillator
– A super sandcastle generator
– Video identification output.
The slice level of sync-separation is fixed by value
of the external resistors R1 and R2. VR is an internally
fixed voltage.
The sync-pulse allows the discharge of the capacitor
by a 2 x I current. A line sync-pulse is not able
to discharge the capacitor under VZ/2. A frame
sync-pulse permits the complete discharge of the
capacitor, so during the frame sync-pulse Q3 and
Q4 provide current for the other parts of the circuit.


ST6356B1/KR 8-BIT HCMOS PIGGYBACK MCUS. FOR TV APPLICATIONS

DEVICE TYPE :
_ ST63 PO6/ 7/8
- ST63P1 6/7/8
_ ST63P26/7/8
_ ST63P36/7/8
_ ST63 P56/7/8

EMULATION OF ST63XX DIP MASKED DEVICES

PIN TO PIN REPLACEMENT OF ALL ROM
MASKED DEVICES

8-BIT ARCHITECTURE

STATIC HCMOS OPERATION

4.5 T0 5.5 V SUPPLY OPERATING RANGE
4MHZ CLOCK OPERATION

PROGRAM ROM 2 16K BYTES EXTERNAL

DATA ROM 2 USER SELECTABLE SIZE
DATA RAM : 256 BYTES
DATA EEPROM : 128 BYTES

40/42 SHRINK/48 PIN DUAL—|N—L|NE PIGGYBACK CERAMIC PACKAGE

14/15 BIT PHASE LOCKED LOOP PERIPHE-
RAL (PLL, ST63P16/7/8, ST63P36/7/8 ONLY)
14 BIT VOLTAGE SYNTHESIS TUNING PERIPHERAL (VS, ST63P56/7/8 only)

SAME I/O PORT CONFIGURATION AS IN THE
MASKED PRODUCTS, INCLUDING DIRECT
LED DRIVING OUTPUTS

TWO TIMERS EACH INCLUDING AN 8-BIT
COUNTER WITH A 7—B|T PROGRAMMABLE
PRESCALER

DIGITAL WATCHDOG



SERIAL PERIPHERAL INTERFACE (SPI) SUPPORTING S—BUS IZCBUS AND STANDARD
SERIAL PROTOCOLS

ON—CHIP 5 LINES BY 15 COLUMNS ON-SCREEN-DISPLAY GENERATOR (NOT
AVAILABLE ON ST63P06/07/08 AND
ST63P1 6/7/8)

FOUR 6-BIT PWM D/A CONVERTERS

I AFC A/D CONVERTER WITH 0.5V RESOLUTION
INFRARED SIGNAL PREPROC ESSOR

- THREE INTERRUPT VECTORS(|R,TIMER 1 &

2, ST63PO6/7/8, ST63P16/7/8)

FOUR INTERRUPT VECTORS (IR, TIMER 1 &
2, OSD VSYNC, ST63P26/7/8, ST63P36/7/8,
ST63P56/7/8)

ON-CHIP CLOCK OSCILLATOR

ON-BOARD POWER—ON RESET CIRCUITRY
BYTE EFFICIENT INSTRUCTION SET

BIT TEST AND JUMP INSTRUCTIONS

WAIT AND BIT MANIPULATION INSTRUCTIONS

3_25ps TCYCLE (WITH 4.0 MHz CLOCK)

I TRUE LIFO 6—LEVEL STACK

THE DEVELOPMENT TOOL OF THE ST63XX
MICFIOCONTROLLERS CONSISTS OF THE
EMST63 HW/TVS EMULATION AND DEVELOPMENT SYSTEM AND CONNECTED VIA A
STANDARD RS232 SERIAL LINE TO AN MSDOS  PC.

GENERAL DESCRIPTION

The ST63PXX microcontrollers are piggyback
members of the 8-bit HCMOS ST63XX family, a
series of devices specially oriented to TV applications. Different packages and configurations are
available to offer different performance/cost tradeoffs. All ST63XX members are based on a building
block approach: to a common Core is associated a
combination of on-chip peripherals (macrocells)
available from a standard |ibrary.These peripherals
are designed with the same Core technology giving
full compatibility, short design and testing time.
Many of these macrocells are specially dedicated to
TV applications. These piggyback devices have the
same functions and pin configuration as all ROM
ST63XX masked products. In the piggyback devices instead of on-chip program and data ROM, the
relevant "address" and "data" lines are lead out to
the 28 pin socket which is directly located on the top
of the package, so that an external memory can be
addressed. These piggyback devices can operate
as an emulator to verify the user code, or for prototype/small volume production in order to test design
concept before commitment is made to high volume
production with masked ST63XX devices. The macrocells of the ST63PXX are: two 8-bit counter with
a 7-bit programmable prescaler (Timer), a Digital
Watchdog Timer, a Serial Peripheral Interface (SPI),
a 5 lines by 15 columns On-screen display generator (OSD, not available on ST63P06/7/8,
ST63P16/7/8), four 6-Bit PWM D/A Converters, an AFC A/D converter with 0.5V resolution, a 14 bit
Phase Locked Loop peripheral (PLL, ST63P16/7/8,
ST63P36/7/8 only). a 14 bit Voltage synthesis tuning peripheral (VS, ST63P56/7/8 only). In addition
all these devices have 128 bytes of on-chip EEPROM. Refers to ST63XX masked devices data-
sheets for additional information.

TDA8191 TV SOUND CHANNEL:

.  HIGH SENSITIVITY
.  EXCELLENT AM REJECTION
.  DC VOLUME CONTROL
.  PERITELEVISION FACILITY
.  4W OUTPUT POWER
.  LOW DISTORTION
.  THERMAL PROTECTION
.  TURN-ON AND TURN-OFF MUTING

DESCRIPTION
The TDA8191 is a monolithic integrated circuit that includes all the functions needed for a complete TV sound channel.The TDA8191 is assembled in a 20 pin dual in line power package.