NORDMENDE PRESTIGE 72 IMC CHASSIS F17 IMC (THOMSON ICC5 / ICC5341) INTERNAL VIEW

NORDMENDE PRESTIGE 72 IMC  CHASSIS F17 IMC (THOMSON ICC5 / ICC5341)  

The ICC5 got a bad press but they were an advanced design and unusual for the time for a European chassis in that they didn't make widespread use of Philips techniques or components.B&O sets have used it like the MX3000, MX4500 and MX5000. B&O had also used the previous ICC3 in the MX2000 and the M20, so they weren't much of a culture shock - the removal of the big mains transformer that the ICC3 had was clearly the key design goal.I found the chassis to be reasonably reliable after reworking and well laid out in general maybe a bit too compact, there were a few quirks without a doubt , the E-W stage once sorted with modified coil etc. wasn't so unreliable after all. The PCB layout was one of the most complex design almost like a computer board. It was only when they aged you started to get some real weird faults. The ICC7/8 were a lot more conventional circuitry wise, and posed few real problems. The ICC9 and IDC2 were not very reliable at all, possibly the least reliable of the lot, the IKC2 was a close second! Personally i disliked the IKC2.This models series are the last featuring the THOMSON CHASSIS ICC5, replaced with THOMSON ICC7, ICC8 SERIES.

 

  As any ICC5 it have had a high rate of failure due to dry joints all around the chassis.

When they're fully reworked they give almost never a problem after.

NORDMENDE PRESTIGE 72 IMC  CHASSIS F17 IMC (THOMSON ICC5 / ICC5341)   CIRCUIT DESCRIPTIONS:

 

NORDMENDE PRESTIGE 72 IMC  CHASSIS F17 IMC (THOMSON ICC5 / ICC5341)  COLOR TV SCANNING AND POWER SUPPLY PROCESSOR TEA2029C

DESCRIPTION
The TEA2029C is a complete (horizontal and vertical)
deflection processor with secondary to primary
SMPS control for color TV sets.

DEFLECTION .CERAMIC 500kHz RESONATOR FREQUENCY
REFERENCE .NO LINE AND FRAME OSCILLATOR ADJUSTMENT
.DUAL PLL FOR LINE DEFLECTION .HIGH PERFORMANCE SYNCHRONIZATION .SUPER SANDCASTLE OUTPUT .VIDEO IDENTIFICATION CIRCUIT .AUTOMATIC 50/60Hz STANDARD IDENTIFICATION
.EXCELLENT INTERLACING CONTROL .SPECIALPATENTED FRAME SYNCHRO DEVICE
FOR VCR OPERATION .FRAME SAW-TOOTH GENERATOR .FRAME PHASE MODULATOR FOR THYRISTOR
SMPS CONTROL .ERROR AMPLIFIER AND PHASE MODULATOR
.SYNCHRONIZATION WITH HORIZONTAL
DEFLECTION .SECURITY CIRCUIT AND START UP PROCESSOR.

GENERAL DESCRIPTION
This integrated circuit uses I2L bipolar technology
and combines analog signal processing with digital
processing.
Timing signals are obtainedfrom a voltage-controlled
oscillator (VCO) operatingat 500KHzby means
of a cheap ceramic resonator. This avoids the
frequency adjustment normally required with line
and frame oscillators.
A chain of dividers and appropriate logic circuitry
produce very accurately defined sampling pulses
and the necessary timing signals.
The principal functions implemented are :
- Horizontal scanning processor.
- Frame scanning processor. Two applications are
possible :
- D Class : Power stage using an external
thyristor.
- B Class : Powerstageusing an externalpower
amplifier with fly-back generator
such as the TDA8170.
- Secondary switch mode power regulation.
The SMPS output synchronize a primary I.C.
(TEA2260/61)at the mains part.
This concept allows ACTIVE STANDBY facilities.
- Dual phase-locked loop horizontal scanning.
- High performance frameand line synchronization
with interlacing control.
- Video identification circuit.
- Super sandcastle.
- AGC key pulse output.
- Automatic 50-60Hz standard identification.
- VCR input for PLL time constant and frame synchro
switching.
- Frame saw-tooth generator and phase modulator.
- Switchingmode regulated power supplycomprising
error amplifier and phase modulator.
- Security circuit and start-up processor.
- 500kHzVCO
The circuit is supplied in a 28 pin DIP case.
VCC = 12V.
Synchronization Separator
Line synchronization separator is clamped to
black level of input video signal with synchronization
pulse bottom level measurement.
The synchronization pulses are divided centrally
between the black level and the synchronization
pulse bottom level, to improve performance on
video signals in noise conditions.
Frame Synchronization
Frame synchronization is fully integrated (no external
capacitor required).
The frame timing identification logic permits automatic
adaptation to 50 - 60Hz standards or non-interlaced
video.
An automatic synchronization window width system
provides :
- fast frame capture (6.7ms wide window),
- good noise immunity (0.4ms narrow window).
The internal generator starts the discharge of the
saw-tooth generator capacitor so that it is not disturbed
by line fly back effects.
Thanks to the logic control, the beginning of the
charge phase does not depend on any disturbing
effect of the line fly-back.
A 32ms timing is automatically applied on standardized
transmissions, for perfect interlacing.
In VCR mode, the discharge time is controlled by
an internal monostable independent of the line
frequency and gives a direct frame synchronization.
Horizontal Scanning
The horizontalscanningfrequencyis obtainedfrom
the 500kHz VCO.
The circuit uses two phase-locked loops (PLL) :
the first one controls the frequency, the second one
controls the relative phase of the synchronization
and line fly-back signals.
The frequency PLL has two switched time constants
to provide :
- capture with a short time constant,
- good noise immunity after capture with a long
time constant.
The output pulse has a constant duration of 26ms,
independent of VCC and any delay in switching off
the scanning transistor.
Video Identification
The horizontal synchronization signal is sampled
by a 2ms pulse within the synchronization pulse.
The signal is integrated by an external capacitor.
The identification function provides three different
levels :
- 0V : no video identification
- 6V : 60Hz video identification
- 12V : 50Hz video identification
This information may be used for timing research
in the case of frequency or voltage synthetizer type
receivers, and for audio muting.
Super Sandcastle with 3 levels : burst, line flyback,
frame blanking
In the event of vertical scanning failure, the frame
blanking level goes high to protect the tube.
Frame blanking time (start with reset of Frame
divider) is 24 lines.
VCR Input
This provides for continuous use of the short time
constant of the first phase-locked loop (frequency).
In VCR mode, the frame synchronization window widens out to a search window and there is no
delay of frame fly-back (direct synchronization).
Frame Scanning
FRAME SAW-TOOTH GENERATOR. The current
to charge the capacitoris automatically switched to
60Hz operation to maintain constant amplitude.
FRAME PHASE MODULATOR (WITH TWO DIFFERENTIAL
INPUTS). The output signal is a pulse
at the line frequency, pulse width modulatedby the
voltage at the differential pre-amplifier input.
This signal is used to control a thyristor which
provides the scanning current to the yoke. The
saw-tooth output is a low impedance,however, and
can therefore be used in class B operation with a
power amplifier circuit.
Switch Mode Power Supply (SMPS) Secondary
to Primary Regulation
This power supply uses a differential error amplifier
with an internal reference voltage of 1.26V and a
phase modulator operating at the line frequency.
The powertransistor is turnedoff bythe falling edge
of the horizontal saw-tooth.
The ”soft start” device imposes a very small conduction
angle on starting up, this angle progressively
increases to its nominal regulation value.
The maximum conductionangle may be monitored
by forcing a voltage on pin 15. This pin may also
be used for current limitation.
The outputpulse is sent to the primaryS.M.P.S. I.C.
(TEA2261) via a low cost synchro transformer.
Security Circuit and Start Up Processor
When the security input (pin 28) is at a voltage
exceeding 1.26V the three outputs are simultaneously
cut off until this voltagedrops below the 1.26V
threshold again. In this case the switch mode
power supply is restarted by the ”soft start” system.
If this cycle is repeated three times, the three
outputs are cut off definitively. To reset the safety
logic circuits, VCC must be zero volt.
This circuit eliminates the risk to switch off the TV
receiver in the event of a flash affecting the tube.
On starting up, the horizontal and vertical scanning
functions come into operation at VCC = 6V. The
power supply then comes into operation progressively.
On shutting down, the three functions are interrupted
simultaneously after the first line fly-back.




APPLICATION INFORMATION ON FRAME
SCANNING IN SWITCHED MODE:


Fundamentals (see Figure 80)
The secondary winding of EHT transformer provides
the energy required by frame yoke.
The frame current modulation is achieved by
modulating the horizontal saw-tooth current and
subsequent integration by a ”L.C” network to reject
the horizontal frequency component.

General Description
The basic circuit is the phase comparator ”C1”
which compares the horizontal saw-tooth and the
output voltage of Error Amplifier ”A”.
The comparator output will go ”high” when the
horizontal saw-tooth voltage is higher than the ”A”
output voltage. Thus, the Pin 4 output signal is
switched in synchronization with the horizontal frequency
and the duty cycle is modulated at frame
frequency.
A driver stage delivers the current required by the
external power switch.
The external thyristor provides for energy transfer
between transformer and frame yoke.
The thyristor will conduct during the last portion of
horizontal trace phase and for half of the horizontal
retrace.
The inverse parallel-connected diode ”D” conducts
during the second portion of horizontal retrace and
at the beginning of horizontal trace phase.
Main advantages of this system are :
- Power thyristor soft ”turn-on”
Once the thyristor has been triggered, the current
gradually rises from 0 to IP, where IP will reach
the maximumvalue at the end of horizontal trace.
The slope current is determined by, the current
available through the secondary winding, the
yoke impedance and the ”L.C.” filter characteristics.
- Power thyristor soft ”turn-off”
The secondary output current begins decreasing
and falls to 0 at the middle of retrace. The thyristor
is thus automatically ”turned-off”.
- Excellent efficiency of power stage dueto very
low ”turn-on” and ”turn-off” switching losses.

Frame Flyback
During flyback, due to the loop time constant, the
frame yoke current cannot be locked onto the
reference saw-tooth. Thus the output of amplifier
”A” will remain high and the thyristor is blocked.
The scanning current will begin flowing through
diode ”D”. As a consequence, the capacitor ”C”
starts charging upto the flyback voltage.The thyristor
is triggeredas soon as the yoke current reaches
the maximum positive value.



TDA4443 MULTISTANDARD VIDEO IF AMPLIFIER  DESCRIPTION
The TDA4443 is a Video IF amplifier with standard
switch for multistandard colour or monochromeTV
sets, and VTR’s.

SWITCHING OFF THE IF AMPLIFIER WHEN
OPERATING IN VTR MODE .DEMODULATION OF NEGATIVE OR POSITIVE
IF SIGNALS. THE OUTPUT REMAINS
ON THE SAME POLARITY IN EVERY CASE .IF AGC AUTOMATICALLY ADJUSTED TO
THE ACTUALSTANDARD .TWO AGC POSSIBILITIES FOR B/G MODE :
1. GATED AGC
2. UNGATED AGC ON SYNC. LEVEL AND
CONTROLLED DISCHARGE DEPENDENT
ON THE AVERAGE SIGNAL LEVEL FOR VTR
AND PERI TV APPLICATIONS
FOR STANDARD L : FAST AGC ON PEAK
WHITE BY CONTROLLED DISCHARGE .POSITIVE OR NEGATIVE GATING PULSE .EXTREMELY HIGH INPUT SENSITIVITY .LOW DIFFERENTIAL DISTORTION .CONSTANT INPUT IMPEDANCE .VERY HIGH SUPPLY VOLTAGE REJECTION .FEW EXTERNAL COMPONENTS .LOW IMPEDANCE VIDEO OUTPUT .SMALL TOLERANCES OF THE FIXED VIDEO
SIGNALAMPLITUDE .ADJUSTABLE, DELAYED AGC FOR PNP
TUNERS.

GENERAL DESCRIPTION
This video IF processing circuit integrates the following
functional blocks : .Three symmetrical, very stable, gain controlled
wideband amplifier stages - without feedback
by a quasi-galvanic coupling. .Demodulator controlled by the picture carrier .Video output amplifier with high supply voltage
rejection .Polarity switch for the video output signal .AGC on peak white level .GatedAGC .Discharge control .Delayed tuner AGC .At VTR Reading mode the video output signal
is at ultra white level.

TBA120U (PHILIPS) GENERAL DESCRIPTION
The TBA120U is an i.f. amplifier with a symmetrical FM demodulator and an a.f. amplifier with adjustable output voltage.
The a.f. amplifier is also provided with an output for volume control and an input for VCR operation.
The input and output of the TBA120U are especially designed for LC-circuits, but the input can also be used with a
ceramic filter.

TDA4445A SOUND IF AMPLIFIER


.QUADRATURE INTERCARRIER DEMODULATOR
.VERY HIGH INPUT SENSITIVITY .GOODSIGNALTO NOISE RATIO .FAST AVERAGINGAGC .IF AMPLIFIER CAN BE SWITCHED OFF FOR
VTR MODE .GOODAM SUPPRESSION .OUTPUT SIGNAL STABILIZED AGAINST
SUPPLY VOLTAGE VARIATIONS .VERY FEW EXTERNAL COMPONENTS
DESCRIPTION
TDA4445A:
Sound IF amplifier, with FM processing for quasi
parallel sound system.
TDA4445B:
Sound IF amplifier, with FM processing and AM
demodulator, for multi-standard sound TV appliances.
TDA4445Badditionnal :
Bistandard applications (B/G and L)
No adjustment of the AM demodulator
Low AMdistortion.


GENERAL DESCRIPTION
This circuit includes the following functions : .Three symmetrical and gain controlled wide
band amplifier stages, which are extremely stable
by quasiDC coupling without feedback. .Averaging AGC with discharge control circuit .AGC voltage generator
Quasi parallel sound operation : .High phase accuracy of the carrier signal processing,
independentfrom AM .Linear quadrature demodulator .Sound-IF-amplifier stage with impedance converter
AM-Demodulation (only TDA4445B) : .Carrier controlled demodulator .Audio frequency stage with impedance converter
.Averaging low passAGC.

NORDMENDE PRESTIGE 72 IMC  CHASSIS F17 IMC (THOMSON ICC5 / ICC5341)    CHASSIS ICC5 Switched mode power supply transformer


A switched mode power supply transformer, particularly for a television receiver, including a primary winding and a secondary winding with the primary winding and the secondary winding each being subdivided into a plurality of respective partial windings. The partial windings of the primary lie in a first group of chambers and the partial windings of the secondary lie in a second group of chambers of a chamber coil body, and the chambers of both groups are nested or interleaved with one another.







1. A switched mode power supply transformer, particularly for a television receiver, comprising in combination:
a primary winding and a secondary winding, with said primary winding being subdivided into three partial windings and said secondary winding being subdivided into two partial windings;
a chamber coil body having a plurality of chambers;
said partial windings of said primary winding being disposed only in a first group of said chambers, and said partial windings of said secondary winding being disposed only in a second group of said chambers, with each of said partial windings being disposed in a respective one of said chambers;
said chambers of said first group being interleaved with said chambers of said second group such that they alternate in sequence with said primary partial windings and said secondary partial windings being alternatingly disposed in five successive said chambers, so as to generate the major operating voltage at said secondary winding;
an additional secondary winding for generating a further operating voltage, said additional secondary winding likewise being subdivided into a plurality of partial windings; and,
said partial windings of said additional secondary winding are disposed only in respective said chambers of said second group below any of said partial windings of said secondary winding.


2. A transformer as defined in claim 1 wherein the total number of said chambers is six.

3. A transformer as defined in claim 1 wherein the width of the narrowest of said chambers is approximately 1 mm.

4. A transformer as defined in claim 1 or 2 wherein the widths of said chambers are different.

5. A transformer as defined in claim 1 or 2 wherein the total width of all of said chambers is only approximately 20 mm, whereby a flat and optimally coupled transformer is realized.

6. A transformer as defined in claim 1 wherein said additional secondary winding provides an operating voltage for a load which has a fluctuating current input.

7. A transformer as defined in claim 1 wherein said partial windings of said additional secondary winding are connected in parallel.

8. A transformer as defined in claim 1 wherein said partial windings of said primary winding are connected in series.

9. A transformer as defined in claim 1 or 8 wherein said partial windings of said secondary winding are connected in series.

10. A transformer as defined in claim 1 further comprising a plurality of auxiliary primary windings disposed in one chamber of said first group which is disposed in approximately the center of said first group and above the said partial winding of said primary winding disposed in said one chamber of said first group.

11. A transformer as defined in claim 1 wherein all of said partial winding disposed in said chambers of both said groups are wound with wire having the same diameter.

12. A switched mode power supply transformer as defined in claim 1 or 10 wherein: said coil body has six of of said chambers; said additional secondary winding is subdivided into three said partial windings; and two of said partial windings of said additional secondary winding are disposed below respective ones of said partial windings of said secondary winding and the third said partial winding of said additional secondary winding is disposed in the sixth said chamber.

13. A switched mode power supply transformer as defined in claim 10 further comprising at least one further secondary winding disposed in one of said chambers of said second group above any partial secondary winding present in said one of said chambers.

14. A switched mode power supply transformer, particularly for a television receiver, comprising in combination:
a primary winding and a secondary winding, with said primary winding and said secondary winding each being subdivided into a plurality of partial windings;
a chamber coil body having a plurality of chambers;
said partial windings of said primary winding being disposed only in a first group of said chambers, and said partial windings of said secondary winding being disposed only in a second group of said chambers with each of said partial windings being disposed in a respective one of said chambers;
said chambers of said first group being interleaved with said chambers of said second group such that said primary partial windings and said secondary partial windings are alternatingly disposed in successive said chambers, so as to generate the major operating voltage at said secondary winding;
an additional secondary winding for generating a further operating voltage, said additional secondary winding likewise being subdivided into a plurality of partial windings, and said partial windings of said additional secondary winding are disposed only in respective said chambers of said second group below any of said partial windings of said secondary winding.


15. A switched mode power supply transformer as defined in claim 1 or 14 wherein each of said partial windings of said primary winding contains the same number of turns and each of said partial windings of said secondary winding contains the same number of turns.

Description:

BACKGROUND OF THE INVENTION
The present invention relates to a switched mode power supply transformer, particularly for a television receiver.
In communications transmissions devices, particularly in television receivers, it is known to effect the desired dc decoupling from the mains by means of so-called switched mode power supply transformers. Such switched mode power supply transformers are substantially smaller and lighter in weight than a mains transformer for the same power operating at 50 Hz, because they operate at a significantly higher frequency of about 20-30 kHz. Such a switched mode power supply transformer (hereinafter called SMPS transformer) generally includes a primary side with a primary winding serving as the operating winding for the switch and further additional auxiliary windings, as well as a secondary side with a secondary winding for generating the essential operating voltage and possibly further additional windings for generating further operating voltages of different magnitude and polarity. The secondary and primary are insulated from one another as prescribed by VDE and have the necessary dielectric strength so that there is no danger of contact between voltage carrying parts on the secondary. A switched mode power supply (SMPS) circuit for a tv-receiver is described in U.S. Pat. No. 3,967,182, issued June 29, 1976.
A further requirement placed on such an SMPS transformer is that the stray inductance at least of the primary winding and of the secondary winding should be as small as possible. With too high a stray inductance, a transient behavior may develop during the switching operation which would not assure optimum switch operation of the switching transistor connected to the primary winding and would endanger this transistor by taking on too much power. Moreover, an increased stray inductance undesirably increases the internal resistance of the voltage sources for the individual operating voltages.
It is known to design the windings for such transformers as layered windings. Such layered windings, however, contain feathered intermediate foil layers and, after manufacture, generally require that the coil or the complete transformer be encased in order to insure VDE safety. Use as a chamber winding in television receivers presently does not take place because of the problems to be discussed below. A chamber winding would have the particular advantage that it could be wound more easily and economically by automatic machines. when using a chamber winding for a switched mode power supply, the detailed insulation between the primary and the secondary would be realized initially by two chambers with one of these chambers being filled only with the windings of the primary and the other of these chambers being filled only with the windings of the secondary. However, with such an arrangement there would exist only slight coupling between the primary and the secondary and thus an undesirably high stray inductance. If, on the other hand, the number of chambers were selected to be substantially larger, the transformer becomes more expensive and unnecessarily large. Moreover, a larger core would be required. Consequently, in the past, no television receiver has been introduced that included an SMPS transformer.
SUMMARY OF THE INVENTION
It is the object of the present invention to provide an SMPS transformer designed in the chamber wound technique which permits economical automatic winding, i.e. can be wound with but a single type of wire, has a structure which is spatially narrow and as flat as possible, provides the required insulation between the primary and secondary windings, and has a low stray inductance. The transformer should not be encased or saturated and nevertheless should produce no interfering noise during operation. The transformer should be able to be held in a circuit board without mechanical aids merely by its connecting terminals which are soldered to the circuit board.
The above object is basically achieved according to the present invention in that the transformer for a switched mode power supply, particularly for a television receiver, comprises: a primary winding and a secondary winding with the primary and secondary windings each being subdivided into a plurality of partial windings; and a chamber coil body with a plurality of chambers; and wherein the partial windings of the primary winding are disposed in a first group of chambers of the coil body, the partial windings of the secondary winding are disposed in a second group of chambers of the coil body, and the chambers of the first and second groups are interleaved.
Due to the fact that the individual windings or partial windings of the primary are disposed only in chambers of the first group and the windings or partial windings of the secondary are disposed only in chambers of the second group, i.e. primary and secondary are distributed to separate chambers, the necessary dielectric strength between primary and secondary is assured. By dividing each of the primary and secondary windings to a respective plurality or group of chambers and, due to the interleaved or nested arrangement of the chambers of the primary and the secondary, the desired fixed coupling between primary and secondary, and thus the desired low stray inductance at the primary and secondary, are realized. It has been found that a total number of chambers in the order of magnitude of six constitutes an economically favorable solution. With a smaller number of chambers, the coupling between primary and secondary is reduced. With a larger number of chambers, however, either the individual chambers become too small or the entire transformer, and particularly the core, become too large.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a circuit diagram for a preferred embodiment of a switched mode power supply transformer according to the invention.
FIG. 2 is a schematic partial sectional view showing the distribution of the individual windings of FIG. 1 to different chambers according to the invention.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT
FIG. 1 shows a transformer intended for a switched mode power supply for a television receiver with a power output between 40 and 150 watts. The transformer includes a primary side P and a secondary side S which, while maintaining the required dielectric strength of, for example, 10,000 V, are galvanically decoupled or separated from one another. The primary side P includes a primary winding 1 which, as the operating winding, will lie in the collector circuit of a switching transistor switched at about 20-30 kHz. The primary winding 1 is divided into three partial windings 1a, 1b and 1c which are connected in series. When utilized in a television receiver, the beginning of partial winding 1a and the end of partial winding 1c are connected into the collector circuit of the switching transistor, while the taps between the partial windings 1a-1b and 1b-1c are not utilized, but rather form supporting points for the connection of the terminals of the partial windings. The primary side P also includes an additional winding 3 which feeds the feedback path with which the primary winding 1a-1c is designed as a self-resonant circuit. Moreover, the primary side P includes an additional winding 4 for regulating the moment of current flow in the switching transistor in the sense of stabilizing the amplitude of the output voltages on the secondary side S.
The secondary side S initially includes the secondary winding 2 from which is obtained, via a rectifier circuit (not shown), the main operating voltage U1. The secondary winding 2 is divided into two series connected partial windings 2a and 2b. Additionally, the secondary winding S includes a winding 5 for generating an operating voltage for the video amplifier and a further winding 6 for generating the operating voltage for the vertical deflection stage of a television receiver. Moreover, an additional secondary winding 7 is provided from which, after rectification, the operating voltage or the audio output stage of the receiver is obtained. Winding 7 comprises three partial windings 7a, 7b, 7c which are connected in parallel. The audio output stage of a television receiver has a greatly fluctuating current input between 50 mA and 1000 mA so that the load of the secondary side S varies considerably. This variation in load may effect an undesirable change in the operating voltage U1 which also influences the horizontal deflection amplitude. This undesirable dependency can be reduced in that the coupling between winding 7 and winding 4 is dimensioned greater, for regulating purposes, than the coupling between winding 2 and winding 4. This solution is described in greater detail in Federal Republic of Germany Offenlegungsschrift (laid open application) DE-OS No. 2,749,847 of May 10, 1979. This increased coupling between windings 7 and 4 is realized in the present case by the three parallel connected windings 7a, 7b, 7c. Finally, the secondary S includes a further winding 8 which serves to generate, after rectification, a negative operating voltage of -30 V.
FIG. 2 shows one half of the chamber coil body 9 for the individual windings of FIG. 1, with the body 9 including a total of six chambers 10. The size and particularly the widths of the individual chambers 10 can vary with respect to one another and the widths may all be different. Preferably, the width of the narrowest chamber 10 is about 1 mm and the total width of all six chambers is only approximately 20 mm so as to realize a flat and optimally coupled transformer.
As shown, one third of the primary winding 1, in the form of respective partial windings 1a, 1b and 1c, is distributed to each of the first, third and fifth chambers 10 of the coil body 9. The additional primary windings 3 and 4 are disposed in the third chamber 10 above the partial winding 1b. One half of the secondary winding 2, in the form of respective partial windings 2a, 2b, is distributed to each of the second and fourth chambers 10 of the coil body 9. The three partial windings 7a, 7b and 7c of the additional secondary winding 7 for the audio output stage are distributed to the second, fourth and sixth chambers 10, respectively, with the partial windings 7a-7c being disposed closest to the longitudinal axis of the coil body 9 and thus below any partial secondary winding 2a, 2b or other secondary winding which may be located in the same chamber. That is, the partial windings 7a and 7b are disposed below the partial windings 2a and 2b, respectively, in the respective second and fourth chambers 10, and below the additional secondary windings 5 and 8 in the sixth chamber 10. Further winding 6 is disposed above partial secondary winding 2b.
As can be seen in FIG. 2, the chambers 10 contain alternatingly only windings or partial windings of the primary side P or of the secondary side S. The illustrated nesting or interleaving of the windings, i.e. the alternating arrangement of windings of the primary side P and of the secondary side S in successive chambers 10, assures the desired close coupling between the primary side P and the secondary side S. The arrangement of the windings 3, 4 in approximately the center of the coil body 9 above partial winding 1b assures the desired close coupling between the windings 3, 4 with the other windings.
In an embodiment of the transformer shown in FIGS. 1 and 2 which was successfully tested in practice, the individual windings were all wound with the same diameter wire and contained the following numbers of turns:

______________________________________

Winding No. Number of Turns

______________________________________

1a 22 1b 22 1c 22 2a 30 2b 30 3 3 4 10 5 25 6 1 7a 11 7b 11 7c 11 8 16

______________________________________

The diameter of the wire of the windings 1-8 may be about 0.40 or 0.45 mm. Also, each winding may exist of two parallel shunted wires each of 0.3 mm diameter. The width of the six chambers 10--seen from the left to the right in FIG. 2--may be 0.95/1.95/1.75/1.95/0.95/2.75 mm and the thickness of the walls forming the chambers 0.65 mm.
It will be understood that the above description of the present invention is susceptible to various modifications, changes and adaptations, and the same are intended to be comprehended within the meaning and range of equivalents of the appended claims.

 

NORDMENDE PRESTIGE 72 IMC  CHASSIS F17 IMC (THOMSON ICC5 / ICC5341)   NS5000 Raster distortion correction circuitry Unit for a video display apparatus that includes a square-planar picture tube

A video display apparatus incorporates a picture tube, such as a square-planar picture tube, that includes a phosphor screen located on a faceplate having an aspherically curved geometry that produces a relatively flat surface contour. Deflection circuitry generates line and field scanning currents in respective line and field deflection windings to enable the electron beams of the picture tube to scan a raster on the phosphor screen. The electron beams are subject to a scanning error that results in raster distortion, such as side pincushion distortion. A parabola generator produces a parabolic modulation of the scanning of the electron beams to generally correct the raster distortion while retaining a residual error due to the aspherically curved geometry of the faceplate. A nonlinear waveshaping circuit modifies the parabolic modulation of the scanning current in accordance with the aspherically curved geometry to provide additional modulation of the electron beam scanning for correcting the residual error. The nonlinear waveshaping circuit includes a current source and a switched current divider that is responsive to a threshold level of the parabolic voltage developed by the parabola generator.

1. Video display apparatus with correction of raster distortion, comprising:
a picture tube having a phosphor screen located on a faceplate having an aspherically curved surface contour, with at least one of a minor and major axis exhibiting a curvature that changes from an edge of the faceplate to the center;
deflection means including horizontal and vertical deflection windings for generating respectively therein horizontal and vertical deflection currents to enable an electron beam of said picture tube to scan a raster on said phosphor screen;
a parabola generator coupled to said deflection means for generating a generally parabolically shaped signal that produces a parabolic modulation of the scanning of said electron beam to generally provide correction of a first raster distortion while leaving uncorrected a residual raster distortion due to the change in curvature of said faceplate from said edge to the center; and
means for nonlinearly modifying said (parabolic modulation) parabolically shaped signal as a function of said change in curvature of said faceplate to provide additional modulation of the scanning of said electron beam for correcting said residual raster distortion.
2. Apparatus according to claim 1 wherein said first raster distortion results in side pincushion raster distortion and wherein said faceplate has an aspherically curved geometry that results in areas of said faceplate near the top and bottom being of increased curvature relative to the curvature in areas near the center. 3. Apparatus according to claim 2 wherein said residual raster distortion comprises a barrel-like distortion of a raster display of a vertical line pattern in said areas near the top and bottom of said faceplate. 4. Apparatus according to claim 2 wherein said nonlinearly modifying means comprises a current source coupled to said parabola generator and a switched current divider that switches from a first conductive state to a second conductive state during that portion of a vertical trace interval when a raster is being scanned on said faceplate in said areas of increased curvature. 5. Apparatus according to claim 4 wherein said parabolically shaped signal is a generally parabolically shaped input voltage repeating at a vertical deflection rate and having both a DC component voltage and an AC parabolic component voltage and wherein said switched current divider comprises an impedance receiving a constant current from said current source for establishing a bias voltage level and switching means responsive to said bias voltage level and direct current coupled to said parabola generator for shunting a portion of said constant current when said input voltage goes beyond a threshold voltage level established in accordance with said bias voltage level to modify the waveshape of said input voltage in a manner that corrects said residual raster distortion. 6. A circuit for correcting a given error of electron beam positioning in a video display apparatus, comprising:
a deflection winding;
an output stage for generating current in said deflection winding to control said electron beam positioning;
a parabolic voltage generator for developing a generally parabolically shaped input voltage repeating at a deflection rate and having both a DC component voltage and an AC parabolic component voltage;
an amplifier for driving said output stage in accordance with said parabolically shaped input voltage to generally correct said given error while retaining a residual error of said electron beam positioning;
a current source;
an impedance receiving current from said current source for establishing a bias voltage level; and
switching means responsive to said bias voltage level and direct current coupled to said parabolically shaped input voltage for shunting a portion of the current from said current source when said input voltage goes beyond a threshold voltage level established in accordance with said bias voltage level to modify the waveshape of said input voltage in a manner that corrects said residual error.
7. A circuit according to claim 6 wherein said switching means is direct current coupled to an output terminal of said parabolic voltage generator, at which terminal said input voltage is developed, and which is direct current coupled to a terminal of said impedance, at which impedance terminal said bias voltage level is developed. 8. A circuit according to claim 7 wherein said switching means comprises a diode in which there flows the shunted portion of current from said current source. 9. A circuit according to claim 7 wherein the shunted portion of current from said current source establishes a modified parabola voltage at an output terminal of said switching means that is direct current coupled to the output terminal of said parabolic voltage generator, said modified parabola voltage having a waveform that generally follows the waveform of said input voltage when said switching means is in one conductive state and having a waveform of waveshape that is substantially different than that of said input voltage when said switching means is in another conductive state. 10. A circuit according to claim 9 including means for AC coupling said modified parabola voltage to said amplifier. 11. A circuit according to claim 10 including means for adjusting said bias voltage level to adjust the switching instants of said switching means and wherein a peak amplitude of said modified parabola voltage remains substantially unchanged for different adjustments of said bias voltage level. 12. A circuit according to claim 11 including an adjustable voltage divider coupled to said AC coupling means and direct current coupled to said amplifier for adjusting the amplitude of the AC coupled modified parabola voltage, and wherein the peak amplitude of the modified parabola voltage that is established at the output terminal of said switching means remains substantially unchanged for different adjustments of said voltage divider. 13. A circuit according to claim 9 wherein said input voltage includes an AC sawtooth component voltage repeating at said deflection rate and further including means for applying said sawtooth component voltage to said impedance to provide common-mode rejection of said sawtooth component voltage with respect to the shunted portion of current from said current source. 14. A circuit according to claim 9 wherein said switching means applies an additional voltage to said terminal of said impedance that is representative of the difference between said bias voltage level and said input voltage to control the amplitude of the shunted portion of current in accordance with said additional voltage. 15. A circuit according to claim 9 wherein said current source comprises a source of DC voltage coupled to a second impedance, and wherein said switching means applies an additional voltage to said terminal of the first mentioned impedance that is representative of a difference between said bias voltage level and said input voltage. 16. A circuit according to claim 15 wherein said DC voltage of said DC voltage source is substantially greater in magnitude than that of said additional voltage to prevent significant changes from occurring in the magnitude of said current source when said switching means changes conductive states. 17. A circuit according to claim 6 wherein said video display apparatus includes a picture tube having a phosphor screen located on a faceplate having an aspherically curved geometry that produces a relatively flat surface contour and wherein said residual error of electron beam positioning is produced in accordance with said aspherically curved geometry. 18. A circuit according to claim 17 wherein said given error is produced by side pincushion distortion and wherein said residual error produces a barrel-like distortion of a raster display of a vertical line pattern in regions near the top and bottom of said faceplate where the curvature of said faceplate is increased relative to the curvature in the center region. 19. Apparatus according to claim 1 wherein said nonlinearly modifying means produces a parabolic modulation when scanning raster lines near top and bottom of said raster that is different than when scanning raster lines near raster center for correcting said residual raster distortion due to the aspherically curved geometry of said faceplate.

Description:

This invention relates to electron beam positioning error correction circuitry in a video display apparatus.
New, flatter faceplate picture tubes, such as the RCA Corporation square-planar picture tubes, have aspherically curved faceplate contours. A tube of this type, having a complex curvature faceplate, is described in the following U.S. patent applications, herein incorporated by reference.
1. U.S. patent application Ser. No. 469,772, filed Feb. 25, 1983, by F. R. Ragland, Jr. entitled CATHODE-RAY TUBE HAVING AN IMPROVED SHADOW MASK CONTOUR.
2. U.S. patent application Ser. No. 469,774, filed Feb. 25, 1983 by F. R. Ragland, Jr. entitled CATHODE-RAY TUBE HAVING A FACEPLATE PANEL WITH A SUBSTANTIALLY PLANAR PERIPHARY.
3. U.S. patent application Ser. No. 469,775, filed Feb. 25, 1983, by R. J. D'Amato et al., entitled CATHODE-RAY TUBE HAVING DIFFERENT CURVATURE ALONG MAJOR AND MINOR AXES.
4. U.S. patent application Ser. No. 529,644, filed Sept. 6, 1983, by R. J. D'Amato et al., entitled CATHODE-RAY TUBE HAVING A FACEPLATE PANEL WITH AN ESSENTIALLY PLANAR SCREEN PERIPHERY.
In one form of flatter faceplate picture tube, as typified by the RCA 110° COTY-SP, square-planar, 27 V, color television picture tube, A68ACC10X, the formula for the tube faceplate sagittal height, z, in millimeters, with reference to the center of the faceplate is given by: Z=A ₁ X ² +A ₂ X ⁴ +A ₃ Y ² +A ₄ X ² Y ² +A ₅ X ⁴ Y ² +A ₆ Y ⁴ +A ₇ X ² Y ⁴ +A ₈ X ⁴ Y ⁴ ,
where X and Y are the distance coordinates, in millimeters, from the faceplate center along the major and minor axes, respectively, and where: A ₁ =-0.236424229×10 ^-4 A ₂ =-0.363538575×10 ^-8 A ₃ =-0.422441063×10 ^-3 A ₄ =-0.213537355×10 ^-8 A ₅ =+0.883912220×10 ^-13 A ₆ =-0.100020398×10 ^-9 A ₇ =+0.117915353×10 ^-14 A ₈ =+0.527722295×10 ^-21
The picture tube faceplate defined by this formula has a relatively shallow curvature near the center of the faceplate, which increases near the edges along paths parallel to both the major and minor axes of the tube. The overall result is a faceplate of relatively flat appearance and with planar edges, namely, with points along the top, bottom, right and left edges located substantially in a common plane.
In general, the raster scanned on the phosphor screen of a picture tube may exhibit an east-west or side pincushion raster distortion. This distortion may be substantially corrected by a side pincushion correction circuit that produces a parabolic amplitude modulation of the horizontal deflection current. The required vertical rate parabola voltage may be obtained from the vertical deflection circuit by integration of the vertical sawtooth current.
When using such a conventional circuit for raster correction in a picture tube, such as a square-planar picture tube that has an aspherically curved faceplate, a small but often objectionable raster distortion may remain at the top and bottom of the display, as illustrated by the solid vertical lines of a raster R display R in FIG. 1. Due to the aspherically curved geometry of the faceplate, the vertical line bend away from the vertical direction near the top and bottom of the raster display, where the curvature of the faceplate increases. The overall appearance of the vertical lines in FIG. 1 is slightly barrel-shaped.
In accordance with an aspect of the invention, a video display apparatus includes a picture tube having a phosphor screen located on a faceplate having an aspherically curved geometry. Correction circuitry is provided that compensates for raster distortion or electron beam positioning errors, such as pincushion or convergence distortions. The correction circuitry includes a parabola generator coupled to deflection circuitry for producing a parabolic modulation of the scanning of the electron beam. The modulation generally provides correction of the raster distortion or electron beam positioning error, while retaining a residual error due to the aspherically curved geometry of the faceplate. The modulation is nonlinearly modified in accordance with the aspherically curved geometry to provide additional modulation of the scanning of the electron beam for correcting the residual error.
In accordance with another aspect of the invention, a particularly advantageous arrangement of correction circuitry smoothly straightens the bent vertical lines near the top and bottom of the raster display illustrated in FIG. 1.
The parabola generator of the correction circuit arrangement produces a generally parabolically shaped input voltage repeating at a deflection rate. An amplifier drives an output stage that generates current in a deflection winding to control the electron beam landing position. The amplifier is responsive to the output of the parabola generator for driving the output stage in accordance with the parabolically shaped input voltage to generally correct electron beam landing error, while retaining a residual error. A current source with a switched current dividing network is responsive to a threshold level of the parabolically shaped input voltage for supplying to the amplifier a portion of the current from the current source when the input voltage exceeds the threshold level to correct the residual error.
FIG. 1 illustrates vertical lines of a raster display scanned on the screen of a square-planar picture tube;
FIG. 2 illustrates in block diagram form raster scanning circuitry used in conjunction with raster scanning on the aspherically curved faceplate of a square-planar picture tube, shown schematically in FIG. 2 from a side elevation view, in partial breakaway;
FIG. 3 illustrates detailed embodiments of the horizontal and vertical deflection circuits of FIG. 2, including circuitry embodying the invention that corrects for the residual side pincushion distortion illustrated in FIG. 1;
FIG. 4 illustrates a detailed embodiment of a portion of the circuit of FIG. 3; and
FIG. 5 illustrates waveforms useful in explaining operation of the circuits of FIGS. 3 and 4.
In FIG. 1, there is illustrated vertical lines of a raster display R that is generated on the phosphor screen of a faceplate 30 of a square-planar picture tube SP of FIG. 2. Horizontal and vertical deflection circuits 20 and 40 of FIG. 2 generate horizontal and vertical deflection currents in horizontal and vertical deflection windings L _H and L _V , respectively. The horizontal and vertical deflection currents deflect electron beams 18 in square-planar picture tube SP to produce raster display R on faceplate 30.
Square-planar picture tube SP incorporates a glass envelope 11 comprising a generally rectangular faceplate panel 19 and a tubular neck 14 connected by a funnel 16. Panel 19 comprises viewing faceplate 30 and a peripheral flange or side wall 12, which is sealed to funnel 16 by a glass frit 17. A generally rectangular 3-color cathodoluminescent phosphor screen 15 is carried by the inner surface of faceplate 30. The screen may be a line screen, with the phosphor lines extending substantially parallel to the minor or vertical axis Y--Y of the tube. Alternatively, the screen may be a dot screen. A multi-aperture color selection electrode or shadow mask 13 is removably mounted within panel 19 in predetermined spaced relation to screen 15. An electron gun 10, shown schematically by dashed lines in FIG. 2, is centrally mounted within neck 14 to generate and accelerate the three electron beams 18 along convergent paths through mask 13 to screen 15.
The line and field deflection currents in line and field deflection windings L _H and L _V , respectively, subject the three electron beams 18 to vertical and horizontal magnetic flux that scans the beams horizontally in the direction of the major or horizontal axis X--X and vertically in the direction of the minor axis Y--Y, in a rectangular raster pattern over screen 15. The longitudinal axis of picture tube SP is labeled Z--Z in FIG. 2.
Faceplate 30 of square-planar color picture tube SP is relatively flat. The curvature of the faceplate is complex and may be approximated in accordance with the polynominal expression given above. In the field scanning direction, or as the electron beams are scanned from top edge to bottom edge, vertically, the curvature of the faceplate decreases from top edge to center and then increases again to the bottom edge. A similar situation holds in the line scanning direction.
Assume that horizontal and vertical deflection circuits 20 and 40 of FIG. 2 correct for distortions such as S-distortion, north-south and gullwing distortion. Furthermore, assume that horizontal deflection circuit 20 generally corrects for side pincushion distortion by parabolically modulating the amplitude of the horizontal deflection current. The display of a vertical line pattern on faceplate 30 by means of raster line scanning produces a raster display such as illustrated in solid-line in FIG. 1. The generally vertical lines exhibit a residual distortion at the top and bottom of the raster which, due to the aspherically curved geometry of faceplate 30, causes the vertical raster lines to be bent inward toward the center in a barrel-like manner.
In accordance with a feature of the invention, horizontal deflection circuit 20 nonlinearly modifies the parabolic modulation of the horizontal deflection current to straighten the vertical lines at the top and bottom of the raster, as illustrated by the dashed-line, straight line segments of FIG. 1.
FIG. 3 illustrates detailed embodiments of vertical deflection circuit 40 and horizontal deflection circuit 20 of FIG. 2 that include nonlinear waveshaping circuitry in accordance with an aspect of the invention. In horizontal deflection circuit 20 of FIG. 3, a B+ voltage is applied to the primary winding W _p of a flyback transformer T1 via a small valued resistor 21. A capacitor 22 provides filtering. Primary winding W _p is coupled to a horizontal output stage 70 of horizontal deflection circuit 20. Horizontal output stage 70 includes a horizontal oscillator and driver 25, a horizontal output transistor Q1, a first retrace capacitor C _R1 coupled across transistor Q1, a damper diode D2, a second retrace capacitor C _R2 coupled across diode D2 and the series arrangement of a linearity inductor 26, and S-shaping capacitor C _s , deflection winding L _H of FIG. 2, and a resonant circuit 27, comprising a capacitor C1 in parallel with the inductance of a tapped winding W1 of a transformer T2. Deflection winding L _H is coupled to the tap terminal of winding W1.
Resonant circuit 27 is tuned to produce approximately two cycles of oscillation during the horizontal trace interval for introducing an oscillatory current component into horizontal deflection current i _H that provides dynamic S-correction of the raster scanned on faceplate 30 of square-planar picture tube SP of FIG. 1. The function of dynamic S-correction, resonant circuit 27 is more fully described in U.S. Pat. No. 4,563,618, by P. E. Haferl, issued Jan. 7, 1986, entitled S-CORRECTED DEFLECTION CIRCUIT.
To provide side pincushion correction, the amplitude of horizontal deflection current i _H is modulated at a vertical rate by a side pincushion correction modulator circuit 30 that drives horizontal output circuit 70. Side pincushion correction circuit 30 includes a damper diode D3 with a grounded anode and a cathode coupled to the anode of damper diode D2, a retrace capacitor C _R3 coupled across diode D3, a modulator choke inductor L _m coupled to the junction of retrace capacitors C _R2 and C _R3 , and a modulator control circuit 60 coupled to choke L _m .
Modulator control circuit 60 modulates at a vertical rate the modulator current i _m in choke L _m , to concurrently modulate the retrace pulse voltage V _Rm developed across modulator retrace capacitor C _R3 . The modulation of retrace pulse voltage V _Rm produces a concurrent but opposite sense modulation of deflection retrace pulse voltage V _Rd across deflection retrace capacitor C _R2 . The vertical rate modulation of deflection retrace pulse voltage V _Rd produces the required vertical rate modulation of horizontal deflection current i _H that provides side pincushion correction.
The opposing sense modulation of retrace pulse voltages V _Rd and V _Rm produces an unmodulated retrace pulse voltage V _R at the collector of horizontal output transistor Q1. Retrace pulse voltage V _R is applied to the primary winding W _p of flyback transformer T1 for generating an unmodulated retrace pulse voltage V _RH at a terminal A of a secondary winding W _s . An unmodulated retrace pulse voltage is also generated in a high voltage winding W _HV for developing an ultor accelerating potential at a terminal U of a high voltage generating circuit 23.
FIG. 3 also illustrates a detailed embodiment of vertical deflection circuit 40 of FIG. 2. Vertical deflection circuit 40 includes a vertical deflection amplifier U1 coupled to vertical deflection winding L _V of FIG. 2 for generating a vertical deflection current i _V that deflects the electron beams in picture tube SP of FIG. 2 in the vertical direction. Vertical deflection winding L _V is coupled to a north-south and gullwing distortion correction circuit 34 for modulating vertical deflection current i _V in a manner that corrects both north-south pincushion distortion and gullwing distortion of the raster when scanning raster lines on square-planar picture tube SP of FIG. 2. A description of the operation of north-south pincushion and gullwing correction circuit 34 may be found in U.S. patent application Ser. No. 719,227, filed Apr. 2, 1985, by P. E. Haferl entitled NORTH-SOUTH PINCUSHION CORRECTED DEFLECTION CIRCUIT, now U.S. Pat. No. 4,668,897 and in U.S. patent application Ser. No. 733,661, filed May 10, 1985, by P. E. Haferl et al, entitled GULLWING DISTORTION CORRECTED DEFLECTION CIRCUITRY FOR A SQUARE-PLANAR PICTURE TUBE, both herein incorporated by reference.
Vertical deflection current i _V , after passing through correction circuit 34, flows through a coupling or vertical S-shaping capacitor C _V and a current sampling resistor R _s . Coupling capacitor C _V intergrates vertical deflection current i _V to develop across the capacitor between terminals 35 and 36 an AC parabola voltage, of almost ideal waveshape, that repeats at the vertical deflection rate. The voltage across capacitor C _V comprises the AC parabola voltage superimposed upon a DC level established by vertical deflection amplifier U1. The voltage V _sV developed across current sampling resistor R _s is illustrated in FIG. 5a and comprises an AC, S-shaped, sawtooth voltage repeating at the vertical deflection rate. The voltage V1 developed at terminal 35 is illustrated in FIG. 5b and equals the sum of the voltages developed across capacitor C _V and resistor R _s . Thus, the AC component of voltage V1 during the vertical trace interval t ₃ -t ₇ of FIG. 5b is a generally parabolically shaped voltage that is skewed downward by the relatively small sawtooth voltage component derived from sampling resistor R _s .
The voltages at terminals 35 and 36 are applied to vertical deflection amplifier U1 to provide DC and AC feeback, respectively, to the amplifier. The vertical rate voltages V1 and V _sV , the horizontal rate retrace pulse voltage V _RH and a voltage V _ds developed across winding W2 of transformer T2 are coupled to correction circuit 34 to provide deflection synchronization information and to provide waveform information that produces the required waveshaping and modulation of vertical deflection current i _v , as described in the aforementioned U.S. patent applications.
Vertical deflection circuit 40 may be considered as a low impedance voltage source 48 that generates parabola voltage V1 at output terminal 35 of the source.
Vertical parabola voltage V1 is nonlinearly waveshaped by a nonlinear network 50 and is then applied via a DC blocking capacitor C2 and a parabola amplitude adjusting potentiometer R _a to the noninverting input terminal of an amplifier U2 of side pincushion control circuit 60. Vertical sawtooth voltage V _sV is applied to the inverting input terminal of amplifier U2 via the wiper arm of a trapeze adjusting potentiometer R _t and a resistor 31. The DC level at the inverting input terminal is controlled by a width adjusting potentiometer 33 that couples a +25 V source to the inverting input terminal via a resistor 32 and the wiper arm of potentiometer 33. The output of amplifier U2 is coupled to an inverting driver stage U3 that applies a modulation voltage V _m to modulator choke inductor L _m .
Side pincushion control circuit 60 is operated in the switched mode at the horizontal rate. A horizontal sawtooth voltage generator 29, synchronized by horizontal retrace pulse voltage V _RH , applies a horizontal rate sawtooth voltage V _sH to the noninverting input terminal of amplifier U2 via a resistor R _g . Resistor R _g represents the effective source impedance of sawtooth voltage generator 29. The output of amplifier U2 is a pulse width modulated, horizontal rate voltage having a duty cycle that varies at a vertical rate. Modulation voltage V _m therefore is also a pulse width modulated, horizontal rate voltage having a duty cycle that varies at a vertical rate. This enables the drive provided by side pincushion modulator circuit 30 to be varied in a manner that corrects side pincushion distortion.
Side pincushion modulator circuit 30 operates in a manner similar to that described in U.S. patent application Ser. No. 651,301, filed Sept. 17, 1984, now U.S. Pat. No. 4,634,937 by P. E. Haferl, entitled EAST-WEST CORRECTION CIRCUIT. Other side pincushion correction circuits, such as switched mode diodc modulator circuits, may be used to drive horizontal output stage 70.
In accordance with an aspect of the invention, nonlinear waveshaping network 50 is interposed between terminal 35 and the noninverting input terminal of amplifier U2 of side pincushion control circuit 60. Nonlinear network 50 modifies the waveshape of parabola voltage V1 at terminal 35 to generate a modified parabola voltage V2 at a terminal 37, as illustrated by the solid-line waveform of voltage V2 in FIG. 5f. Shaped parabola voltage V2 is then applied to the noninverting input terminal of amplifier U2 via AC coupling capacitor C2 and potentiometer R _a . The additional waveshaping provided by nonlinear network 50 corrects the residual side pincushion error that would otherwise exist when scanning a raster on the phosphor screen of a square-planar picture tube.
Nonlinear waveshaping network 50 comprises a constant current source CS in series with a potentiometer R2 that is coupled to the wiper arm of trapeze adjusting potentiometer R _t . A diode D1, functioning as a unidirectional switch, is coupled between the wiper arm of potentiometer R2 and terminal 37, with the cathode of diode D1 being coupled to terminal 37.
In operation, constant current source CS generates an almost ideal constant current i ₀ , illustrated in FIG. 5d, that does not significantly change in value throughout the entire vertical deflection interval t ₃ -t ₈ . Diode D1 is reverse biased by voltage V2 during the interval t _b of FIG. 5. During this interval, all of current i ₀ that flows into end terminal 38 of potentiometer R2 flows out of the other end terminal 39, as illustrated in FIG. 5c by the current i ₃ during the interval t _b . Current i ₃ flows in that portion R2b of potentiometer R2 between intermediate wiper arm terminal 41 and end terminal 39 coupled to the wiper arm of potentiometer R _t . The solid-line waveform of FIG. 5c also illustrates the voltage V3 developed by current i ₃ in resistance R2b.
When diode D1 is nonconductive, during the interval t _b of FIG. 5, constant current source CS advantageously establishes an adjustable DC bias voltage level V _b at intermediate wiper arm terminal 41, as illustrated by the dotted-line waveform of FIG. 5c. Voltage V _b equals the constant voltage level V ₀ that is established for voltage V3 by constant current source CS, summed with the vertical sawtooth voltage developed at the wiper arm of trapeze adjusting potentiometer R _t . Illustratively, voltage level V ₀ is shown in FIG. 5c at a level established by the wiper arm of potentiometer R2 when the wiper arm is in a centered position.
When diode D1 is nonconductive, voltage V1 is divided by a voltage divider (R1, R _a , R _b , R _g ) coupled between terminal 35 and the noninverting input terminal of amplifier U2 for developing voltage V2 at terminal 37, which terminal is an intermediate point of the voltage divider. As illustrated in FIGS. 5b and 5f, voltages V1 and V2 exhibit substantially the same waveshape during the interval t _b .
During the second half of vertical trace, after the center of trace instant t ₅ , voltages V1 and V2 decrease in amplitude. Near time t ₆ , voltage V1 has decreased to a threshold voltage level V' _al and voltage V2 has decreased to a threshold voltage level V _a1 . The decreased voltage V2 at terminal 37 near time t ₆ or time t ₁ , enables diode D1 of nonlinear waveshaping circuit 50 to begin conducting, thereby coupling together terminals 37 and 41.
Diode D1 continues to conduct throughout the interval t _a of FIG. 5. During this interval, voltages V1 and V2 are below the threshold levels V' _a2 and V _a2 , respectively. At the end of the interval t _a , near time t ₉ or time t ₄ , voltages V1 and V2 have increased sufficiently to reestablish at terminal 41 the bias voltage level V _b of FIG. 5c that forces diode D1 to become nonconductive.
During the interval t _a , when diode D1 is conductive, a portion of constant current i _O of FIG. 5d, that flows in the upper resistance portion R2a of potentiometer R2, is shunted away from resistance R2b via the wiper arm of potentiometer R2 and diode D1. The shunt current i _c in diode D1 is illustrated in FIG. 5e during the interval t ₁ -t ₄ or t ₆ -t ₉ . Current i _c substracts from constant current i ₀ when diode D1 is conductive to reduce the amplitude of current i ₃ in resistance R2b by the amount of current shunted. As illustrated in FIG. 5c, current i ₃ , during the interval t _a , has the same waveshape as current i _c of FIG. 5e, but inverted in phase.
The waveshape of current i _c is determined in accordance with the waveshape of the parabolic component of voltage V1 that is applied to the voltage divider (R1, R2b) formed whendiode D1 is conductive. The amplitude of current i _c is related to the difference in value between the bias voltage level V _b and the parabolic voltage V1.
Correction current i _c , flowing into terminal 37, modifies the waveshape of voltage V2 during the interval t _a to correct the residual side pincushion error that would otherwise exist in raster display R of FIG. 1. Correction current i _c flows mainly in resistor R1 to provide an additional voltage drop between terminals 37 and 35 that produces a flatter slope to the sides of parabola voltage V2 during the conduction interval t _a of diode D1.
The solid-line waveform of FIG. 5f during the interval t _a illustrates voltage V2 with diode D1 conducting. The dashed-line waveform illustrates the waveshape that voltage V2 would have assumed had diode D1 remained nonconductive during the interval t _a . Comparing the solid-line waveform with the dashed-line waveform in FIG. 5f, one notes that the presence of nonlinear network 50 waveshapes parabola voltage V2 during the intervals t ₃ -t ₄ and t ₆ -t ₇ , when the top and bottom of the raster are being scanned.
The flattening of parabola voltage V2 occurs when the raster lines between lines L3 and L4 and between lines L6 and L7 of FIG. 1 are being scanned. This flattening produces less modulation of the amplitude of deflection current i _H when scanning the top and bottom raster lines. The result of the nonlinear waveshaping is the straightening of the bent vertical line segments of raster display R of FIG. 1 to correct the residual side pincushion error caused by the increased curvature of the faceplate of a square-planar picture tube in the top and bottom regions of the faceplate.
FIG. 4 illustrates a more detailed embodiment of a portion of the circuitry of FIG. 3 that includes nonlinear network 50. Items in FIGS. 3 and 4 similarly identified perform similar functions or represent similar quantities.
Inverting driver stage U3 comprises a switching transistor Q2 driven at its base by amplifier U2 and having its collector coupled to choke inductor L _m and its emitter coupled to ground. During those intervals within each horizontal deflection cycle that transistor Q2 is cutoff, modulator current i _m flows to the B+ supply via a flywheel diode D4. DC biasing for transistor Q2 is established by voltage dividing resistors 42 and 43. To provide stabilized operation of driver transistor Q2, negative feedback from the collector of the transistor to the noninverting input terminal of amplifier U2 is provided via a resistor 44.
Horizontal sawtooth generator 29 comprises an RC network including a resistor 45 coupled to flyback transformer terminal A and a capacitor 46 coupled to the noninverting input terminal of amplifier U2. DC biasing of the noninverting input terminal is provided by resistor R _b . Horizontal retrace pulse voltage V _RH is integrated by the RC network to develop the horizontal sawtooth voltage V _sH that produces the horizontal rate switching of transistor Q2. The duty cycle of the horizontal rate switching is modulated by means of the vertical rate modulation of the AC-zero level of voltage V _sH .
In FIG. 4, constant current source CS comprises a DC voltage source of relatively large magnitude, such as the 140 volt, B+ voltage source, coupled to a resistor R3 of relatively large value, such as 180 kilohm. The amplitude of constant current i ₀ is mainly determined by the value of the B+ voltage divided by the sum of the values of resistors R3 and R2. Current i ₀ establishes an adjustable bias voltage level V _b at the wiper arm of potentiometer R2 that maintains diode D1 nonconductive during the interval t _b of FIG. 5 when parabola voltage V1 is sufficiently large in amplitude to keep the diode reverse biased. During the remaining interval t _a , parabola voltage V1 is sufficiently small in amplitude to enable diode D1 to shunt some of current i ₀ away from resistance portion R2b of potentiometer R2 to provide the correction current i _c that waveshapes parabola voltage V2.
Advantageously, diode D1 is DC coupled to parabola voltage source 48 via resistor R1, with the cathode of diode D1 being coupled on the DC side (with respect to parabola voltage V1) of coupling capacitor C2. By means of the DC connection of diode D1 to parabola voltage source 48, the diode switching instants t ₄ and T ₆ may be adjusted by potentiometer R2 independently of the adjustment of east-west parabola amplitude potentiometer R _a . When potentiometer R _a is adjusted for the desired parabola amplitude, the AC-zero level of the parabola voltage applied to the noninverting input terminal of amplifier U2 also varies. This variation of the AC-zero level has little or no effect on the switching of diode D1.
For example, assume amplitude potentiometer R _a is adjusted to provide the proper amount of side pincushion correction when the central raster lines are being scanned between raster line L4 and raster line L6 of FIG. 1 during the interval t ₄ -t ₆ of FIG. 5. Potentiometer R2 may then be adjusted to establish a bias voltage level V _b that enables diode D1 to switch conductive states near times t ₄ and t ₆ . The switching of diode D1 near times t ₄ and t ₆ provides the required additional waveshaping of voltage V2 that corrects the residual side pincushion error in the top and bottom regions of raster display R.
The instants when diode D1 switches conductive states are controlled by the DC bias level V _b established by potentiometer R2 rather than by amplitude potentiometer R _a . The adjustment of potentiometer R2 has no significant effect on the previous amplitude adjustment provided by potentiometer R _a .
When the wiper arm of potentiometer R2 is moved towards end terminal 39, the conduction interval t _a of diode D1 decreases and the cutof interval t _b increases. The location of raster lines L4 and L6 where nonlinear waveshaping begins moves away from center raster line L5 towards top and bottom raster lines L3 and L7, respectively. The peak downward excursion of voltage V2, that occurs near the beginning of retrace near times t ₂ and t ₇ , also moves downward toward the dashed-line level that represents the peak downward excursion when diode D1 is cutoff for the entire vertical deflection interval t ₂ -t ₇ .
The amount of nonlinear waveshaping of parabola voltage V2 may be defined as the voltage difference between the dashed and solid-line waveforms V2 of FIG. 5f at times t ₃ and t ₇ , the start and end of vertical trace, respectively. This voltage difference relative to the dashed-line waveform V2 represents the amount of correction resulting on the raster display of FIG. 1.
When the wiper arm of potentiometer R2 is moved toward end terminal 38, the amount of nonlinear waveshaping increases until the conduction interval t _a of diode D1 equals the nonconduction interval t _b . As the wiper arm of potentiometer R2 is moved further toward end terminal 38, the amount of waveshaping begins to decrease and reaches zero when bias voltage level V _b is set at a sufficiently high level to enable diode D1 to conduct for the entire vertical deflection interval.
The amplitude of current i _c changes when potentiometer R2 is adjusted. However, the peak amplitude that parabola voltage V2 attains remains substantially the same at all levels of adjustment because correction current i _c of FIGS. 3 and 4 flows mainly in resistor R1 and does not add any significant charge to AC coupling capacitor C2. No significant portion of current i _c flows in capacitor C2 because of the long time constant associated with capacitor C2 and resistors R _a , R _b , R _g . Current i _c causes a very small increase of the average DC voltage at terminal 37, not illustrated in waveform FIG. 5. This increase amounts to approximately 75 millivolt, which is 1/4 the voltage difference between the dashed and solid-line waveforms of voltage V2 in FIG. 5f, at times t ₃ and t ₇ .
When diode D1 becomes conductive, parabola voltage source 48 becomes DC coupled to current source CS. At the same time an additional load impedance becomes coupled to current source CS derived from the voltage divider (R1, R _a , R _b , R _g ). Because of the DC connection provided by diode D1 between the wiper arm of potentiometer R2 and parabola voltage source 48, the additional voltage that is coupled in-circuit with current source CS during the interval t _a of FIG. 5 is relatively small. The additional voltage, ΔV3, equals the voltage difference between the constant voltage level V ₀ of FIG. 5c and the voltage V3 developed across resistance R2b.
The peak-to-peak amplitude of voltage ΔV3 is relatively small, approximately one volt peak-to-peak for the values given in FIG. 4. Because the peak-to-peak amplitude ΔV3 is much smaller than the B+ voltage of constant current source CS, the shunt current i _c that source CS supplies when diode D1 is conductive is also small relative to current i ₀ and has substantially no effect on the amplitude of the constant current. For the values given in FIG. 4, the amplitude of current i ₀ changes less than one percent during the conduction interval t _a shown in FIG. 5.
End terminal 39 of potentiometer R2 may be advantageously coupled to trapeze adjusting potentiometer R _t rather than to ground. This connection enables nonlinear network 50 to provide a common-mode rejection of the sawtooth voltage component of parabola voltage V1. Thus, diode D1 nonlinearly waveshapes only the parabolic component of voltage V1 and not the sawtooth component. The common-mode rejection of the waveshaping of the sawtooth component of voltage V1 may be noted from the waveforms of FIGS. 5c and 5e, which are symmetrical about the center of trace instant t ₅ .
Nonlinear waveshaping network 50 advantageously produces gradual changes in the slope of parabola voltage V2 at the switching instants of diode D1 that smoothly straightens the bent segments of the vertical lines of raster display R in FIG. 1, without introducing wiggly line excursions of the vertical line pattern near raster lines L4 and L6.
Nonlinear network 50 operates as a current divider to divide current i ₀ into current i ₃ and current i _c during conduction of diode D1. Thus, the change in the forward voltage drop of diode D1, produced by variations in ambient temperature, has little influence on the waveshaping of the parabola voltage.


NORDMENDE PRESTIGE 72 IMC  CHASSIS F17 IMC (THOMSON ICC5 / ICC5341)   Television receiver comprising a teletext videeotext decoding circuit and a page number memory:

A television receiver which is suitable for displaying teletext pages comprises a control system including a microcomputer. The microcomputer is coupled to a volatile memory which comprises a plurality of page number registers. A page number can be temporarily stored in each of these registers. With the aid of a keyboard the user makes known which page numbers he wants to have stored in the different registers and the stored page numbers represent a first series of pages. One single read key (RCL) is provided for the display of such a page. Each time this key is depressed once, a different page belonging to the first series appears on the picture screen. The sequence in which the pages appear is the same as the sequence in which the user has keyed-in the relevant page numbers. This sequence can be interrupted by the occurrence of a preselected operating instruction in response to which a number of teletext pages not associated with said first series can be displayed on the picture screen. Thereafter, the display of the teletext pages of the first series can be continued.


1. A television receiver comprising:
a control system for generating in response to external manipulations control instructions including teletext page numbers of teletext pages to be displayed on said television receiver;
a teletext-decoder circuit having a page number input for receiving from said control system page numbers of teletext pages to be displayed and having a picture output applying the picture signal of the teletext page to be displayed;
a picture screen coupled to display the picture signal from the picture signal output of the teletext decoder circuit, said picture screen displaying a teletext page which is identified by an associated page number;
page number storage means for storing a plurality of page number; and
a programmable control circuit coupled to the page number storage means and to the control system for receiving the control instructions, and to said page number input of the teletext decoder circuit to apply teletext page numbers thereto, the control circuit being programmed for carrying out the steps of:
storing in the page number storage means a first series of preselected teletext page numbers selected by a user in the order in which the corresponding teletext pages are desired for display;
successively applying the teletext page numbers of said first series to the teletext-decoder in response to successive occurrences of a selected first control instruction for successively displaying the teletext pages corresponding to the teletext page numbers successively applied to the teletext-decoder;
interrupting the successive application of teletext page numbers of said first series to the teletext-decoder in response to the occurrence of a selected further control instruction;
storing intermediate teletext page numbers in the order in which the corresponding teletext pages are desired for display;
successively applying the intermediate teletext page number to the teletext-decoder in response to successive further occurrences of the selected control instruction; and
continuing the successive application of the remainder teletext page numbers of said first series to the teletext decoder after all the intermediate teletext page numbers have been applied thereto.
2. A television receiver as claimed in claim 1, in which the storage means comprises N registers, each register storing a teletext page number, whereby registers storing teletext page numbers selected by the user are defined to be occupied registers and whereby the remaining registers are defined to be non-occupied registers, the control circuit is further programmed for:
making a register non-occupied in response to each occurrence of the selected first control instruction,
generating a sequence of further page numbers S+1, S+2, S+3, . . . in which S represents the last teletext page number of the first sequence; and
storing the teletext page numbers S+1, S+2, . . . S+(N-M) in the respective non-occupied registers, where M is the actual number of occupied register.

Description:

BACKGROUND OF THE INVENTION
(1) Field of the Invention
The invention relates to a television receiver of a type comprising a teletext decoding circuit and a storage means (page number memory) in which the page numbers associated with a plurality of teletext pages can be stored.
(2) Description of the Prior Art
Such a television receiver has several operating modes, more specifically a program-mode and a teletext mode. In the program mode the video signal transmitted by a transmitter is applied through a video channel to a picture screen for displaying the television program. In the teletext mode said video signal is applied through a teletext decoder circuit to the picture screen for displaying the teletext associated with the program. The television itself can be partly or wholly suppressed.
The operating mode is determined by the viewer, (user). To enable the viewer to inform the receiver about his wishes, the receiver includes a control system comprising external components which can be manipulated by the viewer. More specifically, this control system has a control panel with control keys, each having a specific control function. This function is indicated by a sign applied on, over or under the relevant control key. Thus, there are for example a volume control key, a luminance key, a teletext key, a mixed-mode key, a program key and a plurality fo figure keys etc. These last-mentioned keys are characterized in that the associated signs are numerals. If the receiver is in the program mode, the viewer can inform the receiver with the aid of the figure keys which program or channel is wanted. After the teletext or the mixed-mode key has been operated the set is in the teletext mode with a partly or wholly suppressed television program and the viewer keys-in the page number of the desired teletext page, using the same above mentioned keys.
Operation (or manupulating) of one or more of the keys on the control panel generally results in the generation of a control instruction by the control system. Such control instruction may include the page numbers of a desired teletext page. All these instructions are received by a control circuit which interprets these instructions and gives instructions to the different circuits to be controlled, including the teletext decoder circuit. More specifically, the teletext decoder receives a page number in response to which the required teletext page is captured, stored in a page memory and thereafther displayed on the picture screen by a character generator.
As is known a teletext index page is first displayed on the picture screen after a teletext key or the mixed-mode key has been operated. By selecting a desired page from this index and keying-in the associated page number with the aid of the numeric keys this teletext page is captured by the teletext decoder circuit and displayed thereafter.
If thereafter the display is required of a page associated with a different subject, the index page must usually again be consulted to find the page number of the relevant page. It should be borne in mind that each time the page number of a desired page is keyed-in it takes a certain period of time before the relevant page is displayed on the screen. It is therefore justified to state that such a television receiver is far from user-friendly. To improve this, it is proposed on page 527 of reference 1 to provide the receiver with a storage means which is coupled to the control circuit and in which a plurality of page numbers can be stored. This storage means will be referred to as the page number memory hereinafter.
By operating the control circuit, the user can store a first series of page numbers in a sequence in which he wants them to be displayed, in the page number memory. To enable the display in the desired sequence of these preselected teletext pages, the control panel has a key which will be called the read key hereinafter. Each time this key is operated, the control circuit receives an accurately defined operating instruction and a subsequent page number of the first series is read from the page number memory and applied to the teletext decoder circuit. In this way the teletext pages of the first series are sequentially displayed on the picture screen.
Thus, for this television receiver it is possible to select all those pages from an index page the viewer is interested in. The page corresponding numbers can be stored in the page number memory in the sequence in which the display of these pages is desired. Thereafter, they can be caused to appear in the desired sequence, one after the other, by pushing the read key once for every page.
It should be noted, that, after the read key has been operated, it also takes a certain time before the new page appears on the picture screen. However, by constructing the teletext decoder circuit in the way described in reference 1 or 2, a new page can be displayed immediately after pushing the read key. It is possible to couple to the teletext decoder circuit detailed in said reference a page memory having a capacity that no less than four pages can be stored therein simultaneously. All this is then organised such that this page memory contains the page actually displayed on the picture screen and also the three pages of the first series.
It should also be noted that the page number memory may be constituted by a non-volatile memory, so that the same series of teletext pages are permanently available. It is alternatively possible to use a volatile memory for this purpose, optionally in combination with a non-volatile page number memory.
SUMMARY OF THE INVENTION
The invention has for its object to further improve the convenience of use of a television receiver of the type defined in the foregoing, having a volatile page number memory. According to the invention, the control circuit performs the following additional steps:
interrupting the sequential display of the teletext pages of the series for the benefit of the sequential display of a number of further teletext pages which do not belong to the first series, whose associated page numbers are generated by means of the control system; and,
continuing the display of the teletext pages of the first series in response to a further operation of the read key, after all the further teletext pages have been displayed on the screen.
The properties of the television receiver thus obtained will no doubt be appreciated when the following is considered. The contents of the first series of pages whose page numbers are stored in the page number memory are not known previously. When those pages are displayed, it may happen that a given page is itself an index page (denoted sub-index page in the sequel) or that it contains a reference to pages in which additional information on the same subject is contained. The viewer can now select from such sub-index page a further series of pages, generate the associated page numbers with the aid of the control system and insert the display of these pages between the sub-index page and the subsequent page of the first series. If the control circuit were not implemented in such a way that the above-defined steps can be performed, then these further pages could not be displayed until all the pages of this first series have been displayed on the picture screen.
REFERENCES
1. Enhanced UK teletext moves towards still pictures; J. P.Chambers: IEEE Transactions on Consumer Electronics, Vol. Ce-26, Aug. 1980, pages 527-532.
2. Computer controlled teletext; J. R.Kinghorn; Electronic Components and Applications, Vol. 6, No. 1, 1984, pages 15-29.
3. Bipolar IC's for video equipment; Philips Data Handbook Integrated Circuits Part 2, Jan. 1983.
4. IC's for digital systems in radio, audio and video equipment; Philips Data Handbook Integrated Circuits, Part 3, Sept. 1982.
BRIEF DESCRIPTION OF THE FIGURES
FIG. 1 shows the general structure of a television receiver comprising a teletext decoder circuit and
FIGS. 2 to 10 shows diagrams to explain the operation of this television receiver.
DESCRIPTION OF THE PREFERRED EMBODIMENTS
General Structures of the Television Receiver
FIG. 1 shows schematically the general structure of a colour television receiver. It has an antenna input 1 connected to an antenna 2, which receives a video signal modulated on a high-frequency carrier and processed in a plurality of processing circuits. More specifically, the video signal is applied to a tuning circuit 3 (tuner or channel selector) This tuning circuit receives a band selection voltage V _B to enable tuning of the receiver to a frequency within one of the frequency bands VHF1, VHF2, UHF etc. In addition, the tuning circuit receives a tuning voltage V _T for tuning the receiver to the desired frequency within the selected frequency band.
This tuning circuit 3 produces an oscillator signal having frequency f _OSC and also an intermediate-frequency signal IF. The last-mentioned signal is applied to an intermediate-frequency amplifying and demodulating circuit 4 which produces a base band composite video signal CVBS. For this circuit 4 reference could be made to Philips IC TDA 2540, described in Reference 3.
The signal CVBS thus obtained is further applied to a colour decoder circuit 5, which produces the three primary colour signals R, G and B, which are applied by an amplifier circuit 6 to a picture tube 7 for displaying television programs on the picture screen 8. In the colour decoding circuit 5 colour saturation, contrast and luminance are influenced by means of control signals. In addition, the colour decoder circuit receives an additional set of primary colour signals R', G' and B', and also a switching signal BLK (Blanking) with which the primary colour signals R, G and B can be suppressed. For this circuit 5 a Philips integrated circuit of the group TDA 356 X, which is also described in Reference 3, can be used.
The video signal CVBS is also applied to a teletext decoder circuit 9, which comprises a video input processor 9 (1) receiving the video signal CVBS, separates the teletext data therefrom and applies the latter through a data line TTD to a circuit 9 (2) which will be called the computer controlled teletext decoder (abbreviated to CCT-decoder). This CCT-decoder also receives a clock signal from the video input processor 9 (1) through a clock line TTC. The decoder is further coupled to a memory 9 (3) in which one or more teletext pages can be stored and which is therefore called the page memory. This CCT-decoder produces the three previously-mentioned primary signals R', G', B' and also the switching signal BLK. The video input processor 9 (1) may be constituted by the Philips IC SAA 5230, the CCT-decoder 9 (2) by the Philips IC SAA 5240 and the page memory by a 1K8 to 8K8 RAM. For an detailed description of the structure and operation of a teletext decoder circuit reference is made, for the sake of brevity, to Reference 2.
The CCT-decoder 9 (2) is further connected to a bus system 10, to which also a control circuit 11, in the form of a microcomputer, an interface circuit 12, a non-volatile storage means 13 and a volatile storage means 14 are connected. The interface circuit 12 produces the band selection voltage V _B , the tuning voltage V _T and also the control signals for controlling the analog functions contrast, luminance, colour saturation. It receives an oscillator signal having frequency f' _OSC which by means of a frequency divider 15 whose dividing factor is 256, is derived from the oscillator signal having frequency f _OSC supplied by the tuning circuit 3. Tuning circuit 3, frequency divider 15 and interface circuit 12 together form a frequency synthesizing circuit. The Philips IC SAB 3035, which is known by the name CITAC (Computer Interface for Tuning and Analog Control) and is described in Reference 4 may be used as the interface circuit.
The storage means is, for example, used to store the tuning data of a plurality of preselected transmitters, or programs. If under the control of the microcomputer 11 such a tuning datum is applied to the interface circuit 12, then it produces a given band selection voltage V _B and given tuning voltage V _T , in response to which the receiver is tuned to the desired transmitter.
For the microcomputer the microcomputer of the Philips MAB 84XX family can be used. Although it may be assumed that the structure of a microcomputer is generally known, it should here be briefly remarked that it comprises a program memory (usually a ROM) in which the manufacturer stores a plurality of control programs, and also a working memory.
The volatile storage means 14 is used as a page number memory. It comprises a number of N page number-registers having the register numbers R(1), R(2), . . . R(p), . . . R(N), respectively, wherein N=10. This volatile storage means 14 which is shown in the drawing as a separate memory, is preferably constituted by a portion of the working memory of the microcomputer 11.
To operate this television receiver a control system is provided which in the embodiment shown is in the form of a remote control system and is constituted by a hand set 16 and a local receiver 17. This receiver 17 has an output which is connected to an input (usually the "interrupt"-input) of the microcomputer. The receiver may be the Philips IC TDB 2033 described in Reference 4 and then has for its object to receive infrared signals transmitted by the hand set 16.
The handset 16 comprises a control panel 16 (1) which, in addition to a number of numeric keys indicated by the numerals 0 to 9, has the following keys; a saturation key SAT, a brightness key BRI, a volume control key VOL, a teletext key TXT, a mixed-mode key MIX, a program key PR, a storage key ENT and a read key RCL. The keys of this control panel are coupled to a transmitter circuit 16 (2) for which the Philips IC SAA 3004 which is described in detail in Reference 4, may, for example, be used. If a key is depressed, then the transmitter circuit 16 (2) generates a code which is specific for that key and which transmitted on a infrared carrier to the local receiver 17, is demodulated there and thereafter applied to the microcomputer 11. Thus, the microcomputer receives control instructions and through the bus system 10 energizes one of the circuits coupled thereto. It should be noted that a control instruction may be single, that is to say that it is complete after only one single key has been operated. It may alternatively be a multiple instruction, that is to say that it is not complete until two or more keys have been operated. This situation occurs, for example, when the receiver is in the teletext mode. In that case operating the numeric keys does not produce a complete operating instruction until, for example, three numeric keys have been depressed. Such an operating instruction, consisting of for example three figures is called a page number.
Operation of the Television Receiver
The operation of the television receiver shown in FIG. 1 is wholly determined by the various control programs stored in the internal program memory of the microcomputer. A control program which is always stored in such a receiver, is the switch-on program SWON which is symbolically shown in FIG. 2. Although this program is generally known, it should be noted for the sake of completeness that this program immediately applies a predetermined tuning datum present in the strorage means 13 to the circuit 12 after the receiver has been switched on, in response to which the receiver is tuned to the relevant transmitter. This may either be a predetermined transmitter, or it may be the transmitter the receiver was tuned to at the moment it was switched off.
After the switch-on program has been performed, the initiation program INT which is symbolically indicated in FIG. 3 is started. During this program the content of the first page number-register R (1) is made equal to a fixed page number; for example 100 (one hundred). This page number 100 is also applied to the CCT-decoder 9 (2) which decodes this page, stores it in the page memory 9 and displays it on the picture screen 8 after the teletext key TXT or the mixed-mode key MIX has been operated. To determine whether a key has been depressed, the so-called background program BGR, which is shown symbolically in FIG. 4 is started.
After the teletext key or the mixed-mode key has been operated a teletext program is started which is given the reference numeral 50 in FIG. 5. This program includes a step 51 in which the value 2 is assigned to a vector p. Thereafter, in a step 52 it is checked whether a page number is received. If so, then a storage program 53 is passed through or, if negative, a read program 54. After such a program has ended, it is checked in step 53 whether a new page number is received.
The storage program 53 includes a step 531 in which the page number received is stored in the register R(p). Thereafter, in a step 532 it is checked whether the storage key (enter key) ENT has been operated. If not, then this storage program has ended and the content of the register R(p) can be overwritten by a different page number. If the enter key has been operated, the vector p is first incremented by one in a step 533. Acting thus, the registers R(1) to R(N) can be loaded with page numbers of a first series of teletext pages. These pages can now be sequentially displayed on the picture screen by means of the read program and by operating the read key RCL. More specifically, the read program 54 has a step 541 in which it is checked whether the read key has been operated. If no, the read program has ended, if yes the contents of the registers are shifted in a step 542 to registers of the next lower number, that is to say the content of register R(2) is shifted to R(1), the content of register R(3) is shifted to R(2) etc. Thereafter the vector p is decremented by one unit in a step 543. So now vector p indicates the empty register having the lowest number. If now a new page number were received and the storage key ENT were depressed, then this new page number would be stored in the register R(p-1). Before the associated teletext page can be displayed, the read key RCL must then first be depressed p-2 times. Prestoring the page numbers of the desired teletext pages and the fact that only one key (namely the read key) must be operated to effect the display of these pages, makes this television receiver very user-friendly. However, the fact that a new page number cannot result in the immediate display of the associated page when not all the page number registers are empty (so that the vector p=1) is experienced as annoying. To increase the convenience and ease of use of this television receiver the storage program is provided, as is shown in FIG. 6, with an auxiliary read program 534 consisting of one step 5341 in which it is checked if after reception of a page number the read key RCL has been operated without the storage key ENT having been depressed. If this is indeed the case, then in a step 5342 the content of register R(p) is transferred to register R(1) and thus the relevant page is pulled-in and displayed as soon as the opportunity arises.
With the program shown in FIG. 6 a subsequent, new page number can be applied after the preceding new page number has been transferred from register R(p) to register R(1). A storage and read program with which the successive display of the teletext pages of the first series can be interrupted to enable the storage of a second series of pages in a sequence the user wants them to be displayed and the sequential display of the pages of this second series in response to the pushing of the read key RCL, followed by the display of the original (first) series of pages, is illustrated in FIG. 7. This program differs from the program shown in FIG. 5 in that now the read program 54, has, instead of the program step 543 a program step 543' in which the vector p is made equal to two after each operation of the read key RCL and the register contents have been shifted one register in step 542, this vector becomes equal to two.
The storage program 53 further comprises a step 535 in which the contents of the register R(p) to R(N-1) are shifted to registers of a next higher number.
If, after the read key RCL has been depressed and the read program has been performed a new page number is applied to the microcomputer, then in step 535 the content of the second register R(2) is shifted to the third register R(3), the content of the third register R(3) is shifted to the fourth register R(4) etc. Thereafter the new page number is stored in the second register R(2) in step 531. If thereafter the storage key ENT is operated, then the vector becomes equal to 3. A new page number is then stored in the third register R(3), whilst the original content of the third, fourth, fifth, sixth etc. registers are shifted to the fourth, fifth, sixth, seventh etc. registers, respectively. So acting thus a second series of Q-1 page numbers can be stored in the registers R(2) to R(Q) each time the read key RCL is operated, the page numbers originally contained in these registers being shifted to registers of Q-1 higher numbers. When the read key is now operated, these Q-1 page numbers of the second series are first applied to the teletext decoding circuit and only thereafter the display of the original (first) series is continued.
The program shown in FIG. 6, which provides the possibility of storing a new page number directly in the first register, and thus to display the associated page on the display screen at the first opportunity can advantageously be combined with the program shown in FIG. 7. For the sake of completeness, FIG. 8 shows a program comprising both the program steps shown in FIG. 6 and those shown in FIG. 7. To have this program proceed adequately, the steps 5343, 5344 are additionally present which, in view of the foregoing need no further explanation.
The teletext programs shown in FIGS. 5, 6, 7 and 8 are structured such that storing a series of new page numbers requires the operation of the storage key ENT after a new page number has been applied. It is however, alternatively possible to structure the teletext program such that the storage key must be operated before a new page number is applied. Such a teletext program is shown for the sake of completeness in FIG. 9. It comprises a step 51' in which the vector p is given the value one. To enable, a decision which the program shown in FIG. 6, also now the immediate storage of any random page number in the register R (1), this program has a step 60 in which it is checked whether a page number is applied. If yes, this page number is immediately stored in the first register R(1) in step 61, whereafter early display of the relevant page can follow. If no page number is coming forward, then it is checked in step 62 whether the storage key ENT has been operated. If not, the read program 54 is effected or else the storage program 63.
The read program again includes the steps 541 and 542. It now also has a step 543" in which the vector p is again made equal to one. The storage program 63 has a step 631 in which the actual value of the vector is incremented by one. Thereafter, in a step 632, the arrival of a new page number is awaited, whereafter in step 633 the contents of the registers R(p) to R(N-1), respectively are shifted to the registers R(p+1) to R(N). Finally, in step 634 the latest page number is stored in the register R(p).
The teletext programs mentioned in the following have the property that those page number registers R(.) in which no page numbers selected by the user are stored remain empty. This implies that when the user repeatedly depresses the read key he may be confronted by the situation that all registers are empty. To prevent this situation from occurring, these registers may be filled automatically with page numbers for which there are two adequate possibilities. Firstly, they might be the page numbers of preferred pages which had previously been stored already by the user in a non-volatile memory, for example, the memory 13 in FIG. 1. Secondly, they might be the page numbers S+1, S+2, . . . etc., S being the last page number of the first series. To accomplish that the page number registers are filled thus with page numbers, the teletext program might be of a structure as shown in FIG. 10. This program corresponds to a considerable extent to the program shown in FIG. 8, but differs therefrom in several respects. Step 52 is followed by a step 70 in which a page number and also a user flag flg.(-) are stored in the registers R(2) to R(N) (see FIG. 1). More specifically, the page number in the register R(i) then becomes one higher than the page number in the preceding register R(i-1), so that at the end of this step 70 the page number registers R(1) to R(n) contain the respective page numbers 100, 101, 102, 103, . . . 100+(N-1). The associated user flags are all zero.
If at a given value of the vector p a new pagenumber, for example S, is applied, then in step 71 it is first checked whether the user flag (flg(p) in the register R(p) is equal to one. If not this implies that the register R(p) is not filled with a page number explicitly stipulated by the user. In step 721 this newly applied page number S is then stored in this register R(p). At the same time the associated user flag flg (p) becomes 1 to indicate that this page number has been selected by the user. Thereafter a step 722 is performed which corresponds to step 70. More specifically, the page number S+1 is then stored in the register R(p+1), the page number S+2 in the register R(p+2) whilst the associated user flags flg(p+11), flg(p+2), etc. all become equal to zero, signifying that these page numbers were not explicitly stated by the user.
If upon performing of step 71 it appears that the user flag flg(p) in the register R(p) is indeed equal to one, then in step 535 the contents of the registers R(p) to R(N-1) are shifted to the respective register R(p+1) to R(N), so that in step 531' the latest page number can be stored in the register R(p), the associated user flag flg(p) then simultaneously becoming equal to one.
This teletext program further differs from the program shown in FIG. 8 in that the auxiliary read program 534 has a further step 5345 and the read program 54 has a further step 544 identical thereto. In these steps, each time after the last page number register R(n) has become empty because of the shift operation effected in the preceding step, a page number which is one higher than the page number stored in the last-but-one register R(N-1) is stored in this register R(N). At the same time the associated user flag flg (N) becomes equal to zero.
It should be noted that in the embodiment shown in FIG. 1 the control circuit is predominantly constituted by the microcomputer 11. In practice it has however been found advantageous to arrange between the microcomputer 11 and the CCT-decoder 9(2) a second micro computer which only controls this CCT-decoder 9(2) and for that purpose comprises one of the teletext programs described in the foregoing.

 THOMSON ICC5 Color television standard identification circuit:

A PAL-NTSC color television standard identification circuit, comprising a first demodulation circuit (7) for a reference component and a second demodulation circuit (11) for a possible color identification component of a color synchronizing signal, can perform a reliable identification by means of a digital decoding circuit (81) for the output signals of the demodulation circuits if the second demodulation circuit (11) is adapted (41, 45, 49) to demodulate along an axis slightly differing from the axis of the color identification component (FIG. 1).



1. A color television standard identification circuit for distinguishing at least a PAL and an NTSC color television signal, said identification circuit comprising a first demodulation circuit for demodulating a reference component (R) of a color synchronizing signal occurring in both PAL and NTSC, a second demodulation circuit for demodulating a color identification component of the color synchronizing signal occurring only in PAL, and a decoding circuit having an input coupled to respective outputs of said first and second demodulation circuits for determining whether the color synchronizing signal is a PAL or an NTSC color synchronizing signal, wherein said identification circuit further comprises a sign determination circuit coupled between the outputs of said first and second demodulation circuits and the input of said decoding circuit, said sign determination circuit comprising a comparison circuit having a comparison level, at which the level of an output signal of said comparison circuit changes, which is substantially equal to a reference level of said first and second demodulation circuits, and a sampling circuit having a input coupled to an output of said comparison circuit, an input of said sign determination circuit being coupled to an input of said comparison circuit and an output of said sign determination circuit being coupled to an output of said sampling circuit, wherein said second demodulation circuit is arranged to demodulate the color synchronizing signal at an axis slightly differing from the axis of the color identification component, whereby said sign determination circuit may accurately determine the correct sign of the output signal from said second demodulation circuit during demodulation of an NTSC color synchronizing signal by said second demodulation circuit. . 2. A color television standard identification circuit as claimed in claim 1, wherein said first demodulation circuit comprises a first synchronous demodulator having an input and an output coupled, respectively, to an input and the output of said first demodulation circuit; and said second demodulation circuit comprises a second synchronous demodulator having an input coupled to an input of said second demodulation circuit, and an adder circuit having a first input coupled to the output of said first synchronous demodulator and a second input coupled to an output of said second synchronous demodulator, an output of said adder circuit being coupled to the output of said second demodulation circuit, and wherein said identification circuit further comprises an oscillator for supplying reference signals to reference signal inputs of said first and second synchronous demodulators, said oscillator having a control input coupled to the output of said second synchronous demodulator thereby forming a phase-locked loop for controlling the phase of said oscillator. 3. A color television standard identification circuit as claimed in claim 1 or 2, wherein a change-over switch is coupled between the input of said sign determination circuit and the outputs of said first and second demodulation circuits, respectively, said change-over switch having a switching signal input coupled to an output of said decoding circuit.

Description:

The invention relates to a color television standard identification circuit for distinguishing at least a PAL and an NTSC color television signal, said circuit comprising a first demodulation circuit for demodulating a reference component of a color synchronizing signal occurring in both PAL and NTSC and a second demodulation circuit for demodulating a color identification component of the color synchronizing signal occurring only in PAL, and a decoding circuit for determining by means of output signals of the first and the second demodulation circuit whether the color synchronizing signal is a PAL or an NTSC color synchronizing signal.
A color television standard identification circuit of the type described above is known from IEEE Transactions on Consumer Electronics, Vol. CE 31, No. 3, August 1985, pp. 147-155. The greater part of this circuit is incorporated in an integrated circuit to which two capacitors performing a memory function in the decoding circuit must be connected.
It is an object of the invention to obviate as much as possible the use of capacitors to be connected externally.
According to the invention, a color television standard identification circuit of the type described in the opening paragraph is therefore characterized in that a sign determination circuit is arranged between an output of the demodulation circuits and an input of the decoding circuit, said sign determination circuit comprising a comparison circuit whose sign reversal level is substantially equal to the rest level of the demodulation circuits and further comprising a sampling circuit, the second demodulation circuit being adapted to demodulate the color synchronizing signal at an axis slightly differing from the axis of the color identification component in such a way that the sign determination circuit cannot determine an incorrect sign during demodulation of an NTSC color synchronizing signal.
It is to be noted that the use of a sign determination circuit with a comparison circuit and a sampling circuit for obtaining a decoding circuit no longer requiring capacitors is known from French Patent Application FR-A 2,575,353 for identifying a color difference signal associated with a given line period in a SECAM receiver.
It has been found that it is insufficient to incorporate a sign determination circuit, for example, after the demodulation circuits of a color television standard identification circuit.
To obtain a reliable standard identification, it is necessary that the second demodulation circuit supplies a signal from which the sign determination circuit can obtain such a signal that the decoding circuit can make a distinction between noise and the presence of an NTSC color synchronizing signal.
If the second demodulation circuit had a demodulation axis which would completely coincide with the phase of the PAL color identification component, it would supply an output signal which would be equal to the rest level of the second demodulation circuit in the case of demodulation of an NTSC color synchronizing signal. With a slight internal shift of its comparison level, its own noise could then cause the sign determination circuit to supply a signal which would not correspond to the sign desired for the rest level of the second demodulation circuit. This is prevented by slightly modifying the demodulation axis of the second demodulation circuit.
The invention will now be described in greater detail, by way of example, with reference to the accompanying drawing in which
FIG. 1 is a block diagram of a color television standard identification circuit according to the invention,
FIG. 2 is a phasor diagram of the demodulation of the components of a PAL color synchronizing signal by means of a circuit according to FIG. 1, and
FIG. 3 is a phasor diagram of the demodulation of the components of an NTSC color synchronizing signal by means of a circuit according to FIG. 1.
In FIG. 1 a chrominance signal is applied to an input 1, from which signal a gating circuit 3 selects the color synchronizing signal and passes it on to an input 5 of a first demodulation circuit 7 and to an input 9 of a second demodulation circuit 11.
The first demodulation circuit 7 is a first synchronous demodulator which receives a reference signal at a reference signal input 13 from an output 15 of a 90° phase-shifting network 17, which reference signal has a phase which is 90° shifted with respect to the phase of a reference signal occurring at an input 19 thereof and originating from an output 21 of an oscillator 23.
The input 9 of the second demodulation circuit 11 is also an input of a second synchronous demodulator 25, a reference signal input 27 of which is connected to the output 21 of the oscillator 23 and an output 29 of which applies, via a low-pass filter 31, a control signal to a control signal input 33 of the oscillator 23.
The oscillator 23, the second synchronous demodulator 25 and the low-pass filter 31 constitute a phase-locked loop controlling the phase of the reference signal at the reference signal input 27 of the second synchronous demodulator 25 in such a way that it differs ninety degrees from that of the reference component of the color synchronizing signal. As a result, the demodulated color identification component of the color synchronizing signal occurs at the output 29 of the second synchronous demodulator 25 in the case of synchronous demodulation of a PAL color synchronizing signal, whilst the phase-locked loop will control said output 29 substantially at its rest level in the case of synchronous demodulation of an NTSC color synchronizing signal.
The demodulation axis of the second synchronous demodulator 25 is the ninety-degree axis in FIGS. 2 and 3, and the demodulation axis of the first synchronous demodulator 7 is the zero axis. The reference component of the color synchronizing signal is denoted by R in the two Figures and has a phase of one hundred and eighty degrees. The PAL color synchronizing signal is denoted by B and B' in FIG. 2, dependent on the line period in which it occurs.
In FIG. 1 an output 35 of the first synchronous demodulator 7 applies the demodulated reference component R of the color synchronizing signal, which has a negative polarity, to an input 37 of a change-over switch 39 and via an attenuator 41 to an input 43 of an adder circuit 45, an output 47 of which is also the output of the second demodulation circuit 11.
The output 29 of the second synchronous demodulator 25 applies the demodulated color identification component via a further attenuator 49 to a further input 51 of the adder circuit 45. The output 47 of the second demodulation circuit 11 now applies a demodulated color synchronizing signal to a further input 53 of the change-over switch 39, which signal is demodulated in accordance with an axis which is denoted by D in FIGS. 2 and 3 and which differs slightly from the ninety-degree axis. This difference is determined by the ratio of the attenuations of the attenuators 41 and 49.
FIGS. 2 and 3 show that in the case of PAL a slightly asymmetrical demodulation of the color identification component is effected with an amplitude A in the one line period and an amplitude A' in the next period, whilst in the case of NTSC a small negative amplitude C is demodulated by the second demodulation circuit 11.
In FIG. 1 an output 55 of the change-over switch 39 is connected to an input 57 of a sign determination circuit 59 via a low-pass filter 56 having an integration time of approximately half a microsecond. The input 57 is also an input of a comparison circuit 61, a reference level input 63 of which receives the rest level of the first and the second demodulation circuits 7, 11, which is symbolically indicated by a connection between this input 63 and a rest level output 65, 67 of the first and the second synchronous demodulator 7, 25, respectively.
An output 69 of the comparison circuit 61 is connected to a D input 71 of a D flip-flop 73 operating as a sampling circuit, a clock signal input 75 of which receives a pulse each time at the end of the occurrence of a color synchronizing signal. As a result, a logic value of one is obtained at an output 77 of the D flip-flop 73, which output is also the output of the sign determination circuit 59, if the signal at the input 57 of the sign determination circuit 59 was positive with respect to the reference level at the reference level input 63 of the comparison circuit 61, and a logic value of zero if the signal at the input 57 was negative with respect to this reference level.
The output 77 of the sign determination circuit 59 applies this logic one or logic zero signal to an input 79 of a decoding circuit 81 which supplies at an output 83 a switching signal of half the line frequency and the correct phase for switching the demodulation axis of a (R-Y) demodulator when a PAL signal is received, at an output combination 85 a signal combination which can bring a color television receiver comprising the color identification circuit to a PAL or NTSC receiving state, and at an output 87 a switching signal which can cause the change-over switch 39 to successively take up its two positions in a given receiving state of the receiver and which to this end is applied to a switching signal input 89 of the change-over switch 39.
The decoding circuit 81 compares the pattern of logic levels at its input 79 with a pattern to be expected in a given receiving state and a given state of the change-over switch 39, and with reference to the number of differences per period of time, for example, per field period it determines whether the receiving state of the receiver is the desired state, or whether no color information is received. This is effected by means of a counter which may be in the form of, for example a pseudo-random counter in order to obtain a small number of components.
The demodulation axis D, which is different from ninety degrees, of the second demodulation circuit 11 can now give a clear distinction between the pattern of logic levels occurring at the output 77 of the sign determination circuit due to a noise signal or due to an NTSC color synchronizing signal which occurs at the input 9 of the second demodulation circuit 11 when the change-over switch 39 is in the state not shown.
In the presence of an NTSC color synchronizing signal the negative amplitude C of the demodulated color synchronizing signal will cause the input 57 to be negative during the occurrence of the signal with respect to the rest level at the rest level input 63 so that the output 77 of the sign determination circuit always remains logic zero. In the presence of a noise signal, thus in the absence of a color synchronizing signal, the output 77 will, at an average, assume a logic zero level approximately as frequently as a logic one level.
If the demodulation axis of the second demodulation circuit 11 had been at ninety degrees, no distinction could be made because the own noise of the comparison circuit 61 could then cause the same logic signal pattern at the input 79 of the decoding circuit 81 in the presence of a noise signal as well as in the presence of an NTSC color synchronizing signal at the input 9 of the second demodulation circuit 11.
As can be seen in FIG. 2, a small difference from ninety degrees will cause a small asymmetry in a demodulated color identification component, which does not, however, introduce any change in the logic signal pattern at the input 79 of the decoding circuit 81.
If desired, the circuit may be extended by a section for identification of a SECAM color television signal, for example, by applying a frequency-demodulated SECAM color synchronizing signal to a third input of the change-over switch 39.
Capacitors are no longer required for the identification function, because this identification is now carried out in a digital signal processing section.
Instead of combining the output signals of the first and the second synchronous demodulator by means of the adder circuit 45, a third synchronous demodulator whose reference signal would have the desired phase D could be used in the second demodulation circuit 11.
The first and the second synchronous demodulators 7, 25 may also be used as color difference signal demodulators if the gating circuit 3 is omitted and if the demodulated color synchronizing signals are obtained from the output signals of the synchronous demodulators by means of gating circuits.
If desired, a sign determination circuit may be incorporated after each demodulation circuit and the change-over switch 39 may be omitted if the decoding circuit 81 is adapted to simultaneously process the output signals of the sign determination circuits.
Instead of using attenuators 41 and 49, the demodulators 7 and 25 may be formed in such a manner, for example, by choosing a certain ratio of currents supplied by current sources of multipliers in the form of synchronous demodulators, that the adder circuit 45 receives the correct amplitude ratio in the non-shown state of the change-over switch 39.

TDA4556 Multistandard decoder


GENERAL DESCRIPTION
The TDA4555 and TDA4556 are monolithic integrated
multistandard colour decoders for the PAL, SECAM,
NTSC 3,58 MHz and NTSC 4,43 MHz standards. The
difference between the TDA4555 and TDA4556 is the
polarity of the colour difference output signals (B-Y)
and (R-Y).
Features
Chrominance part
· Gain controlled chrominance amplifier for PAL, SECAM
and NTSC
· ACC rectifier circuits (PAL/NTSC, SECAM)
· Burst blanking (PAL) in front of 64 ms glass delay line
· Chrominance output stage for driving the 64 ms glass
delay line (PAL, SECAM)
· Limiter stages for direct and delayed SECAM signal
· SECAM permutator
Demodulator part
· Flyback blanking incorporated in the two synchronous
demodulators (PAL, NTSC)
· PAL switch
· Internal PAL matrix
· Two quadrature demodulators with external reference
tuned circuits (SECAM)
· Internal filtering of residual carrier
· De-emphasis (SECAM)
· Insertion of reference voltages as achromatic value
(SECAM) in the (B-Y) and (R-Y) colour difference output
stages (blanking)
Identification part
· Automatic standard recognition by sequential inquiry
· Delay for colour-on and scanning-on
· Reliable SECAM identification by PAL priority circuit
· Forced switch-on of a standard
· Four switching voltages for chrominance filters, traps
and crystals
· Two identification circuits for PAL/SECAM (H/2) and
NTSC
· PAL/SECAM flip-flop
· SECAM identification mode switch (horizontal, vertical
or combined horizontal and vertical)
· Crystal oscillator with divider stages and PLL circuitry
(PAL, NTSC) for double colour subcarrier frequency
· HUE control (NTSC)
· Service switch.




NORDMENDE PRESTIGE 72 IMC  CHASSIS F17 IMC (THOMSON ICC5 / ICC5341)   U4647 - TEA5040 (TELEFUNKEN) WIDE BAND VIDEO PROCESSOR

DESCRIPTION
The U4647 - TEA5040S is a serial bus-controlled videoprocessing
device which integrates a complex architecture
fulfilling multiple functions.


.DIGITAL CONTROL OF BRIGHTNESS,
SATURATION AND CONTRAST ON TV SIGNALS
AND R, G, B INTERNAL OR EXTERNAL
SOURCES .BUS DRIVE OF SWITCHING FUNCTIONS .DEMATRIXING OF R, G, B SIGNALS FROM
Y, R-Y, B-Y, TV MODE INPUTS .MATRIXING OF R, G, B SOURCES INTO
Y, R-Y, B-Y SIGNALS .AUTOMATIC DRIVE AND CUT-OFF CONTROLS
BY DIGITAL PROCESSING DURING
FRAME RETRACE .PEAK ANDAVERAGE BEAM CURRENT LIMITATION
.ON-CHIP SWITCHING FOR R, G, B INPUT
SELECTION .ON-CHIP INSERTION OF INTERNAL OR EXTERNAL
R, G, B SOURCES


An automatic contrast control circuit in a color television receiver for stabilizing the average DC level of the luminance information at a desired level and preventing focus blooming. The control circuitry, which is suitable for fabrication as a monolithic integrated circuit, contemplates the provision of a gain-controlled luminance amplifier stage for driving an image reproducer with luminance information having a stabilized black level. An average detector coupled to the amplifier stage output develops a control signal representative of the average DC level of the luminance information and applies it to the amplifier stage, varying its gain inversely with changes in the average luminance level. A peak limiter circuit is also provided for modifying the control signal to reduce the amplifier stage's gain whenever an AC brightness component comprising the luminance information exceeds a defined threshold level, regardless of the average DC level of the luminance information.

1. In a television receiver having a luminance processing channel for translating instantaneous luminance signals derived from received broadcast transmissions to an image reproducer, said luminance signals including black level reference information, an automatic contrast control circuit comprising in combination:

2. An automatic contrast control circuit in accordance with claim 1, wherein adjustable level shifting means are interposed between said amplifier stage and said average detector means, said adjustable level shifting means providing a contrast control for manually varying the average DC level of said luminance signals.

3. An automatic contrast control circuit in accordance with claim 1, wherein said average detector means includes a capacitor having an output terminal coupled to said amplifier stage and a second terminal coupled to a plane of reference potential, said capacitor being charged by luminance signals from said amplifier stage and developing control signals representative of the average DC level of said luminance signals.

4. An automatic contrast control circuit in accordance with claim 3, wherein said control signals with respect to a plane of reference potential are equal to the potential at which black level is stabilized minus the potential drop between black level and the average DC level of said luminance information, said control signal increasing with respect to said plane of reference potential responsive to decreasing average DC levels of said luminance signals and decreasing responsive to increasing average DC levels.

5. An automatic contrast control circuit in accordance with claim 3, wherein said peak detector means includes a semi-conductor arrangement for providing said capacitor with a low impedance discharge path whenever said brightness components exceed a predetermined threshold level, the impedance of said discharge path being dependent on the amplitude of said brightness components and the discharge interval of said semiconductor arrangement being the time period during which said brightness components exceed said threshold level, said semiconductor arrangement further decreasing said control signals with respect to said plane of reference potential irrespective of the average DC level of said luminance signals.

6. An automatic contrast control circuit in accordance with claim 5, wherein said semiconductor arrangement comprises first and second transistors, said luminance signals from said amplifier stage being coupled to the input base electrode of said first transistor, said first transistor further having an emitter electrode coupled to said capacitor output terminal and a collector electrode coupled to the base electrode of said second transistor, said second transistor having a collector electrode coupled to said capacitor output terminal and an emitter electrode coupled to said plane of reference potential, said semiconductor arrangement being conductive to provide said capacitor with a low impedance discharge path whenever said brightness components exceed the base-emitter junction breakdown voltage of said first transistor.

7. An automatic contrast control circuit in accordance with claim 6, wherein said gain-controlled luminance amplifier stage includes a pair of transistors arranged in a differential amplifier configuration, the gain of which is dependent on the bias applied to the base electrodes of said transistors.

8. An automatic contrast control circuit in accordance with claim 7, wherein inverter means invert and couple said control signals to said base electrodes in said amplifier stage, the inverted control signals increasing the gain of said amplifier stage whenever the average DC level of said luminance signals decreases and decreasing the gain of said amplifier stage whenever the average DC level of said luminance information increases or whenever said brightness components exceed said threshold level.

9. An automatic contrast control circuit in accordance with claim 3, wherein said beam current limiter means provide a low impedance discharge path for said capacitor whenever the beam current exceeds a predetermined level.

10. An automatic contrast control system in accordance with claim 9, wherein said beam current limiter means monitors pulses from a voltage multiplier high-voltage system, said pulses being proportional to the beam current generated during the previous horizontal scan line.

11. An automatic contrast control circuit in accordance with claim 10, wherein said beam current limiter means comprises a transistor having a base electrode coupled to said voltage multiplier high-voltage system, an emitter electrode coupled to a plane of reference potential and a collector electrode coupled to said capacitor, said transistor providing a low impedance discharge path whenever said pulses exceed the base-emitter junction breakdown voltage of said transistor.

Description:

BACKGROUND OF THE INVENTION

This invention relates in general to control circuitry for color television receivers and more particularly to an automatic contrast control circuit incorporated in the luminance processing channel. In accordance therewith, a variable DC control signal is derived from the luminance signal information as a function of the average luminance level. The DC control signal is applied to a gain-controlled amplifier stage in the luminance channel, varying its gain and thereby insuring that excessive beam currents will not be generated due to high average luminance levels. Conversely, the circuit is effective to increase the gain of the amplifier stage when under-modulated signals are received thereby providing the desired contrast level. When the white content of the instantaneous received signal exceeds a predetermined level, however, the DC control signal is modified to reflect the excessive white content even though the average luminance level may be low. Accordingly, the amplifier stage's gain is reduced to prevent defocusing.

In color television receivers, the various elemental areas of differing brightness levels, or shades, in the televised image correspond to the amplitude levels of the instantaneous brightness components of the luminance signals which, together with the chrominance signal, reproduce the transmitted picture information on the image display tube. The intensity of the electron beams developed in the receiver's image display tube are varied, for the most part, according to the detected amplitude levels of the instantaneous luminance signals. Accordingly, progressively higher amplitude levels generate higher intensity electron beams and, consequently, progressively lighter shades. In addition, suitable viewer-adjustable controls are customarily provided in the television receiver whereby a particularized contrast and brightness setting may be selected according to viewer preference.

It is desirable that the level of the luminance signal component corresponding to black in the televised image be maintained at the cut-off of the image reproducer. But even in those instances where there is a measure of DC coupling, the DC components of the luminance signal coupled from the video detector to the luminance channel may be degraded or otherwise restricted due to the nature of the processing circuitry as well as to other factors. Moreover, the luminance processing channel itself may well permit a degradation or undesirable shift in the desired DC characteristics. The result is that the DC level in the processed luminance signal is not properly maintained, such that, upon application to the image display tube, the black level is shifted to some undesirable reference. This leads to less than faithful half-tone reproduction on the screen of the image display tube. Gray tones can be lost simply because they are beyond the cut-off of the display tube. In other instances, blacks may appear as grays on the image display tube screen.

Thus, it is desirable to make provision for the maintenance of black level in the televised image at some stabilized reference. Various systems are of course known in the art for accomplishing this objective and take various forms and configurations. For example, an arrangement commonly known as a DC restorer circuit which includes a clamping device may be employed. However, when the black level is effectively stabilized at the image reproducer's cut-off bias point, the average level of the luminance signal information may reach the point where excessive average beam currents capable of severely damaging the image reproducer are generated. In addition, the high voltage power supply during instances of high beam current may be incapable of delivering the required beam current. Such overloading reduces the power supply output voltage and results in undesirable "focus blooming." That is, there will be a loss of brightness, reduction of horizontal widths and severe defocusing of the reproduced image. The problem in this regard has been further compounded by the "new generation" high-brightness cathode-ray tubes which require higher beam currents in order to illuminate the tube to its fullest capability during high-modulation (white) scenes. In view of the added demands on the high voltage power supply and the danger of damaging the image display tube, some method for effectively limiting the beam current is required.

Accordingly, automatic contrast control systems have been developed which reduce the gain of the luminance amplifier stage to prevent the generation of excessive beam currents or increase the gain when under-modulated signals are received. Most of these prior art automatic contrast control systems, however, measure only the average level of the luminance signals to derive the control signal utilized to vary the gain of the luminance amplifier. Consequently, when all or a major portion of the luminance signal's white content is of a high amplitude level and is concentrated on a very small portion of the image reproducer's screen, the control signal derived from the average luminance level is low, permitting the luminance amplifier stage to operate at nearly maximum gain. By concentrating the high-amplitude white content into a small area of the screen, the image display tube is likely to be overdriven during that period of time and "focus blooming" will result. Some automatic contrast systems, on the other hand, derive a control signal based on the peak amplitudes of the instantaneous luminance signals without regard to the average luminance level. Thus, while preventing blooming on high-amplitude white content, such systems are susceptible to luminance signals which have a dangerously high average level, but do not have any peak white signal content of a level where the system would take corrective action.

OBJECTS OF THE INVENTION

Accordingly, it is an object of the present invention to provide a color television receiver having black level stabilization with a new and improved automatic contrast control circuit which effectively overcomes the aforenoted disadvantages and deficiencies of prior circuits.

A further object of the invention is to provide an improved automatic contrast control circuit which develops control signals effectively varying the gain of a luminance amplifier stage to maintain an optimum contrast, while preventing the generation of excessive beam currents in the cathode-ray tube.

A more particular object of the invention is to provide an improved automatic contrast control circuit for continuously monitoring the average (DC) level of the luminance signal information and providing a control signal representative thereof to vary the gain of a luminance amplifier stage while remaining sensitive to the amplitude levels of brightness components exceeding a threshold level and modifying the control signal in accordance therewith.

Another object of the invention is to provide an improved automatic contrast control circuit which increases the gain of a luminance amplifier stage during reception of undermodulated luminance signals.

A further object of the present invention is to provide an automatic contrast control circuit of the foregoing type for deriving a variable DC control potential from applied luminance signals which, upon application to the luminance channel, adjusts the gain of a luminance amplifier stage in accordance with the varying luminance signal requirements.

Still another object of the invention is to provide a luminance processing channel including automatic contrast control circuitry which may be fabricated as a monolithic integrated circuit to provide an output luminance signal having stabilized black level and optimum contrast without producing excessive beam currents.

SUMMARY OF THE INVENTION

In accordance with the present invention, an improved automatic contrast control circuit is provided for varying the gain of an amplifier stage in the luminance processing channel of a color television receiver whenever the average DC level of the input luminance information varies from a desired level, or whenever the peak amplitudes of the AC brightness components of the luminance information exceed a predetermined threshhold level. In a preferred embodiment, the automatic contrast control circuit includes a gain-controlled luminance amplifier stage in a luminance processing channel for translating instantaneous luminance signals derived from received broadcast transmissions to an image reproducer. The amplified luminance signals found at the output of the amplifier stage have a stabilized black level. There are also provided detector means coupled to the amplifier output for developing control signals that are representative of the average DC level of the instantaneous luminance signals. The control signals are then applied to the gain-controlled amplifier stage to vary its gain inversely with changes in the average luminance level. Finally, peak limiter means are coupled between the amplifier output and the detector means to modify the control signals whenever the instantaneous luminance signals exceed a threshhold level. The modified control signals are similarly utilized to effect inverse gain variations in the gain-controlled amplifier stage regardless of the average level of the luminance signals.

GENERAL DESCRIPTION
Brief Description
This integrated circuit incorporates the following
features :
- a synchro and two video inputs
- a fixed video output
- a switchable video output
- normal Y, R-Y, B-Y TV mode inputs
- double set of R, G, B inputs
- brightness, contrast and saturation controls as
wellon aR,G, B picture ason a normalTVpicture
- digital control inputs by means of serial bus
- peak beam current limitation
- average beam current limitation
- automaticdrive and cut-off controls
Block Diagram Description
BUS DECODER
A 3 lines bus (clock, data, enable) delivered by the
microcontroller of the TV-set enters the videoprocessor
integrated circuit (pins 13-14-15). A control
system acts in such a way that only a 9-bit word is
taken intoaccount by the videoprocessor.Six of the
bits carry the data, the remaining three carry the
address of the subsystem.


A demultiplexer directs the data towards latches
which drive the appropriate control. More detailed
information about serial bus operation is given in
the following chapter.
Video Switch
The video switch has three inputs :
- an internal video input (pin 39),
- an external video input (pin 37),
- a synchro input (pin 41),
and two outputs :
- an internal video output (pin 40),
- a switchable video output (pin 42)
The 1Vpp composite video signal applied to the
internal video input is multiplied by two and then
appears as a 2Vpp low impedance composite
video signal at the output. This signal is used to
deliver a 1Vpp/75W composite video signal to the
peri-TV plug.
The switchable video output canbe any of the three
inputs.When the Int/Ext one active bit word is high
(address number 5), the internal video input is
selected. If not, either a regeneratedsynchro pulse
or the external video signal is directed towards this
output depending on the level of the Sync/Async
one active bit word (address number 4). As this
output is to be connected to the synchro integrated
circuit, RGB information derived from an external
source via the Peri-TV plug canbedisplayed on the
screen, the synchronization of the TV-set being
then made with an external video signal.
When RGB information is derived from a source
integrated in the TV-set, a teletext decoder for
example, the synchronization can be made either
on the internal video input (in case of synchronous
data) or on the synchro input (in case of asynchronous
data).
R, G, B Inputs
There are two sets of R, G, B inputs : one is to be
connected to the peri-TV plug (Ext R, G, B), the
second one to receive the information derived from
the TV-set itself (Int R, G, B).
In order to have a saturation control on a picture
coming from the R, G, B inputs too, it is necessary
to getR-Y, B-Y and Y signals from R, G, B information
: this is performed on the first matrix that
receives the three 0.9Vp (100% white) R, G, B
signals and delivers the corresponding Y, R-Y, B-Y
signals. These ones are multiplied by 1.4 in order
to make the R-Y and B-Y signals compatible with
the R-Y and B-Y TV mode inputs. The desired R,
G, B inputs are selected by means of 3 switches
controlled by the two fast blanking signal inputs. A
high level on FB external pin selects the external
RGB sources. The three selected inputs are
clamped in order to give the required DC level at
the output of this firstmatrix. Thethree not selected
inputs are clamped on a fixed DC level.
Y, R-Y, B-Y Inputs
The 2Vpp composite video signal appearing at the
switchable output of the video switch (pin 42) is
driven through the subcarrier trap and the luminance
delay line with a 6 dB attenuation to the Y
input (1Vpp ; pin 12). In order to make this 1Vpp
(synchro to white) Y signal compatible with the
1Vpp (black to white) Y signal delivered by the first
matrix, it is necessary to multiply it by a coefficient
of 1.4.

Controls
The four brightness, contrastand saturationcontrol
functions are direct digitally controlled without using
digital-to-analog converters.
The contrast control of the Y channel is obtained
by means of a digital potentiometer which is an
attenuator including several switchable cells directly
controlled by a 5 active bit word (address
number 1). The brightness control is also made by
a digital potentiometer (5 active bit word, address
number 0). Since a + 3dB contrast capability is
required, the Y signal value could be up to 0.7Vpp
nominal. For both functions, the control characteristics
are quasi-linear.
In each R-Y and B-Y channel, a six-cell digital
attenuator is directly controlled by a 6 active bit
word (address number 6 and 7). The tracking
needed to keep the saturation constant when
changing the contrast has to be done externally by
the microcontroller. Furthermore, colour can be
disabledby blankingR-Y andB-Ysignals using one
active bit word (address number 2) to drive the
one-chip colour ON/OFF switch.
Second Matrix, Clamp, Peak Clipping, Blanking
The second matrix receives the Y, R-Y and B-Y
signals and delivers the corresponding R, G, B
signals. As it is required to have the capability of +
6dB saturation, an internal gain of 2 is applied on
both R-Y and B-Y signals.
A low clipping level is included in order to ensure a
correct blanking during the line and frame retraces.
Ahigh clipping level ensures thepeakbeamcurrent
limitation. These limitations are correct only if the
DC bias of the three R, G, B signals are precise
enough. Therefore a clamp has been added in
each channel in order to compensate for the inaccuracy
of the matrix.
Sandcastle Detector And Counter
The three level supersandcastle is used in the
circuit to deliver the burst pulse (CLP), the horizontal
pulse (HP), and the composite vertical and
horizontal blanking pulse (BLI). This last one is
regenerated in the counter which delivers a new
composite pulse (BL) in which the vertical part lasts
23 lines when the vertical part of the supersandcastle
lasts more than 11 lines.
The TEA5040S cannot work properly if this minimum
duration of 11 lines is not ensured.
The counterdelivers different pulses neededcircuit
and especially the line pulses 17 to 23 used in the
automatic drive and cut-off control system.
Automatic Drive And Cut-off Control System
Cut-off and drive adjustments are no longer required
with this integrated circuit as it has a sample
and hold feedback loop incorporating the final
stages of the TV-set. This system works in a sequentialmode.
For this purpose, special pulses are
inserted in G, R and B channels. During the lines
17, 18 and 19, a ”drive pulse” is inserted respectively
in the green, red and blue channels. The line
20 is blanked on the three channels. During the
lines 21, 22 and 23, a ”quasi cut-off pulse” is
inserted respectively in the green, red and blue
guns.
The resulting signal is then applied to the input of
a voltage controlled amplifier. In the final stages of
the TV-set, the current flowing in each green, red
and blue cathode is measured and sent to the
videoprocessorby a current source.
The three currents are added together in a resistor
matrix which can be programmed to set the ratio
between the three currents in order to get the
appropriate colour temperature. The output of the
matrix forms a high impedance voltage source
which is connectedto the integratedcircuit (pin 34).
Same measurement range between drive and cutoff
is achieved by internally grounding an external
low impedance resistor during lines 17, 18 and 19.
This is due to the fact that the drive currents are
about one hundred times higher than the cut-off
and leakage currents.
Each voltage appearing sequentially on the wire
pin 34 is then a function of specific cathode current
:
- When a current due to a drive pulse occurs, the
voltage appearing on the pin 34 is compared
within the IC with an internal reference, and the
result of the comparison charges or discharges
an external appropriate drive capacitor which
stores the value during the frame. This voltage is
applied to a voltage controlled amplifier and the
system works in such a waythat the pulse current
drive derived from the cathode is kept constant.
- During the line 20, the three guns of the picture
tube are blanked. The leakagecurrent flowing out
of the final stages is transformed into a voltage which is stored by an external leakage capacitor
to be used later as a reference for the cut-off
current measurement.
- When a current due to a cut-off pulse occurs, the
voltage appearing on the pin 34 is compared
within the ICto the voltagepresenton the leakage
memory. Anappropriate externalcapacitor is then
charged or discharged in such a way that the
difference between each measured current and
the leakage current is kept constant, and thus the
quasi cut-off current is kept constant.
AverageBeam Current Limitation
The total current of the three guns is integrated by
means of an internal resistor and an external capacitor
(pin 36) and thencompared with a programmable
voltage reference(pin 38). When 70% of the
maximum permitted beam current is reached, the
drive gain begins to be reduced ; to do so, the
amplitude of the inserted pulse is increased.
In order to keep enough contrast, the maximum
drive reduction is limited to 6dB. If it is not sufficient,
the brightness is suppressed.
SPECIFICATION FOR THE THOMSON BI-DIRECTIONAL
DATA BUS
This is a bi-directional 3-wire (ENABLE, CLOCK,
DATA) serial bus. The DATA line transmission is
bi-directional whereas ENABLE and CLOCK lines
are only microprocessor controlled. The ENABLE
and CLOCK lines are only driven by the microcomputer.






TDA4565
Colour transient improvement
circuit

GENERAL DESCRIPTION
The TDA4565 is a monolithic integrated circuit for colour transient improvement (CTI) and luminance delay line in gyrator
technique in colour television receivers.
Features
· Colour transient improvement for colour difference signals (R-Y) and (B-Y) with transient detecting-, storage- and
switching stages resulting in high transients of colour difference output signals
· A luminance signal path (Y) which substitutes the conventional Y-delay coil with an integrated Y-delay line
· Switchable delay time from 730 ns to 1000 ns in steps of 90 ns and additional fine adjustment of 50 ns
· Two Y output signals; one of 180 ns less delay.




TDA8421 Hi-fi stereo audio processor;,I2C bus


GENERAL DESCRIPTION
The TDA8421 is a monolithic bipolar integrated stereo sound circuit with a loudspeaker channel (CH1) and a headphone
channel (CH2), digital controlled via the I2C bus, for application in hi-fi audio and television sound.
Features
· Input selector
· Mode selector
· Loudspeaker channel (CH1); with volume control, balance control and mute
· Headphone channel (CH2); with volume control, balance control and mute
· Pseudo stereo and spatial function
· Bass and treble control
· Electrostatic discharge protection diodes


FUNCTIONAL DESCRIPTION
Input selector
The input to channel 1 (CH1) and channel 2 (CH2) is determined by the input selector. The selection is made from the
following AF input signals:
· IN1 L (pin 26); IN1 R (pin 28) or
· IN2 L (pin 1); IN2 R (pin 3)
Where IN1 is an internal input signal and IN2 an external input signal.
Mode selector
For each channel (CH1 and CH2) there is a mode selector which selects between stereo, sound A and sound B in the
event of bilingual transmission. Both mode selectors can be controlled independently.


Headphone channel (CH2)
Volume control and balance
The stages for volume control for CH2 consist of two parts
for left and right. In each part the gain can be adjusted
between 0 and -62 dB in steps of 2 dB. An additional step
allows an attenuation of ³ 90 dB. Both parts can be
controlled independently over the whole range, which
allows the balance to be varied by controlling the volume
of left and right.
Loudspeaker channel (CH1)
Volume control and balance
The loudspeaker channel (CH1) also consists of two parts
for volume control (left and right). In each part the gain
can be adjusted between + 16 dB and -62 dB in steps of
2 dB. An additional step allows an attenuation of ³ 90 dB.
Both parts can be controlled independently over the
whole range, which allows the balance to be varied by
controlling the volume of left and right.
Stereo/pseudo stereo/spatial stereo mode
It is possible to select three modes. Stereo, pseudo or
spatial stereo. The pseudo stereo mode receives mono
transmissions and the stereo and spatial stereo mode
receives stereo transmissions.
Bass control
The bass control stage can be switched from an
emphasis of 15 dB to an attenuation of 12 dB for low
frequencies in steps of 3 dB.
Treble control
The treble control stage can be switched from + 12 dB to
-12 dB in steps of 3 dB.
Bias and power supply
The TDA8421 includes a bias and power supply stage,
which generates a voltage of 1¤2 VCC with a low output
impedance and injector currents for the logic part.
Power-on reset
The on-chip power-on reset circuit sets the mute bit to
active, which mutes both the loudspeaker channel (CH1)
and the headphone channel (CH2). The muting can be
switched by transmission of the mute bit.
I2C bus receiver and data handling
Bus specification
The TDA8421 is controlled via the 2-wire I2C bus by a
microcomputer. The two wires (SDA - serial data, SCL -
serial clock) carry information between the devices
connected to the bus. Both SDA and SCL are bidirectional
lines, connected to a positive supply voltage via a pull up
resistor.
When the bus is free both lines are HIGH. The data on the
SDA line must be stable during the HIGH period of the
clock. The HIGH or LOW state of the data line can only
change when the clock signal on the SCL line is LOW.
The set up and hold times are specified in
AC CHARACTERISTICS.
A HIGH-to-LOW transition of the SDA line while SCL is
HIGH is defined as a start condition. A LOW-to-HIGH
transition of the SDA line while SCL is HIGH is defined as
a stop condition. The bus receiver will be reset by the
reception of a start condition. The bus is considered to be
busy after the start condition. The bus is considered to be
free again after a stop condition.



TEA5115 5 CHANNELS VIDEO SWITCH


EACH CHANNEL EXCEPT FAST BLANKING
HAS 6dB GAIN .R, G, B AND VIDEO SIGNALS ARE CLAMPED
TOTHESAMEREFERENCE VOLTAGEINORDER
TO HAVE NO OUTPUT DIFFERENTIAL
VOLTAGEWHEN SWITCHING .ALL INPUT LEVELSCOMPATIBLE WITH NFC
92250AND EN 50049NORMS .30MHzBAND WIDTH FOR R, G, B SIGNALS .INTERNAL 6.7V SHUNT REGULATOR FOR :
- LOW IMPEDANCE LOADS,
- POWER DISSIPATIONLIMITATION .INDEPENDANT VIDEO OR SYNCHRONIZING
SIGNAL SELECTION .SIMULTANEOUSSWITCHING OFR, G, BAND
FB SIGNALS BY FB1 INPUT (internal)

 

THOMSON CHASSIS ICC5 REPAIRING / SERVICING NOTES:

icc5 (110deg) lg11 faulty cg11(1nf)
icc intermittent controls- replace membrane .
icc5 1 sec eht then stby try s/c pin5 micro pro to earth .
icc5 3 lines of scan at top of pic only il14 tea2029.
icc5 3 trips then off dl55(ba157)+cl58(47uf100v)+rv82(10r).
icc5 330nf s-correction cap, check j134 22v .
icc5 3trips/dead tda2030 .
icc5 3trips/dead ,test pin 4/11 to earth if < 700r loptx.
icc5 3trips/dead dl55 ba157,cl58 47uf100v rv82 (10r, on crt base pcb) .
icc5 3trips/dead l25, zpd10 zener diode.
icc5 3trips/dead tl17 bc548b in trip cct.
icc5 3trips/dead, cp24 47uf,100v from choptr base tp24.
icc5 bent sides ew coil,tda4950,dl41(byw76),dl46(by228),rl44(66+120r).
icc5 bent sides tda4950 ew ig01 dl42(ba157) 18k across it.
icc5 blank bright raster. 10r on crt base.
icc5 blank raster dots hot smell dl21/dl22.
icc5 blank raster no snd tda2541
icc5 blank raster no snd, osd & scart ok,tda2451-2.
icc5 blank raster,line across top, dl21(esm740g).
icc5 child lock “press red green blue then hold yellow 10 secs” .
icc5 cl44(0.44uf250v).
icc5 cl48(12n4f)+tda4950+tl17.
icc5 clicking on nicam add 47k between pins 13 & 16 ic1580 nicam pcb
icc5 cold hiss ds03(bb809).
icc5 cold top lines/foldover cl52 from pin 3 loptx.
icc5 cold tripping il14(tea2029c),
icc5 color cast/bright text tv41(1k).
icc5 dead lg11,cl44(300nf).
icc5 dead rp23+1n4148 dl28.
icc5 dead “88” showing, rp42 1r2 in psu,
icc5 dead 1a6t+cap next to 1r4w resistors in mains filter unit.
icc5 dead 330nf400v lg11 tda4950+fusible jl34(22r) .
icc5 dead bu508at.
icc5 dead choptr(tp24) dp37 tl31 rl10(115k).
icc5 dead cl44 300nf250v .
icc5 dead cl48 12.4nf +tda4950 + bc548b tl17.
icc5 dead cl48.choptr(bu508a),cp23.
icc5 dead coil,lg11, tda4950 tda4950 rl44, cl48 10.5nf cl44 300nf.
icc5 dead cp02(10nf250v) blue disc.
icc5 dead cp37(1000uf) 8v line.
icc5 dead dl55(ba157).
icc5 dead eht surge cp26(470uf16v) loc241
icc5 dead fp05 rp01 rp02 rp01 on scan coils.
icc5 dead front digits ok,line scan coil plug
icc5 dead fuse blown check degauss ptc.
icc5 dead fuse cp02 10nf blue disc cap.
icc5 dead led flash once cp26(470uf25v).
icc5 dead led flash, rr30 pins.
icc5 dead led flicks once,lg11+tda4950+cl44+rl46(1k)+rl44(56r+120r)+j134(22r).
icc5 dead lg11 cl44(33pf) rl44 ig01(tda4950) add 22r in place of ji34.
icc5 dead lg11 coil+rl44(56+120r)+tda4950+cl48(10n5)+cl44(300nf).
icc5 dead lo start volts at il14 ,dp45(zpd9v1).
icc5 dead loptr 2000a3 cl48
icc5 dead loptr cause loptx try discon pins 6/8/9/10 to prove.
icc5 dead loptr cause scan coils leak to field /ew raster coil.
icc5 dead loptr s2000af bend the corners of the heatsink away from choptx.
icc5 dead loptr+cl48 11nf(51k7) loptx rl10
icc5 dead loptr,cl42(360nf250v)
icc5 dead loptr= ew trans=lg11 ig01 rl44 120r+56r.
icc5 dead loptx, choptr bu508a, field thy, jungle chip, fucus/a1 unit
icc5 dead pulse of power at switch off cl44(330nf250v).
icc5 dead rl23 1r
icc5 dead rp23 w/wound,no line drive dl29(1n4148)
icc5 dead s2000a3+4*by255+pins+mains plug.
icc5 dead stby programme up button on tv front for 6 seconds.
icc5 dead stby ir73(mda2062).
icc5 dead stby lg11 ig01 tda4950 cl44 rl46 rrl44 j134 22r
icc5 dead stby tp45=4v(should be 11.5v) stby tx lp03 .
icc5 dead switching stby/on qr27.
icc5 dead throbbing lo ht 50v, 220uf385v mains cap.
icc5 dead tl17 bc548 il14
icc5 dead tl17(bc548)
icc5 dead tp15(bc548b).
icc5 dead tp45 11.5vn, the stby transformer lp03
icc5 dead tp45(bc649).
icc5 dead trip is41(tda2030)
icc5 dead tripping dl18(zpd36),tl31(bu508a),rp43.
icc5 dead/dark blank raster, cp37 4700uf25v
icc5 degauss posistor+1r0+1.6at.
icc5 disable trip by shorting tl17 collector to emitter.
icc5 eht stays up 10 secs/no digits.
icc5 eht stby, ic904(sl486)try reset use remote or hold ch up.”
icc5 eht surge only, try disconnect pin 4 loptx, field collapse
icc5 eht/htrs ok no brill,unplug field scan coils (scr to earth)
icc5 ew (tda4950) cause lg11 flashover.
icc5 ew bowing (59p7).dg 10 6.8 zener
icc5 ew bowing tda4950
icc5 ew coil 1r+6.5r
icc5 ew coil on 110 crt,cl44 330nf,rl44,56+120r,j134 22r,tda4950.cg11 inf
icc5 ew distortion rl44(120r+56r) cl 44 0.3uf tda4950 ig010 ew coil lg11,
icc5 ew j134(22r)+tda4950 dl42(ba159)+18k, ig01
icc5 ew lg11 110deg tubes cl44 330nf; rl44 56r+120r fusible; j134 22r, ig01 tda4950 ew
icc5 ew raster ,tda4950,cg11(1nf),dg13(1n4148),dl41(byw76),lg11,rg08(22r).
icc5 ew raster ig8,rg41(10r),tg62(bc547b).
icc5 ew raster lg11 dl46+dl41+lg11+rl44+cg11+ig01+cl41+cl44+j134(72r),ig01.
icc5 excess blue iv50 .
icc5 excess brill rv82(10r) crt base.
icc5 faint pic snd ok cv90,cp37
icc5 field cl22+rl22+cl52 1000uf.
icc5 field collapse (wavy line) scan coil plug
icc5 field collapse ,line nr top, rl33(3m3),il14.
icc5 field collapse cf01, 470nf,il14,rf01(3m)/rl33, scan coil pins.
icc5 field collapse dp47, bg22,bg36,cf01, scan coil pins.
icc5 field collapse rf01(3m).
icc5 field collapse rf21(820r),rl50(1r), loptx pins.
icc5 field collapse. rf01(3m).
icc5 field top cramp,cl22 rl22,cl52 1,000uf, 23v line.
icc5 field top foldover rf(1k).
icc5 flyback lines, tv50(bf422), dl22,cl22,rl22(1k5),tv81.
icc5 front leds pulsing rp42 (1r) o/c+dp41 o/c pins.
icc5 ha11498 changed to u4647/b1-tea5040
icc5 hot hum bar/field collapse. dp47
icc5 hot snd cracks (51k5), two screen cans on nicam pcb; pin 24 of main edge.
icc5 hot snow it20(tda6316ap).
icc5 hum/hissy snd pc1253 pins cs36 qs05.
icc5 inch of pic lhs, iv02(saa5243) on t/text.
icc5 int blue pic flyback pin 11 of crt base.
icc5 int color when setting pic geometry, mod change dv11 to 100pf.
icc5 int colour,dv21(1n4148)
icc5 int field collapse. dp47
icc5 int interference/lines tda4443
icc5 int line flashes across it20(u6316).
icc5 int nicam pc1253-001.is01 ta8662 is08 adc2300 pins
icc5 int nicam ta8662+adc2300 pins.
icc5 int no color dv21(1n4148).
icc5 int no pic, tuner
icc5 int no snd,headphone socket
icc5 int no start, earth pin28 il14 for tripped test.
icc5 int pic cv57(22nf).
icc5 int sides ew, loptx pins .
icc5 int snd cr56 .
icc5 int snd headphone socket pins.
icc5 int start lines at top,1.5k rl22 4.7nf cl22.cl52 1000uf.
icc5 int stby choptr tp24
icc5 int stby,choptr tp24. pins
icc5 int ticking snd/int mute, earth spkr grill.
icc5 int trip degauss positor .
icc5 int trips ,rl48(4k7).
icc5 int trips led flashing 6 times rl18 4k7 sm.
icc5 int trips,degaussing posistor.
icc5 interference pic ,tda4443
icc5 just osd tda2451-2
icc5 just snow c109(1nf).
icc5 led flashing 6 times,rl18(4k7sm)
icc5 line collapse 2″ dl41, ll46,rl46.
icc5 lineop disconnect ,dummy load tween dp41 cathode, chassis
icc5 lines across screen, pf14(100r) field cct.
icc5 lines flashing , tuner unit,it20(u6316). pll
icc5 low blue tea5040+mod kit.
icc5 low height il14(tea2029c), ty01(bf422).
icc5 low ht(158vn), rl10(115k).
icc5 low tuning voltage ci05(1nf).
icc5 low width cl44(300nf400v)+rl44(120r+56r)
icc5 low width cl54 680nf
icc5 low width, dg10,ig01(tda4950).,dl41(byw76).
icc5 low width/ew ,0.33uf250+td4950+4r7(rf14).
icc5 lop transistor getting hot ,bend h/sink corner away from choptx.
icc5 loptr running hot cause loptx magnetic field hitting heatsink, add shield.
icc5 loptr scancoils lg11/tda4950+,,,.
icc5 loptr(s2000af)
icc5 loptx arcing dst85b172/401416, hr6260
icc5 loptx dst85b243/473197_00= hr6373
icc5 loptx+bu508a choptr (chopper transistor).
icc5 loptx=hr6373/hr6067 dst85b243 473 197_00.
icc5 mod ha11498 changed to u4647/b1-tea5040
icc5 nicam (nasty) resolder earths on nicam pcb screen
icc5 nicam clicking , earth speaker .
icc5 nicam crackles ii71(tda4445b) is09 .
icc5 nicam=nasty inconsistant companded audio muckup
icc5 no 5v cp44(22nf)leaks.
icc5 no blue rv73(47k)
icc5 no blue tea5040 iv21. mod kit wve
icc5 no channel change. ic ir01.
icc5 no channel store ir01 .
icc5 no color chv5700 as panel.
icc5 no eht,loptx.
icc5 no ew correction. j134(22r),ig01(tda4950)
icc5 no fastext ir01.
icc5 no green tv62.
icc5 no line sync ql07 from pin 18 il14.
icc5 no luma/dark screen chroma subpanel.
icc5 no nicam pc1253 qs03(16m384hz).
icc5 no nicam snd poor mono snd c176 10uf inside if can
icc5 no osd rv02(47r) tv05(mps2369a).
icc5 no osd tv07,4v3 zener on text board
icc5 no osd/ttext, tv67(bc547c)
icc5 no osd/ttext. dv05 zener (zpd10) on text pcb.
icc5 no picture bc558b decoder
icc5 no picture dl21
icc5 no picture tv50 on decoder pcb
icc5 no pic/snd lt13 dt21(in4150).
icc5 no pic/snd. cp37(4700uf) .
icc5 no pic/snd/led digits, micropro ir01(ferg07)
icc5 no raster dl22(ba157) il14,rp42(1r).
icc5 no raster/snd cp37(4u700f)
icc5 no remote ,ir receiver remove c950(10uf) add link.
icc5 no remote ir rx (mod c950 with wire)
icc5 no remote ir73/ ir01.
icc5 no scart sound tba120t.
icc5 no sound even on scart tba120t
icc5 no sound just hiss. tda4453 in if can.
icc5 no sound rs13(4r7) tr57(bc558b) ts04 is08(adc2300).
icc5 no sound tba120t sound det chip
icc5 no sound tr57(bc558b), rs13(4r7), headphone socket.
icc5 no start.rp42 on main pcb – low volts to ic il14
icc5 no text cv05 rv43 rv44(0r22).
icc5 no text dv03(zpd4v3)/dvo5(zpd10v) .
icc5 no text/osd iv05 tv67(bc547c) dv05(zpd10)dv03(zpd4v3)
icc5 no text/osd. tv67 (bc547c)
icc5 no ttext/osd. dv05 zener (zpd10) on text pcb.dv03 zener zpd4v3
icc5 no tuning it20 (tda6316ap) no volts to tuner.
icc5 no tuning it20(tda6316ap).
icc5 no video text ok rv74 2r7
icc5 no video tv50.
icc5 no video,nicam pcb 3 connect pins, luma output (top);luma input (bottom).
icc5 no/int color dv21, r35.
icc5 ns raster rg42(1r5).
icc5 odd field coloured lines(1k5) nr thyristor
icc5 odd lines on pic , scart ok,u6316 pll chip it20
icc5 osd sync rv36(22k).
icc5 osg ir01 ir01 tr84(bc238-40).
icc5 picture flutter check cp37(4700uf).
icc5 pic ripple. tr107 l120.
icc5 poor ew,ew coil+tda4950 ,dl41(byw76), dl46(by228),rl44(66+120r)
icc5 poor focus loptx faulty
icc5 poor pic lo emission rv73 47kr 1w,
icc5 poor scart picture,add 6n8f63v across rs26.
icc5 poor sound cs05(22nf/100nf).
icc5 poor start+top lines rl22(1k5) cl22(4u7f)+cl52(1000uf).
icc5 pulsing sound = nicam unit.
icc5 pulsing. dl55 (ba157)
icc5 ragged verticals dv68 on text pcb
icc5 remote control, ir receiver sl466 ic
icc5 rhs crackling is10.
icc5 ripple on picture, tr107+l120.
icc5 rolling lines, dl22(ba157).
icc5 scart poor pic. add 6n8f63v across rs26.
icc5 set trips 3 times tl29(bc639), rl30(1r ).
icc5 slow start dp51(1n4002) 12v bridge.
icc5 smeary picture iv50(u4647b).
icc5 sound hiss, tda4453 in can.
icc5 sound popping add 47k between pins 13 & 16 of is08 on pc1253
icc5 sound stutter front of spk & mid spk mounting
icc5 sound int rhs front mounted headphone socket.
icc5 sparking from res nr coil in corner lg11
icc5 stby programme up button on tv front for 6 seconds.
icc5 stby cp46, dl52(ba157),rp46dp44(zpd5v6),mda2062).
icc5 stby eht surge ic904(sl486) .
icc5 stby loptr s2000a3 tl31,cl48 10.5nf
icc5 stby press prog up front for 6 seconds.
icc5 stby rp42
icc5 stby s2000a3 +cl48(10n5f)
icc5 stby s2000a3 loptr tl31+cl48(10n5)
icc5 telefunken 617 3trips loptx.
icc5 test discon loptx 8+10, bulb 100w pin8 to earth lites 3 times if ok.
icc5 text dropout iv28 dvt5403 ir01.
icc5 text line tearing dv68(zdp6v2).
icc5 text no osg tv07.
icc5 top 3 colored flyback lines dl21 thyristor
icc5 top cramp rf12(1k),il14.
icc5 tripped cp37 4,700uf was .
icc5 tripped rl10
icc5 tripping cl48(11nf).+loptx
icc5 tripping cp29(47nf).
icc5 tripping dl51(by397)/cg05.
icc5 tripping focus arcing.
icc5 tripping ir01(micropro).
icc5 tripping ir81(mc7805).
icc5 tripping lg11 tda 4950 +s2000af .
icc5 tripping loptr+cl48.
icc5 tripping loptx s/c pins 11/3.
icc5 tripping loptx+dp37(byw72).
icc5 trips (0u33f250v)+tda4950 .
icc5 trips (22uf250v)+rl23(1r) .
icc5 trips 3 times dead cp24 47uf100v drive coupler to tr24.
icc5 trips 3 times cp24(47uf100v) drive coupler to tr24 .
icc5 trips 3 times dead dl55 ba157 cl58 47uf100v rv82 10r .
icc5 trips 3 times dl25(zpd10).
icc5 trips 3 times dl55(ba157),cl58(47uf100v),rv82(10r)
icc5 trips cl16(3n3f) il14,dl51.
icc5 trips cp37(4700uf).
icc5 trips disable tl17 c/e. dl25 zpd10 zener 13v line monitor.
icc5 trips dl25(zpd10 zenner.
icc5 trips once stby rl44 56r hold mains sw for 3-4secs
icc5 trips quietly 0u33f 250v nr loptx, e/w coil tda4950
icc5 trips tp16(bc368).
icc5 tuning bad qt16(4mhz).
icc5 tuning no 33v voltage ,tt12 bc547
icc5 vcr flag waving ,use channels end in zero. ie 10, 20 etc.
icc5 warm no ew correction pg02 2k2
icc5 warm trips cl33(10uf25v)+cp23(2n2)
icc5 white raster check rv82.
icc5 white raster rv82.
icc5 width 1″ on lhs text ic iv02.