A very compact CHASSIS THE CHASSIS V.C.182 IN MULTI BOARD FASHION for that era and was used
even for models of 20 Inches (51Cm) sets. The present invention have recognized, among other things, that a
problem to be solved can include organizing, powering, and routing
signals to or from various sections of a tv color receiver. The present subject
matter can help provide a solution to this problem, such as by providing
a modular equipment chassis. Organizing, powering, and routing signals to and from the electronictv parts can be challenging when there is limited space within a television set if it's of a portable type.
Another challenge can include a lack of
mounting locations to affix an electronic part to the compex chassis.
Yet another challenge is that each electronic part can have its own
unique power requirements and/or a dedicated power supply that can
further limit space available within the tv chassis.
Another challenge
can be dissipating or otherwise absorbing heat generated by multiple
electronic part (and their respective power supplies) when such part are mounted within a tv chassis and in close proximity to
one another. Elevated temperatures can, in some instances, damage or
compromise proper function of an electronic part. The aforementioned challenges and problems can be resolved by a modular equipment chassis like the here present the CHASSIS V.C.182.
70 14 654 01 (SYNC + DEFLECTIONS + EHT PANEL)
70 14 653 02 (SUPPLY PANEL)
70 14 655 01 (IF + VIDEO + HF PANEL)
WHITE WESTINGHOUSE (FORMENTI) W342 16" CHASSIS V.C.182 POWER SUPPLY.
What is a Flyback Transformer? The low cost, simplicity of design and intrinsic efficiency of flyback transformers have made them a popular solution for power supply designs of below 100W to 150W. Other advantages of the flyback transformer over circuits with similar topology include isolation between primary and secondary and the ability to provide multiple outputs and a choice of positive or negative voltage for the output.
Flyback transformer, or, line output transformers are a part of the power supplies in cathode ray tubes. The flyback transformer generates a high voltage, as needed by the CRT display or similar devices (e.g. plasma lamps). A flyback transformer generates a voltage between a few kilovolts to 50 kilovolts and uses high frequency switched currents between 17 kHz and 50 kHz.
The chief difference between a flyback transformer and main/audio transformer is that flybacks transfer as well as store energy, for a just a fraction of an entire switching period. The secret behind that is the coil winding on a ferrite core that has an air gap; it increases the magnetic circuit reluctance for storing the energy.
The reason it is called a flyback transformer is because the primary winding uses a relatively low-voltage saw-tooth wave. The wave gets strengthened first and then gets switched off abruptly; this causes the beam to fly back from right to left on the display.
Applications Cathode ray tube. Televisions. Plasma Lamps.
Any display requiring high voltage to operate and much more.
Highly and friendly serviceability we can see here, and it's not highly complex.
THE SIEMENS TDA 4600 Semiconductor circuit description for supplying power to electrical
equipment, comprising a transformer having a primary winding connected,
via a parallel connection of a collector-emitter path of a transistor
with a first capacitor, to both outputs of a rectifier circuit supplied,
in turn, by a line a-c voltage; said transistor having a base
controlled via a second capacitor by an output of a control circuit
acted upon, in turn by the rectified a-c line voltage as actual value
and by a reference voltage; said transformer having a first secondary
winding to which the electrical equipment to be supplied is connected;
said transformer having a second secondary winding with one terminal
thereof connected to the emitter of said transistor and the other
terminal thereof connected to an anode of a first diode leading to said
control circuit; said transformer having a third secondary winding with
one terminal thereof connected, on the one hand, via a series connection
of a third capacitor with a first resistance, to the other terminal of
said third secondary winding and connected, on the other hand, to the
emitter of said transistor, the collector of which is connected to said
primary winding; a point between said third capacitor and said first
resistance being connected to the cathode of a second diode; said
control circuit having nine terminals including a first terminal
delivering a reference voltage and connected, via a voltage divider
formed of a t
hird and fourth series-connected resistances, to the anode
of said second diode; a second terminal of said control circuit serving
for zero-crossing identification being connected via a fifth resistance
to said cathode of said second diode; a third terminal of said
control-circuit serving as actual value input being directly connected
to a divider point of said voltage divider forming said connection of
said first terminal of said control circuit to said anode of said second
diode; a fourth terminal of said control circuit delivering a sawtooth
voltage being connected via a sixth resistance to a terminal of said
primary winding of said transformer facing away from said transistor; a
fifth terminal of said control circuit serving as a protective input
being connected, via a seventh resistance to the cathode of said first
diode and, through the intermediary of said seventh resistance and an
eighth resistance, to the cathode of a third diode having an anode
connected to an input of said rectifier circuit; a sixth terminal of
said control circuit carrying said reference potential and being
connected via a fourth capacitor to said fourth terminal of said control
circuit and via a fifth capacitor to the anode of said second diode; a
seventh terminal of said control circuit establishing a potential for
pulses controlling said transistor being connected directly and an
eighth terminal of said control circuit effecting pulse control of the
base of said transistor being connected through the intermediary of a
ninth resistance to said first capacitor leading to the base of said
transistor; and a ninth terminal of said control circuit serving as a
power supply input of said control circuit being connected both to the
cathode of said first diode as well as via the intermediary of a sixth
capacitor to a terminal of said second secondary winding as well as to a
terminal of said third secondary winding.
Description:
The
invention relates to a blocking oscillator type switching power supply
for supplying power to electrical equipment, wherein the primary winding
of a transformer, in series with the emitter-collector path of a first
bipolar transistor, is connected to a d-c voltage obtained by
rectification of a line a-c voltage fed-in via two external supply
terminals, and a secondary winding of the transformer is provided for
supplying power to the electrical equipment, wherein, furthermore, the
first bipolar transistor has a base controlled by the output of a
control circuit which is acted upon in turn by the rectified a-c line
voltage as actual value and by a set-point transmitter, and wherein a
starting circuit for further control of the base of the first bipolar
transistor is provided.
Such a blocking oscillator switching
power supply is described in the German periodical, "Funkschau" (1975)
No. 5, pages 40 to 44. It is well known that the purpose of such a
circuit is to supply electronic equipment, for example, a television
set, with stabilized and controlled supply voltages. Essential for such
switching power supply is a power switching transistor i.e. a bipolar
transistor with high switching speed and high reverse voltage. This
transistor therefore constitutes an important component of the control
element of the control circuit. Furthermore, a high operating frequency
and a transformer intended for a high operating frequency are provided,
because generally, a thorough separation of the equipment to be supplied
from the supply naturally is desired. Such switching power supplies may
be constructed either for synchronized or externally controlled
operation or for non-synchronized or free-running operation. A blocking
converter is understood to be a switching power supply in which power is
delivered to the equipment to be supplied only if the switching
transistor establishing the connection between the primary coil of the
transformer and the rectified a-c voltage is cut off. The power
delivered by the line rectifier to the primary coil of the transformer
while the switching transistor is open, is interim-stored in the
transformer and then delivered to the consumer on the secondary side of
the transformer with the switching transistor cut off.
In the
blocking converter described in the aforementioned reference in the
literature, "Funkschau" (1975), No. 5, Pages 40 to 44, the power
switching transistor is connected in the manner defined in the
introduction to this applic
ation. In addition, a so-called starting
circuit is provided. Because several diodes are generally provided in
the overall circuit of a blocking oscillator according to the definition
provided in the introduction hereto, it is necessary, in order not to
damage these diodes, that due to the collector peak current in the case
of a short circuit, no excessive stress of these diodes and possibly
existing further sensitive circuit parts can occur.
Considering
the operation of a blocking oscillator, this means that, in the event of
a short circuit, the number of collector current pulses per unit time
must be reduced. For this purpose, a control and regulating circuit is
provided. Simultaneously, a starting circuit must bring the blocking
converter back to normal operation when the equipment is switched on,
and after disturbances, for example, in the event of a short circuit.
The starting circuit shown in the literature reference "Funkschau" on
Page 42 thereof, differs to some extent already from the conventional
d-c starting circuits. It is commonly known for all heretofore known
blocking oscillator circuits, however, that a thyristor or an equivalent
circuit replacing the thyristor is essential for the operation of the
control circuit.
It is accordingly an object of the invention to
provide another starting circuit. It is a further object of the
invention to provide a possible circuit for the control circuit which is
particularly well suited for this purpose. It is yet another object of
the invention to provide such a power supply which is assured of
operation over the entire range of line voltages from 90 to 270 V a-c,
while the secondary voltages and secondary load variations between
no-load and short circuit are largely constant.
With
the foregoing and other objects in view, there is provided, in
accordance with the invention, a blocking oscillator-type switching
power supply for supplying power to electrical equipment wherein a
primary winding of a transformer, in series with an emitter-collector
path of a first bipolar transistor, is connected to a d-c voltage
obtained by rectification of a line a-c voltage fed-in via two external
supply terminals, a secondary winding of the transformer being
connectible to the electrical equipment for supplying power thereto, the
first bipolar transistor having a base controlled by the output of a
control circuit acted upon, in turn, by the rectified a-c line voltage
as actual value and by a set-point transmitter, and including a starting
circuit for further control of the base of the first bipolar
transistor, including a first diode in the starting circuit having an
anode directly connected to one of the supply terminals supplied by the
a-c line voltage and a cathode connected via a resistor to an input
serving to supply power to the control circuit, the input being directly
connected to a cathode of a second diode, the second diode having an
anode connected to one terminal of another secondary winding of the
transformer, the other secondary winding having another terminal
connected to the emitter of the first bipolar transmitter.
In
accordance with another feature of the invention, there is provided a
second bipolar transistor having the same conduction type as that of the
first bipolar transistor and connected in the starting circuit with the
base thereof connected to a cathode of a semiconductor diode, the
semiconductor diode having an anode connected to the emitter of the
first bipolar transistor, the second bipolar transistor having a
collector connected via a resistor to a cathode of the first diode in
the starting circuit, and having an emitter connected to the input
serving to supply power to the control circuit and also connected to the
cathode of the second diode which is connected to the other secondary
winding of the transformer.
In accordance with a further feature
of the invention, the base of the second bipolar transistor is connected
to a resistor and via the latter to one pole of a first capacitor, the
anode of the first diode being connected to the other pole of the first
capacitor.
In accordance with an added feature of the invention,
the input serving to supply power to the control circuit is connected
via a second capacitor to an output of a line rectifier, the output of
the line rectifier being directly connected to the emitter of the first
bipolar transistor.
In accordance with an additional feature of
the invention, the other secondary winding is connected at one end to
the emitter of the first bipolar transistor and to a pole of a third
capacitor, the third capacitor having another pole connected, on the one
hand, via a resistor, to the other end of the other secondary winding
and, on the other hand, to a cathode of a third diode, the third diode
having an anode connected via a potentiometer to an actual value input
of the control circuit and, via a fourth capacitor, to the emitter of
the first bipolar transistor.
In accordance with yet another
feature of the invention, the control circuit has a control output
connected via a fifth capacitor to the base of the first bipolar
transistor for conducting to the latter control pulses generated in the
control circuit.
In accordance with a concomitant feature of the
invention, there is provided a sixth capacitor shunting the
emitter-collector path of the first transistor.
Other features which are considered as characteristic for the invention are set forth in the appended claim.
Although
the invention is illustrated and described herein as embodied in a
blocking oscillator type switching power supply, it is nevertheless not
intended to be limited to the details shown, since various modifications
and structural changes may be made therein without departing from the
spirit of the invention and within the scope and range of equivalents of
the claims.
The construction and method of operation of the invention, however,
together with additional objects and advantages thereof will be best
understood from the following description of specific embodiments when
read in connection with the accompanying drawings, in which:
FIGS. 1 and 2 are circuit diagrams of the blocking oscillator type switching power supply according to the invention; and
FIG. 3 is a circuit diagram of the control unit RS of FIGS. 1 and 2.
Referring
now to the drawing and, first, particularly to FIG. 1 thereof, there is
shown a rectifier circuit G in the form of a bridge current, which is
acted upon by a line input represented by two supply terminals 1' and
2'. Rectifier outputs 3' and 4' are shunted by an emitter-collector path
of an NPN power transistor T1 i.e. the
series connection of the so-called first bipolar transistor referred to
hereinbefore with a primary winding I of a transformer Tr. Together
with the inductance of the transformer Tr, the capacitance C1 determines
the frequency and limits the opening voltages of the switch embodied by
the first transistor T1. A capacitance C2, provided between the base of
the first transistor T1 and the control output 7,8 of a control circuit
RS, separates the d-c potentials of the control or regulating circuit
RS and the switching transistor T1 and serves for addressing this
switching transistor T1 with pulses. A resistor R1 provided at the
control output 7,8 of the control circuit RS is the negative-feedback
resistor of both output stages of the control circuit RS. It determines
the maximally possible output pulse current of the control circuit RS. A
secondary winding II of the transformer Tr takes over the power supply
of the control circuit, in steady state operation, via the diode D1. To
this end, the cathode of this diode D1 is directly connected to a power
supply input 9 of the control circuit RS, while the anode thereof is
connected to one terminal of the secondary winding II. The other
terminal of the secondary winding II is connected to the emitter of the
power switching transistor T1.
The cathode of the diode D1 and,
therewith, the power supply terminal 9 of the control circuits RS are
furthermore connected to one pole of a capacitor C3, the other pole of
which is connected to the output 3' of the rectifier G. The capacitance
of this capacitor C3 thereby smoothes the positive half-wave pulses and
serves simultaneously as an energy storage device during the starting
period. Another secondary windi
ng
III of the transformer Tr is connected by one of the leads thereof
likewise to the emitter of the first transistor T1, and by the other
lead thereof via a resistor R2, to one of the poles of a further
capacitor C4, the other pole of which is connected to the
first-mentioned lead of the other secondary winding III. This second
pole of the capacitor C4 is simultaneously connected to the output 3' of
the rectifier circuit G and, thereby, via the capacitor C3, to the
cathode of the diode D1 driven by the secondary winding II of the
transformer Tr as well as to the power supply input 9 of the control
circuit RS and, via a resistor R9, to the cathode of a second diode D4.
The second pole of the capacitor C4 is simultaneously connected directly
to the terminal 6 of the control circuit RS and, via a further
capacitor C 6, to the terminal 4 of the control circuit RS as well as,
additionally, via the resistor R6, to the other output 4' of the
rectifier circuit G. The other of the poles of the capacitor C4 acted
upon by the secondary winding II is connected via a further capacitor C5
to a node, which is connected on one side thereof, via a variable
resistor R4, to the terminals 1 and 3 of the control circuit RS, with
the intermediary of a fixed resistor R5 in the case of the terminal 1.
On the other side of the node, the latter and, therefore, the capacitor
C5 are connected to the anode of a third diode D2, the cathode of which
is connected on the one hand, to the resistor R2 mentioned hereinbefore
and leads to the secondary winding III of the transformer Tr and, on the
other hand, via a resistor R3 to the terminal 2 of the control circuit
RS.
The nine terminals of the control circuit RS have the following purposes or functions:
Terminal
1 supplies the internally generated reference voltage to ground i.e.
the nominal or reference value required for the control or regulating
process;
Terminal 2 serves as input for the oscillations provided
by the secondary winding III, at the zero point of which, the pulse
start of the driving pulse takes place;
Terminal 3 is the control
input, at which the existing actual value is communicated to the
control circuit RS, that actual value being generated by the rectified
oscillations at the secondary winding III;
Terminal 4 is
responsive to the occurrence of a maximum excursion i.e. when the
largest current flows through the first transistor T1 ;
Terminal 5
is a protective input which responds if the rectified line voltage
drops too sharply; Terminal 6 serves for the power supply of the control
process and, indeed, as ground terminal;
Terminal 7 supplies the
d-c component required for charging the coupling capacitor C2 leading
to the base of the first transistor T1 ;
Terminal 8 supplies the control pulse required for the base of the first transistor T1 ; and
Terminal 9 serves as the first terminal of the power supply of the control circuit RS.
Further details of the control circuit RS are described hereinbelow.
The
capacity C3 smoothes the positive half-wave pulses which are provided
by the secondary winding II, and simultaneously serves as an energy
storage device during the starting time. The secondary winding III
generates the control voltage and is simultaneously used as
feedback. The time delay stage R2 /C4 keeps harmonics and fast
interference spikes away from the control circuit RS. The resistor R3 is
provided as a voltage divider for the second terminal of the control
circuit RS. The diode D2 rectifies the control pulses delivered by the
secondary winding III. The capacity C5 smoothes the control voltage. A
reference voltage Uref, which is referred to ground i.e. the potential
of terminal 6 is present at the terminal 1 of the control circuit RS.
The resistors R4 and R5 form a voltage divider of the input-difference
control amplifier at the terminal 3. The desired secondary voltage can
be set manually via the variable resistor R4. A time-delay stage R6 /C6
forms a sawtooth rise which corresponds to the collector current rise of
the first bipolar transistor T1 via the primary winding I of the
transformer Tr. The sawtooth present at the terminal 4 of the control
circuit RS is limited there between the reference voltage 2 V and 4 V.
The voltage divider R7 /R8 (FIG. 2), brings to the terminal 5 of the
control circuit RS the enabling voltage for the drive pulse at the
output 8 of the control circuit RS.
The diode D4, together with
the resistor R9 in cooperation with the diode D1 and the secondary
winding II, forms the starting circuit provided, in accordance with the
invention. The operation thereof is as follows:
After the
switching power supply is switched on, d-c voltages build up at the
collector of the switching transistor T1 and at the input 4 of the
control circuit RS, as a function in time of the predetermined time
constants. The positive sinusoidal half-waves charge the capacitor C3
via the starting diode D4 and the starting resistor R9 in dependence
upon the time constant R9.C3. Via the protective input terminal 5 and
the resistor
R11 not previously mentioned and forming the connection between the
resistor R9 and the diode D1, on the one hand, and the terminal 5 of the
control circuit RS, on the other hand, the control circuit RS is biased
ready for switching-on, and the capacitor C2 is charged via the output
7. When a predetermined voltage value at the capacitor C3 or the power
supply input 9 of the control circuit RS, respectively, is reached, the
reference voltage i.e. the nominal value for the operation of the
control voltage RS, is abruptly formed, which supplies all stages of the
control circuit and appears at the output 1 thereof. Simultaneously,
the switching transistor T1 is switched into conduction via the output
8. The switching of the transistor T1 at the primary winding T of the
transformer Tr is transformed to the second secondary winding II, the
capacity C3 being thereby charged up again via the diode D1. If
sufficient energy is stored in the capacitor C3 and if the re-charge via
the diode D1 is sufficient so that the voltage at a supply input 9 does
not fall below the given minimum operating voltage, the switching power
supply then remains connected, so that the starting process is
completed. Otherwise, the starting process described is repeated several
times.
In FIG. 2, there is shown a further embodiment of the
circuit for a blocking oscillator type switching power supply, according
to the invention, as shown in FIG. 1. Essential for this circuit of
FIG. 2 is the presence of a second bipolar transistor T2 of the type of
the first bipolar transistor T1 (i.e. in the embodiments of the
invention, an npn-transistor), which forms a further component of the
starting circuit and is connected with the collector-emitter path
thereof between the resistor R9 of the starting circuit and the current
supply input 9 of the control circuit RS. The base of this second
transistor T2 is connected to a node which leads, on the one hand, via a
resistor R10 to one electrode of a capacitor C7, the other electrode of
which is connected to the anode of the diode D4 of the starting circuit
and, accordingl
y,
to the terminal 1' of the supply input of the switching power supply G.
On the other hand, the last-mentioned node and, therefore, the base of
the second transistor T2 are connected to the cathode of a Zener diode
D3, the anode of which is connected to the output 3' of the rectifier G
and, whereby, to one pole of the capacitor C3, the second pole of which
is connected to the power supply input 9 of the control circuit RS as
well as to the cathode of the diode D1 and to the emitter of the second
transistor T2. In other respects, the circuit according to FIG. 2
corresponds to the circuit according to FIG. 1 except for the resistor
R11 which is not necessary in the embodiment of FIG. 2, and the missing
connection between the resistor R9 and the cathode of the diode D1,
respectively, and the protective input 5 of the control circuit RS.
Regarding the operation of the starting circuit according to FIG. 2,
it can be stated that the positive sinusoidal half-wave of the line
voltage, delayed by the time delay stage C7, R10 drives the base of the
transistor T2 in the starting circuit. The amplitude is limited by the
diode D3 which is provided for overvoltage protection of the control
circuit RS and which is preferably incorporated as a Zener diode. The
second transistor T2 is switched into conduction. The capacity C3 is
charged, via the serially connected diode D4 and the resistor R9 and the
collector-emitter path of the transistor T2, as soon as the voltage
between the terminal 9 and the terminal 6 of the control circuit RS i.e.
the voltage U9, meets the condition U9 <[UDs -UBE (T2)].
Because
of the time constant R9.C3, several positive half-waves are necessary
in order to increase the voltage U9 at the supply terminal 9 of the
control circuit RS to such an extent that the control circuit RS is
energized. During the negative sine half-wave, a partial energy
chargeback takes place from the capacitor C3 via the emitter-base path
of the transistor T2 of the starting circuit and via the resistor R10
and the capacitor C7, respectively, into the supply network. At
approximately 2/3 of the voltage U9, which is limited by the diode D3,
the control circuit RS is switched on. At the terminal 1 thereof, the
reference voltage Uref then appears. In addition, the voltage divider R5
/R4 becomes effective. At the terminal 3, the control amplifier
receives the voltage forming the actual value, while the first bipolar
transistor T1 of the blocking-oscillator type switching power supply is
addressed pulsewise via the terminal 8.
Because the capacitor C6
is charged via the resistor R6, a higher voltage than Uref is present at
the terminal 4 if the control circuit RS is activated. The control
voltage then discharges the capacitor C6 via the terminal 4 to half the
value of the reference voltage Uref, and immediately cuts off the
addressing input 8 of the control circuit RS. The first driving pulse of
the switching transistor T1 is thereby limited to a minimum of time.
The power for switching-on the control circuit RS and for driving the
transistor T1 is supplied by the capacitor C3. The voltage U9 at the
capacitor C3 then drops. If the voltage U9 drops below the switching-off
voltage value of the control circuit RS, the latter is then
inactivated. The next positive sine half-wave would initiate the
starting process again.
By switching the transistor T1, a voltage
is transformed in the secondary winding II of the transformer Tr. The
positive component is rectified by the diode D1, recharing of the
capacitor C3 being thereby provided. The voltage U9 at the output 9 does
not, therefore, drop below the minimum value required for the operation
of the control circuit RS, so that the control circuit RS remains
activated. The power supply continues to operate in the rhythm of the
existing conditions. In operation, the voltage U9 at the supply terminal
9 of the control circuit RS has a value which meets the condition U9
>[UDs -UBE (T2)], so that the transistor T2 of the starting circuit
remains cut off.
For the internal layout of the control circuit
RS, the construction shown, in particular, from FIG. 3 is advisable.
This construction is realized, for example, in the commercially
available type TDA 4600 (Siemens AG).
The block diagram of the control circuit according to FIG. 3
shows
the power supply thereof via the terminal 9, the output stage being
supplied directly whereas all other stages are supplied via Uref. In the
starting circuit, the individual subassemblies are supplied with power
sequentially. The d-c output voltage potential of the base current gain
i.e. the voltage for the terminal 8 of the control circuit RS, and the
charging of the capacitor C2 via the terminal 7 are formed even before
the reference voltage Uref appears. Variations of the supply voltage U9
at terminal 9 and the power fluctuations at the terminal 8/terminal 7
and at the terminal 1 of the control circuit RS are leveled or smoothed
out by the voltage control. The temperature sensitivity of the control
circuit RS and, in particular, the uneven heating of the output and
input stages and input stages on the semiconductor chip containing the
control circuit in monolithically integrated form are intercepted by the
temperature compensation provided. The output values are constant in a
specific temperature range. The message for blocking the output stage,
if the supply voltage at the terminal 9 is too low, is given also by
this subassembly to a provided control logic.
The outer voltage divider of the terminal 1 via the resistors
R5 and R4 to the control tap U forms, via terminal 3, the variable side
of the bridge for the control amplifier formed as a differential
amplifier. The fixed bridge side is formed by the reference voltage Uref
via an internal voltage divider. Similarly formed are circuit portions
serving for the detection of an overload short circuit and circuit
portions serving for the "standby" no-load detection, which can be
operated likewise via terminal 3.
Within a provided trigger
circuit, the driving pulse length is determined as a function of the
sawtooth rise at the terminal 4, and is transmitted to the control
logic. In the control logic, the commands of the trigger circuit are
processed. Through the zero-crossing identification at input 2 in the
control circuit RS, the control logic is enabled to start the control
input only at the zero point of the frequency oscillation. If the
voltages at the terminal 5 and at the terminal 9 are too low, the
control logic blocks the output amplifier at the terminal 8. The output
amplifier at the terminal 7 which is responsible for the base charge in
the capacitor C2, is not touched thereby.
The base current gain
for the transistor T1 i.e. for the first transistor in accordance with
the definition of the invention, is formed by two amplifiers which
mutually operate on the capacitor C2. The roof inclination of the base
driving current for the transistor T1 is impressed by the collector
current simulation at the terminal 4 to the amplifier at the terminal 8.
The control pulse for the transistor T1 at the terminal 8 is always
built up to the potential present at the terminal 7. The amplifier
working into the terminal 7 ensures that each new switching pulse at the
terminal 8 finds the required base level at terminal 7.
Supplementing
the comments regarding FIG. 1, it should also be mentioned that the
cathode of the diode D1 connected by the anode thereof to the one end of
the secondary winding II of the transformer Tr is connected via a
resistor R11 to the protective input 5 of the control circuit RS
whereas, in the circuit acco
rding to FIG. 2, the protective input 5 of
the control circuit RS is supplied via a voltage divider R8, R7 directly
from the output 3', 4' of the rectifier G delivering the rectified line
a-c voltage, and which obtains the voltage required for executing its
function. It is evident that the first possible manner of driving the
protective input 5 can be used also in the circuit according to FIG. 2,
and the second possibility also in a circuit in accordance with FIG. 1.
The
control circuit RS which is shown in FIG. 3 and is realized in detail
by the building block TDA 4600 and which is particularly well suited in
conjunction with the blocking oscillator type switching power supply
according to the invention has 9 terminals 1-9, which have the following
characteristics, as has been explained in essence hereinabove:
Terminal
1 delivers a reference voltage Uref which serves as the
constant-current source of a voltage divider R5.R4 which supplies the
required d-c voltages for the differential amplifiers provided for the
functions control, overload detection, short-circuit detection and
"standby"-no load detection. The dividing point of the voltage divider
R5 -R4 is connected to the terminal 3 of the control circuit RS. The
terminal 3 provided as the control input of RS is controlled in the
manner described hereinabove as input for the actual value of the
voltage to be controlled or regulated by the secondary winding III of
the transformer Tr. With this input, the lengths of the control pulses
for the switching transistor T1 are determined.
Via the input
provided by the terminal 2 of the control circuit RS, the zero-point
identification in the control circuit is addressed for detecting the
zero-point of
the oscillations respectively applied to the terminal 2. If this
oscillation changes over to the positive part, then the addressing pulse
controlling the switching transistor T1 via the terminal 8 is released
in the control logic provided in the control circuit.
A
sawtooth-shaped voltage, the rise of which corresponds to the collector
current of the switching transistor T1, is present at the terminal 4 and
is minimally and maximally limited by two reference voltages. The
sawtooth voltage serves, on the one hand as a comparator for the pulse
length while, on the other hand, the slope or rise thereof is used to
obtain in the base current amplification for the switching transistor
T1, via
the terminal 8, a base drive of this switching transistor T1
which is proportional to the collector current.
The terminal 7 of
the control circuit RS as explained hereinbefore, determines the
voltage potential for the addressing pulses of the transistor T2. The
base of the switching transistor T1 is pulse-controlled via the terminal
8, as described hereinbefore. Terminal 9 is connected as the power
supply input of the control circuit RS. If a voltage level falls below a
given value, the terminal 8 is blocked. If a given positive value of
the voltage level is exceeded, the control circuit is activated. The
terminal 5 releases the terminal 8 only if a given voltage potential is
present.
Foreign References:
DE2417628A1 1975-10-23 363/37
DE2638225A1 1978-03-02 363/49
Other References:
Grundig Tech. Info. (Germany), vol. 28, No. 4, (1981).
IBM Technical Disclosure Bulletin, vol. 19, No. 3, pp. 978, 979, Aug. 1976.
German Periodical, "Funkschau", (1975), No. 5, pp. 40 to 44.
Inventors:
Peruth, Gunther (Munich, DE) Siemens Aktiengesellschaft (Berlin and Munich, DE)
A switching mode power supply (SMPS) may be used as an apparatus for
supplying power to electronic products. The SMPS converts input
alternating current (AC) voltages and outputs static voltages to operate
electronic products.The present invention relates to a switched-mode power supply. Such a
switched-mode power supply operates on the flyback converter principle,
in which a switching transistor is switched through during a switched-on
phase and magnetization is in consequence built up in a transformer,
and the switching transistor is switched off during a switched-off phase
and the magnetization is dissipated again via coupled windings of the
transformer.
In a typical switch mode power supply (SMPS) of a television receiver,
for example, the AC mains supply voltage is coupled directly to a bridge
rectifier for producing an unregulated direct current (DC) input supply
voltage that is, for example, referenced
to a common conductor,
referred to as "hot" ground, and that is conductively isolated from the
cold ground conductor. A pulse width modulator controls the duty cycle
of a chopper transistor switch that applies the unregulated supply
voltage across a primary winding of an isolating flyback transformer. In
principle a switched-mode power supply comprises at least the
following components: a switch, an inductor, a rectifier, capacitor and a
load. The load may be considered as a resistance which is in parallel
with the capacitor. During the part of the period in which the switch
conducts a current originating from the input voltage source passes
through the inductor so that energy which is derived from this source is
stored in the inductor. During the other part of the period, in which
the switch is not conducting, the energy stored in the inductor produces
a current through the rectifier which current recharges the capacitor
and, consequently, replenishes the energy losses caused by the load. By
the adjustment or control of the conducting period of the switch
relative to the cycle, the output D.C. voltage across the load can be
independent of variations of the input D.C. voltage, for example, it can
be kept constant. Such variations are caused by, for example,
fluctuations in the electric AC supply where the input voltage is
derived therefrom by rectification. A
flyback voltage at a frequency that is determined by the modulator is
developed at a secondary winding of the transformer and is rectified to
produce a DC output supply voltage such as a voltage B+ that energizes a
horizontal deflection circuit of the television receiver. The primary
winding of the flyback transformer is, for example, conductively coupled
to the hot ground conductor. The secondary winding of the flyback
transformer and voltage B+ may be conductively isolated from the hot
ground conductor by the hot-cold barrier formed by the transformer. Such
a switched mode power supply is generally called SMPS. A SMPS as it
is commonly used, for example, in consumer devices like television
receivers, video recorders, audio equipments etc. generally includes a
main switching transistor connected in series with the primary winding
of a transformer, a base drive circuit for periodically switching said
switching transistor between ON and OFF, and a control circuit for
controlling the base drive current for said main switching transistor in
such a way that output voltages derived from several secondary windings
of said transformer are stabilized.On the other hand such a SMPS generally includes a protection circuit
for case of overloading or a short circuit or any other failures within
the operating voltages. Said protection circuit is needed since without
protection means the collector-emitter current of the main switching
transistor can reach excessively high values in case of a failure which
might damage said switching transistor or cause any other damages of
circuit components.
For some uses a D.C. isolation between the input voltage source and
the output voltage is absolutely required. This is the case, for
example, with power supplies of television receivers especially where it
is desirable to connect additional apparatus to the receiver, such as,
for example, video storage devices or television game circuits. A
switched-mode power supply is eminently suitable for this purpose as the
transformer which must effect that isolation passes signals which
usually have a much higher frequency, for example 15 to 20 kHz, than
those of the electric AC supply source so that said transformer may be
relatively small in size.
With a switched-mode power supply of
the flyback converter type the inductor of the converter can be
implemented in a simple manner as a transformer. A primary winding
thereof is connected in series with the switch between the terminals of
the input voltage source whereas a secondary winding is in series with
the rectifier. The publication "Philips Application Information" 472:
"properties of d.c.-to d.c. converters for switched-mode power supplies"
of Mar. 18, 1975 describes such a circuit. Of the three types the
flyback converter has the best control properties which is evidenced by
the formula which expresses the output voltage as a function of the
input voltage and of the ratio of the time of conduction of the switch
to the entire cycle. However, it should be noted that the entire energy
which is supplied to the load by a flyback converter must be passed on
by the transformer which imposes higher requirements both on the
transformer and, particularly, on the storage capacity thereof as well
as on the switch.
SIEMENS TDA 4600-2 TDA 4600-2D
ControlIer for Switched-Mode Power Supplies / BipolarlC
In
addition to their use with TV receivers and video recorders, the ICs
TDA 4600-2 and TDA 4600-2 D can be applied in power supplied of hi-fi
sets and active speakers due to their wide operational ranges and
superior voltage stability during high load changes.
Features
• Direct driving of switching transistor
• Low start-up current
• Reversing linear overload characteristic
• Collector current - proportional to base-current input
TDA 4600-2 Circuit description
During
start-up, normal and overload operations the TDA 4600-2; or -2D
regulates, controls and protects the switching transistor installed in
the flyback converter power supplies.
I) Start-up operation
The
start-up operation is divided into three consecutive phases: 1. An
internal reference voltage is built up which supplies the voltage
regulator and effects the charging of the coupling electrolytic
capaCitor and the switching transistor. During these procedures an 19
current less than 3.2 mA will be maintained, if the supply voltage Vg
does not exceed", 12 V. 2. At Vg '" 12 V an internal reference voltage
V1 = 4 V is suddenly released to provide all IC components with the
exception of the control logic with a thermally stable and
overload-resistant current. 3. In concurrence with the release of the
reference voltage the control logic is activated by an additional
stabilization circuit, and the IC is now ready for operation. Above
sequential start-up phases ensure the charging of the switching
transistor by the coupling electrolytic capacitor and subsequent
precision switching.
II) Normal operation
Zero passages
of the feedback coil are registered at pin 2 and forwarded to the
control logic. At pin 3 (input control, overload, and standby
recognition) the rectified amplitude variations of the feedback coil are
applied. The regulating (control) amplifier operates with an input
voltage of about 2 V and a current of about 1.4 mA. According to the
internal reference voltage, ttie operating region of the regulating
amplifier will be defined by the collector current simulation pin 4 and
the overload recognition. The simulation of the collector current is
generated by an external RC network at pin 4 and an internally set
voltage level. By increasing the capacitance (10 nFl, the collector
current of the switching transistor is increased as well and establishes
the desired control range. The control range extends between a 2 V
clamped dc voltage and an ac voltage rising as a sawtooth wave, which
may vary up to a maximum amplitude of 4 V (reference voltage). By
reducing the secondary load to 20 W, the switching frequency increases
to about 50 kHz at an almost constant pulse duty factor (on-time to
period approx. 1/3). During additional secondary load reduction to about
1 W, the switching frequency will change to approx. 70 kHz, while the
pulse duty factor falls to approx. 1/11. At the same time, the collector
peak current falls below 1 A. The output level of the regulating
(control) amplifier, the overload recognition, and the collector current
simulation are compared in the trigger and the control logic is
instructed accordingly. Pin 5 will provide additional blocking
alternatives, i.e. the output at pin 8 is blocked at a voltage of equal
to or less than 2.2 Vat pin 5. Based on the start-up circuit, the zero
crossing identification, and the trigger-activated release, the control
logic flipflops are set which control both the base current
amplification and shut-down. The base current amplifier forwards the
sawtooth voltage V 4 to pin 8. Also, a current feedback with an external
resistance of R "" 0.68 Q is inserted between pin 8 and pin 7. The
resistance value determines the maximum amplitude of the base current
for the switch ing transistor. III) Safety features The base current
shut-down, released by the control logic, clamps the output of pin 7 at
1.6 V and thus blocks the driving of the switching transistor. This
preventive method will go into effect, if the voltage at pin 9 falls
below typo 7.4 V or if voltages of less than typo 22 V are present at
pin 5. In case of short-circuited secondary windings in the SMPS, the
fault condition will be continuously monitored by the IC. With the load
completely removed from the secondary winding in the SMPS, the IC is set
at a small pulse duty factor. The total power consumption of the SMPS
is kept below n = 6 to 10 W during both operating conditions. After the
output has been blocked at a supply voltage Vg of less than or equal to
typo 7.4 V, an additional voltage reduction of .1V g = 0.6 V will switch
off the reference voltage (4 V).
Thermal resistance (only applicable to TDA 4600-2 D)
Standardized, ambience-related thermal resistance Rth JA 1 versus lateral length 1of a square
copper-clad cooling area (35 IJ.m copper lamination).
Rth JA
(I = 0) = 60 K/W
Tamb:S;; 70°C
Pv= 1 W
PCB in Ifertical position circuit in vertical position static air.
Measurement circuit 2 and application circuit
Measurement diagram for overload operations
Pin configuration
(TDA 4600-2: Plastic Power Package - 9 pin SIP package)
(TDA 4600-2D: Plastic 18 pin DIP package)
Pin No,
Function
1 Vre! output
2 Zero passage identification
3 Input regulating amplifier, overload amplifier
4 Collector current simulation
5 Possible connection for additional protective circuit
6 Ground
7 DC voltage output for charging the coupling capacitor
8 Pulse output - driving the switching transistor
9 Current supply input
only applicable to TDA 4600-2 D
10
11
12
13
14
interconnected (ground)
15
16
17
18
GENERAL BASIC TRANSISTOR LINE OUTPUT STAGE OPERATION:
The
basic essentials of a transistor line output stage are shown in Fig.
1(a). They comprise: a line output transformer which provides the d.c.
feed to the line output transistor and serves mainly to generate the
high -voltage pulse from which the e.h.t. is derived, and also in
practice other supplies for various sections of the receiver; the line
output transistor and its parallel efficiency diode which form a
bidirectional switch; a tuning capacitor which resonates with the line
output transformer primary winding and the scan coils to determine the
flyback time; and the scan coils, with a series capacitor which provides
a d.c. block and also serves to provide slight integration of the
deflection current to compensate for the scan distortion that would
otherwise be present due to the use of flat screen, wide deflection
angle c.r.t.s. This basic circuit is widely used in small -screen
portable receivers with little elaboration - some use a pnp output
transistor however, with its collector connected to chassis.
Circuit Variations:
Variations
to the basic circuit commonly found include: transposition of the scan
coils and the correction capacitor; connection of the line output
transformer primary winding and its e.h.t. ove
rwinding
in series; connection of the deflection components to a tap on the
transformer to obtain correct matching of the components and conditions
in the stage; use of a boost diode which operates in identical manner to
the arrangement used in valve line output stages, thereby increasing
the effective supply to the stage; omission of the efficiency diode
where the stage is operated from an h.t. line, the collector -base
junction of the line output transistor then providing the efficiency
diode action without, in doing so, producing scan distortion; addition
of inductors to provide linearity and width adjustment; use of a pair of
series -connected line output transistors in some large -screen colour
chassis; and in colour sets the addition of line convergence circuitry
which is normally connected in series between the line scan coils and
chassis. These variations on the basic circuit do not alter the basic
mode of operation however.
Resonance
The
most important fact to appreciate about the circuit is that when the
transistor and diode are cut off during the flyback period - when the
beam is being rapidly returned from the right-hand side of the screen to
the left-hand side the tuning capacitor together with the scan coils
and the primary winding of the line output transformer form a parallel
resonant circuit: the equivalent circuit is shown in Fig. 1(b). The line
output transformer primary winding and the tuning capacitor as drawn in
Fig. 1(a) may look like a series tuned circuit, but from the signal
point of view the end of the transformer primary winding connected to
the power supply is earthy, giving the equivalent arrangement shown in
Fig. 1(b).
The Flyback Period:
Since the operation of the
circuit depends mainly upon what happens during the line flyback period,
the simplest point at which to break into the scanning cycle is at the
end of the forward scan, i.e. with the
beam deflected to the right-hand side of the screen, see Fig. 2. At
this point the line output transistor is suddenly switched off by the
squarewave drive applied to its base. Prior to this action a linearly
increasing current has been flowing in the line output transformer
primary winding and the scan coils, and as a result magnetic fields have
been built up around these components. When the transistor is switched
off these fields collapse, maintaining a flow of current which rapidly
decays to zero and returns the beam to the centre of the screen. This
flow of current charges the tuning capacitor, and the voltage at A rises
to a high positive value - of the order of 1- 2k V in large -screen
sets, 200V in the case of mains/battery portable sets. The e
nergy
in the circuit is now stored in the tuning capacitor which next
discharges, reversing the flow of current in the circuit with the result
that the beam is rapidly deflected to the left-hand side of the screen -
see Fig. 3. When the tuning capacitor has discharged, the voltage at A
has fallen to zero and the circuit energy is once more stored in the
form of magnetic fields around the inductive components. One half -cycle
of oscillation has occurred, and the flyback is complete.
Energy Recovery:
First
Part of Forward Scan The circuit then tries to continue the cycle of
oscillation, i.e. the magnetic fields again collapse, maintaining a
current flow which this time would charge the tuning capacitor
negatively (upper plate). When the voltage at A reaches about -0.6V
however the efficiency diode becomes forward biased and switches on.
This damps the circuit, preventing further oscillation, but the magnetic
fields continue to collapse and in doing so produce a linearly decaying
current flow which provides the first part of the forward s
can,
the beam returning towards the centre of the screen - see Fig. 4. The
diode shorts out the tuning capacitor but the scan correction capacitor
charges during this period, its right-hand plate becoming positive with
respect to its left-hand plate, i.e. point A. Completion of Forward Scan
When the current falls to zero, the diode will switch off. Shortly
before this state of affairs is reached however the transistor is
switched on. In practice this is usually about a third of the way
through the scan. The squarewave applied to its base drives it rapidly
to saturation, clamping the vol
tage
at point A at a small positive value - the collector emitter saturation
voltage of the transistor. Current now flows via the transistor and the
primary winding of the line output transformer, the scan correction
capacitor discharges, and the resultant flow of current in the line scan
coils drives the beam to the right-hand side of the screen see Fig. 5.
Efficiency:
The
transistor is then cut off again, to give the flyback, and the cycle of
events recurs. The efficiency of the circuit is high since there is
negligible resistance present. Energy is fed into the circuit in the
form of the magnetic fields that build up when the output transistor is
switched on. This action connects the line output transformer primary
winding across the supply, and as a result a linearly increasing current
flows through it. Since the width is
dependent on the supply voltage, this must be stabilised.
Harmonic Tuning:
There
is another oscillatory action in the circuit during the flyback period.
The considerable leakage inductance between the primary and the e.h.t.
windings of the line output transformer, and the appreciable self
-capacitance present, form a tuned circuit which is shocked into
oscillation by the flyback pulse. Unless this oscillation is controlled,
it will continue into and modulate the scan. The technique used to
overcome this effect is to tune the leakage inductance and the
associated capacitance to an odd harmonic of the line flyback
oscillation frequency. By doing this the oscillatory actions present at
the beginning of the scan cancel. Either third or fifth harmonic tuning
is used. Third harmonic tuning also has the effect of increasing the
amplitude of the e.h.t. pulse, and is generally used where a half -wave
e.h.t. rectifier is employed. Fifth harmonic tuning results in a
flat-topped e.h.t. pulse, giving improved e.h.t. regulation, and is
generally used where an e.h.t. tripler is employed to produce the e.h.t.
The tuning is mainly built into the line output transformer, though an
external variable inductance is commonly found in colour chassis so that
the tuning can be adjusted. With a following post I will go into the
subject of modern TV line timebases in greater detail with other models
and technology shown here at Obsolete Technology Tellye !
CHASSIS Simplified horizontal / line deflection circuit.
-----------------------------------------------------------------------------------------------
A horizontal deflection circuit makes a sawtooth
current flow through a deflection coil. The current
will have equal amounts of positive and negative
current. The horizontal switch transistor conducts
for the right hand side of the picture. The damper
diode conducts for the left side of the picture.
Current only flows through the fly back capacitor
during retrace time.
For time 1 the transistor is turned on. Current
ramps up in the yoke. The beam is moved from the
center of the picture to the right edge. Energy is
stored on the inductance of the yoke.
E=I2L/2
For time 2 the transistor is turned off. Energy
transfers from the yoke to the flyback capacitor. At
the end of time two all the energy from the yoke is
placed on the flyback capacitor. There is zero
current in the yoke and a large voltage on the
capacitor. The beam is quickly moved from the
right edge back to the middle of the picture.
During time 3 the energy on the capacitor flows
back into the yoke. The voltage on the flyback
capacitor decreases while the current in the yoke
builds until there is no voltage on the capacitor. By
the end of time 3 the yoke current is at it's
maximum amount but in the negative direction.
The beam is quickly deflected form the center to the
left edge.
Time 4 represents the left hand half of the picture.
Yoke current is negative and ramping down. The
beam moves from the left to the center of the
picture.
The current that flows when the horizontal switch is
closed is approximately:
Ipk ≅ Vcc T / Ldy
Ipk = collector current
T = 1/2 trace time
Ldy = total inductance (yoke + lin coil + size coil)
note:The lin coil inductance varies with current.
______
Tr ≅ 3.14 √ L C
The current that flows during retrace is produced by
the C and L oscillation. The retrace time is 1/2 the
oscillation frequency of the L and C.
I2L /2 ≅ V2C /2 or I2L = V2C As stated earlier the energy in the yoke moves to the
flyback capacitor during time 2.
V= the amount of the flyback pulse that is above the
supply voltage.
D.C. annualizes is inductors are considered
shores, capacitors are open and generally
semiconductors are removed. The voltage at the
point “B+” is the supply voltage. The collector
voltage of Q1 is also at the supply voltage. The
voltage across C2 is equal to the supply voltage.
When we A.C. annualize this circuit we will find
that the collector of Q1 has a voltage that ranges
from slightly negative to 1000 volts positive. The
average voltage must remain the same as the D.C.
value.
In the A.C. annualizes of the circuit, the
inductance of the yoke (DY) and the inductance of
the flyback transformer are in parallel. The
inductance of T2 is much larger than that if the
DY. This results is a total system inductance of
about 10% to 20% less than that of the DY it’s
self.
The voltage across the Q1 is a half sinusoid pulse during the flyback or retrace period and close to zero at
all other times. It is not possible or safe to observe this point on an oscilloscope without a proper high
frequency high voltage probe. Normally use a 100:1 probe suitable for 2,000V peak. The probe must have
been high frequency calibrated recently.
VIDEO CHROMA PROCESSING WITH TDA3300 (MOTOROLA)
TDA3300 3301 TV COLOR PROCESSOR
This device will accept a PAL or NTSC composite video signal and output the
three color signals, needing only a simple driver amplifier to interface to the pic-
ture tube. The provision of high bandwidth on-screen display inputs makes it
suitable for text display, TV games, cameras, etc. The TDA3301 B has user con»
trol laws, and also a phase shift control which operates in PAL, as well as NTSC.
0 Automatic Black Level Setup
0 Beam Current Limiting
0 Uses Inexpensive 4.43 MHZ to 3.58 MHz Crystal
0 No Oscillator Adjustment Required
0 Three OSD Inputs Plus Fast Blanking Input
0 Four DC, High Impedance User Controls
0 lnterlaces with TDA33030B SECAM Adaptor
0 Single 12 V Supply
0 Low Dissipation, Typically 600 mW
The brilliance control operates by adding a pedestal to the output
signals. The amplitude of the pedestal is controlled by Pin 30.
During CRT beam current sampling a standard pedestal is
substituted, its value being equivalent tothe value given by V30 Nom
Brightness at black level with V30 Nom is given by the sum of three gun
currents at the sampling level, i.e. 3x20 |.1A with 100 k reference
resistors on Pins 16, 19, and 22.
During picture blanking the brilliance pedestal is zero; therefore, the
output voltage during blanking is always the minimum brilliance black
level (Note: Signal channels are also gain blanked).
Chrominance Decoder
The chrominance decoder section of the TDA3301 B
consists of the following blocks:
Phase-locked reference oscillator;
Phase-locked 90 degree servo loop;
U and V axis decoders
ACC detector and identification detector; .
Identification circuits and PAL bistable; .
Color difference filters and matrixes with fast blanking
Circuits.
The major design considerations apart from optimum
performance were:
o A minimum number of factory adjustments,
o A minimum number of external components,
0 Compatibility with SECAM adapter TDA3030B,
0 Low dissipation,
0 Use of a standard 4.433618 Mhz crystal rather
than a 2.0 fc crystal with a divider.
The crystal VCO is of the phase shift variety in which the
frequency is controlled by varying the phase of the feedback.
A great deal of care was taken to ensure that the oscillator loop
gain and the crystal loading impedance were held constant in
order to ensure that the circuit functions well with low grade
crystal (crystals having high magnitude spurious responses
can cause bad phase jitter). lt is also necessary to ensure that
the gain at third harmonic is low enough to ensure absence of
oscillation at this frequency.
It can be seen that the
necessary 1 45°C phase shift is obtained by variable addition
ol two currents I1 and I2 which are then fed into the load
resistance of the crystal tuned circuit R1. Feedback is taken
from the crystal load capacitance which gives a voltage of VF
lagging the crystal current by 90°.
The RC network in the T1 collector causes I1 to lag the
collector current of T1 by 45°.
For SECAM operation, the currents I1 and I2 are added
together in a fixed ratio giving a frequency close to nominal.
When decoding PAL there are two departures from normal
chroma reference regeneration practice:
a) The loop is locked to the burst entering from the PAL
delay line matrix U channel and hence there is no
alternating component. A small improvement in signal
noise ratio is gained but more important is that the loop
filter is not compromised by the 7.8 kHz component
normally required at this point for PAL identification
b) The H/2 switching of the oscillator phase is carried out
before the phase detector. This implies any error signal
from the phase detector is a signal at 7.8 kHz and not dc.
A commutator at the phase detector output also driven
from the PAL bistable coverts this ac signal to a dc prior
to the loop filter. The purpose ot this is that constant
offsets in the phase detector are converted by the
commutator to a signal at 7.8 kHz which is integrated to
zero and does not give a phase error.
When used for decoding NTSC the bistable is inhibited, and
slightly less accurate phasing is achieved; however, as a hue
control is used on NTSC this cannot be considered to be a
serious disadvantage.
90° Reference Generation
To generate the U axis reference a variable all-pass network
is utilized in a servo loop. The output of the all-pass network
is compared with the oscillator output with a phase detector of
which the output is filtered and corrects the operating point of
the variable all»pass network .
As with the reference loop the oscillator signal is taken after
the H/2 phase switch and a commutator inserted before the
filter so that constant phase detector errors are cancelled.
For SECAM operation the loop filter is grounded causing
near zero phase shift so that the two synchronous detectors
work in phase and not in quadralure.
The use of a 4.4 MHz oscillator and a servo loop to generate
the required 90° reference signal allows the use of a standard,
high volume, low cost crystal and gives an extremely accurate
90° which may be easily switched to 0° for decoding AM
SECAM generated by the TDA3030B adapter.
ACC and Identification Detectors
During burst gate time the output components of the U and
also the V demodulators are steered into PNP emitters. One
collector current of each PNP pair is mirrored and balanced
against its twin giving push-pull current sources for driving the
ACC and the identification filter capacitors.
The identification detector is given an internal offset by
making the NPN current mirror emitter resistors unequal. The
resistors are offset by 5% such that the identification detector
pulls up on its filter capacitor with zero signal.
Identification
See Figure 11 for definitions.
Monochrome I1 > I2
PAL ldent. OK I1 < lg
PAL ldent_ X l1 > I2
NTSC I3 > I2
Only for correctly identified PAL signal is the capacitor
voltage held low since I2 is then greater than I1.
For monochrome and incorrectly identified PAL signals l1>l2
hence voltage VC rises with each burst gate pulse.
When V,ef1 is exceeded by 0.7 V Latch 1 is made to conduct
which increases the rate of voltage rise on C. Maximum
current is limited by R1.
When Vref2 is exceeded by 0.7 V then Latch 2 is made to
conduct until C is completely discharged and the current drops
to a value insufficient to hold on Latch 2.
As Latch 2 turns on Latch 1 must turn off.
Latch 2 turning on gives extra trigger pulse to bistable to
correct identification.
The inhibit line on Latch 2 restricts its conduction to alternate
lines as controlled by the bistable. This function allows the
SECAM switching line to inhibit the bistable operation by firing
Latch 2 in the correct phase for SECAM. For NTSC, Latch 2
is fired by a current injected on Pin 6.
lf the voltage on C is greater than 1.4 V, then the saturation
is held down. Only for SECAM/NTSC with Latch 2 on, or
correctly identified PAL, can the saturation control be
anywhere but minimum.
NTSC Switch
NTSC operation is selected when current (I3) is injected into
Pin 6. On the TDA33O1 B this current must be derived
externally by connecting Pin 6 to +12 V via a 27 k resistor (as
on TDA33OOB). For normal PAL operation Pin 40 should be
connected to +12 V and Pin 6 to the filter capacitor.
4 Color Difference Matrixing, Color Killing,
and Chroma Blanking
During picture time the two demodulators feed simple RC
filters with emitter follower outputs. Color killing and blanking
is performed by lifting these outputs to a voltage above the
maximum value that the color difference signal could supply.
The color difference matrixing is performed by two
differential amplifiers, each with one side split to give the
correct values of the -(B-Y) and -(Ft-Y) signals. These are
added to give the (G-Y) signal.
The three color difference signals are then taken to the
virtual grounds of the video output stages together with
luminance signal.
Sandcastle Selection
The TDA3301B may be used with a two level sandcastle
and a separate frame pulse to Pin 28, or with only a three level
(super) sandcastle. In the latter case, a resistor of 1.0 MQ is
necessary from + 12 V to Pin 28 and a 70 pF capacitor from
Pin 28 to ground.
Timing Counter for Sample Control
In order to control beam current sampling at the beginning
of each frame scan, two edge triggered flip-flops are used.
The output K ofthe first flip-flop A is used to clock the second
tlip-flop B. Clocking of A by the burst gate is inhibited by a count
of A.B.
The count sequence can only be initiated by the trailing
edge of the frame pulse. ln order to provide control signals for:
Luma/Chroma blanking
Beam current sampling
On-screen display blanking
Brilliance control
The appropriate flip-flop outputs ar matrixed with sandcastle
and frame signals by an emitter-follower matrix.
Video Output Sections
Each video output stage consists of a feedback amplifier in A further drive current is used to control the DC operating
which the input signal is a current drive to the virtual earth from point; this is derived from the sample and hold stage which
the luminance, color difference and on-screen display stages. samples the beam current after frame flyback.
TDA2541 IF AMPLIFIER WITH DEMODULATOR AND AFC
DESCRIPTION
The TDA2540 and 2541 are IF amplifier and A.M.
demodulator circuits for colour and black and white
television receivers using PNP or NPN tuners. They
are intended for reception of negative or positive
modulation CCIR standard.
They
incorporate the following functions : .Gain controlled amplifier
.Synchronous demodulator .White spot inverter .Video preamplifier with
noise protection .Switchable AFC .AGC with noise gating .Tuner AGC
output (NPN tuner for 2540)-(PNP
tuner for 2541) .VCR switch for video output inhibition (VCR
play back).An
automatic fine tuning (AFT) circuit is provided which generates an AFT
control signal in response to a video intermediate frequency (I.F.)
signal. The I.F. signal is supplied to the inputs of two buffer
amplifiers, which couple signals of like phase relationship to two
inputs of a discriminator network. The discriminator network is tuned to
the desired frequency of the video I.F. signal, and is responsive to
the buffered I.F. signals for causing respective signal voltages to be
developed at its inputs which vary differentially in magnitude in
response to the frequency deviation of the I.F. signals from the desired
I.F. frequency. The differentially related signals are detected by two
peak detector networks for use as AFT control signals. The buffer
amplifiers and peak detectors may be conveniently fabricated on a single
I.C. chip. The discriminator network is coupled to the buffer
amplifiers by two external I.C. terminals.
WHITE WESTINGHOUSE (FORMENTI) W342 16" CHASSIS V.C.182 Digital phase locked loop tuning system / PLL FREQUENCY SYNTHESIZER:
A phase locked loop circuit for use in an automatic frequency
synthesizing system. The system includes a programmer circuit which is
responsive to a channel number input signal and generates a first
digital control signal which is representative of the selected channel
number and a second digital control signal which is representative of a
predetermined group of channel numbers. A programmable divider is
controlled by the programming circuit and generates a digital output
signal which causes the phase locked loop circuit to generate a desired
system output frequency corresponding to the selected channel number
input signal. The phase locked loop circuit includes automatic fine
tuning and manual fine tuning features.
1. A digital phase locked loop tuning system responsive to a local
oscillator signal for producing a frequency synthesized digital output
signal which is utilized to control the frequency of the local
oscillator, the local oscillator having a plurality of frequencies
associated therewith corresponding, respectively, to a plurality of
selectable channels, each of the channels being allocated to one of at
least two channel groups with each channel in a particular channel group
being separated from an adjacent channel in the particular channel
group by a predetermined frequency spacing of the local oscillator,
comprising:
programming means responsive to an input signal representing a selected
channel number of a particular channel group for generating a first
digital control signal having a value corresponding to the selected
channel number and for generating a second digital control signal
representative of said particular channel group, said second digital
control signal being a constant predetermined value for all of said
channel numbers that are within said group; and
programmable divider means coupled to said programming means being
responsive to said first, second digital control signals and the local
oscillator signal, in a local oscillator mode, for generating the
digital output signal which is representative of a desired frequency
corresponding to said selected channel number, said programmable divider
means including means for dividing the local oscillator signal by first
and second factors, said first factor being related to the frequency
separation between local oscillator signals by an integral number, the
local oscillator signal being divided by said first factor during a
first interval for a first number of periods of the output signal and
being divided by said second factor for a second number of periods of
the output signal, said first number of periods being related to the
number of the channel selected, said second number being related to the
channel group within which the selected channel lies.
2. Phase locked loop system according to claim 1, wherein said
programming means including means coupled to said programming means for
receiving an MFT signal and being responsive to said MFT signal for
altering said first and second digital control signals, and said
programmable divider means being responsive to said altered digital
control signals for generating an altered system output frequency.
3. Phase locked loop system according to claim 2, wherein said
programming means includes first terminal means coupled to said
programming means for receiving an AFT control signal, and first logic
means responsive to the input signal and the AFT control signal for
generating the first digital control signal.
4. Phase locked loop system according to claim 3, wherein said
programming means includes second logic means coupled to said first
logic means and responsive to the AFT control signal for generating the
second digital control signal.
5. Phase locked loop system according to claim 4, wherein said second
logic means includes group decoder means coupled to said first logic
means.
6. Phase locked loop circuit means according to claim 5, wherein said
second logic means includes memory means coupled to said group decoder
means and to said first terminal means.
7. Phase locked loop system according to claim 6, wherein said second
logic means includes second terminal means for receiving an MFT signal,
and up/down counter latch means coupled to said memory means and to said
second terminal means for altering said first and second digital
control signals in response to said MFT signal.
8. Phase locked loop system according to claim 7, wherein said second
logic means includes adder means coupled to said up/down counter latch
means to said memory means.
9. Phase locked loop system according to claim 3, wherein said first
logic means includes channel number generator means coupled to said
first terminal means and responsive to said input signal.
10. Phase locked loop system according to claim 9, wherein said channel
number generator means includes first and second data selector means
coupled to said first terminal means, and adder means coupled to said
second data selector means and to said up/down counter latch means.
11. Phase locked loop system according to claim 1, wherein said means
for dividing the local oscillator signal includes programmable counter
means for generating a modulus control output signal, and variable
modulus prescaler divider means coupled to and responsive to said
programmable counter means, said variable modulus prescaler divider
means dividing the local oscillator signal by said first and second
factors.
12. Phase locked loop system according to claim 11, wherein said
programmable counter means includes third data selector means coupled to
receive said first and second digital control signals and said modulus
control signal.
13. Phase locked loop system according to claim 12, wherein said
programmable counter means includes a programmable counter coupled to
said third data selector means and to said variable modulus prescaler
divider means.
14. Phase locked loop system according to claim 13, wherein said
programmable counter means includes look ahead circuit means coupled to
said programmable counter, and divide by two circuit means coupled to
said look ahead circuit means for generating said modulus control output
signal.
15. Phase locked loop tuning system according to claim 1 including digital automatic fine tuning (AFT) means wherein:
said programmable divider means includes switching means responsive to
an AFT control signal to inhibit the local oscillator signal to said
programmable divider means and to provide an input signal thereto of a
different frequency than the local oscillator signal; and
said programming means including logic means responsive to said AFT
control signal for altering said first and second digital control
signals to predetermined values to cause the phase locked loop tuning
system to be operable in an automatic fine tuning mode.
16. Phase locked loop tuning system of claim 15 wherein said programmable divider means includes:
programmable counter means for generating first and second modulus control signals; and
dual modulus prescaler means responsive to said first modulus control
signal for dividing the local oscillator signal in said local oscillator
mode and said input signal of a different frequency in said automatic
fine tuning mode by said first factor which is equal to the integer six
and being responsive to said second modulus control signal for dividing
said local oscillator signal and said input signal of a different
frequency by said second factor which is equal to the integer five
respectively.
17. Phase locked loop tuning system of claim 16 wherein said signal of a
different frequency is an intermediate frequency signal provided by the
tuning system and supplied to said switching means.
18. In a phase locked loop tuning system for receiving a channel number
input signal and a local oscillator signal having groups of selectable
frequencies wherein the frequency spacing between each adjacent local
oscillator frequency within a single group is uniform, the improvement
comprising programmable divider means for generating a digital output
signal representative of a desired tuning system output frequency
including variable modulus prescaler divider means having a prescaler
division ratio being equal to P = S/Y' for dividing the local oscillator
frequency by said prescaler division ratio during a first interval for a
first number of periods of the digital output signal and for dividing
the local oscillator frequency by a second prescaler division ratio
during a second interval for a second number of periods, said second
ratio being related to said first ratio, where S is the frequency
spacing between each adjacent local oscillator frequency within a single
group (i), Y
i =D
i -X
i S, where D
i is said desired tuning system output frequency within said selected group; X
i =D
i /S rounded off to the nearest integer; Y' is chosen such that Y
i /Y' is an integer and S/Y' is an integer and Y' is the smallest value of all values of Y
i.
19. In a receiver including a tuning apparatus for providing a plurality
of local oscillator signals each corresponding to a respective one of a
plurality of selectable channels, each of the channels being allocated
to one of at least two channel groups wherein each channel is separated
from an adjacent channel in the respective channel group by a
predetermined frequency spacing, a phase locked loop tuning system for
producing a frequency synthesized output signal for controlling the
frequency of the local oscillator, comprising:
variable modulus divider means for selectively dividing the frequency of
the local oscillator signal by first and second factors in response to a
modulus control signal to provide an output signal, said first factor
being related to the frequency separation between local oscillator
signals by an integral number; and
programmable means for generating said modulus control signal to cause
said variable modulus divider means to divide by said first factor
during a first interval for a first number of periods of said output
signal and to divide by said second factor during a second interval for a
second number of periods of said output signal, said first number of
periods being related to the number of the channel selected, said second
number of periods being related to the channel group corresponding to
the selected channel.
20. The phase locked loop tuning system of claim 19 wherein said programmable means includes:
programming means responsive to a selected channel input signal for
producing first and second digital output signals, said first digital
output signal being related to the selected channel number plus one of
two constant values which are determined in accordance within which
channel group the selected channel input signal lies, said second
digital signal being a constant value for all selected channels within a
channel group; and
programmable divider means responsive to said first and second digital
output signals from said programming means for providing said variable
modulus control signal and the frequency synthesized output signal.
21. The phase locked loop tuning system of claim 20 wherein said
programming means includes automatic fine tuning (AFT) means responsive
to a AFT control signal being applied thereto when the receiver is
placed in an AFT mode wherein:
said variable modulus divider means is caused to receive a input signal different from the local oscillator signal;
said programming means being responsive to the AFT control signal for
altering said first and second digital signals such that the receiver is
finely tuned to the frequency of the received signal applied to the
receiver.
22. The phase locked loop tuning system of claim 21 wherein said
programming means includes means for receiving a manual fine tuning
(MFT) signal for altering said first and second digital output signals,
and said programmable divider means being responsive to said altered
digital control signals for generating an altered output signal.
23. The phase locked loop tuning system of claim 19 wherein the one of
said first and second factors is an even number and the other is an odd
number.
24. The phase locked loop tuning system of claim 23 wherein said first
factor is the integer six and said second factor is the integer five.
Description:
BACKGROUND OF THE INVENTION
This invention relates to digital tuning systems, and more particularly,
to a simplified digital phase locked loop (PLL) tuning system
incorporating unique digital automatic fine tuning and manual fine
tuning schemes.
Since the appearance of varactor tuners for television, many tuning
address schemes have evolved for controlling them. PLL techniques have
maintained a performance advantage but have suffered a cost disadvantage
due to complexity, the high frequencies involved, the need for
automatic fine tuning and in some localities, the need for a manual fine
tuning arrangement. With the advances that have taken place in
semiconductor technology in the last several years, the high operating
frequencies no longer present a significant problem.
Prior art PLL systems for use in television tuners have not yet been
able to incorporate an automatic fine tuning feature, nor have they been
able to incorporate a manual fine tuning system which would enable the
PLL tuning system to be intentionally offset in predetermined
increments. Television sets normally have an automatic fine tuning (AFT)
feature, but this is normally incorporated as a separate circuit which
is not directly incorporated into the television tuner.
An additional disadvantage of prior art PLL systems which are designed
for use in a television tuner environment is that they are highly
complex and relatively expensive. In order to convert the channel number
input into the proper digital control signals for the PLL, a relatively
large ROM having a capacity on the order of 82 words by 12 bits was
required. The best prior art PLL tuning systems require two high speed
programmable counters which greatly increase the system complexity. This
together with the large ROM which the system required, greatly
decreased the cost effectiveness of the system so that commercial
manufacturers were able to use these prior art PLL systems only in their
most expensive commercial television receivers.
Therefore, it is a feature of this invention to provide a digital PLL
tuning system which incorporates design techniques that vastly simplify
the complexity of the PLL while at the same time allowing the system to
meet the latest needs of a television tuning system or any other PLL
tuning system which is addressed by a channel number.
It is another feature of this invention to provide a digital PLL tuning
system that has the ability to automatically tune nonprecise station
frequencies and the ability to be manually fine tuned.
It is yet another feature of the present invention to provide a digital
PLL tuning system having only a single high speed programmable counter
and requiring a ROM capacity of only 5 words by 9 bits.
It is still another feature of this invention to provide a digital PLL
tuning system which performs the automatic fine tuning feature by
utilizing the PLL tuning system as a digital discriminator.
It is yet another feature of this invention to provide a digital PLL
tuning system incorporating a manual fine tuning (MFT) arrangement which
is capable of intentionally offsetting the local oscillator frequency
of a TV tuner in one megahertz steps or of offsetting TV IF frequency in
steps of 125 kilohertz.
SUMMARY OF THE INVENTION
The preferred embodiment of the present invention includes a phase
locked loop circuit means for an automatic frequency synthesizing
system. The phase locked loop circuit means includes programming means
which is responsive to an input signal representing a selected channel
number for generating a first digital control signal representative of
the selected channel number and for generating a second digital control
signal representative of a predetermined group of channel numbers. A
programmable divider means is coupled to the first and second digital
control signals and generates a digital output signal representative of a
desired system output frequency corresponding to the selected channel
number.
The phase locked loop circuit means further includes an automatic fine
tuning feature for fine tuning the phase locked loop output frequency to
the exact frequency of the received signal. The system further includes
a manual fine tuning provision which allows the phase locked loop
operating frequency to be intentionally offset in predetermined
increments.
PHILIPS TDA2594 HORIZONTAL COMBINATION
The PHILIPS TDA2594 is a monolithic integrated circuit intended for use in colour television receivers.
The circuit incorporates the following functions:
0 Horizontal oscillator based on the threshold switching principle.
0 Phase comparison between sync pulse and oscillator voltage (tp1).
0 Internal key pulse for phase detector (-D) fYP~ ‘I V
V3-1elp-pl WP- 1° V
* Permissible range: 1 t
Field Timebase IC :
The TDA1170 field timebase i.c. is shown in block diagram form in Fig.
3. The i.c. is housed in a 12 -pin package with copper frame and heat
dissipation tabs. It is capable of supplying up to 1.6A peak -to -peak
to drive any type of saddle -wound scanning yoke but for a colour
receiver it is suggested that the toroidal deflection coil system
developed by RCA is used. In this case the i.c. acts as a driver in
conjunction with a complementary pair of output transistors. The yoke
current in this case is in the region of 6A. The TDA1170 is designed for
operation with a nominal 22V supply. It can be operated at up t
o
35V however. A voltage doubler within the i.c. is brought into action
during the flyback time to raise the supply to 70V. Good frequency
stability is claimed and the yoke current stability with changes in
ambient temperature is such that the usual thermistor in series with the
field coils is not required. For monochrome receiver use the power
supplied to the yoke would be 0-83W for a yoke current of lA peak -to
-peak with a 1012 coil impedance and 20V supply. As the power
dissipation rating of the i.c. is 2.2W no further heatsink is required.
For use in a colour receiver with a toroidal coil impedance of 1.6Ohm
the scanning current would be 7A peak -to -peak. The power supplied to
the yoke may be as much as 6.5W while the dissipation in the i.c. would
be up to 2-3W. In this case a simple heatsink can be formed from a thin
copper sheet soldered to the heat fins- an area of about 3-4 sq. in.
should be adequate. The sync circuit at the input gives good noise
immunity while the difference between the actual and ideal interlace is
less than 0-3% of the field amplitude. Because of the high output
impedance a relatively low value (1/iF or less) output coupling
capacitor can be used. This means that mylar types instead of
electrolytics can be used, reducing the problems of linearity and
amplitude stability with respect to temperature and ageing.
DESCRIPTION
The TDA2006 is a monolithic integrated circuit in Pentawatt package, intended for use as a low frequency class ”AB” amplifier. At ±12V, d = 10 % typically it provides 12W output power on a 4Ω load and 8W on a 8
Ω . The TDA2006 provides high output current and has very low harmonic and cross-over distortion. Further the device incorporates an original (and patented)short circuit protection system comprising an arrangement for automatically limiting the dissipated power so as to keep the working point of the output transistors within their safe operating area. A conventional thermal shutdown system is also included. The TDA2006 is pin to pin equivalent to the TDA2030.
--------------------------------------------------------------------------------------
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More References:
Buhler H (1986) Sliding mode control (in French: Reglage ́
par mode de glissement). Presses
Polytechniques Romandes, Lausanne
Carpita M, Marchesoni M (1996) Experimental study of a power conditioning system using sliding
mode control. IEEE Trans Power Electron 11(5):731–742
Carrasco JM, Quero JM, Ridao FP, Perales MA, Franquelo LG (1997) Sliding mode control of a
DC/DC PWM converter with PFC implemented by neural networks. IEEE Trans Circuit Syst I
Fundam Theor Appl 44(8):743–749
DeBattista H, Mantz RJ, Christiansen CF (2000) Dynamical sliding mode power control of wind
driven induction generators. IEEE Trans Energy Convers 15(4):728–734
DeCarlo RA, Zak ̇
SH, Drakunov SV (2011) Variable structure, sliding mode controller design. In:
Levine WS (ed) The control handbook—control system advanced methods. CRC Press, Taylor
& Francis Group, Boca Raton, pp 50-1–50-22
Emelyanov SV (1967) Variable structure control systems. Nauka, Moscow (in Russian)
Filippov AF (1960) Differential equations with discontinuous right hand side. Am Math Soc
Transl 62:199–231
Guffon S (2000) Modelling and variable structure control for active power filters (in French:
“Modelisation ́
et commandes `
a structure variable de filtres actifs de puissance”). Ph.D. thesis,
Grenoble Institute of Technology, France
Guffon S, Toledo AS, Bacha S, Bornard G (1998) Indirect sliding mode control of a three-phase
active power filter. In: Proceedings of the 29th annual IEEE Power Electronics Specialists
Conference – PESC 1998. Kyushu Island, Japan, pp 1408–1414
Hung JY, Gao W, Hung JC (1993) Variable structure control: a survey. IEEE Trans Ind Electron
40(1):2–22
Itkis U (1976) Control systems of variable structure. Wiley, New York
Levant A (2007) Principles of 2-sliding mode design. Automatica 43(4):576–586
Levant A (2010) Chattering analysis. IEEE Trans Autom Control 55(6):1380–1389
Malesani L, Rossetto L, Spiazzi G, Tenti P (1995) Performance optimization of Cuk ́
converters by
sliding-mode control. IEEE Trans Power Electron 10(3):302–309
Malesani L, Rossetto L, Spiazzi G, Zuccato A (1996) An AC power supply with sliding mode
control. IEEE Ind Appl Mag 2(5):32–38
Martinez-Salamero L, Calvente J, Giral R, Poveda A, Fossas E (1998) Analysis of a bidirectional
coupled-inductor Cuk ́
converter operating in sliding mode. IEEE Trans Circuit Syst I Fundam
Theor Appl 45(4):355–363
Mattavelli P, Rossetto L, Spiazzi G (1997) Small-signal analysis of DC–DC converters with
sliding mode control. IEEE Trans Power Electron 12(1):96–102
ˇ
Sabanovic A (2011) Variable structure systems with sliding modes in motion control—a survey.
IEEE Trans Ind Inform 7(2):212–223
Sabanovic ˇ
A, Fridman L, Spurgeon S (2004) Variable structure systems: from principles to
implementation, IEE Control Engineering Series. The Institution of Engineering and Technol-
ogy, London
Sira-Ramırez ́ H (1987) Sliding motions in bilinear switched networks. IEEE Trans Circuit Syst 34
(8):919–933
Sira-Ramırez ́
H (1988) Sliding mode control on slow manifolds of DC to DC power converters. Int
J Control 47(5):1323–1340
Sira-Ramırez ́
H (1993) On the dynamical sliding mode control of nonlinear systems. Int J Control
57(5):1039–1061
Sira-Ramırez ́
H (2003) On the generalized PI sliding mode control of DC-to-DC power converters:
a tutorial. Int J Control 76(9/10):1018–1033
Sira-Ramırez ́
H, Silva-Ortigoza R (2006) Control design techniques in power electronics devices.
Springer, London
Slotine JJE, Sastry SS (1983) Tracking control of non-linear systems using sliding surface, with
application to robot manipulators. Int J Control 38(2):465–492
Spiazzi G, Mattavelli P, Rossetto L, Malesani L (1995) Application of sliding mode control to
switch-mode power supplies. J Circuit Syst Comput 5(3):337–354
Tan S-C, Lai YM, Cheung KHM, Tse C-K (2005) On the practical design of a sliding mode
voltage controlled buck converter. IEEE Trans Power Electron 20(2):425–437
Tan S-C, Lai Y-M, Tse C-K (2011) Sliding mode control of switching power converters:
techniques and implementation. CRC Press, Taylor & Francis Group, Boca Raton
Utkin VA (1972) Equations of sliding mode in discontinuous systems. Autom Remote Control 2
(2):211–219
Utkin VA (1977) Variable structure systems with sliding mode. IEEE Trans Autom Control 22
(2):212–222
Utkin V (1993) Sliding mode control design principles and applications to electric drives. IEEE
Trans Ind Electron 40(1):23–36
Venkataramanan R, Sabanovic ˇ
A, Cuk ́
S (1985) Sliding mode control of DC-to-DC converters. In:
Proceedings of IEEE Industrial Electronics Conference – IECON 1985. San Francisco,
California, USA, pp 251–258
Young KD, Utkin VI, Ozguner U (1999) A control engineer’s guide to sliding mode control. IEEE
Trans Control Syst Technol 7(3):328–342
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Other References
Buhler H (1986) Sliding mode control (in French: Reglage ́
par mode de glissement). Presses
Polytechniques Romandes, Lausanne
Carpita M, Marchesoni M (1996) Experimental study of a power conditioning system using sliding
mode control. IEEE Trans Power Electron 11(5):731–742
Carrasco JM, Quero JM, Ridao FP, Perales MA, Franquelo LG (1997) Sliding mode control of a
DC/DC PWM converter with PFC implemented by neural networks. IEEE Trans Circuit Syst I
Fundam Theor Appl 44(8):743–749
DeBattista H, Mantz RJ, Christiansen CF (2000) Dynamical sliding mode power control of wind
driven induction generators. IEEE Trans Energy Convers 15(4):728–734
DeCarlo RA, Zak ̇
SH, Drakunov SV (2011) Variable structure, sliding mode controller design. In:
Levine WS (ed) The control handbook—control system advanced methods. CRC Press, Taylor
& Francis Group, Boca Raton, pp 50-1–50-22
Emelyanov SV (1967) Variable structure control systems. Nauka, Moscow (in Russian)
Filippov AF (1960) Differential equations with discontinuous right hand side. Am Math Soc
Transl 62:199–231
Guffon S (2000) Modelling and variable structure control for active power filters (in French:
“Modelisation ́
et commandes `
a structure variable de filtres actifs de puissance”). Ph.D. thesis,
Grenoble Institute of Technology, France
Guffon S, Toledo AS, Bacha S, Bornard G (1998) Indirect sliding mode control of a three-phase
active power filter. In: Proceedings of the 29th annual IEEE Power Electronics Specialists
Conference – PESC 1998. Kyushu Island, Japan, pp 1408–1414
Hung JY, Gao W, Hung JC (1993) Variable structure control: a survey. IEEE Trans Ind Electron
40(1):2–22
Itkis U (1976) Control systems of variable structure. Wiley, New York
Levant A (2007) Principles of 2-sliding mode design. Automatica 43(4):576–586
Levant A (2010) Chattering analysis. IEEE Trans Autom Control 55(6):1380–1389
Malesani L, Rossetto L, Spiazzi G, Tenti P (1995) Performance optimization of Cuk ́
converters by
sliding-mode control. IEEE Trans Power Electron 10(3):302–309
Malesani L, Rossetto L, Spiazzi G, Zuccato A (1996) An AC power supply with sliding mode
control. IEEE Ind Appl Mag 2(5):32–38
Martinez-Salamero L, Calvente J, Giral R, Poveda A, Fossas E (1998) Analysis of a bidirectional
coupled-inductor Cuk ́
converter operating in sliding mode. IEEE Trans Circuit Syst I Fundam
Theor Appl 45(4):355–363
Mattavelli P, Rossetto L, Spiazzi G (1997) Small-signal analysis of DC–DC converters with
sliding mode control. IEEE Trans Power Electron 12(1):96–102
ˇ
Sabanovic A (2011) Variable structure systems with sliding modes in motion control—a survey.
IEEE Trans Ind Inform 7(2):212–223
Sabanovic ˇ
A, Fridman L, Spurgeon S (2004) Variable structure systems: from principles to
implementation, IEE Control Engineering Series. The Institution of Engineering and Technol-
ogy, London
References:
Sira-Ramırez ́
H (1987) Sliding motions in bilinear switched networks. IEEE Trans Circuit Syst 34
(8):919–933
Sira-Ramırez ́
H (1988) Sliding mode control on slow manifolds of DC to DC power converters. Int
J Control 47(5):1323–1340
Sira-Ramırez ́
H (1993) On the dynamical sliding mode control of nonlinear systems. Int J Control
57(5):1039–1061
Sira-Ramırez ́
H (2003) On the generalized PI sliding mode control of DC-to-DC power converters:
a tutorial. Int J Control 76(9/10):1018–1033
Sira-Ramırez ́
H, Silva-Ortigoza R (2006) Control design techniques in power electronics devices.
Springer, London
Slotine JJE, Sastry SS (1983) Tracking control of non-linear systems using sliding surface, with
application to robot manipulators. Int J Control 38(2):465–492
Spiazzi G, Mattavelli P, Rossetto L, Malesani L (1995) Application of sliding mode control to
switch-mode power supplies. J Circuit Syst Comput 5(3):337–354
Tan S-C, Lai YM, Cheung KHM, Tse C-K (2005) On the practical design of a sliding mode
voltage controlled buck converter. IEEE Trans Power Electron 20(2):425–437
Tan S-C, Lai Y-M, Tse C-K (2011) Sliding mode control of switching power converters:
techniques and implementation. CRC Press, Taylor & Francis Group, Boca Raton
Utkin VA (1972) Equations of sliding mode in discontinuous systems. Autom Remote Control 2
(2):211–219
Utkin VA (1977) Variable structure systems with sliding mode. IEEE Trans Autom Control 22
(2):212–222
Utkin V (1993) Sliding mode control design principles and applications to electric drives. IEEE
Trans Ind Electron 40(1):23–36
Venkataramanan R, Sabanovic ˇ
A, Cuk ́
S (1985) Sliding mode control of DC-to-DC converters. In:
Proceedings of IEEE Industrial Electronics Conference – IECON 1985. San Francisco,
California, USA, pp 251–258
Young KD, Utkin VI, Ozguner U (1999) A control engineer’s guide to sliding mode control. IEEE
Trans Control Syst Technol 7(3):328–342
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75. Bulletins PC-104E and PC109C, MPP and Iron Powder Cores, The Arnold Engineering Co., Marengo,
Illinois.
76. Publication TP-25-575, HCR Alloy, Telcon Metals Ltd., Sussex, England.
77. Catalog 4, Iron Powder Toridal Cores for EMI and Power Filters, Micrometals, Anaheim, Calif.
78. Bulletin 59–107, Soft Ferrites, Stackpole, St. Marys, Pa.
79. SOAR—The Basis for Reliable Power Circuit Design, Philips Product Information #68.
80. Bennett, Wilfred P., and Kurnbatovic, Robert A., “Power and Energy Limitations of Bipolar Transistors
Imposed by Thermal-Mode and Current-Mode Second-Breakdown Mechanisms,” IEEE Transactions
on Electron Devices, vol. ED28, no. 10, October 1981.
81. Roark, D. “Base Drive Considerations in High Power Switching Transistors,” TRW Applications Note
#120, 1975.
82. Gates, T. W., and Ballard, M. F., “Safe Operating Area for Power Transistors,” Mullard Technical Com-
munications, vol. 13, no. 122, April 1974.
83. Williams, P. E., “Mathematical Theory of Rectifier Circuits with Capacitor-Input Filters,” Power Con-
version International, October 1982.
84. “Guide for Surge Voltages in Low-Voltage AC Power Circuits,” IEC Publication 664, 1980.
85. Kit Sum, K., PCIM, February 1998.
86. Spangler, J., Proc. Sixth Annual Applied Power Electronics Conf., Dallas, March 10–15, 1991.
87. Neufeld, H., “Control IC for Near Unity Power Factor in SMPS,” Cherry Semiconductor Corp., October 1989.
88. Micro Linear application notes 16 and 33.
89. Micro Linear application note 34.
90. Micrometals’ “Power Conversion & Line Filter Applications” data book.
91. Pressman, Abraham I., Billings, Keith, Morey, Taylor, Switching Power Supply Design, McGraw-Hill,
2009. ISBN 978-0-07-148272-1.
92. Texas Instruments/Unitrode Data Sheet UCC3895 SLUS 157B & application notes U136A & U154.
93. Stanley, William D., Operational Amplifiers with Linear Integrated Circuits, 2d Ed., Merrill, Columbus,
Ohio, 1989. ISBN 067520660-X.
94. “LM13700 Dual Operational Transconductance Amplifiers with Linearizing Diodes and Buffers,”
National Semiconductor Corporation, 2004. http://www.national.com/ds/LM/LM13700.pdf.
Further References:
1. G. Aboud, Cathode Ray Tubes, 1997, 2nd ed., San Jose, CA, Stanford Resources, 1997.
2. G. Aboud, Cathode Ray Tubes, 1997, Internet excerpts, available http://www.stanfordresources.com/
sr/crt/crt.html, Stanford Resources, February 1998.
3. G. Shires, Ferdinand Braun and the Cathode Ray Tube, Sci. Am., 230 (3): 92–101, March 1974.
4. N. H. Lehrer, The challenge of the cathode-ray tube, in L. E. Tannas, Jr., Ed., Flat Panel Displays
and CRTs, New York: Van Nostrand Reinhold, 1985.
5. P. Keller, The Cathode-Ray Tube, Technology, History, and Applications, New York: Palisades Press,
1991.
6. D. C. Ketchum, CRT’s: the continuing evolution, Society for Information Display International
Symposium, Conference Seminar M-3, 1996.
7. L. R. Falce, CRT dispenser cathodes using molybdenum rhenium emitter surfaces, Society for
Information Display International Symposium Digest of Technical Papers, 23: 331–333, 1992.
8. J. H. Lee, J. I. Jang, B. D. Ko, G. Y. Jung, W. H. Kim, K. Takechi, and H. Nakanishi, Dispenser
cathodes for HDTV, Society for Information Display International Symposium Digest of Technical
Papers, 27: 445–448, 1996.
9. T. Nakadaira, T. Kodama, Y. Hara, and M. Santoku, Temperature and cutoff stabilization of
impregnated cathodes, Society for Information Display International Symposium Digest of Technical
Papers, 27: 811–814, 1996.
10. W. Kohl, Materials Technology for Electron Tubes, New York, Reinhold Publishing, 1951.
11. S. Sugawara, J. Kimiya, E. Kamohara, and K. Fukuda, A new dynamic-focus electron gun for color
CRTs with tri-quadrupole electron lens, Society for Information Display International Symposium
Digest of Technical Papers, 26: 103–106, 1995.
12. J. Kimiya, S. Sugawara, T. Hasegawa, and H. Mori, A 22.5 mm neck color CRT electron gun with
simplified dynamically activated quadrupole lens, Society for Information Display International
Symposium Digest of Technical Papers, 27: 795–798, 1996.
13. D. Imabayashi, M. Santoku, and J. Karasawa, New pre-focus system structure for the trinitron gun,
Society for Information Display International Symposium Digest of Technical Papers, 27: 807–810,
1996.
14. K. Kato, T. Sase, K. Sasaki, and M. Chiba, A high-resolution CRT monitor using built-in ultrasonic
motors for focus adjustment, Society for Information Display International Symposium Digest of
Technical Papers, 27: 63–66, 1996.
15. S. Sherr, Electronic Displays, 2nd ed., New York: John Wiley, 1993.
16. N. Azzi and O. Masson, Design of an NIS pin/coma-free 108° self-converging yoke for CRTs with
super-flat faceplates, Society for Information Display International Symposium Digest of Technical
Papers, 26: 183–186, 1995.
17. J. F. Fisher and R. G. Clapp, Waveforms and spectra of composite video signals, in K. Benson and
J. Whitaker, Television Engineering Handbook, Featuring HDTV Systems, New York: McGraw-Hill
Reinhold, 1992.
18. D. Pritchard, Standards and recommended practices, in K. Benson and J. Whitaker, Television
Engineering Handbook, Featuring HDTV Systems, New York: McGraw-Hill Reinhold, 1992.
19. A. Vecht, Phosphors for color emissive displays, Society for Information Display International Sym-
posium Conference Seminar Notes F-2, 1995.
20. Optical Characteristics of Cathode Ray Tube Screens, EIA publication TEP116-C, Feb., 1993.
21. G. Wyszecki and W. S. Stiles, Color Science: Concepts and Methods, Quantitative Data and Formulae,
2nd ed., New York: John Wiley & Sons, 1982.
© 1999 by CRC Press LLC
22. A. Robertson and J. Fisher, Color vision, representation, and reproduction, in K. Benson and J.
Whitaker, Television Engineering Handbook, Featuring HDTV Systems, New York: McGraw-Hill
Reinhold, 1992.
23. M. Maeda, Trinitron technology: current status and future trends, Society for Information Display
International Symposium Digest of Technical Papers, 27: 867–870, 1996.
24. C. Sherman, Field sequential color takes another step, Inf. Display, 11 (3): 12–15, March, 1995.
25. L. Ozawa, Helmet mounted 0.5 in. crt for SVGA images, Society for Information Display Interna-
tional Symposium Digest of Technical Papers, 26: 95–98, 1995.
26. C. Infante, CRT display measurements and quality, Society for Information Display International
Symposium Conference Seminar Notes M-3, 1995.
27. J. Whitaker, Electronic Displays, Technology, Design, and Applications, New York: McGraw-Hill, 1994.
28. P. Keller, Electronic Display Measurement, Concepts, Techniques, and Instrumentation, New York:
John Wiley & Sons, 1997.
Further Information
L. Ozawa, Cathodoluminescence: Theory and Applications, New York: Kodansha, 1990.
V. K. Zworykin and G. A. Morton, Television: The Electronics of Image Transmission in Color and Mono-
chrome, New York: John Wiley & Sons, 1954.
B. Wandell, The foundations of color measurement and color perception, Society for Information Display
International Symposium, Conference Seminar M-1, 1993. A nice brief introduction to color science
(31 pages).
Electronic Industries Association (EIA), 2500 Wilson Blvd., Arlington, VA 22201 (Internet: www.eia.org).
The Electronic Industries Association maintains a collection of over 1000 current engineering publi-
cations and standards. The EIA is an excellent source for information on CRT engineering, standards,
phosphors, safety, market information, and electronics in general.
The Society for Information Display (SID), 1526 Brookhollow Dr., Suite 82, Santa Ana, CA 92705-5421
(Internet: www.display.org). The Society for Information Display is a good source of engineering
research and development information on CRTs and information display technology in general.
Internet Resources:
The following is a brief list of places to begin looking on the World Wide Web for information on CRTs
and displays, standards, metrics, and current research. Also many of the manufacturers listed in Table
91.3 maintain Web sites with useful information.
The Society for Information Display
The Society of Motion Picture and Television Engineers
The Institute of Electrical and Electronics Engineers
The Electronic Industries Association
National Information Display Laboratory
The International Society for Optical Engineering
The Optical Society of America
Electronics & Electrical Engineering Laboratory
National Institute of Standards and Technology (NIST)
The Federal Communications Commission
www.display.org
www.smpte.org
www.ieee.org
www.eia.org
www.nta.org
www.spie.org
www.osa.org
www.eeel.nist.gov
www.nist.gov
www.fcc.gov
This
method of tuning the receiver relies, of course, on the frequency of
the incoming television signal being equal to its nominal or standard
frequency.
Consequently many commercially available
television apparatuses include a separate SCART connectors each
dedicated to receive input television signals in one of an RGB format
and an S-Video format. This limits the functionality of the SCART
connectors. In practical terms, the number of SCART connectors which can
be provided on a television apparatus is limited by cost and space
considerations. However, different users wish the input a wide range of
different combinations of formats of television signals, depending on
the equipment they personally own and use. However, the provision of
SCART connectors dedicated to input television signals in one of an RGB
format and an S-Video format limits the overall connectivity of the
television apparatus. Furthermore, for many users the different RGB
format and S-Video format are confusing. Some users may not understand
or may mistake the format of a television signal being supplied on a
given cable from a given piece of equipment. This can result in the
supply of input television signals of an inappropriate format for the
SCART connector concerned.
The set is build with a unique type of Modular chassis design The modular equipment chassis can include a first top support, a first
bottom support, a first side member, a second side member, and a first
guide rail. because as modern television receivers become more complex the problem of
repairing the receiver becomes more difficult. As the number of
components used in the television receiver increases the susceptibility
to breakdown increases and it becomes more difficult to replace
defective components as they are more closely spaced. The problem has
become even more complicated with the increasing number of color
television receivers in use. A color television receiver has a larger
number of circuits of a higher degree of complexity than the black and
white receiver and further a more highly trained serviceman is required
to properly service the color television receiver. 
der contract with other brands.
