MIVAR 29MF101 100HZ CHASSIS CS1118 INTERNAL VIEW.

MIVAR it's the only Italian manufacturer which has produced an original 100HZ set and, manufactured it under the same name brand, without, like others, buying a pre - made chassis to put in their own sets and after that rebranding it during packaging.

It' also Imprortant to Notice that the technology employed in the Digital Signal Processing it's coming from ITT/MICRONAS and PHILIPS and All other components are coming from Thomson except fro the CRT TUBE which is a PHILIPS.

MIVAR has not developed the technology present in this set, but it has developed the chassis which is the SMALLEST 100HZ Digital Chassis which you can find around the world.

The Video Digital Signal Processing and the Frame rate conversion is based on the ITT/MICRONAS Primus Chipset.

Television receiver for flicker-free reproduction of an interlaced video signal:


In the existing television system, a so-called interlaced scanning system is carried out. That is, one picture (frame) is transmitted by two vertical scannings (fields). This interlaced scanning system is considered in order to increase the number of scanning lines as much as possible in a limited frequency band without a flicker being perceived by a viewer.
However, in the CCIR system employed mainly in European countries, the field frequency is 50 Hz. By this frequency, the flicker can not be removed completely and the flicker becomes conspicuous particularly when the brightness of the television picture is high.

The invention pertains to a television receiver whereby an interlaced video signal containing fields is reproduced flicker-free after analog-to-digital conversion, digital processing, and digital-to-analog conversion, comprising digital memories for the digital video signal, a digital movement detector, and a digital field interpolator whose output provides the digital flicker-free video signal.
The picture quality of currently obtainable television receivers is so good that any further improvement appears impossible in view of the inherent properties of the television systems currently in use. The main reason for this lies in the interlaced scanning system, in which each television picture is divided into two fields which are transmitted at a frequency of 50 Hz or 60 Hz. This results in two types of spurious effects, namely in large-area flicker at the field frequency, which is particularly annoying in the European 50-Hz systems, and in so-called edge flicker, which occurs at horizontal edges of objects in the picture at the frame frequency of 25 Hz or 30 Hz. The latter effect not only is very annoying, especially when characters are superposed on the screen, but also reduces the subjective picture resolution, because fine structures appear to dance and cannot be distinguished very well.
To eliminate flicker, the pictures must be presented at a rate higher than the limit of the response of the human eye, which is about 70 Hz. This requires picture memories in the television receiver, and switching must take place between different picture-frequency-increasing methods depending on whether moving or still scanning lines are present, cf. G. Drechsler, "Tagungsband der 11. Jahrestagung der FKTG", June 1984, pp. 558 to 578.


To illustrate one possibility of eliminating flicker, let us consider three successive frames A, B, C, each of which is divided into two fields A1, A2; B1, B2; C1, C2 in interlaced scanning, and which are transmitted and received in this order. One way of avoiding flicker is to present each pair of fields twice, so that frame A is formed on the screen by the four fields in the order A1, A2, A1, A2, which are reproduced at twice the field frequency. This doubling eliminates large-area flicker completely, and edge flicker to a large extent.
However, difficulties are encountered with moving scenes, because, after the later movement phase contained in the second field A2, the earlier phase of the field A1 appears again, which results in the display of jerky and jagged movements that are unpleasant to view. In the presence of movements, therefore, it is necessary to switch to the field sequence A1, A1, A2, A2, so that the fields are doubled in direct succession.
The switching between these two possibilities of reproduction is effected from picture element to picture element by means of the above-mentioned movement detector, which determines the degree of movement on the basis of the difference between the last picture and the newly received picture information. For movement detection, information delayed by one frame must thus be available from the frame memory. Since, in practice, switchover from one field sequence to another results in further considerable picture disturbance, it is known from the above reference to gradually change from one field sequence to the other depending on the degree of movement.
In the reproducing method just described, the field frequency is doubled, as mentioned above. Since secondary effects, such as line crawl, cannot be eliminated in this manner, the above reference indicates that the field pairs can be combined into fields and reproduced sufficiently fast. However, nothing is said in the reference about the number of memories required for this purpose.
German Offenlegungsschrift DE No. 32 03 978 A1 describes a field-frequency-doubling arrangement which uses three field memories. These are interconnected by a suitable arrangement of multipoint switches. The received digital video signal is written alternately into two field memories. As long as the signal is being written into the first field memory at the normal field rate, the preceding field stored in the second field memory is available for readout at twice the write-in rate. With the third field memory, a further signal delay is produced, so that, if the switches are operated in a suitable manner, a pair of successive fields is available at the output of each of the three field memories. Theoretically, both doubly fast field reproduction and corresponding frame reproduction can be achieved with this system.
As investigations have shown, considerable difficulties are encountered in the practical realization of this arrangement. For example, in certain readout phases, the fields must be simultaneously read from and written into the third field memory at double speed, so that this memory must operate at four times the incoming data rate.

1. A television receiver whereby an interlaced video signal containing fields is reproduced flicker-free, said receiver comprising:
a digital movement detector receiving digital video signals;
a digital field interpolator having an output which provides said digital flicker-free video signal;
a single frame memory which is divided into first, second and third memory areas;
first, second and third bidirectional data buses each respectively associated with said first, second and third memory areas and used for word-section/word-block transfer in a unidirectional mode;
first, second and third multiplexers each connected to all of said first, second and third memory areas by said first, second and third bidirectional data buses, respectively;
a first unidirectional data bus coupling the output of said first multiplexer to a first input of said field interpolator;
a second unidirectional data bus coupling the output of said second multiplexer to a second input of said field interpolator;
a fourth bidirectional data bus coupling said third multiplexer to said movement detector and used for word-section/word-block transfer in a undirectional mode;
a sequence control circuit for controlling said movement detector, said first, second and third multiplexers, said field interpolator and said memory; said sequence control circuit controlling the storing of data words into said first, second and third memory areas at a horizontal frequency rate and controlling the reading of stored data words from said first, second and third memory areas at twice the horizontal frequency rate;
said sequence control circuit operating such that the first and second word blocks of an nth line, the first and second word blocks of line n+1, and the first and second word blocks of line n+2 are written in direct succession into said first, second, third, first, second and third memory areas respectively where n=1, 4, N/2 and N=the number of frame lines or the number of frame lines only containing picture information;
said sequence control circuit further operating such that each data word of a line of a second field is divided into two sections and the first word section of an mth line, the second word section of said mth line, the first and second word sections of line m+1, the first and second word sections of line m+2 are written in direct succession into said second, third, first, second, third and first memory areas, respectively;
said sequence control circuit further operating such that during the second half of the duration of a triple sequence of successive lines, data words of the respective triple sequence which are delayed by one frame period are read from said frame memory and compared with the data words of the triple sequence in said movement detector, and that during the first half of the duration of the next triple sequence, said data words, together with movement information are written into those of said first, second and third memory areas which contain the data word delayed by one frame period, and wherein said first and second word blocks of each data word are read out together with the corresponding word sections of each data word of the respective triple sequence.


2. A television receiver whereby an interlaced video signal containing fields is reproduced flicker-free, said receiver comprising: a digital movement detector receiving digital video signals;
a digital field interpolator having an output which provides said digital flicker-free video signal;
a single frame memory which is divided into first, second and third memory areas;
first, second and third bidirectional data buses each respectively associated with said first, second and third memory areas and used for word-section/word-block transfer in a unidirectional mode;
first, second and third multiplexers each connected to all of said first, second and third memory areas by said first, second and third bidirectional data buses, respectively;
a first unidirectional data bus coupling the output of said first multiplexer to a first input of said field interpolator;
a second unidirectional data bus coupling the output of said second multiplexer to a second input of said field interpolator;
a fourth bidirectional data bus coupling said third multiplexer to said movement detector and used for word-section/word-block transfer in a undirectional mode;
a sequence control circuit for controlling said movement detector, said first, second and third multiplexers, said field interpolator and said memory; said sequence control circuit controlling the circuitry of data words into said first, second and third memory areas at a horizontal frequency rate and controlling the reading of stored data words from said first, second and third memory areas at twice the horizontal frequency rate;
said sequence control circuit operating such that each data word of an nth line of a first field is divided into first, second and third word blocks which are written in direct succession into said first, second, and third memory areas, respectively where n=1, 2 . . . N/2 and N=the number of frame lines or the number of lines containing only picture information;
said sequence control circuit further operating such that each data word of an mth line of a second field is divided into first, second and third word sections which are written in direct succession into said second, third and first memory areas, respectively, where m=1+N/2, 2+N/2 . . . N;
said sequence control circuit further operating such that during the second half of the duration of an mth line and an nth line the data word of the respective mth line and nth line which is delayed by one frame period is read from the frame memory and compared with the data word of the mth line and nth line, respectively in said movement detector, and that during the first half of the duration of lines n+1 and m+1, the data word delayed by one frame period, together with the movement information, is written into those of said first, second and third memory areas which contain the data word delayed by one frame period;
said first, second and third word blocks of each data word of the nth line are read out together with the corresponding word sections of each data word of the mth line.


3. A television receiver whereby an interlaced video signal containing fields is reproduced flicker-free, said receiver comprising: a digital movement detector receiving digital video signals;
a digital field interpolator having an output which provides said digital flicker-free video signal;
a single frame memory which is divided into first, second and third memory areas;
first, second and third bidirectional data buses each respectively associated with said first, second and third memory areas and used for word-section/word-block transfer in a unidirectional mode;
first, second and third multiplexers each connected to all of said first, second and third memory areas by said first, second and third bidirectional data buses, respectively;
a first unidirectional data bus coupling the output of said first multiplexer to a first input of said field interpolator;
a second unidirectional data bus coupling the output of said second multiplexer to a second input of said field interpolator;
a fourth bidirectional data bus coupling said third multiplexer to said movement detector and used for word-section/word-block transfer in a undirectional mode;
a sequence control circuit for controlling said movement detector, said first, second and third multiplexers, said field interpolator and said memory; said sequence control circuit controlling the circuitry of data words into said first, second and third memory areas at a horizontal frequency rate and controlling the reading of stored data words from said first, second and third memory areas at twice the horizontal frequency rate;
said sequence control circuit operating such that each data word of a line of a first field is divided into first, second, third and fourth blocks; said first, second, third and fourth blocks of an nth line are written respectively into said first, second, third and first memory areas; said first, second third and fourth blocks of line n+1 are written respectively into said second, third, first and second memory areas, and said first, second, third and fourth blocks of line n+2 are written into said third, first, second and third memory areas; where n=1, 4 . . . N/2;
said sequence control circuit further operating such that each data word of a line of a second field is divided into first, second, third and fourth sections; said first, second, third and fourth sections of an mth line are written into said second, third, first and second memory areas, respectively; said first, second, third and fourth sections of line m+1 are written into said third, first, second and third memory areas, respectively; and said first, second, third and fourth sections of line m+2 are written into said first, second, third and fourth memory areas, respectively; where m=1+N/2, 4+N/2 . . . N;
said sequence control circuit further operating such that during the second half of the duration of a triple sequence of successive lines, those data words of the respective triple sequence delayed by one frame period are read from said memory and compared with the data words of the triple sequence in said movement detection; and that during the first half of the next triple sequence said data words, together with the movement information, are written into those of said first, second and third memory areas which contain data words delayed by one frame period; and
said first, second, third and fourth word blocks are read out together with the corresponding word sections of each data word of the mth line.

Description:

BACKGROUND OF THE INVENTION
The invention pertains to a television receiver whereby an interlaced video signal containing fields is reproduced flicker-free after analog-to-digital conversion, digital processing, and digital-to-analog conversion, comprising digital memories for the digital video signal, a digital movement detector, and a digital field interpolator whose output provides the digital flicker-free video signal.
The picture quality of currently obtainable television receivers is so good that any further improvement appears impossible in view of the inherent properties of the television systems currently in use. The main reason for this lies in the interlaced scanning system, in which each television picture is divided into two fields which are transmitted at a frequency of 50 Hz or 60 Hz. This results in two types of spurious effects, namely in large-area flicker at the field frequency, which is particularly annoying in the European 50-Hz systems, and in so-called edge flicker, which occurs at horizontal edges of objects in the picture at the frame frequency of 25 Hz or 30 Hz. The latter effect not only is very annoying, especially when characters are superposed on the screen, but also reduces the subjective picture resolution, because fine structures appear to dance and cannot be distinguished very well.
To eliminate flicker, the pictures must be presented at a rate higher than the limit of the response of the human eye, which is about 70 Hz. This requires picture memories in the television receiver, and switching must take place between different picture-frequency-increasing methods depending on whether moving or still scanning lines are present, cf. G. Drechsler, "Tagungsband der 11. Jahrestagung der FKTG", June 1984, pp. 558 to 578.
To illustrate one possibility of eliminating flicker, let us consider three successive frames A, B, C, each of which is divided into two fields A1, A2; B1, B2; C1, C2 in interlaced scanning, and which are transmitted and received in this order. One way of avoiding flicker is to present each pair of fields twice, so that frame A is formed on the screen by the four fields in the order A1, A2, A1, A2, which are reproduced at twice the field frequency. This doubling eliminates large-area flicker completely, and edge flicker to a large extent.
However, difficulties are encountered with moving scenes, because, after the later movement phase contained in the second field A2, the earlier phase of the field A1 appears again, which results in the display of jerky and jagged movements that are unpleasant to view. In the presence of movements, therefore, it is necessary to switch to the field sequence A1, A1, A2, A2, so that the fields are doubled in direct succession.
The switching between these two possibilities of reproduction is effected from picture element to picture element by means of the above-mentioned movement detector, which determines the degree of movement on the basis of the difference between the last picture and the newly received picture information. For movement detection, information delayed by one frame must thus be available from the frame memory. Since, in practice, switchover from one field sequence to another results in further considerable picture disturbance, it is known from the above reference to gradually change from one field sequence to the other depending on the degree of movement.
In the reproducing method just described, the field frequency is doubled, as mentioned above. Since secondary effects, such as line crawl, cannot be eliminated in this manner, the above reference indicates that the field pairs can be combined into fields and reproduced sufficiently fast. However, nothing is said in the reference about the number of memories required for this purpose.
German Offenlegungsschrift DE No. 32 03 978 A1 describes a field-frequency-doubling arrangement which uses three field memories. These are interconnected by a suitable arrangement of multipoint switches. The received digital video signal is written alternately into two field memories. As long as the signal is being written into the first field memory at the normal field rate, the preceding field stored in the second field memory is available for readout at twice the write-in rate. With the third field memory, a further signal delay is produced, so that, if the switches are operated in a suitable manner, a pair of successive fields is available at the output of each of the three field memories. Theoretically, both doubly fast field reproduction and corresponding frame reproduction can be achieved with this system.
As investigations have shown, considerable difficulties are encountered in the practical realization of this arrangement. For example, in certain readout phases, the fields must be simultaneously read from and written into the third field memory at double speed, so that this memory must operate at four times the incoming data rate.

SUMMARY OF THE INVENTION
Accordingly, the object of the invention as claimed is to find a simpler memory arrangement for flicker-free reproduction of video signals and to design the sequence control circuit for this memory arrangement in such a way that it can be implemented with a single integrated circuit that occupies a chip area not greater than the maximum size of mass-produced state-of-the-art devices. The attainment of this object is predicated on the discovery that flicker-free frame reproduction in the above sense is also possible with a single frame memory which is cleverly organized. Thus, compared with the arrangement disclosed in the above-mentioned Offenlegungsschrift, the arrangement in accordance with the invention has the big advantage of requiring one field memory less.

BRIEF DESCRIPTION OF THE DRAWING
The invention will be better understood from a reading of the following detailed description in conjunction with the drawing in which:
FIG. 1 shows schematically the arrangement of the lines in the interlaced scanning system;
FIG. 2 shows an allocation scheme for the lines of FIG. 1 in the frame memory of the invention;
FIG. 3 is a block diagram of an embodiment of the subcircuits that are essential for the invention;
FIGS. 4A-4D show an allocation scheme for a first variant of the invention, the scheme corresponding to that of FIG. 2;
FIGS. 5A-5D show an allocation scheme for a second variant of the invention, and
FIGS. 6A-6D show an allocation scheme for a third variant of the invention.

DETAILED DESCRIPTION

To simplify the explanation of the invention with the aid of the figures, it will be assumed that each field H1, H2 of the transmitted and received television picture consists of 5 alternately interleaved lines, as shown in FIG. 1. Thus, lines 1 . . . 5 of the field H1 are interleaved with lines 6 . . . 10 of the second field H2 to form the line sequence 1, 6; 2, 7; . . . 5, 10.
FIG. 2 shows an allocation scheme for the writing into and the readout at twice the write-in speed from the frame memory vs (FIG. 3) of the invention. As indicated by the arrow t, the allocation scheme is to be understood as relating to time, i.e., it shows how the individual lines are written into and read from the frame memory vs successively in time. Line a of FIG. 2 shows the "slow" (horizontal-frequency) write-in of the fields B1 and B2 of the frame B. The picture element delayed by the duration of one frame can first be read out and then be replaced by the new picture element plus the movement information. Line b of FIG. 2 shows the readout of the successive field pairs A2/B1, A2/B1, B1/B2, B1/B2 at twice the write-in speed. From this it follows that each of these field pairs can be read out twice, so that 100-Hz frame reproduction is possible. The critical points during readout are marked by curved arrows; the lines 5 and 10, marked by downwardly pointing arrows, must have been written in before they can be read out, and the lines 1 and 6, marked by upwardly pointing arrows, must not be overwritten until they have been read out.
The spaces between the individual fields correspond to the retrace lines, which need not be stored in the frame memory. The times required for write-in and for readout show that the write-in time is precisely twice as long as the readout time. During write-in, therefore, readout on a time-division-multiplex basis, which is necessary for the movement detector bt (FIG. 3), is possible without exceeding the data transfer rate necessary for readout at twice the write-in speed.
FIG. 3 shows a block diagram of an embodiment of the invention. The frame memory vs consists of three memory areas sp1, sp2, and sp3. Associated with these memory areas are the first multiplexer mx1, the second multiplexer mx2, and the third multiplexer mx3, respectively, which are connected to these areas by the first, second, and third bidirectional data buses db1, db2, and db3, respectively. The data transfer on these buses (in blocks) is in only one direction, i.e., although the buses are bidirectional, data communication never takes place in both directions at a time.
The first multiplexer mx1 and the second multiplexer mx2 are also connected to the first and second inputs of the field interpolator ip via the first and second unidirectional data buses eb1 and eb2, respectively. Therefore, the two multiplexers mx1, mx2 are preferably unidirectional multiplexers, whereas the multiplexer mx3 must transmit data in both directions and is therefore connected via the fourth bidirectional data bus db4 to the movement detector bt, which is presented with the digital video signal dv. The output of the field interpolator ip provides the digital flicker-free video signal fv.
The sequence control circuit cc, which is controlled by a clock signal ft from a clock generator (not shown) that also generates further clock signals for the individual digital subcircuits of the television receiver, controls the horizontal-frequency writing into, and the single or double readout at twice the horizontal frequency from, the three memory areas of the frame memory vs. The information of the line, hereinafter referred to as "data word", is compressed to one-half of a line period prior to write-in w; this can be done in a suitable stage of the movement detector bt or in a stage specifically provided for this purpose. This makes it possible to interleave the individual data words in time in the three memory areas sp1, sp2, sp3, as will be explained below with the aid of FIGS. 4 to 6.

The construction of the sequence control circuit cc will be apparent to those skilled in the art from the following description of the time sequence for the writing into and readout from the frame memory vs. In the first variant of the solution according to the invention, the data words of the field H1 of FIG. 1, i.e., those of lines 1 to 5, are divided into two blocks, and those of the second field H2, i.e., those of lines 6 to 10, into two sections. FIGS. 4, 5, and 6 show how these word blocks and word sections are written into and read from the three areas of the frame memory vs serially in time. They show temporal allocation schemes for the three memory areas. In each of the stripes shown in these figures, the top row is allocated to the memory area sp1, the middle row to the memory area sp2, and the bottom row to the memory area sp3.
In FIGS. 4A-D, 5A-D, and 6A-D, the blocks and sections of the data words of the individual lines are not distinguished from one another by reference characters, but the blocks and sections belonging to a line are designated by the number of this line. In the variant of the solution shown in FIG. 4, the first word block of an nth line, where n is an integer of the sequence 1, 4, . . . N/2, were N is the number of frame lines or only the number of lines containing picture information of a frame, is stored in the first memory area sp1, and the second word block of this line in the second memory area sp2; the first word block of line n+1 is stored in the third memory area sp3, and the second word block of this line in the first memory area sp1; the first word block of line n+2 is stored in the second memory area, and the second word block of this line in the 3rd memory area; this takes place during write-in w.
Analogously, as shown in FIG. 4c, the first word section of an mth line, where m is 1+N/2, 4+N/2, . . . N, is stored in the second memory area sp2, and the second word section of this line in the third memory area sp3; the first word section of line m+1 is stored in the first memory area sp1, and the second word section of this line in the second memory area sp2; the first word section of line m+2 is stored in the third memory area sp3, and the second word section of this line in the first memory area sp1. It can be seen that the allocation of the data words of the first field H1 is staggered with respect to that of the second field H2 in the individual memory areas, which is an essential idea of the invention.
During the second half of the duration of three successive lines, e.g., 1, 2, 3; 6, 7, 8, hereinafter referred to as "triple sequence" (the triple sequence thus begins with the mth or nth line), that data word of the respective mth or nth line which was delayed by one frame period is read from the frame memory vs, see portion r in FIGS. 4A-D to 6A-D, and compared with the data word of the mth or nth line in the movement detector bt. During the first half of the duration of the next triple sequence of lines, it is written, together with the movement information, into the memory areas containing the data word delayed by one frame period, thereby replacing this data word. Finally, the first, second, and third word blocks of each data word of the nth line are read out together with the corresponding sections of each data word of the mth line, which is done once or twice at twice the horizontal frequency, as was stated above. FIGS. 4B, 4D, 5B, 5D, 6B, and 6D show schematically the temporal assignment of the sections stemming from the individual lines of the fields. Thus, like word blocks and word sections of corresponding lines belong together, as shown in FIGS. 4B and 4D by the line numbers 1, 6; 7, 2; 2, 7, etc., which are in the same column. From the above-explained distribution of the data words among the individual memory areas, it is apparent that, because of the horizontal-frequency write/read cycle and the doubly fast read cycle, each memory area is needed for only a single data transfer at a time. This has the advantage that the data buses are always uniformly loaded. In addition, as is indicated by the dashed rectangle in FIG. 3, it is possible to integrate the subcircuits arranged within this rectangle in a single integrated circuit ic without encountering any problems with the complexity or the number of external terminals of the integrated circuit.
The four allocation schemes of FIG. 5 apply to a different division of the data words, namely into three blocks and sections per word. As can be seen in FIG. 5a, the serial write-in is effected so that the first word block is stored in the first memory area sp1, the second word block in the second memory area sp2, and the third word block in the third memory area sp3. As shown in FIG. 5c, the first word section is stored in the second memory area sp2, the second word section in the third memory area sp3, and the third word section in the first memory area sp1. As can be seen in FIGS. 5b and 5d, like data-word sections are again arranged one above the other in columns; they are read out at twice the horizontal frequency. Otherwise, the processing in the movement detector bt and the re-storing during the period w are analogous to the operations in the variant of FIG. 4.
FIG. 6 shows the data word allocation scheme for a third variant of the solution according to the invention, in which the data words are divided into four blocks and sections. In this case, the first word block of an nth line is written into the first memory area sp1, the second word block into the second memory area sp2, the third word block into the third memory area sp3, and the fourth word block into the first memory area sp1. The first word block of line n+1 is written into the second memory area sp2, the second word block into the third memory area sp3, the third word block into the first memory area sp1, and the fourth word block into the second memory area sp2. The first word block of line n+2 is written into the third memory area sp3, the second word block into the first memory area sp1, the third word block into the second memory area sp2, and the fourth word block into the third memory area sp3.
The storage of the four word sections of an mth line begins as the first word section is written into the second memory area sp2, the second word section into the third memory area sp3, etc., as shown in FIG. 6c. In this case, too, the other operations are analogous to those in the two other variants of the solution shown in FIGS. 4A-D and 5A-D.
The frame memory vs and the integrated circuit ic can be implemented using any of the integration technologies commonly employed for digital circuits, particularly insulated-gate field-effect transistor technology, i.e., MOS technology. The invention can then cooperate with digital integrated signal-processing circuits for television receivers, which are described in the literature, cf., e.g., "Electronics", Aug. 11, 1981, pp. 97 to 103. In the television receiver according to the invention, the above-mentioned conversion of the video signal derived in the television receiver on the analog side into a digital video signal and the subsequent processing of this signal on the digital side can be performed in the manner described in the foregoing. For this reason, the corresponding subcircuits are not shown in the figures of the accompanying drawings, but it is assumed that the digital video signal dv of FIG. 3 is provided by the prior art subcircuits mentioned above.

A television receiver in which a video signal of an interlaced system is received and converted in field frequency by using field memories (6a) and (6b) and then fed to a picture receiving tube (9). In this case, the picture receiving tube (9) is subjected to a vertical deflection scanning by a vertical synchronizing signal of a constant period and the video signal in each field of the video signal to be supplied to the picture receiving tube (9) is delayed by a predetermined time by controlling, for example, the read-out timings of the field memories (6a) and (6b) to thereby keep an interlace-ratio constant. Consequently, since the respective vertical cycles are equal to one another, even if the parabolic current wave of the vertical cycle for deflection correcting, for example, is superposed on the horizontal deflecting current, the horizontal deflection current waveform is equal in each vertical period so that the jitter can be prevented from being produced at the right and left ends of the picture screen.



1. A television receiver comprising:
scan converter means including field-memory means supplied with an input video signal of an interlaced television signal having a first field rate and a predetermined interlace-ratio, said field memory means including a plurality of one-field memories, memory control means supplying writing and reading signals to said field-memory means where a frequency of said reading signal is greater than a frequency of said writing signal for reading out a plurality of fields at a second field rate greater than said first field rate, and an output terminal for deriving an output video signal;
video display means supplied with said output video signal; and
deflection means including vertical deflection means for vertically deflecting said video display means with a vertical synchronizing signal having a constant period, characterized by timing control means for delaying the reading out of at least two selected ones of said plurality of fields and controlling the timing of said output video signal at a vertical rate such that a picture reproduced on said video display means has an interlace-ratio equal to said predetermined interlace-ratio,.
2. A television receiver according to claim 1, wherein said timing control means is provided in said memory control means and controls the timing of said reading signal. 3. A television receiver according to claim 1, wherein said timing control means is formed as a delay compensation circuit operated at a vertical rate and said delay compensation circuit is inserted between said scan converter means and said video display means. 4. A television receiver according to claim 3, wherein said interlace ratio is 2:1, said second field rate is two times said first field rate, and said delay compensation circuit provides a time delay of one-quarter of a horizontal scanning period. 5. A television receiver according to claim 4, wherein said field memory means comprises first and second one-field memories and said memory control means causes readout of said first one-field memory twice in succession and subsequent read out of said second one-field memory twice in succession. 6. A television receiver according to claim 5, wherein said vertical rate is selected to insert said delay compensation means to delay the second read out of said first one-field memory and to delay the first read out of said second one-field memory. 7. A television receiver according to claim 3, wherein said interlace ratio is 2:1, said second field rate is two times said first field rate, and said delay compensation circuit provides a time delay of one-half of a horizontal scanning period. 8. A television receiver according to claim 1, wherein said interlace ratio is 2:1 and said second field rate is two times said first field rate. 9. A television receiver according to claim 8, wherein said field memory means comprises first and second one-field memories and said memory control means causes read out of said first one-field memory twice in succession and subsequent read out of said second one-field memory twice in succession. 10. A television receiver according to claim 9, wherein said timing control means delays the second read out of said first one-field memory and delays the first read out of said second one-field memory by a fraction of a horizontal scanning period. 11. A television receiver according to claim 10, wherein said fraction consists of one-quarter of a horizontal scanning period. 12. A television receiver according to claim 10, wherein said fraction consists of one-half of a horizontal scanning period.

Description:

TECHNICAL FIELD
The present invention relates to a television receiver which displays a television picture at, for example, a field frequency twice the normal field frequency.
BACKGROUND ART
In the existing television system, a so-called interlaced scanning system is carried out. That is, one picture (frame) is transmitted by two vertical scannings (fields). This interlaced scanning system is considered in order to increase the number of scanning lines as much as possible in a limited frequency band without a flicker being perceived by a viewer.
However, in the CCIR system employed mainly in European countries, the field frequency is 50 Hz. By this frequency, the flicker can not be removed completely and the flicker becomes conspicuous particularly when the brightness of the television picture is high.
Therefore, in the prior art, such a television receiver is proposed that a television picture is displayed at a field frequency twice the normal field frequency. FIG. 1 shows an example thereof.
In the figure, reference numeral 1 designates an antenna, 2 a tuner, 3 a video intermediate frequency amplifier, and 4 a video detecting circuit. The video detecting circuit 4 produces a video signal Sv of the interlaced system of, for example, 625 lines/50 fields and 2:1.
This video signal Sv is converted to a digital signal by an A/D converter 5 and then fed to a converting circuit 6 so as to be converted to a field twice normal speed video signal with the field frequency twice the normal field frequency.
The converting circuit 6 is formed of field memories (random access memories each having a storage capacity sufficient for the picture elements of one field period (1V)) 6a and 6b and switching circuits 6c and 6d. The switching circuit 6c is changed in position to the sides of the memories 6a and 6b at every field period 1V, while the switching circuit 6d is changed in position reversely. The memory selected by the switching circuit 6c is supplied with a write clock pulse having a timing corresponding to the above-described picture elements, while the memory selected by the switching circuit 6d is supplied with a read clock pulse with the frequency twice the frequency of the write clock pulse.
The video signal Sv converted to the digital signal by the A/D converter 5 is supplied through the switching circuit 6c to the memories 6a and 6b by one field each at every field period 1V in which it is written. The video signal of one field amount, which is written in the memories 6b and 6a during a field period 1V just before the above-mentioned field period, is read out therefrom continuously twice with a cycle of 1/2V. This video signal is derived through the switching circuit 6d. In other words, the switching circuit 6d delivers a field twice normal speed video signal Sv' with the field frequency.
This video signal Sv' is converted to an analog signal by a D/A converter 7 and then fed to a signal processing circuit 8. Then, from the signal processing circuit 8, red, green and blue primary color signals R, G and B are produced and then supplied to an image receiving tube 9, respectively.
The video signal Sv derived from the video detecting circuit 4 is supplied to a vertical synchronizing separating circuit 10. A vertical synchronizing signal Pv derived from the separating circuit 10 is multiplied twice by a frequency multiplyer 11 to be a signal with the frequency twice the ordinary frequency. This signal is supplied through a vertical deflecting circuit 12 to a deflecting coil 13.
The video signal Sv' derived from the D/A converter 7 is supplied to a horizontal synchronizing separating circuit 14. A horizontal synchronizing signal P _H ' (having the frequency twice the normal frequency) derived from the separating circuit 14 is supplied through a horizontal deflecting circuit 15 to the deflecting coil 13.
Since the example of the television receiver shown in FIG. 1 is constructed as described above, the primary color signals R, G and B each of which has the field frequency twice the normal field frequency are supplied to the picture receiving tube 9 and the horizontal and vertical deflection scannings are carried out at the scanning speed twice the normal scanning speed, and hence a color picture with the field frequency twice the normal field frequency is displayed on the picture receiving tube 9. Accordingly, also in the above CCIR system, the field frequency becomes 100 Hz which is twice the normal field frequency so that the viewer feels no flicker.
In the case of the example shown in FIG. 1, however, the horizontal synchronization of the video signal Sv' derived from the converting circuit 6 is disturbed cyclically so that a distortion occurs in the upper portion of the picture screen.
That is, the write-in state of the video signal Sv derived from the video detecting circuit 4 in the memories 6a and 6b is expressed as shown in FIG. 2A, in which references F ₁ and F ₂ designate first and second fields, respectively. The video signal Sv' from the converting circuit 6 is expressed as shown in FIG. 2B. In the figure, arrows represent the positions of the vertical synchronizing signals. As will be clear from FIG. 2B, in the video signal Sv', the phase of the horizontal synchronization is displaced by 180° at every two fields, or at every 1/50 seconds (shown by broken line arrows), whereby the synchronization on the upper portion of the picture screen is disturbed, resulting in a picture distortion.
Therefore, the present applicant has proposed a television receiver which is free of such picture distortion and FIG. 3 shows an example thereof. In FIG. 3, like parts corresponding to those of FIG. 1 are marked with the same references.
In the figure, the video signal Sv derived from the video detecting circuit 4 is converted to the digital signal by the A/D converter 5 and then fed to a converting circuit 16 so as to be converted to the field twice normal speed video signal with the frequency twice the normal field frequency.
The converting circuit 16 is formed of field memories (random access memories) 16a and 16b having storage capacities of picture elements of 313 horizontal periods (313H) and 312 horizontal periods (312H) and switching circuits 16c and 16d . The switching circuit 16 is changed in position alternately to the side of the memory 16a during each period of 313H and to the side of the memory 16b during each period of 312H, while the switching circuit 16d is changed in position in the reverse manner. These change-overs of the change-over switches 16c and 16d are controlled by a control circuit 17. This control circuit 17 is supplied with horizontal and vertical synchronizing signals P _H and P _V which are separated from the video signal Sv by a synchronizing separating circuit 18.
The memory selected by the switching circuit 16c is supplied with the write clock pulse having the timing corresponding to the above picture elements, while the memory selected by the switching circuit 16d is supplied with a read clock pulse with the frequency twice the frequency of the write clock pulse.
The video signal Sv converted to the digital signal by the A/D converter 5 is supplied through the switching circuit 16c to the memories 16a and 16b in which it is alternately written during each period of 313H and 312H. FIG. 4A shows the write-in state of the memories 16a and 16b, in which references F ₁ and F ₂ represent the first and second fields, respectively. During the periods of 313H and 312H in which the video signal is being written in one of the memories, the video signal written in the other of the memories 16b and 16a during the periods just before the above 312H and 313H are read out therefrom twice continuously. This signal is derived through the switching circuit 16d as a field twice normal speed video signal Sv*. FIG. 4B shows the video signal Sv* which is derived through the switching circuit 16d, in which the field portions corresponding to those of FIG. 4A are marked with the same references. By the way, due to the difference between the write time and the read time, extra or lack of one line amount per field is produced in the video signal Sv*.
In FIG. 4B, at the portions of, for example, the F ₁ and F ₁ fields (the portions read out from the memory 16a), 313 lines are not read out because of a time relation. Further, at, for example, the F ₂ and F ₂ field portions (the portions read out from the momory 16b), the video signal of one line amount is lacked and during that period, the reading operation is stopped and the video signal of one line amount is missing (shown by one-dot chain lines). The extra and lack of the video signal of one line amount as mentioned above occur in the vertical blanking period so that in practice, this does not disturb the television picture.
The writing in and reading out from the memories 16a and 16b are controlled by the control circuit 17.
The video signal Sv* derived from the switching circuit 16d is converted to the analog signal by the D/A converter 7 and then fed to the signal processing circuit 8. Then, the red, green and blue primary color signals R, G and B are produced from the signal processing circuit 8 and then fed to the picture receiving tube 9, respectively.
The control circuit 17 produces a vertical synchronizing signal Pv* at the timing shown by arrows in FIG. 4B. More particularly, the vertical synchronizing signal Pv* is produced at the beginning of the first F ₁ field, at the timing after 312 lines from the preceding line, namely, at the beginning of the second F ₁ field, at the timing after 311.5 lines from the preceding line, at the timing after 313 lines from the preceding line and at the timing after 313.5 lines from the preceding line, or the beginning of the first F ₁ field, hereinafter similarly. This synchronizing signal Pv* is supplied through the vertical deflecting circuit 12 to the deflecting coil 13 by which the vertical deflection scanning is carried out. When the synchronizing signal Pv* is produced at the above-mentioned timing, in the same F ₁ field and F ₂ field , the scanning lines are formed at the same positions and the scanning lines respectively formed at the F ₁ field and F ₂ field are displaced by 1/2 scanning line spacing each. In other words, the interlaced relation of the video signal Sv is kept as it is.
The video signal Sv* from the D/A converter 7 is supplied to the horizontal synchronizing separating circuit 14. A horizontal synchronizing signal P _H * (having the frequency twice the normal frequency) derived from the separating circuit 14 is supplied through the horizontal deflecting circuit 15 to the deflecting coil 13 by which the horizontal deflection scanning is carried out.
According to the example of the television receiver shown in FIG. 3, the horizontal synchronization of the video signal Sv* becomes continuous as shown in FIG. 4B so that the synchronization can be prevented from being disturbed by the insuccessive horizontal synchronization unlike the example of FIG. 1 and thus no picture distortion is produced.
However, in the example of FIG. 3, since the generation timing of the vertical synchronizing signal Pv* is determined such that the scanning lines of the same F ₁ fields and F ₂ fields are formed at the same positions (see the arrows in FIG. 4B), the vertical cycle is made different very slightly and not becomes exactly 1/100 seconds=10 m sec.
By the way, in the television receiver, in order to correct left and right pincushion distortions, a parabolic wave current with the vertical synchronizing frequency is superposed on the horizontal deflection current. In this case, since the cycle of the vertical synchronizing signal Pv* is different (see FIG. 5A) as mentioned above, also the vertical deflection current becomes correspondingly different (see FIG. 5B). Further, the horizontal deflection current waveform is changed at every vertical cycle (see FIG. 5C). As described above, since the horizontal deflection current waveform is different, a jitter appears in the right and left ends of the picture screen at a fundamental frequency of 25 Hz (four field cycles of F ₁ , F ₁ , F ₂ , and F ₂ ). This jitter becomes conspicuous much if the deflection angle becomes larger.
To remove this jitter, it may be considered to correct the horizontal deflection current waveform by the deflecting system. However, the correction thereof is very difficult and requires a special deflection correcting circuit.
In this case, since the cycle of the vertical synchronizing signal Pv* becomes different (see FIG. 5A), also the vertical deflecting current becomes different at every vertical cycle (see FIG. 5B) but this does not exert so serious bad influence on the picture screen.
DISCLOSURE OF INVENTION
The present invention is to prevent a jitter from being produced at the right and left ends of a picture screen without providing a special deflection correcting circuit. To achieve this object, this invention is to provide a television receiver in which a video signal of the interlaced system is received, its field frequency is converted by using a field memory and then the video signal is fed to a picture receiving tube. In this case, in the picture receiving tube the vertical deflection scanning is performed by the vertical synchronizing signal of a constant cycle and a video signal in each field of the video signal supplied to the picture receiving tube is delayed by a predetermined time so as to keep the interlace-ratio constant.
The television receiver of the present invention is constructed as described above and since each vertical period is equal to one another, the horizontal deflecting current waveforms become equal to one another in each vertical cycle. As a result, the jitter can be prevented from being produced at the right and left ends of the picture screen.
BRIEF DESCRIPTION OF DRAWINGS
FIGS. 1 and 3 are respectively diagrams showing prior art examples, FIGS. 2A, 2B, 4A, 4B, 5A, 5B are respectively diagrams useful for explaining the prior art examples, FIG. 6 is a diagram showing an embodiment of a television receiver according to the present invention, FIGS. 7A, 7B and 8A-8F are respectively diagrams useful for the explanation thereof, FIGS. 9, 10, 12, 13, and 14 are respectively diagrams showing other embodiments of the television receiver according to the present invention, and FIGS. 11A and 11B are diagrams useful for explaining the embodiments of FIGS. 9 and 10.
BEST MODE FOR CARRYING OUT THE INVENTION
An embodiment of the television receiver according to the present invention will hereinafter be described with reference to FIG. 6 In FIG. 6, like parts corresponding to those of FIG. 1 are marked with the same references and the description thereof will be omitted.
In the embodiment of FIG. 6, the change-over of the switching circuits 6c and 6d and the writing-in operation to the memories 6a and 6b are carried out similarly to those of the example shown in FIG. 1 but by virtue of the control of a memory control circuit 19, the reading out timing from the memories 6a and 6b are controlled so that from the switching circuit 6d derived is a field twice normal speed video signal S _VN ' shown in FIG. 7B. That is, one-dot chain lines in FIG. 7B indicate signal-missing portions. In this case, of the first and second F ₁ fields read out from the memory 6a, the second F ₁ field is read out with a delay of 0.25 H (corresponding to 0.5 line), while of the first and second F ₂ fields read out from the memory 6b, the first F ₂ field is read out with a delay of 0.25 H (corresponding to 0.5 line).
This video signal S _VN ' is supplied through the D/A converter 7 to the signal processing circuit 8.
Further, the video signal S _VN ' derived from the D/A converter 7 is supplied to the horizontal synchronizing circuit 14. A horizontal synchronizing signal P _HN ' (having the frequency twice the ordinary frequency) therefrom is supplied through the horizontal synchronizing circuit 15 to the deflecting coil 13.
FIG. 7A shows a write-in state of the memories 6a and 6b, in which arrows indicate the positions of the vertical synchronizing signal PV from the vertical synchronizing separating circuit 10.
Further, arrows in FIG. 7B show the positions of signals which are supplied from the multiplier 11 to the vertical deflecting circuit 12. It is natural that the cycles thereof are equal to one another.
In FIG. 6, reference numeral 20 designates a deflection correcting circuit which corrects, for example, the pincushion distortion and this circuit permits a parabolic wave current of the vertical synchronizing frequency for correcting the pincushion distortion to be superposed upon the horizontal deflection current.
Other circuit elements are arranged similarly to those of the example shown in FIG. 1.
FIG. 8D shows the scanning line arrangement and the field arrangement in the embodiment of FIG. 6. In FIGS. 8A-8F, black circles and white circles respectively indicate scanning lines. In the embodiment of FIG. 6, since the second F ₁ ; field is read out with a delay of 0.25 H, the scanning line in the second F ₂ field is formed at the lower side of the scanning line in the first F ₁ field with a displacement of 1/2 scanning line interval. Further, since the reading of the first F ₂ field is carried out with a delay of 0.25 H, the scanning line in the first F ₂ field is formed at the lower side of the scanning line in the second F ₂ field with a displacement of 1/2 scanning line interval.
Whereas, FIG. 8A shows the scanning line arrangement and the field arrangement formed by the video signal S _V . FIG. 8B shows the like arrangement made by the example of FIG. 1 or 3. Further, FIG. 8C shows the scanning line arrangement and the field arrangement provided for the line multiple speed system in which the two scanning lines by the same signal are continued each. As will be clear from these figures, the synthesis of the first and second F ₁ fields of the example of FIG. 6 is equivalent to the F ₁ field of the line multiple speed system and the synthesis of the first and second F ₂ fields in the example of FIG. 6 becomes equivalent to the F ₂ field of this multiple speed system. In other words, the example of FIG. 6 is equivalent to the case where the scanning order of the signal of the previously proposed line multiple speed system is changed such that the signal of 625 lines/50 fields of the non-interlaced system is converted to the signal of the interlaced system with the 312.5 lines/100 fields and 2:1.
According to the television receiver of the embodiment of FIG. 6, since the cycles of the signal to be supplied to the vertical deflecting circuit 12 are equal, the respective vertical periods become equal to one another. Thus, the horizontal deflecting current waveforms on which the parabolic wave current of the vertical synchronizing frequency for correcting the left and right pincushion distortions are superposed are equal to one another during each vertical period. Thus unlike the example of FIG. 3, there occurs no disadvantage that the jitter is produced at the left and right ends of the picture screen and so on. Further, since the interlace-ratio is kept constant, it is possible to obtain a good picture image. Furthermore, according to the embodiment of FIG. 6, since the reading of the second F ₁ field is carried out with a delay of 0.25 H and the reading of the first F ₂ field is carried out with a delay of 0.25 H, similarly to the example of FIG. 3, the continuity of the horizontal synchronization can be kept and no particular problem is caused.
FIG. 9 is a diagram showing another embodiment of the television receiver according to the present invention. In this figure, like parts corresponding to those of FIGS. 1 and 6 are marked with the same references and will not be described in detail.
In the embodiment of FIG. 9, the read timing from the memories 6a and 6b are not controlled but a delay line is used.
In the embodiment of FIG. 9, the change over of the switching circuits 6c and 6d and the writing in and/or reading out from the memories 6a and 6b are carried out similarly to the example of FIG. 1 so that from the switching circuit 6d, there is derived a field twice normal speed video signal S _V ' as shown in FIG. 2B.
In this embodiment of FIG. 9, the video signal S _V ' converted to the analog signal by the D/A converter 7 is supplied to one fixed contact 21a of a switching circuit 21 and also through a delay line 22 having a delay time of 0.25H (corresponding to 0.5 line) to the other fixed contact 21b thereof. This switching circuit 21 is changed in position to the side of the contact 21a during the first F ₁ field and the second F ₂ field, while it is changed in position to the side of the contact 21b during the second F ₁ ; field and the first F ₂ field of the video signal S _V '. Accordingly, from this switching circuit 21, there is derived the video signal S _VN ' (shown in FIG. 7B) similar to the embodiment of FIG. 6, which then is fed to the signal processing circuit 8.
The video signal S _VN ' from the switching circuit 21 is supplied to the horizontal synchronizing separating circuit 14.
The other elements are arranged similarly to those of the examples of FIGS. 1 and 6.
As a result, also in accordance with the embodiment of FIG. 9, the display similar to that of the embodiment of FIG. 6 can be made and thus similar action and effect can be achieved.
Next, FIG. 10 is a diagram showing other embodiment of the television receiver according to the present invention, in which like parts corresponding to those of FIG. 3 are marked with the same references and will not be described in detail.
In the embodiment of FIG. 10, the change over of the switching circuits 16c and 16d and the write-in operation in the memories 16a and 16b are carried out similarly to those of the embodiment of FIG. 3 but the read timing from the memories 16a and 16b is controlled by the control circuit 17 so that from the switching circuit 16d derived is a field twice the normal speed video signal S _VN * shown in FIG. llB. That is, a one-dot chain line in FIG. llB indicates a signal lacked portion and the first and second F ₂ fields are read out from the memory 16b with a delay of 0.5 H (corresponding to one line).
This video signal S _VN * is supplied through the D/A converter 7 to the signal processing circuit 8.
Further, the video signal S _VN * derived from the D/A converter 7 is supplied to the horizontal synchronizing separating circuit 14. A horizontal synchronizing signal P _HN * (having the frequency twice the normal frequency) therefrom is supplied through the horizontal deflecting circuit 15 to the deflecting coil 13.
FIG. llA shows the write-in state of the memories 16a and 16b , in which the arrows indicate the positions of the vertical synchronizing signal P _V from the synchronizing separating circuit 18.
In the embodiment of FIG. 10, from the control circuit 17, the vertical synchronizing signal P _VN * which is produced at the timing shown by the arrows of FIG. llB is supplied to the vertical deflecting circuit 12. That is, the vertical synchronizing signal P _VN * is produced at the timing of the beginning of the first F ₂ field, at the timing with a delay of 312.5 lines after the preceding timing, at the timing with a delay of 312.5 lines after the preceding timing, at the timing with a delay of 312.5 lines after the preceding timing, and at the timing with a delay of 312.5 lines after the preceding timing, or at the timing of the beginning of the first F ₂ field and at the similar timing hereinafter. In this way, the respective cycles of the vertical synchronizing signal P _VN * in the embodiment of FIG. 10 are equal to one another.
In FIG. 10, reference numeral 20 designates a deflection correcting circuit which is used to correct, for example, the pincushion distortion and this deflection correcting circuit is the same as that used in the embodiment of FIG. 6.
The other circuit elements are formed similar to those of the embodiment of FIG. 3.
FIG. 8E shows the scanning line arrangement and the field arrangement in the embodiment of FIG. 10. In the example of FIG. 11, the timing at which the vertical synchronizing signal P _VN * is produced is exactly the same as mentioned above and the reading of the first and second F ₂ fields is carried out with a delay of 0.5 H so that the scanning line in the first F ₁ field and the scanning line in the first F ₂ field are formed at the same position, the scanning line in the second F ₁ field is formed at the upper side of the scanning line in the first F ₁ field with a displacement of 1/2 scanning line interval, and the scanning line in the second F ₂ field is formed at the lower side of the scanning line of the first F ₂ field by the displacement of 1/2 scanning line interval.
The synthesis of the first and second F ₁ fields of the embodiment of FIG. 10 is equivalent to the F ₁ field of the line multiple speed system (see FIG. 8C), while the synthesis of the first and second F ₂ fields of the embodiment shown in FIG. 10 becomes equivalent to the F ₂ field of the line multiple speed system.
As described above, according to the embodiment of FIG. 10, since the cycles of the vertical synchronizing signal P _VN * supplied to the vertical deflecting circuit 12 are equal to one another, the respective vertical periods become equal to one another and thus there occurs no such disadvantage that the jitter will be produced by the fluctuation of each vertical period. Further, since the interlace-ratio is kept constant, it is possible to obtain the picture of good quality. According to this embodiment, since the reading of the first and second F ₂ fields is carried out with a delay of 0.5 H, the continuity of the horizontal synchronization can be maintained similarly to the example of FIG. 3 and thus no trouble occurs.
FIG. 12 shows another embodiment of the television receiver according to the present invention, in which like parts corresponding to those of FIGS. 3 and 10 are marked with the same references and will not be described in detail.
In the embodiment of FIG. 12, instead of controlling the reading out timing from the memories 16a and 16b, there is used a delay line.
In the embodiment of FIG. 12, the change over of the switching circuits 16c and 16d and the write-in and/or read-out from the memories 16a and 16b are carried out similarly to those of the example of FIG. 3 and from the switching circuit 16d , there is derived a field twice the normal speed video signal Sv* such as shown in FIG. 4B.
Further, in the embodiment of FIG. 12, the video signal Sv* converted to the analog signal by the D/A converter 7 is supplied to one fixed contact 23a of a switching circuit 23 and also through a delay line 24 having a delay amount of 0.5 H (corresponding to one line) to the other fixed contact 23b thereof. This switching circuit 23 is changed in position to the side of the contact 23a during the first and second F ₁ fields of the video signal Sv*, while it is changed in position to the side of the contact 23b during the first and second F ₂ fields of the video signal Sv*. Accordingly, from this change-over switch 23, there is derived a video signal S _VN * (shown in FIG. llB) similar to that of the embodiment of FIG. 10 and this video signal is fed to the signal processing circuit 8.
Further, the video signal S _VN * derived from the switching circuit 23 is supplied to the horizontal synchronizing separating circuit 14.
The other circuit elements are arranged similar to those of the examples of FIGS. 3 and 10.
As a result, also in this embodiment of FIG. 12, the display similar to that of the embodiment of FIG. 10 is made and similar action and effect can be achieved.
In the embodiments of FIGS. 10 and 12, while the vertical deflecting circuit 12 is supplied with the vertical synchronizing signal P _VN * from the control circuit 17, it is possible that instead of the synchronizing signal P _VN * , the vertical synchronizing signal Pv, which is supplied from the synchronizing separating circuit 18, is multiplied by two and then supplied to the vertical deflecting circuit.
FIG. 13 shows another embodiment of the television receiver according to the present invention, in which like parts corresponding to those of FIG. 6 are marked with the same references.
In the embodiment of FIG. 6, the display equivalent to the interlaced system of 312.5 lines/100 fields and 2:1 is carried out so that the flicker on the picture screen can be suppressed and the respective vertical cycles become equal to each other, thus requiring no special deflection correcting circuit. However, if such a construction is employed in which the arrangement of the scanning line as shown in FIG. 8D is used or two scanning lines are continuously formed by the same signal, there occurs a problem that a distortion of step-shape, i.e., a so-called "zig-zag" becomes conspicuous on the inclined portion. This "zig-zag" is described in greater detail in the Japanese patent application (patent application Ser. No. 23998/1983) which was filed by the present applicant.
The embodiment of FIG. 13 is the example for reducing this "zig-zag".
In the figure, the video signal S _VN ' analog signal by the D/A converter 7 is supplied to an adder 26 which forms a predicting circuit 25. This video signal S _VN ' is further supplied through a delay line 27 having a delay amount of 0.5 H (corresponding to one line) to one fixed contact 28a of a switching circuit 28 and the adder 26. Then, in this adder 26, the video signal S _VN ' and the signal, which results from delaying this video signal by 0.5 H, are added to each other and then averaged. This added and averaged signal is supplied to the other fixed contact 28b of the switching circuit 28. This switching circuit 28 is changed in position to the side of contact 28a during the first F ₁ field and the second F ₂ field of the video signal S _VN '. (shown in FIG. 7B), while it is changed in position to the side of the contact 28b during the second F ₁ field and the first F ₂ field of the video signal S _VN '. That is, from the switching circuit 28, there are derived a signal, which results from delaying the video signal S _VN ' by 0.5 H, in the first F ₁ field and the second F ₂ field of the video signal S _VN ' and a signal, which results from adding and averaging the video signal S _VN ' and the signal thereof delayed by 0.5 H, in the second F ₁ field and the first F ₂ field of the video signal S _VN ', respectively.
The signal derived from the switching circuit 28 is supplied to the signal processing circuit 8.
Further, in FIG. 13, a delay line 29 having a delay amount of 0.5 H is connected between the multiplier 11 and the vertical deflecting circuit 12.
The other elements thereof are arranged similar to those of the embodiment shown in FIG. 6.
The scanning line arrangement and the field arrangement in the embodiment of FIG. 13 become as shown in FIG. 8F. As will be clear from this figure, in the embodiment of FIG. 13, the two scanning lines by the same signal are not formed continuously but the interpolation signal is formed by adding and averaging the preceding and following scanning lines so that the above-described so-called "zig-zag" can be alleviated.
FIG. 14 shows another embodiment of the present invention which is a color television receiver. In this case, after the luminance signal Y and the chrominance signal C are separated from each other, there is used the predicting circuit 25 as shown in the embodiment of FIG. 13.
In the figure, the video signal S _VN ' from the converting ing circuit 6 is supplied to a luminance signal/chrominance signal separating circuit 30. The luminance signal Y from this separating circuit 30 is supplied through the predicting circuit 25 and a D/A converter 7Y to a matrix circuit 31. The chrominance signal C from the separating circuit 30 is supplied to a color demodulating circuit 32 and this color demodulating circuit 32 produces, for example, a red color difference signal R-Y and a blue color difference signal B-Y which then are respectively supplied through D/A converters 7R and 7B to the matrix circuit 31. Then, from the matrix circuit 31, there are produced red, green and blue primary color signals R, G and B which are respectively fed to a picture receiving tube (not shown in FIG. 14).
The output from the D/A converter 7Y is supplied to the horizontal synchronizing separating circuit 14.
The other portions are formed similarly to those of the embodiment of FIG. 6.
In this case, although the predicting circuit 25 may be provided in the chrominance signal system, if it is omitted, the color television receiver of this embodiment becomes inexpensive.
As the embodiment in which the predicting circuit 25 is provided, the embodiments of FIGS. 13 and 14 each of which corresponds to the embodiment of FIG. 6 are illustrated. However, it is possible to similarly consider the embodiments which correspond to the embodiments of FIGS. 9, 10 and 12.
While in the above-described embodiments the video signal of the interlaced system having 625 lines/50 fields and 2:1 was described, the present invention is not limited to the above interlaced system video signal but can be similarly applied to the video signal of other interlaced system. Further, while in the above-embodiments, the field frequency is selected to be twice, the present invention is not limited to the above field frequency but can be similarly applied to a case in which the field frequency is converted to be three times, four times, . . .
EFFECT OF THE INVENTION
According to the present invention as mentioned above, since the respective vertical cycles are made equal to one another, the horizontal deflecting current waveform on which, for example, the parabolic wave current of the vertical cycle is superposed becomes equal during each vertical period so that the jitters at the right and left ends of the picture screen are not produced. Accordingly, no such special correcting circuit for removing the jitter is required. Furthermore, according to the present invention, since the interlace-ratio is kept constant, it is possible to obtain a good picture.

The Audio / Sound Processing is based on TDA9870A (PHILIPS)




TDA9870A

Digital TV Sound Processor

(DTVSP)



 1 FEATURES  1.1 Demodulator and decoder section  · Sound IF (SIF) input switch e.g. to select between  terrestrial TV SIF and SAT SIF sources  · SIF AGC with 24 dB control range  · SIF 8-bit Analog-to-Digital Converter (ADC)  · Two-carrier multistandard FM demodulation  (B/G, D/K and M standard)  · Decoding for three analog multi-channel systems  (A2, A2+ and A2*) and satellite sound  · Programmable identification (B/G, D/K and M standard)  and different identification times.  1.2 DSP section  · Digital crossbar switch for all digital signal sources and  destinations  · Control of volume, balance, contour, bass, treble,  pseudo stereo, spatial, bass boost and soft mute  · Plop-free volume control  · Automatic Volume Level (AVL) control  · Adaptive de-emphasis for satellite  · Programmable beeper  · Monitor selection for FM/AM DC values and signals,  with peak detection option  · I2S-bus interface for a feature extension (e.g. Dolby  surround) with matrix, level adjust and mute.  1.3 Analog audio section  · Analog crossbar switch with inputs for mono and stereo  (also applicable as SCART 3 input), SCART 1  input/output, SCART 2 input/output and line output  · User defined full-level/-3 dB scaling for SCART outputs  · Output selection of mono, stereo, dual A/B, dual A or  dual B  · 20 kHz bandwidth for SCART-to-SCART copies  · Standby mode with functionality for SCART copies  · Dual audio Digital-to-Analog Converter (DAC) from DSP  to analog crossbar switch, bandwidth of 15 kHz  · Dual audio ADC from analog inputs to DSP  · Two dual audio DACs for loudspeaker (Main) and  headphone (Auxiliary) outputs; also applicable for  L, R, C and S in the Dolby Pro Logic mode with feature  extension.  2 GENERAL DESCRIPTION  The TDA9870A is a single-chip Digital TV Sound  Processor (DTVSP) for analog multi-channel sound  systems in TV sets and satellite receivers.  2.1 Supported standards  The multistandard/multi-stereo capability of the  TDA9870A is mainly of interest in Europe, but also in  Hong Kong/Peoples Republic of China and South East  Asia. This includes B/G, D/K, I, M and L standard. In other  application areas there exists only subsets of those  standard combinations otherwise only single standards  are transmitted.  M standard is transmitted in Europe by the American  Forces Network (AFN) with European channel spacing  (7 MHz VHF, 8 MHz UHF) and monaural sound.  Korea has a stereo sound system similar to Europe and is  supported by the TDA9870A. Differences include  deviation, modulation contents and identification. It is  based on M standard.  An overview of the supported standards and sound  systems and their key parameters is given in Table 1.  The analog multi-channel sound systems (A2, A2+  and A2*) are 2-Carrier Systems (2CS).


1
 FEATURES
1.1
 Demodulator and decoder section
• Sound IF (SIF) input switch e.g. to select between
terrestrial TV SIF and SAT SIF sources
• SIF AGC with 24 dB control range
• SIF 8-bit Analog-to-Digital Converter (ADC)
• Two-carrier multistandard FM demodulation (B/G, D/K
and M standard)
• Decoding for three analog multi-channel systems (A2,
A2+ and A2*) and satellite sound
• Programmable identification (B/G, D/K and M standard)
and different identification times.
1.2
 DSP section
• Digital crossbar switch for all digital signal sources and
destinations
• Control of volume, balance, contour, bass, treble,
pseudo stereo, spatial, bass boost and soft-mute
• Plop-free volume control
• Automatic Volume Level (AVL) control
• Adaptive de-emphasis for satellite
• Programmable beeper
• Monitor selection for FM/AM DC values and signals,
with peak detection option
• I2S-bus interface for a feature extension (e.g. Dolby
surround) with matrix, level adjust and mute.
1.3
 Analog audio section
• Analog crossbar switch with inputs for mono and stereo
(also applicable as SCART 3 input), SCART 1
input/output, SCART 2 input/output and line output
• User defined full-level/−3 dB scaling for SCART outputs
• Output selection of mono, stereo, dual A/B, dual A or
dual B
• 20 kHz bandwidth for SCART-to-SCART copies
• Standby mode with functionality for SCART copies
• Dual audio Digital-to-Analog Converter (DAC) from DSP
to analog crossbar switch, bandwidth of 15 kHz
• Dual audio ADC from analog inputs to DSP
• Two dual audio DACs for loudspeaker (Main) and
headphone (Auxiliary) outputs; also applicable for
L, R, C and S in the Dolby Pro Logic mode with feature
extension.

2
 GENERAL DESCRIPTION
The TDA9870A is a single-chip Digital TV Sound Processor (DTVSP) for analog multi-channel sound systems in TV sets and satellite receivers.
2.1
 Supported standards
The multistandard/multi-stereo capability of the TDA9870A is mainly of interest in Europe, but also in Hong Kong/Peoples Republic of China and South East Asia. This includes B/G, D/K, I, M and L standard. In other application areas there exists only subsets of those standard combinations otherwise only single standards are transmitted. M standard is transmitted in Europe by the American Forces Network (AFN) with European channel spacing (7 MHz VHF, 8 MHz UHF) and monaural sound. Korea has a stereo sound system similar to Europe and is supported by the TDA9870A. Differences include deviation, modulation contents and identification. It is based on M standard. An overview of the supported standards and sound systems and their key parameters is given in Table 1. The analog multi-channel sound systems (A2, A2+ and A2*) are sometimes also named 2CS (2-Carrier Systems).

6
 FUNCTIONAL DESCRIPTION
6.1
6.1.1
Description of the demodulator and decoder
section
SIF INPUT
Two input pins are provided, SIF1 e.g. for terrestrial TV and SIF2 e.g. for a satellite tuner. For higher SIF signal levels the SIF input can be attenuated with an internally switchable −10 dB resistor divider. As no specific filters are integrated, both inputs have the same specification giving flexibility in application. The selected signal is passed through an AGC circuit and then digitized by an 8-bit ADC operating at 24.576 MHz.
6.1.2

 AGC
The gain of the AGC amplifier is controlled from the ADC output by means of a digital control loop employing hysteresis. The AGC has a fast attack behaviour to prevent ADC overloads and a slow decay behaviour to prevent AGC oscillations. For AM demodulation the AGC must be switched off. When switched off, the control loop is reset and fixed gain settings can be chosen (see Table 14; subaddress 0). The AGC can be controlled via the I2C-bus. Details can be found in the I2C-bus register definitions (see Chapter 10).

6.1.3
 MIXER
The digitized input signal is fed to the mixers, which mix one or both input sound carriers down to zero IF. A 24-bit control word for each carrier sets the required frequency. Access to the mixer control word registers is via the I2C-bus.

6.1.4
 FM AND AM DEMODULATION
An FM or AM input signal is fed via a band-limiting filter to a demodulator that can be used for either FM or AM demodulation. Apart from the standard (fixed) de-emphasis characteristic, an adaptive de-emphasis is available for encoded satellite programs. A stereo decoder recovers the left and right signal channels from the demodulated sound carriers. Both the European and Korean stereo systems are supported.

6.1.5
 FM IDENTIFICATION
The identification of the FM sound mode is performed by AM synchronous demodulation of the pilot signal and narrow-band detection of the identification frequencies. The result is available via the I2C-bus interface. A selection can be made via the I2C-bus for B/G, D/K and M standard and for three different modes that represent different trade-offs between speed and reliability of identification.

6.1.6
 CRYSTAL OSCILLATOR
The crystal oscillator (XO) is illustrated in Fig.8 (see Chapter 12). The circuitry of the XO is fully integrated, only the external 24.576 MHz crystal is needed.

6.1.7
 TEST PINS
Both test pins are active HIGH, in normal operation of the device they are connected to VSSD1. Test functions are for manufacturing tests only and are not available to customers. Without external circuitry these pads are pulled down to LOW level with internal resistors.

6.1.8
 POWER FAIL DETECTOR
The power fail detector monitors the internal power supply for the digital part of the device. If the supply has temporarily been lower than the specified lower limit, the power-on reset bit POR, transmitter register subaddress 0 (see Section 10.4.1), will be set to HIGH. The CLRPOR bit, slave register subaddress 1 (see Section 10.3.2), resets the power-on reset flip-flop to LOW. If this is detected, an initialization of the TDA9870A has to be performed to ensure reliable operation.

6.2.1
 LEVEL SCALING
All input channels to the digital crossbar switch (except for the loudspeaker feedback path) are equipped with a level adjust facility to change the signal level in a range of ±15 dB. It is recommended to scale all input channels to be 15 dB below full scale (−15 dB full scale) under nominal conditions.

6.2.2
 FM (AM) PATH
A high-pass filter suppresses DC offsets from the FM demodulator, due to carrier frequency offsets, and supplies the monitor/peak function with DC values and an unfiltered signal, e.g. for the purpose of carrier detection. The de-emphasis function offers fixed settings for the supported standards (50 μs, 60 μs and 75 μs). An adaptive de-emphasis is available for Wegener-Panda 1 encoded programs. A matrix performs the dematrixing of the A2 stereo, dual and mono signals.

6.2.3
 MONITOR
This function provides data words from a number of locations of the signal processing paths to the I2C-bus interface (2 data bytes). Signal sources include the FM demodulator outputs, most inputs to the digital crossbar switch and the outputs of the ADC. Source selection and data read-out is performed via the I2C-bus. Optionally, the peak value can be measured instead of simply taking samples. The internally stored peak value is reset to zero when the data is read via the I2C-bus. The monitor function may be used, for example, for signal level measurements or carrier detection.

6.2.4
 LOUDSPEAKER (MAIN) CHANNEL
The matrix provides the following functions; forced mono, stereo, channel swap, channel 1, channel 2 and spatial effects. There are fixed coefficient sets for spatial settings of 30%, 40% and 52%. The Automatic Volume Level (AVL) function provides a constant output level of −23 dB full scale for input levels between 0 and −29 dB full scale. There are some fixed decay time constants to choose from, i.e. 2, 4 and 8 s. Pseudo stereo is based on a phase shift in one channel via a 2nd-order all-pass filter. There are fixed coefficient sets to provide 90 degrees phase shift at frequencies of 150, 200 and 300 Hz. Volume is controlled individually for each channel ranging from +24 to −83 dB with 1 dB resolution. There is also a mute position. For the purpose of a simple control software in the microcontroller, the decimal number that is sent as an I2C-bus data byte for volume control is identical to the volume setting in dBs (e.g. the I2C-bus data byte +10 sets the new volume value to +10 dB). Balance can be realized by independent control of the left and right channel volume settings. Contour is adjustable between 0 and +18 dB with 1 dB resolution. This function is linked to the volume setting by means of microcontroller software. Bass is adjustable between +15 and −12 dB with 1 dB resolution and treble is adjustable between ±12 dB with 1 dB resolution. For the purpose of a simple control software in the microcontroller, the decimal number that is sent as an I2C-bus data byte for contour, bass or treble is identical to the new contour, bass or treble setting in dBs (e.g. the I2C-bus data byte +8 sets the new value to +8 dB). Extra bass boost is provided up to 20 dB with 2 dB resolution. The implemented coefficient set serves merely as an example on how to use this filter. The beeper provides tones in a range from approximately 400 Hz to 30 kHz. The frequency can be selected via the I2C-bus. The beeper output signal is added to the loudspeaker and headphone channel signals. The beeper volume is adjustable with respect to full scale between 0 and −93 dB with 3 dB resolution. The beeper is not effected by mute. Soft mute provides a mute ability in addition to volume control with a well defined time (32 ms) after which the soft mute is completed. A smooth fading is achieved by a cosine masking.

6.2.5
 HEADPHONE (AUXILIARY) CHANNEL The matrix provides the following functions; forced mono, stereo, channel swap, channel 1 and channel 2 (or C and S in Dolby Surround Pro Logic mode). Volume is controlled individually for each channel in a range from +24 to −83 dB with 1 dB resolution. There is also a mute position.

 For the purpose of a simple control software in the microcontroller, the decimal number that is sent as an I2C-bus data byte for volume control is identical to the volume setting in dB (e.g. the I2C-bus data byte +10 sets the new volume value to +10 dB). Balance can be realized by independent control of the left and right channel volume settings. Bass is adjustable between +15 and −12 dB with 1 dB resolution and treble is adjustable between ±12 dB with 1 dB resolution. For the purpose of a simple control software in the microcontroller, the decimal number that is sent as an I2C-bus data byte for bass or treble is identical to the new bass or treble setting in dB (e.g. the I2C-bus data byte +8 sets the new value to +8 dB). The beeper provides tones in a range from approximately 400 Hz to 30 kHz. The frequency can be selected via the I2C-bus. The beeper output signal is added to the loudspeaker and headphone channel signals. The beeper volume is adjustable with respect to full scale between 0 and −93 dB with 3 dB resolution. The beeper is not effected by mute. Soft mute provides a mute ability in addition to volume control with a well defined time (32 ms) after which the soft mute is completed. A smooth fading is achieved by a cosine masking.

 6.2.6
 FEATURE INTERFACE The feature interface comprises two I2S-bus input/output ports and a system clock output. Each I2S-bus port is equipped with level adjust facilities that can change the signal level in a range of ±15 dB with 1 dB resolution. Outputs can be disabled to improve EMC performance. The I2S-bus output matrix provides the following functions; forced mono, stereo, channel swap, channel 1 and channel 2. One example of how the feature interface can be used in a TV set is to connect an external Dolby Surround Pro Logic DSP, such as the SAA7710, to the I2S-bus ports. Outputs must be enabled and a suitable master clock signal for the DSP can be taken from pin SYSCLK. A stereo signal from any source will be output on one of the I2S-bus serial data outputs and the four processed signal channels will be entered at both I2S-bus serial data inputs. Left and right could then be output to the power amplifiers via the Main channel, centre and surround via the Auxiliary channel.

 6.2.7
 CHANNEL FROM THE AUDIO ADC The signal level at the output of the ADC can be adjusted in a range of ±15 dB with 1 dB resolution. The audio ADC itself is scaled to a gain of −6 dB.

 6.2.8
 CHANNEL TO THE ANALOG CROSSBAR PATH Level adjust with control positions 0 dB, +3 dB, +6 dB and +9 dB.

 6.2.9
 DIGITAL CROSSBAR SWITCH (see Fig.6) Input channels to the crossbar switch are from the audio ADC, I2S1, I2S2, FM path and from the loudspeaker channel path after matrix and AVL. Output channels comprise loudspeaker, headphone, I2S1, I2S2 and the audio DACs for line output and SCART. The I 2S1 and I2S2 outputs also provide digital outputs from the loudspeaker and headphone channels, but without the beeper signals.

 6.2.10
 GENERAL
There are a number of functions that can provide signal gain, e.g. volume, bass and treble control. Great care has to be taken when using gain with large input signals in order not to exceed the maximum possible signal swing, which would cause severe signal distortion. The nominal signal level of the various signal sources to the digital crossbar switch should be 15 dB below digital full scale (−15 dB full scale). This means that a volume setting of, say, +15 dB would just produce a full scale output signal and not cause clipping, if the signal level is nominal. Sending illegal data patterns via the I2C-bus will not cause any changes of the current setting for the volume, bass, treble, bass boost and level adjust functions.

6.2.11
 EXPERT MODE The TDA9870A provides a special expert mode that gives direct write access to the internal Coefficient RAM (CRAM) of the DSP. It can be used to create user-defined characteristics, such as a tone control with different corner frequencies or special boost/cut characteristics to correct the low-frequency loudspeaker and/or cabinet frequency responses by means of the bass boost filter. However, this mode must be used with great care. More information on the functions of this device, such as the number of coefficients per function, their default values, memory addresses, etc., can be made available on request.
 
STV9381 CLASS-D VERTICAL DEFLECTION AMPLIFIER FOR TV AND MONITOR APPLICATION:

DESCRIPTION
Designed for monitors and TVs, the STV9381 is a
class-D vertical deflection booster assembled in
PDIP20 Package.
It operates with supplies up to +/- 18V, provides
up to 3 App output current to drive the yoke. The
internal flyback generator avoids the need for an
extra power supply.

FUNCTIONAL DESCRIPTION
The STV9381 is a vertical deflection circuit operating in class D. The class D is a modulation method
where the output transistors work in switching mode at high frequency. The output signal is restored by filtering
the output square wave with an external LC filter. The major interest of this IC is the low power dissipation
comparatively to traditional amplifiers operating in class AB, eliminating the need of an heatsink.
Except for the output stage which uses the class D modulation, the circuit operation is similar to the one
of a traditional linear vertical amplifier.
A reference signal (sawtooth) has to be applied to the circuit which can accept a differential or single ended
signal. This sawtooth is amplified and applied as a current to the deflection yoke. This current is measured
by means of a low value resistor. The resulting voltage is used as a feed-back signal to guarantee the
conformity of the yoke current with the reference input signal.
The overvoltage necessary for a fast retrace is obtained with a chemical capacitor charged at the power
supply voltage of the circuit. At the flyback moment this capacitor is connected in series with the output
stage power supply. This method, used for several years with the linear vertical boosters and called “internal
flyback” or “flyback generator”, avoids the need of an additional power supply, while reducing the
flyback duration.
The circuit uses a BCD process that combines Bipolar, CMOS and DMOS devices. DMOS transistors are
used in the output stage due to the absence of second breakdown.




FEATURES

n HIGH EFFICIENCY POWER AMPLIFIER

n NO HEATSINK

n SPLIT SUPPLY

n INTERNAL FLYBACK GENERATOR

n OUTPUT CURRENT UP TO 3 APP

n SUITABLE FOR DC COUPLING

APPLICATION

n FEW EXTERNAL COMPONENTS

n PROTECTION AGAINST LOW Vcc


TDA8145 TV EAST/WEST CORRECTION CIRCUIT FOR SQUARE TUBESDESCRIPTION
The TDA8145 is a monolithic integrated circuit in a
8 pin minidip plastic package designed for use in
the square C.R.T. east-west pin-cushion correction
by driving a diode modulator in TV and monitor
applications.

.LOW DISSIPATION
.SQUARE GENERATOR FOR PARABOLIC
CURRENT SPECIALLY DESIGNED FOR
SQUARE C.R.T. CORRECTION
.EXTERNAL KEYSTONE ADJUSTMENT
(symmetry of the parabola)
.INPUT FOR DYNAMIC FIELD CORRECTION
(beam current change)
.STATIC PICTURE WIDTH ADJUSTMENT
.PULSE-WIDTH MODULATOR
.FINAL STAGE D-CLASS WITH ENERGY
REDELIVERY
.PARASITIC PARABOLA SUPPRESSION,
DURING FLYBACK TIME OF THE
VERTICAL SAWTOOTH

CIRCUIT OPERATION (see the schematic diagram)
A differential amplifier OP1 is driven by a vertical
frequency sawtooth current of ± 33µA which is
produced via an external resistor from the sawtooth
voltage. The non–inverting input of this amplifier is
connected with a reference voltage corresponding
to the DC level of the sawtooth voltage. This DC
voltage should be adjustable for the keystone correction.
The rectified output current of this amplifier
drives the parabola network which provides a parabolic
output current.
This output current produces the corresponding
voltage due to the voltage drop across the external
resistor at pin 7.
If the input is overmodulated (> 40µA) the internal
current is limited to 40µA. This limitation can be
used for suppressing the parasitic parabolic current
generated during the flyback time of the frame
sawtooth.
A comparator OP2 is driven by the parabolic current.
The second input of the comparator is connected
with a horizontal frequency sawtooth
voltage the DC level of which can be changed
the external circuitry for the adjustment of the picture
width.
The horizontal frequency pulse–width modulated
output signal drives the final stage. It consists of
class D push–pull output amplifier that drives, via
an external inductor, the diode modulator.

TEA2261 SWITCH MODE POWER SUPPLY CONTROLLER:


.POSITIVE AND NEGATIVE CURRENT UP TO
1.2A and – 2A
.LOW START-UP CURRENT
.DIRECT DRIVE OF THE POWER TRANSISTOR
.TWO LEVELS TRANSISTOR CURRENT LIMITATION
.DOUBLE PULSE SUPPRESSION
.SOFT-STARTING
.UNDER AND OVERVOLTAGE LOCK-OUT
.AUTOMATIC STAND-BY MODE RECOGNITION
.LARGE POWER RANGE CAPABILITY IN
STAND-BY (Burst mode)
.INTERNAL PWM SIGNAL GENERATOR


DESCRIPTION
The TEA2260/61 is a monolithic integrated circuit
for the use in primary part of an off-line switching
mode power supply.
All functions required for SMPS control under normal
operating,transient or abnormal conditions are
provided.
The capability of working according to the ”masterslave”
concept, or according to the ”primary regulation”
mode makes the TEA2260/61 very flexible
and easy to use. This is particularly true for TV
receivers where the IC provides an attractive and
low cost solution (no need of stand-by auxiliary
power supply).

GENERAL DESCRIPTION
The TEA2260/61 is an off-line switch mode power
supply controller. The synchronization functionand
the specificoperationin stand-bymodemake itwell
adapted to video applications such as TV sets,
VCRs, monitors, etc...
The TEA2260/61 can be used in two types of
architectures :
- Master/slave architecture. In this case, the
TEA2260/61 drives the power transistor according
to the pulse width modulated signals generated
by the secondary located master circuit. A
pulse transformer provides the feedback (see
Figure 1).
- Conventional architecture with linear feedback
signal (feedback sources : optocoupler or transformer
winding) (see Figure 2).
Using the TEA2260/61, the stand-by auxiliary
power supply, often realized with a small but costly
50Hz transformer, is no longer necessary. The
burst mode operation of the TEA2260/61 makes
possible the control of very low output power (down
to less than 1W) with the main power transformer.
When used in a master/slave architecture, the
TEA2260/61and also the power transistor turn-off
can be easily synchronized with the line transformer.
The switching noise cannot disturb the
picture in this case.
As an S.M.P.S.controller, the TEA2260/61features
the following functions :
- Power supply start-up (with soft-start)
- PWM generator
- Direct power transistor drive (+1.2A, -2.0A)
- Safety functions : pulse by pulse current limitation,
output power limitation, over and under voltage
lock-out.
S.M.P.S. OPERATING DESCRIPTION
Starting Mode - Stand By Mode
Power for circuit supply is taken from the mains
through a high value resistor before starting. As
long as VCC of the TEA2260/61 is below VCC start,
the quiescent current is very low (typically 0.7mA)
and the electrolytic capacitor across VCC is linearly
charged. When VCC reaches VCC start (typically
10.3V), the circuit starts, generating output pulses
with a soft-starting. Then the SMPS goes into the
stand-bymode and the output voltage is a percentage
of the nominal output voltage (eg. 80%).
For this the TEA2260/61 contains all the functions
required for primary mode regulation : a fixed frequency
oscillator, a voltage reference, an error
amplifier and a pulse width modulator (PWM).
For transmission of low power with a good efficiency
in stand-by, an automatic burst generation
system is used, in order to avoid audible noise.
Normal Mode (secondary regulation)
The normal operating of the TV set is obtained by
sending to the TEA2260/61regulation pulses generated
by a regulator located in the secondary side
of the power supply.
This architectureuses the ”Master-slave Concept”,
advantages of which are now well-known especially
the very high efficiency in stand-bymode, and
the accurate regulation in normal mode.
Stand-by mode or normal mode are obtained by
supplying or not the secondary regulator. This can
be ordonneredfor exemple by a microprocessor in
relation with the remote control unit.
Regulation pulses are applied to the TEA2260/61
through a small pulse-transformer to the IN input
(Pin 2). This input is sensitive to positive square
pulses. The typical threshold of this input is 0.85V.
The frequency of pulses coming from the secondary
regulator can be lower or higher than the
frequency of the starting oscillator.
The TEA2260/61has no soft-starting system when
it receives pulses from the secondary. The softstarting
has to be located in the secondary regulator.
Due to the principle of the primary regulation,
pulses generated by the starting system automatically
disappear when the voltage delivered by the
SMPS increases.
Stand-by Mode - Normal Mode Transition
During the transition there are simultaneously
pulses coming from the primary and secondary
regulators.
These signals are not synchronizedand some care
has to betaken toensure the safety of theswitching
power transistor.
Avery sure and simple way consist in checking the
transformer demagnetization state.
- A primary pulse is taken in account only if the
transformer is demagnetized after a conduction
of the power transistor required by the secondary
regulator.
- A secondary pulse is taken in account only if the
transformer is demagnetized after a conduction
of the power transistor required by the primary
regulator.
With this arrangement the switching safety area of
the power transistor is respected and there is no
risk of transformer magnetization.
The magnetization state of the transformer is
checked by sensing the voltage across a winding
of the transformer (generally the same which supplies
the TEA2261). This is made by connecting a
resistor between this winding and the demagnetization
sensing input of the circuit (Pin 1).


SECURITY FUNCTIONS OF THE TEA2260 (see flow-chart below)
- Undervoltage detection. This protection works
in association with the starting device ”VCC
switch” (see paragraph Starting-mode - standby
mode). If VCC is lower than VCCstop (typically
7.4V) output pulses are inhibited, in order to avoid
wrong operation of the power supply or bad
power transistor drive.
- Overvoltage detection. If VCC exceedsVCCmax
(typically 15.7V) output pulses are inhibited. Restarting
of the power supply is obtained by reducing
VCC below VCCstop.
- Current limitation of the power transistor. The
current is measured by a shunt resistor. Adouble
threshold system is used :
- When the first threshold (VIM1) is reached, the
conduction of the power transistor is stopped
until the end of the period : a new conduction
signal is needed to obtain conduction again.
- Furthermore as long as the first threshold is
reached (it means during several periods), an
external capacitor C2 is charged. When the
voltage across the capacitor reaches VC2 (typically
2.55V) the output is inhibited.This is called
the ”repetitive overload protection”. If the overload
diseappears before VC2 is reached, C2 is
discharged, so transient overloads are tolerated.
- Second current limitation threshold (VIM2).
When this thresholdis reached the output of the
circuit is immediatly inhibited. This protection is
helpfull in case of hard overload for example to
avoid the magnetization of the transformer.
- Restart of the power supply. After stopping due
to VC2, VIM2, VCCMax or VCCstop triggering, restart
of the power supply can be obtained by the
normal operating of the ”VCC switch” but thanks
to an integrted counter, if normal restart cannot
be obtained after three trials, the circuit is definitively
stopped. In this case it is necessary to
reduce VCC below approximately 5V to reset the
circuit. From a practical point of view, it means
that the power supply has to be temporarily disconnected
from any power source to get the
restart.

 

 VIDEO DIGITAL BOARD  CS1114-1

PRIMUS Powerful Scan-Rate Converter including Multistandard Color Decoder.
1. Introduction
The VSP 94x2A (PRIMUS) is a new component of the
Micronas MEGAVISION® IC set in a CMOS embedded
DRAM technology. The VSP 94x2A comprises all
main functions of a digital featurebox in one monolithic
IC. The number of features is limited in favor of a lowcost
solution, but no trade-off has been made concerning
picture quality.
The family is ideally suited to work in conjunction with
the deflection processors SDA 9380 (9402/32) and
DDP 3315C (9412/42). In combination with the ’digital
TV decoder’ MDE 9500, double-scan iDTV is possible.
The package is upward pin-compatible to other
medium-range and high-end devices of the VSP 94xy
family. A 50/60 Hz derivative is also available (9432,
9442). The device comprises a digital multistandard
color decoder, an RGB interface with fast-blank capability
(SCART), digital ITU656 input, scaling units
including panorama, embedded DRAM for upconversion,
picture improvements, temporal noise reduction,
as well as A/D and D/A converters.

1.1. Features
– Integrated video matrix switch
• Up to seven CVBS inputs, up to two Y/C inputs,
• Three CVBS outputs (Y/C inputs signals are combined
to CVBS output format)
• 9 bit amplitude resolution for CVBS, Y/C A/D converter
• AGC (Automatic Gain Control)
– Multi-standard color decoder
• PAL/NTSC/SECAM including all substandards
• Automatic recognition of chroma standard
• Only one crystal necessary for all standards
– RGB-FBL or YUV-H-V input
• 8 bit amplitude resolution for RGB or YUV
• 8 bit amplitude resolution for FBL or H
– ITU656 support (version dependent, refer to next
chapter)
• ITU656 input/output
• DS656 output (double-scan ‘656-like’ output)
– Letterbox detection
– Noise reduction
• Temporal noise reduction
• Field-based temporal noise reduction for luminance
and chrominance
• Different motion detectors for luminance and
chrominance or identical
• Flexible programming of the temporal noise
reduction parameters
• Automatic measurement of the noise level
– Horizontal scaling of the 1fH signal
• Split-screen possible with additional PiP or Text
processor
– Flexible digital horizontal scaling of the 2fH signal
• Scaling factors: 3, ..., 0.75 including 16:9 compatibility
• 5 zone panorama generator
– Embedded memory
• On-chip memory controller
• Embedded DRAM core for field memory
• SRAM for PAL/SECAM delay line
– Data format 4:2:2
– Flexible clock and synchronization concept
• Horizontal line-locked or free-running mode
• Vertical locked or free-running mode
– Scan-rate-conversion
• Simple interlaced modes (100/120 Hz): AABB,
AAAA, BBBB (9402A/9412A only)
• No scan-rate-conversion modes (50/60 Hz): AB,
AA, BB (9432A/9442A only)
– Flexible output sync controller
• Flexible positioning of the output signal
• Flexible programming of the output sync raster
• ‘Blank signal’ generation
– Signal manipulations
• Still field
• Insertion of colored background
• Windowing
• Vertical chrominance shift for improved VCR picture
quality
– Sharpness improvement
• Digital color transition improvement (DCTI)
• Peaking (luminance)
– Three D/A converters
• 9 bit amplitude resolution for Y, -(R-Y), -(B-Y) output
• 72 MHz clock frequency
• Two-fold oversampling for anti-imaging
• Simplification of external analog postfiltering
– 1920 active pixel/per line in default configuration
– I2C-bus control (400 kHz)
• Selectable I2C address
– 1.8V ±5% and 3.3 V ±5% supply voltages
– PMQFP80-1 package.

---------------------------------------


SDA 9380-B21
EDDC
Enhanced Deflection
Controller and
RGB Processor

















1 General description
The SDA 9380 is a highly integrated deflection controller and RGB video processor for CTV receivers
with 15 to 19kHz or 31 to 38kHz line frequencies. The deflection component controls among others
an horizontal driver circuit for a flyback line output stage, a DC coupled vertical saw-tooth output
stage and an East-West raster correction circuit. All adjustable output parameters are I²C-Bus controlled.
Inputs are HSYNC and VSYNC. The HSYNC signal is the reference for the internal clock
system which includes the=χΝ=and χΟ=control loops.
The RGB processor has two YUV/RGB inputs and one RGB input. One YUV/RGB input and the
RGB input are for SVGA and text/OSD with fast blanking. The RGB output stage has two control
loops for cut off and white level with halt capability in vertical shrink modes. An overall Y output and
an adjustable delay of the RGB outputs related to this signal are suitable for a scan velocity modulation
circuit.
The supply voltages of the IC are 3.3V and 8V. It is mounted in a P-MQFP package with 64 pins.
2 Features
2.1 Deflection
=No external clock needed
=χΝ=PLL and=χΟ=PLL on chip
=Standard line frequencies for NTSC and PAL
= =18.75kHz line frequency for 625 lines/60 Hz
= =Doubled line frequencies for NTSC and PAL, MUSE standard, DTV standard
Also suitable for VGA, Macintosh (35kHz) and SVGA standard (38kHz, 800*600*60Hz)
=Automatic switching between 31, 35 and 38kHz in Monitor mode with 2 digital outputs for
Controlling B+ and 1 analog input to keep watch on it
=I²C-Bus alignment of all deflection parameters
=All EW-, V- and H- functions
=Picture width and picture height EHT compensation
=Dynamic PH EHT compensation (white bar)
=Compensation of H-phase deviation (e.g. caused by white bar)
=Upper/lower EW-corner correction separately adjustable
=Extreme EW-corner correction (coefficient of sixth order) for super flat tubes
=V-angle and V-bow correction
=Two special control items for vertical zoom/shrink and scroll function with absolutely
correct tracking of the E/W and HD-output signals
=No re-adjustment of E/W after changing vertical S-correction and linearity needed
=H-frequent PWM output signal for generating an adjustable vertical frequent parabola or
a constant pulse width, selectable by I²C
=H- and V-blanking time adjustable
=Partial overscan adjustable to hide the cut off control measuring lines in the reduced
scan modes
=Self adaptation of V-frequency / number of lines per field between 192 and 680 for
each possible line frequency
=Selectable Black Switch-Off behaviour via I²C-Bus


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SDA5553

1. Introduction
The Micronas SDA 55xx TV microcontroller is dedicated
to 8 bit applications for TV control and provides
dedicated graphic features designed for modern low
class to mid range TV sets.
The SDA 55xx is a microcontroller and single chip teletext
decoder for decoding World System Teletext data
as well as other data services as Video Programming
System (VPS), Program Delivery Control (PDC), and
Wide Screen Signalling (WSS) data used for PAL plus
transmissions (in line 23). The data slicer and display
part of the SDA 55xx supports a wide range of TV
standards including PAL, NTSC as well as the acquisition
of the above mention data services as VPS, WSS,
PDC, TTX and Closed Caption data.
The slicer combined with its dedicated hardware
stores TTX data in a VBI buffer of 1 kByte. The Microcontroller
firmware available from Micronas performs
all the acquisition tasks (hamming and parity checks,
page search and evaluation of header control bits)
once per field. Additionally, the firmware can provide
high end teletext features like Packet-26-handling,
FLOF, TOP and list page mode. The Application Program
Interface (API) to the user software is optimized
for a minimum SW overhead.
The on-chip display unit used to display teletext data
up to level 1.5 can also be used for customer defined
on-screen displays (OSD). The display generator is
able to handle parallel display attributes, pixel oriented
displays and dynamically re-definable characters
(DRCS).
The SDA 55xx provides also an integrated generalpurpose,
fully 8051-compatible microcontroller with
specific hardware features especially suitable in TV
sets. The microcontroller core has been enhanced to
provide powerful features such as memory banking,
data pointers and additional interrupts, etc.
The internal XRAM consists of up to 16 kBytes. The
microcontroller provides an internal ROM of up to
128 kBytes. ROMless versions can access up to
1 MByte of external RAM and ROM.
The 8-bit microcontroller runs at 33.33 MHz internal
clock. SDA 55xx is realized in 0.25 micron technology
with 2.5 V supply voltage for the core and 3.3 V for the
I/O port pins to make them TTL compatible.
Based on the SDA 55xx microcontroller the MINTS
software package was developed and provides dedicated
device drivers for many Micronas video & audio
products and includes a full blown TV control SW for
the PEPER application chassis. The SDA 55xx is also
supported with powerful design tools like emulators
from Hitex, Kleinhenz, iSystems, the Keil C51 Compiler
and TEDIpro OSD development SW by Tara Systems.
This support provided by Micronas leads to:
– Shorter time to market
– Re-usability of the SW also for future Micronas
products
– Target independent SW development based on
ANSI C.
– Verification and validation of SW before targeting
and improved SW test concept
– Graphical interface design requiring a minimum
effort for OSD programming and TV controlled know
how.
– Complete, modular and open tool chain available
and configurable by customer.
1.1. General Features
– 8051 compatible microcontroller with TV related
special features and advanced OSD display
– Feature selection via special function register
– Simultaneous processing of TTX, VPS, PDC and
WSS (line 23) data
– Supply voltage 2.5 V for core and 3.3 V for ports
– ROM version package PSDIP52-2, PMQFP64-1
– Romless version package PMQFP100-2
– 128 kByte Flash ROM version package PSDIP52-2
1.1.1. External Crystal and Programmable Clock
Speed
– Normal mode 33.33 MHz CPU clock, power save
mode 8.33 MHz
– CPU clock speed selectable via special function
registers.
– Single external 6 MHz crystal, all necessary clock
signals are generated internally by means of PLLs
1.1.2. Microcontroller Features
– 8-bit 8051 instruction set compatible CPU
– Two 16-bit timers
– Watchdog timer
– Capture compare timer for infrared remote control
decoding
– Pulse width modulation unit (2 channels 14 bit,
6 channels 8 bit).

– ADC (4 channels, 8 bit)
– UART
1.1.3. Memory
– Non-multiplexed 8-bit data and 16…20-bit address
bus (ROMless version)
– Memory banking up to 1 MByte (ROMless version)
– Up to 128 kByte on-chip program ROM
– Eight 16-bit data pointer registers (DPTR)
– 256-bytes on-chip processor internal RAM (IRAM)
– 128 bytes extended stack memory
– Display RAM and TXT/VPS/PDC/WSS Data Acquisition
Buffer directly accessible via MOVX command
– Up to 16 kByte on-chip extended RAM (XRAM) consisting
of
• 1 kByte on-chip ACQ buffer RAM (access via
MOVX)
• 1 kByte on-chip extended RAM (XRAM, access via
MOVX) for user software
• 3 kByte display memory
1.1.4. Display Features
– ROM character set supports all east and west European
languages in a single device
– Mosaic graphic character set
– Parallel display attributes
– Single/double width/height of characters
– Variable flash rate
– Programmable screen size
(25 rows × 33 … 64 columns)
– Flexible character matrixes (H x V) 12 x 9 … 16
– Up to 256 dynamically re-definable characters in
standard mode; 1024 dynamically re-definable characters
in enhanced mode
– CLUT with up to 4096 color combinations
– Up to 16 colors per DRCS character
– One out of eight colors for foreground and background
colors for 1-bit DRCS and ROM characters
– Shadowing & contrast reduction
– Pixel by pixel shiftable cursor with up to 4 different
colors
– Support of progressive and 100 Hz double scan
– 3 × 4 bits RGB-DACs on chip
– Free programmable pixel clock from 10 MHz to
32 MHz
– Pixel clock independent from CPU clock
– Multinorm H/V-display synchronization in master or
slave mode
1.1.5. Acquisition Features
– Multistandard digital data slicer
– Parallel multinorm slicing (TTX, VPS, WSS, CC, G+)
– Four different framing codes available
– Data caption only limited by available memory
– Programmable VBI-buffer
– Full channel data slicing supported
– Fully digital signal processing
– Noise measurement and controlled noise compensation
– Attenuation measurement and compensation
– Group delay measurement and compensation
– Exact decoding of echo disturbed signals
1.1.6. Ports
– One 8-bit I/O-port with open drain output and
optional I2C bus emulation support (Port 0)
– Two 8-bit multifunction I/O-ports (Port 1, Port 3)
– One 4-bit port working as digital or analog inputs for
the ADC (Port 2)
– One 2-bit I/O-port with secondary functions (P4.2,
4.3, 4.7)
– One 4-bit I/O-port with secondary function (P4.0,
4.1, 4.4) Not available in PSDIP52-2)