FINLUX TYPE 153 1532 28 CHASSIS 1000 INTERNAL VIEW.

The FINLUX CHASSIS 1000 is developed in 2 boards carrying all functions of the tellye.

Left board - panel all signal processing and controls + teletext.

Bottom board panel all power circuits and deflections + EHT.


CIRCUITS DESCRIPTIONS:




















































FINLUX TYPE 153 1532 28  CHASSIS 1000 Supply is based on TDA4600 (SIEMENS).

Power supply Description based on TDA4601d (SIEMENS)

TDA4601 Operation. * The TDA4601 device is a single in line, 9 pin chip. Its predecessor was the TDA4600 device, the TDA4601 however has improved switching, better protection and cooler running. The (SIEMENS) TDA4601 power supply is a fairly standard parallel chopper switch mode type, which operates on the same basic principle as a line output stage. It is turned on and off by a square wave drive pulse, when switched on energy is stored in the chopper transformer primary winding in the form of a magnetic flux; when the chopper is turned off the magnetic flux collapses, causing a large back emf to be produced. At the secondary side of the chopper transformer this is rectified and smoothed for H.T. supply purposes. The advantage of this type of supply is that the high chopping frequency (20 to 70 KHz according to load) allows the use of relatively small H.T. smoothing capacitors making smoothing easier. Also should the chopper device go short circuit there is no H.T. output. In order to start up the TDA4601 I.C. an initial supply of 9v is required at pin 9, this voltage is sourced via R818 and D805 from the AC side of the bridge rectifier D801, also pin 5 requires a +Ve bias for the internal logic block. (On some sets pin 5 is used for standby switching). Once the power supply is up and running, the voltage on pin 9 is increased to 16v and maintained at this level by D807 and C820 acting as a half wave rectifier and smoothing circuit. PIN DESCRIPTIONS Pin 1 This is a 4v reference produced within the I.C. Pin 2 This pin detects the exact point at which energy stored in the chopper transformer collapses to zero via R824 and R825, and allows Q1 to deliver drive volts to the chopper transistor. It also opens the switch at pin 4 allowing the external capacitor C813 to charge from its external feed resistor R810. Pin 3 H.T. control/feedback via photo coupler D830. The voltage at this pin controls the on time of the chopper transistor and hence the output voltage. Normally it runs at Approximately 2v and regulates H.T. by sensing a proportion of the +4v reference at pin 1, offset by conduction of the photo coupler D830 which acts like a variable resistor. An increase in the conduction of transistor D830 and therefor a reduction of its resistance will cause a corresponding reduction of the positive voltage at Pin 3. A decrease in this voltage will result in a shorter on time for the chopper transistor and therefor a lowering of the output voltage and vice versa, oscillation frequency also varies according to load, the higher the load the lower the frequency etc. should the voltage at pin 3 exceed 2.3v an internal flip flop is triggered causing the chopper drive mark space ratio to extend to 244 (off time) to 1 (on time), the chip is now in over volts trip condition. Pin 4 At this pin a sawtooth waveform is generated which simulates chopper current, it is produced by a time constant network R810 and C813. C813 charges when the chopper is on and is discharged when the chopper is off, by an internal switch strapping pin 4 to the internal +2v reference, see Fig 2. The amplitude of the ramp is proportional to chopper drive. In an overload condition it reaches 4v amplitude at which point chopper drive is reduced to a mark-space ratio of 13 to 1, the chip is then in over current trip. The I.C. can easily withstand a short circuit on the H.T. rail and in such a case the power supply simply squegs quietly. Pin 4 is protected by internal protection components which limit the maximum voltage at this pin to 6.5v. Should a fault occur in either of the time constant components, then the chopper transistor will probably be destroyed. Pin 5 This pin can be used for remote control on/off switching of the power supply, it is normally held at about +7v and will cause the chip to enter standby mode if it falls below 2v. Pin 6 Ground. Pin 7 Chopper switch off pin. This pin clamps the chopper drive voltage to 1.6v in order to switch off the chopper. Pin 8 Chopper base current output drive pin. Pin 9 L.T. pin, approximately 9v under start-up conditions and 16v during normal running, Current consumption of the I.C. is typically 135mA. The voltage at this pin must reach 6.7v in order for the chip to start-up.
MC144111 6–bit D/A converters
CMOS LSI
The MC144110 and MC144111 are low–cost 6–bit D/A converters with serial
interface ports to provide communication with CMOS microprocessors and
microcomputers. The MC144110 contains six static D/A converters; the
MC144111 contains four converters.
Due to a unique feature of these DACs, the user is permitted easy scaling of
the analog outputs of a system. Over a 5 to 15 V supply range, these DACs may
be directly interfaced to CMOS MPUs operating at 5 V.
• Direct R–2R Network Outputs
• Buffered Emitter–Follower Outputs
• Serial Data Input
• Digital Data Output Facilitates Cascading
• Direct Interface to CMOS mP
• Wide Operating Voltage Range: 4.5 to 15 V
• Wide Operating Temperature Range: 0 to 85°C



TDA3505 Video control combination circuit with automatic cut-off control


GENERAL DESCRIPTION
The TDA3505 and TDA3506 are monolithic integrated circuits which perform video control functions in a PAL/SECAM
decoder. The TDA3505 is for negative colour difference signals -(R-Y), -(B-Y) and the TDA3506 is for positive colour
difference signals +(R-Y), +(B-Y).
The required input signals are: luminance and colour difference (negative or positive) and a 3-level sandcastle pulse for
control purposes. Linear RGB signals can be inserted from an external source. RGB output signals are available for
driving the video output stages. The circuits provide automatic cut-off control of the picture tube.
Features
· Capacitive coupling of the colour difference and
luminance input signals with black level clamping in the
input stages
· Linear saturation control acting on the colour difference
signals
· (G-Y) and RGB matrix
· Linear transmission of inserted signals
· Equal black levels for inserted and matrixed signals
· 3 identical channels for the RGB signals
· Linear contrast and brightness controls, operating on
both the inserted and matrixed RGB signals
· Peak beam current limiting input
· Clamping, horizontal and vertical blanking of the three
input signals controlled by a 3-level sandcastle pulse
· 3 DC gain controls for the RGB output signals (white
point adjustment)
· Emitter-follower outputs for driving the RGB output
stages
· Input for automatic cut-off control with compensation for
leakage current of the picture tube

Notes
1. < 110 mA after warm-up.
2. Values are proportional to the supply voltage.
3. When V11-24 < 0,4 V during clamping time - the black levels of the inserted RGB signals are clamped on the black
levels of the internal RGB signals.
When V11-24 > 0,9 V during clamping time - the black levels of the inserted RGB signals are clamped on an internal
DC voltage (correct clamping of the external RGB signals is possible only when they are synchronous with the
sandcastle pulse).
4. When pins 21, 22 and 23 are not connected, an internal bias voltage of 5,5 V is supplied.
5. Automatic cut-off control measurement occurs in the following lines after start of the vertical blanking pulse:
line 20: measurement of leakage current (R + G + B)
line 21: measurement of red cut-off current
line 22: measurement of green cut-off current
line 23: measurement of blue cut-off current
6. Black level of the measured channel is nominal; the other two channels are blanked to ultra-black.
7. All three channels blanked to ultra-black.
The cut-off control cycle occurs when the vertical blanking part of the sandcastle pulse contains more than 3 line
pulses.
The internal blanking continues until the end of the last measured line.
The vertical blanking pulse is not allowed to contain more than 34 line pulses, otherwise another control cycle begins.
8. The sandcastle pulse is compared with three internal thresholds (proportional to VP) and the given levels separate
the various pulses.
9. Blanked to ultra-black (-25%).
10. Pulse duration ³ 3,5 ms.


TV Stereo Decoder with Matrix TDA6600 2
SIEMENSPreliminary Data Bipolar IC
The TDA 6600-2 includes an advanced decoder for the identification signals for the
multichannel TV sound systems according to the dual-carrier system as well as a matrix
switched by the decoder to provide the L-Ft-information.
Features
0 Increased switching reliability and recognition by means of two PLLs for stereo
(117 Hz) and / or dual channel (274 Hz)
0 Separate bandwidth selection for dual-tone (pins 17-18) and stereo (pins 14-15)
0 Separate setting for the PLL time constants for dual-tone (pin 10) and stereo (pin 11)
0 Adjustable cut level for dual-tone (pin 8) and stereo (pin 9)
0 Cross-talk rejection independent of external component accuracy
0 Adjustment to minimal cross-talk level through external DC voltage
0 Suitable for TV sets with a 15625-Hz signal.
Type Ordering Code Package
TDA 6600-2 Q67000-A8210 P-DlP-24
Circuit Description
The circuitry has two functional sections:
Two phase locked loops for generating the required comparison frequencies (54.96
kHz and 54.8 kHz) from the line frequency. The phase detectors of the control loops
operate in a frequency range of 117 Hz and/or 274 Hz.
Four demodulators to evaluate the 54-kHz pilot signal. The capacitors at the mixer
outputs determine the bandwidth (and thus the signal-to-noise ratio) of the pilot tone
recognition.
An evaluation circuitry for decoding "stereo", "dual sound", and "mono" from the mixer
output levels. ln order to assure interference-free operation in case of high noise level
input signals, the individual signals "stereo" and "dual sound" are delayed via an
externally adjustable integrator. The subsequent digital evaluation provides the
information "mono", "dual sound", or "stereo" to the matrix and the 4 level input/output
(to drive the TDA 6200). If this four level input/output is connected to ground externally
(e.g. by the TDA 6200), the decoder will recognize this signal as "forced mono".
A stereo matrix with deemphasis and SCART output switched by the pilot frequency
decoder. The SCART output can be disabled by a MUTE signal (coincidence).


TDA4555 Multistandard decoder.


GENERAL DESCRIPTION
The TDA4555 and TDA4556 are monolithic integrated
multistandard colour decoders for the PAL, SECAM,
NTSC 3,58 MHz and NTSC 4,43 MHz standards. The
difference between the TDA4555 and TDA4556 is the
polarity of the colour difference output signals (B-Y)
and (R-Y).
Features
Chrominance part
· Gain controlled chrominance amplifier for PAL, SECAM
and NTSC
· ACC rectifier circuits (PAL/NTSC, SECAM)
· Burst blanking (PAL) in front of 64 ms glass delay line
· Chrominance output stage for driving the 64 ms glass
delay line (PAL, SECAM)
· Limiter stages for direct and delayed SECAM signal
· SECAM permutator
Demodulator part
· Flyback blanking incorporated in the two synchronous
demodulators (PAL, NTSC)
· PAL switch
· Internal PAL matrix
· Two quadrature demodulators with external reference
tuned circuits (SECAM)
· Internal filtering of residual carrier
· De-emphasis (SECAM)
· Insertion of reference voltages as achromatic value
(SECAM) in the (B-Y) and (R-Y) colour difference output
stages (blanking)
Identification part
· Automatic standard recognition by sequential inquiry
· Delay for colour-on and scanning-on
· Reliable SECAM identification by PAL priority circuit
· Forced switch-on of a standard
· Four switching voltages for chrominance filters, traps
and crystals
· Two identification circuits for PAL/SECAM (H/2) and
NTSC
· PAL/SECAM flip-flop
· SECAM identification mode switch (horizontal, vertical
or combined horizontal and vertical)
· Crystal oscillator with divider stages and PLL circuitry
(PAL, NTSC) for double colour subcarrier frequency
· HUE control (NTSC)
· Service switch.



TDA4560 Colour transient improvement circuit


GENERAL DESCRIPTION
The TDA4560 is a monolithic integrated circuit for colour transient improvement (CTI) and luminance delay line in gyrator
technique in colour television receivers.
Features
· Colour transient improvement for colour difference signals (R-Y) and (B-Y) with transient detecting-, storage- and
switching stages resulting in high transients of colour difference output signals
· A luminance signal path (Y) which substitutes the conventional Y-delay coil with an integrated Y-delay line
· Switchable delay time from 720 ns to 1035 ns in steps of 45 ns
· Output for the option of velocity modulation


FUNCTIONAL DESCRIPTION
The IC consists of two colour difference channels (B-Y) and (R-Y) and a luminance signal path (Y) as shown in Fig.1.
Colour difference channels
The (B-Y) and (R-Y) colour difference channels consist of a buffer amplifier at the input, a switching stage and an output
amplifier. The switching stages, which are controlled by transient detecting stages (differentiators), switch to a value that
has been stored at the beginning of the transients. The differentiating stages get their signal direct from the colour
difference detecting signal (pins 1 and 2). Two parallel storage stages are incorporated in which the colour difference
signals are stored during the transient time of the signal. After a time of about 600 ns they are switched immediately
(transient time of 150 ns) to the outputs. The colour difference channels are not attenuated.
Y-signal path
The Y-signal input (pin 17) is capacitively coupled to an input clamping circuit. Gyrator delay cells provide a maximum
delay of 1035 ns including an additional delay of 45 ns via the fine adjustment switch (S1) at pin 13. Three delay cells
are switched with two interstage switches dependent on the voltage at pin 15. Thus three switchable delay times of
90 ns, 180 ns or 270 ns less than the maximum delay time are available. A tuning compensation circuit ensures accuracy
of delay time despite process tolerances. The Y-signal path has a 7 dB attenuation as a normal Y-delay coil and can
replace this completely. The output is fed to pin 12 via a buffer amplifier. An additional output stage provides a signal of
90 ns less delay at pin 11 for the option of velocity modulation.




TDA4443 MULTISTANDARD VIDEO IF AMPLIFIERDESCRIPTION
The TDA4443 is a Video IF amplifier with standard
switch for multistandard colour or monochromeTV
sets, and VTR’s.

SWITCHING OFF THE IF AMPLIFIER WHEN
OPERATING IN VTR MODE .DEMODULATION OF NEGATIVE OR POSITIVE
IF SIGNALS. THE OUTPUT REMAINS
ON THE SAME POLARITY IN EVERY CASE .IF AGC AUTOMATICALLY ADJUSTED TO
THE ACTUALSTANDARD .TWO AGC POSSIBILITIES FOR B/G MODE :
1. GATED AGC
2. UNGATED AGC ON SYNC. LEVEL AND
CONTROLLED DISCHARGE DEPENDENT
ON THE AVERAGE SIGNAL LEVEL FOR VTR
AND PERI TV APPLICATIONS
FOR STANDARD L : FAST AGC ON PEAK
WHITE BY CONTROLLED DISCHARGE .POSITIVE OR NEGATIVE GATING PULSE .EXTREMELY HIGH INPUT SENSITIVITY .LOW DIFFERENTIAL DISTORTION .CONSTANT INPUT IMPEDANCE .VERY HIGH SUPPLY VOLTAGE REJECTION .FEW EXTERNAL COMPONENTS .LOW IMPEDANCE VIDEO OUTPUT .SMALL TOLERANCES OF THE FIXED VIDEO
SIGNALAMPLITUDE .ADJUSTABLE, DELAYED AGC FOR PNP
TUNERS.

GENERAL DESCRIPTION
This video IF processing circuit integrates the following
functional blocks : .Three symmetrical, very stable, gain controlled
wideband amplifier stages - without feedback
by a quasi-galvanic coupling. .Demodulator controlled by the picture carrier .Video output amplifier with high supply voltage
rejection .Polarity switch for the video output signal .AGC on peak white level .GatedAGC .Discharge control .Delayed tuner AGC .At VTR Reading mode the video output signal
is at ultra white level.



TDA4445A SOUND IF AMPLIFIER


.QUADRATURE INTERCARRIER DEMODULATOR
.VERY HIGH INPUT SENSITIVITY .GOODSIGNALTO NOISE RATIO .FAST AVERAGINGAGC .IF AMPLIFIER CAN BE SWITCHED OFF FOR
VTR MODE .GOODAM SUPPRESSION .OUTPUT SIGNAL STABILIZED AGAINST
SUPPLY VOLTAGE VARIATIONS .VERY FEW EXTERNAL COMPONENTS
DESCRIPTION
TDA4445A:
Sound IF amplifier, with FM processing for quasi
parallel sound system.
TDA4445B:
Sound IF amplifier, with FM processing and AM
demodulator, for multi-standard sound TV appliances.
TDA4445Badditionnal :
Bistandard applications (B/G and L)
No adjustment of the AM demodulator
Low AMdistortion.


GENERAL DESCRIPTION
This circuit includes the following functions : .Three symmetrical and gain controlled wide
band amplifier stages, which are extremely stable
by quasiDC coupling without feedback. .Averaging AGC with discharge control circuit .AGC voltage generator
Quasi parallel sound operation : .High phase accuracy of the carrier signal processing,
independentfrom AM .Linear quadrature demodulator .Sound-IF-amplifier stage with impedance converter
AM-Demodulation (only TDA4445B) : .Carrier controlled demodulator .Audio frequency stage with impedance converter
.Averaging low passAGC.



FINLUX TYPE 153 1532 28  CHASSIS 1000 Description Of The TMS7000/TMS7020/TMS7040/TMS70120/TMS7001/TMS7041

The TMS70X0 devices (TMS7000, TMS7020, TMS7040, and TMS70120) are single chip
8-bit microcomputers containing a CPU, timer, lIO, RAM, and various amounts of on-chip
ROM. The TMS7020 contains the CPU, RAM, timer, and l/O on-chip, and also provides 2K
bytes of on-chip ROM. The TMS7040 offers the same features as the TMS7020 and has an
increased on-chip ROM size of 4K bytes. The TMS7020 offers the same features as the
general family and efficiently handles large programs with 12K bytes of on-chip ROM. The
TMS7000 family member contains the same features of the TMS7020 except itcontains no
on-chip ROM.

The TMS70X1 devices (TMS7001 and TMS7041) contain a flexible on-chip serial port in
addition the CPU, timer, I/0, and on-chip RAM and ROM. The TMS7041 contains 4K bytes of
on-chip ROM, while the TMS7001 has no on-chip ROM.
Each member in the TMS70X0 and TMS70X1 families have 128 bytes of on-chip RAM, and all
have the capability through memory expansion modes, to access up to 64K bytes of address
space. For additional information on the TMS7000 family architecture, refer to Section 2.

Key Features:
Microprogrammable instruction set
Strip Chip Architecture Topology lSCAT) for rapid family expansion
Register-to-register architecture
Family members with 2K, 4K, and 12K bytes of on-chip ROM and ROMless versions
On-chip 8-bit timer/event counter with 5-bit prescale:
— Internal interrupt with automatic reload
— Capture latch
— Second 8-bit timer/event counter with 5-bit prescale and cascade capabilit
(TMS7001 and TMS7041 onlyl
Flexible on-chip serial port (TMS7001 and TMS7041 only)
- Fully software programmable
— Internal or external baud rate generator
— Separate baud rate timer usable as a third timer
— Asynchronous. isosynchronous, or serial modes
— Two multiprocessor communication formats
128-byte RAM register file
Full-feature datalprogram stack
32 TTL-compatible I/O pins:
— 16 bi-directional pins (22 bi-directional pins on TMS7001 and TMS7041)
— 8 output pins
— 8 high-impedance input pins (2 input pins on TMS7001 and TMS7041l
Memory-mapped ports for easy addressing
256-byte peripheral file
Memory expansion capability:
64K byte address space



TDA2541 IF AMPLIFIER WITH DEMODULATOR AND AFC
DESCRIPTION
The TDA2540 and 2541 are IF amplifier and A.M.
demodulator circuits for colour and black and white
televisionreceiversusingPNPorNPNtuners. They
are intended for reception of negative or positive
modulation CCIR standard.
They incorporate the following functions : .Gain controlled amplifier .Synchronous demodulator .White spot inverter .Video preamplifier with noise protection .Switchable AFC .AGC with noise gating .Tuner AGC output (NPN tuner for 2540)-(PNP
tuner for 2541) .VCR switch for video output inhibition (VCR
play back).




 
TDA2578A SYNCHRONIZATION CIRCUITWITH VERTICAL OSCILLATOR AND DRIVER STAGES
GENERAL DESCRIPTION
The TDA2578A separates the.verticaI and horizontal sync pulses from the composite TV video signal
and uses them to synchronize horizontal and vertical oscillators.
Features
O Horizontal sync separator and noise inverter
I Horizontal oscillator
0 Horizontal output stage
O Horizontal phase detector (sync to oscillator)
0 Time constant switch for phase detector (fast time constant during catching)
0 Slow time constant for noise only conditions
0 Time constant externally switchable (e.g. fast for VCR)
0 Inhibit of horizontal phase detector and video transmitter identification circuit during vertical
oscillator flyback
O Second phase detector ((p2) for storage compensation of horizontal deflection stage
I Sandcastle pulse generator (3~levels)
0 Video transmitter identification circuit
I Stabilizer and supply circuit for starting the horizontal oscillator and output stage directly from the
mains rectifier
0 Duty factor of horizontal output pulse is 50% when flyback pulse is absent
O Vertical sync separator
0 Bandgap 6,5 V reference voltage for vertical oscillator and comparator
0 Synchronized vertical oscillator/sawtooth generator
(synchronization inhibited when no video transmitter is detected)
0 Internal circuit for 6% parabolic pre-correction of the oscillator/sawtooth generator. Comparator
supplied with pre-corrected sawtooth and external feedback input
O Vertical driver stage
I Vertical blanking pulse generator
O 50/60 Hz detector
0 50/60 Hz identification output
I Automatic amplitude adjustment for 60 Hz
0 Automatic adjustment of blanking pulse duration
(50 Hz: 21 lines; 60 Hz:17Iines)
O Vertical guard curcuit
QUICK REFERENCE DATA
_i_i____.
Supply
Minimum current required to start horizontal
oscillator and output stage (pin 16) I15 > 4,5 mA
Main supply voltage (pin 10) Vp = V10_9 typ. I2 V
Supply current lp = I19 typ. 55 mA
Input signals
Sync pulse input voltage (peak-to-peak value; negative-going) V5_9(p_p) 0,15 to I V
Output signals
Horizontal output pulse (open collector) at I11 = 40 mA V11_9 < 0,5 V
Vertical output pulse (emitter-follower) at I1 = I0 mA V1_9 > 4 V

APPLICATION INFORMATION
The TDA2578A generates the signal for driving the horizontal deflection output circuit. lt also contains
a synchronized vertical sawtooth generator for direct drive of the vertical deflection output stage.
The horizontal oscillator and output stage can start operating on a very low supply current (I16 > 4,5 mA),
which can be taken directly from the mains rectifier. Therefore, it is possible to derive the main supply
(pin 10) from the horizontal deflection output stage. The duty factor of the horizontal output signal
is about 65% during the starting-up procedure. After starting-up, the second phase detector (tp2) is
activated to control the timing of the positive-going edge of the horizontal output signal.
A bandgap reference voltage (6,5 V) is provided for supply and reference of the vertical oscillator and
comparator stage. *
The slicing level of the horizontal sync separator is independent of the amplitude of the sync pulse at
the input. The resistor between pins 6 and 7 determines its value. A 4,7 kS2 resistor gives a slicing level
at the middle of the sync pulse. The nominal top sync level at the input is 3,1 V. The amplitude
selective noise inverter is activated at a level of 0,7 V.
Good stability is obtained by means of the two control loops. In the first loop, the phase of the
horizontal sync signal is compared with a waveform of which the rising edge refers to the top of the
horizontal oscillator signal. ln the second loop, the phase of the flyback pulse is compared with
another reference waveform, the timing of which is such that the top of the flyback pulse is situated
symmetrically on the horizontal blanking internal of the video signal. Therefore the first loop can be
designed for a good noise immunity, whereas the second loop can be as fast as desired for compensation
of switch-off delays in the horizontal output stage.
The first phase detector is gated with a pulse derived from the horizontal oscillator signal. This gating
(slow time constant) is switched off during catching. Also, the output current of the phase detector
is increased fivefold, during the catching time and VCR conditions (fast time constant). The first phase
detector is inhibited during the retrace time of the vertical oscillator.
The in-sync, out-of-sync or no video condition is detected by the video transmitter identification/coin-
cidence detector circuit (pin 18). The voltage on pin 18 defines the time constant and gating of the
first phase detector. The relationship between this voltage and the various switching levels is shown in
Fig. 3. The complete survey of the switching actions is given in Table 1.
Table 1 Switching levels at pin 18. ' -
voltage at first phase detector np1 I mute output receiving conditions
E
7,5 V X X X video signal detected
7,5 to 3,5 V X X X video signal detected
3,5 to 1,2 V X X X video signal detected
1,2 to 0,1 V X X X noise only
0,1 to 1,7 V X * X * X new video signal detected
1,7 to 5,0 V X X X horizontal oscillator locked
VCR playback with mute function
5,0 to 7,5 V X X X horizontal oscillator locked
8,7 V X X X VCR playback without mute function
Where: * = 3 vertical periods.

The stability of displayed video information (e.g. channel number), during noise only conditions, is
improved by the first phase detector time constant being set to slow.
The average voltage level of the video input on pin 5 during noise only conditions should not exceed
5,5 V otherwise the time constant switch may be set to fast due to the average voltage level on pin I8
dropping below 0,1 V. When the voltage on pin 18 drops below I00 mV a counter is activated which
sets the time constant switch to fast, and not gated for 3 vertical periods. This condition occurs when
a new video signal is present at pin 5. When the horizontal oscillator is locked the voltage on pin I8
increases. Nominally a level of 5 V is reached within 15 ms (I vertical period). The mute switching
level of 1,2 V is reached within 5 ms (C18 = 47 nF). If the video transmitter identification circuit is
required to operate under VCR playback conditions the first phase detector can be set to fast by
connecting a resistor of I80 kS2 between pin I8 and ground (see Fig. 7).
The supply for the horizontal oscillator (pin 15) and horizontal output stage (pin II) is derived from
the voltage at pin 16 during the start condition. The horizontal output signal starts at a nominal
supply current into pin 16 of 4,2 mA, which will result in a supply voltage of about 5,5 V (for
guaranteed operation of all devices I16 > 4,5 mA). lt is possible that the main supply voltage at pin 10
is O V during starting, so the main supply of the lC can be taken from the horizontal deflection output
stage. The start of the other lC functions depends on the value of the main supply voltage at pin IO.
At 5,5 V all IC functions start operating except the second phase detector (oscillator to flyback pulse).
The output voltage of the second phase detector at pin 14 is clamped by means of an internally
loaded n-p-n emitter follower. This ensures that the duty factor of the horizontal output signal (pin 11)
remains at about 65%. The second phase detector will close if the supply voltage at pin 10 reaches
8,8 V. At this value the supply current for the horizontal oscillator and output stage is delivered by
pin IO, which also causes the voltage at pin 16 to change to a stabilized 8,7 V. This change switches
off the n-p-n emitter follower at pin 14 and activates the second phase detector. The supply voltage
for the horizontal oscillator will, however, still be referred to the stabilized voltage at pin I6, and the
duty factor of the output signal at pin I2 is at the value required by the delay at the horizontal
deflection stage. Thus switch-off delays in the horizontal output stage are compensated. When no
horizontal flyback signal is detected the duty factor of the horizontal output signal is 50%.
Horizontal picture shift is possible by externally charging or discharging the 47 nF capacitor connected
to pin I4.
The IC also contains a synchronized vertical oscillator/sawtooth generator. The oscillator signal is
connected to the internal comparator (the other side of which is connected to pin 2), via an inverter
and amplitude divider stage. The output of the comparator drives an emitter-follower output stage at
pin I. For a linear sawtooth in the oscillator, the load resistor at pin 3 should be connected to a voltage
source of 26 V or higher. The sawtooth amplitude is not influenced by the main supply at pin 10.
The feedback signal is applied to pin 2 and compared to the sawtooth signal at pin 3. For an economical
feedback circuit with less picture bounce the sawtooth signal is internally pre-corrected by 6% (convex)
referred to pin 2. The linearity of the vertical deflection current depends upon the oscillator signal at
pin 3 and the feedback signal at pin 2.
Synchronization of the vertical oscillator is inhibited when the mute output is present at pin 13.
To minimize the influence of the horizontal part on the vertical part a 6,7 V bandgap reference source
is provided for supply and reference of the vertical oscillator and comparator.
The sandcastle pulse, generated at pin 17, has three different voltage levels. The highest level (ll V) can
be used for burst gating and black level clamping. The second level (4,6 V) is obtained from the
horizontal flyback pulse at pin 12 and used for horizontal blanking. The third level (2,5 V) is used for
vertical blanking and is derived by counting the horizontal frequency pulses. For 50 Hz the blanking
pulse duration is 21 lines and for 60 Hz it is 17 lines. The blanking pulse duration and sawtooth
amplitude is automatically adjusted via the 50/60 Hz detector.


TDA3654 TDA3654Q Vertical deflection and guard circuit (110°)


GENERAL DESCRIPTION
The TDA3654 is a full performance vertical deflection output circuit for direct drive of the deflection coils and can be used
for a wide range of 90° and 110° deflection systems.
A guard circuit is provided which blanks the picture tube screen in the absence of deflection current.
Features
· Direct drive to the deflection coils
· 90° and 110° deflection system
· Internal blanking guard circuit
· Internal voltage stabilizer.

FUNCTIONAL DESCRIPTION
Output stage and protection circuits
The output stage consists of two Darlington configurations in class B arrangement.
Each output transistor can deliver 1,5 A maximum and the VCEO is 60 V.
Protection of the output stage is such that the operation of the transistors remains well within the SOAR area in all
circumstances at the output pin, (pin 5). This is obtained by the cooperation of the thermal protection circuit, the
current-voltage detector and the short circuit protection.
Special measures in the internal circuit layout give the output transistors extra solidity, this is illustrated in Fig.5 where
typical SOAR curves of the lower output transistor are given. The same curves also apply for the upper output device.
The supply for the output stage is fed to pin 6 and the output stage ground is connected to pin 4.
Driver and switching circuit
Pin 1 is the input for the driver of the output stage. The signal at pin 1 is also applied to pin 3 which is the input of a
switching circuit (pin 1 and 3 are connected via external resistors).
This switching circuit rapidly turns off the lower output stage when the flyback starts and it, therefore, allows a quick start
of the flyback generator. The maximum required input signal for the maximum output current peak-to-peak value of 3 A
is only 3 V, the sum of the currents in pins 1 and 3 is then maximum 1 mA.
Flyback generator
During scan, the capacitor between pins 6 and 8 is charged to a level which is dependent on the value of the resistor at
pin 8 When the flyback starts and the voltage at the output pin (pin 5) exceeds the supply voltage, the flyback generator is
activated.

The supply voltage is then connected in series, via pin 8, with the voltage across the capacitor during the flyback period.
This implies that during scan the supply voltage can be reduced to the required scan voltage plus saturation voltage of
the output transistors.
The amplitude of the flyback voltage can be chosen by changing the value of the external resistor at pin 8.
It should be noted that the application is chosen such that the lowest voltage at pin 8 is > 1,5 V, during normal operation.
Guard circuit
When there is no deflection current, for any reason, the voltage at pin 8 becomes less than 1 V, the guard circuit will
produce a d.c. voltage at pin 7. This voltage can be used to blank the picture tube, so that the screen will not burn in.
Voltage stabilizer
The internal voltage stabilizer provides a stabilized supply of 6 V to drive the output stage, so the drive current is not
affected by supply voltage variations.