LENOIR KHB8114TX CHASSIS 190-931323-P1 031298 INTERNAL VIEW

 The chassis is manily based around PHILIPS semiconductors and the PHILIPS TDA8361.

TDA3653B
TDA4665
TDA1013B
SEC916
ML7805A
SAA5290PS/082
ML7808A
ATMEL 948

LENOIR  KHB8114TX  CHASSIS  190-931323-P1 031298  Self-oscillation type switching power supply unit:
 A switching transistor is connected to a primary winding of a transformer, an oscillation frequency control circuit is connected to a feedback winding, the oscillation frequency control circuit controls a first controlling transistor, and the first controlling transistor controls the delay time when the switching transistor is turned on. The oscillation frequency control circuit is set in a first operation mode in which the above delay does not take place at the rated load, in a second operation mode in which the oscillation frequency is controlled such that the oscillation frequency becomes constant or slowly decreases at light loading and in a third operation mode in which the oscillation frequency is further decreased while a switch is switched on.


1. A self-oscillation type switching power supply unit comprising: a transformer having a primary winding, a secondary winding, and a feedback winding; a switching transistor which self-oscillates by receiving a feedback signal from the feedback winding and which switches flow of current in the primary winding between an OFF period and an ON period; a rectifying and smoothing circuit connected to the secondary winding; and an oscillation frequency control circuit for extending an OFF period of the switching transistor by preventing the switching transistor from turning on for a predetermined period after the switching transistor has been turned off such that a control signal to be input to the switching transistor is controlled; wherein, at a rated load exceeding a predetermined current, the oscillation frequency control circuit is set in a first operation mode in which a normal ringing choke converter operation is performed to lower the oscillation frequency as the loading becomes heavier; wherein, at light loading in which the load current is the predetermined current or less, the oscillation frequency control circuit is set in a second operation mode in which the OFF period is extended so that the oscillation frequency is constant or slowly decreases as the load current is reduced; and wherein the oscillation frequency control circuit includes a switch for setting in a third operation mode in which, when the switch is in a fixed state, the oscillation frequency is lowered further than in the second operation mode.

2. The self-oscillation type switching power supply unit of claim 1, wherein the oscillation frequency control circuit comprises a capacitor which is charged while the switching transistor is turned on and is discharged while the switching transistor is turned off, a first controlling transistor for preventing the switching transistor from turning on until the voltage of the capacitor reaches a predetermined voltage at which time the capacitor is discharged, and a second controlling transistor for keeping the first controlling transistor turned off while the switching transistor is turned on, and wherein, the switch maintains the predetermined voltage of the capacitor lower during the fixed state.

3. The self-oscillation type switching power supply unit of claim 2, wherein, when the switch is turned on, said capacitor begins to discharge at a lower predetermined voltage.

4. The self-oscillation type switching power supply unit of claim 3, further comprising a first Zener diode coupled in a discharge path of the capacitor, and further comprising a second Zener diode coupled in series with the switch, the second Zener diode having a lower Zener voltage and said switch and second Zener diode being coupled in parallel with the first Zener diode.

5. The self-oscillation type switching power supply unit of claim 1, wherein the oscillation frequency control circuit comprises a capacitor which is charged while the switching transistor is turned on and is discharged while the switching transistor is turned off, a first controlling transistor for preventing the switching transistor from turning on until the voltage of the capacitor reaches a fixed voltage at which time the capacitor is discharged, a second controlling transistor for keeping the first controlling transistor turned off while the switching transistor is turned on, and a discharge circuit in which the capacitor is discharged by applying the charged voltage of the capacitor to the control terminal of the switching transistor, wherein, the switch is provided in the discharge circuit, and wherein an amount of discharged current from the capacitor is decreased when the switch is in the fixed state.

6. The self-oscillation type switching power supply unit of claim 5, wherein the discharge circuit comprises a first resistance coupled in series with a diode to said capacitor and a second resistance coupled in series with the switch, the switch and second resistance being coupled in parallel to the first resistance.

7. The self-oscillation type switching power supply unit of claim 6, wherein the fixed state is when the switch is open.

8. The self-oscillation type switching power supply unit of claim 1, wherein the switch is switched on and off by an external signal.

9. The self-oscillation type switching power supply unit of claim 1, further comprising: a load detector for detecting the magnitude of the load and a switching circuit for switching the switch such that the oscillation frequency control circuit is set in the third operation mode after a predetermined period when the load detector has detected light loading.

10. The self-oscillation type swit

11. The self-oscillation type switching power supply unit of claim 9, wherein the load detector is coupled to a photo coupler for controlling the switch.

12. The self-oscillation type switching power supply unit of claim 9, wherein the load detector comprises first and second comparators, the first comparator detecting whether output current is light or at rated load and the second comparator determining whether to cause said switch to enter the fixed state and the third operation mode to be set.

13. The self-oscillation type switching power supply unit of claim 12, wherein the second comparator includes a delay circuit whereby the third operation mode is entered from the first operation mode after a time delay.

14. The self-oscillation type switching power supply unit of clam 13, wherein the second comparator responds so that the third operation mode changes to the first operation mode substantially without delay.

ching power supply unit of claim 8, wherein the external signal controls the switch via a photo coupler.

Description:

BACKGROUND OF THE INVENTION

1. Field of the Invention
The present invention relates to a self-oscillation type switching power supply unit.

LENOIR  KHB8114TX  CHASSIS  190-931323-P1 031298 TDA8361 Integrated PAL and PAL/NTSC TV processor

GENERAL DESCRIPTION
The TDA8360, TDA8361 and
TDA8362 are single-chip TV
processors which contain nearly all
small signal functions that are
required for a colour television
receiver. For a complete receiver the
following circuits need to be added:
a base-band delay line (TDA4661),
a tuner and output stages for audio,
video and horizontal and vertical
deflection.
Because of the different functional
contents of the ICs the set maker can
make the optimum choice depending
on the requirements for the receiver.
The TDA8360 is intended for simple
PAL receivers (all PAL standards,
including PAL-N and PAL-M are
possible).
The TDA8361 contains a PAL/NTSC
decoder and has an A/V switch.
For real multistandard applications
the TDA8362 is available. In addition
to the extra functions which are
available in the TDA8361, the
TDA8362 can handle signals with
positive modulation and it supplies
the signals which are required for the
SECAM decoder TDA8395.

FUNCTIONAL DESCRIPTION
Video IF amplifier
The IF amplifier contains
3 AC-coupled control stages with a
total gain control range of greater
than 60 dB. The sensitivity of the
circuit is comparable with that of
modern IF ICs.



The reference carrier for the video
demodulator is obtained by means of
passive regeneration of the picture
carrier. The external reference tuned
circuit is the only remaining
adjustment of the IC.
In the TDA8362 the polarity of the
demodulator can be switched so that
the circuit is suitable for both positive
and negative modulated signals.
The AFC circuit is driven with the
same reference signal as the video
demodulator. To ensure that the
video content does not disturb the
AFC operation a sample-and-hold
circuit is incorporated; the capacitor
for this function is internal. The AFC
output voltage is 6 V.
The AGC detector operates on levels,
top sync for negative modulated and
top white for positive modulated
signals.The AGC detector time
constant capacitor is connected
externally. This is mainly because of
the flexibility of the application.
The time constant of the AGC system
during positive modulation
(TDA8362) is slow, this is to avoid any
visible picture variations. This,
however, causes the system to react
very slowly to sudden changes in the
input signal amplitude.
To overcome this problem a speed-up
circuit has been included which
detects whether the AGC detector is
activated every frame period. If,
during a 3-frame period, no action is
detected the speed of the system is
increased. When the incoming signal
has no peak white information (e.g.
test lines in the vertical retrace period)
the gain would be video signal
dependent. To avoid this effect the
circuit also contains a black level
AGC detector which is activated when
the black level of the video signal
exceeds a certain level.
The TDA8361 and TDA8362 contain
a video identification circuit which is
independent of the synchronization
circuit. Therefore search tuning is
possible when the display section of
the receiver is used as a monitor. In
the TDA8360 this circuit is only used
for stable OSD at no signal input. In
the normal television mode the
identification output is connected to
the coincidence detector, this applies
to all three devices. The identification
output voltage is LOW when no
transmitter is identified. In this
condition the sound demodulator is
switched off (mute function). When a
transmitter is identified the output
voltage is HIGH. The voltage level is
dependent on the frequency of the
incoming chrominance signal.

Sound circuit
The sound bandpass and trap filters
have to be connected externally. The
filtered intercarrier signal is fed to a
limiter circuit and is demodulated by
means of a PLL demodulator. The
PLL circuit tunes itself automatically
to the incoming signal, consequently,
no adjustment is required.
The volume is DC controlled. The
composite audio output signal has an
amplitude of 700 mV RMS at a
volume control setting of -6 dB. The
de-emphasis capacitor has to be
connected externally. The
non-controlled audio signal can be
obtained from this pin via a buffer
stage. The amplitude of this signal is
350 mV RMS.
The TDA8361 and TDA8362 external
audio input signal must have an
amplitude of 350 mV RMS. The
audio/video switch is controlled via
the chrominance input pin.
Synchronization circuit
The sync separator is preceded by a
voltage controlled amplifier which
adjusts the sync pulse amplitude to a
fixed level. The sync pulses are then
fed to the slicing stage (separator)
which operates at 50% of the
amplitude.
The separated sync pulses are fed to
the first phase detector and to the
coincidence detector. The
coincidence detector is used for
transmitter identification and to detect
whether the line oscillator is
synchronized. When the circuit is not
synchronized the voltage on the
peaking control pin (pin 14) is LOW
so that this condition can be detected
externally. The first PLL has a very
high static steepness, this ensures
that the phase of the picture is
independent of the line frequency.
The line oscillator operates at twice
the line frequency.
The oscillator network is internal.
Because of the spread of internal
components an automatic adjustment
circuit has been added to the IC.
The circuit compares the oscillator
frequency with that of the crystal
oscillator in the colour decoder. This
results in a free-running frequency
which deviates less than 2% from the
typical value.
The circuit employs a second control
loop to generate the drive pulses for
the horizontal driver stage.
X-ray protection can be realised by
switching the pin of the second
control loop to the positive supply line.
The detection circuit must be
connected externally. When the X-ray
protection is active the horizontal
output voltage is switched to a high
level. When the voltage on this pin
returns to its normal level the
horizontal output is released again.
The IC contains a start-up circuit for
the horizontal oscillator. When this
feature is required a current of 6.5 mA
has to be supplied to pin 36. For an
application without start-up both
supply pins (10 and 36) must be
connected to the 8 V supply line.
The drive signal for the vertical ramp
generator is generated by means of a
divider circuit. The RC network for the
ramp generator is external.
Integrated video filters
The circuit contains a chrominance
bandpass and trap circuit. The filters
are realised by means of gyrator
circuits and are automatically tuned
by comparing the tuning frequency
with the crystal frequency of the
decoder.
In the TDA8361 and TDA8362 the
chrominance trap is active only when
the separate chrominance input pin is
connected to ground or to the positive
supply voltage and when a colour
signal is recognized.
When the pin is left open-circuit the
trap is switched off so that the circuit
can also be used for S-VHS
applications.
The luminance delay line and the
delay for the peaking circuit are also
realised by means of gyrator circuits.
Colour decoder
The colour decoder in the various ICs
contains an alignment-free crystal
oscillator, a colour killer circuit and
colour difference demodulators.
The 90° phase shift for the reference
signal is achieved internally. Because
the main differences of the 3 ICs are
found in the colour decoder the
various types will be discussed.




TDA8361
This IC contains an automatic
PAL/NTSC decoder. The conditions
for connecting the reference crystals
are the same as for the TDA8360.
The decoder can be forced to PAL
when the hue control pin is connected
to the positive supply voltage via a
5 kW or 10 kW resistor
(approximately). The decoder cannot
be forced to the NTSC standard. It is
also possible to see if a colour signal
is recognized via the saturation pin.
TDA8362
In addition to the possibilities of the
TDA8361, the TDA8362 can
co-operate with the SECAM add-on
decoder TDA8395.
The communication between the two
ICs is achieved via pin 32. The
TDA8362 supplies the reference
signal (4.43 MHz) for the calibration
system of the TDA8395, identification
of the colour standard is via the same
connection. When a SECAM signal is
detected by the TDA8395 the IC will
draw a current of 150 mA. When
TDA8362 has not identified a colour
signal in this condition it will go into
the SECAM mode, that means it will
switch off the R-Y and B-Y outputs
and increase the voltage level on PIN 32.


RGB output circuit
The colour difference signals are
matrixed with the luminance signal to
obtain the RGB signals. Linear
amplifiers have been chosen for the
RGB inputs so that the circuit is
suitable for incoming signals from the
SCART connector. The contrast and
brightness controls operate on
internal and external signals.
The fast blanking pin has a second
detection level at 3.5 V.
When this level is exceeded the
RGB outputs are blanked so that
“On-Screen-Display” signals can be
applied to the outputs.
The output signal has an amplitude of
approximately 4 V, black-to-white,
with nominal input signals and
nominal control settings. The nominal
black level is 1.3 V.



LENOIR  KHB8114TX  CHASSIS  190-931323-P1 031298 TDA3653B TDA3653C Vertical deflection and guard circuit (90°):

GENERAL DESCRIPTION
The TDA3653B/C is a vertical deflection output circuit for drive of various deflection systems with currents up to
1.5 A peak-to-peak.
Features
· Driver
· Output stage
· Thermal protection and output stage protection
· Flyback generator
· Voltage stabilizer
· Guard circuit

QUICK REFERENCE DATA
Note to the quick reference data
1. The maximum supply voltage should be chosen such that during flyback the voltage at pin 5 does not exceed 60 V.

 FUNCTIONAL DESCRIPTION
Output stage and protection circuit
Pin 5 is the output pin. The supply for the output stage is fed to pin 6 and the output stage ground is connected to pin 4.
The output transistors of the class-B output stage can each deliver 0.75 A maximum.
The maximum voltage for pin 5 and 6 is 60 V.
The output power transistors are protected such that their operation remains within the SOAR area. This is achieved by
the co-operation of the thermal protection circuit, the current-voltage detector, the short-circuit protection and the special
measures in the internal circuit layout.
Driver and switching circuit
Pin 1 is the input for the driver of the output stage. The signal at pin 1 is also applied via external resistors to pin 3 which
is the input of a switching circuit. When the flyback starts, this switching circuit rapidly turns off the lower output stage
and so limits the turn-off dissipation. It also allows a quick start of the flyback generator.
External connection of pin 1 to pin 3 allows for applications in which the pins are driven separately.
Flyback generator
During scan the capacitor connected between pins 6 and 8 is charged to a level which is dependent on the value of the
resistor at pin 8 (see Fig.1).
When the flyback starts and the voltage at the output pin (pin 5) exceeds the supply voltage, the flyback generator is
activated.
The supply voltage is then connected in series, via pin 8, with the voltage across the capacitor during the flyback period.
This implies that during scan the supply voltage can be reduced to the required scan voltage plus saturation voltage of
the output transistors.
The amplitude of the flyback voltage can be chosen by changing the value of the external resistor at pin 8.
It should be noted that the application is chosen such that the lowest voltage at pin 8 is > 2.5 V, during normal operation.
Guard circuit
When there is no deflection current and the flyback generator is not activated, the voltage at pin 8 reduces to less than
1.8 V. The guard circuit will then produce a DC voltage at pin 7, which can be used to blank the picture tube and thus
prevent screen damage.
Voltage stabilizer
The internal voltage stabilizer provides a stabilized supply of 6 V to drive the output stage, which prevents the drive
current of the output stage being affected by supply voltage variations.


PACKAGE OUTLINES
TDA3653B: 9-lead SIL; plastic (SOT110B); SOT110-1; 1996 November 25.
TDA3653C: 9-lead SIL; plastic power (SOT131); SOT131-2 November 25.
PARAMETER SYMBOL MIN. TYP. MAX. UNIT
Supply (note 1)
Supply voltage range
pin 9 VP = V9-4 10 - 40 V
pin 6 V6-4 - - 60 V
Output (pin 5)
Peak output voltage during flyback V5-4M - - 60 V
Output current I5(p-p) - 1.2 1.5 A
Operating junction temperature range Tj -25 - +150 °C
Thermal resistance junction to mounting base
(SOT110B) Rth j-mb - 10 - K/W
(SOT131) Rth j-mb - 3.5 - K/W.


LENOIR  KHB8114TX  CHASSIS  190-931323-P1 031298 SAA5x9x family Economy teletext and TV microcontrollers :
1 FEATURES
1.1 General
· Single chip microcontroller with integrated teletext
decoder
· Single +5 V power supply
· Single crystal oscillator for teletext decoder, display and
microcontroller
· Teletext function can be powered-down independently
of microcontroller function for reduced power
consumption in standby
· Pin compatibility throughout family.
1.2 Microcontroller
· 80C51 microcontroller core
· 16/32/64 kbyte mask programmed ROM
· 256/768/1280 bytes of microcontroller RAM
· Eight 6-bit Pulse Width Modulator (PWM) outputs for
control of TV analog signals
· One 14-bit PWM for Voltage Synthesis Tuner control
· Four 8-bit Analog-to-Digital converters
· 2 high current open-drain outputs for directly driving
LEDs etc.
· I2C-bus interface
· External ROM and RAM capability on QFP80 package
version.
1.3 Teletext acquisition
· 1 page and 10 page Teletext version
· Acquisition of 525-line and 625-line World System
Teletext, with automatic selection
· Acquisition and decoding of VPS data (PDC system A)
· Page clearing in under 64 ms (1 TV line)
· Separate storage of extension packets
(SAA5296/7, SAA5296/7A and SAA5496/7)
· Inventory of transmitted Teletext pages stored in the
Transmitted Page Table (TPT) and Subtitle Page Table
(SPT) (SAA5296/7, SAA5296/7A and SAA5496/7)
· Automatic detection of FASTEXT transmission
· Real-time packet 26 engine for processing accented
(and other) characters
· Comprehensive Teletext language coverage
· Video signal quality detector.
1.4 Teletext Display
· 525-line and 625-line display
· 12 ´ 10 character matrix
· Double height, width and size On-Screen Display (OSD)
· Definable border colour
· Enhanced display features including meshing and
shadowing
· 260 characters in mask programmed ROM
· Automatic FRAME output control with manual override
· RGB push-pull output to standard decoder ICs
· Stable display via slave synchronisation to horizontal
sync and vertical sync.
1.5 Additional features of SAA529xA devices
· Wide Screen Signalling (WSS) bit decoding (line 23).
1.6 Additional features of SAA549x devices
· Wide Screen Signalling bit decoding (line 23)
· Quad width OSD capability
· 32 additional OSD characters in mask programmed
ROM
· 8 foreground and 8 background colours definable from a
palette of 64.

2 GENERAL DESCRIPTION
The SAA529x, SAA529xA and SAA549x family of
microcontrollers are a derivative of the Philips’
industry-standard 80C51 microcontroller and are intended
for use as the central control mechanism in a television
receiver. They provide control functions for the television
system and include an integrated teletext function.
The teletext hardware has the capability of decoding and
displaying both 525-line and 625-line World System
Teletext. The same display hardware is used both for
Teletext and On-Screen Display, which means that the
display features give greater flexibility to differentiate the
TV set.
The family offers both 1 page and 10 page Teletext
capability, in a range of ROM sizes. Increasing display
capability is offered from the SAA5290 to the SAA5497.
2.1 Device masking history
A number of mask variants have been produced for the
ETT family of devices. The current mask variants available
are:
· SAA5x90 M5A
· SAA5x91 M1A
· SAA5x96 M5A
· SAA5x97 M1A.
There have been two design issues with the M1 mask,
which required resolving, these brought about the
introduction of the M1A mask:
· Spanish G3 arrows
· OSD twist effect.
The Spanish G3 arrows issue was only encountered on
the Pan-European device, it became apparent that an
up arrow and a right arrow were missing from the Spanish
character map.
The OSD twist effect was inherent on all devices, although
not visible on the Pan-European version. Essentially, OSD
characters had the ability to set and reset the serial
attribute “twist”. This effect is described in detail in
Application note “SPG/AN97004 Version 1.0”.


7 FUNCTIONAL DESCRIPTION
7.1 Microcontroller
The functionality of the microcontroller used in this family
is described here with reference to the industry-standard
80C51 microcontroller. A full description of its functionality
can be found in the “80C51-Based 8-Bit Microcontrollers;
Data Handbook IC20”. Using the 80C51 as a reference,
the changes made to this family fall into two categories:
· Features not supported by the SAA529x, SAA529xA or
SAA549x devices
· Features found on the SAA529x, SAA529xA or
SAA549x devices but not supported by the 80C51.
7.2 80C51 features not supported
7.2.1 INTERRUPT PRIORITY
The IP SFR is not implemented and all interrupts are
treated with the same priority level. The normal
prioritisation of interrupts is maintained within the level.
Table 2 Interrupts and vectors address
Note
1. SAA5290, SAA5290A, SAA5291, SAA5291A and
SAA5491 only.
7.2.2 OFF-CHIP MEMORY
The SDIP52 version does not support the use of off-chip
program memory or off-chip data memory.
7.2.3 IDLE AND POWER-DOWN MODES
As Idle and Power-down modes are not supported, their
respective bits in PCON are not available.
7.2.4 UART FUNCTION
The 80C51 UART is not available. As a consequence the
SCON and SBUF SFRs are removed and the ES bit in the
IE SFR is unavailable.
INTERRUPT SOURCE VECTOR ADDRESS
Reset 000H
External INT0 003H
Timer 0 00BH
External INT1 013H
Timer 1 01BH
Byte I2C-bus 02BH
Bit I2C-bus; note 1 053H
7.3 Additional features
The following features are provided in addition to the
standard 80C51 features.
7.3.1 INTERRUPTS
The external INT1 interrupt is modified to generate an
interrupt on both the rising and falling edges of the INT1
pin, when EX1 bit is set. This facility allows for software
pulse width measurement for handling of a remote control.
7.3.2 BIT LEVEL I2C-BUS INTERFACE
For reasons of compatibility with SAA5290 and
SAA5290A, the SAA5291, SAA5291A and SAA5491
contain a bit level serial I/O which supports the I2C-bus.
P1.6/SCL and P1.7/SDA are the serial I/O pins. These two
pins meet the I2C-bus specification “The I2C-bus and how
to use it (including specifications)” concerning the input
levels and output drive capability. Consequently, these two
pins have an open-drain output configuration. All the four
following modes of the I2C-bus are supported.
· Master transmitter
· Master receiver
· Slave transmitter
· Slave receiver.
Three SFRs support the function of the bit-level I2C-bus
hardware: S1INT, S1BIT and S1SCS and are enabled by
setting register bit TXT8.I2C SELECT to logic 0.
7.3.3 BYTE LEVEL I2C-BUS INTERFACE
The byte level serial I/O supports the I2C-bus protocol.
P1.6/SCL and P1.7/SDA are the serial I/O pins. These two
pins meet the I2C-bus specification concerning the input
levels and output drive capability. Consequently, these two
pins have an open-drain output configuration.
The byte level I2C-bus serial port is identical to the I2C-bus
serial port on the 8xC552. The operation of the subsystem
is described in detail in the 8xC552 data sheet found in
“80C51-Based 8-Bit Microcontrollers; Data Handbook
IC20”.
Four SFRs support the function of the byte level I2C-bus
hardware, they are S1CON, S1STA, S1DAT and S1ADR
and are enabled by setting register bit TXT8.I2C SELECT
to logic 1.
7.3.4 LED SUPPORT
Port pins P0.5 and P0.6 have a 10 mA current sinking
capability to enable LEDs to be driven directly.





8 TELETEXT DECODER
8.1 Data slicer
The data slicer extracts the digital teletext data from the
incoming analog waveform. This is performed by sampling
the CVBS waveform and processing the samples to
extract the teletext data and clock.
8.2 Acquisition timing
The acquisition timing is generated from a logic level
positive-going composite sync signal VCS. This signal is
generated by a sync separator circuit which adaptively
slices the sync pulses. The acquisition clocking and timing
are locked to the VCS signal using a digital
phase-locked-loop. The phase error in the acquisition
phase-locked-loop is detected by a signal quality circuit
which disables acquisition if poor signal quality is detected.
8.3 Teletext acquisition
This family is capable of acquiring 625-line and 525-line
World System Teletext see “World System Teletext and
Data Broadcasting System”. Teletext pages are identified
by seven numbers: magazine (page hundreds), page tens,
page units, hours tens, hours units, minutes tens and
minutes units. The last four digits, hours and minutes, are
known as the subcode, and were originally intended to be
time related, hence their names. A page is requested by
writing a series of bytes into the TXT3 SFR which
corresponds to the number of the page required.
The bytes written into TXT3 are put into a small RAM with
an auto-incrementing address. The start address for the
RAM is set using the TXT2 SFR. Table 12 shows the
contents of the page request RAM.
TXT2.REQ0 to TXT2.REQ3 determine which of the
10 page requests is being modified for a 10 page teletext
decoder. If TXT2.REQ is given a value greater than 09H,
then data written into TXT3 is ignored.
Up to 10 pages of teletext can be acquired on the 10 page
device, when TXT1.EXT PKT OFF is set to logic 1, and up
to 9 pages can be acquired when this bit is set to logic 0.
If the ‘DO CARE’ bit for part of the page number is set to a
logic 0 then that part of the page number is ignored when
the teletext decoder is deciding whether a page being
received off air should be stored or not. For example, if the
‘DO CARE’ bits for the 4 subcode digits are all set to
logic 0s then every subcode version of the page will be
captured.
When the HOLD bit is set to a logic 0 the teletext decoder
will not recognise any page as having the correct page
number and no pages will be captured. In addition to
providing the user requested hold function this bit should
be used to prevent the inadvertent capture of an unwanted
page when a new page request is being made. For
example, if the previous page request was for page 100
and this was being changed to page 234, it would be
possible to capture page 200 if this arrived after only the
requested magazine number had been changed.
The E1 and E0 bits control the error checking which should
be carried out on packets 1 to 23 when the page being
requested is captured. This is described in more detail in
Section 8.5.
For the ten page device, each packet can only be written
into one place in the teletext RAM so if a page matches
more than one of the page requests the data is written into
the area of memory corresponding to the lowest numbered
matching page request.
At power-up each page request defaults to any page, hold
on and error check Mode 0.