GRUNDIG SUPER COLOR P45-740 TOP CHASSIS CUC7300 INTERNAL VIEW.

The GRUNDIG CHASSIS CUC7300 was first GRUNDIG COLOR TV CHASSIS featuring the Monochip TDA8361 and a sophisticated microcomputer toghether with teletext on chip functions in one chassis board with dual layer PCB.


GRUNDIG SUPER COLOR  P45-740 TOP CHASSIS CUC7300  Switched-mode power supply control circuit: Siemens Function and Application of the Switch Mode Powersupply IC TDA4605;

A controller for a switch mode power supply includes an undervoltage protection circuit responsive to an input supply voltage indicative signal. The input supply voltage indicative signal is also coupled to a foldback point correction circuit. The correction circuit causes a decrease in a maximum duty cycle of a control signal when the input supply voltage increases and is still smaller than a predetermined magnitude. A zener diode limits the input supply voltage indicative signal in a manner to prevent a further decrease in the duty cycle when the input supply voltage exceeds the predetermined magnitude.

1. A switch mode power supply, comprising: a source of an input supply voltage;
a switch responsive to a first control signal having a controllable duty cycle and coupled to said source of input supply voltage for generating an output supply voltage, in accordance with said duty cycle of said first control signal;

a duty cycle modulator responsive to a second control signal for generating said first control signal and for controlling said duty cycle of said first control signal in accordance therewith, said modulator being responsive to a signal that is indicative of said input supply voltage for decreasing said duty cycle when said input supply voltage increases; and
a limiter coupled to said modulator for limiting the decrease in duty cycle, for a given increase in said input supply voltage, when said input supply voltage exceeds a first magnitude.


2. A power supply according to claim 1, wherein said duty cycle of said first control signal varies within a control range, in accordance with said second control signal, and wherein said limiter limits a decrease of said duty cycle when said duty cycle is at an end of said control range.

3. A power supply according to claim 1, wherein said limiter comprises a clamper coupled in a signal path of said input supply voltage indicative signal for clamping said input voltage indicative signal, when said input supply voltage exceeds said first magnitude, and for disabling the clamping thereof, when said input supply voltage does not exceed said first magnitude.

4. A power supply according to claim 3, wherein said voltage clamper comprises a diode.

5. A power supply according to claim 3, further comprising a disabling circuit responsive to said input supply voltage indicative signal for disabling said output supply voltage, when said input supply voltage is smaller than a second magnitude and wherein said voltage clamper is coupled in a common signal path of said input supply voltage indicative signal with respect to each of an input of said disabling circuit and an input of said limiter.

6. A power supply according to claim 1, wherein said modulator comprises a foldback point corrector for decreasing said duty cycle, when said input supply voltage increases and wherein said limiter is coupled to said corrector.

7. A power supply according to claim 1, wherein said second control signal is produced in a feedback path for regulating said output supply voltage.

8. A power supply according to claim 1, wherein said input supply voltage indicative signal is coupled to said modulator from said source of input supply voltage via a signal path that bypasses said switch.

9. A power supply according to claim 8, wherein said limiter comprises a clamp coupled in said signal path for clamping said input supply voltage indicative signal, when said input supply voltage exceeds said first magnitude, and for disabling the clamping operation, when said input supply voltage does not exceed said first magnitude.

10. A power supply, comprising: an input supply voltage, a transformer and a switch coupled for switch mode generation of a regulated output supply voltage, said switch being responsive to a first control signal having a controllable duty cycle;
a duty cycle modulator for generating said first control signal responsive to a second control signal for limiting a duty cycle of said switch, said modulator operating in a first mode when said second control signal is in a predetermined range of voltage levels and operating in a second mode when said second control signal is outside of said range; and
a voltage monitor circuit for generating said second control signal, said second control signal representing a first proportion of said input supply voltage in a first range of input supply voltage values and a second proportion of said input supply voltage in a second range of input supply voltage values.


11. A power supply according to claim 10 wherein said voltage monitor circuit comprises a clamp coupled in a signal path of said second control signal.

12. A power supply according to claim 11, wherein said second signal is coupled to said modulator from said input supply voltage via a signal path that bypasses said switch.

13. A power supply, comprising: an input supply voltage, a transformer and a switch coupled for switch mode generation of a regulated output supply voltage, said switch being responsive to a first control signal having a controllable duty cycle;
a duty cycle modulator for generating said first control signal responsive to a second control signal, said modulator operating in a first mode when said second control signal is in a predetermined range of voltage levels and operating in a second mode when said second control signal is outside of said range; and
a voltage monitor circuit for generating said second control signal, said second control signal representing a first proportion of said input supply voltage in a first range of input supply voltage values and a second proportion of said input supply voltage in a second range of input supply voltage values, such that as long as said input supply voltage is in said first range of input supply voltage values, said second control signal varies when said input supply voltage varies and said modulator operates in said first mode of operation.


14. A power supply, comprising: an input supply voltage, a transformer and a switch coupled for switch mode generation of a regulated output supply voltage, said switch being responsive to a first control signal having a controllable duty cycle;
a duty cycle modulator for generating said first control signal responsive to a second control signal, said modulator operating in a first mode when said second control signal is in a predetermined range of voltage levels and operating in a second mode when said second control signal is outside of said range; and
a nonlinear voltage divider circuit coupled to said input supply voltage for generating said second control signal, said second control signal representing a first proportion of said input supply voltage in a first range of input supply voltage values and a second proportion of said input supply voltage in a second range of input supply voltage values.

Description:

The invention relates to a switch mode power supply control circuit.
Switched-mode power supplies efficiently generate a variety of regulated voltages from a single line voltage level (e.g., 220 volts AC). One important use of these power supplies is within a television signal receiver where they are used to produce a regulated B+ voltage for the horizontal deflection circuit as well as other regulated voltages for powering various digital and analog circuits.
Typically, a switched-mode power supply contains a full-wave rectifier, a power supply controller, a switch, and an output transformer. The switch is typically a high-power transistor such as a MOSFET. To regulate the output voltages, the controller activates and deactivates (e.g., pulse width modulates) the gate of the transistor in response to power supply loading and other control parameters. The switched voltage from the transistor drives a primary winding of the transformer, while various power supply loads are connected to one or more secondary windings. As such, the power supply converts an AC input voltage into one or more DC voltages.
One particular controller is an integrated circuit available from Siemens as Model TDA 4605. This power supply controller is typically used to drive the MOSFET transistor, which in turn drives the primary coil of the transformer. This specific integrated circuit, as well as others used in the art, typically contain a control mechanism that disables the power supply when the input voltage drops below a pre-defined voltage level. Such protection is necessary because, to produce regulated output voltages, the switched-mode power supply increases the duty cycle of the control signal driving the transistor as the input voltage decreases. At some point, the input voltage decreases to a level where the output of the power supply is unregulated (e.g., the maximum pulse length is used to drive the transistor). Such unregulated operation can damage the power supply electronics, but is more likely to damage the load electronics.

For the integrated circuit (IC) TDA4605, as defined in the TDA4605 Technical Manual available from Siemens AG, dated Jul. 27, 1989, pin 3 of the integrated circuit is used for sensing or monitoring the primary input voltage (vp) for the power supply (e.g., the rectified AC voltage). The threshold voltage for disabling or deactivating the integrated circuit, and thus the power supply, is pre-established by the controller at one volt. As such, the primary input voltage (vp) is reduced using a voltage divider at the input of pin 3. By selecting appropriate resistor values within the voltage divider, a nominal value of monitoring voltage is applied to pin 3. Typically, this voltage is approximately 2.0 volts for a primary input voltage of 120 volts. When the primary input voltage falls to a level that causes the monitoring voltage at pin 3 to fall below one volt, the power supply is deactivated to avoid unregulated operation.
As stated above, this form of switched-mode power supply has been finding use within television signal receivers. However, television receivers, in particular, present peculiar loading characteristics to a power supply. Specifically, a television receiver power supply is called upon to produce a regulated B+ voltage, typically of approximately 140 volts, as well as a low voltage DC level of 16 volts for powering all of the digital and analog circuitry within the receiver. When the television receiver is switched from stand-by to run mode, a heavy load is produced by the in-rush of current into filter capacitors connected to the regulated B+ voltage. This heavy load causes the power supply to temporarily operate in an unregulated (maximum pulse width) mode, and may cause the primary input voltage to drop to a low level. Furthermore, when the degaussing circuit is activated to degauss the cathode ray tube (CRT), the main AC supply voltage is depressed due to the substantial load presented by the degaussing circuit. Consequently, the drop in line voltage could typically cause the monitoring voltage to drop below the 1 volt, first threshold level, and as such, to disable the power supply.
Therefore, there it is desirable to produce a monitoring voltage indicative of the primary input voltage, but to insure that the power supply will not be deactivated for the expected heavy loads found in a television receiver.

The IC TDA 4605 includes a foldback point correction circuit that reduces the maximum duty cycle of the MOSFET control signal, when the monitoring voltage exceeds a second threshold level of approximately 1.7 V. The monitoring voltage is applied to the correction circuit also via pin 3.

In a circuit embodying an inventive feature, a resistive voltage divider that produces the monitoring input or sense signal from the primary input voltage is designed such that the first threshold level is not attained during the expected temporary loading of the primary input voltage. However, such a voltage divider results in a higher voltage being applied to the monitoring voltage input of the controller during normal operation of the power supply. As such, an increase of the primary input voltage to a higher level, which is still within the acceptable tolerance range of the AC line voltage, can cause the monitoring voltage to rise to a level that exceeds the second threshold level at which the integrated circuit begins to limit the maximum duty cycle of the control signal that controls the MOSFET, i.e., the controller applies a foldback correction technique. When the second threshold level is exceeded, the power supply automatically limits the output power of the power supply for an increase in the primary voltage. As a result of the voltage divider design that provides sufficient headroom to overcome loading generated drop outs in the primary input voltage, the maximum power supply output could be, undesirably, significantly reduced at high primary input voltage.
In carrying out an inventive feature, to insure that such inconsequential increase in the primary input voltage does not cause the power supply to significantly reduce the maximum duty cycle of the control signal and thereby, the power output of the power supply, a zener diode is coupled to the voltage divider. The zener diode limits the magnitude of the monitoring voltage to a level that avoids further maximum duty cycle limiting when the primary input voltage further increases. Consequently, when the power supply is used in a television signal receiver, the voltage divider provides enough head room for the primary voltage to drop substantially due to degaussing circuit activation or other loading conditions, while the zener diode insures that the primary voltage can rise above its nominal voltage without causing a significant power limitation of the power supply output.
A switch mode power supply, embodying an aspect of the invention, includes a source of an input supply voltage. A switch is responsive to a first control signal having a controllable duty cycle and coupled to the source of input supply voltage for generating an output supply voltage, in accordance with the duty cycle of the first control signal. A duty cycle modulator is responsive to a second control signal for generating the first control signal and for controlling the duty cycle of the first control signal in accordance therewith in a manner to control the current pulses. An increase in the duty cycle produces an increase in a magnitude of the current pulses. The modulator is responsive to a signal that is indicative of the input supply voltage for decreasing the duty cycle when the input supply voltage increases. A limiter is coupled to the modulator for limiting the decrease in duty cycle, for a given increase in said input supply voltage, when the input supply voltage exceeds a first magnitude.

FIG. 1 depicts a schematic diagram of a switched-mode power supply incorporating the teachings of the present invention.

FIG. 1 depicts a schematic diagram of a switched-mode power supply 100 incorporating the present invention. The embodiment shown is designed for use as a power supply for a television signal receiver, wherein the power supply generates a regulated B+ voltage (e.g., 140 volts) and a low voltage (e.g., 16 volts). The regulated B+ voltage is used to power a horizontal deflection circuit and the regulated low voltage is used to power the digital and analog electronics (continuous load 118). Other applications for the power supply may require slight variation in the depicted components and their interconnections; however, such variations are well within the scope of the present invention.
The power supply contains a number of major components, including a full-wave rectifier 102, the power supply controller 106, a MOSFET transistor Q1, a monitor voltage generator 110, an output transformer 112, and a plurality of circuit components used to complete the power supply electronics. Illustratively, the input to the power supply is a 110-volt AC, 60 hertz voltage.
Rectifier 102 is a conventional full-wave bridge rectifier coupled to an AC input voltage source 101. The output of the bridge rectifier 102 is coupled to capacitor C1 approximately 680 μF). A voltage RAW B+ forms raw (unregulated) B+ voltage (also referred to herein as the primary input voltage vp) having a nominal value of approximately 150 volts. Capacitor C1, connected from the output of the rectifier to ground, smoothes the voltage from the bridge rectifier such that a DC voltage, i.e., the primary input voltage vp, is available at the upper terminal of the transformer's primary winding W₁.
The primary input voltage forms an input to the monitor voltage generator 110 which produces a monitor voltage VZ1 for the controller 106. The monitor voltage generator is discussed in detail below.
The controller is illustratively a TDA4605 power supply controller available from Siemens AG of Munich, Germany. The eight pins of the controller are connected to signals and voltages that enable the controller to produce a pulse width or duty cycle modulated signal at pin five for controlling the duty cycle of the transistor Q1. Specifically, pin 4 of controller 106 is grounded. Pin 3 is coupled to the monitor voltage.
Pin 2 is supplied information concerning the primary current. A primary current increase in the primary winding W₁ is simulated as a voltage rise of a periodical, ramp voltage VC2 at pin 2 using an external RC element formed by resistor R3, capacitor C2, and resistor R4 (where R3 is approximately 360 kΩ, C2 is approximately 6,800 pF; and R4 is approximately 220 Ω). These elements are connected in series from the primary input voltage to ground. Pin 2 of the controller 106 is coupled to the junction of R3 and C2. A pulse width modulator 106c of the controller 106 controls the duration of the forward phase, and thus, the primary peak current, using ramp voltage VC2 that is proportional to the drain current of the transistor Q1. As indicated before, the ramp voltage is derived from the primary input voltage using the RC elements connected to pin 2, i.e., the ramp voltage simulates the primary current. Controller pin 1 is supplied secondary voltage information which internally compares the control voltage sampled from the regulating winding W3 of the transformer 112 and compares that sample voltage with an internal reference voltage.
Pin 5 generates a duty cycle modulated control signal or voltage VOUT via a push-pull output driver for rapid charge and discharge of the input capacitance of a MOSFET power transistor Q1 (Model IRF740).
Pin 6 is coupled to the supply voltage for the controller. Pin 7 forms a soft start input terminal. Capacitor C5 (0.1 μF) is connected from pin 7 to ground to reduce the pulse duration during start-up. Lastly, pin 8 is the input pin for the oscillator feedback.
In operation, the transistor Q1 is used as a power switch controlled by the controller 106. A snubber circuit is connected to the drain of the transistor Q1. The snubber circuit contains a combination of diode D3, resistor R16 and capacitor C12, which together limit the voltage overshoot when the transistor is turned off. D3 is a MUR450 diode, C12 is a 1000 pF capacitor, and R16 is a 2-watt, 30 kΩ resistor.
Together with the stray capacitance of the transformer, capacitor C7 (470 pF connected from drain terminal to ground) determines the no-load frequency, and consequently, the maximum slew rate of the drain voltage for a transistor Q1.
Transistor Q1 is driven with pulse width modulated signal VOUT produced at pin 5 of controller 106 and coupled to the gate terminal of the transistor via resistor R11 (35 Ω). Furthermore, a capacitor C6 (4700 pF) is coupled from the source terminal to the drain terminal. The source terminal is coupled to ground through resistor R13 (0.27 KΩ). Resistor R12 (10 kΩ) is optionally connected between the source terminal and gate terminal to ensure that the transistor will not be activated if power is applied to the power supply without the controller 106 being installed. The drain terminal is coupled to one terminal of the primary winding W1 of transformer 112. Consequently, the transistor Q1 controls the current flow from the primary input voltage through the primary winding.
The secondary circuit of the transformer 112 consists of several windings, each of which has a different number of turns, polarity, and load capacity. Specifically, winding W2 forms the output voltage for the regulated B+, while winding W4 forms the output winding for the regulated 16-volt low voltage output, and winding W3 generates the feedback voltage for the controller 106.
The load circuitry includes, connected to winding W2, an output diode D4 and capacitor C13 that couple power to the horizontal deflection circuit 116. Additionally, the center tap of the output secondary winding is connected to ground, and winding W4 is coupled to diode D5 and capacitor C14. This output is the 16 volts that powers the continuous load 118 of the television receiver, e.g., all of the electronics and integrated circuits. This circuit 118 also controls the timing of when the degaussing circuit 114 is activated using degaussing control line 120. The control line for the continuous load is the run/standby control signal that essentially turns the television receiver on and off. The continuous load circuitry 118 is also coupled to the horizontal deflection circuit 116 to provide control signals therefor.
The controller 106 is started up using resistor R17 (100 KΩ) as a start resistor. As such, capacitor C11 (100 μF) is charged with half-wave currents at the voltage supply pin of the controller 106, e.g., pin 6. These half-wave currents are supplied from the primary input voltage through resistor R17 (100 KΩ) to ground through series connected resistor R14 (202 Ω), diode D2 (148 Ω) and regulating winding W3. When the voltage at C11 reaches the switch-on threshold, the switched-mode power supply begins to function and supplies the feedback voltage, via winding W3, resistor R14 and diode D2. This feedback voltage, when rectified by diode D2 and smoothed by capacitor C11, forms the supply voltage (v_cc) for the controller 106 via pin 6.
A control signal or voltage VCT for pin 1 is generated in a circuit parallel to the controller supply voltage circuit. The control voltage is produced by diode D1 (ERB43) charging capacitor C3 (1.5 μF) through resistor R8 (10 Ω). The RC element, consisting of series connected R15 (30 Ω) and C10 (0.01 μF), prevents peak value rectification of high frequency components of the feedback signal.
More specifically, regulating winding W3 is coupled to one terminal of resistor R15. The other terminal of resistor R15 is coupled to capacitor C10 to ground. Diode D1 is connected at the junction of resistor R15 and capacitor C10. Capacitor C9 (1000 pF) is connected in parallel with diode D1. Diode D1 has an output voltage that is coupled to series connected R8 and C3 which couples the output of the diode to ground. The output of the diode is also coupled through resistive divider network R6 and R7 which are respectively connected in series to ground. The voltage at the junction of R6 and R7 forms control voltage VCT and is coupled to pin 1 of the controller 106. These resistors define the no-load frequency of oscillation of the controller 106. Therefore, they are typically 0.1% accurate resistors having R6 being 5.49 KΩ, and R7 being 174 Ω. Control voltage VCT is coupled to a pulse-width modulator 106c within controller 106 that controls the duty cycle modulation of voltage VOUT for regulating, for example, voltage REGB+.
During the power supply start-up, capacitor C5 at the soft-start pin (e.g., pin 7), influences the duration of the forward phase by controlling the error voltage of the pulse width modulator. The controller detects the end of the transformer discharge phase via resistor R10 (20 KΩ) that is coupled at one end to controller pin 8 and at the other end to resistor R14, and ultimately to the regulating winding W3. Additionally, capacitor C8 (0.022 μF) is coupled from the junction of R10 and R14 to ground. At this point, the voltage changes polarity from positive to negative, i.e., the voltage represents zero crossings.
A voltage VZ1, embodying an inventive feature, is generated by the monitor voltage generator 110 and is coupled to pin 3 of the controller 106. Voltage VZ1 is used both for determining the minimum line voltage that will allow the power supply to operate and for controlling a foldback point correction circuit 106b within the controller 106.
The monitor voltage generator 110 contains resistor R1 (270 kΩ) coupled in series with resistor R2 (5100 Ω) to form a resistive voltage divider network with respect to primary input voltage RAW B+. The junction of the two resistors is coupled to the pin 3 of controller 106. Furthermore, a zener diode Z1 (B2X55/C3VO), embodying an inventive feature, is connected in parallel with resistor R2 from the junction point to ground. Zener diode Z1 forms a limiter for limiting the maximum voltage across R2 to the breakdown voltage of the zener diode Z1. Consequently, the voltage at the output of the monitor voltage generator 110 tracks the primary input voltage RAW B+ up to the threshold point where the zener diode Z1 begins to conduct.
The controller 106 includes an under-voltage detector 106a that uses a fixed, internal voltage threshold that causes the controller to disable the power supply whenever the monitor voltage VZ1 drops below a first threshold voltage. For the TDA 4605 integrated circuit, this first threshold voltage is one volt. As such, the divider network of R1 and R2 defines a voltage at the output that under typical operation would not cause the controller to deactivate the power supply.
In one particular application, e.g., a television signal receiver, a degaussing circuit 114 for a television signal receiver is typically connected directly across the input AC power. Consequently, when the degaussing circuit is activated, it will typically cause a drop in the AC voltage that is applied to the input of the voltage rectifier 102. Consequently, the primary input voltage RAW B+ will drop significantly during the degaussing period. Since this is a normal behavior of a conventional television receiver circuit, it is desirable that the monitor voltage generator 110 be designed such that the controller 106 will not deactivate the power supply during the degaussing period.
For a primary input voltage of 120 volts and using a resistive divider of 270 KΩ for R1 and 5100 Ω for R2, the nominal voltage VZ1 at the voltage monitor input pin is 2 volts. Such a value for the voltage monitor voltage will avoid power supply deactivation during the degaussing period or other heavy load period.
When the duty cycle of voltage VOUT is at the maximum as a result of an overload condition, an increase in voltage RAW B+, produced by an increase in the AC line voltage, causes the voltage across primary winding w₁ to increase. As the primary input voltage RAW B+ rises, the available input power to the power supply increases which could damage the power supply when the power supply is overloaded. During a period of overloaded, unregulated output, the modulator 106c generates the voltage VOUT having a maximum duty cycle for driving transistor Q1. As a result, a primary current IP in winding W₁ of transformer 112 has also a maximum duty cycle. Therefore, undesirably an increase in voltage RAW B+ can produce a large voltage across the transistor that could damage the transistor or other circuitry.
To maintain the power supply within a safe operation range, the controller 106 includes what is known as a foldback or overload point correction circuit 106b. This foldback point correction circuit reduces the maximum duty cycle of voltage VOUT when the primary input voltage exceeds a predetermined magnitude. An increase above the predetermined magnitude causes the foldback point correction circuit 106b to decrease the maximum duty cycle of signal VOUT as voltage RAW B+ increases. The decrease is done by generating a correction current ICOR that is coupled to capacitor C2 causing an increase in the rate of change of voltage VC2 at pin 2 of controller 106 when voltage VZ1 exceeds a second threshold voltage.
When voltage RAW B+ increases and causes voltage VZ1 to further increase above the second threshold voltage an increase in current ICOR produces a decrease in the maximum duty cycle of signal VOUT, in a well know manner. The second threshold voltage occurs when voltage VZ1 is above a voltage level of approximately 1.7 V. The result is that, when voltage RAW B+ further increases the maximum duty cycle decreases proportionally. The decrease in the maximum duty cycle tends to stabilize the maximum power produced in the power supply against an increase of voltage RAW B+. On the other hand, an increase of voltage VZ1 when voltage VZ1 is below the 1.7 V level, does not affect current ICOR and the duty cycle of voltage VOUT.
Because the divider network (R1 and R2) establishes a sufficiently large monitor voltage VZ1 that provides sufficient headroom for preventing power supply shutdown when the degaussing circuit is activated, primary input voltage RAW B+ may be at a level that causes voltage VZ1 to exceed the second threshold voltage of circuit 106b by an excessive amount even when voltage RAW B+ is within the normal tolerance range. Therefore, disadvantageously, the maximum duty cycle may further decrease by a significant amount in a manner to lower the maximum power that can be derived. Such significant reduction in power capability can occur even though primary input voltage is not truly at such a high level that could damage the power supply.
In accordance with an inventive feature, to prevent current ICOR from further reducing the maximum duty cycle of voltage VOUT when voltage RAW B+ increases above a threshold magnitude that corresponds to voltage VZ1 being equal to 3 V, the monitor voltage generator 110 contains the zener diode Z1 operating as a limiter which limits the primary input voltage indicative voltage VZ1 to 3 V. Consequently, the monitor voltage VZ1 can never rise above a pre-defined level (e.g., 3 volts) that would otherwise cause the foldback point correction circuit 106b within the controller 106 to further decrease the maximum duty cycle. In this way, advantageously, the decrease in the maximum duty cycle as a function of an increase in voltage RAW B+ is limited.
The decrease in the duty cycle of voltage VOUT produced by current ICOR, for a given increase in voltage RAW B+, is limited when voltage RAW B+ is greater than a threshold magnitude that corresponds to voltage VZ1 equal to 3 V. In contrast, the decrease in the duty cycle produced by current ICOR is not limited but varies proportionally to voltage RAW B+ when voltage VZ1 is between 1.7 V and 3 V. Thus, zener diode Z1 operates as a limiter for limiting the decrease in the duty cycle when the voltage RAW B+ exceeds the threshold magnitude relative to when voltage RAW B+ does not exceed the threshold magnitude. An increase in voltage RAW B+ that produces voltage VZ1 below the second threshold voltage of 1.7 V, does not affect current ICOR.
Specifically, for the TDA 4605 integrated circuit control, the zener diode has a value of three volts. Consequently, the input signal to the monitor voltage generator cannot rise above the three volt level before the zener diode will begin to conduct current to ground. As such, the monitor voltage generator establishes a range of voltages that pre-defines a range of primary input voltages at which the controller 106 operates in a normal manner that avoids both an undervoltage power supply deactivation and a further decrease in the maximum duty cycle. The input voltage dynamic range is thereby extended.

GRUNDIG SUPER COLOR  P45-740 TOP CHASSIS CUC7300  TDA4605-3 Control IC for Switched-Mode Power Supplies usingMOS-Transistor

The IC TDA 4605-3 controls the MOS-power transistor and performs all necessary control and

protection functions in free running flyback converters. Because of the fact that a wide load range
is achieved, this IC is applicable for consumer as well as industrial power supplies.
The serial circuit and primary winding of the flyback transformer are connected in series to the input
voltage. During the switch-on period of the transistor, energy is stored in the transformer. During the
switch-off period the energy is fed to the load via the secondary winding. By varying switch-on time
of the power transistor, the IC controls each portion of energy transferred to the secondary side
such that the output voltage remains nearly independent of load variations. The required control
information is taken from the input voltage during the switch-on period and from a regulation winding
during the switch-off period. A new cycle will start if the transformer has transferred the stored
energy completely into the load.

In the different load ranges the switched-mode power supply (SMPS) behaves as follows:
No load operation
The power supply is operating in the burst mode at typical 20 to 40 kHz. The output voltage can be
a little bit higher or lower than the nominal value depending of the design of the transformer and the
resistors of the control voltage divider.
Nominal operation
The switching frequency is reduced with increasing load and decreasing AC-voltage.
The output voltage is only dependent on the load.
Overload point
Maximal output power is available at this point of the output characteristic.
Overload
The energy transferred per operation cycle is limited at the top. Therefore the output voltages
declines by secondary overloading.


Circuit Description
Application Circuit
The application circuit shows a flyback converter for video recorders with an output power rating of
70 W. The circuit is designed as a wide-range power supply for AC-line voltages of 180 to 264 V.
The AC-input voltage is rectified by the bridge rectifier GR1 and smoothed by C1 . The NTC limits
the rush-in current.
In the period before the switch-on threshold is reached the IC is suppled via resistor R 1 ; during the
start-up phase it uses the energy stored in C2 , under steady state conditions the IC receives its
supply voltage from transformer winding n1 via diode D1. The switching transistor T1 is a BUZ 90.
The parallel connected capacitor C3 and the inductance of primary winding n 2 determine the
system resonance frequency. The R 2-C4-D2 circuitry limits overshoot peaks, and R 3 protects the
gate of T1 against static charges.
During the conductive phase of the power transistor T1 the current rise in the primary winding
depends on the winding inductance and the mains voltage. The network consisting of R 4-C5 is used
to create a model of the sawtooth shaped rise of the collector current. The resulting control voltage
is fed into pin 2 of the IC. The RC-time constant given by R 4-C5 must be designed that way that
driving the transistor core into saturation is avoided.
The ratio of the voltage divider R 10/R 11 is fixing a voltage level threshold. Below this threshold the
switching power supply shall stop operation because of the low mains voltage. The control voltage
present at pin 3 also determines the correction current for the fold-back point. This current added to
the current flowing through R 4 and represents an additional charge to C5 in order to reduce the turnon
phase of T1. This is done to stabilize the fold-back point even under higher mains voltages.
Regulation of the switched-mode power supplies via pin 1. The control voltage of winding n1 during
the off period of T1 is rectified by D3, smoothed by C6 and stepped down at an adjustable ratio by
R 5 , R 6 and R 7 . The R 8-C7 network suppresses parasitic overshoots (transformer oscillation). The
peak voltage at pin 2, and thus the primary peak current, is adjusted by the IC so that the voltage
applied across the control winding, and hence the output voltages, are at the desired level.
When the transformer has supplied its energy to the load, the control voltage passes through zero.
The IC detects the zero crossing via series resistors R 9 connected to pin 8. But zero crossings are
also produced by transformer oscillation after T1 has turned off if output is short-circuited. Therefore
the IC ignores zero crossings occurring within a specified period of time after T1 turn-off.
The capacitor C8 connected to pin 7 causes the power supply to be started with shorter pulses to
keep the operating frequency outside the audible range during start-up.
On the secondary side, five output voltages are produced across winding n3 to n7 rectified by D4 to
D8 and smoothed by C9 to C13 . Resistors R 12 , R 14 and R 19 to R 21 are used as bleeder resistors.
Fusable resistors R 15 to R 18 protect the rectifiers against short circuits in the output circuits, which
are designed to supply only small loads.

Pin 1
The regulating voltage forwarded to this pin is compared with a stable internal reference voltage VR
in the regulating and overload amplifier. The output of this stage is fed to the stop comparator. If
the control voltage is rather small at pin 1 an additional current is added by means of current source
which is controlled according the level at pin 7. This additional current is virtually reducing the
control voltage present at pin 1.
Pin 2
A voltage proportional to the drain current of the switching transistor is generated there by the
external RC-combination in conjunction with the primary current transducer. The output of this
transducer is controlled by the logic and referenced to the internal stable voltage V2B . If the voltage
V2 exceeds the output voltage of the regulations amplifier, the logic is reset by the stop comparator
and consequently the output of pin 5 is switched to low potential. Further inputs for the logic stage
are the output for the start impulse generator with the stable reference potential VST and the
supply voltage motor.
Pin 3
The down divided primary voltage applied there stabilizes the overload point. In addition the logic is
disabled in the event of low voltage by comparison with the internal stable voltage VV in the primary
voltage monitor block.
Pin 4
Ground
Pin 5
In the output stage the output signals produced by the logic are shifted to a level suitable for MOSpower
transistors.
Pin 6
From the supply voltage V6 are derived a stable internal references VREF and the switching
threshold V6A , V6E , V6 max and V6 min for the supply voltage monitor. All references values (VR ,
V2B , VST) are derived from VREF . If V6 > VVE , the VREF is switched on and switched off when V6 <
V 6A . In addition, the logic is released only for V6 min < V6 < V6 max .
Pin 7
The output of the overload amplifier is connected to pin 7. A load on this output causes a reduction
in maximal impulse duration. This function can be used to implement a soft start, when pin 7 is
connected to ground by a capacitor.

Pin 8
The zero detector controlling the logic block recognizes the transformer being discharged by
positive to negative zero crossing of pin 8 voltage and enables the logic for a new pulse. Parasitic
oscillations occurring at the end of a pulse cannot lead to a new pulse (double pulsing), because an
internal circuit inhibits the zero detector for a finite time tUL after the end of each pulse.
Start-Up Behaviour
The start-up behaviour of the application circuit per sheet 88 is represented an sheet 90 for a line
voltage barely above the lower acceptable limit time t0 the following voltages built up:
– V6 corresponding to the half-wave charge current over R1

– V2 to V2 max (typically 6.6 V)
– V3 to the value determined by the divider R 10/R 11 .
The current drawn by the IC in this case is less than 1.6 mA.
If V6 reaches the threshold V6E (time point t1), the IC switches on the internal reference voltage. The
current draw max. rises to 12 mA. The primary current- voltage reproducer regulates V2 down to V2B
and the starting impulse generator generates the starting impulses from time point t5 to t6 . The
feedback to pin 8 starts the next impulse and so on. All impulses including the starting impulse are
controlled in width by regulating voltage of pin 1. When switching on this corresponds to a shortcircuit
event, i.e. V1 = 0. Hence the IC starts up with "short-circuit impulses" to assume a width
depending on the regulating voltage feedback (the IC operates in the overload range). The IC
operates at the overload point. Thereafter the peak values of V2 decrease rapidly, as the starting
attempt is aborted (pin 5 is switched to low). As the IC remains switched on, V6 further decreases
to V6 . The IC switches off; V6 can rise again (time point t4) and a new start-up attempt begins at
time point t1 . If the rectified alternating Iine voltage (primary voltage) collapses during load, V3 can
fall below V3A , as is happening at time point t3 (switch-on attempt when voltage is too low). The
primary voltage monitor then clamps V3 to V3S until the IC switches off (V6 < V6A). Then a new startup
attempt begins at time point t1 .

Regulation, Overload and No-Load Behaviour
When the IC has started up, it is operating in the regulation range. The potential at pin 1 typically is
400 mV. If the output is loaded, the regulation amplifier allows broader impulses (V5 = H). The peak
voltage value at pin 2 increases up to V2S max . If the secondary load is further increased, the
overload amplifier begins to regulate the pulse width downward. This point is referred to as the
overload point of the power supply. As the IC-supply voltage V6 is directly proportional to the
secondary voltage, it goes down in accordance with the overload regulation behaviour. If V6 falls
below the value V6 min , the IC goes into burst operation. As the time constant of the half-wave
charge-up is relatively large, the short-circuit power remains small. The overload amplifier cuts back
to the pulse width tpk . This pulse width must remain possible, in order to permit the IC to start-up
without problems from the virtual short-circuit, which every switching on with V1 = 0 represents. If
the secondary side is unloaded, the loading impulses (V5 = H) become shorter. The frequency
increases up to the resonance frequency of the system. If the load is further reduced, the secondary
voltages and V6 increase. When V6 = V6 max the logic is blocked. The IC converts to burst
operation.This renders the circuit absolutely safe under no-load conditions.
Behaviour when Temperature Exceeds Limit
An integrated temperature protection disables the logic when the chip temperature becomes too
high. The IC automatically interrogates the temperature and starts as soon as the temperature
decreases to permissible values.


GRUNDIG SUPER COLOR  P45-740 TOP CHASSIS CUC7300 TDA8361 Integrated PAL and PAL/NTSC TV processor
PHILIPS TDA8362 (TDA8361) MAIN CHARACTERISTICS
The TDA8362 television processor microcircuit contains an intermediate frequency (IF) signal processing circuit, a multi-standard demodulator of a frequency-modulated sound signal, automatically tuned notch and band-pass filters in the video signal processing channel, a luminance signal delay line, a color signal decoder in the PAL and NTSC system with automatic detection systems, TV / AV input selector, RGB signal switching scheme, horizontal and vertical scanning synchronization circuits.
Variant TDA8362A also contains automatic white balance circuits. Thus, the TDA8362 includes all the basic low signal circuits needed to build a color television receiver.
The minimum number of elements connected to external circuits and only one element requiring adjustment (reference circuit of the IF signal demodulator) creates an exceptional usability of the TDA8362. As a result, the TDA8362 processor has become one of the most widely used chips in modern television technology.
The main characteristics of TDA8362 are given in table. 1.

Parameter	Value
Supply voltage	8 ± 0.8
Current consumption, mA	80
Power consumption	0.7
Sensitivity of the IFI, μV	70
Sensitivity UPCHZ, mV	1
Sound signal from an external input, mVeff	350
Video signal from external input, Vp_p	1
Signals at the inputs in RGB, Bn n	0.7
Demodulated PTsTS, Vp-p	2,4
Tuner AGC control current, mA	0 ... 5
The range of voltage changes AFCG, V	6
Audio output signal (vyv. 50), mV	700
Output signals in RGB, Bn_n	4
Horizontal line output current, mA	10
Framing output current, mA	1
Control voltage range, V	0 ... 5

Table 1. Key Features of the TDA8362 Processor

The construction, pinout and basic parameters of all modifications of the TDA8362 microcircuits (with the exception of the TDA8362A variant) are the same. Features of their application will be discussed below.
 

DESCRIPTION OF STRUCTURAL SCHEME

Table 2 gives the pin assignment of TDA8362, and also shows the difference in pinout of the TDA8362 and TDA8362A options.
The latter contains a circuit for automatic white balance, the measuring signal at the input of which comes from pin 14 of TDA8362.

TDA8362	TDA8362A	Pin assignment
1	1	Pre-emphasis correction of sound signal and switching to positive modulation
2	2	IF signal demodulator reference circuit
3	3	IF signal demodulator reference circuit
4	4	Video identification circuit output, sound switch input
5	5	IF signal input and volume control
6	6	Audio input from external connectors
7	7	PCTS output
8	8	Decoupling capacitor of the power supply circuit of the digital part
9	41	Earth 1 (common)
10	10	Power input
eleven	eleven	Earth 2 (common)
12	12	Decoupling capacitor filter settings
thirteen	thirteen	Internal video input
14	14	RF correction circuit adjustment input (sharpness)
fifteen	fifteen	External video input
16	16	Chroma input
17	17	Brightness adjustment
18	18	Exit to
19	19	Output G
20	20	Output R
21	21	RGB switch and blanking output
22	22	Signal output R (from external sources)
23	23	Signal output G (from external sources)
24	24	Signal output B (from external sources)
25	25	Contrast adjustment
26	26	Saturation Adjustment
27	27	Color tone adjustment (or color signal output)
28	28	CV input BY (from delay line)
29th	29th	RRS input RY (from delay line)
thirty	thirty	RCS RY output (to delay line)
31	31	TsRS BY output (to the delay line)
32	32	4.43 MHz reference signal output on TDA8395
33	33	Phase detector filter
34	34	Conclusion connection of a quartz resonator of 3.58 MHz
35	35	4.43 MHz quartz resonator connection terminal
36	36	Power output to trigger horizontal scanning
37	37	Horizontal scan trigger output
38	38	Horizontal Flyback Pulse Input / Gating Pulse Output (SSC)
39	39	Phase Detector Filter 2
40	40	Phase Detector Filter 1
41	42	Frame Reverse Pulse Input
42	43	Conclusion conclusion of an RC chain of ZG frame scan
43	44	Firing trigger pulses output
44	9	AFC output
45	45	IF signal input 1
46	46	IF signal input 2
47	47	AGC circuit output
48	48	A conclusion of the connection of the decoupling capacitor of the AGC circuit
49	49	Tuner AGC adjustment input
fifty	fifty	Sound output
51	51	Conclusion connection output decoupling capacitor demodulator sound
52	52	Decoupling capacitor of the power control circuit

Table 2. TDA8362 Processor Pin Assignment

 IF SIGNAL PROCESSING CIRCUIT
The IF image signal amplifier (IFI) is a three-stage differential amplifier with an adjustable gain and a symmetrical differential input (vyv. 45 and 46 TDA8362). The gain variation range is at least 64 dB. The sensitivity of the IFI (70 μV) is comparable to the parameters of modern specialized TDA8362 IFI.
Maximum input signal up to 100 mV eff. The IF signal is demodulated using a reference carrier frequency generated by passive regeneration of the carrier image. The reference circuit of the demodulator is connected to pin 2 and 3 of the TDA8362. It is the only item that needs to be configured. The demodulator provides the ability to process IF signals with both negative and positive modulation. The automatic frequency control circuit (AFC) generates a signal at pin 44 of TDA8362, which provides tuning of the tuner local oscillator frequency with an error of no more than 50 kHz.
The circuit uses the same reference signal as for the demodulator.
The built-in sampling-storage circuit ensures the protection of the AFC circuit from the penetration of a video signal. A storage capacitor is built into the TDA8362. The steepness of the characteristics of the AFC circuit (33 mV / kHz) directly depends on the quality factor of the reference circuit. To reduce the steepness, a resistor is connected to pin 44 of the TDA8362. The output voltage range is 6 V (at a nominal frequency of 3.5 V). The characteristic of the AFC for the TDA8362-N5 modification is optimized for the European IF standard. The automatic gain control (AGC) circuit generates the control voltage of the amplifier and the tuner (vv. 47 TDA8362), ensuring a constant amplitude of the signals at the input of the amplifier and at the output of the video amplifier.
To exclude the influence of the AGC circuit on the tuner at low levels of the input signal, an AGC response delay is introduced. The delay value is regulated by applying a control voltage to pin 49 of the TDA8362. The voltage variation range is 0.5 ... 4.5 V. The minimum and maximum signal levels at pin 49, at which the tuner AGC is triggered, are 0.2 mV eff and 150 mV eff, respectively.
The AGC detector monitors the amplitude of the clock pulses with negative modulation of the IF signal and white peaks with positive modulation. To ensure noise immunity, the gating of the detector is used. Gating is disabled for the duration of the reverse frame scan. This allows you to avoid changing the amplitude of the video signal in the playback mode from the VCR due to phase shifts that occur during the switching of video heads. A capacitor (usually 2.2 μF) is connected to pin 48 of the TDA8362, which sets the time constant of the AGC circuit.

The external connection of this capacitor provides the flexibility of using the TDA8362. The permissible leakage current of the capacitor is 10 μA for negative and 200 nA for positive modulation. An increase in leakage current degrades the characteristics of the AGC circuit and leads to a change in the amplitude of the video signal during the field. The voltage at the output of the AGC circuit (vyv. 47) is at maximum gain (U pit +1) V and at minimum gain (saturation voltage) - 0.3 V.
Switching the demodulator and the AGC circuit to the IF signal processing mode with positive modulation is carried out by supplying voltage (U pit -1) V to pin 1 of TDA8362. The video signal identification circuit works independently of the synchronization circuit, which ensures that the setting is saved to the received television channel during translation TV to monitor mode.
The circuit generates the following signals at the output (pin 4 of TDA8362):

• voltage no more than 0.5 V in the absence of a video signal (in this case, the sound detector is turned off);
• voltage of 6 V when receiving a signal with a frequency of a subcarrier of color of 3.58 MHz;
• voltage of 8 V when receiving a signal with a frequency of a subcarrier of color 4.43 MHz.

In the modification of TDA8362-N5, an identification mode is provided for tuner detuning. To do this, when the signal is weak, the gating of the tuner AGC circuitry for the time of receiving horizontal synchronization pulses is disabled, which prevents erroneous identification of color subcarrier outbreaks by signals. The video amplifier provides amplification of the detected video signal, matching with the load and limiting noise emissions in the video signal.
The signal amplitude at the output (pin 7 of TDA8362) is 2.4 V. The output impedance of the amplifier is not more than 50 Ohms, the load current is not more than 5 mA. The bandwidth of the video amplifier (at the level of -3 dB) is up to 9 MHz, which makes it possible to use TDA8362 in all broadcasting standards. The emission control scheme provides the inversion of white peaks exceeding 4.8 V, noise emissions having a level below 1.4 V (the tops of the clock pulses have a level of 2 V), and their introduction into the video signal at 3.2 V and 2.6 V , respectively. At the same time, the noise emission inversion circuit only works during the reception of a large signal, since with a weak signal it negatively affects the operation of the audio signal processing channel.
In the modification of TDA8362-N4, an ultra-white peaks binding scheme is used in the video signal. The TDA8362-N5 modification does not use a white peak limiting scheme, since when there are a large number of white peaks, inverting and introducing them at 3.2 V results in the image becoming gray.

SOUND PROCESSING CHAIN

The sound signal to the second PC sound extracted from the full television signal is fed to pin 5 of the television processor (TDA8362). To the same output, a control voltage is supplied through the resistor to adjust the volume. The control voltage range is 0 ... 5 V.
The IF signal of the sound is limited and fed to the demodulator, made in the form of a phase locked loop (PLL). The PLL system is automatically tuned to the input frequency and does not require adjustments. The PLL system capture range is 4.2 ... 6.8 MHz.
The preliminary amplifier (PU) provides amplification of the detected sound signal to a level of 350 mV eff. This signal, which is not adjustable in magnitude, is fed to pin 1 of the TDA8362, to which an external capacitor is connected to correct the distortion of the sound signal, and to the switching and volume control circuitry. PU also provides mute when there is no identification of the video signal.
The signal from pin 1 of the TDA8362 is used to output to external connectors (for example, SCART). The sound signal from external connectors is fed to pin 6 of the TDA8362, its magnitude is 350 mV eff. The switching circuit, controlled by the voltage supplied to pin 16 of the TDA8362, provides for the output of pin 50 of the TDA8362 sound output signal, which then goes to the low-frequency amplifier.
The value of the output signal, which is -6 dB from the maximum is 700 mB eff, when adjusting the volume changes in the range of 80 dB. DC voltage at the terminal 50 TDA8362 3.3 V (when turning off the sound 10 ... 50 mB). The TDA8362-N5 modification provides click protection in the speakers when the sound is turned on, while using the previous TDA8362 modifications, a 290 kOhm resistor was needed between pin 1 of the TDA8362 and the +8 B bus to solve this problem.
Switching the TDA8362 to the signal processing mode with positive modulation is carried out by supplying at least 1 (U pit - 1) V to pin 1 of the TDA8362.

SYNCHRONIZATION CHAIN

The selection of clock pulses (SI) from the video signal arriving at vyv.13 or 15 TDA8362 is carried out by a selector containing an amplifier, an amplitude selector and a circuit for the selection of lowercase and frame SI.
Lower case SIs are supplied to the first phase detector (PD1) and a coincidence detector, which identifies the presence of a video signal and controls the synchronization of the master oscillator (ZG) of horizontal scanning. In the absence of synchronization, the voltage at pin 14 of the TDA8362 becomes low, which can be used to identify the presence of a video signal. PD1, together with a low-pass filter (LPF) connected to pin 40 of TDA8362, and a horizontal scan line generator form a PLL that provides frequency and phase adjustment of the pulse pulses to lower case SI parameters.
The time constant ФД1 is automatically switched (by switching internal resistance) according to the signals from the noise detector and from the coincidence detector. With an increase in the noise level in the video signal at pin 13 of TDA8362, the PD1 time constant increases (the output current is 30 μA). In the absence of a video signal, the time constant increases even more (output current 6 μA), which ensures synchronization in the on-screen display (OSD) mode.
When a normal signal is received, as well as when processing a signal fed to pin 15 of the TDA8362, the time constant decreases (output current 180 μA) to expand the capture band and increase the noise immunity of the synchronization circuit.
To ensure quick compensation of the phase error that occurs in the signal from the VCR when switching the video heads, the time constant is further reduced by about 1.5 times for the reverse scan time of the vertical scan (output current 270 μA). Thus, good synchronization circuit characteristics are achieved both in the case of receiving a weak signal and in the case of signal processing from a VCR.
The video signal span on pin 13 of the TDA8362 (including sync pulses) must be at least 2 V when a normal signal is received. Otherwise, the noise detector will switch the time constant at a lower IF signal level (switching occurs at a signal-to-noise ratio of 20 dB), which will lead to a “jitter” phase of the horizontal scanning signal.
To ensure the independence of the image phase from the horizontal frequency (15.625 or 15.734 kHz), the PD1 static characteristic has a very high slope. Horizontal scanning operates at a double horizontal scanning frequency. Its frequency is automatically calibrated using the tuning circuit by comparing it with the frequency of the generator with quartz stabilization of the color decoder. As a result, the frequency of free oscillations of the GB has a deviation of no more than 2% of the central value. At startup, calibration is always performed with 4.43 MHz quartz, unless the 3.58 MHz quartz forced mode is selected.
The second phase detector (FD2) ensures the formation of horizontal line triggering pulses on pin 37 of the TDA8362 and maintaining the phase of these pulses relative to 3G pulses in the capture mode in PD1. PD2 together with the low-pass filter connected to pin 39 of the TDA8362 and the 3G form a PLL. The initial phase of the image is set by changing the external load connected to pin 39 of TDA8362. The shift range is ± 2 μs when the control current changes within ± 6 μA. The horizontal flyback pulses necessary for the operation of PD2 are received at pin 38 of TDA8362.
At the same output, combined strobe pulses are formed, which are necessary for operation of integrated delay line microcircuits (TDA4661 or TDA4665) and SECAM decoder (TDA 8395).
Gating pulses have the following parameters:

• binding voltage during the reverse pulse: 3 ± 0.4 V;
• voltage during the quenching pulse: 2 ± 0.2 V;
• voltage during the color subcarrier flash: 5.3 ± 0.5 V;
• field blanking pulse width: 14 lines;
• flash highlight pulse width: 3.5 ± 0.2 μs.

When using the TDA8362 in question, X-ray protection can be implemented. For this, the external detector must provide switching of a constant voltage (at least 6 V) on pin 39 of TDA8362. In this case, the formation of horizontal line triggering pulses stops, and the voltage at pin 37 of the TDA8362 becomes approximately equal to the supply voltage. If the voltage on pin 39 returns to its normal level, then trigger pulses reappear on pin 37.
Parameters of pulses of start of horizontal scanning:

• lower level of output voltage: 0.3 V;
• maximum level: U pit;
• pulse duty cycle: 2;
• maximum permissible output current: 10 mA.

The launch of the horizontal scanning line is carried out by applying a voltage of 8 V to terminal 36 of the TDA8362 (minimum starting current of 6.5 mA). It should be noted that it is possible to start when the current is 5.5 mA. At the same time, calibration of the ZG is not carried out and its frequency will be higher than the nominal (maximum frequency deviation is 75%).
 In TDA8362-N5, the maximum trigger pulse frequency is limited to 20 kHz. When the voltage on pin 36 of TDA8362 decreases to 5.8, the formation of start pulses immediately stops. If the pre-start mode of the ЗГ is not used, then pin 36 and 10 of the TDA8362 are connected to the 8 V power bus. With separate power supply, the voltage at pin 36 must always be greater than or equal to the voltage at pin 10 of the TDA8362.

The control pulses for the HR horizontal scan, which is a sawtooth voltage generator, are obtained by dividing the frequency of the horizontal horizontal scan.
The frequency divider has two operating modes.
The “large window” mode is activated when there is no synchronization or when a non-standard signal is received (the number of lines in a half-frame is from 311 to 314 in 50 Hz mode and from 261 to 264 in 60 Hz mode). In this case, the divider is in search mode and switches from a frequency of 45 Hz to a frequency of 64.5 Hz.
The narrow window mode is activated when more than 15 consecutive frame sync pulses are detected.
This is the standard mode of operation. In the absence of clock pulses, the reverse motion of Zr turns on at the end of the half-frame (window), which ensures minimal image distortion.
The divider switches back to search mode if there are no frame sync pulses for 6 consecutive periods of frame scan. To pin 42 of TDA8362 is connected an external RC chain of a 3G frame scan.
The amplitude of the sawtooth voltage at pin 42 is 1.5 ... 1.8 V. At pin 41 of the TDA8362, reverse-frequency pulses of a vertical sweep (from the output stage) are applied to ensure the linearity of the output voltage.
The constant voltage on pin 41 is 2.5 ± 0.5 V, the alternating voltage is 1 V. In the TDA8362, the kinescope is protected against burn-through in the event of a frame scan failure, which dampens the rays when the direct voltage on pin 41 of the TDA8362 increases or decreases by 1 5 in (relative to the above). Framing control pulses are formed on pin 43 of TDA8362. The maximum and minimum voltage are respectively 4 and 0.3 V.
The maximum permissible output current is 1 mA. The delay in turning on the vertical scan at power-on is 140 ms, and the output voltage is high. When you start the HR frame scan is turned on at a frequency of 60 Hz.
In the TDA8362-N5 modification, the launch is carried out at a frequency of 50 Hz, which is used for the on-screen display. The voltage at pin 43 of the TDA8362 when turned on is low, which makes it easier to start the frame sweep.
TDA8362 synchronization circuit The TDA8362 provides reliable horizontal and frame synchronization of the image when processing a signal from a VCR, both in the case of phase displacement of the clock pulses (with a stretched tape), and in the case of playing back video tapes with copy protection.

TDA8362 VIDEO PROCESSING CIRCUIT
The full color television signal allocated on pin 7 of the TDA8362 passes notch filters to suppress the second intermediate frequency of the sound and goes to pin 13 of the TDA8362 (internal signal). On pin 15 of the TDA8362, a signal is supplied from external inputs (external signal).
The signal swing at pin 13 (including sync pulses) is 2 ... 2.8 V, and at pin 15 is TDA8362 1 ... 1.4 V. Switching the input video signal is carried out by a switching circuit controlled by voltage level on pin 16 of TDA8362 (U 16). At U 16 <0.5B, internal video and audio signals are processed (a notch filter that suppresses the color signal is turned on). With 3 <U16 <5V, external video and audio signals in the S-VHS standard are processed. In this case, a color signal is supplied to pin 16 of the TDA8362, and a brightness signal to pin 15. The notch filter is disabled in this mode. At U16> 7.5 V, external video and audio signals are processed (notch filter on).
The TDA8362 contains notch and bandpass filters to separate color and luminance signals.
The filter tuning scheme provides automatic adjustment of the filters in accordance with the frequency of the crystal oscillator included in the decoder. A pin 12 of the TDA8362 is connected to a decoupling capacitor of the tuning circuit.

In modification TDA8362-N5, the resonant frequency of the notch filter during signal processing in the SECAM system is reduced to 4.2 MHz to provide better suppression of the DR and DB subcarriers in the luminance signal. Filters are calibrated during the reverse frame scan. The luminance signal enters the delay line (480 ns) and the RF correction circuit, which provides an increase in the frequency response in the high-frequency region, and then to the matrixing circuit. pin 14 TDA8362 is used to control the RF correction circuit (image sharpness). The control voltage range is 0 ... 5 V. When a voltage of 7 V is applied to pin 14, the correction circuit is switched off (nominal mode). In the absence of a video signal, the current consumed by TDA8362 according to pin 14 increases to 1 mA (in versions N3 and N4 - up to 200 μA). The voltage on pin 14 is reduced. This information can be used to identify the video signal.

 The color signal is fed to a band-pass filter and an amplifier with AGC, and then to a decoder, which includes a generator with quartz frequency stabilization, a color difference signal demodulator (CRS), and a color off circuit.
The generator generating the signal of the reference subcarrier, the PD, and the low-pass filter connected to pin 33 of the TDA8362 form a PLL system that provides synchronization in frequency and phase of the signals of the reference subcarrier with a color burst signal (SCC). Quartz resonators are connected to pin 34 and 35 of the TDA8362, while a resonator with a frequency of 4.43 MHz is connected to pin 35. This frequency is used for calibrating 3G horizontal scanning, and to pin 34 - a resonator with a frequency of 3.58 MHz.
When using one quartz or connecting two quartz to one pin (usually to pin 34) and using an external switching circuit, pin 35, the TDA8362 is connected to the power bus through a 47 kOhm resistor. This ensures the forced inclusion of the generator.

When using modifications N4 and N5 TDA8362, the value of the resistor is reduced to 8.2 kOhm. This is essential to enable 3G line scan calibration. The system's automatic detection circuitry provides recognition of color signals in PAL and NTSC systems and switching of signal processing circuits.
To process the color signal in the SECAM system, a TDA8395 decoder is used, to which a 4.43 MHz reference signal is supplied from pin 32 of the TDA8362. The amplitude of the reference signal is 0.25 ± 0.5 V. In the case of identifying a color signal in a PAL or NTSC system, the voltage at pin 32 of the TDA8362 is 1.5 V. If there is no identification, the color scheme disables the outputs of the demodulator central circuit (pin 30 and 31) , and the voltage on pin 32 of the TDA8362 increases to 5 V. This voltage blocks the TDA8395 color shutdown circuit in m / s and connects its outputs to the central control system.

The current consumed by TDA8395 with pin 32 of TDA8362 when identifying a color signal in the SECAM system is 150 μA. Increasing the current to this value forces the TDA8362 to SECAM mode. In this case, the system automatic detection circuit does not search for color signals in PAL and SECAM systems. Forcing the TDA8362 to NTSC mode is not possible.

The color signal for the TDA8395 can be obtained on pin 27 of the TDA8362 by connecting this output to the power bus via a 4.7 ... 12 kΩ resistor. The signal span is 330 mV. This combination of chips can only be used as a PAL / SECAM decoder. In the case of color signals processing, PAL / SECAM / NTSC systems use an external color signal extraction circuit for TDA8395.

It should be noted that when using modifications N4 and N5 of TDA8362, to prevent erroneous identification of the signal from the video recorder in the SECAM system as NTSC, it is necessary to provide a voltage at the terminal 27 of TDA8362 of at least 6 V.

GENERAL DESCRIPTION
The TDA8360, TDA8361 and
TDA8362 are single-chip TV
processors which contain nearly all
small signal functions that are
required for a colour television
receiver. For a complete receiver the
following circuits need to be added:
a base-band delay line (TDA4661),
a tuner and output stages for audio,
video and horizontal and vertical
deflection.
Because of the different functional
contents of the ICs the set maker can
make the optimum choice depending
on the requirements for the receiver.
The TDA8360 is intended for simple
PAL receivers (all PAL standards,
including PAL-N and PAL-M are
possible).
The TDA8361 contains a PAL/NTSC
decoder and has an A/V switch.
For real multistandard applications
the TDA8362 is available. In addition
to the extra functions which are
available in the TDA8361, the
TDA8362 can handle signals with
positive modulation and it supplies
the signals which are required for the
SECAM decoder TDA8395.

FUNCTIONAL DESCRIPTION
Video IF amplifier
The IF amplifier contains
3 AC-coupled control stages with a
total gain control range of greater
than 60 dB. The sensitivity of the
circuit is comparable with that of
modern IF ICs.
The reference carrier for the video
demodulator is obtained by means of
passive regeneration of the picture
carrier. The external reference tuned
circuit is the only remaining
adjustment of the IC.
In the TDA8362 the polarity of the
demodulator can be switched so that
the circuit is suitable for both positive
and negative modulated signals.
The AFC circuit is driven with the
same reference signal as the video
demodulator. To ensure that the
video content does not disturb the
AFC operation a sample-and-hold
circuit is incorporated; the capacitor
for this function is internal. The AFC
output voltage is 6 V.
The AGC detector operates on levels,
top sync for negative modulated and
top white for positive modulated
signals.The AGC detector time
constant capacitor is connected
externally. This is mainly because of
the flexibility of the application.
The time constant of the AGC system
during positive modulation
(TDA8362) is slow, this is to avoid any
visible picture variations. This,
however, causes the system to react
very slowly to sudden changes in the
input signal amplitude.
To overcome this problem a speed-up
circuit has been included which
detects whether the AGC detector is
activated every frame period. If,
during a 3-frame period, no action is
detected the speed of the system is
increased. When the incoming signal
has no peak white information (e.g.
test lines in the vertical retrace period)
the gain would be video signal
dependent. To avoid this effect the
circuit also contains a black level
AGC detector which is activated when
the black level of the video signal
exceeds a certain level.
The TDA8361 and TDA8362 contain
a video identification circuit which is
independent of the synchronization
circuit. Therefore search tuning is
possible when the display section of
the receiver is used as a monitor. In
the TDA8360 this circuit is only used
for stable OSD at no signal input. In
the normal television mode the
identification output is connected to
the coincidence detector, this applies
to all three devices. The identification
output voltage is LOW when no
transmitter is identified. In this
condition the sound demodulator is
switched off (mute function). When a
transmitter is identified the output
voltage is HIGH. The voltage level is
dependent on the frequency of the
incoming chrominance signal.

Sound circuit
The sound bandpass and trap filters
have to be connected externally. The
filtered intercarrier signal is fed to a
limiter circuit and is demodulated by
means of a PLL demodulator. The
PLL circuit tunes itself automatically
to the incoming signal, consequently,
no adjustment is required.
The volume is DC controlled. The
composite audio output signal has an
amplitude of 700 mV RMS at a
volume control setting of -6 dB. The
de-emphasis capacitor has to be
connected externally. The
non-controlled audio signal can be
obtained from this pin via a buffer
stage. The amplitude of this signal is
350 mV RMS.
The TDA8361 and TDA8362 external
audio input signal must have an
amplitude of 350 mV RMS. The
audio/video switch is controlled via
the chrominance input pin.
Synchronization circuit
The sync separator is preceded by a
voltage controlled amplifier which
adjusts the sync pulse amplitude to a
fixed level. The sync pulses are then
fed to the slicing stage (separator)
which operates at 50% of the
amplitude.
The separated sync pulses are fed to
the first phase detector and to the
coincidence detector. The
coincidence detector is used for
transmitter identification and to detect
whether the line oscillator is
synchronized. When the circuit is not
synchronized the voltage on the
peaking control pin (pin 14) is LOW
so that this condition can be detected
externally. The first PLL has a very
high static steepness, this ensures
that the phase of the picture is
independent of the line frequency.
The line oscillator operates at twice
the line frequency.
The oscillator network is internal.
Because of the spread of internal
components an automatic adjustment
circuit has been added to the IC.
The circuit compares the oscillator
frequency with that of the crystal
oscillator in the colour decoder. This
results in a free-running frequency
which deviates less than 2% from the
typical value.
The circuit employs a second control
loop to generate the drive pulses for
the horizontal driver stage.
X-ray protection can be realised by
switching the pin of the second
control loop to the positive supply line.
The detection circuit must be
connected externally. When the X-ray
protection is active the horizontal
output voltage is switched to a high
level. When the voltage on this pin
returns to its normal level the
horizontal output is released again.
The IC contains a start-up circuit for
the horizontal oscillator. When this
feature is required a current of 6.5 mA
has to be supplied to pin 36. For an
application without start-up both
supply pins (10 and 36) must be
connected to the 8 V supply line.
The drive signal for the vertical ramp
generator is generated by means of a
divider circuit. The RC network for the
ramp generator is external.
Integrated video filters
The circuit contains a chrominance
bandpass and trap circuit. The filters
are realised by means of gyrator
circuits and are automatically tuned
by comparing the tuning frequency
with the crystal frequency of the
decoder.
In the TDA8361 and TDA8362 the
chrominance trap is active only when
the separate chrominance input pin is
connected to ground or to the positive
supply voltage and when a colour
signal is recognized.
When the pin is left open-circuit the
trap is switched off so that the circuit
can also be used for S-VHS
applications.
The luminance delay line and the
delay for the peaking circuit are also
realised by means of gyrator circuits.
Colour decoder
The colour decoder in the various ICs
contains an alignment-free crystal
oscillator, a colour killer circuit and
colour difference demodulators.
The 90° phase shift for the reference
signal is achieved internally. Because
the main differences of the 3 ICs are
found in the colour decoder the
various types will be discussed.

TDA8361
This IC contains an automatic
PAL/NTSC decoder. The conditions
for connecting the reference crystals
are the same as for the TDA8360.
The decoder can be forced to PAL
when the hue control pin is connected
to the positive supply voltage via a
5 kW or 10 kW resistor
(approximately). The decoder cannot
be forced to the NTSC standard. It is
also possible to see if a colour signal
is recognized via the saturation pin.
TDA8362
In addition to the possibilities of the
TDA8361, the TDA8362 can
co-operate with the SECAM add-on
decoder TDA8395.
The communication between the two
ICs is achieved via pin 32. The
TDA8362 supplies the reference
signal (4.43 MHz) for the calibration
system of the TDA8395, identification
of the colour standard is via the same
connection. When a SECAM signal is
detected by the TDA8395 the IC will
draw a current of 150 mA. When
TDA8362 has not identified a colour
signal in this condition it will go into
the SECAM mode, that means it will
switch off the R-Y and B-Y outputs
and increase the voltage level on PIN 32.


RGB output circuit
The colour difference signals are
matrixed with the luminance signal to
obtain the RGB signals. Linear
amplifiers have been chosen for the
RGB inputs so that the circuit is
suitable for incoming signals from the
SCART connector. The contrast and
brightness controls operate on
internal and external signals.
The fast blanking pin has a second
detection level at 3.5 V.
When this level is exceeded the
RGB outputs are blanked so that
“On-Screen-Display” signals can be
applied to the outputs.
The output signal has an amplitude of
approximately 4 V, black-to-white,
with nominal input signals and
nominal control settings. The nominal
black level is 1.3 V.



TDA3653B TDA3653C Vertical deflection and guard circuit (90°):

GENERAL DESCRIPTION
The TDA3653B/C is a vertical deflection output circuit for drive of various deflection systems with currents up to
1.5 A peak-to-peak.
Features
· Driver
· Output stage
· Thermal protection and output stage protection
· Flyback generator
· Voltage stabilizer
· Guard circuit

QUICK REFERENCE DATA
Note to the quick reference data
1. The maximum supply voltage should be chosen such that during flyback the voltage at pin 5 does not exceed 60 V.

 FUNCTIONAL DESCRIPTION
Output stage and protection circuit
Pin 5 is the output pin. The supply for the output stage is fed to pin 6 and the output stage ground is connected to pin 4.
The output transistors of the class-B output stage can each deliver 0.75 A maximum.
The maximum voltage for pin 5 and 6 is 60 V.
The output power transistors are protected such that their operation remains within the SOAR area. This is achieved by
the co-operation of the thermal protection circuit, the current-voltage detector, the short-circuit protection and the special
measures in the internal circuit layout.
Driver and switching circuit
Pin 1 is the input for the driver of the output stage. The signal at pin 1 is also applied via external resistors to pin 3 which
is the input of a switching circuit. When the flyback starts, this switching circuit rapidly turns off the lower output stage
and so limits the turn-off dissipation. It also allows a quick start of the flyback generator.
External connection of pin 1 to pin 3 allows for applications in which the pins are driven separately.
Flyback generator
During scan the capacitor connected between pins 6 and 8 is charged to a level which is dependent on the value of the
resistor at pin 8 (see Fig.1).
When the flyback starts and the voltage at the output pin (pin 5) exceeds the supply voltage, the flyback generator is
activated.
The supply voltage is then connected in series, via pin 8, with the voltage across the capacitor during the flyback period.
This implies that during scan the supply voltage can be reduced to the required scan voltage plus saturation voltage of
the output transistors.
The amplitude of the flyback voltage can be chosen by changing the value of the external resistor at pin 8.
It should be noted that the application is chosen such that the lowest voltage at pin 8 is > 2.5 V, during normal operation.
Guard circuit
When there is no deflection current and the flyback generator is not activated, the voltage at pin 8 reduces to less than
1.8 V. The guard circuit will then produce a DC voltage at pin 7, which can be used to blank the picture tube and thus
prevent screen damage.
Voltage stabilizer
The internal voltage stabilizer provides a stabilized supply of 6 V to drive the output stage, which prevents the drive
current of the output stage being affected by supply voltage variations.













PACKAGE OUTLINES
TDA3653B: 9-lead SIL; plastic (SOT110B); SOT110-1; 1996 November 25.
TDA3653C: 9-lead SIL; plastic power (SOT131); SOT131-2 November 25.
PARAMETER SYMBOL MIN. TYP. MAX. UNIT
Supply (note 1)
Supply voltage range
pin 9 VP = V9-4 10 - 40 V
pin 6 V6-4 - - 60 V
Output (pin 5)
Peak output voltage during flyback V5-4M - - 60 V
Output current I5(p-p) - 1.2 1.5 A
Operating junction temperature range Tj -25 - +150 °C
Thermal resistance junction to mounting base
(SOT110B) Rth j-mb - 10 - K/W
(SOT131) Rth j-mb - 3.5 - K/W.