Memory - 24C02
SMPS - TDA4601 & S2000A
TR Chopper - FM2051 / OR49-110
SAW - G1961
Secam - TEA5640F
Video - TEA5040
VIF - TDA4427A
Vertical - TDA8170
Sound - TDA1013B
SIF - U829B
Tuner -
TV/AV - HCF4053
Tube - A59ECF10X05
FBT -
HOT - S2000A
RGB Amp. - TEA5101A
IC remote - IRT1250
Other ICs - TBA2800, TDA8185I, HCF4060
Power supply Description based on TDA4601d (SIEMENS)
TDA4601 Operation. * The TDA4601 device is a single in line, 9 pin chip. Its predecessor was the TDA4600 device, the TDA4601 however has improved switching, better protection and cooler running. The (SIEMENS) TDA4601 power supply is a fairly standard parallel chopper switch mode type, which operates on the same basic principle as a line output stage. It is turned on and off by a square wave drive pulse, when switched on energy is stored in the chopper transformer primary winding in the form of a magnetic flux; when the chopper is turned off the magnetic flux collapses, causing a large back emf to be produced. At the secondary side of the chopper transformer this is rectified and smoothed for H.T. supply purposes. The advantage of this type of supply is that the high chopping frequency (20 to 70 KHz according to load) allows the use of relatively small H.T. smoothing capacitors making smoothing easier. Also should the chopper device go short circuit there is no H.T. output. In order to start up the TDA4601 I.C. an initial supply of 9v is required at pin 9, this voltage is sourced via R818 and D805 from the AC side of the bridge rectifier D801, also pin 5 requires a +Ve bias for the internal logic block. (On some sets pin 5 is used for standby switching). Once the power supply is up and running, the voltage on pin 9 is increased to 16v and maintained at this level by D807 and C820 acting as a half wave rectifier and smoothing circuit. PIN DESCRIPTIONS Pin 1 This is a 4v reference produced within the I.C. Pin 2 This pin detects the exact point at which energy stored in the chopper transformer collapses to zero via R824 and R825, and allows Q1 to deliver drive volts to the chopper transistor. It also opens the switch at pin 4 allowing the external capacitor C813 to charge from its external feed resistor R810. Pin 3 H.T. control/feedback via photo coupler D830. The voltage at this pin controls the on time of the chopper transistor and hence the output voltage. Normally it runs at Approximately 2v and regulates H.T. by sensing a proportion of the +4v reference at pin 1, offset by conduction of the photo coupler D830 which acts like a variable resistor. An increase in the conduction of transistor D830 and therefor a reduction of its resistance will cause a corresponding reduction of the positive voltage at Pin 3. A decrease in this voltage will result in a shorter on time for the chopper transistor and therefor a lowering of the output voltage and vice versa, oscillation frequency also varies according to load, the higher the load the lower the frequency etc. should the voltage at pin 3 exceed 2.3v an internal flip flop is triggered causing the chopper drive mark space ratio to extend to 244 (off time) to 1 (on time), the chip is now in over volts trip condition. Pin 4 At this pin a sawtooth waveform is generated which simulates chopper current, it is produced by a time constant network R810 and C813. C813 charges when the chopper is on and is discharged when the chopper is off, by an internal switch strapping pin 4 to the internal +2v reference, see Fig 2. The amplitude of the ramp is proportional to chopper drive. In an overload condition it reaches 4v amplitude at which point chopper drive is reduced to a mark-space ratio of 13 to 1, the chip is then in over current trip. The I.C. can easily withstand a short circuit on the H.T. rail and in such a case the power supply simply squegs quietly. Pin 4 is protected by internal protection components which limit the maxi
mum voltage at this pin to 6.5v. Should a fault occur in either of the time constant components, then the chopper transistor will probably be destroyed. Pin 5 This pin can be used for remote control on/off switching of the power supply, it is normally held at about +7v and will cause the chip to enter standby mode if it falls below 2v. Pin 6 Ground. Pin 7 Chopper switch off pin. This pin clamps the chopper drive voltage to 1.6v in order to switch off the chopper. Pin 8 Chopper base current output drive pin. Pin 9 L.T. pin, approximately 9v under start-up conditions and 16v during normal running, Current consumption of the I.C. is typically 135mA. The voltage at this pin must reach 6.7v in order for the chip to start-up.
Semiconductor circuit for supplying power to electrical equipment, comprising a transformer having a primary winding connected, via a parallel connection of a collector-emitter path of a transistor with a first capacitor, to both outputs of a rectifier circuit supplied, in turn, by a line a-c voltage; said transistor having a base controlled via a second capacitor by an output of a control circuit acted upon, in turn by the rectified a-c line voltage as actual value and by a reference voltage; said transformer having a first secondary winding to which the electrical equipment to be supplied is connected; said transformer having a second secondary winding with one terminal thereof connected to the emitter of said transistor and the other terminal thereof connected to an anode of a first diode leading to said control circuit; said transformer having a third secondary winding with one terminal thereof connected, on the one hand, via a series connection of a third capacitor with a first resistance, to the other terminal of said third secondary winding and connected, on the other hand, to the emitter of said transistor, the collector of which is connected to said primary winding; a point between said third capacitor and said first resistance being connected to the cathode of a second diode; said control circuit having nine terminals including a first terminal delivering a reference voltage and connected, via a voltage divider formed of a third and fourth series-connected resistances, to the anode of said second diode; a second terminal of said control circuit serving for zero-crossing identification being connected via a fifth resistance to said cathode of said second diode; a third terminal of said control-circuit serving as actual value input being directly connected to a divider point of said voltage divider forming said connection of said first terminal of said control circuit to
said anode of said second diode; a fourth terminal of said control circuit delivering a sawtooth voltage being connected via a sixth resistance to a terminal of said primary winding of said transformer facing away from said transistor; a fifth terminal of said control circuit serving as a protective input being connected, via a seventh resistance to the cathode of said first diode and, through the intermediary of said seventh resistance and an eighth resistance, to the cathode of a third diode having an anode connected to an input of said rectifier circuit; a sixth terminal of said control circuit carrying said reference potential and being connected via a fourth capacitor to said fourth terminal of said control circuit and via a fifth capacitor to the anode of said second diode; a seventh terminal of said control circuit establishing a potential for pulses controlling said transistor being connected directly and an eighth terminal of said control circuit effecting pulse control of the base of said transistor being connected through the intermediary of a ninth resistance to said first capacitor leading to the base of said transistor; and a ninth terminal of said control circuit serving as a power supply input of said control circuit being connected both to the cathode of said first diode as well as via the intermediary of a sixth capacitor to a terminal of said second secondary winding as well as to a terminal of said third secondary winding.
Such a blocking oscillator switching power supply is described in the German periodical, "Funkschau" (1975) No. 5, pages 40 to 44. It is well known that the purpose of such a circuit is to supply electronic equipment, for example, a television set, with stabilized and controlled supply voltages. Essential for such switching power supply is a power switching transistor i.e. a bipolar transistor with high switching speed and high reverse voltage. This transistor therefore constitutes an important component of the control element of the control circuit. Furthermore, a high operating frequency and a transformer intended for a high operating frequency are provided, because generally, a thorough separation of the equipment to be supplied from the supply naturally is desired. Such switching power supplies may be constructed either for synchronized or externally controlled operation or for non-synchronized or free-running operation. A blocking converter is understood to be a switching power supply in which power is delivered to the equipment to be supplied only if the switching transistor establishing the connection between the primary coil of the transformer and the rectified a-c voltage is cut off. The power delivered by the line rectifier to the primary coil of the transformer while the switching transistor is open, is interim-stored in the transformer and then delivered to the consumer on the secondary side of the transformer with the switching transistor cut off.
In the blocking converter described in the aforementioned reference in the literature, "Funkschau" (1975), No. 5, Pages 40 to 44, the power switching transistor is connected in the manner defined in the introduction to this application. In addition, a so-called starting circuit is provided. Because several diodes are generally provided in the overall circuit of a blocking oscillator according to the definition provided in the introduction hereto, it is necessary, in order not to damage these diodes, that due to the collector peak current in the case of a short circuit, no excessive stress of these diodes and possibly existing further sensitive circuit parts can occur.
Considering the operation of a blocking oscillator, this means that, in the event of a short circuit, the number of collector current pulses per unit time must be reduced. For this purpose, a control and regulating circuit is provided. Simultaneously, a starting circuit must bring the blocking converter back to normal operation when the equipment is switched on, and after disturbances, for example, in the event of a short circuit. The starting circuit shown in the literature reference "Funkschau" on Page 42 thereof, differs to some extent already from the conventional d-c starting circuits. It is commonly known for all heretofore known blocking oscillator circuits, however, that a thyristor or an equivalent circuit replacing the thyristor is essential for the operation of the control circuit.
It is accordingly an object of the invention to provide another starting circuit. It is a further object of the invention to provide a possible circuit for the control circuit which is particularly well suited for this purpose. It is yet another object of the invention to provide such a power supply which is assured of operation over the entire range of line voltages from 90 to 270 V a-c, while the secondary voltages and secondary load variations between no-load and short circuit are largely constant.
With the foregoing and other objects in view, there is provided, in accordance with the invention, a blocking oscillator-type switching power supply for supplying power to electrical equipment wherein a primary winding of a transformer, in series with an emitter-collector path of a first bipolar transistor, is connected to a d-c voltage obtained by rectification of a line a-c voltage fed-in via two external supply terminals, a secondary winding of the transformer being connectible to the electrical equipment for supplying power thereto, the first bipolar transistor having a base controlled by the output of a control circuit acted upon, in turn, by the rectified a-c line voltage as actual value and by a set-point transmitter, and including a starting circuit for further control of the base of the first bipolar transistor, including a first diode in the starting circuit having an anode directly connected to one of the supply terminals supplied by the a-c line voltage and a cathode connected via a resistor to an input serving to supply power to the control circuit, the input being directly connected to a cathode of a second diode, the second diode having an anode connected to one terminal of another secondary winding of the transformer, the other secondary winding having another terminal connected to the emitter of the first bipolar transmitter.
In accordance with another
feature of the invention, there is provided a second bipolar
transistor having the same conduction type as that of the first
bipolar transistor and connected in the starting circuit with the base
thereof connected to a cathode of a semiconductor
diode, the semiconductor diode having an anode connected to the
emitter of the first bipolar transistor, the second bipolar
transistor having a collector connected via a resistor to a cathode
of the first diode in the starting circuit, and having an emitter
connected to the input serving to supply power to the control circuit
and also connected to the cathode of the second diode which is
connected to the other secondary winding of the transformer. In accordance with a further feature of the invention, the base of the second bipolar transistor is connected to a resistor and via the latter to one pole of a first capacitor, the anode of the first diode being connected to the other pole of the first capacitor.
In accordance with an added feature of the invention, the input serving to supply power to the control circuit is connected via a second capacitor to an output of a line rectifier, the output of the line rectifier being directly connected to the emitter of the first bipolar transistor.
In accordance with an additional feature of the invention, the other secondary winding is connected at one end to the emitter of the first bipolar transistor and to a pole of a third capacitor, the third capacitor having another pole connected, on the one hand, via a resistor, to the other end of the other secondary winding and, on the other hand, to a cathode of a third diode, the third diode having an anode connected via a potentiometer to an actual value input of the control circuit and, via a fourth capacitor, to the emitter of the first bipolar transistor.
In accordance with yet another feature of the invention, the control circuit has a control output connected via a fifth capacitor to the base of the first bipolar transistor for conducting to the latter control pulses generated in the control circuit.
In accordance with a concomitant feature of the invention, there is provided a sixth capacitor shunting the emitter-collector path of the first transistor.
Other features which are considered as characteristic for the invention are set forth in the appended claim.
Although the invention is illustrated and described herein as embodied in a blocking oscillator type switching power supply, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
TEA5040 (THOMSON / TELEFUNKEN) WIDE BAND VIDEO PROCESSOR
DESCRIPTION
The U4647 - TEA5040S is a serial bus-controlled videoprocessing
device which integrates a complex architecture
fulfilling multiple functions.
1. In a television receiver having a luminance processing channel for translating instantaneous luminance signals derived from received broadcast transmissions to an image reproducer, said luminance signals including black level reference information, an automatic contrast control circuit comprising in combination:
2. An automatic contrast control circuit in accordance with claim 1, wherein adjustable level shifting means are interposed between said amplifier stage and said average detector means, said adjustable level shifting means providing a contrast control for manually varying the average DC level of said luminance signals.
3. An automatic contrast control circuit in accordance with claim 1, wherein said average detector means includes a capacitor having an output terminal coupled to said amplifier stage and a second terminal coupled to a plane of reference potential, said capacitor being charged by luminance signals from said amplifier stage and developing control signals representative of the average DC level of said luminance signals.
4. An automatic contrast control circuit in accordance with claim 3, wherein said control signals with respect to a plane of reference potential are equal to the potential at which black level is stabilized minus the potential drop between black level and the average DC level of said luminance information, said control signal increasing with respect to said plane of reference potential responsive to decreasing average DC levels of said luminance signals and decreasing responsive to increasing average DC levels.
5. An automatic contrast control circuit in accordance with claim 3, wherein said peak detector means includes a semi-conductor arrangement for providing said capacitor with a low impedance discharge path whenever said brightness components exceed a predetermined threshold level, the impedance of said discharge path being dependent on the amplitude of said brightness components and the discharge interval of said semiconductor arrangement being the time period during which said brightness components exceed said threshold level, said semiconductor arrangement further decreasing said control signals with respect to said plane of reference potential irrespective of the average DC level of said luminance signals.
6. An automatic contrast control circuit in accordance with claim 5, wherein said semiconductor arrangement comprises first and second transistors, said luminance signals from said amplifier stage being coupled to the input base electrode of said first transistor, said first transistor further having an emitter electrode coupled to said capacitor output terminal and a collector electrode coupled to the base electrode of said second transistor, said second transistor having a collector electrode coupled to said capacitor output terminal and an emitter electrode coupled to said plane of reference potential, said semiconductor arrangement being conductive to provide said capacitor with a low impedance discharge path whenever said brightness components exceed the base-emitter junction breakdown voltage of said first transistor.
7. An automatic contrast control circuit in accordance with claim 6, wherein said gain-controlled luminance amplifier stage includes a pair of transistors arranged in a differential amplifier configuration, the gain of which is dependent on the bias applied to the base electrodes of said transistors.
9. An automatic contrast control circuit in accordance with claim 3, wherein said beam current limiter means provide a low impedance discharge path for said capacitor whenever the beam current exceeds a predetermined level.
10. An automatic contrast control system in accordance with claim 9, wherein said beam current limiter means monitors pulses from a voltage multiplier high-voltage system, said pulses being proportional to the beam current generated during the previous horizontal scan line.
11. An automatic contrast control circuit in accordance with claim 10, wherein said beam current limiter means comprises a transistor having a base electrode coupled to said voltage multiplier high-voltage system, an emitter electrode coupled to a plane of reference potential and a collector electrode coupled to said capacitor, said transistor providing a low impedance discharge path whenever said pulses exceed the base-emitter junction breakdown voltage of said transistor.
This invention relates in general to control circuitry for color television receivers and more particularly to an automatic contrast control circuit incorporated in the luminance processing channel. In accordance therewith, a variable DC control signal is derived from the luminance signal information as a function of the average luminance level. The DC control signal is applied to a gain-controlled amplifier stage in the luminance channel, varying its gain and thereby insuring that excessive beam currents will not be generated due to high average luminance levels. Conversely, the circuit is effective to increase the gain of the amplifier stage when under-modulated signals are received thereby providing the desired contrast level. When the white content of the instantaneous received signal exceeds a predetermined level, however, the DC control signal is modified to reflect the excessive white content even though the average luminance level may be low. Accordingly, the amplifier stage's gain is reduced to prevent defocusing.
In color television receivers, the various elemental areas of differing brightness levels, or shades, in the televised image correspond to the amplitude levels of the instantaneous brightness components of the luminance signals which, together with the chrominance signal, reproduce the transmitted picture information on the image display tube. The intensity of the electron beams developed in the receiver's image display tube are varied, for the most part, according to the detected amplitude levels of the instantaneous luminance signals. Accordingly, progressively higher amplitude levels generate higher intensity electron beams and, consequently, progressively lighter shades. In addition, suitable viewer-adjustable controls are customarily provided in the television receiver whereby a particularized contrast and brightness setting may be selected according to viewer preference.
It is desirable that the level of the luminance signal component corresponding to black in the televised image be maintained at the cut-off of the image reproducer. But even in those instances where there is a measure of DC coupling, the DC components of the luminance signal coupled from the video detector to the luminance channel may be degraded or otherwise restricted due to the nature of the processing circuitry as well as to other factors. Moreover, the luminance processing channel itself may well permit a degradation or undesirable shift in the desired DC characteristics. The result is that the DC level in the processed luminance signal is not properly maintained, such that, upon application to the image display tube, the black level is shifted to some undesirable reference. This leads to less than faithful half-tone reproduction on the screen of the image display tube. Gray tones can be lost simply because they are beyond the cut-off of the display tube. In other instances, blacks may appear as grays on the image display tube screen.
Thus, it is desirable to make provision for the maintenance of black level in the televised image at some stabilized reference. Various systems are of course known in the art for accomplishing this objective and take various forms and configurations. For example, an arrangement commonly known as a DC restorer circuit which includes a clamping device may be employed. However, when the black level is effectively stabilized at the image reproducer's cut-off bias point, the average level of the luminance signal information may reach the point where excessive average beam currents capable of severely damaging the image reproducer are generated. In addition, the high voltage power supply during instances of high beam current may be incapable of delivering the required beam current. Such overloading reduces the power supply output voltage and results in undesirable "focus blooming." That is, there will be a loss of brightness, reduction of horizontal widths and severe defocusing of the reproduced image. The problem in this regard has been further compounded by the "new generation" high-brightness cathode-ray tubes which require higher beam currents in order to illuminate the tube to its fullest capability during high-modulation (white) scenes. In view of the added demands on the high voltage power supply and the danger of damaging the image display tube, some method for effectively limiting the beam current is required.
Accordingly, automatic contrast control systems have been developed which reduce the gain of the luminance amplifier stage to prevent the generation of excessive beam currents or increase the gain when under-modulated signals are received. Most of these prior art automatic contrast control systems, however, measure only the average level of the luminance signals to derive the control signal utilized to vary the gain of the luminance amplifier. Consequently, when all or a major portion of the luminance signal's white content is of a high amplitude level and is concentrated on a very small portion of the image reproducer's screen, the control signal derived from the average luminance level is low, permitting the luminance amplifier stage to operate at nearly maximum gain. By concentrating the high-amplitude white content into a small area of the screen, the image display tube is likely to be overdriven during that period of time and "focus blooming" will result. Some automatic contrast systems, on the other hand, derive a control signal based on the peak amplitudes of the instantaneous luminance signals without regard to the average luminance level. Thus, while preventing blooming on high-amplitude white content, such systems are susceptible to luminance signals which have a dangerously high average level, but do not have any peak white signal content of a level where the system would take corrective action.
OBJECTS OF THE INVENTION
Accordingly, it is an object of the present invention to provide a color television receiver having black level stabilization with a new and improved automatic contrast control circuit which effectively overcomes the aforenoted disadvantages and deficiencies of prior circuits.
A further object of the invention is to provide an improved automatic contrast control circuit which develops control signals effectively varying the gain of a luminance amplifier stage to maintain an optimum contrast, while preventing the generation of excessive beam currents in the cathode-ray tube.
A more particular object of the invention is to provide an improved automatic contrast control circuit for continuously monitoring the average (DC) level of the luminance signal information and providing a control signal representative thereof to vary the gain of a luminance amplifier stage while remaining sensitive to the amplitude levels of brightness components exceeding a threshold level and modifying the control signal in accordance therewith.
Another object of the invention is to provide an improved automatic contrast control circuit which increases the gain of a luminance amplifier stage during reception of undermodulated luminance signals.
A further object of the present invention is to provide an automatic contrast control circuit of the foregoing type for deriving a variable DC control potential from applied luminance signals which, upon application to the luminance channel, adjusts the gain of a luminance amplifier stage in accordance with the varying luminance signal requirements.
Still another object of the invention is to provide a luminance processing channel including automatic contrast control circuitry which may be fabricated as a monolithic integrated circuit to provide an output luminance signal having stabilized black level and optimum contrast without producing excessive beam currents.
SUMMARY OF THE INVENTION
In accordance with the present invention, an improved automatic contrast control circuit is provided for varying the gain of an amplifier stage in the luminance processing channel of a color television receiver whenever the average DC level of the input luminance information varies from a desired level, or whenever the peak amplitudes of the AC brightness components of the luminance information exceed a predetermined threshhold level. In a preferred embodiment, the automatic contrast control circuit includes a gain-controlled luminance amplifier stage in a luminance processing channel for translating instantaneous luminance signals derived from received broadcast transmissions to an image reproducer. The amplified luminance signals found at the output of the amplifier stage have a stabilized black level. There are also provided detector means coupled to the amplifier output for developing control signals that are representative of the average DC level of the instantaneous luminance signals. The control signals are then applied to the gain-controlled amplifier stage to vary its gain inversely with changes in the average luminance level. Finally, peak limiter means are coupled between the amplifier output and the detector means to modify the control signals whenever the instantaneous luminance signals exceed a threshhold level. The modified control signals are similarly utilized to effect inverse gain variations in the gain-controlled amplifier stage regardless of the average level of the luminance signals.
.DIGITAL CONTROL OF BRIGHTNESS,
SATURATION AND CONTRAST ON TV SIGNALS
AND R, G, B INTERNAL OR EXTERNAL
SOURCES .BUS DRIVE OF SWITCHING FUNCTIONS .DEMATRIXING OF R, G, B SIGNALS FROM
Y, R-Y, B-Y, TV MODE INPUTS .MATRIXING OF R, G, B SOURCES INTO
Y, R-Y, B-Y SIGNALS .AUTOMATIC DRIVE AND CUT-OFF CONTROLS
BY DIGITAL PROCESSING DURING
FRAME RETRACE .PEAK ANDAVERAGE BEAM CURRENT LIMITATION
.ON-CHIP SWITCHING FOR R, G, B INPUT
SELECTION .ON-CHIP INSERTION OF INTERNAL OR EXTERNAL
R, G, B SOURCES
GENERAL DESCRIPTION
Brief Description
This integrated circuit incorporates the following
features :
- a synchro and two video inputs
- a fixed video output
- a switchable video output
- normal Y, R-Y, B-Y TV mode inputs
- double set of R, G, B inputs
- brightness, contrast and saturation controls as
wellon aR,G, B picture ason a normalTVpicture
- digital control inputs by means of serial bus
- peak beam current limitation
- average beam current limitation
- automaticdrive and cut-off controls
Block Diagram Description
BUS DECODER
A 3 lines bus (clock, data, enable) delivered by the
microcontroller of the TV-set enters the videoprocessor
integrated circuit (pins 13-14-15). A control
system acts in such a way that only a 9-bit word is
taken intoaccount by the videoprocessor.Six of the
bits carry the data, the remaining three carry the
address of the subsystem.
A demultiplexer directs the data towards latches
which drive the appropriate control. More detailed
information about serial bus operation is given in
the following chapter.
Video Switch
The video switch has three inputs :
- an internal video input (pin 39),
- an external video input (pin 37),
- a synchro input (pin 41),
and two outputs :
- an internal video output (pin 40),
- a switchable video output (pin 42)
The 1Vpp composite video signal applied to the
internal video input is multiplied by two and then
appears as a 2Vpp low impedance composite
video signal at the output. This signal is used to
deliver a 1Vpp/75W composite video signal to the
peri-TV plug.
The switchable video output canbe any of the threeinputs.When the Int/Ext one active bit word is high
(address number 5), the internal video input is
selected. If not, either a regeneratedsynchro pulse
or the external video signal is directed towards this
output depending on the level of the Sync/Async
one active bit word (address number 4). As this
output is to be connected to the synchro integrated
circuit, RGB information derived from an external
source via the Peri-TV plug canbedisplayed on the
screen, the synchronization of the TV-set being
then made with an external video signal.
When RGB information is derived from a source
integrated in the TV-set, a teletext decoder for
example, the synchronization can be made either
on the internal video input (in case of synchronous
data) or on the synchro input (in case of asynchronous
data).
R, G, B Inputs
There are two sets of R, G, B inputs : one is to be
connected to the peri-TV plug (Ext R, G, B), the
second one to receive the information derived from
the TV-set itself (Int R, G, B).
In order to have a saturation control on a picture
coming from the R, G, B inputs too, it is necessary
to getR-Y, B-Y and Y signals from R, G, B information
: this is performed on the first matrix that
receives the three 0.9Vp (100% white) R, G, B
signals and delivers the corresponding Y, R-Y, B-Y
signals. These ones are multiplied by 1.4 in order
to make the R-Y and B-Y signals compatible with
the R-Y and B-Y TV mode inputs. The desired R,
G, B inputs are selected by means of 3 switches
controlled by the two fast blanking signal inputs. A
high level on FB external pin selects the external
RGB sources. The three selected inputs are
clamped in order to give the required DC level at
the output of this firstmatrix. Thethree not selected
inputs are clamped on a fixed DC level.
Y, R-Y, B-Y Inputs
The 2Vpp composite video signal appearing at the
switchable output of the video switch (pin 42) is
driven through the subcarrier trap and the luminance
delay line with a 6 dB attenuation to the Y
input (1Vpp ; pin 12). In order to make this 1Vpp
(synchro to white) Y signal compatible with the
1Vpp (black to white) Y signal delivered by the first
matrix, it is necessary to multiply it by a coefficient
of 1.4.
Controls
The four brightness, contrastand saturationcontrol
functions are direct digitally controlled without using
digital-to-analog converters.
The contrast control of the Y channel is obtained
by means of a digital potentiometer which is an
attenuator including several switchable cells directly
controlled by a 5 active bit word (address
number 1). The brightness control is also made by
a digital potentiometer (5 active bit word, address
number 0). Since a + 3dB contrast capability is
required, the Y signal value could be up to 0.7Vpp
nominal. For both functions, the control characteristics
are quasi-linear.
In each R-Y and B-Y channel, a six-cell digital
attenuator is directly controlled by a 6 active bit
word (address number 6 and 7). The tracking
needed to keep the saturation constant when
changing the contrast has to be done externally by
the microcontroller. Furthermore, colour can be
disabledby blankingR-Y andB-Ysignals using one
active bit word (address number 2) to drive the
one-chip colour ON/OFF switch.
Second Matrix, Clamp, Peak Clipping, Blanking
The second matrix receives the Y, R-Y and B-Y
signals and delivers the corresponding R, G, B
signals. As it is required to have the capability of +
6dB saturation, an internal gain of 2 is applied on
both R-Y and B-Y signals.
A low clipping level is included in order to ensure a
correct blanking during the line and frame retraces.
Ahigh clipping level ensures thepeakbeamcurrent
limitation. These limitations are correct only if the
DC bias of the three R, G, B signals are precise
enough. Therefore a clamp has been added in
each channel in order to compensate for the inaccuracy
of the matrix.
Sandcastle Detector And Counter
The three level supersandcastle is used in the
circuit to deliver the burst pulse (CLP), the horizontal
pulse (HP), and the composite vertical and
horizontal blanking pulse (BLI). This last one is
regenerated in the counter which delivers a new
composite pulse (BL) in which the vertical part lasts
23 lines when the vertical part of the supersandcastle
lasts more than 11 lines.
The TEA5040S cannot work properly if this minimum
duration of 11 lines is not ensured.
The counterdelivers different pulses neededcircuit
and especially the line pulses 17 to 23 used in the
Automatic Drive And Cut-off Control System
Cut-off and drive adjustments are no longer required
with this integrated circuit as it has a sample
and hold feedback loop incorporating the final
stages of the TV-set. This system works in a sequentialmode.
For this purpose, special pulses are
inserted in G, R and B channels. During the lines
17, 18 and 19, a ”drive pulse” is inserted respectively
in the green, red and blue channels. The line
20 is blanked on the three channels. During the
lines 21, 22 and 23, a ”quasi cut-off pulse” is
inserted respectively in the green, red and blue
guns.
The resulting signal is then applied to the input of
a voltage controlled amplifier. In the final stages of
the TV-set, the current flowing in each green, red
and blue cathode is measured and sent to the
videoprocessorby a current source.
The three currents are added together in a resistor
matrix which can be programmed to set the ratio
between the three currents in order to get the
appropriate colour temperature. The output of the
matrix forms a high impedance voltage source
which is connectedto the integratedcircuit (pin 34).
Same measurement range between drive and cutoff
is achieved by internally grounding an external
low impedance resistor during lines 17, 18 and 19.
This is due to the fact that the drive currents are
about one hundred times higher than the cut-off
and leakage currents.
Each voltage appearing sequentially on the wire
pin 34 is then a function of specific cathode current
:
- When a current due to a drive pulse occurs, the
voltage appearing on the pin 34 is compared
within the IC with an internal reference, and the
result of the comparison charges or discharges
an external appropriate drive capacitor which
stores the value during the frame. This voltage is
applied to a voltage controlled amplifier and the
system works in such a waythat the pulse current
drive derived from the cathode is kept constant.
- During the line 20, the three guns of the picture
tube are blanked. The leakagecurrent flowing out
of the final stages is transformed into a voltage which is stored by an external leakage capacitor
to be used later as a reference for the cut-off
current measurement.
- When a current due to a cut-off pulse occurs, the
voltage appearing on the pin 34 is compared
within the ICto the voltagepresenton the leakage
memory. Anappropriate externalcapacitor is then
charged or discharged in such a way that the
difference between each measured current and
the leakage current is kept constant, and thus the
quasi cut-off current is kept constant.
AverageBeam Current Limitation
The total current of the three guns is integrated by
means of an internal resistor and an external capacitor
(pin 36) and thencompared with a programmable
voltage reference(pin 38). When 70% of the
maximum permitted beam current is reached, the
drive gain begins to be reduced ; to do so, the
amplitude of the inserted pulse is increased.
In order to keep enough contrast, the maximum
drive reduction is limited to 6dB. If it is not sufficient,
the brightness is suppressed.
SPECIFICATION FOR THE THOMSON BI-DIRECTIONAL
DATA BUS
This is a bi-directional 3-wire (ENABLE, CLOCK,
DATA) serial bus. The DATA line transmission is
bi-directional whereas ENABLE and CLOCK lines
are only microprocessor controlled. The ENABLE
and CLOCK lines are only driven by the microcomputer.
TDA8185 HORIZONTALAND VERTICAL PROCESSOR:
503kHz REFERENCE OSCILLATOR
5.5V SUPPLY VOLTAGE INTERNALLY
REGULATED
VERY SOPHISTICATED SYNC. SEPARATOR
COUNTDOWN TIMING LOGIC
ADAPTS AUTOMATICALLY TO
LINE/50Hz AND 525 LINE/60Hz STANDARDS
50/60 Hz IDENTIFICATION OUTPUT
AUTOMATIC VERTICAL AMPLITUDE CORRECTION
50/60Hz
CRT PROTECTION CIRCUIT
PHASE-CORRECTED HORIZONTAL OUTPUT
WITH CONSTANT DUTY CYCLE.
DESCRIPTION
The TDA8185 is a monolithic integrated circuit in
24 pins dual in line plastic package intended for TV
signal processing and driving Horizontal and Vertical
output stages. It was specially designed for
VCR working conditions.
TDA8170
TDA8170 TV VERTICAL DEFLECTION OUTPUT CIRCUIT:DESCRIPTION
The TDA8170 is a monolithic integrated circuit in
HEPTAWATT packa
ge. It is a high efficiency
power booster for direct driving of verticalwindings
of TV yokes. It is intended for use in Colour and B
&Wtelevision receivers as well as in monitorsand
displays.
The functions incorporated are :
.POWERAMPLIFIER
.FLYBACKGENERATOR
.REFERENCE VOLTAGE
.THERMAL PROTECTION
The power dissipated in the circuit must be removed
by adding an external heatsink.
Thanks to the HEPTAWATTTM package attaching
the heatsink is very simple, a screwa compression
spring (clip) being sufficient. Betweenthe heatsink
andthe packageit isbetter to insert a layerof silicon
grease, to optimizethe thermal contact ; no electrical
isolation is needed between the two surfaces.
ABSOLUTE MAXIMUMRATINGS
Symbol Parameter Value Unit
VS Supply Voltage (pin 2) 35 V
V5, V6 Flyback Peak Voltage 60 V
V3 Voltage at Pin 3 + Vs
V1, V7 Amplifier Input Voltage + Vs, – 0.5 V
Io Output Peak Current (non repetitive, t = 2 msec) 2.5 A
Io Output Peak Current at f = 50 or 60 Hz, t 3 10 msec 3 A
Io Output Peak Current at f = 50 or 60 Hz, t > 10 msec 2 A
I3 Pin 3 DC Current at V5 < V2 100 mA
I3 Pin 3 Peak to Peak Flyback Current at f= 50 or 60 Hz, tfly 31.5msec 3 A
Ptot Total Power Dissipation at Tcase = 90 °C 20 W
Tstg, Tj Storage and Junction Temperature – 40, +150 °C
Typically, a vertical deflection circuit of, for example, a television receiver includes an amplifier referred to as the vertical amplifier having a push-pull output stage. An output terminal of the push-pull output stage is coupled to a series arrangement of a vertical deflection winding, a DC blocking capacitor and a deflection current sampling resistor for producing a vertical deflection current in the series arrangement. A sawtooth feedback voltage developed in the sampling resistor and a sawtooth input voltage are coupled to an input of the amplifier to form a closed loop feedback operation mode, during vertical trace.
During vertical retrace, one of the transistors of the push-pull output stage operates as a switch to couple a boosted-up supply voltage to the deflection winding that causes the deflection current to reverse its polarity. After the deflection current reverses its polarity and attains approximately a peak value, that transistor begins operating as an amplifier stage and the vertical amplifier operates again in the closed loop feedback operation mode. Thus, vertical trace is resumed.
CHASSIS EUROMONO SCHEMATIC / CIRCUIT DIAGRAM:
TEA5101A - RGB HIGH VOLTAGE AMPLIFIER BASIC OPERATION AND APPLICATIONS:
GENERALThe control of state-of-the-art color cathode ray tubes requires high
performance video amplifiers which must satisfy both tube and video processor
characteristics. When considering tube characteristics (see Fig- ures 13 and
14),we note that a 130V cutoff voltage is necessary to ensure a 5mA peak
current.How- ever 150V is a more appropriate value if the satu- ration effect of
the amplifier is to be taken into account. As the dispersion range of the three
guns is ± 12%, the cutoff voltage should be adjustable from 130V to 170V. The G2
voltage, from 700 to 1500V allows overall adjustment of the cutoff volt- age for
similar tube types. A 200V supply voltage of the video amplifier is necessary to
achieve a correct blanking operation. In addition, the video amplifier should
have an output saturation voltage drop lower than 15V, as a drive voltage of
130V (resp. 115V) is necessary to obtain a beam current of 4 mA for a gun which
has a cutoff point of 170V (resp. 130V). Note : For all the calculations
discussed above, the G1 voltage is assumed to be 0V. The video processor
characteristics must also be considered. As it generally delivers an output
volt- age of 2 to 3V, the video amplifier must provide a closed loop DC g ain of
approximately 40. The video amplifier dynamic performances must also meet the
requirements of good definition even with RGB input signals (teletext,home
computer...), e.g. 1mm resolution on a 54cm CRT width scanned in 52µs.
Consequently, a slew rate better than 2000V/µs, i.e. rise and fall times lower
than 50ns, is needed. In addition, transition times must be the same for the
three channels so as to avoid coloured transitions when displaying white
characters. The bandwidth of a video amplifier satisfying all these requirements
must be at least 7MHz for high level signals and 10MHz for small signals. One
major feature of a video amplifier is its capa- bility to monitor the beam
current of the tube. This function is necessary with modern video proces- sors:
- for automatic adjustment of cutoff and also, where required,video gain in
order to improve the long term performances by compensation for aging effects
through the life of the CRT. This adjust- ment can be done either sequentially
(gun after gun) or in a parallel mode. - for limiting the average beam current A
video amplifier must also be flashover protected and provide high crosstalk
performances. Cros- stalk effects are mainly caused by parasitic capaci- tors
and thus increase with the signal frequency. A crosstalk level of -20dB at 5MHz
is generally ac- ceptable. Table 1 summarizes the main features of a high
performance video amplifier. Table 1 : Main Features of a High Performance Video
Amplifier Maximum Supply Voltage 220V Output voltage swing "Average" 100V Output
voltage swing "Peak" 130V Low level saturation (refered to VG1) 15V Closed loop
gain 40 Transition time 50ns Large signal bandwidth 7MHz Small signal bandwidth
10MHz Beam current monitoring Flash over protection Crosstalk at 5MHz -20d B The
SGS-THOMSON Microelectronics TEA5101A is a high performance and large bandwidth
3 chan- nel video amplifier which fulfills all the criteria dis- cussed above.
Designed in a 250V DMOS bipolar technology, it operates with a 200V power supply
and can deliver 100V peak-to-peak output signals with rise and fall times equal
to 50ns. The 5101A features a large signal bandwidth of 8MHz, which can be
extended to 10MHz for small signals (50 Vpp). Each channel incorporates a PMOS
transistor to monitor the beam current. The circuit provides internal protection
against electrostatic discharges and high voltage CRT discharges. The best
utilization of the TEA 5101A high perform- ance features such as dynamic
characteristics, crosstalk,or flashover protection requires opti- mized
application implementation. This aspect will be discussed in the fourth part of
this document. I.1 - Input Stage The differential input stage consists of the
transistor T1 and T2 and the resistors R4,R5 and R6. This stage is biased by a
voltage source T3,R1,R2 and R3. VB(T1) = (1 + R2 R3) x VB(T3) ≅ 3.8V Each
amplifier is biased by a separate voltage source in order to reduce internal
crosstalk. The load of the input stage is composed of the transistor T4 (cascode
configuration) and the resistor R7. The cascode configuration has been chosen so
as to reduce the Miller input capacitance. The voltage gain of the input stage
is fixed by R7 and the emitter degenerati on resistors R5,R6,and the T1,T2
internal emitter resistances. The voltage gain is approxi- mately 50dB. Using a
bipolar transistor T4 and a polysilicon re- sistor R7 gives rise to a very low
parasitic capaci- tance at the output of this stage (about 1.5pF). Hence the
rise and fall times are about 50ns for a 100V peak-to-peak signal (between 50V
and 150V). I.2 - Output Stage The output stage is a quasi-complementary class B
push-pull stage. This design ensures a symetrical load of the first stage for
both rising and falling signals. The positive output stage is made of the DMOS
transistor T5,and the negative output stage is made of the transistors PMOS T6
and DMOS T7. The compound configuration T6-T7 is equivalent to a single PMOS. A
single PMOS transistor capable of sinking the total current would have been too
large. By virtue of the symetrical drive properties of the output stage the rise
and fall times are equal (50ns for 100V DC output voltage). I.3 - Beam Current
Monitoring This function is performed by the PMOS transistor T8 in source
follower configuration. The voltage on the source (cathode output) follows the
gate volt- age (feedback output). The beam current is ab- sorbed via T8 . On the
drain of T8, this current will be monitored by the videoprocessor. I.4 -
Protection Circuits I.4.1 - MOS protection Four zener diodes DZ(1-4) are
connected between gate and source of each MOS in order to prevent the voltage
from reaching the breakdown volt- age.Hence the VGS voltage is internally
limited to ± 15V. I.4.2 - Protection against electrostatic dis- charges All the
input/output pins of the TEA5101A are pro- tected by the diodes D1-D7 which
limit the overvol- tage due to ESD. I.4.3 - Flashover Protection A high voltage
and high current diode D5 is con- nected between each output and the high
voltage power supply. During a flash, most of the current is generally absorbed
by the spark gap connected to the CRT socket. The remaining current is absorbed
by the high voltage decoupling capacitor through the diode D5. Hence the cathode
voltage is clamped to the supply voltage and the output volt- age does not
exceed this value. I.1 - Voltage Amplifier II.1.1 - Bias conditions Vin = Vref
The bias point is fixed by the feedback resistor Rf,the bias resistor Rp, and by
the internal refer- ence voltage when Vin = Vref. If VO is the output voltage
(pin 9) : VO = (1 + Rf Rp) x Vref (1) In this state T1 and T2 are conducting. A
current flows in R7 and T4 soT5 is on. The T5 drain current is fed to the
amplifier input through the feedback resistor. The current in R7 is: I(R7) = VDD
− VO − VGS(T5) R7 ≅ VDD − VO R7 and the current in T5 and Rf is : I(T5) = VO −
Vref Rf ≅ VO Rf Thus the total current absorbed by each channel of the TEA5101A
is : VDD R7 + VO x (1 Rf − 1 R7) The cathode (pin 7) output voltage is: VO +
VGS(T8) = VO The beam current is absorbed by T8 and Rm. The voltage developed
across Rm by this current is fed to the videoprocessor in order to monitor the
beam current. II.1.2 - Dynamic operation The TEA5101A operates as a closed loop
amplifier, with its voltage gain fixed by the resistors Rf and Re. Since the
open loop gain A is not infinite, the resistor Rp and the input impedance Rin
must be consid- ered.Hence the voltage gain is G = − Rf Re x 1 1 + 1 A (1 + Rf
Rp ⁄ ⁄ Re ⁄ ⁄ Rin) (2) II.1.2.1 - Input voltage Vin < Vref (black picture) In
this case the current flowing in R7 and T1 de- creases whilst the collector
voltage of T4 and the output voltage both increase. In the extreme case, I(T1) =
I(R7) = 0 and VO= VDD-VGS(T5) In order to charge the tube capacitor the voltage
is fed to the cathode output in two ways: - through the PMOS (with a VGS
difference) for the low frequency part - through the capacitor C for the high
frequency part (output signal leading e dge) To correctly transmit the rising
edge, the value of the capacitor C must be high compared to CL. With the current
values used (C = 1nF,CL = 10pF), the attenuation is very small (0.99) II.1.2.2 -
Input voltage Vin > Vref (white picture) In this case,the current in R7 and T1
increases with an accompanying drop of T4’s collector voltage until T1 and T4
are saturated. At this point: VO ≅ VC(T4) ≅ VCC During a high to low transition
(i.e. black-white picture), the beam current is absorbed in two ways: - through
the capacitor C and the compound PMOS T6-T7 for the high frequency part (falling
edge) - through the PMOS T8 and the resistor Rm for the low frequency part. II.2
- Beam Current Monitoring II.2.1 - Stationary state The beam current monitoring
is performed by the PMOS T8 and the resistor Rm. When measuring low currents
(leakage, quasi cutoff),the Rm value is generally high. When measuring high
currents (drive, average or peak beam current),Rm is gen- erally bypassed by a
lower impedance. It should be noted that the current supplied by the three guns
flows through this resistor.Hence,with too large a value for the resistor Rm,the
cathode voltage of the tubes will become too high for the required operating
current values.This is a funda- mental difference between the TEA5101A and dis-
crete video amps. In discrete video amps, the current monitoring transistor is a
high voltage PNP bipolar which may saturate. In this case the beam current can
flow through the transistor base and it is no longer monitored by the video
processor. This effect does not occur with the TEA 5101A. II.2.2 - Transient
phase : low current measure- ments The cut-off adjustment sequence is generally
as follows: In a first step, the cathode is set to a high voltage (180V) in
order to blank the CRT and to measure the leakage current. In a second step, the
tube is slighly switched on to measure a very low current (quasi cut-off
current). This operation is performed by setting the cathode voltage to about
150V and adjusting it until the proper current is obtained. The maximum time
available to do this operation is generally about 52µs. Figure 3 shows the
simplified diagram of the TEA5101A output, the voltages during the different
steps,and the stationary state the system must reach for correct adjustment. I.1
- Voltage Amplifier II.1.1 - Bias conditions Vin = Vref The bias point is fixed
by the feedback resistor Rf,the bias resistor Rp, and by the internal refer-
ence voltage when Vin = Vref. If VO is the output voltage (pin 9) : VO = (1 + Rf
Rp) x Vref (1) In this state T1 and T2 are conducting. A current flows in R7 and
T4 soT5 is on. The T5 drain current is fed to the amplifier input through the
feedback resistor. The current in R7 is: I(R7) = VDD − VO − VGS(T5) R7 ≅ VDD −
VO R7 and the current in T5 and Rf is : I(T5) = VO − Vref Rf ≅ VO Rf Thus the
total current absorbed by each channel of the TEA5101A is : VDD R7 + VO x (1 Rf
− 1 R7) The cathode (pin 7) output voltage is: VO + VGS(T8) = VO The beam
current is absorbed by T8 and Rm. The voltage developed across Rm by this
current is fed to the videoprocessor in order to monitor the beam current.
II.1.2 - Dynamic operation The TEA5101A operates as a closed loop amplifier,
with its voltage gain fixed by the resistors Rf and Re. Since the open loop gain
A is not infinite, the resistor Rp and the input impedance Rin must be consid-
ered.Hence the voltage gain is G = − Rf Re x 1 1 + 1 A (1 + Rf Rp ⁄ ⁄ Re ⁄ ⁄
Rin) (2) II.1.2.1 - Input voltage Vin < Vref (black picture) In this case the
current flowing in R7 and T1 de- creases whilst the collector voltage of T4 and
the output voltage both increase. In the extreme case, I(T1) = I(R7) = 0 and VO=
VDD-VGS(T5) In order to charge the tube capacitor the voltage is fed to the
cathode output in two ways: - through the PMOS (with a VGS difference) for the
low frequency part - through the capacitor C for the high frequency part (output
signal leading edge) To correctly transmit the rising edge, the value of the
capacitor C must be high compared to CL. With the current values used (C =
1nF,CL = 10pF), the attenuation is very small (0.99) II.1.2.2 - Input voltage
Vin > Vref (white picture) In this case,the current in R7 and T1 increases with
an accompanying drop of T4’s collector voltage until T1 and T4 are saturated. At
this point: VO ≅ VC(T4) ≅ VCC During a high to low transition (i.e. black-white
picture), the beam current is absorbed in two ways: - through the capacitor C
and the compound PMOS T6-T7 for the high frequ ency part (falling edge) -
through the PMOS T8 and the resistor Rm for the low frequency part. II.2 - Beam
Current Monitoring II.2.1 - Stationary state The beam current monitoring is
performed by the PMOS T8 and the resistor Rm. When measuring low currents
(leakage, quasi cutoff),the Rm value is generally high. When measuring high
currents (drive, average or peak beam current),Rm is gen- erally bypassed by a
lower impedance. It should be noted that the current supplied by the three guns
flows through this resistor.Hence,with too large a value for the resistor Rm,the
cathode voltage of the tubes will become too high for the required operating
current values.This is a funda- mental difference between the TEA5101A and dis-
crete video amps. In discrete video amps, the current monitoring transistor is a
high voltage PNP bipolar which may saturate. In this case the beam current can
flow through the transistor base and it is no longer monitored by the video
processor. This effect does not occur with the TEA 5101A. II.2.2 - Transient
phase : low current measure- ments The cut-off adjustment sequence is generally
as follows: In a first step, the cathode is set to a high voltage (180V) in
order to blank the CRT and to measure the leakage current. In a second step, the
tube is slighly switched on to measure a very low current (quasi cut-off
current). This operation is performed by setting the cathode voltage to about
150V and adjusting it until the proper current is obtained. The maximum time
available to do this operation is generally about 52µs. Figure 3 shows the
simplified diagram of the TEA5101A output, the voltages during the different
steps,and the stationary state the system must reach for correct adjustment. I.1
- Voltage Amplifier II.1.1 - Bias conditions Vin = Vref The bias point is fixed
by the feedback resistor Rf,the bias resistor Rp, and by the internal refer-
ence voltage when Vin = Vref. If VO is the output voltage (pin 9) : VO = (1 + Rf
Rp) x Vref (1) In this state T1 and T2 are conducting. A current flows in R7 and
T4 soT5 is on. The T5 drain current is fed to the amplifier input through the
feedback resistor. The current in R7 is: I(R7) = VDD − VO − VGS(T5) R7 ≅ VDD −
VO R7 and the current in T5 and Rf is : I(T5) = VO − Vref Rf ≅ VO Rf Thus the
total current absorbed by each channel of the TEA5101A is : VDD R7 + VO x (1 Rf
− 1 R7) The cathode (pin 7) output voltage is: VO + VGS(T8) = VO The beam
current is absorbed by T8 and Rm. The voltage developed across Rm by this
current is fed to the videoprocessor in order to monitor the beam current.
II.1.2 - Dynamic operation The TEA5101A operates as a closed loop amplifier,
with its voltage gain fixed by the resistors Rf and Re. Since the open loop gain
A is not infinite, the resistor Rp and the input impedance Rin must be consid-
ered.Hence the voltage gain is G = − Rf Re x 1 1 + 1 A (1 + Rf Rp ⁄ ⁄ Re ⁄ ⁄
Rin) (2) II.1.2.1 - Input voltage Vin < Vref (black picture) In this case the
current flowing in R7 and T1 de- creases whilst the collector voltage of T4 and
the output voltage both increase. In the extreme case, I(T1) = I(R7) = 0 and VO=
VDD-VGS(T5) In order to charge the tube capacitor the voltage is fed to the
cathode output in two ways: - through the PMOS (with a VGS difference) for the
low frequency part - through the capacitor C for the high frequency part (output
signal leading edge) To correctly transmit the rising edge, the value of the
capacitor C must be high compared to CL. With the current values used (C =
1nF,CL = 10pF), the attenuation is very small (0.99) II.1.2.2 - Input voltage
Vin > Vref (white picture) In this case,the current in R7 and T1 increases with
an accompanying drop of T4’s collector voltage until T1 and T4 are saturated. At
this point: VO ≅ VC(T4) ≅ VCC During a high to low transition (i.e. black-white
picture), the beam current is absorbed in two ways: - through the capacitor C
and the compound PMOS T6-T7 for the high frequency part (falling edge) - through
the PMOS T8 and the resistor Rm for the low frequency part. II.2 - Beam Current
Monitoring II.2.1 - Stationary state The beam current monitoring is performed by
the PMOS T8 and the resistor Rm. When measuring low currents (leakage, quasi
cutoff),the Rm value is generally high. When measuring high currents (drive,
average or peak beam current),Rm is gen- erally bypassed by a lower impedance.
It should be noted that the current supplied by the three guns flows through
this resistor.Hence,with too large a value for the resistor Rm,the cathode
voltage of the tubes will become too high for the required operating current
values.This is a funda- mental difference between the TEA5101A and dis- crete
video amps. In discrete video amps, the current monitoring transistor is a high
voltage PNP bipolar which may saturate. In this case the beam current can flow
through the transistor base and it is no longer monitored by the video
processor. This effect does not occur with the TEA 5101A. II.2.2 - Transient
phase : low current measure- ments The cut-off adjustment sequence is generally
as follows: In a first step, the cathode is set to a high voltage (180V) in
order to blank the CRT and to measure the leakage current. In a second step, the
tube is slighly switched on to measure a very low current (quasi cut-off
current). This operation is performed by setting the cathode voltage to about
150V and adjusting it until the proper current is obtained. The maximum time
available to do this operation is generally about 52µs. Figure 3 shows the
simplified diagram of the TEA5101A output, the voltages during the different
steps,and the stationary state the system must reach for correct adjustment.
During the blanking phase, the tube is switched off, the PMOS is switched off
and its VGS voltage is equal to the pinch-off voltage (about 1.5V). The voltages
at the different nodes are shown in figure 3 (V(9) = 180V, V(k) = 181.5V). The
falling edge of the cutoff pulse is instantaneously transmitted by the capacitor
C. When the stationary state is reached, the cathode voltage will be 152.5V if
the voltage on pin 9 is 150V, as the VGS voltage of the conducting PMOS is about
2.5V. We can see that the voltage on C must increase by an amount of ∆Vc = 1V.
This charge is furnished by the tube capacitor which is discharged by an amount
of ∆VCL = 29V with a time constant equal to R x CL (10 ns). By considering the
energy balance, we can calculate the maximum charge ∆Vmax that CL can furnished
to C ∆Vmax = √CL C x ∆VCL ≅ 3V Since this voltage is greater than ∆VC, the
capacitor C can be charged and the stationary state is reached without any
contribution being required from the tube current,i.e. the whole tube current
can flow through the PMOS and the adjustment can be performed correctly.
Considering higher voltage and beam current swings, the margin is greater
because: - the voltage swing across the tube capacitor is greater - the tube
current is higher and the picture is not disturbed even if part of the beam
current is used to charge the capacitor C.
ITT TVPO2066 TV Controller with On-Screen Display for TV Receivers.
Introduction In comparison to the older TVPO 2065 hardware, the port 3 of the TVPO 2066 consists of 6 x 12 V/2 mA open– drain outputs instead of 5 V/25 mA open–drain outputs. “TVPO 2066” is the name of the unprogrammed hard- ware. The programmed versions will be called: – TVPO 2066–Axx for analog TV–sets – TVPO 2066–Dxx for digital TV–sets with the version–no. xx. Application diagrams and de- scriptions of different software versions are available in additional data sheets. The TVPO 2066 is an intelligent microcomputer in N– channel MOS technology. On one silicon chip, it con- tains all operating and tuning functions of a modern TV receiver. Thus, along with the non–volatile memory (MDA 2062, NVM 3060), the SAA 1250, IRT 1250 or IRT 1260 remote–control transmitter and the TBA 2800 pre- amplifier this offers a very economic solution for TV re- ceivers with on–screen display and voltage synthesizer. The device is available in 44–pin PLCC package and 40–pin DIL package. The PLCC version has 4 pins more for digital combined inputs/outputs. 2. The Functional Blocks of the TVPO 2066 The hardware components of the TVPO 2066 are: – 8048–core, fully compatible to 8048 instruction set – 10K ROM, 256 byte RAM – four 64 steps analog output to control vol., color etc. – single 4032 steps analog output for controlling of a VS–tuner – IR decoder for ITT–IR (remote control with IRT 1250/60) – mains flip–flop for standby mode – IM–bus interface for non–volatile memory and devices of DIGIT 2000 system for digital video–processing. – fast counter input (T1) for automatic search (for analog TV–sets) – 12 digital combined inputs/outputs (8 or 10 for DIL– package) – 8 digital outputs – integrated 12–digit on–screen display 2.1. The 8049 Microcomputer For the description of the commands and characteristics of the 8049, please refer to the CCU 2030, CCU 2050, CCU 2070 data sheet. The 8049 provides separate address space for program, data, in/out, and external data. The ROM is organized in banks of 2 K Bytes. Bank 0 occupies the addresses 0 to 2047. The other banks (10, 11, 12, 13) share the ad- dresses 2048 to 4095. The different banks are selected through the bank select register 15 as described for the CCU 2070 in the CCU 2030, 2050, 2070 data sheet. Banks 14 through 17 of the CCU 2070 are not available in the TVPO. The data and control registers of the TVPO’s peripheral units are located in the address space of external data. They are accessed by the “Move External” instruction (MOVX). Electrically, the connection is provided by the lines DB0 to DB7, RD, WR, and ALE. These connections of the 8049 microcomputer are not available during nor- mal operation. In “Test Mode” (EA = 5 V or EA = 12 V), some pins are switched so that the TVPO’s peripherals can be accessed from the outside via DB0 to DB7. In normal operation, only P2 of the 8049’s original ports remains unchanged. During test operation, RD, WR, ALE and PSEN are connected to P24 to P27 (compare CCU 2030, CCU 2050, CCU 2070 data sheet). 2.2. The Remote–Control Decoder In the already mentioned standby mode, and also during normal operation, the remote–control decoder expects infrared–transmitted signals that were transmitted by the SAA 1250, IRT 1250 or IRT 1260 remote–control transmitter IC, received by an infrared photo diode, and amplified by the TBA 2800 infrared preamplifier IC. The decoder frees the remote–control signal from interfer- ence and decodes each command word that is recog- nized as correct. A valid command word is made avail- able to the microcomputer by way of two registers. No interrupt is initiated. Rather, it is the task of the program to continuously check the infrared registers. A command word transmitted via infrared consists of 10 bits – four address bits and six data bits. These two parts of the command word are provided in two different regis- ters. Bit 7 in the address register is low when a valid com- mand word is detected. When the data word is read, both infrared registers are cleared. It is possible to mask–program which infrared com- mands also carry the power–on information and switch the TVPO from standby to full operation. For this pur- pose, up to five groups of commands within a binary de- coder matrix are programmable for one infrared address (compare CCU 2030, CCU 2050, CCU 2070 data sheet). 2.3. The Mains Flip–Flop and Reset Circuit Mains flip–flop and reset circuit operate from the stand- by supply. After switching on the standby supply it takes 100 ms at most until the TVPO is in full standby opera- tion. The Mains output is controlled by the mains flip– flop. In the “Mains off” position the output is high. The mains flip–flop is set by means of the infrared “Mains on” commands or by an active low level applied to the Mains output for at least 20 µs. A reset for the mains flip–flop is generated whenever: 1. The standby supply voltage is less than approx. 3.5 V (e.g. during power–on) 2. The microcomputer executes a “Mains off” command. The microcomputer clears the mains flip–flop by writing a 1 into bit 3 of the external register 13. In order to proper- ly charge the stray capacitances at the Mains output, the mains flip–flop remains blocked in the “Mains off” posi- tion for 16 ms after any reset. After this time has elapsed, the TV set may be turned on again. With no Reset option set (compare CCU 2030, CCU 2050, CCU 2070 data sheet), the mains flip–flop is also reset by any Reset signal going low. The TVPO–internal Reset’, which is different from the externally–applied Reset is high only when both Mains is in the low state and Reset is at high level. Two options are mask–pro- grammable in this respect: Reset 1: The Reset signal, going low, does not reset the mains flip–flop. If the customer does not specify, this op- tion will be set as default. Reset 2: The TVPO–internal Reset’ is identical to the Reset signal and independent of the state of the mains flip–flop. Resetting the mains flip–flop clears the remote–control decoder. The other parts of the TVPO are cleared by the TVPO–internal Reset’ signal via the Reset input. Delay- ing the Reset signal with respect to the VDD supply volt- age is done by an external RC network at the Reset in- put. The input voltage of the regulator for the 5 V VDD supply voltage should be monitored to prevent the system’s cir- cuits from resetting improperly and the NVM 3060 EE- PROM from programming false data. With no Reset option set, any spike or excessive noise present on the Reset line may cause the mains flip–flop to be reset. In such cases, a ceramic filter capacitor should be provided near the Reset pin. 2.4. The IM–Bus and Non–Volatile–Memory It is by means of this part of the circuit that the TVPO 2066 communicates with the non–volatile memory (MDA 2062 or NVM 3060) which stores the tuning and analog data, acquired during the Memo procedure and the options. The IM–Bus consists of three lines Clock, Ident and Data. Clock and Ident are unidirectional sig- nals from the TVPO 2066 to the memory (and to the VSP–processor in case of a digital TV set), and Data is bidirectional for transferring the data in both directions. In addition, the MDA 2062 (not the NVM 3060) requires a memory clock signal which is issued from the TVPO 2066 (approx. 1 kHz). All these signals on the IM–Bus have TTL level. In the nonoperative state all three bus lines are high. The start of a telegram is initiated when Ident and Data are low. Data takeover occurs at the posi- tive edge of Clock. For a detailed description of the IM– Bus protocol please refer to the data sheet of the MDA 2062 or NVM 3060. 2.5. The Clock Generator and the Sequence Control For the purpose of generating the clock signals required to operate the TVPO 2066 the chip contains an oscillator which is designed for crystals in the frequency range from 3.5 to 4.5 MHz. For the exact requirement of “off– timer” and “sleep–timer” functions, a 4 MHz crystal is needed. The crystal is connected to the ‘Xtal’ input. All timing specification in this data sheet relate to a crystal frequency of 4 MHz. With other crystal frequencies, there will be corresponding variations. 2.6. The D/A Converters for the Analog Outputs The TVPO 2066 provides four analog outputs for adjust- ment of the TV’s basic settings (e.g. volume and for ana- log TV sets additional brightness, contrast and color sat- uration). These control voltages are made available as pulse/pause modulated signals, where the ratio can be varied in 64 steps. The needed DC level signal is ob- tained by means of a simple RC lowpass filter. 2.7. The Tuning Voltage Generator The tuning voltage for the capacitance diodes of the TV tuner is generated as a pulse/interval modulated signal by a modified rate multiplier. The range of variation of the pulse/interval ratio extends from 0 (no pulses) to infinity (continuous signal) with a resolution of 4032 steps. At a clock frequency of 4 MHz the basic period of the rate multiplier is 0.5 ms which results in tolerable filter expen- diture. 2.8. The Ports The TVPO 2066 has two ports (Port 2 and Port 3) which are used by the software versions as control outputs/in- puts for a keyboard, band selection, multi–standard indi- cators, multi–video indicators and AFC switch. The PLCC version of the TVPO 2066 has in addition four pins of Port 1 (P14...P17). The DIL version of the TVPO 2066 is also available in other pinnings: the D/A conver- ter DA3 and DA4 can be exchanged to port input/out- puts. DA3 to Port 1, Bit 5 (P15) and DA4 to Port 1, Bit 6 (P16). This possibility is very useful in digital TV sets, be- cause in this case only one D/A converter is needed for volume control. 2.9. The On–Screen Display 2.9.1. Outputs and Inputs for the OSD The OSD is an additional hardware module on the TVPO 2066 chip, which allows the display of 12 different characters such as the program number and analog val- ues (volume, brightness etc.) on a TV screen. The TVPO 2066 software controls the OSD through a set of 16 ex- ternal write registers. The TVPO 2066 delivers four additional output signals: – R_out character signal red (1 Vpp) – G_out character signal green (1 Vpp) – B_out character signal blue (1 Vpp) – FB_out fast blanking (TTL level) Fast blanking is used for switching between video and OSD signals and shows the validity of the R, G, B out- puts. For synchronization and to place the display, the TVPO 2066 needs two additional input signals: – H_in horizontal synchronization (TTL level) – V_in vertical synchronization (TTL level) 2.9.2. Display Format The OSD generates a rectangular display block, which contains 2 rows of 6 characters each (see Fig. 2–1). The characters are addressed depending on their position within this display block. Each address is attached to one TVPO 2066 register. The content of each register describes the character type and its color. Pin Descriptions for 44–Pin PLCC Pin 1 – Vsup This pin must be connected to the positive of the 5 V sup- ply. Pin 2 – Ground This pin must be connected to the negative of the supply. Pin 3 – Vstb: Standby Supply pin +5 V Via this pin, clock oscillator, reset circuit and remote– control decoder are powered. By means of this, it is pos- sible to switch on the TV receiver by remote control. The standby consumption is very small. Pins 4 to 7, 8 to 21 – Port P2, Bits 0 to 7 The internal configuration of these in/outputs is shown in Fig. 4–3. Direct data transfer with the µC can be ex- ecuted via this port. The push–pull outputs drive one TTL gate. Pins 8 to 11 – Port P1, Bits 4 to 7 The internal configuration of these in/outputs is shown in Fig. 4–4. Direct data transfer with the µC can be ex- ecuted via this port. The outputs are open–drain with a 12 V rating. Four outputs are available in the 44–pin PLCC package. In the 40–pin DIL package up to two P1–outputs (instead of analog outputs) are available by changing the bonding. Pins 12 and 13 – Vertical and Horizontal synchronization Inputs These inputs are shown in Fig. 4–5. They are used to synchronize the on–screen display. Negative pulses are needed. The internal delayed–clock–generator for the OSD section synchronizes to the positive edge of the Hin signal. Pin 14 – Fast Blank Output This output, which is shown in Fig. 4–6, is used to stop the normal display, and thus characters can be dis- played on the screen. Pins 15 to 17 – Video Outputs Red, Green and Blue (RGB) These outputs are shown in Fig. 4–7 and used for on– screen display outputs. Therefore, there are different colors to represent the output. Pins 22 to 29 – Port P3, Bits 0 to 7 The diagram of these open–drain outputs is shown in Fig. 4–8. The voltage handling capability of Port–bits 0 and 1 (pins 28 and 29) is limited to Vsup, but supplies a high output current. The Port–bits 2 to 7 (pins 22 to 27) are outputs with a 12 V rating and a lower output current. In standby, bit 7 of P3 is grounded. Pin 30 – Tuning Voltage Output Fig. 4–9 shows the diagram of this push–pull output. Pin 30 supplies the tuning voltage for the capacitance diodes of the TV tuner in the shape of a pulsewidth–mo- dulated signal. After amplification by an external transis- tor, the tuner DC voltage is derived by multiple RC filter- ing. A temperature–compensated Zener diode ZTK 33 must be provided for stabilizing the tuning voltage against variations of supply voltage and ambient tem- perature. Pin 31 – IR: Remote–Control Input The internal configuration of this pin is shown in Fig. 4–10. Via an external coupling capacitor of 10 nF, the remote–control signal, amplified by the TBA 2800 preamplifier IC, is fed to the remote–control decoder. The input is self–biasing to approximately 1.4 V, and the input DC resistance is approximately 150 kOhm. For highest input sensitivity, this pin must not be loaded re- sistively. A small capacitor connected from pin 31 to ground can be useful to suppress steep transients. Pins 32 to 35 – Analog Outputs These pins are open–drain outputs with diagram shown in Fig. 4–11. They supply the squarewave signals whose variable pulse/interval ratio is described in section 2.5. These signals serve for actuating the analog control ele- ments. External pull–up resistors are required to pro- duce the squarewave output signals. Pins 36 to 38 – IM Bus Connections The internal configuration of these pins are shown in Figs. 4–12 and 4–13. Via these pins, the ITT TVPO 2066 is connected to the IM bus (see section 2.3.). This bus in- terlinks the TVPO 2066 and the non–volatile memory. The ident and clock outputs are unidirectional (see Fig. 4–12). The data pin acts as input and output for reading and writing data (Fig. 4–13). Pin 40 – Mains: Mains Switch Input/Output The internal configuration of this input/output is shown in Fig. 4–13. Pin 40 represents the output of the mains flip–flop with a resistive pull–up. The output is active low (mains on). In the case of infrared remote control, this pin acts as output and drives an external switching am- plifier, the mains relay, In the case of direct operation, this pin is used as input for switching on the TV receiver by means of an active low level applied to this pin, which sets the main flip–flop. Pin 41 – Reset: Reset Input The internal configuration of this input is shown in Fig. 4–14. The function of this pin is explained in section 2.4. The input circuit is of a Schmitt trigger configuration and provides some noise immunity. In critical applica- tions, however, an additional ceramic capacitor, con- nected between this pin and GND, may be necessary to increase noise immunity. Pin 42 – Osc Out: fosc/4096 Output The internal configuration of this output is shown in Fig. 4–15. This push–pull output provides the memory clock signal for the non–volatile memory MDA 2062 EEPROM (1 kHz). The drive capability of this pin is one TTL gate. This pin is not needed for the non–volatile memory NVM 3060. Pin 43 – T1: T1 Input This input can be used as timer input or normal input (e.g. to count the pulses of the horizontal frequency for autosearch function in analog TV sets). For more details about this input, see the CCU 2030, CCU 2050, CCU2070 data sheet. Pin 44 – Xtal: Oscillator Crystal The internal configuration of this input/output is shown in Fig. 4–16. For normal use, a 4 MHz crystal is con- nected to this oscillator pin and to GND. The input is self– biasing to approximately 3.8 V, input DC resistance is approx. 350 kOhm. The output signal is the 4 MHz clock signal of the TVPO 2066. Programmed Versions of TVPO 2066 Some programmed versions of the TVPO 2066 are available (all versions use the non–volatile–memory NVM 3060): – TVPO 2066–A25 for analog TV–sets. With auto–searching of stations, 4 multi–standards, up to 99 stations, sleep–timer, Teletext with TPU 2735 with FLOF & exended charac- ters (Spanish, Polish, Hungarian and Turkish). – TVPO 2066–D03 for digital TV–sets. Along with the VSP 2860 and the VCU 2133 it offers a very economical solution of digital TV–sets (simple TV). Some features are 4 standards: PAL, NTSC, SECAM East/West, up to 99 stations, 3 video modes, auto–searching analog output for ana- log audio (volume) control and more. Separate data sheets are available for analog and digital versions. Application diagrams will be found there. The last page shows an application diagram for analog TV– sets. 5.5. User Options If the manufacturer writes his own software for the TVPO 2066, he can choose some options by program mask or diffusion mask.
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