TELEFUNKEN (THOMSON) MA110C CHASSIS TX807EU (124R/TX807EU) INTERNAL VIEW

 POWER SUPPLY SECTION:
It is a FROSIN (Free Oscillating Safe Intelligent) auto-oscillating switching power supply. The ac supply voltage is in the range 180 to 265V. When operating, switching frequency is of the order of 70kHz for a power consumption of 45W. In standby, power consumption is less than 2W. TURNING ON OF TP20 SWITCHING POWER SUPPLY The ac supply voltage, which is rectified and filtered by DP01 and CP08, is applied to the switching transistor TP20 via the 9-5 coil of LP03. Simultaneously, the capacitor CP24 is charged by RP05, RPO6 and RP07. When the voltage on the terminals of CP24 reaches about 9V (threshold of the zener diode DP23), the transistor TP25 becomes conducting and turns on the switching transistor TP20. The zener diode DP21 limits the TP20 grid/supply voltage. TURNING OFF OF TP20 SWITCHING POWER SUPPLY The voltage on the terminals of RP20, when high enough, turns on TP22 ther TP23. Consequently, the TP20 grid current is diverted to ground via TP23, RP28 and RP20. TP20 is turned off. Inverting polarity on
the terminals of LPO3 results ir the following: l
 TP25 turned off.
l
 Charging of CP24 via 2 of LPO3 and DP25.
l
 Recuperation of energy in the secondary coils.
l
 Activation of regulation.
l
 Charging of CP40 via DP40 (soft start circuit).
l
 TP22/23 maintained turned on via DP37/38 and RP37 (FROSIN circuit). SOFT START The negative voltage, rectified and filtered by DP40/CP40, delays the instant at which TP22/23 turns on and consequently the instant at which TP20 is turned off a the t start, this negative voltage is zero. TP22 is controlled by RP20. Later, the negative voltage appears and increases, delaying control of TP22/23. The conducting time of TP20 therefore becomes longer and longer.

/
FROSIN CIRCUIT During the energy restitution phase, the transistors TP22/23, maintained turned or h by network 2 of LPO3, DP37/38 and RP37, ensure that TP20 is turned off. At the ? end of demagnetisation, the voltage sent to the collector of TP20 falls and CPO! 3 charging starts an oscillation cycle with the primary coil of LP03. Consequently, the ? collector voltage of TP20 continues to fall when it reaches 3OOV. The new TP20 saturation command occurs when TP20 has a collector voltage a close to 0, an effect obtained by the delay resulting from the negative voltage ? applied to 2 of LP03. This limits power losses due to TP20 switching, and the efficiency of this power supply is thus increased to 81% in operation (38% in stand by).

This delay results from the discharge time of TP22/23 (related to FROSIN circuit DP37/38, RP37 by control of saturation current) and the charge time of CP23 via 3 RP25 when Pin 2 of LPO3 becomes negative.

POWER SUPPLY BEHAVIOR IN STANDBY
In standby, because the energy required by the secondary coils is low, the saturation time for TP20 tends to a value below 1 l.~, a value too low to affect power supply efficiency in this mode. A minimum conduction time circuit (Ton min) has there fore been added to TP20 using the components CP38/RP38. In steady state, the regulation photo-transistor IP01 cannot alone perform saturation of TP22/23 and consequently the turning off of TP20.
The assistance of the following is required:
l
 The positive voltage produced on the terminals of RP20 in the storage phase. . The positive voltage supplied by the FROSIN circuit (DP37/38, RP37) in the restitution phase. In standby mode, due to the effect of the Ton min circuit, the energy stored I becomes greater than the small requirements of the secondary coils Consequently, the secondary voltages increase during energy restitution phases The conduction of IP01 is then such that it is alone sufficient to maintain TP22/23 I saturated over several LPO3/CPO9 oscillation cycles. The Ton min results from the negative impulse obtained from the voltage induced I n 2 of LPO3 (negative when TP20 is conducting) and the charging of CP38 viaI RP38. This impulse maintains TP22 turned off for a minimum time.f-

In standby, the management microcontroller (IROl) re-starts the power supply 351 QJS approximately every 1 lms (BURST signal which turns off the transistor TP 52). Due to this signal, the regulation becomes operative and the voltages UI ant3 UB increase. This voltage increase is necessary when the television
is switching  on (VCC greater than 6.6V at 12 of IVOl). The ON command (20 of IROl arrives during these impulses. The transistor TP52 is locked on (V base = 0, V emit ter = 5.5V).
/
REGULATION
The voltages UA and UB are regulated. UA informs the anode of the IPOl photo-transducer diode. UB informs the error amplifier IP50 (pin 3). The resulting error voltage is applied tc the IPOl photo-transducer cathode. It should be noted that an increase of UE results in a reduction in the voltage on the photo-transducer cathode. The conductivity of the photo-transducer transistor is proportional to the current passing through the photo-transducer diode. The voltage on the terminals of CP24, via RP30, DP30 and the photo-transducer transistor is applied to the base of TP21. The components RP54/56/58 and DP30 set the regulation range. When the energy recuperated from LPO3 is low, the voltage on the terminals o CP24 is insufficient to make DP30 conducting. Consequently, the conductivity o TP20 increases and recuperated energy is increased.

SAFETY
The zener diode DP27 limits the grid voltage of the TP20 switching supply. The zener diode DP21 limits the grid-supply voltage of the TP20 switching supply The zener diode DP40 limits the conducting time of the TP20 switching supply in the event of overcharging or regulation malfunction (the soft start voltage will become less and less negative). The transistor TP52 acts as an over voltage protection. When UA (P) is too high TP52 is turned off via the zener diode DP57. Therefore, more current passes through IPOl and consequently TP20 is less conducting. The resistor RP90 protects against overvoltages on UA.

DEMAGNETISATION
The voltage VP (12V) recuperated from the line transformer is used. When this vol
tage appears (television ON), the transistor TP71 saturates during the charge time
of CP71 (5 to 10 seconds). It causes the contacts of relay SPOl to be closed thu:
activating the demagnetisation loop.

Mains frequency synchronous burst mode power supply

 1. A synchronous burst mode power supply comprising:

a power converter for transforming an AC mains from a relatively low frequency to a higher frequency; and

a gate circuit responsive to said AC mains supply for enabling said power converter to initiate a burst of output pulses at said higher frequency each time a momentary amplitude of said AC mains supply occurs within a predetermined range.


2. The power supply according to claim 1, further comprising means for regulating a transformed output) from said converter circuit to a standby voltage, said means being coupled back to said gate circuit for controlling operation of said power converter circuit in response to load changes to said power supply.

3. The power supply according to claim 1, wherein said power converter comprises a self-oscillating circuit and said gate circuit enables operating of said self-oscillating circuit only during two periods of each cycle of said supply from said AC mains when said supply has a single voltage polarity.

4. The power supply according to claim 1, wherein said gate circuit comprises a threshold detector circuit for generating voltage pulses when detecting portions of positive waveforms of said mains voltage within said predetermined range.

5. The power supply according to claim 4, wherein said threshold detector comprises a transistor biased at its base terminal by a first voltage division of said positive waveforms to pass said voltage pulses from a second voltage division of said positive waveforms.

6. The power supply circuit of claim 5, wherein said first voltage division comprises a resistor pair divider coupled to a base terminal B of said transistor, and said second voltage division comprises a resistor pair coupled to said positive waveforms and an emitter terminal of said transistor.

7. The power supply circuit of claim 4, wherein said power converter circuit comprises a free running oscillator circuit for converting said voltage pulses from said gate circuit at a first frequency to current pulses at a second frequency greater than said first frequency.

8. The power supply circuit of claim 7, wherein said free running oscillator circuit comprises a transistor biased at its base terminal B by said voltage pulses that are rectified by a first diode and then charge a first capacitor for enabling said second transistor to conduct said current pulses, said current pulses being derived from said positive waveforms ripple attenuated by a second capacitor coupled to an emitter terminal of said second transistor, said positive waveforms energizing a primary winding of a transformer to develop in a flyback manner a secondary winding voltage across a secondary winding of said transformer.

9. The power supply circuit of claim 7, further comprising a voltage regulating circuit coupled to a secondary winding of a transformer having a primary winding coupled to said free running oscillator circuit, said secondary winding developing a secondary voltage from said current pulses conducted through a primary winding of said transformer.

10. The power supply circuit of claim 9, wherein said voltage regulating circuit comprises an integrated voltage regulator coupled to a diode and a first capacitor arrangement for rectifying and filtering said current pulses from said secondary winding to provide a secondary voltage stabilized by said integrated voltage regulator, said secondary voltage being filtered by a second capacitor to provide a standby voltage.

11. The power supply circuit of claim 7, further comprising a voltage regulating circuit coupled to a secondary winding of a transformer having a primary winding through which said current pulses controllably conduct to develop a secondary winding voltage that is coupled back to and adjust on-time operation of said threshold detector circuit.

12. A synchronous burst mode standby power supply comprising:

a self-oscillating power converter for receiving an AC mains supply;

a transformer primary winding coupled to said power converter and receiving pulses therefrom for generating a supply of power at a secondary winding of said transformer; and

a gate circuit coupled to said AC mains supply and said power converter, wherein said gate circuit enable operation of said self-oscillating power converter while a momentary amplitude of said AC mains supply cycles through a predetermined range.


13. The power supply circuit of claim 12, wherein said gate circuit comprises a threshold detector for generating voltage pulses when detecting positive waveforms of said mains voltage below a threshold.

14. The power supply circuit of claim 13, wherein said threshold detector comprises a transistor biased at its base terminal by a first voltage division of said positive waveforms to pass said voltage pulses from a second voltage division and filtering of said positive waveforms.

15. The power supply circuit of claim 14, wherein said first voltage division comprises a first resistor pair divider coupled to a base terminal B of said transistor, and said second voltage division comprises a second resistor pair coupled between said positive waveforms and an emitter terminal of said transistor.

16. The power supply circuit of claim 2, wherein said self-oscillating power converter circuit converts said voltage pulses at a first frequency to current pulses at a second frequency greater than said first frequency.

17. The power supply circuit of claim 16, further comprising a voltage regulating circuit coupled to a secondary winding of a transformer having a primary winding through which said current pulses controllably conduct to develop a secondary winding voltage that is coupled back to said threshold detector for influencing on-time operation of said self-oscillating power converter.

18. The power supply circuit of claim 17, wherein said voltage regulating circuit

comprises an integrated voltage regulator, coupled to a diode D6 and capacitor arrangement, for receiving said secondary winding voltage and providing a voltage input for said integrated voltage regulator, and an opto-coupler coupled to said integrated voltage regulator for conducting current derived from said secondary winding voltage back to said threshold detector when said voltage input is above a reference voltage.


19. The power supply circuit of claim 18, wherein said reference voltage is developed across a resistor and zener diode arrangement coupled between the voltage input and said opto-coupler.

20. A method for providing synchronous burst mode power comprising the steps of:

receiving an AC mains supply at a relatively low frequency;

detecting when a momentary amplitude of said AC mains supply occurs within a predetermined range, and

initiating a burst of output pulses at a higher frequency than said relatively low frequency responsive to said detecting step.


21. The method according to claim 20, further comprising the step of terminating further initiation of said burst of output pulses responsive to said detecting.

22. The method according to claim 20, wherein said detecting step comprises when said AC mains occurs below a first threshold and above a second threshold.

23. The method according to claim 20, further comprising the step of regulating said output pulses to a standby voltage output.

24. The method according to claim 20, further comprising the step of controlling timing of said initiating by a voltage derived from said output pulses.

25. The method according to claim 21, further comprising the step of controlling timing of said initiating and terminating by a voltage derived from said output pulses.

Description:

BACKGROUND

This invention relates generally to the field of power supplies, and, in particular, to standby mode power supplies for television receivers.

The power consumed by electronic equipment in the standby mode is becoming an increasingly visible public policy issue. For example, an article in the Sep. 19, 1997, issue of Europe Energy reports that the European Commission regards reducing the energy consumed by electronic equipment in the standby mode of operation as a priority. The article further states that the Commission has concentrated its initial efforts at reducing the standby power consumption of televisions and VCRs, and that it has elicited voluntary commitments from manufacturers of such products to progressively reduce average standby power consumption.

Modern televisions can have a standby power consumption of about 5 to 10 Watts caused by the degaussing circuit and switched mode power supply running in standby mode. Televisions that have an additional standby power supply and disconnect the degaussing circuit can reduce the power consumption to 1 Watt.

In a conventional power supply arrangement for a video display apparatus, a primary winding of a standby transformer is coupled to the AC mains. A transformed voltage across a secondary winding of the standby transformer is full-wave rectified and is regulated by some form of linear regulation to provide power for the video display apparatus in a standby mode of operation. This standby power supply consumes power as long as the video display apparatus is connected to the AC mains, and thus also consumes power during the run mode of operation. During standby mode, power losses are incurred partly due to switching losses. U.S. Pat. No. 6,043,994 proposes a power supply for reducing standby power consumption attributable to a start-up resistor of the switched mode power supply controller integrated circuit IC.

It is therefore desirable to provide a simple and cost-effective method for reducing the standby power consumption attributable to the switching losses.

SUMMARY

The present invention is directed to a standby power supply circuit that reduces the standby consumption attributable to switching losses from coupling full AC mains to power conversion circuitry. A synchronous burst mode power supply includes a power converter for transforming an AC mains from a relatively low frequency to a higher frequency; and a gate circuit responsive to the AC mains supply for enabling the power converter to initiate a burst of output pulses at the higher frequency each time the AC mains supply occurs within a predetermined range. A method for providing synchronous burst mode power includes the steps of receiving an AC mains supply at a relatively low frequency, detecting when the AC mains supply occurs within a predetermined range, and initiating a burst of output pulses at a higher frequency than the relatively low frequency in response to the detecting step.

The above, and other features, aspects, and advantages of the present invention will become apparent from the following description read in conjunction with the accompanying drawings, in which like reference numerals designate the same elements.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows a block diagram and waveforms that illustrate the present invention.

FIGS. 2 and 3 show schematic diagrams of standby power supplies that embody the present invention.

FIG. 4 is a graph of the range of input power verses output power.

Similar reference characters refer to similar elements in each of the drawings. Resistors values shown are in units of measure indicated as ohms, kilo-ohms (k), or Mega-ohms (M), and capacitor values are in units of measure indicated as microfarads (u) or picofarads (p).

DESCRIPTION OF THE PREFERRED EMBODIMENTS

The present invention reduces power losses associated with circuit switching in a standby switched mode power supply SMPS. The inventive standby SMPS is connected directly to a rippled but rectified mains voltage, which is then gated to the SMPS during periods of low levels of the rectified mains voltage. Gating of the rectified mains voltage to the standby SMPS, which responds by generating burst pulses, is synchronous with a predetermined range in the rectified mains voltage.

The invention is illustrated with a block diagram 10 and waveforms 11-3 in FIG. 1. A mains voltage Vmains is rectified by a diode D1 to provide rippled and positive half wave voltages V1 to a threshold detector 1. Voltage pulses V2 are output by the threshold detector 1 when the rise and fall of the positive half wave voltages V1 are below a threshold level (horizontal line 16 in graph 11 of FIG. 1). The voltage pulses V2 at the relatively low frequency of the mains voltage Vmains, for example 50 or 60 Hz, are converted by the free running oscillator 23 to sawtooth current pulses ITr at a higher frequency. In a sense, the detector acts as a gate with respect to passing part of the positive half-waves to the oscillator circuit 23. It is noted that the Ac mains voltage alone initiates and terminates the burst pulses V2, independent of any external switching control. In the exemplary embodiment of FIG. 1, nine sawtooth pulses ITr are generated for every voltage pulse V2 output by the detector 1. This number is related to the free running frequency of the oscillator, for example 25 kHz. Peaks of the sawtooth current pulses decrease in a linear sloping manner, as shown, because the positive half-wave pulse V1 imposed on the transformer Tr1 decreases from its peak to zero. Voltage imposed on a transformer follows the relationship (voltage/inductance) multiplied by time. In the present circuit the time factor is constant but the mains sine wave voltage increases from zero to a peak value and then decreases from its peak value to zero. The decrease from peak value to zero causes the linear decaying peaks in the sawtooth current pulses ITr. Conversely, during the rising edge of the mains voltage sine wave the peaks of the sawtooth current pulses ITr rise linearly.

The sawtooth current pulses ITr are transformed into a secondary winding voltage VTR1, which is then diode D7 rectified into an unregulated voltage V3. The unregulated voltage V3 is smoothed and regulated by a voltage regulator 3 to an output voltage Vout of 5V DC.

An exemplary circuit in FIG. 2 includes a circuit arrangement 20 for controllably coupling the voltage main

s Vmains over to a connection point for a run mode power supply (not shown). The voltage mains Vmains is switched across an opto-relay, Triac T2, responding to a run control signal through current limiting resistor R13 from a known type of microcontroller (not shown). Alternative relay switches in lieu of triac driver T2 can be employed. The voltage Vmains is also coupled across a triac T1 triggered when the mains voltage is passed by the triac driver T2 and dropped across a voltage divider made up by resistors R11 and R12. The voltage mains Vmains passed by triac T1 is coupled across a degaussing circuit 21, full wave rectified by a diode bridge arrangement D11-D14 and filtered by capacitor C11 for a run mode power supply.

The circuit embodiment of FIG. 2 further includes exemplary circuit embodiments for the threshold detector 1, free running oscillator 2 and voltage stabilizer 3.

Positive half wave voltages V1 from the voltage mains Vmains rectified by diode D1 are voltage divided between resistors R4 and R5, voltage limited by zener diode D3, and ripple attenuated by capacitor C1 to provide +12V to the emitter terminal E of transistor Q1. Transistor Q1 is biased by voltage developed at its base terminal B from the rectifier arrangement of voltage divider resistors R1 and R3 and filtering capacitor C2. An optional adjustable resistor R2 allows for fine adjustment of the base terminal B voltage. Transistor Q1 is protected by diode D2 against a possible reverse biasing due to the +12V developed at the emitter terminal E of transistor Q. When the input voltage to the base terminal B of transistor Q1 is below a certain threshold, determined by the emitter E voltage of transistor Q1 and the voltage divider R4, R5 and D3, transistor Q1 turns on and provides the free running oscillator circuit 23 with a bias voltage. It is noted that resistor R5 adapts the on-time of the oscillator circuit 23 to different mains voltages.

In the threshold detector circuit 22, +12V at the positive terminal of capacitor C1 is compared with voltage at the base terminal B of transistor Q1. A positive voltage at terminal B of transistor Q1 greater than 0 and less than about 11.3 volts biases transistor Q1 on, providing the threshold level 16 of about 11.3 volts. Above 11.3 volts at base terminal B, PNP transistor Q1 is biased off. The threshold detector or gate circuit 22 provides low voltage level switching which reduces losses otherwise present in a typical switched mode standby power supply.

The oscillator 23 in FIG. 2 is a blocking oscillator formed by transformer Tr1, resistor R6, capacitor C3, secondary winding n3 and transistor Q2. The blocking oscillator operates in a conventional manner. It is noted that diodes D4 and D5 and resistor R7 are not necessary for basic operation of the oscillator circuit, but have been included as one form of signal conditioning. The depiction of blocking oscillator circuit 23 is merely exemplary and does not proscribe the use of other oscillator circuits or topologies in the context of the present invention.

Positive feedback provided by secondary winding n3 keeps transistor Q2 conducting. Current through base terminal B of transistor Q2 keeps capacitor C3 discharging until the voltage across the capacitor C3 is 1.4V, at which point transistor Q2 stops conducting and power is transferred to the secondary side via winding n2 in a flyback manner. When there is flyback voltage at the secondary winding n3 capacitor C3 is pulled down to negative. At this point current has to be fed through resistor R6 again to charge up capacitor C3 and start conduction of another saw tooth current ITR, derived from the positive half-wave pulses V1. Capacitor C4 reduces radiation of the fast switching.

The blocking oscillator 23 runs with an almost constant frequency that is dependent on the voltage Vmains, resistor R6, capacitor C3 and the relationship between windings nl and n3. The duty cycle of the oscillation can be substantially constant so that the energy transferred to the secondary winding n2 is substantially constant. This substantially constant energy has two consequences. First, the standby power supply is inherently protected against a short circuit condition on the secondary side of the transformer Tr1. Second, parallel voltage regulation techniques can be used to regulate the voltages provided by the secondary windings n2. For example, in FIG. 2, the +5V output provided by the secondary winding n2 can be partly limited by zener diode D7 and regulated by the voltage regulator IC1. The use of voltage regulator IC1 and diode D7 is merely illustrative and does not preclude the applicability of other voltage regulation techniques in the context of the present invention.

In the embodiment of FIG. 2, the blocking oscillator 23 is advantageously used to transform the relatively low mains voltage frequency, for example 50 to 60 Hz, from which two voltage pulses V2 appear per cycle to a frequency from which nine sawtooth current pulses are generated for each voltage pulse V2. This transformation permits a decrease in the size of standby transformer Tr1, which in turn, leads to a decrease in the power consumption by the standby transformer Tr1. The secondary winding voltage VTR1, reaching 7.2V in the exemplary circuit, is initially rectified by diode D5, filtered by capacitor C5 and then regulated by the voltage regulator IC1. In case of reload, diode D7 prevents capacitor C5 and voltage regulator IC1 from too much voltage. Voltage output by the regulator IC is filtered by capacitor C6 to provide the +5V standby power.

The circuit of FIG. 3 is similar to the standby power arrangement of FIG. 2, except for the current feedback loop from an additional opto-coupler IC2 coupled to the terminal between resistor R5 and zener diode D3 of the threshold detector circuit 22. The circuit embodiment of FIG. 2 is suited for a static load or a relatively small variation in load where resistor R2 can be adjusted to optimally time the initiation and termination of burst pulses suitable for the load amount. If R2 is optimally adjusted for a certain load and the actual load is relatively small then the burst pulse frequency will be too high and the power output will be greater than needed for the load, resulting in wasted power. Dynamic load applications are appropriate for the circuit embodiment of FIG. 3, where the current feedback adjusts the initiation and termination of burst pulses V2 by the gate circuit. The current feedback loop of FIG. 3 eliminates the need for the variable resistor R2 adjustment of FIG. 2.

The opto-coupler IC2 conducts whenever secondary voltage V3 is above a reference voltage developed across D7. Conduction by the opto-coupler IC2 reduces the reference voltage for the emitter of transistor Q1 via current I1 in the feedback loop, which reduces the on time of the free running oscillator circuit 22. As a consequence, the input power is reduced when load decreases, and the voltage controlling potentiometer R2 in the circuit embodiment of FIG. 2 is unnecessary.

FIG. 4 is a graph of the range of input power versus output power demonstrating the increased efficiency provided by the invention. An ordinary power supply will ordinarily consume 1 W to output 200 mW, representing a 20% power conversion efficiency. As the graph of FIG. 4 demonstrates, for example, that with the inventive gating on of momentary low voltage mains an input mains voltage power Pinput of approximately 337 mW is converted to standby power of approximately 115 mW. This represents an increase in power conversion efficiency to approximately 30%.

The standby transformer TR1 may be constructed using an EF16, N67 core with an air gap equal to approximately 0.1 mm. The inductance of the primary winding n1 of the standby transformer Tr1 may be equal to approximately 18 mH, using approximately 160 turns, in two layers, of 0.1 mm diameter CuL wire.

Approximately one layer of 0.1 mm thickness MYLAR® brand polymeric film may be used to provide electrical isolation between the two layers of wire to reduce parasitic capacitance. The secondary winding n2 may use 23 turns of 0.315 mm diameter CuL wire, and the secondary winding n3 may use 16 turns of 0.315 mm diameter wire. Approximately 2 layers of 0.1 mm thickness MYLAR® brand polymeric film may be used to provide electrical isolation between the primary winding n1 and the secondary windings n2 and n3.

It will be apparent to those skilled in the art that, although the invention has been described in terms of specific examples, modifications and changes may be made to the disclosed embodiments without departing from the essence of the invention. For example, in the embodiment discussed portions of positive half-wave voltage levels between 0 and 12V were shown to be passed to the oscillator circuit 23. However, the inventive Ac mains initiated and termination of burst pulses could be practiced with a threshold range of 2V to 12V. However, the 0 to 12V range is preferable because the lower zero boundary makes the circuit design simpler. Also, in lieu of the preferred gating of positive half-waves from the Ac mains, full wave rectified pulses of the AC mains could be gated to the oscillator circuit 23. However, gating of full wave rectified AC mains pulses would require dissipating excess power, not needed for standby mode operation, thereby making the power supply circuit less efficient. Accordingly, reference should be made to the appended claims, rather than to the foregoing specification, as indicating the true scope of the invention.


Management of TX807 rack is ensured by a 4-bit microcontroller, Thoshiba TMP47C1637. ts clock speed is 6MHz. t is associated with an EEPROM memory, IR02, for the storage of user parameters, the service mode and backup in the event of mains power failure. t performs the following functions:
l
 Remote control and keyboard management.
9 Standby or switching on the television or radio.
l
 Standards switching.
9 Voltage or frequency synthesis.
l
 Volume, brightness, contrast and colour regulation.
l
 OSD signal generation.
l
 Power supply control in standby mode.
l
 Watchdog circuit for monitoring the time bases.

 POWER SUPPLY AND FUNCTIONAL SIGNALS

POWER SUPPLY
The microcontroller, IROl, is supplied with 5V (pin 42), from the voltage P and the stabilisation circuit TROl/DR02. The origin of the voltage P is:
l
 the voltage UA (15V during operation and 9V in standby) at start-up because VTU= 0 and then TL03 is saturated. . the voltage +VP (125V) in steady state because VTU= 86V and then TL03 i! blocked.

CLOCK
Its 6MHz clock is obtained from the quartz oscillator QROl (pins 31 and 32 o IROl).
RESET
The reset time constant is composed of RR46 and CR25 The components TR02 TR03 and DR02 activate this time constant when the IROl supply voltage is suffi cient. The transistors TR02 and TR03 are turned on when the voltage on the ter minals of CR01 is close to 5.8V (DR02 threshold + TR03 vbe).

AC SUPPLY FAILURE DETECTION
In the event of mains supply failure, the voltage P drops. This turns off the transistors TR03ITR02 and causes the voltage to drop to 0 on pin 37 of IROl The micro, controller saves in the EEPROM the parameters necessary for switching the tele vision on. HOLD This input (pin 34) monitors the microcontroller supply voltage. If this voltage falls below 4.5V, the television switches to standby.

TV ON/STANDBY COMMAND
Output 20 of IROl corresponds to an open drain output. ‘when the television is switched on, it passes to a high level resulting in the sat\ ation of TR08 and TR07. A +8.5VS voltage appears on the collector of TR07 an supplies the integrated circuit IV01 (pin 37). The time base command signals mu )e output from IV01 . The voltage +VP (129.9, recuperated from a secondary coil of the line transformer lia the diode DLOl , takes over from the voltage UA. Wring the reset, the time constant CR04/RR07 and the transistor TR04 suppres he 5Vcc positive impulse present on output 20 of IR01.

THE KEYBOARD
depending on rack version, the keyboard comprises 4 or I3 keys. It is organized i 3 line/column matrix. The outputs (pins 9 to 12) provide, in standby, negative signals with a period c approximately 40ms. The function inputs, pins 13 and 14, are in a low level in th absence of key operation. iNhen a key is pressed, a high level (pin 9) or sweep signals (pins 10 to 12) transmitted to an input function.

REMOTE CONTROL The emitted codes arrive at 35 of IROl . They are repeated every 80ms. They are composed of 12-bit serial words. l
 4 address bits.
l
 1 call bit.
l
 7 function bits.
FRONT PANEL LED This indicator light consists of a two-colour LED (RED-GREEN). luring operation, the green LED is powered from +VP (12.5V) originating from the line transformer.
In standby, the red LED is powered from UA (9V) originating from the main power Supply. This UA voltage, switched by transistor TL03, gives the voltage P. n electronic key, programmable stop and safety modes, it cycles between 2 states l In electronic key mode, the red LED flashes (T = 1 second). l In programmable stop mode, the red LED flashes (T = 1 second). . In time base safety mode, it flashes red/green in alternation.

CHANNEL AND STANDARDS MANAGEMENT
‘he pins 17,18 and 19 of IROl manage the tuner reception bands. The varicap vol age is composed from the signal available at 1 of IROl (VT), the variable resistor RHO1 and the low-pass filter RH01/02/04/CH03 at CH05 Automatic frequency control is performed by the integrated circuit IV01 and informs IROl via the bus IIC Output 3 of IROl allows: -The disabling of the 40.4MHz rejecter in the 1C band. -To tune the sound FI to 40.4MHz (1 C band) or 32.4MHz (other case). output 7 of IROl selects the filters Ql31 (5.5MHz) or Cl132 (6MHz) for the FM audited-carriers.


OSD SIGNAL GENERATOR
The microcontroller IROl produces the necessary signals for the display of menu! on the screen. Via pin 25, it delivers the encrustation command, FB (fast blanking). This results via the transistor TVOl, in input 26 of IV01 being informed and allows the RVB out puts of IV01 (pins 19 to 21) to be cleaned. Using pins 22 to 24, it delivers the RVB signals. These signals are amplitude adjusted, black level corrected using the burst port impulse and sent to the RVB amplifier. The transistors TV08, TV03, TV05 and TV07 perform signal alignment. A clock having a speed close to 7MHz (pins 28 and 29) sets the encrustation frame width. It is enabled in OSD mode only. The line return impulse (HFY) taken from point 7 of the line transformer LLOt arrives at pin 26 via the transistor TR05. A raster return impulse arrives on pin 27. It is obtained by integrating the sand castle (RR67/RR68/CR40), available at 41 of IVOl, and by the shaping transistor TRlO. These two signals H and V, present with and without video signal, are
required setting the position of the OSD window with respect to the television raster.
NOTES:
If the line return impulses are absent, there is no OSD. If the raster return impulses are absent from 27 or 38, the microcontroller IROl will no longer perform functions and consequently the screen will remain black.



OTHER COMMANDS
Pin 15: receives the slow switching from the peritel connector AVl . Pin 8: performs switching of internal/external audio sources in 1120, via the transistor TR06. Pin 6: audio MUTE, it is enabled at 5V. For 36cm televisions (pin 36 of IROl grounded by a 10K resistor), mute is enable 1 when the television is switched on or switched to standby. For the other cases mute is performed by the software in IV01 . For 51 and 55cm televisions (pin 36 of IROl at 5V by a 10K resistor), mute i enabled when the television is switched on, channel is changed, in the absence c a signal and when switched to standby. Pin 39: certain televisions incorporate an FM radio. This output allows the radio tc be switched on. Pin 2: command bursts for the main power supply are generated in standby mode

 The heart of the total system is formed by the “One Chip” TV processor PHILIPS  TDA884X.
This chapter gives a short description of this IC family. More detailed information concerning the
internal circuitry can be found in report ref. Report no: AN98002.
Common features of the family:

•
 Vision IF circuit with alignment-free PLL demodulator
•
 Alignment-free multi-standard FM sound demodulator (4.5 to 6.5 MHz)
•
 Audio switch
•
 Flexible source selection with internal and external CVBS input, Y(CVBS)/C input and selected
CVBS out, suited for comb filter use
•
 Integrated chroma trap (auto calibrated)
•
 Integrated chroma band pass (auto calibrated) with switchable centre frequency
•
 Integrated luminance delay line
•
 Asymmetrical peaking in luminance channel with defeatable coring function
•
 Black stretching
•
 Blue stretch circuit which offsets near white colours to blue
•
 Integrated RGB processor with “continuous cathode calibration” and white point adjustment
•
 Linear RGB inputs with fast blanking input
•
 Possibility to insert “blue mute” when no signal is present
•
 Dynamic skin tone (“flesh”) correction for NTSC signals
•
 Horizontal synchronisation with two control loops and alignment-free horizontal oscillator
•
 Slow start and stop of the horizontal drive pulses
•
 Vertical divider circuit
•
 Vertical driver stage optimized for DC-coupled output stages
•
 I 2C bus control
•
 Low power dissipation

GENERAL DESCRIPTION:
The various versions of the PHILIPS TDA 884X/5X series are
I2C-bus controlled single chip TV processors which are
intended to be applied in PAL, NTSC, PAL/NTSC and
multi-standard television receivers. The N2 version is pin
and application compatible with the N1 version, however,
a new feature has been added which makes the N2 more
attractive. The IF PLL demodulator has been replaced by
an alignment-free IF PLL demodulator with internal VCO
(no tuned circuit required). The setting of the various
frequencies (33.4, 33.9, 38, 38.9, 45,75 and 58.75 MHz)
can be made via the I2C-bus.
Because of this difference the N2 version is compatible
with the N1, however, N1 devices cannot be used in an
optimised N2 application.
Functionally the IC series is split up is 3 categories, viz:
· Versions intended to be used in economy TV receivers
with all basic functions (envelope: S-DIP 56 and QFP
64)
· Versions with additional features like E-W geometry
control, H-V zoom function and YUV interface which are
intended for TV receivers with 110° picture tubes
(envelope: S-DIP 56)
· Versions which have in addition a second RGB input
with saturation control and a second CVBS output
(envelope: QFP 64)

FUNCTIONAL DESCRIPTION
Vision IF amplifier
The IF-amplifier contains 3 ac-coupled control stages with
a total gain control range which is higher then 66 dB. The
sensitivity of the circuit is comparable with that of modern
IF-IC’s.
The video signal is demodulated by means of an
alignment-free PLL carrier regenerator with an internal
VCO. This VCO is calibrated by means of a digital control
circuit which uses the X-tal frequency of the colour
decoder as a reference. The frequency setting for the
various standards (33.4, 33.9, 38, 38.9, 45.75 and 58.75
MHz) is realised via the I2C-bus. To get a good
performance for phase modulated carrier signals the
control speed of the PLL can be increased by means of the
FFI bit.
The AFC output is generated by the digital control circuit of
the IF-PLL demodulator and can be read via the I2C-bus.
For fast search tuning systems the window of the AFC can
be increased with a factor 3. The setting is realised with the
AFW bit. The AFC data is valid only when the horizontal
PLL is in lock (SL = 1)
Depending on the type the AGC-detector operates on
top-sync level (single standard versions) or on top sync
and top white- level (multi standard versions). The
demodulation polarity is switched via the I2C-bus. The
AGC detector time-constant capacitor is connected
externally. This mainly because of the flexibility of the
application. The time-constant of the AGC system during
positive modulation is rather long to avoid visible variations
of the signal amplitude. To improve the speed of the AGC
system a circuit has been included which detects whether
the AGC detector is activated every frame period. When
during 3 field periods no action is detected the speed of the
system is increased. For signals without peak white
information the system switches automatically to a gated
black level AGC. Because a black level clamp pulse is
required for this way of operation the circuit will only switch
to black level AGC in the internal mode.
The circuits contain a video identification circuit which is
independent of the synchronisation circuit. Therefore
search tuning is possible when the display section of the
receiver is used as a monitor. However, this ident circuit
cannot be made as sensitive as the slower sync ident
circuit (SL) and we recommend to use both ident outputs
to obtain a reliable search system. The ident output is
supplied to the tuning system via the I2C-bus.
The input of the identification circuit is connected to pin 13

(S-DIP 56 devices), the “internal” CVBS input (see Fig.6).
This has the advantage that the ident circuit can also be
made operative when a scrambled signal is received
(descrambler connected between pin 6 (IF video output)
and pin 13). A second advantage is that the ident circuit
can be used when the IF amplifier is not used (e.g. with
built-in satellite tuners).
The video ident circuit can also be used to identify the
selected CBVS or Y/C signal. The switching between the
2 modes can be realised with the VIM bit.

Video switches
The circuits have two CVBS inputs (internal and external
CVBS) and a Y/C input. When the Y/C input is not required
the Y input can be used as third CVBS input. The switch
configuration is given in Fig.6. The selection of the various
sources is made via the I2C-bus.
For the TDA 884X devices the video switch configuration
is identical to the switch of the TDA8374/75 series. So the
circuit has one CVBS output (amplitude of 2 VP-P for the
TDA 884X series) and the I2C-bus control is similar to that
of the TDA 8374/75. For the TDA 885X IC’s the video
switch circuit has a second output (amplitude of 1 VP-P)
which can be set independently of the position of the first
output. The input signal for the decoder is also available on
the CVBS1-output.
Therefore this signal can be used to drive the Teletext
decoder. If S-VHS is selected for one of the outputs the
luminance and chrominance signals are added so that a
CVBS signal is obtained again.
Sound circuit
The sound bandpass and trap filters have to be connected
externally. The filtered intercarrier signal is fed to a limiter
circuit and is demodulated by means of a PLL
demodulator. This PLL circuit tunes itself automatically to
the incoming carrier signal so that no adjustment is
required.
The volume is controlled via the I2C-bus. The deemphasis
capacitor has to be connected externally. The
non-controlled audio signal can be obtained from this pin
(via a buffer stage).
The FM demodulator can be muted via the I2C-bus. This
function can be used to switch-off the sound during a
channel change so that high output peaks are prevented.
The TDA 8840/41/42/46 contain an Automatic Volume
Levelling (AVL) circuit which automatically stabilises the
audio output signal to a certain level which can be set by
the viewer by means of the volume control. This function
prevents big audio output fluctuations due to variations of
the modulation depth of the transmitter. The AVL function
can be activated via the I2C-bus.
Synchronisation circuit
The sync separator is preceded by a controlled amplifier
which adjusts the sync pulse amplitude to a fixed level.
These pulses are fed to the slicing stage which is operating
at 50% of the amplitude. The separated sync pulses are
fed to the first phase detector and to the coincidence
detector. This coincidence detector is used to detect
whether the line oscillator is synchronised and can also be
used for transmitter identification. This circuit can be made
less sensitive by means of the STM bit. This mode can be
used during search tuning to avoid that the tuning system
will stop at very weak input signals. The first PLL has a
very high statical steepness so that the phase of the
picture is independent of the line frequency.
The horizontal output signal is generated by means of an
oscillator which is running at twice the line frequency. Its
frequency is divided by 2 to lock the first control loop to the
incoming signal. The time-constant of the loop can be
forced by the I2C-bus (fast or slow). If required the IC can
select the time-constant depending on the noise content of
the incoming video signal.
The free-running frequency of the oscillator is determined
by a digital control circuit which is locked to the reference
signal of the colour decoder. When the IC is switched-on
the horizontal output signal is suppressed and the
oscillator is calibrated as soon as all sub-address bytes
have been sent. When the frequency of the oscillator is
correct the horizontal drive signal is switched-on. To obtain
a smooth switching-on and switching-off behaviour of the
horizontal output stage the horizontal output frequency is
doubled during switch-on and switch-off (slow start/stop).
During that time the duty cycle of the output pulse has such
a value that maximum safety is obtained for the output
stage.
To protect the horizontal output transistor the horizontal
drive is immediately switched off when a power-on-reset is
detected. The drive signal is switched-on again when the
normal switch-on procedure is followed, i.e. all
sub-address bytes must be sent and after calibration the
horizontal drive signal will be released again via the slow
start procedure. When the coincidence detector indicates
an out-of-lock situation the calibration procedure is
repeated. The circuit has a second control loop to generate
the drive pulses for the horizontal driver stage. The
horizontal output is gated with the flyback pulse so that the
horizontal output transistor cannot be switched-on during
the flyback time.
Via the I2C-bus adjustments can be made of the horizontal
and vertical geometry. The vertical sawtooth generator
drives the vertical output drive circuit which has a
differential output current. For the E-W drive a single
ended current output is available. A special feature is the
zoom function for both the horizontal and vertical
deflection and the vertical scroll function which are
available in some versions. When the horizontal scan is
reduced to display 4:3 pictures on a 16:9 picture tube an
accurate video blanking can be switched on to obtain well
defined edges on the screen.

Overvoltage conditions (X-ray protection) can be detected
via the EHT tracking pin. When an overvoltage condition is
detected the horizontal output drive signal will be
switched-off via the slow stop procedure but it is also
possible that the drive is not switched-off and that just a
protection indication is given in the I2C-bus output byte.
The choice is made via the input bit PRD. The IC’s have a
second protection input on the j2 filter capacitor pin. When
this input is activated the drive signal is switched-off
immediately and switched-on again via the slow start
procedure. For this reason this protection input can be

used as “flash protection”.
The drive pulses for the vertical sawtooth generator are
obtained from a vertical countdown circuit. This countdown
circuit has various windows depending on the incoming
signal (50 Hz or 60 Hz and standard or non standard). The
countdown circuit can be forced in various modes by
means of the I2C-bus. During the insertion of RGB signals
the maximum vertical frequency is increased to 72 Hz so
that the circuit can also synchronise on signals with a
higher vertical frequency like VGA. To obtain short
switching times of the countdown circuit during a channel
change the divider can be forced in the search window by
means of the NCIN bit. The vertical deflection can be set
in the de-interlace mode via the I2C bus.
To avoid damage of the picture tube when the vertical
deflection fails the guard output current of the TDA
8350/51 can be supplied to the beam current limiting input.
When a failure is detected the RGB-outputs are blanked
and a bit is set (NDF) in the status byte of the I2C-bus.
When no vertical deflection output stage is connected this
guard circuit will also blank the output signals. This can be
overruled by means of the EVG bit.
Chroma and luminance processing
The circuits contain a chroma bandpass and trap circuit.
The filters are realised by means of gyrator circuits and
they are automatically calibrated by comparing the tuning
frequency with the X-tal frequency of the decoder. The
luminance delay line and the delay for the peaking circuit
are also realised by means of gyrator circuits. The centre
frequency of the chroma bandpass filter is switchable via
the I2C-bus so that the performance can be optimised for
“front-end” signals and external CVBS signals. During
SECAM reception the centre frequency of the chroma trap
is reduced to get a better suppression of the SECAM
carrier frequencies. All IC’s have a black stretcher circuit
which corrects the black level for incoming video signals
which have a deviation between the black level and the
blanking level (back porch). The timeconstant for the black
stretcher is realised internally.
The resolution of the peaking control DAC has been
increased to 6 bits. All IC’s have a defeatable coring
function in the peaking circuit. Some of these IC’s have a
YUV interface (see table on page 2) so that picture
improvement IC’s like the TDA 9170 (Contrast
improvement), TDA 9177 (Sharpness improvement) and
TDA 4556/66 (CTI) can be applied. When the CTI IC’s are
applied it is possible to increase the gain of the luminance
channel by means of the GAI bit in subaddress 03 so that
the resulting RGB output signals are not affected.
Colour decoder
Depending on the IC type the colour decoder can decode
PAL, PAL/NTSC or PAL/NTSC/SECAM signals. The
PAL/NTSC decoder contains an alignment-free X-tal
oscillator, a killer circuit and two colour difference
demodulators. The 90° phase shift for the reference signal
is made internally.
The IC’s contain an Automatic Colour Limiting (ACL)
circuit which is switchable via the I2C-bus and which
prevents that oversaturation occurs when signals with a
high chroma-to-burst ratio are received. The ACL circuit is
designed such that it only reduces the chroma signal and
not the burst signal. This has the advantage that the colour
sensitivity is not affected by this function.
The SECAM decoder contains an auto-calibrating PLL
demodulator which has two references, viz: the 4.4 MHz
sub-carrier frequency which is obtained from the X-tal
oscillator which is used to tune the PLL to the desired
free-running frequency and the bandgap reference to
obtain the correct absolute value of the output signal. The
VCO of the PLL is calibrated during each vertical blanking
period, when the IC is in search or SECAM mode.
The frequency of the active X-tal is fed to the Fsc output
(pin 33) and can be used to tune an external comb filter
(e.g. the SAA 4961).
The base-band delay line (TDA 4665 function) is
integrated in the PAL/SECAM IC’s and in the NTSC IC
TDA 8846A. In the latter IC it improves the cross colour
performance (chroma comb filter). The demodulated
colour difference signals are internally supplied to the
delay line. The colour difference matrix switches
automatically between PAL/SECAM and NTSC, however,
it is also possible to fix the matrix in the PAL standard.
The “blue stretch” circuit is intended to shift colour near
“white” with sufficient contrast values towards more blue to
obtain a brighter impression of the picture.

Which colour standard the IC’s can decode depends on
the external X-tals. The X-tal to be connected to pin 34
must have a frequency of 3.5 MHz (NTSC-M, PAL-M or
PAL-N) and pin 35 can handle X-tals with a frequency of
4.4 and 3.5 MHz. Because the X-tal frequency is used to
tune the line oscillator the value of the X-tal frequency
must be given to the IC via the I2C-bus. It is also possible
to use the IC in the so called “Tri-norma” mode for South
America. In that case one X-tal must be connected to pin
34 and the other 2 to pin 35. The switching between the 2
latter X-tals must be done externally. This has the
consequence that the search loop of the decoder must be
controlled by the m-computer. To prevent calibration
problems of the horizontal oscillator the external switching
between the 2 X-tals should be carried out when the
oscillator is forced to pin 34. For a reliable calibration of the
horizontal oscillator it is very important that the X-tal
indication bits (XA and XB) are not corrupted. For this
reason the X-tal bits can be read in the output bytes so that
the software can check the I2C-bus transmission.

RGB output circuit and black-current stabilisation
The colour-difference signals are matrixed with the
luminance signal to obtain the RGB-signals. The TDA
884X devices have one (linear) RGB input. This RGB
signal can be controlled on contrast and brightness (like
TDA 8374/75). By means of the IE1 bit the insertion
blanking can be switched on or off. Via the IN1 bit it can be
read whether the insertion pin has a high level or not.
The TDA 885X IC’s have an additional RGB input. This
RGB signal can be controlled on contrast, saturation and
brightness. The insertion blanking of this input can be
switched-off by means of the IE2 bit. Via the IN2 bit it can
be read whether the insertion pin has a high level or not.
The output signal has an amplitude of about 2 volts
black-to-white at nominal input signals and nominal
settings of the controls. To increase the flexibility of the IC
it is possible to insert OSD and/or teletext signals directly
at the RGB outputs. This insertion mode is controlled via
the insertion input (pin 26 in the S-DIP 56- and pin 38 in the
QFP-64 envelope). This blanking action at the RGB
outputs has some delay which must be compensated
externally.
To obtain an accurate biasing of the picture tube a
“Continuous Cathode Calibration” circuit has been
developed. This function is realised by means of a 2-point
black level stabilisation circuit. By inserting 2 test levels for
each gun and comparing the resulting cathode currents
with 2 different reference currents the influence of the
picture tube parameters like the spread in cut-off voltage
can be eliminated. This 2-point stabilisation is based on
the principle that the ratio between the cathode currents is
coupled to the ratio between the drive voltages according
to:
The feedback loop makes the ratio between the cathode
currents Ik1 and Ik2 equal to the ratio between the
reference currents (which are internally fixed) by changing
the (black) level and the amplitude of the RGB output
signals via 2 converging loops. The system operates in
such a way that the black level of the drive signal is
controlled to the cut-off point of the gun so that a very good
grey scale tracking is obtained. The accuracy of the
adjustment of the black level is just dependent on the ratio
of internal currents and these can be made very accurately
in integrated circuits. An additional advantage of the
2-point measurement is that the control system makes the
absolute value of Ik1 and Ik2 identical to the internal
reference currents. Because this adjustment is obtained
by means of an adaption of the gain of the RGB control
stage this control stabilises the gain of the complete
channel (RGB output stage and cathode characteristic).
As a result variations in the gain figures during life will be
compensated by this 2-point loop.

An important property of the 2-point stabilisation is that the
off-set as well as the gain of the RGB path is adjusted by
the feedback loop. Hence the maximum drive voltage for
the cathode is fixed by the relation between the test
pulses, the reference current and the relative gain setting
of the 3 channels. This has the consequence that the drive
level of the CRT cannot be adjusted by adapting the gain
of the RGB output stage. Because different picture tubes
may require different drive levels the typical “cathode drive
level” amplitude can be adjusted by means of an I2C-bus
setting. Dependent on the chosen cathode drive level the
typical gain of the RGB output stages can be fixed taking

into account the drive capability of the RGB outputs (pins
19 to 21). More details about the design will be given in the
application report.
The measurement of the “high” and the “low” current of the
2- point stabilisation circuit is carried out in 2 consecutive
fields. The leakage current is measured in each field. The
maximum allowable leakage current is 100 mA
When the TV receiver is switched-on the RGB output
signals are blanked and the black current loop will try to set
the right picture tube bias levels. Via the AST bit a choice
can be made between automatic start-up or a start-up via
the m-processor. In the automatic mode the RGB drive
signals are switched-on as soon as the black current loop
has been stabilised. In the other mode the BCF bit is set to
0 when the loop is stabilised. The RGB drive can than be
switched-on by setting the AST bit to 0. In the latter mode
some delay can be introduced between the setting of the
BCF bit and the switching of the AST bit so that switch-on
effects can be suppressed.
It is also possible to start-up the devices with a fixed
internal delay (as with the TDA 837X and the TDA884X/5X
N1). This mode is activated with the BCO bit.
The vertical blanking is adapted to the incoming CVBS
signal (50 Hz or 60 Hz). When the flyback time of the
vertical output stage is longer than the 60 Hz blanking time
the blanking can be increased to the same value as that of
the 50 Hz blanking. This can be set by means of the LBM
bit.
For an easy (manual) adjustment of the Vg2 control voltage
the VSD bit is available. When this bit is activated the black
current loop is switched-off, a fixed black level is inserted
at the RGB outputs and the vertical scan is switched-off so
that a horizontal line is displayed on the screen. This line
can be used as indicator for the Vg2 adjustment. Because
of the different requirements for the optimum cut-off
voltage of the picture tube the RGB output level is
adjustable when the VSD bit is activated. The control
range is 2.5 ± 0.7 V and can be controlled via the
brightness control DAC.
It is possible to insert a so called “blue back” back-ground
level when no video is available. This feature can be
activated via the BB bit in the control2 subaddress.

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