Richtige Fernseher haben Röhren!

Richtige Fernseher haben Röhren!

In Brief: On this site you will find pictures and information about some of the electronic, electrical and electrotechnical technology relics that the Frank Sharp Private museum has accumulated over the years .

Premise: There are lots of vintage electrical and electronic items that have not survived well or even completely disappeared and forgotten.

Or are not being collected nowadays in proportion to their significance or prevalence in their heyday, this is bad and the main part of the death land. The heavy, ugly sarcophagus; models with few endearing qualities, devices that have some over-riding disadvantage to ownership such as heavy weight,toxicity or inflated value when dismantled, tend to be under-represented by all but the most comprehensive collections and museums. They get relegated to the bottom of the wants list, derided as 'more trouble than they are worth', or just forgotten entirely. As a result, I started to notice gaps in the current representation of the history of electronic and electrical technology to the interested member of the public.


Following this idea around a bit, convinced me that a collection of the peculiar alone could not hope to survive on its own merits, but a museum that gave equal display space to the popular and the unpopular, would bring things to the attention of the average person that he has previously passed by or been shielded from. It's a matter of culture. From this, the Obsolete Technology Tellye Web Museum concept developed and all my other things too. It's an open platform for all electrical Electronic TV technology to have its few, but NOT last, moments of fame in a working, hand-on environment. We'll never own Colossus or Faraday's first transformer, but I can show things that you can't see at the Science Museum, and let you play with things that the Smithsonian can't allow people to touch, because my remit is different.

There was a society once that was the polar opposite of our disposable, junk society. A whole nation was built on the idea of placing quality before quantity in all things. The goal was not “more and newer,” but “better and higher" .This attitude was reflected not only in the manufacturing of material goods, but also in the realms of art and architecture, as well as in the social fabric of everyday life. The goal was for each new cohort of children to stand on a higher level than the preceding cohort: they were to be healthier, stronger, more intelligent, and more vibrant in every way.

The society that prioritized human, social and material quality is a Winner. Truly, it is the high point of all Western civilization. Consequently, its defeat meant the defeat of civilization itself.

Today, the West is headed for the abyss. For the ultimate fate of our disposable society is for that society itself to be disposed of. And this will happen sooner, rather than later.

OLD, but ORIGINAL, Well made, Funny, Not remotely controlled............. and not Made in CHINA.

How to use the site:

- If you landed here via any Search Engine, you will get what you searched for and you can search more using the search this blog feature provided by Google. You can visit more posts scrolling the left blog archive of all posts of the month/year,
or you can click on the main photo-page to start from the main page. Doing so it starts from the most recent post to the older post simple clicking on the Older Post button on the bottom of each page after reading , post after post.

You can even visit all posts, time to time, when reaching the bottom end of each page and click on the Older Post button.

- If you arrived here at the main page via bookmark you can visit all the site scrolling the left blog archive of all posts of the month/year pointing were you want , or more simple You can even visit all blog posts, from newer to older, clicking at the end of each bottom page on the Older Post button.
So you can see all the blog/site content surfing all pages in it.

- The search this blog feature provided by Google is a real search engine. If you're pointing particular things it will search IT for you; or you can place a brand name in the search query at your choice and visit all results page by page. It's useful since the content of the site is very large.

Note that if you don't find what you searched for, try it after a period of time; the site is a never ending job !

Every CRT Television saved let revive knowledge, thoughts, moments of the past life which will never return again.........

Many contemporary "televisions" (more correctly named as displays) would not have this level of staying power, many would ware out or require major services within just five years or less and of course, there is that perennial bug bear of planned obsolescence where components are deliberately designed to fail and, or manufactured with limited edition specificities..... and without considering........picture......sound........quality........

..............The bitterness of poor quality is remembered long after the sweetness of todays funny gadgets low price has faded from memory........ . . . . . .....
Don't forget the past, the end of the world is upon us! Pretty soon it will all turn to dust!

Have big FUN ! !
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©2010, 2011, 2012, 2013, 2014 Frank Sharp - You do not have permission to copy photos and words from this blog, and any content may be never used it for auctions or commercial purposes, however feel free to post anything you see here with a courtesy link back, btw a link to the original post here , is mandatory.
All sets and apparates appearing here are property of
Engineer Frank Sharp. NOTHING HERE IS FOR SALE !

Tuesday, October 19, 2010

BRIONVEGA COSMO 2 TVC 26 CHASSIS 509 INTERNAL VIEW.






























































BRIONVEGA COSMO2 TVC 26. Internal Chassis and Tube viewing.
Developed with philips components.














































































Supply, Line + EHT and Frame deflection + E/W Correction, Frequency Synthesizer Tuning System (Without uC) like Philips TRD, Signal Section Parts.





















































































































































































 





















BRIONVEGA COSMO 2 TVC 26. Chassis detailed parts:
Front Local setup Commands keyboard, RGB Matrix (TDA2530) and RGB Amplifiers,
Luminance and Chrominance (TDA2560/3) (TDA2522), IF sound + Sound Amplifier,
Twin tuner (VHF + UHF) with prescaler unit, FRAME Deflection + E/W Correction in one Module, CRT Socket for PHILIPS A66-540X.


The BRIONVEGA CHASSIS 509.01 is developed and organized on 2 main sections and a central fitted power supply unit.


Right side Panel Line + EHT and Frame deflection + E/W Correction,

Left side panel Signal Section Parts.


SYNCHRONIZATION UNIT: 509.01.3561

FRAME DEFLECTION AND E/W CORRECTION UNIT:509.01.3701

SOUND I.F. + AMPL UNIT:509.01. (TDA4290 - TBA120U).

RGB AMPLIFIER UNIT:509.01.3941


The BRIONVEGA COSMO 2 TVC 26 CHASSIS 509 POWER SUPPLY Control UNIT is developed around the PHILIPS TDA2640.
"Television Switched-Mode Power Supply Using the TDA2640", Mullard Technical Communications, L. M. White, pp. 258-279, Jul. 1975.

A switched-mode power supply provided with a control stage and a switching stage coupled by means of a transformer. The collector of an additional transistor is connected to the transformer. In this manner the ratio of the collector current to the base current of the switching transistor can assume a predetermined value, for example a constant value whatever the value of the mains voltage applied to the power supply.

What is claimed is:

1. A control circuit for a switched-mode power supply, said power supply comprising a non-regulated rectified DC voltage source, a driver transistor, a first transformer having primary and secondary windings, an end of said primary being coupled to the collector-emitter path of said driver transistor, a switching transistor having a base coupled to said secondary, a second transformer having a primary winding coupled in series with said switching transistor, and a plurality of secondary windings, said control circuit comprising a first additional transistor having a collector coupled to the remaining end of the primary winding of the first transformer not connected to the driver-transistor and an emitter coupled to the non-regulated direct voltage source.

2. A control circuit as claimed in claim 1, further comprising a constant voltage source coupled to the base of the additional transistor.

3. A control circuit as claimed in claim 1, further comprising a constant current source, and a resistor coupled between the emitter of the additional transistor and the constant current source.

4. A control circuit as claimed in claim 3, wherein the constant current source comprises a second additional transistor, the two additional transistors being of complementary conductivity and their emitters being connected with each other through said resistor, the collector of the second additional transistor being coupled to the non-regulated rectified direct voltage source and the collector of the first additional transistor being coupled to the end of the primary winding of the first transformer not connected to the driver transistor.

5. A control circuit as claimed in claim 4, further comprising a resistor coupled in series with the collector circuit of said second additional transistor and the non-regulated rectified direct voltage source.

6. A control circuit as claimed in claim 5, further comprising a zener diode coupled between the base of the second additional transistor and the non-regulated voltage source.

7. A control circuit as claimed in claim 6, further comprising a resistance bridge coupled to the base of the first additional transistor and arranged between the two electrodes of the zener diode.

8. A control circuit as claimed in claim 7, wherein the driver transistor and the switching transistor do not conduct simultaneously, and the voltage between the two electrodes of the zener diode as well as the values of the resistors arranged between the said electrodes and of the resistor arranged between the emitters of the two additional transistors are chosen so that the first additional transistor is in the saturated state at the lowest value of the non-regulated voltage while it operates in the linear state at a higher value of said non-regulated voltage.

Description:
The present invention relates to a control circuit for a switched-mode power supply, particularly in a television receiver, said power supply comprising a rectified, non-regulated rectified DC voltage source, a driver transistor whose collector-emitter path is arranged in series with a primary winding of a first transformer, a secondary winding of the latter being coupled to the base of a switching transistor which is arranged in series with a primary winding of a second transformer having a plurality of secondary windings.
This type of switched-mode power supply is used more and more because of the numerous advantages it presents as regards energy efficiency, reliability, compactness, etc. However, as for the majority of the other types of power supplies, its operation on mains supplies of different voltages imposes the use of either a transformer with taps or switch-over from full wave rectification at the highest mains voltage to a voltage doubler rectification for the lowest mains voltage.
It is known that the specific qualities of a switched-mode power supply depend for a large part on the switching speed of the switching transistor at the moment at which the latter passes periodically from the conductive state to the blocking state; this speed is at its maximum when the switching transistor presents, at the turn-off moment, a certain ratio between the collector current and the base current IC/IB: if this ratio is too low, the delay in the recombination of the charges stored in the base increases the switching time; if it is too high there is the risk that the transistor is brought out of saturation before it is blocked, which results in its substantially immediate destruction. For the known switched-mode power supplies it is not possible to maintain a suitable IC/IB ratio in the presence of large variations of the non-regulated rectified DC voltage which result from the connection to the nominal mains voltages of, for example, 110 or 220 V; actually, if the variations in IB are substantially proportional to the variations in the non-regulated voltage, the same does not happen for those of the IC whose amplitude is less.
However, the importance of having a power supply which can operate without any switching on mains supplies of 110 or 220 V is evident: for the manufacturer it is cheaper to produce and the reliability is increased; while the user does not run the risk of incorrect manipulations, particularly when the power supply is destined for use in portable television sets.
One of the objects of the invention is to realize a control circuit which permits the switched-mode power supply to operate without switching in conditions which are substantially optimum and in the presence of mains voltage variations in the range of 90 to 250 Volts.
A further object of the invention is to ensure that said IC/IB ratio of the switching transistor has a predetermined and, more particularly a constant value at the turn-off moment whatever the value of the mains voltage applied to the power supply.
The control circuit according to the invention is characterized in that the end of the primary winding of the first transformer not connected to the driver transistor is connected to the collector of an additional transistor whose emitter is coupled with the non-regulated direct voltage source. Advantageously it is characterized in that the emitter of the additional transistor is connected to one end of a resistor, the other end of this resistor being connected to a constant current source, and that the constant current source is constituted by a second additional transistor, the two additional transistors being of complementary conductivity and their emitters being connected with each other through a resistor, whilst the collector of the second additional transistor is connected to one of the poles of the non-regulated rectified direct voltage source and the collector of the first additional transistor is connected to the end of the primary winding of the first transformer not connected to the driver transistor.
Whilst combining the action of a ballast transistor with that of a variable current generator, the circuit according to the invention thus maintains automatically a desired IC/IB ratio of the switching transistor whatever the value of the mains voltage applied to the power supply.

BRIONVEGA COSMO 2 TVC 26 CHASSIS 509 Digital phase locked loop tuning system / PLL FREQUENCY SYNTHESIZER:

A phase locked loop circuit for use in an automatic frequency synthesizing system. The system includes a programmer circuit which is responsive to a channel number input signal and generates a first digital control signal which is representative of the selected channel number and a second digital control signal which is representative of a predetermined group of channel numbers. A programmable divider is controlled by the programming circuit and generates a digital output signal which causes the phase locked loop circuit to generate a desired system output frequency corresponding to the selected channel number input signal. The phase locked loop circuit includes automatic fine tuning and manual fine tuning features.


1. A digital phase locked loop tuning system responsive to a local oscillator signal for producing a frequency synthesized digital output signal which is utilized to control the frequency of the local oscillator, the local oscillator having a plurality of frequencies associated therewith corresponding, respectively, to a plurality of selectable channels, each of the channels being allocated to one of at least two channel groups with each channel in a particular channel group being separated from an adjacent channel in the particular channel group by a predetermined frequency spacing of the local oscillator, comprising:

programming means responsive to an input signal representing a selected channel number of a particular channel group for generating a first digital control signal having a value corresponding to the selected channel number and for generating a second digital control signal representative of said particular channel group, said second digital control signal being a constant predetermined value for all of said channel numbers that are within said group; and
programmable divider means coupled to said programming means being responsive to said first, second digital control signals and the local oscillator signal, in a local oscillator mode, for generating the digital output signal which is representative of a desired frequency corresponding to said selected channel number, said programmable divider means including means for dividing the local oscillator signal by first and second factors, said first factor being related to the frequency separation between local oscillator signals by an integral number, the local oscillator signal being divided by said first factor during a first interval for a first number of periods of the output signal and being divided by said second factor for a second number of periods of the output signal, said first number of periods being related to the number of the channel selected, said second number being related to the channel group within which the selected channel lies.
2. Phase locked loop system according to claim 1, wherein said programming means including means coupled to said programming means for receiving an MFT signal and being responsive to said MFT signal for altering said first and second digital control signals, and said programmable divider means being responsive to said altered digital control signals for generating an altered system output frequency. 3. Phase locked loop system according to claim 2, wherein said programming means includes first terminal means coupled to said programming means for receiving an AFT control signal, and first logic means responsive to the input signal and the AFT control signal for generating the first digital control signal. 4. Phase locked loop system according to claim 3, wherein said programming means includes second logic means coupled to said first logic means and responsive to the AFT control signal for generating the second digital control signal. 5. Phase locked loop system according to claim 4, wherein said second logic means includes group decoder means coupled to said first logic means. 6. Phase locked loop circuit means according to claim 5, wherein said second logic means includes memory means coupled to said group decoder means and to said first terminal means. 7. Phase locked loop system according to claim 6, wherein said second logic means includes second terminal means for receiving an MFT signal, and up/down counter latch means coupled to said memory means and to said second terminal means for altering said first and second digital control signals in response to said MFT signal. 8. Phase locked loop system according to claim 7, wherein said second logic means includes adder means coupled to said up/down counter latch means to said memory means. 9. Phase locked loop system according to claim 3, wherein said first logic means includes channel number generator means coupled to said first terminal means and responsive to said input signal. 10. Phase locked loop system according to claim 9, wherein said channel number generator means includes first and second data selector means coupled to said first terminal means, and adder means coupled to said second data selector means and to said up/down counter latch means. 11. Phase locked loop system according to claim 1, wherein said means for dividing the local oscillator signal includes programmable counter means for generating a modulus control output signal, and variable modulus prescaler divider means coupled to and responsive to said programmable counter means, said variable modulus prescaler divider means dividing the local oscillator signal by said first and second factors. 12. Phase locked loop system according to claim 11, wherein said programmable counter means includes third data selector means coupled to receive said first and second digital control signals and said modulus control signal. 13. Phase locked loop system according to claim 12, wherein said programmable counter means includes a programmable counter coupled to said third data selector means and to said variable modulus prescaler divider means. 14. Phase locked loop system according to claim 13, wherein said programmable counter means includes look ahead circuit means coupled to said programmable counter, and divide by two circuit means coupled to said look ahead circuit means for generating said modulus control output signal. 15. Phase locked loop tuning system according to claim 1 including digital automatic fine tuning (AFT) means wherein:
said programmable divider means includes switching means responsive to an AFT control signal to inhibit the local oscillator signal to said programmable divider means and to provide an input signal thereto of a different frequency than the local oscillator signal; and
said programming means including logic means responsive to said AFT control signal for altering said first and second digital control signals to predetermined values to cause the phase locked loop tuning system to be operable in an automatic fine tuning mode.
16. Phase locked loop tuning system of claim 15 wherein said programmable divider means includes:
programmable counter means for generating first and second modulus control signals; and
dual modulus prescaler means responsive to said first modulus control signal for dividing the local oscillator signal in said local oscillator mode and said input signal of a different frequency in said automatic fine tuning mode by said first factor which is equal to the integer six and being responsive to said second modulus control signal for dividing said local oscillator signal and said input signal of a different frequency by said second factor which is equal to the integer five respectively.
17. Phase locked loop tuning system of claim 16 wherein said signal of a different frequency is an intermediate frequency signal provided by the tuning system and supplied to said switching means.
18. In a phase locked loop tuning system for receiving a channel number input signal and a local oscillator signal having groups of selectable frequencies wherein the frequency spacing between each adjacent local oscillator frequency within a single group is uniform, the improvement comprising programmable divider means for generating a digital output signal representative of a desired tuning system output frequency including variable modulus prescaler divider means having a prescaler division ratio being equal to P = S/Y' for dividing the local oscillator frequency by said prescaler division ratio during a first interval for a first number of periods of the digital output signal and for dividing the local oscillator frequency by a second prescaler division ratio during a second interval for a second number of periods, said second ratio being related to said first ratio, where S is the frequency spacing between each adjacent local oscillator frequency within a single group (i), Yi =Di -Xi S, where Di is said desired tuning system output frequency within said selected group; Xi =Di /S rounded off to the nearest integer; Y' is chosen such that Yi /Y' is an integer and S/Y' is an integer and Y' is the smallest value of all values of Yi. 19. In a receiver including a tuning apparatus for providing a plurality of local oscillator signals each corresponding to a respective one of a plurality of selectable channels, each of the channels being allocated to one of at least two channel groups wherein each channel is separated from an adjacent channel in the respective channel group by a predetermined frequency spacing, a phase locked loop tuning system for producing a frequency synthesized output signal for controlling the frequency of the local oscillator, comprising:
variable modulus divider means for selectively dividing the frequency of the local oscillator signal by first and second factors in response to a modulus control signal to provide an output signal, said first factor being related to the frequency separation between local oscillator signals by an integral number; and
programmable means for generating said modulus control signal to cause said variable modulus divider means to divide by said first factor during a first interval for a first number of periods of said output signal and to divide by said second factor during a second interval for a second number of periods of said output signal, said first number of periods being related to the number of the channel selected, said second number of periods being related to the channel group corresponding to the selected channel.
20. The phase locked loop tuning system of claim 19 wherein said programmable means includes:
programming means responsive to a selected channel input signal for producing first and second digital output signals, said first digital output signal being related to the selected channel number plus one of two constant values which are determined in accordance within which channel group the selected channel input signal lies, said second digital signal being a constant value for all selected channels within a channel group; and
programmable divider means responsive to said first and second digital output signals from said programming means for providing said variable modulus control signal and the frequency synthesized output signal.
21. The phase locked loop tuning system of claim 20 wherein said programming means includes automatic fine tuning (AFT) means responsive to a AFT control signal being applied thereto when the receiver is placed in an AFT mode wherein:
said variable modulus divider means is caused to receive a input signal different from the local oscillator signal;
said programming means being responsive to the AFT control signal for altering said first and second digital signals such that the receiver is finely tuned to the frequency of the received signal applied to the receiver.
22. The phase locked loop tuning system of claim 21 wherein said programming means includes means for receiving a manual fine tuning (MFT) signal for altering said first and second digital output signals, and said programmable divider means being responsive to said altered digital control signals for generating an altered output signal. 23. The phase locked loop tuning system of claim 19 wherein the one of said first and second factors is an even number and the other is an odd number. 24. The phase locked loop tuning system of claim 23 wherein said first factor is the integer six and said second factor is the integer five.
Description:
BACKGROUND OF THE INVENTION
This invention relates to digital tuning systems, and more particularly, to a simplified digital phase locked loop (PLL) tuning system incorporating unique digital automatic fine tuning and manual fine tuning schemes.
Since the appearance of varactor tuners for television, many tuning address schemes have evolved for controlling them. PLL techniques have maintained a performance advantage but have suffered a cost disadvantage due to complexity, the high frequencies involved, the need for automatic fine tuning and in some localities, the need for a manual fine tuning arrangement. With the advances that have taken place in semiconductor technology in the last several years, the high operating frequencies no longer present a significant problem.
Prior art PLL systems for use in television tuners have not yet been able to incorporate an automatic fine tuning feature, nor have they been able to incorporate a manual fine tuning system which would enable the PLL tuning system to be intentionally offset in predetermined increments. Television sets normally have an automatic fine tuning (AFT) feature, but this is normally incorporated as a separate circuit which is not directly incorporated into the television tuner.
An additional disadvantage of prior art PLL systems which are designed for use in a television tuner environment is that they are highly complex and relatively expensive. In order to convert the channel number input into the proper digital control signals for the PLL, a relatively large ROM having a capacity on the order of 82 words by 12 bits was required. The best prior art PLL tuning systems require two high speed programmable counters which greatly increase the system complexity. This together with the large ROM which the system required, greatly decreased the cost effectiveness of the system so that commercial manufacturers were able to use these prior art PLL systems only in their most expensive commercial television receivers.
Therefore, it is a feature of this invention to provide a digital PLL tuning system which incorporates design techniques that vastly simplify the complexity of the PLL while at the same time allowing the system to meet the latest needs of a television tuning system or any other PLL tuning system which is addressed by a channel number.
It is another feature of this invention to provide a digital PLL tuning system that has the ability to automatically tune nonprecise station frequencies and the ability to be manually fine tuned.
It is yet another feature of the present invention to provide a digital PLL tuning system having only a single high speed programmable counter and requiring a ROM capacity of only 5 words by 9 bits.
It is still another feature of this invention to provide a digital PLL tuning system which performs the automatic fine tuning feature by utilizing the PLL tuning system as a digital discriminator.
It is yet another feature of this invention to provide a digital PLL tuning system incorporating a manual fine tuning (MFT) arrangement which is capable of intentionally offsetting the local oscillator frequency of a TV tuner in one megahertz steps or of offsetting TV IF frequency in steps of 125 kilohertz.
SUMMARY OF THE INVENTION
The preferred embodiment of the present invention includes a phase locked loop circuit means for an automatic frequency synthesizing system. The phase locked loop circuit means includes programming means which is responsive to an input signal representing a selected channel number for generating a first digital control signal representative of the selected channel number and for generating a second digital control signal representative of a predetermined group of channel numbers. A programmable divider means is coupled to the first and second digital control signals and generates a digital output signal representative of a desired system output frequency corresponding to the selected channel number.
The phase locked loop circuit means further includes an automatic fine tuning feature for fine tuning the phase locked loop output frequency to the exact frequency of the received signal. The system further includes a manual fine tuning provision which allows the phase locked loop operating frequency to be intentionally offset in predetermined increments.



PHILIPS TDA2593 SYNCHRO AND HORIZONTAL DEFLECTION CONTROL FOR COLOR TV SET

DESCRIPTION
The TDA2593 is a circuit intended for the horizontal
deflectionof color TVsets, suppliedwith transistors
or SCR’S.

.LINE OSCILLATOR(two levels switching) .PHASE COMPARISON BETWEEN SYNCHRO-
PULSE AND OSCILLATOR VOLTAGE
Ø 1, ENABLED BY AN INTERNAL PULSE,
(better parasitic immunity) .PHASE COMPARISON BETWEEN THE FLYBACK
PULSES AND THE OSCILLATORVOLTAGE
Ø2 .COINCIDENCE DETECTOR PROVIDING A
LARGE HOLD-IN-RANGE .FILTER CHARACTERISTICS AND GATE
SWITCHING FOR VIDEO RECORDER APPLICATION
.NOISE GATED SYNCHRO SEPARATOR .FRAME PULSE SEPARATOR .BLANKING AND SAND CASTLE OUTPUT
PULSES .HORIZONTAL POWER STAGE PHASE LAGGING
CIRCUIT .SWITCHING OF CONTROL OUTPUT PULSE
WIDTH .SEPARATED SUPPLY VOLTAGE OUTPUT
STAGE ALLOWING DIRECT DRIVE OF
SCR’S CIRCUIT .SECURITY CIRCUIT MAKES THE OUTPUT
PULSE SUPPRESSED WHEN LOW SUPPLY
VOLTAGE.

A phase-lock loop circuit of a video display apparatus is synchronized by a horizontal synchronizing input signal. The phase-lock loop circuit includes a frequency-to-voltage converter that is responsive to the synchronizing input signal for generating a control voltage indicative of the frequency of the synchronizing input signal. A voltage-to-current converter responsive to the control voltage generates a control current that is indicative of the frequency of the input signal. The control current varies the free running frequency of a controlled oscillator of the phase-lock loop circuit such that the free running frequency of the oscillator is directly related to the frequency of the input signal. The phase of the output signal of the oscillator is controlled by a second control current that is indicative of the phase difference between the oscillator output signal and the synchronizing input signal. When the frequency of the input signal is lower than a predetermined frequency, the first control current is at a level that causes the free running frequency to be above a predetermined minimum frequency.



TDA2522 PAL TV CHROMA DEMODULATOR COMBINATION
FAIRCHILD LINEAR INTEGRATED CIRCUIT
GENERAL DESCRIPTION- The TDA2522 is a monolithic integrated circuit designed as
a synchronous demodulator for PAL color television receivers. It includes an 8,8 MHz
oscillator and divider to generate two 4.4 MHz reference signals and provides color difference outputs.
PACKAGE OUTLINE 9B

The TDA2522 is Intended to Interface directly with the TDA2560 with a minimum oF external components. The TDA2530 may be added if RGB drive is required. The TDA2522
is constructed using the Fairchild Planar* process.





TDA2560 LUMINANCE AND CHROMINANCE CONTROL COMBINATION
The TDA2560 is a monolithic integrated circuit for use in decoding systems of COLOR
television receivers. The circuit consists of a luminance and chrominance amplifier.
The luminance amplifier has a low input impedance so that matching of the luminance
delay line is very easy.
It also incorporates the following functions:
- d.c. contrast control;
- d.c. brightness control;
- black level clamp;
- blanking;
- additional video output with positive-going sync.
The chrominance amplifier comprises:
- gain controlled amplifier;
- chrominance gain control tracked with contrast control;
- separate d.c. saturation control:
- combined chroma and burst output, burst signal amplitude not affected by contrast and
saturation control;
- the delay line can be driven directly ‘by the IC.

APPLICATION INFORMATION (continued)
The function is quoted against the corresponding pin number
Balanced chrominance input signal (in conjunction with pin 2)
This is derived from the chrominance signal bandpass filter, designed to provide a
push-pull input. A signal amplitude of at least 4 mV peak-to-peak is required
between pins l and 2. The chrominance amplifier is stabilized by an external feedback
loop from the output (pin 6) to the input (pins I and 2). The required level at pins l
and 2 will be 3 V.
All figures for the chrominance signals are based on a colour bar signal with 75%
saturation: i.e. burst-to-chrominance ratio of input signal is 1 1 2.
Chrominance signal input (see pin 1)
A. C.C. input
A negative-going potential, starting at +l,2 V, gives a 40 dB range of a. c. c.
Maximum gain reduction is achieved at an input voltage of 500 mV.
Chrominance saturation control
A control range of +6 dB to >-14 dB is provided over a range of d. c. potential on
pin 4 from +2 to +4 V. The saturation control is a linear function of the control
voltage.
Negative supply (earth)
Chro minance signal output
For nominal settings of saturation and contrast controls (max. -6 dB for saturation,
and max. -3 dB for contrast) both the chroma' and burst are available at this pin, and
in the same ratio as at the input pins 1 and 2. The burst signal is not affected by the
saturation and contrast controls. The a.c. c. circuit of the TDA2522 will hold
constant the colour burst amplitude at the input of the TDA2522. As the PAL delay
line is situated here between the TDA256O and TDA2522 there may be some variation
of the nominal 1 V peak-to-peak burst output of the TDA2560, according to the
tolerances of the delay line. An external network is required from pin 6 of the
TDA256O to provide d. c. negative feedback in the chroma channel via pins I and 2.
Burst gating and clamping pulse input
A two-level pulse is required at this pin to be used for burst gate and black level
clamping. The black level clamp is activated when the pulse level is greater than
7 V. The timing of this interval should be such that no appreciable encroachment
occurs into the sync pulse on picture line periods during normal operation of the
receiver. The burst gate, which switches the gain of the chroma amplifier to
maximum, requires that the input pulse at pin 7 should be sufficiently wide, at least
8 ps, at the actuating level of 2,3 V.

+12 V power supply
Correct operation occurs within the range 10 to 14 V. All signal and control levels
have a linear dependency on supply voltage but, in any given receiver design, this
range may be restricted due to considerations of tracking between the power supply
variations and picture contrast and chroma levels.
Flyback blanking input waveform
This pin is used for blanking the luminance amplifier. When the input pulse exceeds
the +2, 5 Vlevel, the output signal is blanked to a level of about 0 V. When the input
exceeds a +6 V level, a fixed level of about 1, 5 V is inserted in the output. This
level can be used for clamping purposes.
Luminance sigal output
An emitter follower provides a low impedance output signal of 3 V black-to-white
amplitude at nominal contrast setting having a black level in the range 1 to 3 V. An
external emitter load resistor is not required.
The luminance amplitude available for nominal contrast may be modified according
to the resistor value from pin 13 to the +12 V supply. At an input bias current
114 of 0,25 mA during black level the amplifier is compensated so that no black
level shift more than 10 mV occurs at contrast control. When the input current
deviates from the quoted value the black level shift amounts to 100 mV/rnA.
Brightness control
The black level at the luminance output (pin 10) is identical to the control voltage
required at this pin, A range of black level from l to 3 V may be obtained.
Black level clamp capacitor
Luminance gain setting resistor
The gain of the luminance amplifier may be adjusted by selection of the resistor
value from pin 13 to +12 V. Nominal luminance output amplitude is then 3 V
black-to-white at pin 10 when this resistor is 2, 7 l


TDA2530 RGB MATRIX PREAMPLIFIER
The TDA2530 is an integrated RGB -matrix preamplifier for colour television receivers,
incorporating a matrix preamplifier for RGB cathode drive of the picture tube with
clamping circuits. The three channels have the same layout to ensure identical frequency
behaviour.
This integrated circuit has been designed to be driven from the TDA2522 Synchronous
demodulator and oscillator IC.











PHILIPS TDA2653A Vertical deflection circuit

DESCRIPTION
The TDA2653A is a monolithic integrated circuit for vertical deflection in large screen colour television receivers.
The circuit incorporates the following functions:
· Oscillator; switch capability for 50 Hz/60 Hz operation
· Synchronization circuit
· Blanking pulse generator with guard circuit
· Sawtooth generator with buffer stage
· Preamplifier with fed-out inputs
· Output stage with thermal and short-circuit protection
· Flyback generator
· Voltage stabilizers.

APPLICATION INFORMATION
The function is described against the corresponding pin number
1, 13. Oscillator
The oscillator frequency is determined by a potentiometer at pin 1 and a capacitor at pin 13.
2. Sync input/blanking output
Combination of sync input and blanking output. The oscillator has to be synchronized by a positive-going
pulse between 1 and 12 V. The integrated frequency detector delivers a switching level at pin 12.
The blanking pulse amplitude is 20 V with a load of 1 mA.
3. Sawtooth generator output
The sawtooth signal is fed via a buffer stage to pin 3. It delivers the signal which is used for linearity control,
and drive of the preamplifier. The sawtooth is applied via a shaping network to pin 11 (linearity) and via a
resistor to pin 4 (preamplifier).
4. Preamplifier input
The DC voltage is proportional to the output voltage (DC feedback). The AC voltage is proportional to the
sum of the buffered sawtooth voltage at pin 3 and the voltage, with opposite polarity, at the feedback
resistor (AC feedback).
5. Positive supply of output stage
This supply is obtained from the flyback generator. An electrolytic capacitor between pins 7 and 5, and a
diode between pins 5 and 9 have to be connected for proper operation of the flyback generator.
6. Output of class-B power stage
The vertical deflection coil is connected to this pin, via a series connection of a coupling capacitor and a
feedback resistor, to ground.
7. Flyback generator output
An electrolytic capacitor has to be connected between pins 7 and 5 to complete the flyback generator.
8. Negative supply (ground)
Negative supply of output stage and small signal part.
9. Positive supply
The supply voltage at this pin is used to supply the flyback generator, voltage stabilizer, blanking pulse
generator and buffer stage.
10. Reference voltage of preamplifier
External adjustment and decoupling of reference voltage of the preamplifier.
11. Sawtooth capacitor
This sawtooth capacitor has been split to realize linearity control.
12. 50 Hz/60 Hz switching level
This pin delivers a LOW voltage level for 50 Hz and a HIGH voltage level for 60 Hz. The amplitudes of the
sawtooth signals can be made equal for 50 Hz and 60 Hz with these levels.




TDA2545A TDA2546Quasi-split-sound circuit:
GENERAL DESCRIPTION The TDA2545A is a monolithic integrated circuit for quasi-split-sound processing in television receivers. Features · 3-stage gain controlled i.f. amplifier · A.G.C. circuit · Reference amplifier and limiter amplifier for vision carrier (V.C.) processing · Linear multiplier for quadrature demodulation.


TDA2541 IF AMPLIFIER WITH DEMODULATOR AND AFC

DESCRIPTION
The TDA2540 and 2541 are IF amplifier and A.M.
demodulator circuits for colour and black and white
televisionreceiversusingPNPorNPNtuners. They
are intended for reception of negative or positive
modulation CCIR standard.
They incorporate the following functions : .Gain controlled amplifier .Synchronous demodulator .White spot inverter .Video preamplifier with noise protection .Switchable AFC .AGC with noise gating .Tuner AGC output (NPN tuner for 2540)-(PNP
tuner for 2541) .VCR switch for video output inhibition (VCR
play back).















































BRIONVEGA COSMO 2 TVC 26. Chassis detailed viewing:
Line output transistor (RCA BU208A), PCB Power part (large signals) view, PCB Signal Part (small signals) view.
509.01.3492


BU208(A)

Silicon NPN
npn transistors,pnp transistors,transistors
Category: NPN Transistor, Transistor
MHz: <1 MHz
Amps: 5A
Volts: 1500V
HIGH VOLTAGE CAPABILITY
JEDEC TO-3 METAL CASE.

DESCRIPTION
The BU208A, BU508A and BU508AFI are
manufactured using Multiepitaxial Mesa
technology for cost-effective high performance
and use a Hollow Emitter structure to enhance
switching speeds.

APPLICATIONS:
* HORIZONTAL DEFLECTION FOR COLOUR TV With 110° or even 90° degree of deflection angle.

ABSOLUTE MAXIMUM RATINGS
Symbol Parameter Value Unit
VCES Collector-Emit ter Voltage (VBE = 0) 1500 V
VCEO Collector-Emit ter Voltage (IB = 0) 700 V
VEBO Emitter-Base Voltage (IC = 0) 10 V
IC Collector Current 8 A
ICM Collector Peak Current (tp < 5 ms) 15 A
TO - 3 TO - 218 ISOWATT218
Ptot Total Dissipation at Tc = 25 oC 150 125 50 W
Tstg Storage Temperature -65 to 175 -65 to 150 -65 to 150 oC
Tj Max. Operating Junction Temperature 175 150 150 °C.

BRIONVEGA COSMO 2 TVC 26 CHASSIS 509 Electronic digital clocks:

 This invention relates to an electronic digital clock having at least one time-programmed electrical output for triggering switching functions.

Electronic clocks providing a digital display are known, in which a constant-frequency signal is applied to a clock circuit. The constant-frequency signal can be generated by a crystal or can be derived from the electrical mains supply. The clock circuit generates coded signals, usually BCD signals, which are applied to
a display logic circuit. The display logic circuit in turn drives for example a seven segment display. The switching sequence of the coded signals and the display logic circuit is determined by a multiplexer which is supplied with pulses from the clock circuit. In this fashion, it is possible to provide an opto-electronic digital time display, which may for example include a display of the day of the week.

Time switches are known which have a time-programmed electrical output in order to trigger switching functions. The time-programming is performed mechanically by a timer disc which at a preset time, which is determined mechanically, closes or opens switching contacts. In electronic digital equipment such an arrangement is not possible because no mechanical moving parts are present.

In electronic digital clocks it is, however, known to provide a time switching function. For this purpose, an electronic store is provided and, when the stored value corresponds with the time displayed by the clock, a signal triggering a switching function is generated. The store can consist of a decade counter pulsed by the clock circuit. A disadvantage of such an arrangement is the relatively high outlay in circuitry involved in the execution of just one switching function. A further disadvantage resides in the fact that in the event of any interruption in the current supply the store is erased and the information has to be restored into it.

This invention seeks to provide a clock in which at least the former disadvantage is reduced.

According to this invention there is provided an electronic digital clock having at least one time-programmed electrical output for triggering switching functions, the clock comprising a digital electrical time display, a clock circuit for producing and applying to said display coded signals representing time, a multiplexer, at least one coded fixed-value store, a sampling logic circuit and a comparator circuit, wherein coded values stored in the fixed-value store are sampled under the control of the multiplexer by the sampling logic circuit and are compared in the comparator circuit with said coded signals representing time, and wherein in the event of coincidence between the sampled values and the coded signals representing time an output signal is produced at said time-programmed electrical output.

It is possible in this fashion to provide a virtually arbitrary number of stores without increasing the outlay in circuitry as a consequence of the number of stores. By using fixed-value stores which comprise coding switches, it is also possible to contrive that even after an interruption in the current supply, the stored value previously written in is retained un-disturbed. A further advantage resides in the fact that the stored values adjusted can be read out at any time, i.e. it is possible at any desired time to determine which store is set to which value.



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