The SHARP 54DT-25S CHASSIS CA-1 is a monocarrier chassis featuring all functions on one board.
Mainly based around the PHILIPS TDA8840 IS A I2C-bus controlled single chip TV processors which IS intended to be applied in PAL, NTSC, PAL/NTSC and multi-standard television receivers.
THE SHARP 54DT-25S CHASSIS CA-1 is quite sophisticated and many parts are discretes realized in a complicated way.
SHARP 54DT-25S CHASSIS CA-1 Switching power supply unit:
An inexpensive power supply unit which may be used for video display devices is provided. The unit saves power when supplying power to a light load, such as during remote control standby. Power for a controller which controls each part of a video display device is supplied from the switching power supply. Power consumption of the switching power supply is reduced by extending an OFF period setting for the switching power supply when operation of a display drive circuit is turned off.
The present invention relates to switching circuitry wherein a low-loss "drive" inductance is "charged" and "discharged" to provide the energy for turning a power switch on and off. The drive-inductance and a tapped-winding transformer co-act in a novel manner to provide a large "sweep-out" current that quickly turns off the power switch, the sweep-out time being extremely short.
FIELD OF THE INVENTION
The present invention relates to the field of power supply units generally, and more specifically to exemplary power supply units which are used for video display devices including television sets and display monitors for computers.
BACKGROUND OF THE INVENTION
Conventional power supply units for video display devices, for example television sets, use a single converter for supplying the power necessary for heavy loads such as during watching TV and for light loads when the TV is turned off or in the remote control standby state by employing a self-excited power supply (hereafter referred to as "switching power supply"). This system, however, causes great loss in the remote control standby state because the energy continuously regenerates in the switching element and transformer. (Refer to Japanese Laid-open Patent H4-172090.)
One alternative system is to employ two power supplies: a main power supply and a power supply for a control means such as a microcomputer (hereafter referred to generically as the microcomputer).
1. A switching power supply unit comprising:
ON period control means for controlling an ON period;
minimum OFF period setting means for setting a minimum time amount for an OFF period; and
OFF period control means for controlling the setting of the OFF period;
wherein said ON period control means controls output voltage of said switching power supply unit by controlling said ON period while said OFF period control means fixes the OFF period to the minimum time amount for the OFF period; and
said OFF period control means controls output voltage of said switching power supply unit by controlling the OFF period while said ON period control means fixes the ON period to a fixed minimum time amount of said ON period responsive to the output voltage of said switching power supply unit dropping.
2. A power supply unit according to claim 1, wherein said controller for the main converter comprises an OFF period setting circuit, wherein said OFF period setting circuit determines an OFF period based on a specified minimum OFF period and a period controlled by a feedback signal.
3. A power supply unit according to claim 1, including a transformer and wherein said controller for the main converter comprises: a capacitor
an ON period controller which discharges voltage charged in said capacitor and controls an ON period based on the terminal voltage of said capacitor and a control voltage in response to a feedback signal;
an OFF period controller which charges said capacitor and controls the OFF period based on the terminal voltage of said capacitor and the control voltage in response to a feedback signal; and
a transformer reset detector which suppresses the turning on of a switching device during resonance of said transformer.
4. A power supply unit according to claim 1, wherein said controller for the main converter comprises: a capacitor;
means for setting a specified voltage; and
an OFF period controller which increases charge voltage of said capacitor to said specified voltage at a first rate of charge and then further increases voltage at a rate of charge less than the first rate of charge, to a voltage above said specified voltage to a control voltage, the control voltage being based on a feedback signal.
5. A power supply unit according to claim 1, wherein said controller for the main converter comprises an OFF period controller, the OFF period controller comprising: means for setting a specified voltage and
means for charging voltage of a capacitor to said specified voltage at substantially high speed,
wherein said means for charging voltage is used for determining a minimum OFF period.
6. A power supply unit according to claim 1 wherein the power supply unit is a power supply unit for a video display device, the power supply unit comprising: an output voltage terminal for outputting multiple levels of voltage;
a first output voltage terminal for outputting voltage applied to a display drive circuit of the video display device using a switching means; and
a second output voltage terminal for outputting voltage applied to a controller which controls on and off of said switching means;
whereby an OFF period setting of the power supply unit is extended when said switching means is turned off.
7. A power supply unit according to claim 1 wherein the power supply unit is a power supply unit for a video display device, the power supply unit comprising: a first switching power supply for supplying power supply voltage to a display drive circuit of the video display device and a second switching power supply for supplying power supply voltage to a signal processor and a range of controllers; whereby an OFF period setting of said second switching power supply is extended when said first switching power supply is turned off by a switching means.
8. A switching power supply unit comprising: i) a first switching power supply unit;
ii) a second switching power supply unit for supplying power for less load than said first switching power supply unit supplies, said second switching power supply unit comprising:
a) means for switching on or off power for said first switching power supply unit;
b) ON period control means for controlling ON period;
c) minimum OFF period setting means for setting a minimum time amount of an OFF period;
d) OFF period control means for controlling the setting of the OFF period;
said OFF period control means controls output voltage of said second switching power supply unit by controlling the OFF period when said ON period control means fixes the ON period to a fixed minimum ON period while said second switching power supply unit switches off power for said first switching power supply unit.
9. A power supply unit according to claim 8, wherein the power supply unit is a power supply unit for a video display device, and the first load is a display drive circuit of the video display device.
1. Switching circuitry comprising:
a control switch;
a drive circuit comprising a charge circuit and a discharge circuit;
a drive inductor;
a drive transformer;
said drive transformer having a charge primary winding, a discharge primary winding, and a secondary winding;
said charge circuit comprising said secondary winding and a series circuit of said drive inductor, said control switch, and said charge primary winding;
whereby when said control switch assumes its ON state, a charge current in said charge circuit charges said drive inductor, and produces an enabling signal in said secondary winding;
a power switch adapted to permit the flow of an electric current therethrough;
means for applying said enabling signal to said power switch, for causing said power switch to quickly and positively assume its ON state and for permitting the flow of a load current;
said discharge circuit comprising said secondary winding and a series circuit of said drive inductor and said discharge primary winding;
whereby, when said control switch assumes its OFF state, the energy of said charged drive inductor directly produces a discharge current, and said discharge current in said discharge circuit produces a disabling signal in said secondary winding;
means for applying said disabling signal to said power switch for causing said power switch to quickly and positively assume its OFF state, and for terminating the flow of the load current.
2. The invention of claim 1, wherein said control switch and said power switch are transistors.
3. The invention of claim 1, wherein said discharge circuit further comprises blocking diode means for blocking said charge current from flowing in said discharge circuit.
4. The invention of claim 1, including a second drive circuit; means for causing said power switch to function as a control switch for said second drive circuit,
whereby said drive circuits are cascaded.
5. The invention of claim 1, including a plurality of control switches, a corresponding plurality of drive circuits associated with respective ones of said control switches, and a corresponding plurality of power switches associated with respective ones of said drive circuits; means for causing said control-circuit means to conductivate said individual control switches of said plurality of control switches in a sequential timed manner;
whereby said individual drive circuits and said individual power switches are energized in a corresponding sequential timed manner.
6. Switching circuitry comprising: a control transistor;
control-circuit means for controlling the ON/OFF state of said control transistor;
a drive circuit comprising a charge circuit and a discharge circuit;
a drive inductor;
a drive transformer;
said drive transformer having a charge primary winding, a discharge primary winding, and a secondary winding;
said charge circuit comprising said secondary winding, blocking diode means for blocking said charge current from flowing in said discharge circuit and a series circuit of said drive inductor, said control switch, and said charge primary winding;
whereby, when said control transistor assumes its ON state, a charge current in said charge circuit charges said drive inductor, and produces an enabling signal in said secondary winding;
a power transistor adapted for the flow of an electric current therethrough;
means for applying said enabling signal to said power transistor, for causing said power transistor to quickly and positively assume its ON state;
said discharge circuit comprising said said secondary winding and a series circuit of said drive inductor and said discharge primary winding;
whereby, when said control transistor assumes its OFF state, the energy of said charged drive inductor directly produces a discharge current, and said discharge current in said discharge circuit produces an opposite-polarity disabling signal in said secondary winding;
said disabling signal being a short-interval, high-magnitude, sweep-out current;
means for applying said disabling signal to said power transistor for causing said power transistor to quickly and positively assume its OFF state.
7. The invention of claim 6, including means for controlling the timing of said control circuit means.
In the field of electronics, it is frequently necessary to "transform" one form of electricity to another form, such transformations taking place in circuits known as power sources, converters, inverters, rectifiers, etc. Some of these circuits function, for example, to transform AC to DC, DC to AC, DC of one voltage to DC of another voltage, etc. Such circuits often use switches of one type or another; but, unfortunately, switches tend to raise severe problems -- such as power loss, low efficiency, undesirable heating, transients, impaired lifetimes, and the like.
OBJECTIVES AND DRAWINGS
It is, therefore, the principal objective of the present invention to provide improved switching circuitry.
It is another objective of the present invention to provide improved switching circuitry that provides extremely fast turn-off.
It is still another objective of the present invention to provide improved switching circuitry wherein a low-power system controls a high-power system.
It is a further objective of the present invention to provide improved switching circuitry adapted to be used in a cascaded manner, in order to control the switching of even higher power systems.
It is a further objective of the present invention to provide improved switching circuitry adapted to be used in a timed manner, in order to provide higher-power and smoother-power systems.
TDA8840 I2C-bus controlled PAL/NTSC/SECAM TV processor:
The various versions of the TDA 884X/5X series are
I2C-bus controlled single chip TV processors which are
intended to be applied in PAL, NTSC, PAL/NTSC and
multi-standard television receivers. The N2 version is pin
and application compatible with the N1 version, however,
a new feature has been added which makes the N2 more
attractive. The IF PLL demodulator has been replaced by
an alignment-free IF PLL demodulator with internal VCO
(no tuned circuit required). The setting of the various
frequencies (33.4, 33.9, 38, 38.9, 45,75 and 58.75 MHz)
can be made via the I2C-bus.
Because of this difference the N2 version is compatible
with the N1, however, N1 devices cannot be used in an
optimised N2 application.
Functionally the IC series is split up is 3 categories, viz:
· Versions intended to be used in economy TV receivers
with all basic functions (envelope: S-DIP 56 and QFP
· Versions with additional features like E-W geometry
control, H-V zoom function and YUV interface which are
intended for TV receivers with 110° picture tubes
(envelope: S-DIP 56)
· Versions which have in addition a second RGB input
with saturation control and a second CVBS output
(envelope: QFP 64)
Vision IF amplifier
The IF-amplifier contains 3 ac-coupled control stages with
a total gain control range which is higher then 66 dB. The
sensitivity of the circuit is comparable with that of modern
The video signal is demodulated by means of an
alignment-free PLL carrier regenerator with an internal
VCO. This VCO is calibrated by means of a digital control
circuit which uses the X-tal frequency of the colour
decoder as a reference. The frequency setting for the
various standards (33.4, 33.9, 38, 38.9, 45.75 and 58.75
MHz) is realised via the I2C-bus. To get a good
performance for phase modulated carrier signals the
control speed of the PLL can be increased by means of the
The AFC output is generated by the digital control circuit of
the IF-PLL demodulator and can be read via the I2C-bus.
For fast search tuning systems the window of the AFC can
be increased with a factor 3. The setting is realised with the
AFW bit. The AFC data is valid only when the horizontal
PLL is in lock (SL = 1)
Depending on the type the AGC-detector operates on
top-sync level (single standard versions) or on top sync
and top white- level (multi standard versions). The
demodulation polarity is switched via the I2C-bus. The
AGC detector time-constant capacitor is connected
externally. This mainly because of the flexibility of the
application. The time-constant of the AGC system during
positive modulation is rather long to avoid visible variations
of the signal amplitude. To improve the speed of the AGC
system a circuit has been included which detects whether
the AGC detector is activated every frame period. When
during 3 field periods no action is detected the speed of the
system is increased. For signals without peak white
information the system switches automatically to a gated
black level AGC. Because a black level clamp pulse is
required for this way of operation the circuit will only switch
to black level AGC in the internal mode.
The circuits contain a video identification circuit which is
independent of the synchronisation circuit. Therefore
search tuning is possible when the display section of the
receiver is used as a monitor. However, this ident circuit
cannot be made as sensitive as the slower sync ident
circuit (SL) and we recommend to use both ident outputs
to obtain a reliable search system. The ident output is
supplied to the tuning system via the I2C-bus.
The input of the identification circuit is connected to pin 13
(S-DIP 56 devices), the “internal” CVBS input (see Fig.6).
This has the advantage that the ident circuit can also be
made operative when a scrambled signal is received
(descrambler connected between pin 6 (IF video output)
and pin 13). A second advantage is that the ident circuit
can be used when the IF amplifier is not used (e.g. with
built-in satellite tuners).
The video ident circuit can also be used to identify the
selected CBVS or Y/C signal. The switching between the
2 modes can be realised with the VIM bit.
The circuits have two CVBS inputs (internal and external
CVBS) and a Y/C input. When the Y/C input is not required
the Y input can be used as third CVBS input. The switch
configuration is given in Fig.6. The selection of the various
sources is made via the I2C-bus.
For the TDA 884X devices the video switch configuration
is identical to the switch of the TDA 8374/75 series. So the
circuit has one CVBS output (amplitude of 2 VP-P for the
TDA 884X series) and the I2C-bus control is similar to that
of the TDA 8374/75. For the TDA 885X IC’s the video
switch circuit has a second output (amplitude of 1 VP-P)
which can be set independently of the position of the first
output. The input signal for the decoder is also available on
Therefore this signal can be used to drive the Teletext
decoder. If S-VHS is selected for one of the outputs the
luminance and chrominance signals are added so that a
CVBS signal is obtained again.
The sound bandpass and trap filters have to be connected
externally. The filtered intercarrier signal is fed to a limiter
circuit and is demodulated by means of a PLL
demodulator. This PLL circuit tunes itself automatically to
the incoming carrier signal so that no adjustment is
The volume is controlled via the I2C-bus. The deemphasis
capacitor has to be connected externally. The
non-controlled audio signal can be obtained from this pin
(via a buffer stage).
The FM demodulator can be muted via the I2C-bus. This
function can be used to switch-off the sound during a
channel change so that high output peaks are prevented.
The TDA 8840/41/42/46 contain an Automatic Volume
Levelling (AVL) circuit which automatically stabilises the
audio output signal to a certain level which can be set by
the viewer by means of the volume control. This function
prevents big audio output fluctuations due to variations of
the modulation depth of the transmitter. The AVL function
can be activated via the I2C-bus.
The sync separator is preceded by a controlled amplifier
which adjusts the sync pulse amplitude to a fixed level.
These pulses are fed to the slicing stage which is operating
at 50% of the amplitude. The separated sync pulses are
fed to the first phase detector and to the coincidence
detector. This coincidence detector is used to detect
whether the line oscillator is synchronised and can also be
used for transmitter identification. This circuit can be made
less sensitive by means of the STM bit. This mode can be
used during search tuning to avoid that the tuning system
will stop at very weak input signals. The first PLL has a
very high statical steepness so that the phase of the
picture is independent of the line frequency.
The horizontal output signal is generated by means of an
oscillator which is running at twice the line frequency. Its
frequency is divided by 2 to lock the first control loop to the
incoming signal. The time-constant of the loop can be
forced by the I2C-bus (fast or slow). If required the IC can
select the time-constant depending on the noise content of
the incoming video signal.
The free-running frequency of the oscillator is determined
by a digital control circuit which is locked to the reference
signal of the colour decoder. When the IC is switched-on
the horizontal output signal is suppressed and the
oscillator is calibrated as soon as all sub-address bytes
have been sent. When the frequency of the oscillator is
correct the horizontal drive signal is switched-on. To obtain
a smooth switching-on and switching-off behaviour of the
horizontal output stage the horizontal output frequency is
doubled during switch-on and switch-off (slow start/stop).
During that time the duty cycle of the output pulse has such
a value that maximum safety is obtained for the output
To protect the horizontal output transistor the horizontal
drive is immediately switched off when a power-on-reset is
detected. The drive signal is switched-on again when the
normal switch-on procedure is followed, i.e. all
sub-address bytes must be sent and after calibration the
horizontal drive signal will be released again via the slow
start procedure. When the coincidence detector indicates
an out-of-lock situation the calibration procedure is
repeated. The circuit has a second control loop to generate
the drive pulses for the horizontal driver stage. The
horizontal output is gated with the flyback pulse so that the
horizontal output transistor cannot be switched-on during
the flyback time.
Via the I2C-bus adjustments can be made of the horizontal
and vertical geometry. The vertical sawtooth generator
drives the vertical output drive circuit which has a
differential output current. For the E-W drive a single
ended current output is available. A special feature is the
zoom function for both the horizontal and vertical
deflection and the vertical scroll function which are
available in some versions. When the horizontal scan is
reduced to display 4:3 pictures on a 16:9 picture tube an
accurate video blanking can be switched on to obtain well
defined edges on the screen.
Overvoltage conditions (X-ray protection) can be detected
via the EHT tracking pin. When an overvoltage condition is
detected the horizontal output drive signal will be
switched-off via the slow stop procedure but it is also
possible that the drive is not switched-off and that just a
protection indication is given in the I2C-bus output byte.
The choice is made via the input bit PRD. The IC’s have a
second protection input on the j2 filter capacitor pin. When
this input is activated the drive signal is switched-off
immediately and switched-on again via the slow start
procedure. For this reason this protection input can be
used as “flash protection”.
The drive pulses for the vertical sawtooth generator are
obtained from a vertical countdown circuit. This countdown
circuit has various windows depending on the incoming
signal (50 Hz or 60 Hz and standard or non standard). The
countdown circuit can be forced in various modes by
means of the I2C-bus. During the insertion of RGB signals
the maximum vertical frequency is increased to 72 Hz so
that the circuit can also synchronise on signals with a
higher vertical frequency like VGA. To obtain short
switching times of the countdown circuit during a channel
change the divider can be forced in the search window by
means of the NCIN bit. The vertical deflection can be set
in the de-interlace mode via the I2C bus.
To avoid damage of the picture tube when the vertical
deflection fails the guard output current of the TDA
8350/51 can be supplied to the beam current limiting input.
When a failure is detected the RGB-outputs are blanked
and a bit is set (NDF) in the status byte of the I2C-bus.
When no vertical deflection output stage is connected this
guard circuit will also blank the output signals. This can be
overruled by means of the EVG bit.
Chroma and luminance processing
The circuits contain a chroma bandpass and trap circuit.
The filters are realised by means of gyrator circuits and
they are automatically calibrated by comparing the tuning
frequency with the X-tal frequency of the decoder. The
luminance delay line and the delay for the peaking circuit
are also realised by means of gyrator circuits. The centre
frequency of the chroma bandpass filter is switchable via
the I2C-bus so that the performance can be optimised for
“front-end” signals and external CVBS signals. During
SECAM reception the centre frequency of the chroma trap
is reduced to get a better suppression of the SECAM
carrier frequencies. All IC’s have a black stretcher circuit
which corrects the black level for incoming video signals
which have a deviation between the black level and the
blanking level (back porch). The timeconstant for the black
stretcher is realised internally.
The resolution of the peaking control DAC has been
increased to 6 bits. All IC’s have a defeatable coring
function in the peaking circuit. Some of these IC’s have a
YUV interface (see table on page 2) so that picture
improvement IC’s like the TDA 9170 (Contrast
improvement), TDA 9177 (Sharpness improvement) and
TDA 4556/66 (CTI) can be applied. When the CTI IC’s are
applied it is possible to increase the gain of the luminance
channel by means of the GAI bit in subaddress 03 so that
the resulting RGB output signals are not affected.
Depending on the IC type the colour decoder can decode
PAL, PAL/NTSC or PAL/NTSC/SECAM signals. The
PAL/NTSC decoder contains an alignment-free X-tal
oscillator, a killer circuit and two colour difference
demodulators. The 90° phase shift for the reference signal
is made internally.
The IC’s contain an Automatic Colour Limiting (ACL)
circuit which is switchable via the I2C-bus and which
prevents that oversaturation occurs when signals with a
high chroma-to-burst ratio are received. The ACL circuit is
designed such that it only reduces the chroma signal and
not the burst signal. This has the advantage that the colour
sensitivity is not affected by this function.
The SECAM decoder contains an auto-calibrating PLL
demodulator which has two references, viz: the 4.4 MHz
sub-carrier frequency which is obtained from the X-tal
oscillator which is used to tune the PLL to the desired
free-running frequency and the bandgap reference to
obtain the correct absolute value of the output signal. The
VCO of the PLL is calibrated during each vertical blanking
period, when the IC is in search or SECAM mode.
The frequency of the active X-tal is fed to the Fsc output
(pin 33) and can be used to tune an external comb filter
(e.g. the SAA 4961).
The base-band delay line (TDA 4665 function) is
integrated in the PAL/SECAM IC’s and in the NTSC IC
TDA 8846A. In the latter IC it improves the cross colour
performance (chroma comb filter). The demodulated
colour difference signals are internally supplied to the
delay line. The colour difference matrix switches
automatically between PAL/SECAM and NTSC, however,
it is also possible to fix the matrix in the PAL standard.
The “blue stretch” circuit is intended to shift colour near
“white” with sufficient contrast values towards more blue to
obtain a brighter impression of the picture.
Which colour standard the IC’s can decode depends on
the external X-tals. The X-tal to be connected to pin 34
must have a frequency of 3.5 MHz (NTSC-M, PAL-M or
PAL-N) and pin 35 can handle X-tals with a frequency of
4.4 and 3.5 MHz. Because the X-tal frequency is used to
tune the line oscillator the value of the X-tal frequency
must be given to the IC via the I2C-bus. It is also possible
to use the IC in the so called “Tri-norma” mode for South
America. In that case one X-tal must be connected to pin
34 and the other 2 to pin 35. The switching between the 2
latter X-tals must be done externally. This has the
consequence that the search loop of the decoder must be
controlled by the m-computer. To prevent calibration
problems of the horizontal oscillator the external switching
between the 2 X-tals should be carried out when the
oscillator is forced to pin 34. For a reliable calibration of the
horizontal oscillator it is very important that the X-tal
indication bits (XA and XB) are not corrupted. For this
reason the X-tal bits can be read in the output bytes so that
the software can check the I2C-bus transmission.
RGB output circuit and black-current stabilisation
The colour-difference signals are matrixed with the
luminance signal to obtain the RGB-signals. The TDA
884X devices have one (linear) RGB input. This RGB
signal can be controlled on contrast and brightness (like
TDA 8374/75). By means of the IE1 bit the insertion
blanking can be switched on or off. Via the IN1 bit it can be
read whether the insertion pin has a high level or not.
The TDA 885X IC’s have an additional RGB input. This
RGB signal can be controlled on contrast, saturation and
brightness. The insertion blanking of this input can be
switched-off by means of the IE2 bit. Via the IN2 bit it can
be read whether the insertion pin has a high level or not.
The output signal has an amplitude of about 2 volts
black-to-white at nominal input signals and nominal
settings of the controls. To increase the flexibility of the IC
it is possible to insert OSD and/or teletext signals directly
at the RGB outputs. This insertion mode is controlled via
the insertion input (pin 26 in the S-DIP 56- and pin 38 in the
QFP-64 envelope). This blanking action at the RGB
outputs has some delay which must be compensated
To obtain an accurate biasing of the picture tube a
“Continuous Cathode Calibration” circuit has been
developed. This function is realised by means of a 2-point
black level stabilisation circuit. By inserting 2 test levels for
each gun and comparing the resulting cathode currents
with 2 different reference currents the influence of the
picture tube parameters like the spread in cut-off voltage
can be eliminated. This 2-point stabilisation is based on
the principle that the ratio between the cathode currents is
coupled to the ratio between the drive voltages according
The feedback loop makes the ratio between the cathode
currents Ik1 and Ik2 equal to the ratio between the
reference currents (which are internally fixed) by changing
the (black) level and the amplitude of the RGB output
signals via 2 converging loops. The system operates in
such a way that the black level of the drive signal is
controlled to the cut-off point of the gun so that a very good
grey scale tracking is obtained. The accuracy of the
adjustment of the black level is just dependent on the ratio
of internal currents and these can be made very accurately
in integrated circuits. An additional advantage of the
2-point measurement is that the control system makes the
absolute value of Ik1 and Ik2 identical to the internal
reference currents. Because this adjustment is obtained
by means of an adaption of the gain of the RGB control
stage this control stabilises the gain of the complete
channel (RGB output stage and cathode characteristic).
As a result variations in the gain figures during life will be
compensated by this 2-point loop.
An important property of the 2-point stabilisation is that the
off-set as well as the gain of the RGB path is adjusted by
the feedback loop. Hence the maximum drive voltage for
the cathode is fixed by the relation between the test
pulses, the reference current and the relative gain setting
of the 3 channels. This has the consequence that the drive
level of the CRT cannot be adjusted by adapting the gain
of the RGB output stage. Because different picture tubes
may require different drive levels the typical “cathode drive
level” amplitude can be adjusted by means of an I2C-bus
setting. Dependent on the chosen cathode drive level the
typical gain of the RGB output stages can be fixed taking
into account the drive capability of the RGB outputs (pins
19 to 21). More details about the design will be given in the
The measurement of the “high” and the “low” current of the
2- point stabilisation circuit is carried out in 2 consecutive
fields. The leakage current is measured in each field. The
maximum allowable leakage current is 100 mA
When the TV receiver is switched-on the RGB output
signals are blanked and the black current loop will try to set
the right picture tube bias levels. Via the AST bit a choice
can be made between automatic start-up or a start-up via
the m-processor. In the automatic mode the RGB drive
signals are switched-on as soon as the black current loop
has been stabilised. In the other mode the BCF bit is set to
0 when the loop is stabilised. The RGB drive can than be
switched-on by setting the AST bit to 0. In the latter mode
some delay can be introduced between the setting of the
BCF bit and the switching of the AST bit so that switch-on
effects can be suppressed.
It is also possible to start-up the devices with a fixed
internal delay (as with the TDA 837X and the TDA884X/5X
N1). This mode is activated with the BCO bit.
The vertical blanking is adapted to the incoming CVBS
signal (50 Hz or 60 Hz). When the flyback time of the
vertical output stage is longer than the 60 Hz blanking time
the blanking can be increased to the same value as that of
the 50 Hz blanking. This can be set by means of the LBM
For an easy (manual) adjustment of the Vg2 control voltage
the VSD bit is available. When this bit is activated the black
current loop is switched-off, a fixed black level is inserted
at the RGB outputs and the vertical scan is switched-off so
that a horizontal line is displayed on the screen. This line
can be used as indicator for the Vg2 adjustment. Because
of the different requirements for the optimum cut-off
voltage of the picture tube the RGB output level is
adjustable when the VSD bit is activated. The control
range is 2.5 ± 0.7 V and can be controlled via the
brightness control DAC.
It is possible to insert a so called “blue back” back-ground
level when no video is available. This feature can be
activated via the BB bit in the control2 subaddress.