THE SAMSUNG CB-20F12T CHASSIS KS1A was first samsung tv color chassis featuring the Ultimate One chip developed by PHILIPS and was the most integrated tv analog chassis at the time with many features and..............light weight.
The
Ultimate One Chip Television provides manufacturers with a single chip,
global TV concept with a wide range of options using advanced proven
technologies for both mixed-signal and digital processes.
By
integrating the core functions of picture and sound decoding, digital
processing and teletext and on-screen display into a single package, the
Ultimate One Chip Television reduces the number of peripheral devices
required. It
allows the manufacturer to design a single chassis for a world family of
television receivers. The same chassis can be used for different size
tubes, for single and multiple transmission standard receivers
(PAL/NTSC/SECAM), and can provide a range of facilities including stereo
sound and different teletext standards.
The analog circuitry, built in Philips' BiMOS process technology, is
primarily concerned with the colour decoding and other picture and sound
processing. The digital circuitry, built with Philips' CMOS technology,
looks after on screen display using a microprocessor core and
specialist caption decoder and teletext circuitry. Also included as part
of the digital circuitry is one time programmable (OTP) memory and up
to 2K RAM. The process technologies are both regarded as amongst the
most advanced in the industry, providing higher levels of integration
and lower levels of power consumption than competitive processes.
The Ultimate One Chip Television requires lower power at start up, for operation and for standby, than other solutions currently available, providing the opportunity for 'green' sets. The TV signal processor includes a single, automatic search, PAL/NTSC or multi-standard decoder, with a multi-standard IF circuit incorporating an alignment free PLL (Phase Loop Lock) demodulator. Other features include multi-standard FM sound, with a choice of mono or stereo, an audio switch, which removes the need for separate external band-pass filters, and an automatic volume levelling circuit. The design was carried out initially at two of Philips Semiconductors design centres, with Southampton, UK, carrying out digital design and software development and Nijmegen, Netherlands responsible for analog design. The design team in Taiwan has since become involved in tailoring the design for specific applications.
ONE CHIP TV CHASSIS DESIGN BACKGROUND OF THE INVENTION:
1. Field of Invention The present invention relates to television technology, and more particularly to providing television functionality on a single integrated circuit chip.
2. Background
Television systems have become increasingly complex as consumers continue to demand greater functionality and performance from television sets. Furthermore, the miniaturization of television systems demands that while complexity is increasing, that the size of electronic circuitry to support this complexity and performance must be reduced. At the same time, market forces continue to drive prices lower for television sets. Current electronic circuitry to support the functionality needed to receive audio and video signals that are either analog or digital and process those signals to provide a signal suitable for display on a television often consist of several integrated circuits. Furthermore, additional functionality related to value added features, such as teletext or e-commerce often requires additional integrated circuits.
What is needed is a system for providing television functionality and ancillary functionality on a single integrated chip to reduce costs and support the continued miniaturization of electronics for televisions.
The present invention addresses the conflicting consumer demands of television system miniaturization and reducing the cost of televisions.
SAMSUNG CB-20F12T CHASSIS KS1A IC Line Up
Table Line-Up
Loc. No
Specification
Description
HC101
PAP103
IF PRE-AMP
TTX, English/Croatian/Romanian/Hungarian/Polish/Czech/
SPM802ER
Bulgarian/Russian/Portugal
IC201S
W/O TTX, English/Croatian/Romanian/Hungarian/Polish/Czech/
SPM802ERN
Bulgarian/Russian/Portugal
IC301
LA7840
VERTICAL OUTPUT
IC501
TDA6107Q
RGB DRIVE AMP
IC601
TDA7266S
SOUND-AMP (3W x 1CH or 3W x 2CH or 5W x 2CH)
IC801S
KA5Q0765R
POWER IC (STR)
IC802
KA7632
CUSTOM REGULATOR (5V, 8V, 3.3V)
IC902
24C08/KS28C040
EEPROM
PC801S
TCET1108 / LTV817B
PHOTO COUPLER
IC101
U4468B
SIF - IC
Remark
Philips
Sanyo
Philips
TEMIC
Popular Samsung TVs with the KS1A Chassis:
CB-14Y52T, CS-1439C, CS-1439R, CS-1448R, CS-1448X, CS-14E3WX, CS-14C8R, CS-14C8TR, CS-14F10R, CS-14F1R, CS-14F1S, CB-14F1T, CS- 14H1X, CS-14R1S, CS-14R1X, CS-14V10, CS-14Y52X, CS-15K2Q, CS-15K5S / NWT, CS-15K5WQ, CS-15K8WQ, CS-15M16MJQ
CS-2038R, CS-2039R, CS-2039C, CS-2039X / NWT / VWT / BWT, CS-2073R, CS-2085S, CS-2085TX, CS-20C8X, CS-20E1C, CS-20E3WX, CS-20F1R, CS-20F1S, CZ-20F12ZR, CS-20F2R, CL-20F12ZSR, CS-20F32TSXBWT, CS-20F32ZSXBWT, CS-20H1X, CS-20H4R, CS-20R1R, CS-20R1X
CB-21F12TSXXEC, CI-21F32TSXXEU, CS-2139TR, CS-2139TX, CS-2139X / BWT, CS-2148X / VWT, CS-2173S / BWT, CS-2185R, CS-2185S, CS-21D8R, CS-21F10MJR, CS-21F32TSXBWT, CS-21F32ZSXBWT, CS-21F5R, CS-21H4MLR, CS-21S43NSXBWT, CS-2218, CZ-21D83N, CZ-21F12T, CZ-21F32T, SZ-21F52ZR.
Features of the KS1A chassis:
The base chassis KS1A is structurally composed of two printed circuit boards - the main and the tube. Depending on the modification of the base chassis, televisions based on it can receive and process broadcast television signals of all analog standards and systems. The chassis is based on Philips Semiconductors' new Ultimate One Chip (UOC) TDA935x chip. This chip is the third generation of well-known integrated television chips, the One Chip Television family. The UOC microcircuit uses the combined Bi CMOS and CMOS technologies, which made it possible to combine a complete video processor with a video detector and a sound demodulator, a teletext decoder that accepts all international broadcasting standards, and an 80C51-based microprocessor with an expanded set of functions.
KS1A Chassis Block Diagram Description
The block diagram of the KS1A chassis and the oscillograms at the main control points are shown in Fig. 1. The IF signal (waveform TP07) from the output of the channel selector through an RF amplifier, which compensates for the attenuation of the signal in the SAW filters, is fed to switchable SAW bandpass filters. Filter SF101S selects the IF image signal, coming further to the pin. 23, 24 IC201S video processor chips. The demodulated video signal (TP10 waveform) is removed from the pin. 38 of the video processor to an external circuit of notch filters that suppress the subcarrier of the audio signal. The video signal generated at the output of the notch filter circuit (waveform TP11) is fed to the pin. 40 video processor, as well as through the input / output node to external devices. The video signal from external devices is fed to the pin. 42 IC201S. From the video signal, the video processor generates the primary color signals, which are pin. 51, 52, 53 (waveforms TP04, TP05, TP06) through the CN501 connector are fed to the IC501 chip of the RGB amplifier of the kinescope board signals. In turn, the signal for stabilizing the dark current of the kinescope (waveform TP12), taken from the kinescope board, is fed to the pin. 50 video processor.
The SF102S filter selects the IF signal of the sound, which is then fed to IC101 - the chip of the IF converter and the FM demodulator of sound (pin 1, 2 of the chip). The use of switchable filters allows the reception of signals of various standards. Demodulated audio signal with pin. 12 IC101 chips are fed to the pin. 32 video processors (waveform TP14). With vyv. 28 of the video processor, the audio signal is removed to the input / output unit for supply to external devices. In turn, the sound signal from external devices through the input / output node is fed to the pin. 35 video processor (waveform TP15). An external VLF IC601 receives an adjustable sound signal from the pin. 44 IC201S. The amplified sound signal from the VLF outputs (TP16 waveform) through the CN601-CN603 connectors is fed to the TV speakers.
To control the electron beam of the kinescope, the video processor generates frame signals and horizontal triggers. Frame bipolar pulses of a sawtooth shape are removed from the pin. 21, 22 (waveform TP17) of the IC201S microcircuit and are fed to the terminal cascade of vertical scanning (RC) - the IC301 microcircuit. The frame coils of the deflecting system are connected to its output via the CN603 connector. A feedback signal (waveform TP13) to stabilize the size and generate a signal for protection of the kinescope comes from the output stage of the Kyrgyz Republic to the pin. 49 video processors.
Trigger pulses (waveform TP09) horizontal scan (SR) with pin. 33 video processors arrive at the driver circuit and the output stage of the SR (waveforms TP18, TP19, TP20). The output stage CP (Q401, Q402, T444S) generates the deflection currents of the lowercase coils, the supply voltage of the video amplifiers and the output stage of the KR, as well as the voltages that determine the operating mode of the tube. The pulses of the reverse stroke (waveform TP08) for synchronization of the SR are fed to the pin. 34 video processors.
The microcontroller, which is part of the IC201S video processor, controls all the functions of the TV. External nodes and microchips are controlled using the I2C control bus - pin. 2, 3 video processor chips. The signals at these pins are shown on the waveforms TP01 and TP02. Settings and values of operational adjustments are stored in non-volatile memory of IC902. To vyv. 6, 7 IC201S connected control buttons, and to the pin. 62 connected to the output of the photodetector. The external circuit of the video processor clock synchronization generator is connected to the pin. 57, 58, 59. The type of signal on the pin. 59 is shown on the waveform TP03.
The switching power supply of the chassis is implemented on the IC801S chip, which includes a powerful field-effect transistor. The signals at the main control points are presented on the waveforms TP21, TP22. The power source generates a voltage to power the output stage of the CP and a voltage of 13 V, from which a series of voltages are generated with the help of a stabilizer on the IC802 to power various chassis units.
A feature of the circuit diagram of the KS1A chassis (
) is that almost all functions of signal processing and TV control are performed by the IC201S chip based on the UOC of the TDA935x video processor.In the structural diagram of the control node of the TDA935x chip (Fig. 3), the core of the control node is the core of the microcontroller based on the well-known 80C51 processor. In addition to it, the node includes a teletext signal decoding device and non-volatile program memory. The microcontroller core includes four I / O ports, the configuration of which is determined by the program loaded into the chip (program memory). Traditionally, the microcontroller port is 8 pins, by the number of bits in a byte. Partial ports are used to reduce the number of pins on the TDA935x chip. At the same time, the device addressing is saved, like the standard microcontroller core. In this regard, some ports of the TDA935x chip lack a number of conclusions.
Port 0 is represented by pin. 10 and 11 (P0.5 and P0.6) with increased load capacity. These conclusions have three stable states, which allows the formation of three-level signals. In this software configuration pin. 10 is intended for switching external devices to the reception modes of signals with positive or negative modulation, as well as controlling the “monitor” mode, when external signals (VIDEO, AUDIO) received at the inputs of the TV are transmitted to its outputs (VIDEO, AUDIO). Vyv. 11 is defined for switching external devices (notch filters and SAW filters) when receiving PAL or NTSC signals.
The pin configuration for port 1 is determined independently for each of them - either by directly connecting the pin to the I / O interface, or by using an additional device (timer, interrupt detector, I2C interface). The microcontroller receives remote control signals from the photodetector through pin. 62 (P1.0) and interrupt detector 1, forming an interrupt flag in the presence of a remote control signal. The demagnetization loop is controlled by a signal taken from the pin. 63 (P1.1). At the moment the TV is turned on, a short-term high-level signal is formed on this output. Vyv. 64 (P1.2) in this configuration is used to control the supply voltage of the main nodes of the microcontroller. The signal removed from the pin. 1 (P1.3), is used to turn on and off (put on standby) the TV. Vyv. 2 and 3 (P1.6 and P1.7) are configured to form an external I2C control bus.
Port 2 is represented in the chip by one pin. 4 (P2.0), the output of which is used to block sound. Sound blocking is carried out by reducing the voltage of the reference level (about 5.6 V) on the pin. 6 microcircuit terminal ULF IC601. Sound blocking circuits are shown in fig. 4. Reducing the voltage on the pin. 6 IC601 is produced when the Q904 transistor is turned on (the microcontroller issues a sound blocking command), in the event of a 13 V voltage drop or loss, and in standby mode (low potential at pin 1 of the TDA935x). To . 5 (P3.0) of the microcircuit related to port 3 of the microcontroller, Q901 transistor is connected, which controls the LD901 LED. LED indication indicates the functioning of the microcontroller work program. In addition, this conclusion is used for technological purposes. To connect the buttons of the controls are used pin. 6 and 7 (P3.1 and P3.2). They are connected to the inputs of the internal ADCs, and the button circuits form dividers (Fig. 5). The recognition of control commands is carried out by measuring the voltage at the input of the ADC. Vyv. 8 (P3.3) is configured to recognize an external device connected to the TV via a SCART connector.
Demodulation of the video signal and the sound signal is carried out in the node of the demodulators and sound channel of the TDA935x chip. Functional diagram of the node is shown in Fig. 6. The IF signal from the outputs of the filter SF101 is fed to the pin. 23 and 24, the input of the inverter amplifier. The demodulated full video signal is formed on the pin. 38. The demodulated sound signal is allocated to the pin. 28. The same output is used as an input for an audio signal from an external additional demodulator of an audio signal (IC101 chip). The sound signal from external devices is sent to the pin. 35 microchips. The sound channel of the IC201S microcircuit selects an audio signal, adjusts it (volume control) and automatically adjusts the level. Adjustable sound signal through pin. 44 of the chip is fed to the input of the ULF, made on the IC601 chip.The demodulation of color signals and the formation of color difference signals is carried out in the node of the demodulator of color signals of the IC201S microcircuit (Fig. 7). In the same node, the full video signal is extracted from the brightness signal. On vyv. 40 of the microcircuit receives a video signal taken from the output of the notch filter circuit of sound signals Z201, Z202, Z203 (see. Fig. 2). Vyv. 42 is designed to supply video from external devices.
The formation of the main RGB signals (vyv. 51, 52, 53), the adjustment of the level of dark currents, insertion of information signals is carried out in the node for generating RGB signals of the TDA935x chip. Functional diagram of the node is shown in Fig. 8. The signals from the node demodulation of color signals are fed to the 1st signal selector YUV. RGB signals from external devices are fed to pin. 46, 47 and 48 microcircuits. The signal switching voltage is supplied to the pin. 45. On vyv. 49, a signal is supplied to limit the level of output signals (kinescope beam current), as well as a protection signal from the output stage of the KR IC301. A signal proportional to the kinescope beam current and used to adjust the level of dark currents is fed to the pin. fifty.
The scanning node in the functional diagram of the scanning node of the TDA935x microcircuit (Fig. 9) generates bipolar Raman signals, SR triggering pulses, SC gate pulses and a geometric distortion correction signal for picture tubes with a beam deflection angle of 110 ° (picture tubes only with a beam deflection angle are used with this chassis 90 °). The output cascades of horizontal and personnel scans do not have any circuitry features (see Fig. 2). It should be noted that the output stage of the KR (IC301) is supplied by bipolar voltage.
The power supply of the base chassis also does not have any circuit features. It is based on a converter microcircuit with a built-in high-power field effect transistor IC801S (KA5Q0765). The power source generates two secondary voltages 110 ... 125 V - to power the output stage of the SR and 13 V - to power the remaining nodes. The output voltage level is stabilized using an optocoupler feedback circuit (PC801S). The demagnetization loop is controlled by switching the RL801S relay on command from the control system.
The I / O node, depending on the modification of the TVs, can have several versions (see Fig. 2).
Adjusting and tuning the KS1A chassis
Factory settings that determine the operating conditions of the kinescope, as well as the values of the adjustment parameters are stored in the non-volatile memory of IC902. therefore, in case of its replacement or replacement of the kinescope, it is required to carry out a repeated adjustment of the parameters and save them. After replacing the IC902, the TV turns on after about 10 seconds (chip initialization time). In case of replacing the kinescope in service mode, it is necessary, having previously adjusted the color purity and mixing the kinescope rays, sequentially adjust the following parameters: white balance, preset brightness, vertical alignment, vertical size, horizontal size.
The TV is put into service mode by sending a certain sequence of commands from the remote control:
* DISPLAY> FACTORY.
* STAND-BY> DISPLAY> MENU> MUTE> POWER ON.
When the TV is switched to service mode, the message “SERVICE (FACTORY)” is displayed on the screen. In this mode, the options are ADJUST, OPTION and Reset. Selection of parameters in the ADJUST option is carried out using the “VOLUME” (Up or Down) buttons in the sequence:
SCT> SBT> BLR> BLB> RG> GG> BG> VSL> VS> VA> HS> SC> SDL> STT> SSP> PDL> NDL> PSR> NSR> AGC> VOL> LCO> TXP. the set parameter values when exiting the service mode are recorded in non-volatile memory. The service mode is exited by pressing the “FACTORY” or “Power OFF” buttons. The range of adjustable functions and their values set during initialization are given in table. 2.
table 2
| Parameter | Function | Value | Initialization Value |
|---|---|---|---|
| SCT | Preset Contrast | 0 ~ 23 | 13 |
| SBT | Preset Brightness | 0 ~ 23 | 9 |
| BLR | Black channel level setting R | 0 ~ 15 | 9 |
| BLB | Black channel level setting B | 0 ~ 15 | 7 |
| RG | Channel Gain R | 0 ~ 63 | 32 |
| GG | Channel Gain G | 0 ~ 63 | 25 |
| BG | Channel Gain B | 0 ~ 63 | 31 |
| VSL | Vertical linearity | 0 ~ 63 | 19 |
| VS | Vertical Alignment | 0 ~ 63 | 38 |
| VA | Vertical Size | 0 ~ 63 | 40 |
| HS | Horizontal Size | 0 ~ 63 | 30 |
| SC | S-correction | 0 ~ 63 | 9 |
| CDL | Dark Current Level | 0 ~ 15 | 9 |
| STT | Preset Color Tone | 0 ~ 7 | 3 |
| SSP | Pre-Clarity Adjustment | 0 ~ 7 | 0 |
| PDL | PAL delay adjustment PAL | 0 ~ 15 | 15 |
| NDL | Delay adjustment in NTSC mode | 0 ~ 15 | 10 |
| PSR | Preset saturation in PAL mode | 0 ~ 23 | 2 |
| NSR | Preset saturation in NTSC mode | 0 ~ 23 | 5 |
| AGC | AGC Adjustment | 0 ~ 63 | 23 |
| VOL | Preset volume | 0 ~ 63 | 10 |
| L CO | SECAM IF | 0 ~ 1 | 0 |
| TXP | Teletext Positioning | 0 ~ 15 | 9 |
In OPTION mode, the chassis parameters for this TV model are set. Settable options and option modes are given in table. 3.
table 3
| item | option | option item |
|---|---|---|
| 1 | LNA | ON |
| 2 | SYSTEM | CZ |
| 3 | AUDIO | MONO |
| 4 | JACK | RCA |
| 5 | ZOOM | NOR/ZOOM/16:9 |
| 6 | AUTO POWER | ON |
| 7 | SBL | OFF |
| 8 | 2nd SIF | ON |
| 9 | HOTEL MODE | OFF |
| 10 | BKS | ON |
The Reset preset mode allows you to set certain functions to predefined states (Table 4).
table 4
Position
| Function | Status | condition |
|---|---|---|
| 1 | Picture (picture options) | current |
| 2 | Auto Volume | OFF (disabled) |
| 3 | Color System (оп)(depending on option) | AUTO (automatic) |
| 4 | Sound System | D/K (depending on option |
| 5 | Blue Screen | OFF (disabled) |
| 6 | Low Noise AMP (Noise Reduction) | OFF (excluded) |
| 7 | volume(volume control) | 10 |
| 8 | CH. Skip(skipped channels) | Erased (excluded) |
| 9 | CH. Lock (prohibit viewing the channel) | OFF (disabled) |
| 10 | Timer | OFF (disabled) |
Samsung CHASSIS KS1A Typical defects:
Of the most common malfunctions of Samsung TVs made on the KS1A chassis, the following can be distinguished:
1. Do not switch channels.
After several years of operation, difficulties begin with switching channels.
When switching, only the digits of the channel indication number change.
The mechanical effect on the antenna plug helps to restore the normal operation of the TV, but not for long and the situation will happen again sooner or later. The defect progresses over time. Owners sometimes have time to brutally shake or tear off the antenna jack during this time. The reason is the quality of the tuner. The contact of one of the connections with the mass (common wire) of the tuner is broken.
The metal case walls inside, which serve as the conclusions of the mass, are possibly not adequately tinned and eventually oxidize under the solder layer.
The problem is not new to tuners from the time of Sony's Spanish build and some LG analog tuners.
2. The image is shifted.The image shifts to the left, a dark vertical bar with a reddish tint appears on the right. In some cases, a burning smell appears.
The reason is related to the quality of the capacitors in the voltage divider of the reverse pulse to form the 2nd PLL loop.
A bad contact inside the 4700 pF capacitor is finally destroyed by high-voltage pulses, and the 15k resistor after this circuit burns to coal from the overpulse voltage and current. The zener diode protects the processor at the PLL input.
Due to a short circuit inside the 680 pF capacitor, the upper arm of the divider can also burn out the resistor.
After replacing the defective circuit elements, the normal operation of the TV is restored.
This divider is applied to other chassis of Samsung TVs, creating the same problems. In some TVs with large diagonals, where a more powerful resistor to the PLL circuits is installed, together with the resistor, a portion of the board along with the connections can burn out.
3. There is no sound.
There is no sound. ULF and speakers are working. Switching the BG / DK system does not solve the problem.
It is necessary to enter the service menu (Servise Mode) in the option setting mode (OPTION TABLE) and switch the eighth option 2ND SIF (ON-OFF).
4. The TV does not turn on.
The power module does not start. The zener diode in the primary circuit is short-circuited by the power of the PWM controller.
The reason is the overestimated ESR of the 33uF 50V electrolytic capacitor. Zener breakdown is associated with the design features of PWM power supply and protection against excesses.
After replacing the capacitor and the zener diode, the performance of the TV is restored. In the case of a power supply module without an optocoupler, a 33V zener diode (1N4752) is installed.
Another malfunction in which the TV does not turn on is a breakdown of the line transistor 2SC2499. There may be several reasons. Immediately agree that 2SC2499 transistors or their analogs from a tested batch are used for replacement. The problems associated with the use of "left" transistors are not considered here.
In televisions with a 15 "flat kinescope, a 5100 pF 1600V capacitor is installed in the HOT collector circuit as a resonant capacitor, which is often found to be slightly swollen in such an accident. In any case, it must be checked and replaced if necessary. With a faulty capacitor, the transistor will be instantly overstated voltage pulse immediately upon switching on from standby mode.
If the transistor breaks through when turned on with a working capacitor, there is a high probability of short circuit in lower case deflecting coils. In Samsung TVs 15 "chassis KS1A and KS9A, SOK circuits were found repeatedly.
If the transistor heats up quickly when it is turned on, there is no high voltage, power supply B + is underestimated - FBT is faulty.
KA5Q0765RT/KA5Q12656RT/KA5Q1265RF/
KA5Q1565RF
Fairchild Power Switch(FPS)
Description The Fairchild Power Switch(FPS) product family is specially designed for an off-line SMPS with minimal external components. The Fairchild Power Switch(FPS) consist of high voltage power SenseFET and current mode PWM controller IC. PWM controller features integrated fixed oscillator, under voltage lock out, leading edge blanking, optimized gate turn-on/ turn-off driver, thermal shut down protection, over voltage protection, temperature compensated precision current sources for loop compensation and fault protection circuit. compared to discrete MOSFET and controller or RCC switching converter solution, a Fairchild Power Switch(FPS) can reduce total component count, design size, and weight and at the same time increase & efficiency, productivity, and system reliability. It has a basic platform well suited for cost-effective design in quasi resonant converter as C-TV power supply.
•
Quasi Resonant Converter Controller
•
Internal Burst Mode Controller for Stand-by Mode
•
Pulse by Pulse Current Limiting
•
Over Current Latch Protection
•
Over Voltage Protection (Vsync: Min. 11V)
•
Internal Thermal Shutdown Function
•
Under Voltage Lockout
•
Internal High Voltage Sense FET
•
Auto-Restart Mode
U4468B:
The U4468B is an integrated bipolar circuit for full multistandard sound IF signal processing in TV/VTR and multimedia applications. It supplies AM signals as well as FM/NICAM sound IF signals and thu
s allows the design of a universal sound IF module for various applications.
IF Amplifier and AGC
The symmetrical IF input signal from the external SAW filter is fed to the pins 1 and 2. In case of
FM/NICAM applications, a SAW filter with double band-pass characteristic is required for the
vision and sound carrier. In case of the L-standard, a band-pass filter with the center frequency
at the L-sound carrier is used.
The amplifier consists of three AC-coupled wide-band IF stages. Each differential amplifier stage
is gain controlled by the AGC (Automatic Gain Control) voltage, available at pin 3. The output
signal of the IF amplifier is then applied to the FPLL carrier generation, to the mixer for
FM/NICAM signals and to the AM demodulator.
The IF-AGC is derived from the average level of the AM carrier (L-standard) or from the peak
value of the FM carrier (e.g., B/G standard). It controls the three-stage wide-band amplifier to
provide a constant SIF signal to the AM demodulator or to the QSS (quasi-split sound) mixer.
Standard Switch
If the standard switch (pin 7) is in position “low” (for AM sound), the AGC is operating as an average level detector. In position “open” or “high” (for FM/NICAM sound), the AGC acts as a peak
value detector.
Internal Voltage Stabilizer
The internal band gap reference voltage (4.25V at pin 4) ensures constant performance, independent of supply voltage and temperature.
FPLL, VCO
The FPLL (frequency-phase-locked loop) circuit consists of a frequency detector and a phase
detector to generate a control voltage for the VCO tuning. In locked mode, the VCO is controlled
by the phase detector while in unlocked mode, the frequency detector is superimposed. The
VCO operates with an external resonance circuit (L and C parallel) and is controlled by inte-
grated varicaps.
A practicable VCO alignment of the external coil is the adjustment of the loop filter voltage (pin
5) to 2.3 V. At this value, the capture and hold range are centered.
AM Demodulator
The alignment-free AM demodulator is realized by a synchronous detector. The modulated IF
signal from the wide-band IF amplifier output is multiplied in phase with the limited SIF signal to
remove the AM. Then, the resulting AF signal of the demodulator output is fed to the output
amplifier and to the AGC stage.
Quasi-Split-Sound (QSS) Mixer
The QSS mixer is realized by a multiplier circuit. The IF signal (FM/NICAM) is converted to the
intercarrier frequency by means of a quadrature signal from the generated picture carrier provided by the PLL. The intercarrier signal is fed via an output amplifier to pin 12.
Mute Switch
The AM sound output (pin 6) can be muted by switching the pulling mute switch (pin 10) to “low”.
sanyo LA7840Vertical Deflection Output Circuit
Overview
The LA7840 is a vertical deflection output IC for TVs and CRT displays with excellent image quality that use a BUS control system signal processing IC. This IC can drive the direct (even including a DC component) deflection yoke with the sawtooth wave output from the BUS control system signal processing IC. When used in conjunction with Sanyo’s LA7615 series of BUS control system signal processing ICs for TVs, this IC can process all color television signal system functions through the BUS system. Because the maximum deflection current is 1.8 Ap-p, the LA7840 is suited for small and medium screen sets.
Features
.Low power dissipation due to built-in pump-up circuit
. Vertical output circuit
.Thermal protection circuit built in
. Excellent crossover characteristics
.DC coupling possible.
PHILIPS TDA6107Q
Triple video output amplifier
GENERAL DESCRIPTION
The TDA6107Q includes three video output amplifiers in one plastic DIL-bent-SIL 9-pin medium power (DBS9MPF) package (SOT111-1), using high-voltage DMOS technology, and is intended to drive the three cathodes of a colour CRT directly. To obtain maximum performance, the amplifier should be used with black-current control.FEATURES
• Typical bandwidth of 5.5 MHz for an output signal of
60 V (peak-to-peak value)
• High slew rate of 900 V/μs
• No external components required
• Very simple application
• Single supply voltage of 200 V
• Internal reference voltage of 2.5 V
• Fixed gain of 50
• Black-Current Stabilization (BCS) circuit
• Thermal protection.
THOMSON TDA72667+7W DUAL BRIDGE AMPLIFIER
DESCRIPTION
The TDA7266 is a dual bridge amplifier specially
designed for TV and Portable Radio applications.
WIDE SUPPLY VOLTAGE RANGE (3-18V)
MINIMUM EXTERNAL COMPONENTS
– NO SWR CAPACITOR
– NO BOOTSTRAP
– NO BOUCHEROT CELLS
– INTERNALLY FIXED GAIN
STAND-BY & MUTE FUNCTIONS
SHORT CIRCUIT PROTECTION
THERMAL OVERLOAD PROTECTION
APPLICATION SUGGESTION
STAND-BY AND MUTE FUNCTIONS
(A) Microprocessor Application In order to avoid annoying "Pop-Noise" during Turn-On/Off transients, it is necessary to guaran- tee the right St-by and mute signals sequence. It is quite simple to obtain this function using a mi- croprocessor (Fig. 1 and 2). At first St-by signal (from mP) goes high and the voltage across the St-by terminal (Pin 7) starts to increase exponentially. The external RC network is intended to turn-on slowly the biasing circuits of the amplifier, this to avoid "POP" and "CLICK" on the outputs. When this voltage reaches the St-by threshold level, the amplifier is switched-on and the external capacitors in series to the input terminals (C3, C5) start to charge. It’s necessary to mantain the mute signal low until the capacitors are fully charged, this to avoid that the device goes in play mode causing a loud "Pop Noise" on the speakers. A delay of 100-200ms between St-by and mute signals is suitable for a proper operation.
(B) Low Cost Application
In low cost applications where the mP is not pre- sent, the suggested circuit is shown in fig.3. The St-by and mute terminals are tied together and they are connected to the supply line via an external voltage divider. The device is switched-on/off from the supply line and the external capacitor C4 is intended to delay the St-by and mute threshold exceeding, avoiding "Popping" problems.
SAMSUNG CB-20F12T CHASSIS KS1A PHILIPS TDA9351/N2/N3/0463 SPM802OEW
TDA935X/6X/8X series
TV signal processor-Teletext decoder with embedded μ-Controller.
GENERAL DESCRIPTION
The various versions of theTDA935X/6X/8X series combine the functions of a TV signal processor together with a μ-Controller and US Closed Caption decoder. Most versions have a Teletext decoder on board. The Teletext decoder has an internal RAM memory for 1or 10 page text. The ICs are intended to be used in economy television receivers with 90° and 110° picture tubes. The ICs have supply voltages of 8 V and 3.3 V and they are mounted in S-DIP envelope with 64 pins. The features are given in the following feature list.
FEATURES
TV-signal processor
• Multi-standard vision IF circuit with alignment-free PLL
demodulator
• Internal (switchable) time-constant for the IF-AGC circuit
• A choice can be made between versions with mono
intercarrier sound FM demodulator and versions with
QSS IF amplifier.
• The mono intercarrier sound versions have a selective
FM-PLL demodulator which can be switched to the
different FM sound frequencies (4.5/5.5/6.0/6.5 MHz).
The quality of this system is such that the external
band-pass filters can be omitted.
• Source selection between ‘internal’ CVBS and external
CVBS or Y/C signals
• Integrated chrominance trap circuit
• Integrated luminance delay line with adjustable delay
time
• Asymmetrical ‘delay line type’ peaking in the luminance
channel
• Black stretching for non-standard luminance signals
• Integrated chroma band-pass filter with switchable
centre frequency
• Only one reference (12 MHz) crystal required for the
μ-Controller, Teletext- and the colour decoder
• PAL/NTSC or multi-standard colour decoder with
automatic search system
• Internal base-band delay line
• RGB control circuit with ‘Continuous Cathode
Calibration’, white point and black level off set
adjustment so that the colour temperature of the dark
and the light parts of the screen can be chosen
independently.
• Linear RGB or YUV input with fast blanking for external
RGB/YUV sources. The Text/OSD signals are internally
supplied from the μ-Controller/Teletext decoder
• Contrast reduction possibility during mixed-mode of
OSD and Text signals
• Horizontal synchronization with two control loops and
alignment-free horizontal oscillator
• Vertical count-down circuit
• Vertical driver optimized for DC-coupled vertical output
stages
• Horizontal and vertical geometry processing
• Horizontal and vertical zoom function for 16 : 9
applications
• Horizontal parallelogram and bow correction for large
screen picture tubes
• Low-power start-up of the horizontal drive circuit
μ-Controller
• 80C51 μ-controller core standard instruction set and
timing
• 1 μs machine cycle
• 32 - 128Kx8-bit late programmed ROM
• 3 - 12Kx8-bit Auxiliary RAM (shared with Display and
Acquisition)
• Interrupt controller for individual enable/disable with two
level priority
• Two 16-bit Timer/Counter registers
• WatchDog timer
• Auxiliary RAM page pointer
• 16-bit Data pointer
• IDLE and Power Down (PD) mode
• 14 bits PWM for Voltage Synthesis Tuning
• 8-bit A/D converter
• 4 pins which can be programmed as general I/O pin,
ADC input or PWM (6-bit) output
Data Capture
• Text memory for 1 or 10 pages
• In the 10 page versions inventory of transmitted Teletext
pages stored in the Transmitted Page Table (TPT) and
Subtitle Page Table (SPT)
• Data Capture for US Closed Caption
• Data Capture for 525/625 line WST, VPS (PDC system
A) and Wide Screen Signalling (WSS) bit decoding
• Automatic selection between 525 WST/625 WST
• Automatic selection between 625 WST/VPS on line 16
of VBI
• Real-time capture and decoding for WST Teletext in
Hardware, to enable optimized μ-processor throughput
• Automatic detection of FASTEXT transmission
• Real-time packet 26 engine in Hardware for processing
accented, G2 and G3 characters
• Signal quality detector for video and WST/VPS data
types
• Comprehensive teletext language coverage
• Full Field and Vertical Blanking Interval (VBI) data
capture of WST data
Display
• Teletext and Enhanced OSD modes
• Features of level 1.5 WST and US Close Caption
• Serial and Parallel Display Attributes
• Single/Double/Quadruple Width and Height for
characters
• Scrolling of display region
• Variable flash rate controlled by software
• Enhanced display features including overlining,
underlining and italics
• Soft colours using CLUT with 4096 colour palette
• Globally selectable scan lines per row (9/10/13/16) and
character matrix [12x10, 12x13, 12x16 (VxH)]
• Fringing (Shadow) selectable from N-S-E-W direction
• Fringe colour selectable
• Meshing of defined area
• Contrast reduction of defined area
• Cursor
• Special Graphics Characters with two planes, allowing
four colours per character
• 32 software redefinable On-Screen display characters
• 4 WST Character sets (G0/G2) in single device (e.g.
Latin, Cyrillic, Greek, Arabic)
• G1 Mosaic graphics, Limited G3 Line drawing
characters
• WST Character sets and Closed Caption Character set
in single device
Microcontroller
The functionality of the microcontroller used on the device is described here with reference to the industry standard 80C51 microcontroller. A full description of its functionality can be found in the "80C51 Based 8-Bit Microcontrollers - Philips Semiconductors (ref. IC20)" (Reference [1]) Memory Organisation The device has the capability of a maximum of 128K PROGRAM ROM and 12K DATA RAM internally. ROM BANK SWITCHING Devices with up to 64K Program ROM have a continuous address space. Devices with over 64K Program ROM use ROM bank switching. The 128K version is arranged in four banks of 32K. One of the 32K banks is common and is always addressable. The other three banks(Bank0,Bank1,Bank2) can be accessed by selecting the right bank via the SFR ROMBK bits 1/0.
Security Bits - Program and Verify
TDA935X/6X/8X devices have three sets of security bits, one set for each of the three One Time Programmable memories, i.e. Program ROM, Character ROM and Packet 26 ROM. The security bits are used to prevent the ROM from being overwritten once programmed, and also the contents being verified once programmed. The security bits are one-time programmable and cannot be erased. The TDA935X/6X/8X memory and security bits are structured as shown in Figure 6. The security bits are set as shown in Figure 7 for production programmed devices and are set as shown in Figure 8 for production blank devices.
RAM ORGANISATION
The Internal Data RAM is organised into two areas, Data Memory and Special Function Registers (SFR’s) as
shown in Figure 9.
Data Memory
The Data memory is 256 x 8 bits wide (byte) and occupies the address range 00h to 255h when using indirect
addressing and 00h to 127h when using Direct addressing. The SFRs occupy the address range 128 to 255 and
are accessible using Direct addressing only.
Power-on Reset
An automatic reset can be obtained when VDD is applied by connecting the RESET pin to VDDP through a 10uF
capacitor, providing the VDD rise time does not exceed 1ms, and the oscillator start-up time does not exceed
10ms.
To ensure correct initialisation, the RESET pin must be held high long enough for the oscillator to settle following
power-up, usually a few milli-seconds. Once the oscillator is stable, a further 12 clocks are required to generate
the Reset (One machine cycle of the Micro-controller). Once the above reset condition has been detected an
internal reset signal is triggered which remains active for 2048 clock cycles.
Reduced Power modes
There are three power saving modes: Stand-by, Idle and Power Down. In all three modes the 3.3v power
supplies (Vddp, Vddc & Vdda) to the device must be maintained. Power saving is achieved by clock gating on
a section by section basis.
STAND-BY M ODE
When Stand-by mode is entered both Acquisition and Display sections are disabled. The following functions
remain active:-
•
80c51 Core
•
Memory Interface
•
I2C
•
Timer/Counters
•
WatchDog Timer
•
Software A/D
•
Pulse Width Modulators
To enter Stand-by mode, the STANDBY control bit in the ROMBANK SFR (Bit-7) must be set. It can be used in conjunction with either Idle or Power-Down to switch between power saving modes. This mode enables the 80c51 core to decode either IR Remote Commands or receive IIC commands without the need to fully power the device. The Stand-by state is maintained upon exit from Idle / Power-Down. No wake-up from Stand-by is necessary as the 80c51 core remains operational. Since the output values on RGB and VDS are maintained the teletext/OSD display must be disabled before entering this mode.
IDLE MODE
During Idle mode, Acquisition, Display and the CPU sections of the device are disabled. The following functions
remain active:-
•
Memory Interface
•
I2C
•
Timer/Counters
•
•
WatchDog Timer
Pulse Width Modulators
To enter Idle mode the IDL bit in the PCON register must be set. The WatchDog timer must be disabled prior to
entering Idle to prevent the device being reset. Once in Idle mode, the XTAL oscillator continues to run, but the
internal clock to the CPU, Acquisition and Display are gated out. However, the clocks to the Memory Interface,
I2C, Timer/Counters, WatchDog Timer and Pulse Width Modulators are maintained. The CPU state is frozen
along with the status of all SFRs, internal RAM contents are maintained, as are the device output pin values.
Since the output values on RGB and VDS are maintained the teletext/OSD display must be disabled before
entering this mode.
There are three methods available to recover from Idle:-
Assertion of an enabled interrupt will cause the IDL bit to be cleared by hardware, thus terminating Idle
mode. The interrupt is serviced, and following the instruction RETI, the next instruction to be executed will
be the one after the instruction that put the device into Idle mode.
A second method of exiting Idle is via an Interrupt generated by the SAD DC Compare circuit. When
Painter is configured in this mode, detection of an analogue threshold at the input to the SAD may be
used to trigger wake-up of the device i.e. TV Front Panel Key-press. As above, the interrupt is serviced,
and following the instruction RETI, the next instruction to be executed will be the one following the
instruction that put the device into Idle. For further details of the SAD DC Compare mode refer to the
Software A/D description within the micro-controller section.
The third method of terminating Idle mode is with an external hardware reset. Since the oscillator is
running, the hardware reset need only be active for one machine cycle (12 clocks at 12MHz) to complete
the reset operation. Reset defines all SFRs and Display memory to a pre-defined state, but maintains all
other RAM values. Code execution commences with the Program Counter set to ’0000’.
POWER DOWN MODE
In Power Down mode the XTAL oscillator is stopped. The contents of all SFR, and RAM is maintained, however
the Auxiliary/Display memory is not maintained. The port pins maintain the values defined by the SFR’s. Since
the output values on RGB and VDS are maintained the teletext/OSD display must be made inoperative before
entering Power Down mode.
The power down mode is activated by setting the PD bit in the PCON register. The WatchDog timer must be
disabled before entering Power down.
There are two methods of exiting power down. Since the clock is stopped, external interrupts needs to be set to
level sensitive, by changing the level of these interrupts the device can be taken out of power down.
The second method of terminating the power down mode is with an external hardware reset. Reset defines all
SFR’s and Display memory, but maintains all other RAM values.
I/O Facility
I/O PORTS
The device has a number of micro-controller port I/O lines, each are individually addressable.
2The I C-bus ports (P1.6 and P1.7) can only be configured as Open-drain.
PORT TYPE
All individual ports bits can be programmed to function in one of four modes, the mode is defined by eight Port
Configuration SFR’s (P0CFGA/P0CFGB, P1CFGA/P1CFGB, P2CFGA/P2CFGB and P3CFGA/P3CFGB). The
modes available are Open Drain, Quasi-bidirectional, High Impedance, Push-Pull.
Open Drain
The Open drain mode can be used for bi-directional operation of a port. It requires an external pull-up resistor,
the pull-up voltage has a maximum value of 5.5V, to allow connection of the device into a 5V environment.
Quasi-bidirectional
The quasi-bidirectional mode is a combination of open drain and push pull. It requires an external pull-up resistor
to VDDp (nominally 3.3V). When a signal transition from 0 to 1 is output from the device, the pad is put into push-
pull mode for one clock cycle (166ns) after which the pad goes into open drain mode. The mode may be used
to speed up the edges of signal transitions. This is the default mode of operation of the pads after reset.
High Impedance
The high impedance mode can be used for Input only operation of the port. When using this configuration the
two output transistors are turned off.
Push-Pull
The push pull mode can be used for output only. In this mode the signal is driven to either 0V or VDDp, which
is nominally 3.3V.
Interrupt System
The device has 7 interrupt sources, each of which can be enabled or disabled. When enabled each interrupt
can be assigned one of two priority levels. There are four interrupts that are common to the 80C51, two of these
are external interrupts (EX0 and EX1) and the other two are timer interrupts (ET0 and ET1). In addition to the
conventional 80c51, two application specific interrupts are incorporated internal to the device which have
following functionality:-
ECC (Closed Caption Data Ready Interrupt) - This interrupt is generated when the device is configured in
Closed Caption Acquisition mode. The interrupt is activated at the end of the currently selected Slice Line as
defined in the CCLIN SFR.
EBUSY (Display Busy Interrupt) - An interrupt is generated when the Display enters either a Horizontal or
Vertical Blanking Period. i.e. Indicates when the micro-controller can update the Display RAM without causing
undesired effects on the screen. This interrupt can be configured in one of two modes using the MMR
Configuration Register (Address 87FF, Bit-3 [TXT/V]):-
•
•
TeXT Display Busy: An interrupt is generated on each active horizontal display line when the Horizontal
Blanking Period is entered.
Vertical Display Busy: An interrupt is generated on each vertical display field when the Vertical Blanking
Period is entered.
TCON, TMOD, TL0, TH0, TL1 and TH1.
The Timer/Counter function is selected by control bits C/T in the Timer Mode SFR(TMOD). These two Timer/
Counter have four operating modes, which are selected by bit-pairs (M1.M0) in the TMOD. Details of the modes
of operation are given in the "80C51 Based 8-Bit Microcontrollers - Philips Semiconductors (ref. IC20)"
(Reference [1]).
TL0 and TH0 are the actual timer/counter registers for timer 0. TL0 is the low byte and TH0 is the high byte. TL1
and TH1 are the actual timer/counter registers for timer 1. TL1 is the low byte and TH1 is the high byte.
WatchDog Timer
The WatchDog timer is a counter that when it overflows forces the microcontroller in to a reset. The purpose of
the WatchDog timer is to reset the microcontroller if it enters an erroneous processor state (possibly caused by
electrical noise or RFI) within a reasonable period of time. When enabled, the WatchDog circuitry will generate
a system reset if the user program fails to reload the WatchDog timer within a specified length of time known as
the WatchDog interval.
The WatchDog timer consists of an 8-bit counter with an 11 bit prescaler. The prescaler is fed with a signal
whose frequency is 1/12 fosc (1MHz). The 8 bit timer is incremented every ‘t’ seconds where:
t=12x2048x1/fosc=12x2048x1/12x106 = 2.048ms
WATCHDOG TIMER OPERATION
The WatchDog operation is activated when the WLE bit in the Power Control SFR (PCON) is set. The WatchDog
can be disabled by Software by loading the value 55H into the WatchDog Key SFR (WDTKEY). This must be
performed before entering Idle/Power Down mode to prevent exiting the mode prematurely.
Once activated the WatchDog timer SFR (WDT) must be reloaded before the timer overflows. The WLE bit must
be set to enable loading of the WDT SFR, once loaded the WLE bit is reset by hardware, this is to prevent
erroneous Software from loading the WDT SFR.
The value loaded into the WDT defines the WatchDog interval.
WatchDog interval = (256 - WDT) * t = (256 -WDT)*2.048ms
The range of intervals is from WDT = 00H which gives 524ms to WDT = FFH which gives 2.048ms
PORT Alternate Functions
The Ports 1,2 and 3 are shared with alternate functions to enable control of external devices and circuitry. The
alternate functions are enabled by setting the appropriate SFR and also writing a logic ‘1’ to the Port bit that the
function occupies.
If the Pulse Width Modulator outputs (PWM) are required on Ports 3.0 to 3.3, they require an additional bit to be
set in the Character ROM. If this facility is required, it should be requested when ordering the Language Set.
The PWMs may be enabled per pin, thus giving any combination of either PWM output, SFR output or SAD
input.
PWM PULSE WIDTH MODULATORS
The device has up to 4 6-bit Pulse Width Modulated (PWM) outputs for analogue control of e.g. volume, balance,
bass, treble, brightness, contrast, hue and saturation. The PWM outputs generate pulse patterns with a
repetition rate of 21.33us, with the high time equal to the PWM SFR value multiplied by 0.33us. The analogue
value is determined by the ratio of the high time to the repetition time, a D.C. voltage proportional to the PWM
setting is obtained by means of an external integration network (low pass filter).
PWM Control
The relevant PWM is enabled by setting the PWM enable bit PWxE in the PWMx Control register. The high time
is defined by the value PWxV<5:0>
TPWM TUNING PULSE WIDTH MODULATOR
The device has a single 14-bit PWM that can be used for Voltage Synthesis Tuning. The method of operation
is similar to the normal PWM except the repetition period is 42.66us.
TPWM Control
Two SFR are used to control the TPWM, they are TDACL and TDACH. The TPWM is enabled by setting the
TPWE bit in the TDACH SFR. The most significant bits TD<13:7> alter the high period between o and 42.33us.
The 7 least significant bits TD<6:0> extend certain pulses by a further 0.33us. e.g. if TD<6:0> = 01H then 1 in
128 periods will be extended by 0.33us, if TD<6:0>=02H the 2 in 128 periods will be extended.
The TPWM will not start to output a new value until writing a value to TDACH. Therefore, if the value is to be
changed TACL should be written before TDACH.
SAD SOFTWARE A/D
Four successive approximation Analogue to Digital Converters can be implemented in software by making use
of the on board 8-bit Digital to Analogue Converter and Analogue Comparator.
SAD Control
The control of the required analogue input is done using the channel select bits CH<1:0> in the SAD SFR, this
selects the required analogue input to be passed to one of the inputs of the comparator. The second comparator
input is generated by the DAC whose value is set by the bits SAD<7:0> in the SAD and SADB SFR’s. A
comparison between the two inputs is made when the start compare bit ST in the SAD SFR is set, this must be
at least one instruction cycle after the SAD<7:0> value has been set. The result of the comparison is given on
VHI one instruction cycle after the setting of ST
SAD Input Voltage
The external analogue voltage that is used for comparison with the internally generated DAC voltage do not
have the same voltage range. The DAC has a lower reference level of VSSA and an upper reference level of
VSSA.The resolution of the DAC voltage with a nominal values is 3.3/256 ~ 13mv. The external analogue voltage
has a lower value equivalent to VSSA and an upper value equivalent to VDDP - Vtn, were Vtn is the threshold
voltage for an NMOS transistor. The reason for this is that the input pins for the analogue signals (P3.0 to P3.3)
are 5V tolerant for normal port operations, i.e. when not used as analogue input. To protect the analogue
multiplexer and comparator circuitry from the 5V, a series transistor is used to limit the voltage. This limiting
introduces a voltage drop equivalent to Vtn (~0.6V) on the input voltage. Therefore for an input voltage in the
range VDDP to VDDp-Vtn the SAD returns the same comparison value.
When utilising Port 3.0 to Port 3.3 for SAD operation, the associated PWM outputs must be disabled.
SAD DC Comparator mode
The SAD module incorporates a DC Comparator mode which is selected using the ‘DC_COMP’ control bit in
the SADB SFR. This mode enables the microcontroller to detect a threshold crossing at the input to the selected
analog input pin (P3.0/ADC0, P3.1/ADC1, P3.2/ADC2 or P3.3/ADC3) of the software ADC. A level sensitive
interrupt is generated when the analog input voltage level at the pin falls below the analog output level of the
SAD Digital-to-Analog Converter.
This mode is intended to provide the device with a wake-up mechanism from Power-down or Idle mode when
a key-press on the front panel of the TV is detected.
The following software sequence should be used when utilizing this mode for Power-down or Idle mode:
1. Disable INT1 using the IE SFR
2. Set INT1 to level sensitive using the TCON SFR
3. Set the DAC digital input level to the desired threshold level using SAD/SADB SFRs and select the required
input pin (P3.0, P3.1, P3.2 or P3,3) using CH1 and CH0 in the SAD SFR
4. Enter DC Compare mode by setting the ‘DC_COMP’ enable bit in the SADB SFR
5. Enable INT1 using the IE SFR
6. Enter Power-down/Idle mode. Upon wake-up the SAD should be restored to its conventio
nal operating modeby disabling the ‘DC_COMP’ control bit.
I2C Serial I/O Bus
2The I C bus consists of a serial data line (SDA on Port P1.7) and a serial clock line (SCL on Port P1.6).
2These Ports may be enabled/disabled using TXT21.0 (I C Port Enable Bit).
Within the device, two separate hardware modules utilise this Bus: The Micro-controller and the TV Signal
Processor. The Micro-controller I2C peripheral may operate in four different configurations:
•
Master Transmitter
•
Master Receiver
•
Slave Transmitter
•
Slave Receiver
The TV Signal Processor may be addressed in Slave Mode only, either via the 80C51 micro-controller or from
Port P1.6 and Port P1.7 by another master in the system.
I2C-bus control of the TV signal processor
For compatibility and possible re-use of software blocks, the I2C-bus control for the TV signal processor is
organised as in the stand-alone TV signal processors. The internal communication is independent of the
programming of the Ports P1.6 and P1.7. All details on the control of the TV signal processor are given in the
description of the TV signal processor.
The byte level I2C serial port on the device is identical in operation/configuration to the I2C serial port on the
8xC558, with the exception of the clock rate selection bits CR<2:0>. The operation of the I2C subsystem is
described in detail in the 8xC558 datasheet contained in reference [1].
I2C Port Selection
The selection of the SCL0/SDA0 port is done using TXT21.I2C PORT0 bit. When the port is enabled any
information transmitted from the device goes onto the enabled port. Any information transmitted to the device
can only be acted on if the port is enabled.
LED Support
Port pins P0.5 and P0.6 have an 8mA current sinking capability to enable LEDs in series with current limiting
resistors to be driven directly, without the need for additional buffering circuitry.
Memory Interface
The memory interface controls access to the embedded DRAM, refreshing of the DRAM and page clearing. The
DRAM is shared between Data Capture, Display and Microcontroller sections. The Data Capture section uses
the DRAM to store acquired information that has been requested. The Display reads from the DRAM information
and converts it into RGB values. The Microcontroller uses the DRAM as embedded auxiliary RAM and to
generate OSD.
Memory Structure
The memory is partitioned into two distinct areas, the dedicated auxiliary RAM area, and the Display RAM area.
The Display RAM area when not being used for Data Capture or Display can be used as an extension to the
auxiliary RAM area.
AUXILIARY RAM
The auxiliary RAM is not initialised at power up. The contents of the auxiliary RAM are maintained during Idle
mode, but are lost if Power Down mode is entered.
DISPLAY RAM
The Display RAM is initialised on power up to a value 20H. The contents of the Display RAM are maintained
when entering Idle mode. If Idle mode is exited using an Interrupt then the contents are unchanged, if Idle mode
is exited using a RESET then the Display RAM is initialised to 20H.
The size of the DRAM can be any value up to 2K.
Memory Mapping
The dedicated auxiliary RAM area occupies a maximum of 2K, with an address range from 0000H to 07FFH.The
Display RAM occupies a maximum of 10K with an address range from 2000H to 47FFH for TXT mode and
8000H to 86FFH for CC mode (see Figure 15). The two modes although having different address ranges occupy
physical the same DRAM area.
When not utilising the display memory, up to 12K is available for use as dedicated auxiliary RAM.
Teletext Memory Organisation
The teletext memory is divided in to 10 blocks. Normally, when the TXT1.EXT PKT OFF bit is logic 0, each of
blocks 0 to 8 contain a teletext page arranged in the same way as the basic page memory of the page device
and block 9 contains extension packets. When the TXT1.EXT PKT OFF bit is logic 1, no extension packets are
captured and block 9 of the memory is used to store another page. The number of the memory block into which
a page is written corresponds to the page request number which resulted in the capture of the page.
Packet 0, the page header, is split into 2 parts when it is written into the text memory. The first 8 bytes of the
header contain control and addressing information. They are Hamming decoded and written into columns 0 to
7 of row 25. Row 25 also contains the magazine number of the acquired page and the PBLF flag but the last 13
bytes are unused and may be used by the software. Row 25, column 10 is reserved and should not be used by
software.
.PACKET 26 PROCESSING
One of the uses of packet 26 is to transmit characters which are not in the basic teletext character set. The family
automatically decodes packet 26 data and, if a character corresponding to that being transmitted is available in
the character set, automatically writes the appropriate character code into the correct location in the teletext
memory. This is not a full implementation of the packet 26 specification allowed for in level 2 teletext, and so is
often referred to as level 1.5.
By convention, the packets 26 for a page are transmitted before the normal packets. To prevent the default
character data over writing the packet 26 data the device incorporates a mechanism which prevents packet 26
data from being overwritten. This mechanism is disabled when the Spanish national option is detected as the
Spanish transmission system sends even parity (i.e. incorrect) characters in the basic page locations
corresponding to the characters sent via packet 26 and these will not over write the packet 26 characters
anyway. The special treatment of Spanish national option is prevented if TXT12. ROM VER R4 is logic 0 or if
the TXT8.DISABLE SPANISH is set.
Packet 26 data is processed regardless of the TXT1. EXT PKT OFF bit, but setting theTXT1.X26 OFF disables
packet 26 processing.
The TXT8. Packet 26 received bit is set by the hardware whenever a character is written into the page memory
by the packet 26 decoding hardware. The flag can be reset by writing a logic 0 into the SFR bit.
525 LINE WORLD SYSTEM TELETEXT
The 525 line format is similar to the 625 line format but the data rate is lower and there are less data bytes per
packet (32 rather than 40). There are still 40 characters per display row so extra packets are sent each of which
contains the last 8 characters for four rows. These packets can be identified by looking at the ‘tabulation bit’ (T),
which replaces one of the magazine bits in 525 line teletext. When an ordinary packet with T = 1 is received, the
decoder puts the data into the four rows starting with that corresponding to the packet number, but with the 2
LSBs set to 0. For example, a packet 9 with T = 1 (packet X/1/9) contains data for rows 8, 9, 10 and 11. The
error checking carried out on data from packets with T = 1 depends on the setting of the TXT1. 8 BIT bit and the
error checking control bits in the page request data and is the same as that applied to the data written into the
same memory location in the 625 line format.
The rolling time display (the last 8 characters in row 0) is taken from any packets X/1/1, 2 or 3 received. In
parallel magazine mode only packets in the correct magazine are used for rolling time. Packet number X/1/0 is
ignored.
The tabulation bit is also used with extension packets. The first 8 data bytes of packet X/1/24 are used to extend
the Fastext prompt row to 40 characters. These characters are written into whichever part of the memory the
packet 24 is being written into (determined by the ‘X24 Posn’ bit).
Packets X/0/27/0 contain 5 Fastext page links and the link control byte and are captured, Hamming checked
and stored by in the same way as are packets X/27/0 in 625 line text. Packets X/1/27/0 are not captured.
Because there are only 2 magazine bits in 525 line text, packets with the magazine bits all set to 0 are referred
to as being in magazine 4. Therefore, the broadcast service data packet is packet 4/30, rather than packet 8/
30. As in 625 line text, the first 20 bytes of packet 4/30 contain encoded data which is decoded in the same way
as that in packet 8/30. The last 12 bytes of the packet contains half of the parity encoded status message.
Packet 4/0/30 contains the first half of the message and packet 4/1/30 contains the second half. The last 4 bytes
of the message are not written into memory. The first 20 bytes of the each version of the packet are the same
so they are stored whenever either version of the packet is acquired.
Display
The display section is based on the requirements for a Level 1.5 WST Teletext and US Closed Caption. There
are some enhancements for use with locally generated On-Screen Displays.
The display section reads the contents of the Display memory and interprets the control/character codes. From
this information and other global settings, the display produces the required RGB signals and Video/Data (Fast
Blanking) signal.
Display Features
•
Teletext and Enhanced OSD modes
•
Level 1.5 WST features
•
US Closed Caption Features
•
Serial and Parallel Display Attributes
•
Single/Double/Quadruple Width and Height for characters
•
Scrolling of display region
•
Variable flash rate controlled by software
•
Globally selectable scan lines per row 9/10/13/16
•
Globally selectable character matrix (HxV) 12x9, 12x10, 12x13, 12x16
•
Italics
•
Soft Colours using CLUT with 4096 colour palette
•
Underline
•
Overline
•
Fringing (Shadow) selectable from N-S-E-W direction
•
Fringe colour selectable
•
Meshing of defined area
•
Contrast reduction of defined area
•
Cursor
•
Special Graphics characters with two planes, allowing four colours per character
•
32 Software re-definable On-Screen Display characters
•
4 WST Character sets(G0/G2) in single device (e.g. Latin,Cyrillic,Greek,Arabic)
•
G1 Mosaic graphics, Limited G3 Line drawing characters
•
WST Character sets and Closed Caption Character set in single device
Display Modes
The display section has two distinct modes with different features available in each. The two modes are:
•
•
TXT:-
CC:-
This is the display configured as the WST mode with additional serial and global attributes to
enable the same functionality as the SAA5497 (ETT) device.The display is configured as a
fixed 25 rows with 40 characters per row.
This is the display configured as the US Closed Caption mode with the same functionality as
the PC83C771 device. The display is configured as a maximum of 16 rows with a maximum of
48 characters per row.
In both of the above modes the Character matrix, and TV lines per row can be defined. There is an option of 9/
10/13/16 TV lines per display row, and a Character matrix (HxV) of 12x9, 12x10, 12x13, or 12x16. Not all
combinations of TV lines per row and maximum display rows give a sensible OSD display, since there is limited
number of TV scan lines available.
Special Function Register, TXT21 and memory mapped registers are used to control the mode selection.
Throughout this section, the features will be described, and there function in each mode given. If the feature is
different in either mode then this is stated.
FLASH
Flashing causes the foreground colour pixel to be displayed as the background pixels.The flash frequency is
controlled by software setting and resetting display register REG0: Status (see) at the appropriate interval.
CC:- This attribute is valid from the time set (see Table 21) until the end of the row or until otherwise modified.
TXT:- This attribute is set by the control character ‘flash’ (08h) (see Figure 31) and remains valid until the end
of the row or until reset by the control character ‘steady’ (09h).
BOXES
CC:- This attribute is valid from the time set until end of row or otherwise modified if set with Serial Mode 0. If
set with Serial Mode 1, then it is set from the next character onwards.
In text mode (within CC mode) the background colour is displayed regardless of the setting of the box attribute
bit. Boxes take affect only during mixed mode, where boxes are set in this mode the background colour is
displayed. Character locations where boxes are not set show video/screen colour (depending on the setting in
the display control register. REG0: Display Control) in stead of the background colour.
TXT:- Two types of boxes exist the Teletext box and the OSD box. The Teletext box is activated by the ‘start
box’ control character (0Bh), Two start box characters are required begin a Teletext box, with box starting
between the 2 characters. The box ends at the end of the line or after a ‘end box’ control character.
TXT mode can also use OSD boxes, they are started using size implying OSD control chracters(BCh/BDh/BEh/
BFh). The box starts after the control character (‘set after’) and ends either at the end of the row or at the next
size implying OSD character (‘set at’). To allow OSD boxes to be placed over teletext page the attributes flash,
teletext box, conceal, separate graphics, twist and hold graphics are all reset at the start of an OSD box, as they
are at the start of the row. OSD Boxes are only valid in TV mode which is defined by TXT5=03h and TXT6=03h.
SIZE
The size of the characters can be modified in both the horizontal and vertical directions.
CC:- Two sizes are available in both the horizontal and vertical directions. The sizes available are normal (x1),
double(x2) height/width and any combination of these. The attribute setting is always valid for the whole row.
Mixing of sizes is within a row is not possible.
TXT:- Three horizontal sizes are available normal (x1),double (x2),quadruple (x4). The control characters
‘normal size’ (0Ch/BCh) enables normal size, the ‘double width’ or double size (0Eh/BEh/0Fh/BFh) enables
double width characters. Any two consecutive combination of ‘double width’ or ‘double size’ (0Eh/BEh/0Fh/Bfh)
activates quadruple width characters, provided quadruple width characters are enabled by TXT4.Quad Width
Enable.
Three vertical sizes are available normal(x1),double(x2),quadruple(x4). The control characters ‘normal size’
(0Ch/BCh) enable normal size, the ‘double height’ or ‘double size’ (0Dh/BDh/0Fh/BFh) enable double height
characters. Quadruple height character are achieved by using double height characters and setting the global
attributes TXT7.Double Height(expand) and TXT7.Bottom/Top.
ITALIC
CC:- This attribute is valid from the time set until the end of the row or otherwise modified. The attribute causes
the character foreground pixels to be offset horizontally by 1 pixel per 4 scan lines (interlaced mode). The base
is the bottom left character matrix pixel. The pattern of the character is indented as shown in Figure 26.
FUNCTIONAL DESCRIPTION OF VIDEO PROCESSOR
Vision IF amplifier
The vision IF amplifier can demodulate signals with positive and negative modulation. The PLL demodulator is completely alignment-free. The VCO of the PLL circuit is internal and the frequency is fixed to the required value by using the clock frequency of the μ-Controller/Teletext decoder as a reference. The setting of the various frequencies (38, 38.9, 45.75 and 58.75 MHz) can be made via the control bits IFA-IFC in subaddress 27H. Because of the internal VCO the IF circuit has a high immunity to EMC interferences. QSS Sound circuit (QSS versions) The sound IF amplifier is similar to the vision IF amplifier and has an external AGC decoupling capacitor. The single reference QSS mixer is realised by a multiplier. In this multiplier the SIF signal is converted to the intercarrier frequency by mixing it with the regenerated picture carrier from the VCO. The mixer output signal is supplied to the output via a high-pass filter for attenuation of the residual video signals. With this system a high performance hi-fi stereo sound processing can be achieved. The AM sound demodulator is realised by a multiplier. The modulated sound IF signal is multiplied in phase with the limited SIF signal. The demodulator output signal is supplied to the output via a low-pass filter for attenuation of the carrier harmonics. The AM signal is supplied to the output (pin 44) via the volume control. It is possible to get the AM output signal (not controlled on amplitude) on the QSS intercarrier output. The selection is made by means of the AM bit in subaddress 29H. Another possibility is that pin 35 is transferred to external audio input pin and pin 32 to (non-controlled) AM output pin. This can be realised by means of the setting the control bits CMB0 and CMB1 in subaddress 22H. FM demodulator and audio amplifier (mono versions) The FM demodulator is realised as narrow-band PLL with external loop filter, which provides the necessary selectivity without using an external band-pass filter. To obtain a good selectivity a linear phase detector and a constant input signal amplitude are required. For this reason the intercarrier signal is internally supplied to the demodulator via a gain controlled amplifier and AGC circuit. The nominal frequency of the demodulator is tuned to the required frequency (4.5/5.5/6.0/6.5 MHz) by means of a calibration circuit which uses the clock frequency of the μ-Controller/Teletext decoder as a reference. The setting to the wanted frequency is realised by means of the control bits FMA and FMB in
control byte 29H. When required an external sound band-pass filter can be inserted in front of the narrow-band PLL. In that case pin 32 has to be switched to sound IF input by means of the bits SIF (subaddress 21H) and CMB0/CMB1 (subaddress 22H). When the sound IF input is selected the subcarrier output (90° versions) or AVL function (110° versions) are not available. From the output status bytes it can be read whether the PLL frequency is inside or outside the window and whether the PLL is in lock or not. With this information it is possible to make an automatic search system for the incoming sound frequency. This can be realised by means of a software loop which switches the demodulator to the various frequencies and then select the frequency on which a lock condition has been found. The deemphasis output signal amplitude is independent of the TV standard and has the same value for a frequency deviation of ±25 kHz at the 4.5 MHz standard and for a deviation of ±50 Khz for the other standards. The audio control circuit contains an audio switch and volume control. In the mono intercarrier sound versions the Automatic Volume Levelling (AVL) function can be activated. The pin to which the external capacitor has to be connected depends on the IC version. For the 90° types the capacitor is connected to the EW output pin (pin 20). For the 110° types a choice must be made between the AVL function and a sub-carrier output for comb filter applications. This choice is made via the CBM0 and CMB1bits (in subaddress 22H). When the AVL is active it automatically stabilises the audio output signal to a certain level. The signal on the deemphasis pin (28) can be supplied to the SCART connector via a buffer stage. It is also possible to use this pin as additional audio input. In that case the internal signal must, of course, be switched off. This can be realised by means of the sound mute bit (SM in subaddress 29H). When the IF circuit is switched to positive modulation the internal signal on the deemphasis pin is automatically muted.Video switches
The video switch has one input for an external CVBS or Y/C signal. The switch configuration is given in Fig.40. The selected CVBS signal can be supplied to pin 38, the IF video output. The selection between both signals is realised by means of the SVO bit in subaddress 22H. The video ident circuit can be connected to the incoming ‘internal’ video signal or to the selected signal. This ident circuit is independent of the synchronisation and can be used to switch the time-constant of the horizontal PLL depending on the presence of a video signal (via the VID bit). In this way a very stable OSD can be realised. Because of the availability of the Y/C input and the subcarrier output an external comb-filter can be applied. In that case an external video switch (or comb-filter with integrated switch) must be used. The subcarrier output is combined with a 3-level output switch (0 V, 4 V and 8 V). The output level and the availability of the subcarrier signal is controlled by the CMB1 and CMB0 bits. The output can be used to switch sound traps etc. It is also possible to use this pin for the connection of the AVL capacitor, external sound IF input or as AM output. The possibilities are illustrated in table 1. Synchronisation circuit The IC contains separator circuits for the horizontal and vertical sync pulses and a data-slic
ing circuit which extracts the digital teletext data from the analog signal. The horizontal drive signal is obtained from an internal VCO which is running at a frequency of 25 MHz. This oscillator is stabilised to this frequency by using a 12 MHz signal coming from the reference oscillator of the μ-Controller/Teletext decoder. The horizontal drive is switched on and off via the soft start/stop procedure. This function is realised by means of variation of the TON of the horizontal drive pulses. In addition the horizontal drive circuit has a ‘low-power start-up’ function. The vertical synchronisation is realised by means of a divider circuit. The vertical ramp generator needs an external resistor and capacitor. For the vertical drive a differential output current is available. The outputs must be DC coupled to the vertical output stage. In the types which are intended for 90° picture tubes the following geometry parameters can be adjusted:• Horizontal shift
• Vertical amplitude
• Vertical slope
• S-correction
• Vertical shift
The types which are intended to be used in combination
with 110° picture tubes have an East-West control circuit
in stead of the AVL function. The additional controls for
these types are:
• EW width
• EW parabola width
• EW upper and lower corner parabola correction
• EW trapezium correction
• Vertical zoom
and in some versions:
• horizontal parallelogram and bow correction.
Chroma and luminance processing
The chroma band-pass and trap circuits (including the SECAM cloche filter) are realised by means of gyrators and are tuned to the right frequency by comparing the tuning frequency with the reference frequency of the colour decoder. The luminance delay line and the delay cells for the peaking circuit are also realised with gyrators. The circuit contains a black stretcher function which corrects the black level for incoming signals which have a difference between the black level and the blanking level. Colour decoder The ICs can decode PAL, NTSC and SECAM signals. The PAL/NTSC decoder does not need external reference crystals but has an internal clock generator which is stabilised to the required frequency by using the 12 MHz clock signal from the reference oscillator of the μ-Controller/Teletext decoder. Under bad-signal conditions (e.g. VCR-playback in feature mode), it may occur that the colour killer is activated although the colour PLL is still in lock. When this killing action is not wanted it is possible to overrule the colour killer by forcing the colour decoder to the required standard and to activate the FCO-bit (Forced Colour On) in subaddress 21H. The Automatic Colour Limiting (ACL) circuit (switchable via the ACL bit in subaddress 20H) prevents that oversaturation occurs when signals with a high chroma-to-burst ratio are received. The ACL circuit is designed such that it only reduces the chroma signal and not the burst signal. This has the advantage that the colour sensitivity is not affected by this function. The SECAM decoder contains an auto-calibrating PLL demodulator which has two references, viz: the divided 12 MHz reference frequency (obtained from the μ-Controller) which is used to tune the PLL to the desired free-running frequency and the bandgap reference to obtain the correct absolute value of the output signal. The VCO of the PLL is calibrated during each vertical blanking period, when the IC is in search or SECAM mode. The base-band delay line (TDA 4665 function) is integrated. This delay line is also active during NTSC to obtain a good suppression of cross colour effects. The demodulated colour difference signals are internally supplied to the delay line. RGB output circuit and black-current stabilization In the RGB control circuit the signal is controlled on contrast, brightness and saturation. The ICs have a linear input for external RGB signals. It is possible to use this input for the insertion of YUV signals. Switching between RGB and YUV can be realised via the YUV-bit in subaddress 2BH. The signals for OSD and text are internally supplied to the control circuit. The output signal has an amplitude of about 2 Volts black-to-white at nominal input signals and nominal settings of the various controls.To obtain an accurate biasing of the picture tube the ‘Continuous Cathode Calibration’ system has been included in these ICs. A black level off set can be made with respect to the level which is generated by the black current stabilization system. In this way different colour temperatures can be obtained for the bright and the dark part of the picture. The black current stabilization system checks the output level of the 3 channels and indicates whether the black level of the highest output is in a certain window (WBC-bit) or below or above this window (HBC-bit). This indication can be read from the status byte 01 and can be used for automatic adjustment of the Vg2 voltage during the production of the TV receiver. During switch-off of the TV receiver a fixed beam current is generated by the black current control circuit. This current ensures that the picture tube capacitance is discharged. During the switch-off period the vertical deflection is placed in an overscan position so that the discharge is not visible on the screen.
SOFTWARE CONTROL
Notes
1. When the 3.3 V supply is present and the μ-Controller is active a ‘low-power start-up’ mode can be activated. When
all sub-address bytes have been sent and the POR and XPR flags have been cleared the horizontal output can be
switched-on via the STB-bit (subaddress 24H). In this condition the horizontal drive signal has the nominal TOFF and
the TON grows gradually from zero to the nominal value. As soon as the 8 V supply is present the switch-on procedure
(e.g. closing of the second loop) is continued.
2. On set AGC.
3. This parameter is not tested during production and is just given as application information for the designer of the
television receiver.
4. Loop bandwidth BL = 60 kHz (natural frequency fN = 15 kHz; damping factor d = 2; calculated with top sync level as
FPLL input signal level).
5. The IF-PLL demodulator uses an internal VCO (no external LC-circuit required) which is calibrated by means of a
digital control circuit which uses the clock frequency of the μ-Controller as a reference. The required IF frequency for
the various standards is set via the IFA-IFC bits in subaddress 27H. When the system is locked the resulting IF
frequency is very accurate with a deviation from the nominal value of less than 25 kHz.
6. This parameter is not tested during production but is guaranteed by the design and qualified by means of matrix
batches which are made in the pilot production period.
7. Measured at 10 mV (RMS) top sync input signal.
8. Via this pin (38) both the demodulated IF signal and the selected CVBS (or Y+C) signal can be supplied to the output.
The selection between both signals is realised by means of the SVO bit in subaddress 22H.
9. So called projected zero point, i.e. with switched demodulator.
10. Measured in accordance with the test line given in Fig.49. For the differential phase test the peak white setting is
reduced to 87%.
The differential gain is expressed as a percentage of the difference in peak amplitudes between the largest and
smallest value relative to the subcarrier amplitude at blanking level.
The phase difference is defined as the difference in degrees between the largest and smallest phase angle.
11. This figure is valid for the complete video signal amplitude (peak white-to-black), see Fig.50.
12. The noise inverter is only active in the ‘strong signal mode’ (no noise detected in the incoming signal)
13. Measured at an input signal of 10 mVRMS. The S/N is the ratio of black-to-white amplitude to the black level noise
voltage (RMS value). B = 5 MHz. Weighted in accordance with CCIR 567.
14. The time-constant of the IF-AGC is internal and the speed of the AGC can be set via the bits AGC1 and AGC0 in
subaddress 28H. The AGC response time is also dependent on the acquisition time of the PLL demodulator. The
values given are valid for the ‘norm’ setting (AGC1-AGC0 = 0-1) and when the PLL is in lock.
15. The AFC control voltage is generated by the digital tuning system of the PLL demodulator. This system uses the
clock frequency of the μ-Controller/Teletext decoder as a reference and is therefore very accurate. For this reason
no maximum and minimum values are given for the window sensitivity figures (parameters M.7.2 and M.7.3). The
tuning information is supplied to the tuning system via the AFA and AFB bits in output byte 02H. The AFC value is
valid only when the LOCK-bit is 1.
16. The weighted S/N ratio is measured under the following conditions:
a) The vision IF modulator must meet the following specifications:
Incidental phase modulation for black-to-white jumps less than 0.5 degrees.
QSS AF performance, measured with the television-demodulator AMF2 (audio output, weighted S/N ratio) better
than 60 dB (deviation 27 kHz) for 6 kHz sine wave black-to-white modulation.
Picture-to-sound carrier ratio: PC/SC1 = 13 dB (transmitter).
b) The measurements must be carried out with the Siemens SAW filters G3962 for vision IF and G9350 for sound
IF. Input level for sound IF 10 mVRMS with 27 kHz deviation.
c) The PC/SC ratio at the vision IF input is calculated as the addition of the TV transmitter ratio and the SAW filter
PC/SC ratio. This PC/SC ratio is necessary to achieve the S/N(W) values as indicated.
17. Calculation of the FM-PLL filter can be done approximately by use of the following equations:
1 K0 K D
f = ------ -
-------------
-
o 2π CP
1
υ = ----------------------------------
-
2R K0 K DC P
BL−3dB = f0(1.55 − υ2)
These equations are only valid under the conditions that υ ≤ 1 and CS >5CP.
Definitions:
K0 = VCO steepness in rad/V
KD = phase detector steepness μA/rad
R = loop filter resistor
CS = series capacitor
CP = parallel capacitor
f0 = natural frequency of PLL
BL−3dB = loop bandwidth for −3dB
υ = damping factor
Some examples for these values are given in table 121
18. Modulation frequency: 1 kHz, ∆f = ± 50 kHz.
19. f = 4.5/5.5 MHz; FM: 70 Hz, ± 50 kHz deviation; AM: 1.0 kHz, 30% modulation.
20. This figure is independent of the TV standard and valid for a frequency deviation of ±25 kHz at a carrier frequency
of 4.5 MHz or a deviation of ±50 kHz at a carrier frequency of 5.5/6.0/6.5 MHz.
21. The deemphasis pin can also be used as additional audio input. In that case the internal (demodulated FM signal)
must be switched off. This can be realised by means of the SM (sound mute) bit. When the vision IF amplifier is
switched to positive modulation the signal from the FM demodulator is automatically switched off. The external signal
on pin 28 must be switched off when the internal signal is selected.
22. f = 5.5 MHz; FM: 1 kHz, ± 17.5 kHz deviation. Measured with a bandwidth of 15 kHz and the audio attenuator at −6
dB.
23. f = 4.5 MHz, FM: 1 kHz, ± 100 kHz deviation and the volume control setting such that no clipping occurs in the audio
output.
24. Unweighted RMS value, Vi = 100 mVRMS, FM: 1 kHz, ± 50 kHz deviation, audio attenuator at −6 dB.
25. Audio attenuator at −20 dB; temperature range 10 to 50 °C.
26. In various versions the Automatic Volume Levelling (AVL) function can be activated. The pin to which the external
capacitor has to be connected depends on the IC version. For the 90° types the capacitor is connected to the EW
output pin (pin 20). For the 110° types a choice can be made between the AVL function and a sub-carrier output /
general purpose switch output. The selection must be made by means of the CMB0 and CMB1 bit in subaddress
22H (see also table G-1 on page G-9). More details about the sub-carrier output are given in the parameters D.10.
The Automatic Volume Levelling (AVL) circuit stabilises automatically the audio output signal to a certain level which
can be set by means of the volume control. This AVL function prevents big audio output fluctuations due to variation
of the modulation depth of the transmitter. The AVL can be switched on and off via the AVL bit in subaddress 29H.
The AVL is active over an input voltage range (measured at the deemphasis output) of 150 to 1500 mVRMS. The AVL
control curve is given in Fig.51. The control range of +6 dB to −14 dB is valid for input signals with 50% of the
maximum frequency deviation.
27. Signal with negative-going sync. Amplitude includes sync pulse amplitude.
28. This parameter is measured at nominal settings of the various controls.
29. Indicated is a signal for a colour bar with 75% saturation (chroma : burst ratio = 2.2 : 1).
30. The contrast and saturation control is active on the internal signal (YUV) and on the external RGB/YUV input. The
Text/OSD input can be controlled on brightness only. Nominal contrast is specified with the DAC in position 20 HEX.
Nominal saturation as maximum −10 dB.
31. The YUV input signal amplitudes are based on a colour bar signal with 75% saturation.
32. When the decoder is forced to a fixed subcarrier frequency (via the CM-bits) the chroma trap is always switched-on,
also when no colour signal is identified. In the automatic mode the chroma trap is switched-off when no colour signal
is identified.
33. Valid for a signal amplitude on the Y-input of 0.7 V black-to-white (100 IRE) with a rise time (10% to 90%) of 70 ns
and the video switch in the Y/C mode. During production the peaking function is not tested by measuring the
overshoots but by measuring the frequency response of the Y output.
34. For video signals with a black level which deviates from the back-porch blanking level the signal is “stretched” to the
blanking level. The amount of correction depends on the IRE value of the signal (see Fig.52). The black level is
detected by means of an internal capacitor. The black level stretcher can be switched on and off via the BKS bit in
subaddress 2DH. The values given in the specification are valid only when the luminance input signal has an
amplitude of 1 Vp-p.
35. The slicing level is independent of sync pulse amplitude. The given percentage is the distance between the slicing
level and the black level (back porch). When the amplitude of the sync pulse exceeds the value of 350 mV the sync
separator will slice the sync pulse at a level of 175 mV above top sync. The maximum sync pulse amplitude is 4 Vp-p.
36. To obtain a good performance for both weak signal and VCR playback the time constant of the first control loop is
switched depending on the input signal condition and the condition of the POC, FOA, FOB and VID bits in
subaddress 24H. The circuit contains a noise detector and the time constant is switched to ‘slow’ when too much
noise is present in the signal. In the ‘fast’ mode during the vertical retrace time the phase detector current is increased
50% so that phase errors due to head-switching of the VCR are corrected as soon as possible. Switching of the time
constant can be automatically or can be set by means of the control bits.
The circuit contains a video identification circuit which is independent of the first loop. This identification circuit can
be used to close or open the first control loop when a video signal is present or not present on the input. This enables
a stable On Screen Display (OSD) when just noise is present at the input.
To prevent that the horizontal synchronisation is disturbed by anti copy signals like Macrovision the phase detector
is gated during the vertical retrace period so that pulses during scan have no effect on the output voltage. The width
of the gate pulse is about 22 μs. During weak signal conditions (noise detector active) the gating is active during the
complete scan period and the width of the gate pulse is reduced to 5.7 μs so that the effect of noise is reduced to a
minimum.
The output current of the phase detector in the various conditions are shown in Table 122.
37. The ICs have 2 protection inputs. The protection on the second phase detector pin is intended to be used as ‘flash’
protection. When this protection is activated the horizontal drive is switched-off immediately and then switched-on
again via the slow start procedure.
The protection on the EHT input is intended for overvoltage (X-ray) protection. When this protection is activated the
horizontal drive is directly switched-off (via the slow stop procedure).
The EHT protection input can also be used to switch-off the TV receiver in a correct way when it is switched off via
the mains power switch or when the power supply is interrupted by pulling the mains plug. This can be realised by
means of a detection circuit which monitors the main supply voltage of the receiver. When this voltage suddenly
decreases the EHT protection input must be pulled HIGH and then the horizontal drive is switched off via the slow
stop procedure. Whether the EHT capacitor is discharged in the overscan or not during the switch-off period depends
on the setting of the OSO bit (subaddress 25H, D4). See also note 56.
38. The control range indicates the maximum phase difference at the top and the bottom of the screen. Compared with
the phase position at the centre of the screen the maximum phase difference at the top and the bottom of the screen
is ±0.5 μs.
39. During switch-on the horizontal drive starts-up in a soft-start mode. The horizontal drive starts with a very short TON
time of the horizontal output transistor, the ‘off time’ of the transistor is identical to the ‘off time’ in normal operation.
The starting frequency during switch-on is therefore about 2 times higher than the normal value. The ‘on time’ is
slowly increased to the nominal value. When the nominal frequency is reached the PLL is closed in such a way that
only very small phase corrections are necessary. This ensures a safe operation of the output stage. The switch-on
characteristic is given in Fig.54
During switch-off the soft-stop function is active. This is realised by decreasing the TON of the output transistor
complimentary to the start-up behaviour. The switch-off time is about 43 ms. The soft-stop procedure is synchronised
to the start of the first new vertical field after the reception of the switch-off command. Furthermore the EHT capacitor
of the picture tube is discharged with a fixed beam current which is forced by the black current loop. The discharge
time is about 38 ms. During switch-off the vertical scan is stopped so that the discharge takes place in the overscan.
The horizontal output is gated with the flyback pulse so that the horizontal output transistor cannot be switched-on
during the flyback time.
40. The vertical blanking pulse in the RGB outputs has a width of 26 or 21 lines (50 or 60 Hz system). The vertical pulse
in the sandcastle pulse has a width of 14 lines. This to prevent a phase distortion on top of the picture due to a timing
modulation of the incoming flyback pulse.
41. The timing pulses for the vertical ramp generator are obtained from the horizontal oscillator via a divider circuit.
During TV reception this divider circuit has 3 modes of operation:
a) Search mode ‘large window’.
This mode is switched on when the circuit is not synchronized or when a non-standard signal (number of lines
per frame outside the range between 311 and 314(50 Hz mode) or between 261 and 264 (60 Hz mode) is
received). In the search mode the divider can be triggered between line 244 and line 361 (approximately
45 to 64.5 Hz).
b)c)Standard mode ‘narrow window’.
This mode is switched on when more than 15 succeeding vertical sync pulses are detected in the narrow window.
When the circuit is in the standard mode and a vertical sync pulse is missing the retrace of the vertical ramp
generator is started at the end of the window. Consequently, the disturbance of the picture is very small. The
circuit will switch back to the search window when, for 6 successive vertical periods, no sync pulses are found
within the window.
Standard TV-norm (divider ratio 525 (60 Hz) or 625 (50 Hz).
When the system is switched to the narrow window it is checked whether the incoming vertical sync pulses are
in accordance with the TV-norm. When 15 standard TV-norm pulses are counted the divider system is switched
to the standard divider ratio mode. In this mode the divider is always reset at the standard value even if the vertical
sync pulse is missing.
When 3 vertical sync pulses are missed the system switches back to the narrow window and when also in this
window no sync pulses are found (condition 3 missing pulses) the system switches over to the search window.
The vertical divider needs some waiting time during channel-switching of the tuner. When a fast reaction of the
divider is required during channel-switching the system can be forced to the search window by means of the NCIN bit
in subaddress 25H.
When RGB signals are inserted the maximum vertical frequency is increased to 72 Hz. This has the consequence
that the circuit can also be synchronised by signals with a higher vertical frequency like VGA.
42. Conditions: frequency is 50 Hz; normal mode; VS = 1F.
43. The output range percentages mentioned for E-W control parameters are based on the assumption that 400 μA
variation in E-W output current is equivalent to 20% variation in picture width.
44. The ICs have a zoom adjustment possibility for the horizontal and vertical deflection. For this reason an extra DAC
has been added in the vertical amplitude control which controls the vertical scan amplitude between 0.75 and 1.38
of the nominal scan. At an amplitude of 1.06 of the nominal scan the output current is limited and the blanking of the
RGB outputs is activated. This is illustrated in Fig.53.
The nominal scan height must be adjusted at a position of 19 HEX of the vertical ‘zoom’ DAC.
45. At a chrominance input voltage of 660 mV (p-p) (colour bar with 75% saturation i.e. burst signal amplitude
300 mV (p-p)) the dynamic range of the ACC is +6 and −20 dB.
46. The ACL function can be activated by via the ACL bit in the subaddress 20H. The ACL circuit reduces the gain of the
chroma amplifier for input signals with a chroma-to-burst ratio which exceeds a value of 3.0.
47. This parameter indicates the bandwidth of the complete chrominance circuit including the chrominance bandpass
filter. The bandwidth of the low-pass filter of the demodulator is approximately 1 MHz.
48. The subcarrier output is combined with a 3-level switch output which can be used to switch external circuits like
sound traps etc. This output is controlled by the CMB1 and CMB0 bits in control byte 22H. The subcarrier signal is
available when CMB1/0 are set to 0/1. When CMB1/0 are set to 00 in versions for 90° picture tubes (no EW output)
this pin is switched to external sound IF input.
49. Because of the 2-point black current stabilization circuit both the black level and the amplitude of the RGB output
currents meet the requirement and adapts the output level and gain of the circuit when necessary. Therefore the
typical value of the black level and amplitude at the output are just given as an indication for the design of the RGB
output stage.
The 2-point black level system adapts the drive voltage for each cathode in such a way that the 2 measuring currents
have the right value. This has the consequence that a change in the gain of the output stage will be compensated
by a gain change of the RGB control circuit. Because different picture tubes may require different drive voltage
amplitudes the ratio between the output signal amplitude and the inserted measuring pulses can be adapted via the
I2C-bus. This is indicated in the parameter Adjustment range of the ratio between the amplitudes of the RGB drive
voltage and the measuring pulses’.
Because of the dependence of the output signal amplitude on the application the soft clipping limiting has been
related to the input signal amplitude.
50. For the alignment of the picture tube the vertical scan can be stopped by means of the VSD bit. In that condition a
certain black level is inserted at the RGB outputs. The value of this level can be adjusted by means of the brightness
control DAC. An automatic adjustment of the Vg2 of the picture tube can be realised by using the WBC and HBC bits
in output byte 01. For a black level feedback current between 2 and 5 μA the WBC = 1, for a higher or lower current
WBC = 0. Whether the current is too high or too low can be found from the HBC bit.
51. When the reproduction of 4 : 3 pictures on a 16 : 9 picture tube is realised by means of a reduction of the horizontal
scan amplitude the edges of the picture may slightly be disturbed. This effect can be prevented by adding an
additional blanking to the RGB signals. The blanking pulse is derived form the horizontal oscillator and is directly
related to the incoming video signal (independent of the flyback pulse). The additional blanking overlaps the normal
blanking signal with about 1 μs on both sides. This blanking is activated with the HBL bit.
52. Signal-to-noise ratio (S/N) is specified as peak-to-peak signal with respect to RMS noise (bandwidth 5 MHz).
53. When the black-current stabilization loop is switched off (AKB = 1) the WPA control range is reduced to ±1 dB.
54. This is a current input. The start-up procedure is as follows.
When the TV receiver is switched-on the RGB outputs are blanked and the black-current loop will try to adjust the
picture tube to the right bias levels. The RGB drive signals are switched-on as soon as the black current loop is
stabilised. This results in the shortest switch-on time.
When this switch-on system results in a visible disturbance of the picture it is possible to add a further switch-on delay
via a software routine. In that case the RGB outputs must be blanked by means of the RBL bit. As soon as the black
current loop is stabilised the BCF-bit is set to 0 (output byte 01). This information can then be used to switch-on the
RGB outputs with some additional delay.
55. The beam current limiting and the vertical guard function have been combined on this pin. The beam current limiting
function is active during the vertical scan period.
56. During switch-off the magnitude of the discharge current of the picture tube is controlled by the black current loop.
Dependent on the setting of the OSO bit the vertical scan can be stopped in an overscan position during that time so
that the discharge is not visible on the screen. The switch-off procedure is as follows:
a) The vertical scan and retrace are completed
b) The soft-stop procedure is started with a reduction of the TON of the output stage from nominal to zero
c) The fixed beam current is forced via the black current loop
d) If OSO = 1 the vertical deflection stays in the overscan position
e) If OSO = 0 the vertical deflection will keep running during the switch-off time
Adjustment of geometry control parameters
The deflection processor offers 5 control parameters for
picture alignment, viz:
• S-correction
• vertical amplitude
• vertical slope
• vertical shift
• horizontal shift.
The 110° types offer in addition:
• EW width
• EW parabola width
• EW upper/lower corner parabola
• EW trapezium correction.
• Vertical zoom
• Horizontal parallelogram and bow correction for some
versions in the range
It is important to notice that the ICs are designed for use with a DC-coupled vertical deflection stage. This is the reason why a vertical linearity alignment is not necessary (and therefore not available). For a particular combination of picture tube type, vertical output stage and EW output stage it is determined which are the required values for the settings of S-correction, EW parabola/width ratio and EW corner/parabola ratio. These parameters can be preset via the I2C-bus, and do not need any additional adjustment. The rest of the parameters are preset with the mid-value of their control range (i.e. 1FH), or with the values obtained by previous TV-set adjustments. The vertical shift control is meant for compensation of off sets in the external vertical output stage or in the picture tube. It can be shown that without compensation these off sets will result in a certain linearity error, especially with picture tubes that need large S-correction. The total linearity error is in first order approximation proportional to the value of the off set, and to the square of the S-correction needed. The necessity to use the vertical shift alignment depends on the expected off sets in vertical output stage and picture tube, on the required value of the S-correction, and on the demands upon vertical linearity. For adjustment of the vertical shift and vertical slope independent of each other, a special service blanking mode can be entered by setting the SBL bit HIGH. In this mode the RGB-outputs are blanked during the second half of the picture. There are 2 different methods for alignment of the picture in vertical direction. Both methods make use of the service blanking mode. The first method is recommended for picture tubes that have a marking for the middle of the screen. With the vertical shift control the last line of the visible picture is positioned exactly in the middle of the screen. After this adjustment the vertical shift should not be changed.
The top of the picture is placed by adjustment of the vertical amplitude, and the bottom by adjustment of the vertical slope. The second method is recommended for picture tubes that have no marking for the middle of the screen. For this method a video signal is required in which the middle of the picture is indicated (e.g. the white line in the circle test pattern). With the vertical slope control the beginning of the blanking is positioned exactly on the middle of the picture. Then the top and bottom of the picture are placed symmetrical with respect to the middle of the screen by adjustment of the vertical amplitude and vertical shift. After this adjustment the vertical shift has the right setting and should not be changed. If the vertical shift alignment is not required VSH should be set to its mid-value (i.e. VSH = 1F). Then the top of the picture is placed by adjustment of the vertical amplitude and the bottom by adjustment of the vertical slope. After the vertical picture alignment the picture is positioned in the horizontal direction by adjustment of the EW width and the horizontal shift. Finally (if necessary) the left- and right-hand sides of the picture are aligned in parallel by adjusting the EW trapezium control. To obtain the full range of the vertical zoom function the adjustment of the vertical geometry should be carried out at a nominal setting of the zoom DAC at position 19 HEX.4-2 Factory/Service Mode4-2-1 Procedure for the “Adjustment” Mode
1. This mode uses the standard remote control. The Service Mode is activated by entering the following remote-control sequence :
(1) DISPLAY→FACTORY.
(2) STAND-BY→ DISPLAY→ MENU→ MUTE →POWER ON.
2.THE “SERVICE (FACTORY)” MESSAGE WILL BE
DISPLAYED. THE SERVICE MODE HAS FOUR COMPO-
NENTS: ADJUST, OPTION AND RESET.
3.ACCESS THE ADJUSTMENT MODE BY PRESSING THE
“VOLUME” KEYS ( UP OR DOWN). THE ADJUST-
MENT PARAMETERS ARE LISTED IN THE ACCOMPANY-
ING TABLE, AND SELECTED BY PRESSING THE CHAN-
NEL KEYS (V ,W).
4. Selection sequences for the all system: DOWN or UP key: SCT>SBT>BLR>BLB>RG>GG>BG>VSL> VS>VA>HS>SC>SDL>STT>SSP>PDL> NDL>PSR>NSR>AGC>VOL>LCO>TXP
5.The VOLUME keys increase or decrease the adjustment values (stored in the non-volatile memory) when Adjustment Mode is cancelled. 6.Cancel the Adjustment Mode by re-pressing the “FACTORY” or “Power OFF” keys.
4-3-3 High Voltage Check CAUTION: There is no high voltage adjustment on this chassis. The B+ power supply must be set to +125 volts (Full color bar input and normal picture level).
1.Connect a digital voltmeter to the second anode of the picture tube.
2.Turn on the TV. Set the Brightness and Contrast controls to minimum (zero beam cur-
rent).
3. The high voltage should not exceed 27.5KV.
4.Adjust the Brightness and contrast controls to both extremes. Ensure that the high voltage does not exceed 27.5KV under any conditions.
4-3-4 FOCUS Adjustment
1. Input a black and white signal.
2. Adjust the tuning control for the clearest pic-
ture.
3. Adjust the FOCUS control for well defined scanning lines in the center area of the screen.
4-3-5 Cathode Voltage Adjustment
(Screen Adjustment)
1.2.3.Connect CRT socket pin GK to an oscilloscope probe. Input a gray scale pattern. (Use a pattern generator, PM5518)
Use the P mode key (on the remote control) for the STANDARD picture.
4-3-6 Purity Adjustment
1. Warm up the receiver for at least 20 minutes.
2. Plug in the CRT deflection yoke and tighten the clamp screw.
3. Plug the convergence yoke into the CRT and set in as shown in Fig. 4-2.
4. Input a black and white signal.
5. Fully demagnetize the receiver by applying an external degaussing coil.
6. Turn the CONTRAST and BRIGHTNESS controls to maximum.
7. Loosen the clamp screw holding the yoke. Slide the yoke backward or forward to pro-
vide vertical green belt. (Fig. 4-3).
8. Tighten the convergence yoke.
9. Slowly move the deflection yoke forward, and adjust for the best overall green screen.
10. Temporarily tighten the deflection yoke.
11. Produce blue and red rasters by adjusting the low-light controls. Check for good purity in each field.
12. Tighten the deflection yoke.
SAMSUNG CB-20F12T CHASSIS KS1A FBT, its bleeder resistor, and device for coupling bleeder resistor
An FBT (fly-back transformer), its bleeder resistor (installed on the top of the FBT), and a device for coupling the bleeder resistor are disclosed. The bleeder resistor 100 is accommodated within a resistor case 180, and the resistor case 180 is installed on the top of an FBT case 110. A resistor pattern 140 is printed on the substrate 130 of the bleeder resistor 100. Openings 150 are formed within the wavy portions of the resistor pattern 140, and the resistor case 180 has a plurality of isolating sheets 160 within its interior 170, so that the isolating sheets 160 can be inserted into the openings 150. When manufacturing the bleeder resistor, the glass coating, the baking, the epoxy resin dipping are eliminated, but the voltage breakdown resisting property is improved. Further, the manufacturing cost is lowered owing to the simplification of the process.
Inventors:
Choi, Dae Sung (KyungKi-do, KR) Samsung Electro-Mechanics Co., Ltd. (Kyungki-do, KR)
1. An FBT bleeder resistor coupling device comprising:
a bleeder resistor including a substrate and a resistance pattern on said substrate, said substrate including openings interposed between relatively adjacent portions of said resistance pattern;
a resistor case for receiving said bleeder resistor, said resistor case having isolating sheets positioned for insertion into said openings of said bleeder resistor substrate and for projecting above said bleeder resistor pattern; and
a lid for covering a top of said resistor case, after insertion of said bleeder resistor into said case.
2. The FBT bleeder resistor coupling device as claimed in claim 1, wherein said lid has a plurality of insertion grooves for receiving a plurality of said isolating sheets of said resistor case.
3. The FBT bleeder resistor coupling device as claimed in claim 1, in combination with an FBT case, wherein said resistor case for accommodating said bleeder resistor is formed integrally with said FBT case by an injection molding process.
4. The FBT bleeder resistor coupling device as claimed in claim 1, wherein an interior of said resistor case for accommodating said bleeder resistor is not dipped into an insulating resin.
5. The FBT bleeder resistor coupling device as claimed in claim 1, wherein said isolating sheets are formed integrally in said resistor case.
6. The FBT bleeder resistor coupling device as claimed in claim 1, wherein said substrate has opposite edges and a face extending between said opposite edges, said resistor pattern being disposed on said face, and said openings including alternating first and second openings, said first openings extending from one opposite edge part way across said face and the second opening extending from the other opposite edge part way across said face.
7. The FBT bleeder resistor coupling device as claimed in claim 6, wherein the first and second openings extend more than half way across said face.
8. The FBT bleeder resistor coupling device as claimed in claim 1, wherein said FBT case has side walls, and said isolating sheets extend inwardly from said side walls.
9. The FBT bleeder resistor coupling device as claimed in claim 8, wherein said isolating sheets include alternating first and second sheets, said first sheets extending inwardly from one side wall of said FBT case and the second sheets extending inwardly from another side wall of said FBT case opposite said one side wall.
10. The FBT bleeder resistor coupling device as claimed in claim 9, wherein the first and second sheets extend more than half the distance between said one and another side walls.
11. An FBT comprising:
high voltage and low voltage bobbins, with coils being wound thereon for generating a high voltage;
an FBT case for accommodating said high voltage and low voltage bobbins and filled with an insulating resin;
a bleeder resistor including a resistance pattern;
a bleeder resistor substrate having one or more pair of adjacently disposed first and second openings, said first opening being open at one edge of said substrate, said second opening being open at an opposite edge of said substrate, and a sum total of lengths of said first and second openings being larger than an average width of said substrate between said first and second openings;
said resistance pattern extending wavily between said first and second openings;
a resistor case for receiving said bleeder resistor, and having isolating sheets for being inserted into said openings of said bleeder resistor and projecting above said bleeder resistor; and
a lid for covering a top of said resistor case, after insertion of said bleeder resistor into said case.
12. The FBT as claimed in claim 11, wherein said lid has a plurality of insertion grooves for receiving a plurality of said isolating sheets of said resistor case.
Description:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an FBT (fly-back transformer), its bleeder resistor (installed on the top of the FBT), and a device for coupling the bleeder resistor, the FBT being for generating a high voltage in cathode ray tube for use in television, monitor or the like. Particularly, the present invention relates to an FBT, its bleeder resistor, and a device for coupling the bleeder resistor, in which two or more openings are formed adjacently to a resistance pattern on a substrate, and the first and second openings are formed alternately and mutually facingly. Further, the sum total of the lengths of the first and second openings is made larger than the average distance between the first and second openings. Thus, when manufacturing the non-coated bleeder resistor, there are not needed the glass coating, the baking, the dipping into the epoxy resin, and the curing. Notwithstanding, the voltage resistant property is reinforced, and the manufacturing process is simplified. Thus the bleeder resistor can be manufactured in an easy manner with a decreased cost.
2. Description of the Prior Art
Generally, the conventional bleeder resistor is manufactured in the following manner. That is, as shown in FIG. 1, there is prepared a ceramic substrate 10 made of Al2 O3 having a purity of about 96%. Its thickness is about 0.5-1.2 mm, and its area is 400-1500 mm2. Upon the ceramic substrate 10, there is printed PbAg, PtAg, Ag or their combination paste. Then the printed substrate is baked at a temperature of about 800° C., and thus, a printed circuit board is formed, and then lead wires are soldered. Then RuO2 is printed thereupon, and then the structure is baked at a temperature of about 850° C. Thus a resistor having a certain thickness is completed.
Meanwhile, in this resistor, electric current can flow only if the electrical resistance per unit length of the resistor is smaller than the air contact electrical resistivity. In the case where the voltage breakdown resistivity of air is 0.5 KV/mm, if a voltage of 20 KV is supplied across a resistor 12, there has to be secured a distance of 20 KV÷0.5 KV/mm=40 mm. Further, if the thermal degradation and the environmental factors are taken into account, then the safe distance must be 1.8 times as large as the above distance, that is, 40 mm×1.8=72 mm. Meanwhile, in the case where the resistor 12 is printed on the ceramic substrate 10 in a straight line, the length of the ceramic substrate has to be longer, with the result that the total bulk of the ceramic substrate becomes too large.
Therefore, the resistor 12 on the ceramic substrate 10 has to be made curved, so as to reduce the bulk of the ceramic substrate 10. In this case, however, the potential difference over per unit length of the curved pattern exceeds the straight line voltage breakdown resisting distance 0.5 KV/mm. If the environmental factors and the thermal degradation are taken into account, the potential difference per unit length far more exceeds the air voltage breakdown resisting distance, with the result that glow discharges may occur between the curved patterns. Therefore, conventionally after forming the curved resistor, the resistor patterns are insulated by a glass coating, and then, a sealed baking is carried out, thereby preventing the occurrence of the glow discharges.
Meanwhile, although the glass coating can insulate the patterns, the moisture and the thermal impact during the curing of the crystalline epoxy resin weakens the insulation, or damage the bleeder. Therefore, a dipping into the epoxy resin is carried out after the glass coating.
However, the bleeder resistor manufactured in the above method is accompanied by the following disadvantages.
First, the resistor 12 is printed upon the ceramic substrate 10, then a glass coating is carried out, then a baking is carried out, then the epoxy resin 15 is coated, and then its curing is carried out. Therefore, due to this complicated manufacturing process, the productivity is lowered, and the manufacturing cost rises.
Second, the resistor 12 is printed upon the ceramic substrate 10, then a glass coating is carried out to insulate the resistor patterns, then a baking is carried out, then the epoxy resin 15 is coated, and then its curing is carried out. Therefore, the characteristics of the printed resistor 12 are degraded, and the resistance error fluctuation rate is increased.
Third, due to the continued baking, the grains of the resistor are continuously rearranged, and therefore are easily deranged. Therefore, the surface of the resistor becomes rough and sharp, with the result that the resistance against the voltage breakdown steeply drops.
Fourth, the resistance error become higher as described above, and therefore, to cater to the consumers, incomplete products are discarded. Ultimately, the product price has to be decided higher.
Fifth, due to the use of glass and soft epoxy resin, the material cost is increased, with the ultimate result that the price is further increased.
FIGS. 2A-2E illustrate various examples of the conventional bleeder resistors. The total area of the ceramic substrate 10 on which the resistor is printed is dipped into the molten epoxy resin to coat the substrate. FIG. 2A illustrates a bleeder resistor having three lead lines 14, the lead lines being connected by soldering. Therefore, this resistor has the above described disadvantages. FIG. 2B illustrates a bleeder resistor in which the resistor patterns are formed very densely, and only one face of the ceramic substrate is coated.
FIG. 2C illustrates another conventional bleeder resistor in which only a part of one face of the ceramic substrate is coated with silicon. FIG. 2D illustrates a bleeder resistor in which a focus volume substrate is formed integrally, the resistor 12 is coated with an epoxy resin, and an opening is formed at a part of the substrate. FIG. 2E illustrates an example in which the focus volume substrate is integrally formed (it is not a bleeder resistor), and the straight distance between the openings (which are for insulating the patterns) is smaller than the width (W) of the ceramic substrate.
In the above described conventional techniques, there are the above described disadvantages due to the adoption of the glass coating and the soft epoxy coating. Besides, even if there are openings, glow discharges occur between the patterns all the same when the voltage rises to the rated level. Further, as described above, the complicated processes bring the lowering of the workability and the productivity.
SUMMARY OF THE INVENTION
The present invention is intended to overcome the above described disadvantages of the conventional techniques.
Therefore it is an object of the present invention to provide an FBT and its bleeder resistor, in which the glass coating, the baking, the dipping into the epoxy resin, and its curing are all eliminated, but the voltage breakdown resisting property is improved, and the product can be easily manufactured owing to the simplification of the manufacturing process.
It is another object of the present invention to provide a bleeder resistor and a coupling device for the bleeder resistor, in which openings are formed between wavily curved resistor patterns so as to prevent glow discharges at a high voltage, and the bleeder resistor is inserted into a casing to perfectly insulate the resistor patterns, thereby improving the electrical characteristics of the bleeder resistor.
In achieving the above objects, the FBT bleeder resistor according to the present invention includes: a substrate, and a
wavily
curved resistor pattern formed on the substrate. The FBT bleeder
resistor further includes: one or more pairs of openings formed in the
substrate, each pair of the openings consisting of a first opening and a
second opening; the first opening being open at one edge of the
substrate; the second opening being open at an opposite edge of the
substrate; the first and second openings extending laterally on the
substrate; and a sum total of lengths of the first and second openings
being larger than an average width of the substrate between the first
and second openings.In another aspect of the present invention, the FBT bleeder resistor coupling device according to the present invention includes: a bleeder resistor; a resistor case for receiving the bleeder resistor having openings alternately and mutually facingly arranged; isolating sheets formed within the resistor case, for being inserted into the openings of the bleeder resistor, and projecting above the bleeder resistor; and a lid for covering the top of the resistor case, after the insertion of the bleeder resistor into the case.
In still another aspect of the present invention, the FBT according to the present invention includes: high voltage and low voltage bobbins, with coils being wound thereon for generating a high voltage; an FBT case for accommodating the high voltage and low voltage bobbins and filled with an insulating resin; a bleeder resistor including a resistance pattern; a bleeder resistor substrate having one or more pair of adjacently disposed first and second openings, the first opening being open at one edge of the substrate, the second opening being open at the opposite edge of the substrate, and a sum total of lengths of the first and second openings being larger than an average width of the substrate between the first and second openings; the resistance pattern extending wavily between the first and second openings; a resistor case for receiving the bleeder resistor, and having a plurality of isolating sheets for being inserted into the openings of the bleeder resistor and projecting above the bleeder resistor; and a lid for covering the top of the resistor case, after the insertion of the bleeder resistor into the case.
BRIEF DESCRIPTION OF THE DRAWINGS
The above objects and other advantages of the present invention will become more apparent by describing in detail the preferred embodiment of the present invention with reference to the attached drawings in which:
FIG. 1 illustrates the manufacturing process for the general FBT bleeder resistor;
FIGS. 2A-2E illustrate various examples of the bleeder resistors for use on the conventional FBT;
FIG. 3 is an exploded perspective view showing the FBT, the bleeder resistor and the lid according to the present invention;
FIG. 4 is a perspective view showing the bleeder resistor according to the present invention;
FIG. 5 is a perspective view showing another embodiment of the bleeder resistor according to the present invention; and
FIG. 6 is a perspective view showing the lid of the resistor case.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
FIG. 3 is an exploded perspective view showing the FBT, the bleeder resistor and the lid according to the present invention. FIG. 4 is a perspective view showing the bleeder resistor according to the present invention.
Inside the FBT of the present invention, there are high voltage and low voltage bobbins with coils would thereon. An FBT case 110 accommodates the high voltage and low voltage bobbins, and contains an insulating resin for insulating the high voltage and low voltage bobbins. On the top of the FBT case 110, there are installed a resistor case 180. The resistor case 180 accommodates a bleeder resistor 100 which includes a substrate 130 and a resistor pattern 140 formed on the substrate 130. The resistor case 180 is covered with a lid 210.
As shown in FIGS. 4 and 5, the bleeder resistor 100 is formed such that a resistor pattern 140 is printed on the substrate 130, and that first and second openings 150 and 150' are formed alternately mutually facingly within the wavy portions of the resistor pattern 140.
That is, one or more pairs of the first and second openings 150 and 150' are formed adjacently to each other on the substrate 130. The first opening 150 is open at one edge of the substrate 130.
The second opening 150' is open at the opposite edge of the substrate 130, and the first and second openings 150 and 150' are formed laterally in the substrate 130. The sum total (L1 +L2) of the lengths of the first and second openings 150 and 150' is made larger than an average substrate width Ws between the first and second openings 150 and 150'.
As shown in FIG. 3, on the top of the FBT case 110, there is installed a resistor case 180, and the resistor case 180 has a plurality of isolating sheets 160 within the interior 170 of the resistor case 180, so that the isolating sheets 160 can be inserted into the openings 150 and 150'. As shown in FIG. 6, a lid 210 is coupled to the resistor case 180, and has a plurality of insertion grooves 200, so that the lid can be coupled to the resistor case 180. The insertion grooves 200 are formed by the surrounding walls 190.
The present invention constituted as above will now be described as to its action and effects.
As shown in FIGS. 3 to 6, the resistor case 180 is installed on the top of the FBT case 110, and the bleeder resistor 100 is installed within the resistor case 180. On the substrate 130 of the bleeder resistor 100, there is printed a wavy (sweep) resistor pattern 140. Within the adjacent wavy portions of the resistor pattern 140, there are formed openings 150 and 150' of a certain depth, and the openings are for insulation.
As shown in FIG. 4, within the wavy portions of the resistor pattern 140 which is printed on the substrate 130 of the bleeder resistor 100, there are formed at least one or more pairs of the first and second openings 150 and 150'. Further, the first opening 150 is open at one edge of the substrate 130, and the second opening 150' is open at the opposite edge of the substrate 130.
The first and second openings 150 and 150' are formed laterally in the substrate 130, and the sum total (L1 +L2) of the lengths of the first and second openings 150 and 150' is made larger than the average substrate width Ws between the first and second openings 150 and 150'. Thus through between the oppositely open first and second openings 150 and 150', the resistor pattern 140 can be printed in a wavy (sweep) form. Thus sufficient insulating distances are secured, and more reinforced insulation is ensured owing to the openings 150 and 150'.
FIG. 5 is a perspective view showing another embodiment of the bleeder resistor according to the present invention. In this case, the width of the substrate 130 is not constant, but the pairs of the first and second openings 150 and 150' are properly formed laterally in the substrate 130. Further, the sum total (L1 +L2) of the lengths of the first and second openings 150 and 150' is made larger than the average substrate width Ws between the first and second openings 150 and 150'.
As shown in FIG. 3, if the bleeder resistor 100 is to be conveniently installed on the top of the FBT case 110, the resistor case 180 having the isolating sheets 160 has to be installed on the top of the FBT case 110. The resistor case 180 not only secures the bleeder resistor 100 but also reinforces the insulating characteristics of the bleeder resistor 100.
That is, a plurality of the isolating sheets 160 are formed within the resistor case 180, so that the isolating sheets 160 can be precisely mated with the openings 150 and 150'. Thus not only the bleeder resistor 100 can be firmly secured, but also the wavy portions of the printed resistor pattern 140 can be perfectly insulated from each other. Here the height of the isolating sheets 160 has to be larger than the thickness t of the substrate 130.
Meanwhile, as shown in FIG. 6, the lid 210 is for covering the resistor case 180, and the lid 210 has a plurality of surrounding walls 190 to form a plurality of insertion grooves 200. After the bleeder resistor 100 is installed within the resistor case 180, the lid 210 is fitted to the resistor case 180, with the isolating sheets 160 being closely mated with the insertion grooves 200 of the lid 210.
Therefore, if a high voltage is supplied to an input terminal of the resistor pattern 140 (which is printed on the ceramic substrate 130), the voltage drops across the resistor pattern 140. Under this condition, glow discharges do not occur owing to the isolating sheets 160 which come between the wavy portions of the resistor pattern 140.
For example, if a voltage of 20 KV(dc) is supplied to the input terminal 120 of the resistor pattern 140, and if the ceramic substrate 130 has a width of 10 mm and a length of 30 mm, then the total length of the resistor pattern 140 becomes 80
mm.
If the air voltage breakdown resisting limit of 0.5 KV/mm and the
environmental factors and the thermal degradation are taken into
account, then a factor of 1.8 is needed. That is, 0.5 KV/mm÷1.8
KV/mm=0.28 KV/mm has to be maintained, and therefore, 20 KV(dc)÷0.28
KV/mm=71.4 mm is needed. Meanwhile the resistor pattern 140 has a length
of 80 mm, and therefore, a sufficient resistance is ensured. Further,
the wavy portions of the resistor pattern 140 are isolated by the
isolating sheets 160, and therefore, any glow discharge can be
prevented.Thus a perfect insulation is achieved, and therefore, the conventional glass coating becomes needless. Therefore, the bleeder resistor can be used under the air, and therefore, the conventional resin dipping which causes cracks needs not be carried out.
In order to prevent the intrusion of moisture, a final sealing is carried out after installing the bleeder resistor and after fitting the lid 210 to the resistor case 180. The final sealing is carried out by dipping the completed FBT into epoxy resin, thereby perfectly insulating the FBT from the outside. Thus the bleeder resistor is not influenced by the contraction phenomenon of the conventional epoxy resin coating. Further, the final coating such as glass coating and epoxy resin dipping has to be done even on the soldered lead lines. Further, the input terminal 120 and the output terminal 120' of the resistor pattern 140 can be made of a contact spring or an insulating rubber.
According to the present invention as described above, when manufacturing the bleeder resistor of the FBT, the glass coating, the baking, the soft epoxy resin dipping and the curing are eliminated. However, the voltage breakdown resisting property is improved. The simplification of the manufacturing process makes it possible to manufacture the bleeder resistor in an easy manner, and the manufacturing cost is significantly lowered. Further, the openings are formed within the wavy portions of the curved resistor pattern on the substrate, and therefore, any glow discharge can be prevented. The bleeder resistor with the openings formed is accommodated within the resistor case having isolating sheets, in such a manner that the isolating sheets are inserted into the openings of the bleeder resistor. Thus the wavy portions of the curved resistor pattern are perfectly insulated from each other, thereby further improving the electrical characteristics of the bleeder resistor.
References:
5859407 Connecting board for connection between base plate and mounting board 1999-01-12 Saiki et al. 338/307
4829282 High efficiency high heat output electrical heater assembly 1989-05-09 Waugh et al. 338/279
4521761 Small outline potentiometer 1985-06-04 Welch 338/184
4369424 Slide rheostat 1983-01-18 Miyamoto 338/184
3860789 HEATING ELEMENT ASSEMBLY 1975-01-14 Maake 219/532
3588642 N/A 1971-06-28 Fabricius 338/184
3543213 GRID-TYPE RESISTOR 1970-11-24 Weyenberg 338/290
3069598 Modular electronic circuit device 1962-12-18 Darly et al. 338/184
2367170 Heater 1945-01-09 Fahrenwald 219/540
Foreign References:
KR95-011766 May, 1995
KR950011766A 1995-05-16
SAMSUNG CB-20F12T CHASSIS KS1A Flyback transformer and device for holding bleeder resistor in such transformer
A flyback transformer, used as a high voltage generator for supplying a high voltage to the CRT of a TV receiver or a monitor, and a bleeder resistor holding device for such transformers is disclosed. The bleeder resistor holding device is designed to hold a bleeder resistor at a position between a high voltage bobbin and a low voltage bobbin of the transformer, thus accomplishing compactness and smallness of a focus pack of the transformer. In the flyback transformer of this invention, the bleeder resistor is positioned at a gap defined between the pin terminals of the high voltage bobbin and the low voltage bobbin such that the bleeder resistor is spaced apart from the pin terminal of the low voltage bobbin by a predetermined distance.
Inventors:Cho, Dong Hwan (Hwasung-gun, KR) Samsung Electro-Mechanics Co., Ltd.
1. A flyback transformer, comprising: a high voltage bobbin and a low voltage bobbin, each provided with a pin terminal, in addition to an internal coil used for generating a high voltage; a flyback transformer casing receiving both the high voltage bobbin and the low voltage bobbin, and electrically insulated by an insulating resin; and a bleeder resistor consisting of a ceramic board printed with a resistor pattern on a top surface thereof, said bleeder resistor being positioned at a gap defined between the pin terminals of the high voltage bobbin and the low voltage bobbin such that the bleeder resistor is spaced apart from the pin terminal of said low voltage bobbin by a predetermined distance.
2. The flyback transformer according to claim 1, further comprising a board holding device projecting from at least one of the high voltage bobbin and the low voltage bobbin, said board holding device receiving an end of said ceramic board of the bleeder resistor for holding the bleeder resistor in the flyback transformer.
3. The flyback transformer according to claim 1, wherein the distance between the bleeder resistor and the pin terminal of the low voltage bobbin is not less than 1.0 mm.
4. The flyback transformer according to claim 2, wherein said board holding device consists of first and second holders, respectively projecting from the low voltage bobbin and the high voltage bobbin and receiving opposite ends of said ceramic board of the bleeder resistor to hold the bleeder resistor in the flyback transformer.
5. The flyback transformer according to claim 4, wherein the second holder projecting from the high voltage bobbin is spaced apart from the pin terminal of the low voltage bobbin by at least 2.5 mm, and the distance between the bleeder resistor and the pin terminal of the low voltage bobbin is not less than 2.5 mm.
6. The flyback transformer according to claim 4, wherein the first holder projecting from the low voltage bobbin is spaced apart from the pin terminal of the low voltage bobbin by at least 1.5 mm, and the distance between the bleeder resistor and the pin terminal of the low voltage bobbin is not less than 1.5 mm.
7. A device for holding a bleeder resistor in a flyback transformer including a bleeder resistor consisting of a ceramic board printed with a resistor pattern on a top surface thereof, and a high voltage bobbin and a low voltage bobbin each provided with an internal coil for generating a high voltage, comprising: resistor holding means projecting from at least one of the high voltage bobbin and the low voltage bobbin at a position between pin terminals of the high voltage bobbin and the low voltage bobbin, said holding means receiving an end of said ceramic board of the bleeder resistor for holding the bleeder resistor in the flyback transformer, whereby the bleeder resistor held by the holding means is positioned at a gap defined between the pin terminals of the high voltage bobbin and the low voltage bobbin such that the bleeder resistor is spaced apart from the pin terminal of said low voltage bobbin by a predetermined distance.
8. The device according to claim 7, wherein the resistor holding means consists of first and second holders, respectively projecting from the low voltage bobbin and the high voltage bobbin and receiving opposite ends of said ceramic board of the bleeder resistor to hold the bleeder resistor in the flyback transformer.
9. The device according to claim 8, wherein the second holder projecting from the high voltage bobbin is spaced apart from the pin terminal of the low voltage bobbin by at least 2.5 mm, and the distance between the bleeder resistor and the pin terminal of the low voltage bobbin is not less than 2.5 mm.
10. The device according to claim 8, wherein the first holder projecting from the low voltage bobbin is spaced apart from the pin terminal of the low voltage bobbin by at least 1.5 mm, and the distance between the bleeder resistor and the pin terminal of the low voltage bobbin is not less than 1.5 mm.
Description:
BACKGROUND OF THE INVENTION
[0001] 1. Field of the Invention
[0002] The present invention relates, in general, to flyback transformers used as high voltage generators for supplying high voltages to the CRTs of TV receivers or monitors and, more particularly, to a flyback transformer having a structurally improved bleeder resistor holding structure, which is designed to hold a bleeder resistor at a position between a high voltage bobbin and a low voltage bobbin of the flyback transformer, thus accomplishing compactness and smallness of a focus pack of the transformer.
[0003] 2. Description of the Prior Art
[0004] FIG. 1 is a perspective view, showing the construction of a conventional bleeder resistor for flyback transformers (hereinbelow, referred to simply as “FBT”). As shown in the drawing, the bleeder resistor consists of a focus pack board 110 and a bleeder resistor board 170. The FBT focus pack board 110 is printed on its top surface with two screen focus resistor patterns 120 and 130. Two screen focus voltage output terminals 140 are provided at the centers of the two resistor patterns 120 and 130, respectively. In addition, two screen focus voltage input terminals 150 are provided at the outer ends of the two resistor patterns 120 and 130, respectively. The bleeder resistor board 170, printed on its top surface with a resistor pattern 160, is positioned at a side of the focus pack board 110, and is connected to the focus pack board 110, thus forming a bleeder resistor.
[0005] FIG. 2 shows a conventional structure for holding such a bleeder resistor in an FBT. As shown in the drawing, the bleeder resistor 207 is held in an EBT by both a resistor holder 205 formed in a focus pack 201 and a resistor insert groove 204 formed in an FBT casing 203. A high voltage bobbin 208 is inserted in the FBT casing 203. However, this bleeder resistor holding structure is problematic in that it is necessary to secure additional space in the focus pack 203 for holding the bleeder resistor 207. Therefore, this holding structure fails to accomplish the recent trend of compactness or smallness of the focus pack 201.
[0006] In an effort to overcome the above-mentioned problem, an FBT of FIG. 3 having a structurally improved bleeder resistor holding structure has been used. The FBT of FIG. 3 is disclosed in Korean Utility Model Publication No. 87-4463. In this FBT, a resistor holder 303 is integrally formed at a coil separating wall 302 of a high voltage bobbin 301, with a resistor holding channel 305 formed in the resistor holder 303. A bleeder resistor 304 is inserted in the holding channel 305 of the holder 303 such that the resistor 304 is positioned at a side of the high voltage bobbin 301 while extending outside the bobbin 301 in an axial direction of the bobbin 301. This bleeder resistor holding structure is advantageous in that it accomplishes smallness of the FBT. However, this structure is problematic in that the bleeder resistor 304 may interfere with the high voltage output coils of the high voltage bobbin 301. The above holding structure also undesirably increases the length of the bleeder resistor 304 by the length of the bobbin 301, thus enlarging the size of the bleeder resistor 304 and increasing the production cost of the bleeder resistors.
[0007] In an effort to accomplish compactness and smallness of FBTs, in addition to providing a stable structure for holding the bleeder resistors in the FBTs, an FBT having another bleeder resistor holding structure of FIG. 4 was proposed. This FBT is disclosed in Japanese Patent laid-open Publication No. Heisei. 7-75339. In this FBT, a bleeder resistor 401 consisting of a plurality of small boards is held on a high voltage bobbin 403 while being connected to the high voltage output coils 405 and the diodes 407 of the bobbin 403. Since this FBT uses the bleeder resistor 401 consisting of the small-sized boards, it is possible to accomplish compactness and smallness of the FBTs, in addition to providing a stable structure for holding the bleeder resistor 401 in the FBT without causing interference of the bleeder resistor 401 with the high voltage output coils 405 of the high voltage bobbin 403. However, since the small boards of the
bleeder resistor 401 are held at positions between the high voltage output coils 405 and the diodes 407 of the bobbin 403, it is difficult to produce the EBT. Another problem of this FBT resides in that it is necessary to provide a complex circuit for connecting the small boards of the bleeder resistor 401 to the high voltage output coils 405 and the diodes 407 of the bobbin 403.
[0008] Therefore, it has been required to provide a bleeder resistor holding structure for FBTs, which accomplishes compactness and smallness of the FBTS, stably holds bleeder resistors in the FBTs while allowing the bleeder resistors to have a desired size, and easily receives a bleeder resistor when installing the bleeder resistor in an FBT.
SUMMARY OF THE INVENTION
[0009] Accordingly, the present invention has been made keeping in mind the above problems occurring in the prior art, and an object of the present invention is to provide a bleeder resistor holding device for FBTs, which holds a bleeder resistor at a gap defined between a high voltage bobbin and a low voltage bobbin of an FBT, thus accomplishing compactness and smallness of the FBT and reducing the production cost of the FBT, and which easily receives the bleeder resistor when installing the bleeder resistor in the FBT.
[0010] Another object of the present invention is to provide a bleeder resistor holding device for FBTs, which stably holds a bleeder resistor in an FBT at a gap defined between the high voltage bobbin and the low voltage bobbin.
[0011] A further object of the present invention is to provide an FBT having such a bleeder resistor holding device.
[0012] In order to accomplish the above objects, the present invention provides a flyback transformer, comprising: a high voltage bobbin and a low voltage bobbin, each provided with a pin terminal, in addition to an internal coil used for generating a high voltage; an FBT casing receiving both the high voltage bobbin and the low voltage bobbin, and electrically insulated by an insulating resin; and a bleeder resistor consisting of a ceramic board printed with a resistor pattern on the top surface thereof, the bleeder resistor being positioned at a gap defined between the pin terminals of the high voltage bobbin and the low voltage bobbin such that the bleeder resistor is spaced apart from the pin terminal of the low voltage bobbin by a predetermined distance.
[0013] The present invention also provides a device for holding a bleeder resistor in such a flyback transformer, comprising: a resistor holding means projecting from at least one of the high voltage bobbin and the low voltage bobbin at a position between pin terminals of the high voltage bobbin and the low voltage bobbin, the holding means receiving an end of the ceramic board of the bleeder resistor for holding the bleeder resistor in the flyback transformer, whereby the bleeder resistor held by the holding means is positioned at a gap defined between the pin terminals of the high voltage bobbin and the low voltage bobbin such that the bleeder resistor is spaced apart from the pin terminal of the low voltage bobbin by a predetermined distance.
BRIEF DESCRIPTION OF THE DRAWINGS
[0014] The above and other objects, features and other advantages of the present invention will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:
[0015] FIG. 1 is a perspective view showing the construction of a conventional bleeder resistor for flyback transformers, including a focus pack board and a bleeder resistor board;
[0016] FIG. 2 is an exploded perspective view of an FBT having a bleeder resistor holding structure according to an embodiment of the prior art;
[0017] FIG. 3 is a view of an FBT having a bleeder resistor holding structure according to another embodiment of the prior art;
[0018] FIG. 4 is a perspective view of an FBT having a bleeder resistor holding structure according to a further embodiment of the prior art;
[0019] FIG. 5 is an exploded perspective view, showing the construction of a high voltage bobbin and a low voltage bobbin of an FBT having a bleeder resistor holding device in accordance with the preferred embodiment of the present invention;
[0020] FIG. 6 is a perspective view of the low voltage bobbin of the FBT having a first holder of the bleeder resistor holding device according to this invention;
[0021] FIGS. 7a and 7b are views showing the construction of the low voltage bobbin of this invention in more detail, in which:
[0022] FIG. 7a is a front view of the low voltage bobbin; and
[0023] FIG. 7b is a side view of the low voltage bobbin;
[0024] FIGS. 8a and 8b are views of the high voltage bobbin of the FBT having a second holder of the bleeder resistor holding device according to this invention, in which:
[0025] FIG. 8a is a view of the high voltage bobbin; and
[0026] FIG. 8b is a view of the second holder of the bleeder resistor holding device; and
[0027] FIGS. 9a and 9b are views of the assembled FBT, with a bleeder resistor installed in the FBT by the bleeder resistor holding device of this invention, in which:
[0028] FIG. 9a is a front view of the FBT; and
[0029] FIG. 9b is a plan view of the FBT.
DETAILED DESCRIPTION OF THE INVENTION
[0030] Reference now should be made to the drawings, in which the same reference numerals are used throughout the different drawings to designate the same or similar components.
[0031] FIG. 5 is an exploded perspective view showing a high voltage bobbin and a low voltage bobbin of an FBT in accordance with the preferred embodiment of this invention. FIG. 6 is a perspective view of the low voltage bobbin having a first holder of a bleeder resistor holding device according to this invention. FIGS. 7a and 7b are views showing the construction of the low voltage bobbin of this invention in more detail. FIGS. 8a and 8b are views of the high voltage bobbin having a second holder of the bleeder resistor holding device according to this invention. FIGS. 9a and 9b are views of the FBT, with a bleeder resistor installed in the FBT by the bleeder resistor holding device of this invention.
[0032] As shown in the drawings, a high voltage bobbin 3 of the FBT is a hollow cylindrical body having a pin terminal 5 at one end thereof, and axially receives a low voltage bobbin 1 therein. The low voltage bobbin 1 has a first holder 2, while the high voltage bobbin 3 has a second holder 4. The first and second holders 2 and 4 project from the low voltage bobbin 1 and the high voltage bobbin 3, respectively, and form a bleeder resistor holding device of this invention. The two holders 2 and 4 of the bleeder resistor holding device receive the opposite ends of a bleeder resistor, thus holding the bleeder resistor in the FBT.
[0033] The construction of the first and second holders 2 and 4 are shown in detail in FIGS. 6 to 8b. As shown in FIGS. 6, 7a and 7b, the first holder 2 is formed on the low voltage bobbin 1 at a position under a pin terminal 5. This first holder 2 has a box shape, which is formed by top and bottom walls and has a channel defined between the top and bottom walls so as to receive one end of the bleeder resistor board. The bottom wall of the first holder 2 is slit along its central axis from the outer edge to a predetermined length, thus more easily receiving the bleeder resistor board in the channel of the first holder 2. The above first holder 2 is preferably formed at a position around the pin terminal 5, at which a voltage output coil is connected to the low voltage bobbin 1.
[0034] FIGS. 8a and 8b show the second holder 4 formed at the high voltage bobbin 3. As shown in FIG. 8a, the second holder 4 is formed on the high voltage bobbin 3 at a position above an output cable terminal 7. This holder 4 has a channel for receiving the other end of the bleeder resistor board. In a detailed description, the second holder 4 is formed on the high voltage bobbin 3 at a position corresponding to the first holder 2 of the low voltage bobbin 1, and so the opposite ends of the bleeder resistor board are inserted into the channels of the first and second holders 2 and 4, respectively.
[0035] In the present invention, the first and second holders 2 and 4 may be integrally formed on the bobbins 1 and 3. Alternatively, the holders 2 and 4 may be produced separate from the bobbins 1 and 3 prior to being attached to the bobbins 1 and 3 using an appropriate means, such as bonding agent or setscrews. The first and second holders 2 and 4 must be designed such that the bleeder resistor is spaced apart from the pin terminal 5 of the low voltage bobbin 1 by a predetermined distance when the board of the bleeder resistor is inserted at its opposite ends into the two holders 2 and 4. That is, when the low voltage bobbin 1 is assembled with the high voltage bobbin 3 into a single body, the bleeder resistor must be positioned at a gap defined between the pin terminals of the two bobbins 1 and 3. In such a case, the bleeder resistor must be spaced apart from the pin terminals of the bobbins 1 and 3 by the distance so as to prevent any interference of the bleeder resistor with the pin terminals.
[0036] The distance between the bleeder resistor and the pin terminal 5 of the low voltage bobbin 1 is preferably set to at least 1.0 mm. In order to accomplish the above object, the first holder 2 is preferably spaced apart from the pin terminal 5 of the low voltage bobbin 1 by at least 1.0 mm. In an operation of the FBT, a high voltage of about 10˜12 kV is typically generated at the bleeder resistor set in the first holder 2, while a low voltage of only several hundred volts is generated at the pin terminal 5 of the low voltage bobbin 1. Therefore, there is a potential difference of about 10˜12 kV between the first holder 2 and the pin terminal 5 of the low voltage bobbin 1, and so it is necessary to space the first holder 2 from the pin terminal 5 by at least 1.0 mm, and electrically insulate the pin terminal 5 from the first holder 2 by filling an epoxy resin in the gap between the first holder 2 and the pin terminal 5. Since the insulating power of the epoxy resin is at least 12 kV per 1 mm thickness, the epoxy resin filled in the gap between the first holder 2 and the pin terminal 5 effectively insulates the pin terminal 5 from the first holder 2. In the present invention, it is more preferable to space the first holder 2 from the pin terminal 5 of the low voltage bobbin 1 by at least 1.5 mm. In such a case, the distance between the bleeder resistor and the pin terminal 5 of the low voltage bobbin 1 is set to at least 1.5 mm.
[0037] The second holder 4 of the high voltage bobbin 3 is preferably spaced apart from the pin terminal 5 of the low voltage bobbin 1 by at least 2.5 mm. In an operation of the FBT, a high voltage of about 25˜30 kV is typically generated at the bleeder resistor set in the second holder 4, and so there is a potential difference of about 25˜30 kV between the second holder 4 and the pin terminal 5. It is thus necessary to space the pin terminal 5 from the second holder 4 by at least 2.5 mm, and insulate the pin terminal 5 from the second holder 4 by filling an epoxy resin in the gap between the second holder 4 and the pin terminal 5. In such a case, the epoxy resin, the insulation power of which is at least 12 kV per 1 mm thickness, effectively insulates the pin terminal 5 from the second holder 4.
[0038] FIGS. 9a and 9b are views of the assembled FBT, with a bleeder resistor installed in the FBT by the bleeder resistor holding device of this invention. The operational effect of the bleeder resistor holding device of this invention will be described herein below with reference to FIGS. 9a and 9b.
[0039] As shown in FIGS. 9a and 9b, in order to fabricate an FBT, the low voltage bobbin 1 having the first holder 2 is assembled with the high voltage bobbin 3 having the second holder 4 into a single body. In such a case, the board of a bleeder resistor 9 is inserted at its opposite ends into the holders 2 and 4 such that the bleeder resistor 9 is spaced apart from the pin terminal 5 of the low voltage bobbin 1 by a predetermined distance due to the specified positions of the two holders 2 and 4. The assembled bobbins 1 and 3 with the bleeder resistor 9 are inserted into an FBT casing 11 prior to injecting an epoxy resin into desired portions for accomplishing insulating effect. Thereafter, a ferrite core and a high voltage cable are set in the FBT casing 11, thus completely fabricating a desired FBT.
[0040] As shown in FIG. 9b, the bleeder resistor 9 is positioned at the gap defined between the pin terminals of the low voltage bobbin 1 and the high voltage bobbin 3. In such a case, the bleeder resistor 9 is installed in the FBT casing 11 without being exposed to the outside of the FBT casing 11. Due to the holders 2 and 4 formed on the bobbins 1 and 3, it is not necessary to secure additional space for installing the bleeder resistor in the FBT, and so compactness and smallness of the FBT is accomplished. Particularly, the bleeder resistor holding device of this invention desirably simplifies the structure of an FBT focus pack, and so it is possible to more effectively accomplish compact
ness and smallness of FBTs.[0041] As described above, the present invention provides a bleeder resistor holding device for FBTs, which is designed to hold a bleeder resistor at a gap defined between a high voltage bobbin and a low voltage bobbin of an FBT. The bleeder resistor holding device of this invention thus accomplishes compactness and smallness of the FBTs and reduces the production cost of the FBTs, in addition to easily receiving the bleeder resistor when installing the bleeder resistor in an FBT.
[0042] Although a preferred embodiment of the present invention has been described for illustrative purposes, those skilled in the art will appreciate that various modifications, additions and substitutions are possible, without departing from the scope and spirit of the invention as disclosed in the accompanying claims.
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CROSS REFERENCE TO RELATED APPLICATIONS
This application is a continuation of U.S. patent application Ser. No. 12/367,425, filed Feb. 6, 2009, which is a continuation of U.S. patent application Ser. No. 10/791,686 filed Mar. 3, 2004, entitled “Television Functionality on a Chip” (the '686 application), both of which are incorporated by referenced herein in its entirety
The '686 application claims the benefit of priority to the following U.S. Provisional Patent Applications: Application No. 60/451,265, filed Mar. 4, 2003; Application No. 60/467,574, filed May 5, 2003; Application No. 60/495,129, filed Aug. 15, 2003; Application No. 60/495,127, filed Aug. 15, 2003; and Application No. 60/495,121, filed Aug. 15, 2003; all of which are incorporated herein by reference in their entireties.
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